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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 | 15 | * Author: MontaVista Software, Inc. |
ec7eabdd | 16 | * ppopov@mvista.com or source@mvista.com |
1da177e4 LT |
17 | * |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
30 | * with this program; if not, write to the Free Software Foundation, Inc., | |
31 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
32 | * | |
33 | * ######################################################################## | |
34 | * | |
6aa20a22 | 35 | * |
1da177e4 | 36 | */ |
bc36b428 | 37 | #include <linux/capability.h> |
d791c2bd | 38 | #include <linux/dma-mapping.h> |
1da177e4 LT |
39 | #include <linux/module.h> |
40 | #include <linux/kernel.h> | |
1da177e4 LT |
41 | #include <linux/string.h> |
42 | #include <linux/timer.h> | |
43 | #include <linux/errno.h> | |
44 | #include <linux/in.h> | |
45 | #include <linux/ioport.h> | |
46 | #include <linux/bitops.h> | |
47 | #include <linux/slab.h> | |
48 | #include <linux/interrupt.h> | |
1da177e4 LT |
49 | #include <linux/init.h> |
50 | #include <linux/netdevice.h> | |
51 | #include <linux/etherdevice.h> | |
52 | #include <linux/ethtool.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/skbuff.h> | |
55 | #include <linux/delay.h> | |
8cd35da0 | 56 | #include <linux/crc32.h> |
0638dec0 | 57 | #include <linux/phy.h> |
bd2302c2 | 58 | #include <linux/platform_device.h> |
25b31cb1 YY |
59 | |
60 | #include <asm/cpu.h> | |
1da177e4 LT |
61 | #include <asm/mipsregs.h> |
62 | #include <asm/irq.h> | |
63 | #include <asm/io.h> | |
64 | #include <asm/processor.h> | |
65 | ||
25b31cb1 | 66 | #include <au1000.h> |
bd2302c2 | 67 | #include <au1xxx_eth.h> |
25b31cb1 YY |
68 | #include <prom.h> |
69 | ||
1da177e4 LT |
70 | #include "au1000_eth.h" |
71 | ||
72 | #ifdef AU1000_ETH_DEBUG | |
73 | static int au1000_debug = 5; | |
74 | #else | |
75 | static int au1000_debug = 3; | |
76 | #endif | |
77 | ||
7cd2e6e3 FF |
78 | #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK) | |
81 | ||
89be0501 | 82 | #define DRV_NAME "au1000_eth" |
8020eb82 | 83 | #define DRV_VERSION "1.7" |
1da177e4 LT |
84 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
85 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
86 | ||
87 | MODULE_AUTHOR(DRV_AUTHOR); | |
88 | MODULE_DESCRIPTION(DRV_DESC); | |
89 | MODULE_LICENSE("GPL"); | |
13130c7a | 90 | MODULE_VERSION(DRV_VERSION); |
1da177e4 | 91 | |
1da177e4 LT |
92 | /* |
93 | * Theory of operation | |
94 | * | |
6aa20a22 JG |
95 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
96 | * There are four receive and four transmit descriptors. These | |
97 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
98 | * hardware registers. |
99 | * | |
100 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 101 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
102 | * hardware registers, however, are still mapped at KSEG1 to |
103 | * make sure there's no out-of-order writes, and that all writes | |
104 | * complete immediately. | |
105 | */ | |
106 | ||
1da177e4 LT |
107 | struct au1000_private *au_macs[NUM_ETH_INTERFACES]; |
108 | ||
0638dec0 HVR |
109 | /* |
110 | * board-specific configurations | |
111 | * | |
112 | * PHY detection algorithm | |
113 | * | |
bd2302c2 | 114 | * If phy_static_config is undefined, the PHY setup is |
0638dec0 HVR |
115 | * autodetected: |
116 | * | |
117 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
bd2302c2 | 118 | * selecting the first (or last, if phy_search_highest_addr is |
0638dec0 HVR |
119 | * defined) PHY address not already claimed by another netdev. |
120 | * | |
121 | * If nothing was found that way when searching for the 2nd ethernet | |
bd2302c2 | 122 | * controller's PHY and phy1_search_mac0 is defined, then |
0638dec0 HVR |
123 | * the first MII bus is searched as well for an unclaimed PHY; this is |
124 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
125 | * bus. | |
126 | * | |
127 | * Finally, if no PHY is found, then the corresponding ethernet | |
128 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
129 | */ |
130 | ||
bd2302c2 | 131 | /* autodetection defaults: phy1_search_mac0 */ |
1da177e4 | 132 | |
0638dec0 HVR |
133 | /* static PHY setup |
134 | * | |
135 | * most boards PHY setup should be detectable properly with the | |
136 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
137 | * you have a switch attached, or want to use the PHY's interrupt | |
138 | * notification capabilities) you can provide a static PHY | |
139 | * configuration here | |
140 | * | |
141 | * IRQs may only be set, if a PHY address was configured | |
142 | * If a PHY address is given, also a bus id is required to be set | |
143 | * | |
144 | * ps: make sure the used irqs are configured properly in the board | |
145 | * specific irq-map | |
146 | */ | |
1da177e4 | 147 | |
eb049630 | 148 | static void au1000_enable_mac(struct net_device *dev, int force_reset) |
5ef3041e FF |
149 | { |
150 | unsigned long flags; | |
151 | struct au1000_private *aup = netdev_priv(dev); | |
152 | ||
153 | spin_lock_irqsave(&aup->lock, flags); | |
154 | ||
ec7eabdd | 155 | if (force_reset || (!aup->mac_enabled)) { |
5ef3041e FF |
156 | *aup->enable = MAC_EN_CLOCK_ENABLE; |
157 | au_sync_delay(2); | |
158 | *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 | |
159 | | MAC_EN_CLOCK_ENABLE); | |
160 | au_sync_delay(2); | |
161 | ||
162 | aup->mac_enabled = 1; | |
163 | } | |
164 | ||
165 | spin_unlock_irqrestore(&aup->lock, flags); | |
166 | } | |
167 | ||
0638dec0 HVR |
168 | /* |
169 | * MII operations | |
170 | */ | |
1210dde7 | 171 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 172 | { |
454d7c9b | 173 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
174 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
175 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
176 | u32 timedout = 20; |
177 | u32 mii_control; | |
178 | ||
1da177e4 LT |
179 | while (*mii_control_reg & MAC_MII_BUSY) { |
180 | mdelay(1); | |
181 | if (--timedout == 0) { | |
5368c726 | 182 | netdev_err(dev, "read_MII busy timeout!!\n"); |
1da177e4 LT |
183 | return -1; |
184 | } | |
185 | } | |
186 | ||
6aa20a22 | 187 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 188 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 LT |
189 | |
190 | *mii_control_reg = mii_control; | |
191 | ||
192 | timedout = 20; | |
193 | while (*mii_control_reg & MAC_MII_BUSY) { | |
194 | mdelay(1); | |
195 | if (--timedout == 0) { | |
5368c726 | 196 | netdev_err(dev, "mdio_read busy timeout!!\n"); |
1da177e4 LT |
197 | return -1; |
198 | } | |
199 | } | |
200 | return (int)*mii_data_reg; | |
201 | } | |
202 | ||
1210dde7 AB |
203 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
204 | int reg, u16 value) | |
1da177e4 | 205 | { |
454d7c9b | 206 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
207 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
208 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
209 | u32 timedout = 20; |
210 | u32 mii_control; | |
211 | ||
1da177e4 LT |
212 | while (*mii_control_reg & MAC_MII_BUSY) { |
213 | mdelay(1); | |
214 | if (--timedout == 0) { | |
5368c726 | 215 | netdev_err(dev, "mdio_write busy timeout!!\n"); |
1da177e4 LT |
216 | return; |
217 | } | |
218 | } | |
219 | ||
6aa20a22 | 220 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 221 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 LT |
222 | |
223 | *mii_data_reg = value; | |
224 | *mii_control_reg = mii_control; | |
225 | } | |
226 | ||
1210dde7 | 227 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 HVR |
228 | { |
229 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
230 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */ | |
231 | struct net_device *const dev = bus->priv; | |
232 | ||
eb049630 | 233 | au1000_enable_mac(dev, 0); /* make sure the MAC associated with this |
0638dec0 | 234 | * mii_bus is enabled */ |
1210dde7 | 235 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 236 | } |
1da177e4 | 237 | |
1210dde7 AB |
238 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
239 | u16 value) | |
1da177e4 | 240 | { |
0638dec0 | 241 | struct net_device *const dev = bus->priv; |
1da177e4 | 242 | |
eb049630 | 243 | au1000_enable_mac(dev, 0); /* make sure the MAC associated with this |
0638dec0 | 244 | * mii_bus is enabled */ |
1210dde7 | 245 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 246 | return 0; |
1da177e4 LT |
247 | } |
248 | ||
1210dde7 | 249 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 250 | { |
0638dec0 | 251 | struct net_device *const dev = bus->priv; |
1da177e4 | 252 | |
eb049630 | 253 | au1000_enable_mac(dev, 0); /* make sure the MAC associated with this |
0638dec0 HVR |
254 | * mii_bus is enabled */ |
255 | return 0; | |
256 | } | |
1da177e4 | 257 | |
eb049630 | 258 | static void au1000_hard_stop(struct net_device *dev) |
5ef3041e FF |
259 | { |
260 | struct au1000_private *aup = netdev_priv(dev); | |
261 | ||
5368c726 | 262 | netif_dbg(aup, drv, dev, "hard stop\n"); |
5ef3041e FF |
263 | |
264 | aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
265 | au_sync_delay(10); | |
266 | } | |
267 | ||
eb049630 | 268 | static void au1000_enable_rx_tx(struct net_device *dev) |
5ef3041e FF |
269 | { |
270 | struct au1000_private *aup = netdev_priv(dev); | |
271 | ||
5368c726 | 272 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); |
5ef3041e FF |
273 | |
274 | aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
275 | au_sync_delay(10); | |
276 | } | |
277 | ||
278 | static void | |
279 | au1000_adjust_link(struct net_device *dev) | |
280 | { | |
281 | struct au1000_private *aup = netdev_priv(dev); | |
282 | struct phy_device *phydev = aup->phy_dev; | |
283 | unsigned long flags; | |
284 | ||
285 | int status_change = 0; | |
286 | ||
287 | BUG_ON(!aup->phy_dev); | |
288 | ||
289 | spin_lock_irqsave(&aup->lock, flags); | |
290 | ||
291 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
2cc3c6b1 | 292 | /* speed changed */ |
5ef3041e | 293 | |
2cc3c6b1 | 294 | switch (phydev->speed) { |
5ef3041e FF |
295 | case SPEED_10: |
296 | case SPEED_100: | |
297 | break; | |
298 | default: | |
5368c726 FF |
299 | netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", |
300 | phydev->speed); | |
5ef3041e FF |
301 | break; |
302 | } | |
303 | ||
304 | aup->old_speed = phydev->speed; | |
305 | ||
306 | status_change = 1; | |
307 | } | |
308 | ||
309 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
2cc3c6b1 | 310 | /* duplex mode changed */ |
5ef3041e FF |
311 | |
312 | /* switching duplex mode requires to disable rx and tx! */ | |
eb049630 | 313 | au1000_hard_stop(dev); |
5ef3041e FF |
314 | |
315 | if (DUPLEX_FULL == phydev->duplex) | |
316 | aup->mac->control = ((aup->mac->control | |
317 | | MAC_FULL_DUPLEX) | |
318 | & ~MAC_DISABLE_RX_OWN); | |
319 | else | |
320 | aup->mac->control = ((aup->mac->control | |
321 | & ~MAC_FULL_DUPLEX) | |
322 | | MAC_DISABLE_RX_OWN); | |
323 | au_sync_delay(1); | |
324 | ||
eb049630 | 325 | au1000_enable_rx_tx(dev); |
5ef3041e FF |
326 | aup->old_duplex = phydev->duplex; |
327 | ||
328 | status_change = 1; | |
329 | } | |
330 | ||
2cc3c6b1 FF |
331 | if (phydev->link != aup->old_link) { |
332 | /* link state changed */ | |
5ef3041e FF |
333 | |
334 | if (!phydev->link) { | |
335 | /* link went down */ | |
336 | aup->old_speed = 0; | |
337 | aup->old_duplex = -1; | |
338 | } | |
339 | ||
340 | aup->old_link = phydev->link; | |
341 | status_change = 1; | |
342 | } | |
343 | ||
344 | spin_unlock_irqrestore(&aup->lock, flags); | |
345 | ||
346 | if (status_change) { | |
347 | if (phydev->link) | |
5368c726 FF |
348 | netdev_info(dev, "link up (%d/%s)\n", |
349 | phydev->speed, | |
5ef3041e FF |
350 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); |
351 | else | |
5368c726 | 352 | netdev_info(dev, "link down\n"); |
5ef3041e FF |
353 | } |
354 | } | |
355 | ||
ec7eabdd | 356 | static int au1000_mii_probe(struct net_device *dev) |
0638dec0 | 357 | { |
454d7c9b | 358 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 | 359 | struct phy_device *phydev = NULL; |
18b8e15b | 360 | int phy_addr; |
0638dec0 | 361 | |
bd2302c2 FF |
362 | if (aup->phy_static_config) { |
363 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
0638dec0 | 364 | |
bd2302c2 FF |
365 | if (aup->phy_addr) |
366 | phydev = aup->mii_bus->phy_map[aup->phy_addr]; | |
367 | else | |
5368c726 | 368 | netdev_info(dev, "using PHY-less setup\n"); |
0638dec0 | 369 | return 0; |
18b8e15b | 370 | } |
0638dec0 | 371 | |
18b8e15b FF |
372 | /* find the first (lowest address) PHY |
373 | * on the current MAC's MII bus */ | |
374 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) | |
375 | if (aup->mii_bus->phy_map[phy_addr]) { | |
376 | phydev = aup->mii_bus->phy_map[phy_addr]; | |
377 | if (!aup->phy_search_highest_addr) | |
378 | /* break out with first one found */ | |
379 | break; | |
380 | } | |
0638dec0 | 381 | |
18b8e15b FF |
382 | if (aup->phy1_search_mac0) { |
383 | /* try harder to find a PHY */ | |
384 | if (!phydev && (aup->mac_id == 1)) { | |
385 | /* no PHY found, maybe we have a dual PHY? */ | |
386 | dev_info(&dev->dev, ": no PHY found on MAC1, " | |
387 | "let's see if it's attached to MAC0...\n"); | |
388 | ||
389 | /* find the first (lowest address) non-attached | |
390 | * PHY on the MAC0 MII bus | |
391 | */ | |
392 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
393 | struct phy_device *const tmp_phydev = | |
394 | aup->mii_bus->phy_map[phy_addr]; | |
395 | ||
396 | if (aup->mac_id == 1) | |
397 | break; | |
398 | ||
399 | /* no PHY here... */ | |
400 | if (!tmp_phydev) | |
401 | continue; | |
402 | ||
403 | /* already claimed by MAC0 */ | |
404 | if (tmp_phydev->attached_dev) | |
405 | continue; | |
406 | ||
407 | phydev = tmp_phydev; | |
408 | break; /* found it */ | |
bd2302c2 | 409 | } |
1da177e4 LT |
410 | } |
411 | } | |
1da177e4 | 412 | |
0638dec0 | 413 | if (!phydev) { |
5368c726 | 414 | netdev_err(dev, "no PHY found\n"); |
1da177e4 LT |
415 | return -1; |
416 | } | |
417 | ||
0638dec0 | 418 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
419 | BUG_ON(phydev->attached_dev); |
420 | ||
db1d7bf7 KS |
421 | phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link, |
422 | 0, PHY_INTERFACE_MODE_MII); | |
0638dec0 HVR |
423 | |
424 | if (IS_ERR(phydev)) { | |
5368c726 | 425 | netdev_err(dev, "Could not attach to PHY\n"); |
0638dec0 HVR |
426 | return PTR_ERR(phydev); |
427 | } | |
428 | ||
429 | /* mask with MAC supported features */ | |
430 | phydev->supported &= (SUPPORTED_10baseT_Half | |
431 | | SUPPORTED_10baseT_Full | |
432 | | SUPPORTED_100baseT_Half | |
433 | | SUPPORTED_100baseT_Full | |
434 | | SUPPORTED_Autoneg | |
435 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
436 | | SUPPORTED_MII | |
437 | | SUPPORTED_TP); | |
438 | ||
439 | phydev->advertising = phydev->supported; | |
440 | ||
441 | aup->old_link = 0; | |
442 | aup->old_speed = 0; | |
443 | aup->old_duplex = -1; | |
444 | aup->phy_dev = phydev; | |
445 | ||
5368c726 FF |
446 | netdev_info(dev, "attached PHY driver [%s] " |
447 | "(mii_bus:phy_addr=%s, irq=%d)\n", | |
db1d7bf7 | 448 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); |
1da177e4 LT |
449 | |
450 | return 0; | |
451 | } | |
452 | ||
453 | ||
454 | /* | |
455 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 456 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
457 | * both, receive and transmit operations. |
458 | */ | |
3441592b | 459 | static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup) |
1da177e4 | 460 | { |
3441592b | 461 | struct db_dest *pDB; |
1da177e4 LT |
462 | pDB = aup->pDBfree; |
463 | ||
ec7eabdd | 464 | if (pDB) |
1da177e4 | 465 | aup->pDBfree = pDB->pnext; |
ec7eabdd | 466 | |
1da177e4 LT |
467 | return pDB; |
468 | } | |
469 | ||
3441592b | 470 | void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB) |
1da177e4 | 471 | { |
3441592b | 472 | struct db_dest *pDBfree = aup->pDBfree; |
1da177e4 LT |
473 | if (pDBfree) |
474 | pDBfree->pnext = pDB; | |
475 | aup->pDBfree = pDB; | |
476 | } | |
477 | ||
eb049630 | 478 | static void au1000_reset_mac_unlocked(struct net_device *dev) |
0638dec0 | 479 | { |
454d7c9b | 480 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
481 | int i; |
482 | ||
eb049630 | 483 | au1000_hard_stop(dev); |
0638dec0 HVR |
484 | |
485 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
486 | au_sync_delay(2); | |
487 | *aup->enable = 0; | |
488 | au_sync_delay(2); | |
489 | ||
1da177e4 LT |
490 | aup->tx_full = 0; |
491 | for (i = 0; i < NUM_RX_DMA; i++) { | |
492 | /* reset control bits */ | |
493 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
494 | } | |
495 | for (i = 0; i < NUM_TX_DMA; i++) { | |
496 | /* reset control bits */ | |
497 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
498 | } | |
0638dec0 HVR |
499 | |
500 | aup->mac_enabled = 0; | |
501 | ||
1da177e4 LT |
502 | } |
503 | ||
eb049630 | 504 | static void au1000_reset_mac(struct net_device *dev) |
0638dec0 | 505 | { |
454d7c9b | 506 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
507 | unsigned long flags; |
508 | ||
5368c726 FF |
509 | netif_dbg(aup, hw, dev, "reset mac, aup %x\n", |
510 | (unsigned)aup); | |
0638dec0 HVR |
511 | |
512 | spin_lock_irqsave(&aup->lock, flags); | |
513 | ||
ec7eabdd | 514 | au1000_reset_mac_unlocked(dev); |
0638dec0 HVR |
515 | |
516 | spin_unlock_irqrestore(&aup->lock, flags); | |
517 | } | |
1da177e4 | 518 | |
6aa20a22 | 519 | /* |
1da177e4 LT |
520 | * Setup the receive and transmit "rings". These pointers are the addresses |
521 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
522 | * these are not descriptors sitting in memory. | |
523 | */ | |
6aa20a22 | 524 | static void |
eb049630 | 525 | au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) |
1da177e4 LT |
526 | { |
527 | int i; | |
528 | ||
529 | for (i = 0; i < NUM_RX_DMA; i++) { | |
6aa20a22 | 530 | aup->rx_dma_ring[i] = |
18b8e15b FF |
531 | (volatile struct rx_dma *) |
532 | (rx_base + sizeof(struct rx_dma)*i); | |
1da177e4 LT |
533 | } |
534 | for (i = 0; i < NUM_TX_DMA; i++) { | |
6aa20a22 | 535 | aup->tx_dma_ring[i] = |
18b8e15b FF |
536 | (volatile struct tx_dma *) |
537 | (tx_base + sizeof(struct tx_dma)*i); | |
1da177e4 LT |
538 | } |
539 | } | |
540 | ||
0638dec0 HVR |
541 | /* |
542 | * ethtool operations | |
543 | */ | |
1da177e4 | 544 | |
0638dec0 | 545 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 546 | { |
454d7c9b | 547 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 548 | |
0638dec0 HVR |
549 | if (aup->phy_dev) |
550 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 551 | |
0638dec0 | 552 | return -EINVAL; |
1da177e4 LT |
553 | } |
554 | ||
0638dec0 | 555 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 556 | { |
454d7c9b | 557 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 558 | |
0638dec0 HVR |
559 | if (!capable(CAP_NET_ADMIN)) |
560 | return -EPERM; | |
1da177e4 | 561 | |
0638dec0 HVR |
562 | if (aup->phy_dev) |
563 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 564 | |
0638dec0 | 565 | return -EINVAL; |
1da177e4 LT |
566 | } |
567 | ||
568 | static void | |
569 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
570 | { | |
454d7c9b | 571 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 LT |
572 | |
573 | strcpy(info->driver, DRV_NAME); | |
574 | strcpy(info->version, DRV_VERSION); | |
575 | info->fw_version[0] = '\0'; | |
576 | sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id); | |
577 | info->regdump_len = 0; | |
578 | } | |
579 | ||
7cd2e6e3 FF |
580 | static void au1000_set_msglevel(struct net_device *dev, u32 value) |
581 | { | |
582 | struct au1000_private *aup = netdev_priv(dev); | |
583 | aup->msg_enable = value; | |
584 | } | |
585 | ||
586 | static u32 au1000_get_msglevel(struct net_device *dev) | |
587 | { | |
588 | struct au1000_private *aup = netdev_priv(dev); | |
589 | return aup->msg_enable; | |
590 | } | |
591 | ||
7282d491 | 592 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
593 | .get_settings = au1000_get_settings, |
594 | .set_settings = au1000_set_settings, | |
595 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 596 | .get_link = ethtool_op_get_link, |
7cd2e6e3 FF |
597 | .get_msglevel = au1000_get_msglevel, |
598 | .set_msglevel = au1000_set_msglevel, | |
1da177e4 LT |
599 | }; |
600 | ||
5ef3041e FF |
601 | |
602 | /* | |
603 | * Initialize the interface. | |
604 | * | |
605 | * When the device powers up, the clocks are disabled and the | |
606 | * mac is in reset state. When the interface is closed, we | |
607 | * do the same -- reset the device and disable the clocks to | |
608 | * conserve power. Thus, whenever au1000_init() is called, | |
609 | * the device should already be in reset state. | |
610 | */ | |
611 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 612 | { |
5ef3041e FF |
613 | struct au1000_private *aup = netdev_priv(dev); |
614 | unsigned long flags; | |
615 | int i; | |
616 | u32 control; | |
89be0501 | 617 | |
5368c726 | 618 | netif_dbg(aup, hw, dev, "au1000_init\n"); |
1da177e4 | 619 | |
5ef3041e | 620 | /* bring the device out of reset */ |
eb049630 | 621 | au1000_enable_mac(dev, 1); |
89be0501 | 622 | |
5ef3041e | 623 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 624 | |
5ef3041e FF |
625 | aup->mac->control = 0; |
626 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
627 | aup->tx_tail = aup->tx_head; | |
628 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 629 | |
5ef3041e FF |
630 | aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4]; |
631 | aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
632 | dev->dev_addr[1]<<8 | dev->dev_addr[0]; | |
633 | ||
18b8e15b | 634 | |
ec7eabdd | 635 | for (i = 0; i < NUM_RX_DMA; i++) |
5ef3041e | 636 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; |
ec7eabdd | 637 | |
5ef3041e | 638 | au_sync(); |
1da177e4 | 639 | |
5ef3041e FF |
640 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
641 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
642 | control |= MAC_BIG_ENDIAN; | |
643 | #endif | |
644 | if (aup->phy_dev) { | |
645 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
646 | control |= MAC_FULL_DUPLEX; | |
647 | else | |
648 | control |= MAC_DISABLE_RX_OWN; | |
649 | } else { /* PHY-less op, assume full-duplex */ | |
650 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
651 | } |
652 | ||
5ef3041e FF |
653 | aup->mac->control = control; |
654 | aup->mac->vlan1_tag = 0x8100; /* activate vlan support */ | |
655 | au_sync(); | |
1da177e4 | 656 | |
5ef3041e FF |
657 | spin_unlock_irqrestore(&aup->lock, flags); |
658 | return 0; | |
659 | } | |
1da177e4 | 660 | |
eb049630 | 661 | static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) |
5ef3041e | 662 | { |
5ef3041e | 663 | struct net_device_stats *ps = &dev->stats; |
1da177e4 | 664 | |
5ef3041e FF |
665 | ps->rx_packets++; |
666 | if (status & RX_MCAST_FRAME) | |
667 | ps->multicast++; | |
1da177e4 | 668 | |
5ef3041e FF |
669 | if (status & RX_ERROR) { |
670 | ps->rx_errors++; | |
671 | if (status & RX_MISSED_FRAME) | |
672 | ps->rx_missed_errors++; | |
4989ccb2 | 673 | if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) |
5ef3041e FF |
674 | ps->rx_length_errors++; |
675 | if (status & RX_CRC_ERROR) | |
676 | ps->rx_crc_errors++; | |
677 | if (status & RX_COLL) | |
678 | ps->collisions++; | |
2cc3c6b1 | 679 | } else |
5ef3041e | 680 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; |
298cf9be | 681 | |
1da177e4 LT |
682 | } |
683 | ||
6aa20a22 | 684 | /* |
5ef3041e | 685 | * Au1000 receive routine. |
1da177e4 | 686 | */ |
5ef3041e | 687 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 688 | { |
454d7c9b | 689 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 690 | struct sk_buff *skb; |
3441592b | 691 | volatile struct rx_dma *prxd; |
5ef3041e | 692 | u32 buff_stat, status; |
3441592b | 693 | struct db_dest *pDB; |
5ef3041e | 694 | u32 frmlen; |
1da177e4 | 695 | |
5368c726 | 696 | netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); |
1da177e4 | 697 | |
5ef3041e FF |
698 | prxd = aup->rx_dma_ring[aup->rx_head]; |
699 | buff_stat = prxd->buff_stat; | |
700 | while (buff_stat & RX_T_DONE) { | |
701 | status = prxd->status; | |
702 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
eb049630 | 703 | au1000_update_rx_stats(dev, status); |
5ef3041e | 704 | if (!(status & RX_ERROR)) { |
1da177e4 | 705 | |
5ef3041e FF |
706 | /* good frame */ |
707 | frmlen = (status & RX_FRAME_LEN_MASK); | |
708 | frmlen -= 4; /* Remove FCS */ | |
709 | skb = dev_alloc_skb(frmlen + 2); | |
710 | if (skb == NULL) { | |
5368c726 | 711 | netdev_err(dev, "Memory squeeze, dropping packet.\n"); |
5ef3041e FF |
712 | dev->stats.rx_dropped++; |
713 | continue; | |
714 | } | |
715 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
716 | skb_copy_to_linear_data(skb, | |
717 | (unsigned char *)pDB->vaddr, frmlen); | |
718 | skb_put(skb, frmlen); | |
719 | skb->protocol = eth_type_trans(skb, dev); | |
720 | netif_rx(skb); /* pass the packet to upper layers */ | |
2cc3c6b1 | 721 | } else { |
5ef3041e FF |
722 | if (au1000_debug > 4) { |
723 | if (status & RX_MISSED_FRAME) | |
724 | printk("rx miss\n"); | |
725 | if (status & RX_WDOG_TIMER) | |
726 | printk("rx wdog\n"); | |
727 | if (status & RX_RUNT) | |
728 | printk("rx runt\n"); | |
729 | if (status & RX_OVERLEN) | |
730 | printk("rx overlen\n"); | |
731 | if (status & RX_COLL) | |
732 | printk("rx coll\n"); | |
733 | if (status & RX_MII_ERROR) | |
734 | printk("rx mii error\n"); | |
735 | if (status & RX_CRC_ERROR) | |
736 | printk("rx crc error\n"); | |
737 | if (status & RX_LEN_ERROR) | |
738 | printk("rx len error\n"); | |
739 | if (status & RX_U_CNTRL_FRAME) | |
740 | printk("rx u control frame\n"); | |
5ef3041e FF |
741 | } |
742 | } | |
743 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
744 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
745 | au_sync(); | |
1da177e4 | 746 | |
5ef3041e FF |
747 | /* next descriptor */ |
748 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
749 | buff_stat = prxd->buff_stat; | |
1da177e4 | 750 | } |
1da177e4 LT |
751 | return 0; |
752 | } | |
753 | ||
eb049630 | 754 | static void au1000_update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 755 | { |
454d7c9b | 756 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 757 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 758 | |
5ef3041e FF |
759 | if (status & TX_FRAME_ABORTED) { |
760 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { | |
761 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { | |
762 | /* any other tx errors are only valid | |
763 | * in half duplex mode */ | |
764 | ps->tx_errors++; | |
765 | ps->tx_aborted_errors++; | |
766 | } | |
2cc3c6b1 | 767 | } else { |
5ef3041e FF |
768 | ps->tx_errors++; |
769 | ps->tx_aborted_errors++; | |
770 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
771 | ps->tx_carrier_errors++; | |
772 | } | |
773 | } | |
774 | } | |
0638dec0 | 775 | |
5ef3041e FF |
776 | /* |
777 | * Called from the interrupt service routine to acknowledge | |
778 | * the TX DONE bits. This is a must if the irq is setup as | |
779 | * edge triggered. | |
780 | */ | |
781 | static void au1000_tx_ack(struct net_device *dev) | |
782 | { | |
783 | struct au1000_private *aup = netdev_priv(dev); | |
3441592b | 784 | volatile struct tx_dma *ptxd; |
0638dec0 | 785 | |
5ef3041e | 786 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 787 | |
5ef3041e | 788 | while (ptxd->buff_stat & TX_T_DONE) { |
eb049630 | 789 | au1000_update_tx_stats(dev, ptxd->status); |
5ef3041e FF |
790 | ptxd->buff_stat &= ~TX_T_DONE; |
791 | ptxd->len = 0; | |
792 | au_sync(); | |
0638dec0 | 793 | |
5ef3041e FF |
794 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
795 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 796 | |
5ef3041e FF |
797 | if (aup->tx_full) { |
798 | aup->tx_full = 0; | |
799 | netif_wake_queue(dev); | |
800 | } | |
1da177e4 | 801 | } |
5ef3041e | 802 | } |
1da177e4 | 803 | |
5ef3041e FF |
804 | /* |
805 | * Au1000 interrupt service routine. | |
806 | */ | |
807 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
808 | { | |
809 | struct net_device *dev = dev_id; | |
1da177e4 | 810 | |
5ef3041e FF |
811 | /* Handle RX interrupts first to minimize chance of overrun */ |
812 | ||
813 | au1000_rx(dev); | |
814 | au1000_tx_ack(dev); | |
815 | return IRQ_RETVAL(1); | |
1da177e4 LT |
816 | } |
817 | ||
818 | static int au1000_open(struct net_device *dev) | |
819 | { | |
820 | int retval; | |
454d7c9b | 821 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 822 | |
5368c726 | 823 | netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); |
1da177e4 | 824 | |
2cc3c6b1 FF |
825 | retval = request_irq(dev->irq, au1000_interrupt, 0, |
826 | dev->name, dev); | |
827 | if (retval) { | |
5368c726 | 828 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
0638dec0 HVR |
829 | return retval; |
830 | } | |
831 | ||
2cc3c6b1 FF |
832 | retval = au1000_init(dev); |
833 | if (retval) { | |
5368c726 | 834 | netdev_err(dev, "error in au1000_init\n"); |
1da177e4 LT |
835 | free_irq(dev->irq, dev); |
836 | return retval; | |
837 | } | |
1da177e4 | 838 | |
0638dec0 HVR |
839 | if (aup->phy_dev) { |
840 | /* cause the PHY state machine to schedule a link state check */ | |
841 | aup->phy_dev->state = PHY_CHANGELINK; | |
842 | phy_start(aup->phy_dev); | |
1da177e4 LT |
843 | } |
844 | ||
0638dec0 | 845 | netif_start_queue(dev); |
1da177e4 | 846 | |
5368c726 | 847 | netif_dbg(aup, drv, dev, "open: Initialization done.\n"); |
1da177e4 LT |
848 | |
849 | return 0; | |
850 | } | |
851 | ||
852 | static int au1000_close(struct net_device *dev) | |
853 | { | |
0638dec0 | 854 | unsigned long flags; |
454d7c9b | 855 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 | 856 | |
5368c726 | 857 | netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); |
1da177e4 | 858 | |
0638dec0 HVR |
859 | if (aup->phy_dev) |
860 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
861 | |
862 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 | 863 | |
ec7eabdd | 864 | au1000_reset_mac_unlocked(dev); |
0638dec0 | 865 | |
1da177e4 LT |
866 | /* stop the device */ |
867 | netif_stop_queue(dev); | |
868 | ||
869 | /* disable the interrupt */ | |
870 | free_irq(dev->irq, dev); | |
871 | spin_unlock_irqrestore(&aup->lock, flags); | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
1da177e4 LT |
876 | /* |
877 | * Au1000 transmit routine. | |
878 | */ | |
61357325 | 879 | static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 880 | { |
454d7c9b | 881 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 882 | struct net_device_stats *ps = &dev->stats; |
3441592b | 883 | volatile struct tx_dma *ptxd; |
1da177e4 | 884 | u32 buff_stat; |
3441592b | 885 | struct db_dest *pDB; |
1da177e4 LT |
886 | int i; |
887 | ||
5368c726 FF |
888 | netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", |
889 | (unsigned)aup, skb->len, | |
1da177e4 LT |
890 | skb->data, aup->tx_head); |
891 | ||
892 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
893 | buff_stat = ptxd->buff_stat; | |
894 | if (buff_stat & TX_DMA_ENABLE) { | |
895 | /* We've wrapped around and the transmitter is still busy */ | |
896 | netif_stop_queue(dev); | |
897 | aup->tx_full = 1; | |
5b548140 | 898 | return NETDEV_TX_BUSY; |
2cc3c6b1 | 899 | } else if (buff_stat & TX_T_DONE) { |
eb049630 | 900 | au1000_update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
901 | ptxd->len = 0; |
902 | } | |
903 | ||
904 | if (aup->tx_full) { | |
905 | aup->tx_full = 0; | |
906 | netif_wake_queue(dev); | |
907 | } | |
908 | ||
909 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
bd2302c2 | 910 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 | 911 | if (skb->len < ETH_ZLEN) { |
ec7eabdd | 912 | for (i = skb->len; i < ETH_ZLEN; i++) |
1da177e4 | 913 | ((char *)pDB->vaddr)[i] = 0; |
ec7eabdd | 914 | |
1da177e4 | 915 | ptxd->len = ETH_ZLEN; |
2cc3c6b1 | 916 | } else |
5ef3041e | 917 | ptxd->len = skb->len; |
1da177e4 | 918 | |
5ef3041e FF |
919 | ps->tx_packets++; |
920 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 921 | |
5ef3041e FF |
922 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
923 | au_sync(); | |
924 | dev_kfree_skb(skb); | |
925 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
6ed10654 | 926 | return NETDEV_TX_OK; |
1da177e4 LT |
927 | } |
928 | ||
1da177e4 LT |
929 | /* |
930 | * The Tx ring has been full longer than the watchdog timeout | |
931 | * value. The transmitter must be hung? | |
932 | */ | |
933 | static void au1000_tx_timeout(struct net_device *dev) | |
934 | { | |
5368c726 | 935 | netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); |
eb049630 | 936 | au1000_reset_mac(dev); |
1da177e4 | 937 | au1000_init(dev); |
1ae5dc34 | 938 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
939 | netif_wake_queue(dev); |
940 | } | |
941 | ||
d9a92cee | 942 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 943 | { |
454d7c9b | 944 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 945 | |
18b8e15b | 946 | netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); |
1da177e4 LT |
947 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
948 | aup->mac->control |= MAC_PROMISCUOUS; | |
1da177e4 | 949 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 950 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { |
1da177e4 LT |
951 | aup->mac->control |= MAC_PASS_ALL_MULTI; |
952 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
5368c726 | 953 | netdev_info(dev, "Pass all multicast\n"); |
1da177e4 | 954 | } else { |
22bedad3 | 955 | struct netdev_hw_addr *ha; |
1da177e4 LT |
956 | u32 mc_filter[2]; /* Multicast hash filter */ |
957 | ||
958 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
959 | netdev_for_each_mc_addr(ha, dev) |
960 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, | |
1da177e4 | 961 | (long *)mc_filter); |
1da177e4 LT |
962 | aup->mac->multi_hash_high = mc_filter[1]; |
963 | aup->mac->multi_hash_low = mc_filter[0]; | |
964 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
965 | aup->mac->control |= MAC_HASH_MODE; | |
966 | } | |
967 | } | |
968 | ||
1da177e4 LT |
969 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
970 | { | |
454d7c9b | 971 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 972 | |
2cc3c6b1 FF |
973 | if (!netif_running(dev)) |
974 | return -EINVAL; | |
1da177e4 | 975 | |
2cc3c6b1 FF |
976 | if (!aup->phy_dev) |
977 | return -EINVAL; /* PHY not controllable */ | |
1da177e4 | 978 | |
28b04113 | 979 | return phy_mii_ioctl(aup->phy_dev, rq, cmd); |
1da177e4 LT |
980 | } |
981 | ||
d9a92cee AB |
982 | static const struct net_device_ops au1000_netdev_ops = { |
983 | .ndo_open = au1000_open, | |
984 | .ndo_stop = au1000_close, | |
985 | .ndo_start_xmit = au1000_tx, | |
986 | .ndo_set_multicast_list = au1000_multicast_list, | |
987 | .ndo_do_ioctl = au1000_ioctl, | |
988 | .ndo_tx_timeout = au1000_tx_timeout, | |
989 | .ndo_set_mac_address = eth_mac_addr, | |
990 | .ndo_validate_addr = eth_validate_addr, | |
991 | .ndo_change_mtu = eth_change_mtu, | |
992 | }; | |
993 | ||
bd2302c2 | 994 | static int __devinit au1000_probe(struct platform_device *pdev) |
5ef3041e | 995 | { |
2cc3c6b1 | 996 | static unsigned version_printed; |
5ef3041e | 997 | struct au1000_private *aup = NULL; |
bd2302c2 | 998 | struct au1000_eth_platform_data *pd; |
5ef3041e | 999 | struct net_device *dev = NULL; |
3441592b | 1000 | struct db_dest *pDB, *pDBfree; |
bd2302c2 FF |
1001 | int irq, i, err = 0; |
1002 | struct resource *base, *macen; | |
5ef3041e | 1003 | |
bd2302c2 FF |
1004 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1005 | if (!base) { | |
5368c726 | 1006 | dev_err(&pdev->dev, "failed to retrieve base register\n"); |
bd2302c2 FF |
1007 | err = -ENODEV; |
1008 | goto out; | |
1009 | } | |
5ef3041e | 1010 | |
bd2302c2 FF |
1011 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1012 | if (!macen) { | |
5368c726 | 1013 | dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); |
bd2302c2 FF |
1014 | err = -ENODEV; |
1015 | goto out; | |
1016 | } | |
5ef3041e | 1017 | |
bd2302c2 FF |
1018 | irq = platform_get_irq(pdev, 0); |
1019 | if (irq < 0) { | |
5368c726 | 1020 | dev_err(&pdev->dev, "failed to retrieve IRQ\n"); |
bd2302c2 FF |
1021 | err = -ENODEV; |
1022 | goto out; | |
1023 | } | |
5ef3041e | 1024 | |
18b8e15b FF |
1025 | if (!request_mem_region(base->start, resource_size(base), |
1026 | pdev->name)) { | |
5368c726 | 1027 | dev_err(&pdev->dev, "failed to request memory region for base registers\n"); |
bd2302c2 FF |
1028 | err = -ENXIO; |
1029 | goto out; | |
1030 | } | |
1031 | ||
18b8e15b FF |
1032 | if (!request_mem_region(macen->start, resource_size(macen), |
1033 | pdev->name)) { | |
5368c726 | 1034 | dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); |
bd2302c2 FF |
1035 | err = -ENXIO; |
1036 | goto err_request; | |
1037 | } | |
5ef3041e FF |
1038 | |
1039 | dev = alloc_etherdev(sizeof(struct au1000_private)); | |
1040 | if (!dev) { | |
5368c726 | 1041 | dev_err(&pdev->dev, "alloc_etherdev failed\n"); |
bd2302c2 FF |
1042 | err = -ENOMEM; |
1043 | goto err_alloc; | |
5ef3041e FF |
1044 | } |
1045 | ||
bd2302c2 FF |
1046 | SET_NETDEV_DEV(dev, &pdev->dev); |
1047 | platform_set_drvdata(pdev, dev); | |
5ef3041e FF |
1048 | aup = netdev_priv(dev); |
1049 | ||
1050 | spin_lock_init(&aup->lock); | |
18b8e15b FF |
1051 | aup->msg_enable = (au1000_debug < 4 ? |
1052 | AU1000_DEF_MSG_ENABLE : au1000_debug); | |
5ef3041e FF |
1053 | |
1054 | /* Allocate the data buffers */ | |
1055 | /* Snooping works fine with eth on all au1xxx */ | |
1056 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * | |
1057 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1058 | &aup->dma_addr, 0); | |
1059 | if (!aup->vaddr) { | |
5368c726 | 1060 | dev_err(&pdev->dev, "failed to allocate data buffers\n"); |
bd2302c2 FF |
1061 | err = -ENOMEM; |
1062 | goto err_vaddr; | |
5ef3041e FF |
1063 | } |
1064 | ||
1065 | /* aup->mac is the base address of the MAC's registers */ | |
18b8e15b FF |
1066 | aup->mac = (volatile struct mac_reg *) |
1067 | ioremap_nocache(base->start, resource_size(base)); | |
bd2302c2 | 1068 | if (!aup->mac) { |
5368c726 | 1069 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); |
bd2302c2 FF |
1070 | err = -ENXIO; |
1071 | goto err_remap1; | |
1072 | } | |
5ef3041e | 1073 | |
ec7eabdd | 1074 | /* Setup some variables for quick register address access */ |
18b8e15b FF |
1075 | aup->enable = (volatile u32 *)ioremap_nocache(macen->start, |
1076 | resource_size(macen)); | |
bd2302c2 | 1077 | if (!aup->enable) { |
5368c726 | 1078 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); |
bd2302c2 FF |
1079 | err = -ENXIO; |
1080 | goto err_remap2; | |
1081 | } | |
1082 | aup->mac_id = pdev->id; | |
5ef3041e | 1083 | |
f6673653 | 1084 | if (pdev->id == 0) |
eb049630 | 1085 | au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); |
f6673653 | 1086 | else if (pdev->id == 1) |
eb049630 | 1087 | au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); |
5ef3041e | 1088 | |
f6673653 ML |
1089 | /* set a random MAC now in case platform_data doesn't provide one */ |
1090 | random_ether_addr(dev->dev_addr); | |
5ef3041e FF |
1091 | |
1092 | *aup->enable = 0; | |
1093 | aup->mac_enabled = 0; | |
1094 | ||
bd2302c2 FF |
1095 | pd = pdev->dev.platform_data; |
1096 | if (!pd) { | |
18b8e15b FF |
1097 | dev_info(&pdev->dev, "no platform_data passed," |
1098 | " PHY search on MAC0\n"); | |
bd2302c2 FF |
1099 | aup->phy1_search_mac0 = 1; |
1100 | } else { | |
f6673653 ML |
1101 | if (is_valid_ether_addr(pd->mac)) |
1102 | memcpy(dev->dev_addr, pd->mac, 6); | |
1103 | ||
bd2302c2 FF |
1104 | aup->phy_static_config = pd->phy_static_config; |
1105 | aup->phy_search_highest_addr = pd->phy_search_highest_addr; | |
1106 | aup->phy1_search_mac0 = pd->phy1_search_mac0; | |
1107 | aup->phy_addr = pd->phy_addr; | |
1108 | aup->phy_busid = pd->phy_busid; | |
1109 | aup->phy_irq = pd->phy_irq; | |
1110 | } | |
1111 | ||
1112 | if (aup->phy_busid && aup->phy_busid > 0) { | |
18b8e15b | 1113 | dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n"); |
bd2302c2 FF |
1114 | err = -ENODEV; |
1115 | goto err_mdiobus_alloc; | |
1116 | } | |
1117 | ||
5ef3041e | 1118 | aup->mii_bus = mdiobus_alloc(); |
bd2302c2 | 1119 | if (aup->mii_bus == NULL) { |
5368c726 | 1120 | dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); |
bd2302c2 FF |
1121 | err = -ENOMEM; |
1122 | goto err_mdiobus_alloc; | |
1123 | } | |
5ef3041e FF |
1124 | |
1125 | aup->mii_bus->priv = dev; | |
1126 | aup->mii_bus->read = au1000_mdiobus_read; | |
1127 | aup->mii_bus->write = au1000_mdiobus_write; | |
1128 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1129 | aup->mii_bus->name = "au1000_eth_mii"; | |
1130 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id); | |
1131 | aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
dcbfef82 | 1132 | if (aup->mii_bus->irq == NULL) |
1133 | goto err_out; | |
1134 | ||
2cc3c6b1 | 1135 | for (i = 0; i < PHY_MAX_ADDR; ++i) |
5ef3041e | 1136 | aup->mii_bus->irq[i] = PHY_POLL; |
5ef3041e | 1137 | /* if known, set corresponding PHY IRQs */ |
bd2302c2 FF |
1138 | if (aup->phy_static_config) |
1139 | if (aup->phy_irq && aup->phy_busid == aup->mac_id) | |
1140 | aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; | |
1141 | ||
1142 | err = mdiobus_register(aup->mii_bus); | |
1143 | if (err) { | |
5368c726 | 1144 | dev_err(&pdev->dev, "failed to register MDIO bus\n"); |
bd2302c2 FF |
1145 | goto err_mdiobus_reg; |
1146 | } | |
5ef3041e | 1147 | |
eb049630 | 1148 | if (au1000_mii_probe(dev) != 0) |
5ef3041e | 1149 | goto err_out; |
5ef3041e FF |
1150 | |
1151 | pDBfree = NULL; | |
1152 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1153 | pDB = aup->db; | |
1154 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1155 | pDB->pnext = pDBfree; | |
1156 | pDBfree = pDB; | |
1157 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1158 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1159 | pDB++; | |
1160 | } | |
1161 | aup->pDBfree = pDBfree; | |
1162 | ||
1163 | for (i = 0; i < NUM_RX_DMA; i++) { | |
eb049630 | 1164 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1165 | if (!pDB) |
5ef3041e | 1166 | goto err_out; |
ec7eabdd | 1167 | |
5ef3041e FF |
1168 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1169 | aup->rx_db_inuse[i] = pDB; | |
1170 | } | |
1171 | for (i = 0; i < NUM_TX_DMA; i++) { | |
eb049630 | 1172 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1173 | if (!pDB) |
5ef3041e | 1174 | goto err_out; |
ec7eabdd | 1175 | |
5ef3041e FF |
1176 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1177 | aup->tx_dma_ring[i]->len = 0; | |
1178 | aup->tx_db_inuse[i] = pDB; | |
1179 | } | |
1180 | ||
bd2302c2 FF |
1181 | dev->base_addr = base->start; |
1182 | dev->irq = irq; | |
1183 | dev->netdev_ops = &au1000_netdev_ops; | |
1184 | SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops); | |
1185 | dev->watchdog_timeo = ETH_TX_TIMEOUT; | |
1186 | ||
5ef3041e FF |
1187 | /* |
1188 | * The boot code uses the ethernet controller, so reset it to start | |
1189 | * fresh. au1000_init() expects that the device is in reset state. | |
1190 | */ | |
eb049630 | 1191 | au1000_reset_mac(dev); |
5ef3041e | 1192 | |
bd2302c2 FF |
1193 | err = register_netdev(dev); |
1194 | if (err) { | |
5368c726 | 1195 | netdev_err(dev, "Cannot register net device, aborting.\n"); |
bd2302c2 FF |
1196 | goto err_out; |
1197 | } | |
1198 | ||
5368c726 FF |
1199 | netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", |
1200 | (unsigned long)base->start, irq); | |
bd2302c2 FF |
1201 | if (version_printed++ == 0) |
1202 | printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
1203 | ||
1204 | return 0; | |
5ef3041e FF |
1205 | |
1206 | err_out: | |
bd2302c2 | 1207 | if (aup->mii_bus != NULL) |
5ef3041e | 1208 | mdiobus_unregister(aup->mii_bus); |
5ef3041e FF |
1209 | |
1210 | /* here we should have a valid dev plus aup-> register addresses | |
1211 | * so we can reset the mac properly.*/ | |
eb049630 | 1212 | au1000_reset_mac(dev); |
5ef3041e FF |
1213 | |
1214 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1215 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1216 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
5ef3041e FF |
1217 | } |
1218 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1219 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1220 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
5ef3041e | 1221 | } |
bd2302c2 FF |
1222 | err_mdiobus_reg: |
1223 | mdiobus_free(aup->mii_bus); | |
1224 | err_mdiobus_alloc: | |
1225 | iounmap(aup->enable); | |
1226 | err_remap2: | |
1227 | iounmap(aup->mac); | |
1228 | err_remap1: | |
5ef3041e FF |
1229 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), |
1230 | (void *)aup->vaddr, aup->dma_addr); | |
bd2302c2 | 1231 | err_vaddr: |
5ef3041e | 1232 | free_netdev(dev); |
bd2302c2 FF |
1233 | err_alloc: |
1234 | release_mem_region(macen->start, resource_size(macen)); | |
1235 | err_request: | |
1236 | release_mem_region(base->start, resource_size(base)); | |
1237 | out: | |
1238 | return err; | |
5ef3041e FF |
1239 | } |
1240 | ||
bd2302c2 | 1241 | static int __devexit au1000_remove(struct platform_device *pdev) |
5ef3041e | 1242 | { |
bd2302c2 FF |
1243 | struct net_device *dev = platform_get_drvdata(pdev); |
1244 | struct au1000_private *aup = netdev_priv(dev); | |
1245 | int i; | |
1246 | struct resource *base, *macen; | |
5ef3041e | 1247 | |
bd2302c2 FF |
1248 | platform_set_drvdata(pdev, NULL); |
1249 | ||
1250 | unregister_netdev(dev); | |
1251 | mdiobus_unregister(aup->mii_bus); | |
1252 | mdiobus_free(aup->mii_bus); | |
1253 | ||
1254 | for (i = 0; i < NUM_RX_DMA; i++) | |
1255 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1256 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
bd2302c2 FF |
1257 | |
1258 | for (i = 0; i < NUM_TX_DMA; i++) | |
1259 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1260 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
bd2302c2 FF |
1261 | |
1262 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1263 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1264 | (void *)aup->vaddr, aup->dma_addr); | |
1265 | ||
1266 | iounmap(aup->mac); | |
1267 | iounmap(aup->enable); | |
1268 | ||
1269 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1270 | release_mem_region(base->start, resource_size(base)); | |
1271 | ||
1272 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1273 | release_mem_region(macen->start, resource_size(macen)); | |
1274 | ||
1275 | free_netdev(dev); | |
5ef3041e | 1276 | |
5ef3041e FF |
1277 | return 0; |
1278 | } | |
1279 | ||
bd2302c2 FF |
1280 | static struct platform_driver au1000_eth_driver = { |
1281 | .probe = au1000_probe, | |
1282 | .remove = __devexit_p(au1000_remove), | |
1283 | .driver = { | |
1284 | .name = "au1000-eth", | |
1285 | .owner = THIS_MODULE, | |
1286 | }, | |
1287 | }; | |
1288 | MODULE_ALIAS("platform:au1000-eth"); | |
1289 | ||
1290 | ||
1291 | static int __init au1000_init_module(void) | |
1292 | { | |
1293 | return platform_driver_register(&au1000_eth_driver); | |
1294 | } | |
1295 | ||
1296 | static void __exit au1000_exit_module(void) | |
5ef3041e | 1297 | { |
bd2302c2 | 1298 | platform_driver_unregister(&au1000_eth_driver); |
5ef3041e FF |
1299 | } |
1300 | ||
1da177e4 | 1301 | module_init(au1000_init_module); |
bd2302c2 | 1302 | module_exit(au1000_exit_module); |