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1da177e4 LT |
1 | #ifndef _B44_H |
2 | #define _B44_H | |
3 | ||
4 | /* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */ | |
5 | #define B44_DEVCTRL 0x0000UL /* Device Control */ | |
6 | #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */ | |
7 | #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */ | |
8 | #define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */ | |
9 | #define DEVCTRL_EPR 0x00008000 /* EPHY Reset */ | |
10 | #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */ | |
11 | #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */ | |
12 | #define DEVCTRL_PADDR 0x0007c000 /* PHY Address */ | |
13 | #define DEVCTRL_PADDR_SHIFT 18 | |
14 | #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ | |
15 | #define B44_WKUP_LEN 0x0010UL /* Wakeup Length */ | |
16 | #define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */ | |
17 | #define WKUP_LEN_D0 0x00000080 | |
18 | #define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */ | |
19 | #define WKUP_LEN_P1_SHIFT 8 | |
20 | #define WKUP_LEN_D1 0x00008000 | |
21 | #define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */ | |
22 | #define WKUP_LEN_P2_SHIFT 16 | |
23 | #define WKUP_LEN_D2 0x00000000 | |
24 | #define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */ | |
25 | #define WKUP_LEN_P3_SHIFT 24 | |
26 | #define WKUP_LEN_D3 0x80000000 | |
27 | #define B44_ISTAT 0x0020UL /* Interrupt Status */ | |
28 | #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */ | |
29 | #define ISTAT_PME 0x00000040 /* Power Management Event */ | |
30 | #define ISTAT_TO 0x00000080 /* General Purpose Timeout */ | |
31 | #define ISTAT_DSCE 0x00000400 /* Descriptor Error */ | |
32 | #define ISTAT_DATAE 0x00000800 /* Data Error */ | |
33 | #define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ | |
34 | #define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ | |
35 | #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ | |
36 | #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ | |
37 | #define ISTAT_RX 0x00010000 /* RX Interrupt */ | |
38 | #define ISTAT_TX 0x01000000 /* TX Interrupt */ | |
39 | #define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ | |
40 | #define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ | |
41 | #define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ | |
42 | #define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|ISTAT_RDU|ISTAT_RFO|ISTAT_TFU) | |
43 | #define B44_IMASK 0x0024UL /* Interrupt Mask */ | |
44 | #define IMASK_DEF (ISTAT_ERRORS | ISTAT_TO | ISTAT_RX | ISTAT_TX) | |
45 | #define B44_GPTIMER 0x0028UL /* General Purpose Timer */ | |
46 | #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */ | |
47 | #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */ | |
48 | #define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */ | |
49 | #define B44_FILT_DATA 0x0094UL /* ENET Filter Data */ | |
50 | #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ | |
51 | #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */ | |
52 | #define B44_MAC_CTRL 0x00A8UL /* MAC Control */ | |
53 | #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ | |
54 | #define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ | |
55 | #define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected */ | |
56 | #define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */ | |
57 | #define MAC_CTRL_PHY_LEDCTRL_SHIFT 5 | |
58 | #define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */ | |
59 | #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */ | |
60 | #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ | |
61 | #define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */ | |
62 | #define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */ | |
63 | #define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */ | |
64 | #define RCV_LAZY_FC_SHIFT 24 | |
65 | #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */ | |
66 | #define DMATX_CTRL_ENABLE 0x00000001 /* Enable */ | |
67 | #define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ | |
68 | #define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ | |
69 | #define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */ | |
70 | #define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */ | |
71 | #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */ | |
72 | #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */ | |
73 | #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */ | |
74 | #define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ | |
75 | #define DMATX_STAT_SMASK 0x0000f000 /* State Mask */ | |
76 | #define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */ | |
77 | #define DMATX_STAT_SACTIVE 0x00001000 /* State Active */ | |
78 | #define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */ | |
79 | #define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */ | |
80 | #define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */ | |
81 | #define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */ | |
82 | #define DMATX_STAT_ENONE 0x00000000 /* Error None */ | |
83 | #define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ | |
84 | #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ | |
85 | #define DMATX_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ | |
86 | #define DMATX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ | |
87 | #define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */ | |
88 | #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */ | |
89 | #define DMARX_CTRL_ENABLE 0x00000001 /* Enable */ | |
90 | #define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ | |
91 | #define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ | |
92 | #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */ | |
93 | #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */ | |
94 | #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */ | |
95 | #define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ | |
96 | #define DMARX_STAT_SMASK 0x0000f000 /* State Mask */ | |
97 | #define DMARX_STAT_SDISABLED 0x00000000 /* State Disbaled */ | |
98 | #define DMARX_STAT_SACTIVE 0x00001000 /* State Active */ | |
99 | #define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */ | |
100 | #define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */ | |
101 | #define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */ | |
102 | #define DMARX_STAT_ENONE 0x00000000 /* Error None */ | |
103 | #define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ | |
104 | #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */ | |
105 | #define DMARX_STAT_EBEBW 0x00030000 /* Error Bus Error on Buffer Write */ | |
106 | #define DMARX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ | |
107 | #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */ | |
108 | #define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */ | |
109 | #define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */ | |
110 | #define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */ | |
111 | #define DMAFIFO_AD_SXDP 0x00010000 /* Select Transmit DMA Pointers */ | |
112 | #define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */ | |
113 | #define DMAFIFO_AD_SRDP 0x00050000 /* Select Receive DMA Pointers */ | |
114 | #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */ | |
115 | #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */ | |
116 | #define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */ | |
117 | #define DMAFIFO_AD_SRFP 0x000c0000 /* Select Receive FIFO Pointers */ | |
118 | #define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */ | |
119 | #define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */ | |
120 | #define B44_RXCONFIG 0x0400UL /* EMAC RX Config */ | |
121 | #define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */ | |
122 | #define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */ | |
123 | #define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Receive Disable While Transmitting */ | |
124 | #define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */ | |
125 | #define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */ | |
126 | #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */ | |
127 | #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ | |
128 | #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */ | |
129 | #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */ | |
130 | #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */ | |
131 | #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */ | |
132 | #define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */ | |
133 | #define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */ | |
134 | #define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */ | |
135 | #define MDIO_DATA_DATA 0x0000ffff /* R/W Data */ | |
136 | #define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */ | |
137 | #define MDIO_DATA_TA_SHIFT 16 | |
138 | #define MDIO_TA_VALID 2 | |
139 | #define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */ | |
140 | #define MDIO_DATA_RA_SHIFT 18 | |
141 | #define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */ | |
142 | #define MDIO_DATA_PMD_SHIFT 23 | |
143 | #define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */ | |
144 | #define MDIO_DATA_OP_SHIFT 28 | |
145 | #define MDIO_OP_WRITE 1 | |
146 | #define MDIO_OP_READ 2 | |
147 | #define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */ | |
148 | #define MDIO_DATA_SB_SHIFT 30 | |
149 | #define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */ | |
150 | #define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */ | |
151 | #define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */ | |
152 | #define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ | |
153 | #define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ | |
154 | #define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ | |
155 | #define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */ | |
156 | #define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */ | |
157 | #define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */ | |
158 | #define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */ | |
159 | #define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */ | |
160 | #define CAM_CTRL_MSEL 0x00000002 /* Mask Select */ | |
161 | #define CAM_CTRL_READ 0x00000004 /* Read */ | |
162 | #define CAM_CTRL_WRITE 0x00000008 /* Read */ | |
163 | #define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */ | |
164 | #define CAM_CTRL_INDEX_SHIFT 16 | |
165 | #define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */ | |
166 | #define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */ | |
167 | #define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */ | |
168 | #define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */ | |
169 | #define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */ | |
170 | #define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */ | |
171 | #define B44_TX_CTRL 0x0430UL /* EMAC TX Control */ | |
172 | #define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */ | |
173 | #define TX_CTRL_FMODE 0x00000002 /* Flow Mode */ | |
174 | #define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */ | |
175 | #define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */ | |
176 | #define B44_TX_WMARK 0x0434UL /* EMAC TX Watermark */ | |
177 | #define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */ | |
178 | #define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */ | |
179 | #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */ | |
180 | #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */ | |
181 | #define B44_TX_O 0x0508UL /* MIB TX Octets */ | |
182 | #define B44_TX_P 0x050CUL /* MIB TX Packets */ | |
183 | #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */ | |
184 | #define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */ | |
185 | #define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */ | |
186 | #define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */ | |
187 | #define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */ | |
188 | #define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */ | |
189 | #define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */ | |
190 | #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */ | |
191 | #define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */ | |
192 | #define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */ | |
193 | #define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */ | |
194 | #define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */ | |
195 | #define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */ | |
196 | #define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */ | |
197 | #define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */ | |
198 | #define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */ | |
199 | #define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */ | |
200 | #define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */ | |
201 | #define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */ | |
202 | #define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */ | |
203 | #define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */ | |
204 | #define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */ | |
205 | #define B44_RX_O 0x0588UL /* MIB RX Octets */ | |
206 | #define B44_RX_P 0x058CUL /* MIB RX Packets */ | |
207 | #define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */ | |
208 | #define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */ | |
209 | #define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */ | |
210 | #define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */ | |
211 | #define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */ | |
212 | #define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */ | |
213 | #define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */ | |
214 | #define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */ | |
215 | #define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */ | |
216 | #define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */ | |
217 | #define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */ | |
218 | #define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */ | |
219 | #define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */ | |
220 | #define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */ | |
221 | #define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */ | |
222 | #define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */ | |
223 | #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */ | |
224 | #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */ | |
225 | #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */ | |
226 | ||
227 | /* Silicon backplane register definitions */ | |
228 | #define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */ | |
229 | #define SBIMSTATE_PC 0x0000000f /* Pipe Count */ | |
230 | #define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ | |
231 | #define SBIMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */ | |
232 | #define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */ | |
233 | #define SBIMSTATE_AP_TK 0x00000020 /* Use token only */ | |
234 | #define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */ | |
235 | #define SBIMSTATE_IBE 0x00020000 /* In Band Error */ | |
236 | #define SBIMSTATE_TO 0x00040000 /* Timeout */ | |
237 | #define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */ | |
238 | #define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ | |
239 | #define SBINTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ | |
240 | #define SBINTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ | |
241 | #define SBINTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ | |
242 | #define SBINTVEC_USB 0x00000010 /* Enable interrupts for usb */ | |
243 | #define SBINTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ | |
244 | #define SBINTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ | |
245 | #define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */ | |
246 | #define SBTMSLOW_RESET 0x00000001 /* Reset */ | |
247 | #define SBTMSLOW_REJECT 0x00000002 /* Reject */ | |
248 | #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ | |
249 | #define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ | |
250 | #define SBTMSLOW_PE 0x40000000 /* Power Management Enable */ | |
251 | #define SBTMSLOW_BE 0x80000000 /* BIST Enable */ | |
252 | #define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */ | |
253 | #define SBTMSHIGH_SERR 0x00000001 /* S-error */ | |
254 | #define SBTMSHIGH_INT 0x00000002 /* Interrupt */ | |
255 | #define SBTMSHIGH_BUSY 0x00000004 /* Busy */ | |
256 | #define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */ | |
257 | #define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */ | |
258 | #define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */ | |
259 | #define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */ | |
260 | #define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */ | |
261 | #define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */ | |
262 | #define SBIDHIGH_CC_SHIFT 4 | |
263 | #define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */ | |
264 | #define SBIDHIGH_VC_SHIFT 16 | |
265 | ||
266 | /* SSB PCI config space registers. */ | |
267 | #define SSB_BAR0_WIN 0x80 | |
268 | #define SSB_BAR1_WIN 0x84 | |
269 | #define SSB_SPROM_CONTROL 0x88 | |
270 | #define SSB_BAR1_CONTROL 0x8c | |
271 | ||
272 | /* SSB core and host control registers. */ | |
273 | #define SSB_CONTROL 0x0000UL | |
274 | #define SSB_ARBCONTROL 0x0010UL | |
275 | #define SSB_ISTAT 0x0020UL | |
276 | #define SSB_IMASK 0x0024UL | |
277 | #define SSB_MBOX 0x0028UL | |
278 | #define SSB_BCAST_ADDR 0x0050UL | |
279 | #define SSB_BCAST_DATA 0x0054UL | |
280 | #define SSB_PCI_TRANS_0 0x0100UL | |
281 | #define SSB_PCI_TRANS_1 0x0104UL | |
282 | #define SSB_PCI_TRANS_2 0x0108UL | |
283 | #define SSB_SPROM 0x0800UL | |
284 | ||
285 | #define SSB_PCI_MEM 0x00000000 | |
286 | #define SSB_PCI_IO 0x00000001 | |
287 | #define SSB_PCI_CFG0 0x00000002 | |
288 | #define SSB_PCI_CFG1 0x00000003 | |
289 | #define SSB_PCI_PREF 0x00000004 | |
290 | #define SSB_PCI_BURST 0x00000008 | |
291 | #define SSB_PCI_MASK0 0xfc000000 | |
292 | #define SSB_PCI_MASK1 0xfc000000 | |
293 | #define SSB_PCI_MASK2 0xc0000000 | |
294 | ||
295 | /* 4400 PHY registers */ | |
296 | #define B44_MII_AUXCTRL 24 /* Auxiliary Control */ | |
297 | #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ | |
298 | #define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */ | |
299 | #define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */ | |
300 | #define B44_MII_ALEDCTRL 26 /* Activity LED */ | |
301 | #define MII_ALEDCTRL_ALLMSK 0x7fff | |
302 | #define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */ | |
303 | #define MII_TLEDCTRL_ENABLE 0x0040 | |
304 | ||
305 | struct dma_desc { | |
306 | u32 ctrl; | |
307 | u32 addr; | |
308 | }; | |
309 | ||
310 | /* There are only 12 bits in the DMA engine for descriptor offsetting | |
311 | * so the table must be aligned on a boundary of this. | |
312 | */ | |
313 | #define DMA_TABLE_BYTES 4096 | |
314 | ||
315 | #define DESC_CTRL_LEN 0x00001fff | |
316 | #define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */ | |
317 | #define DESC_CTRL_EOT 0x10000000 /* End of Table */ | |
318 | #define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */ | |
319 | #define DESC_CTRL_EOF 0x40000000 /* End of Frame */ | |
320 | #define DESC_CTRL_SOF 0x80000000 /* Start of Frame */ | |
321 | ||
322 | #define RX_COPY_THRESHOLD 256 | |
323 | ||
324 | struct rx_header { | |
325 | u16 len; | |
326 | u16 flags; | |
327 | u16 pad[12]; | |
328 | }; | |
329 | #define RX_HEADER_LEN 28 | |
330 | ||
331 | #define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ | |
332 | #define RX_FLAG_CRCERR 0x00000002 /* CRC Error */ | |
333 | #define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ | |
334 | #define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ | |
335 | #define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ | |
336 | #define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ | |
337 | #define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ | |
338 | #define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ | |
339 | #define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ | |
340 | #define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR | RX_FLAG_CRCERR | RX_FLAG_OFIFO) | |
341 | ||
342 | struct ring_info { | |
343 | struct sk_buff *skb; | |
344 | DECLARE_PCI_UNMAP_ADDR(mapping); | |
345 | }; | |
346 | ||
347 | #define B44_MCAST_TABLE_SIZE 32 | |
348 | ||
349 | /* SW copy of device statistics, kept up to date by periodic timer | |
350 | * which probes HW values. Must have same relative layout as HW | |
351 | * register above, because b44_stats_update depends upon this. | |
352 | */ | |
353 | struct b44_hw_stats { | |
354 | u32 tx_good_octets, tx_good_pkts, tx_octets; | |
355 | u32 tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; | |
356 | u32 tx_len_64, tx_len_65_to_127, tx_len_128_to_255; | |
357 | u32 tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; | |
358 | u32 tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; | |
359 | u32 tx_underruns, tx_total_cols, tx_single_cols; | |
360 | u32 tx_multiple_cols, tx_excessive_cols, tx_late_cols; | |
361 | u32 tx_defered, tx_carrier_lost, tx_pause_pkts; | |
362 | u32 __pad1[8]; | |
363 | ||
364 | u32 rx_good_octets, rx_good_pkts, rx_octets; | |
365 | u32 rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; | |
366 | u32 rx_len_64, rx_len_65_to_127, rx_len_128_to_255; | |
367 | u32 rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; | |
368 | u32 rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; | |
369 | u32 rx_missed_pkts, rx_crc_align_errs, rx_undersize; | |
370 | u32 rx_crc_errs, rx_align_errs, rx_symbol_errs; | |
371 | u32 rx_pause_pkts, rx_nonpause_pkts; | |
372 | }; | |
373 | ||
374 | struct b44 { | |
375 | spinlock_t lock; | |
376 | ||
377 | u32 imask, istat; | |
378 | ||
379 | struct dma_desc *rx_ring, *tx_ring; | |
380 | ||
381 | u32 tx_prod, tx_cons; | |
382 | u32 rx_prod, rx_cons; | |
383 | ||
384 | struct ring_info *rx_buffers; | |
385 | struct ring_info *tx_buffers; | |
386 | ||
387 | u32 dma_offset; | |
388 | u32 flags; | |
389 | #define B44_FLAG_INIT_COMPLETE 0x00000001 | |
390 | #define B44_FLAG_BUGGY_TXPTR 0x00000002 | |
391 | #define B44_FLAG_REORDER_BUG 0x00000004 | |
392 | #define B44_FLAG_PAUSE_AUTO 0x00008000 | |
393 | #define B44_FLAG_FULL_DUPLEX 0x00010000 | |
394 | #define B44_FLAG_100_BASE_T 0x00020000 | |
395 | #define B44_FLAG_TX_PAUSE 0x00040000 | |
396 | #define B44_FLAG_RX_PAUSE 0x00080000 | |
397 | #define B44_FLAG_FORCE_LINK 0x00100000 | |
398 | #define B44_FLAG_ADV_10HALF 0x01000000 | |
399 | #define B44_FLAG_ADV_10FULL 0x02000000 | |
400 | #define B44_FLAG_ADV_100HALF 0x04000000 | |
401 | #define B44_FLAG_ADV_100FULL 0x08000000 | |
402 | #define B44_FLAG_INTERNAL_PHY 0x10000000 | |
403 | ||
404 | u32 rx_offset; | |
405 | ||
406 | u32 msg_enable; | |
407 | ||
408 | struct timer_list timer; | |
409 | ||
410 | struct net_device_stats stats; | |
411 | struct b44_hw_stats hw_stats; | |
412 | ||
413 | void __iomem *regs; | |
414 | struct pci_dev *pdev; | |
415 | struct net_device *dev; | |
416 | ||
417 | dma_addr_t rx_ring_dma, tx_ring_dma; | |
418 | ||
419 | u32 rx_pending; | |
420 | u32 tx_pending; | |
421 | u8 phy_addr; | |
422 | u8 core_unit; | |
423 | ||
424 | struct mii_if_info mii_if; | |
425 | }; | |
426 | ||
427 | #endif /* _B44_H */ |