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6b7c5b94 SP |
1 | /* |
2 | * Copyright (C) 2005 - 2009 ServerEngines | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | #include "be.h" | |
8788fdc2 | 19 | #include "be_cmds.h" |
6b7c5b94 | 20 | |
8788fdc2 | 21 | static void be_mcc_notify(struct be_adapter *adapter) |
5fb379ee | 22 | { |
8788fdc2 | 23 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
5fb379ee SP |
24 | u32 val = 0; |
25 | ||
26 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | |
27 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
8788fdc2 | 28 | iowrite32(val, adapter->db + DB_MCCQ_OFFSET); |
5fb379ee SP |
29 | } |
30 | ||
31 | /* To check if valid bit is set, check the entire word as we don't know | |
32 | * the endianness of the data (old entry is host endian while a new entry is | |
33 | * little endian) */ | |
efd2e40a | 34 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) |
5fb379ee SP |
35 | { |
36 | if (compl->flags != 0) { | |
37 | compl->flags = le32_to_cpu(compl->flags); | |
38 | BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); | |
39 | return true; | |
40 | } else { | |
41 | return false; | |
42 | } | |
43 | } | |
44 | ||
45 | /* Need to reset the entire word that houses the valid bit */ | |
efd2e40a | 46 | static inline void be_mcc_compl_use(struct be_mcc_compl *compl) |
5fb379ee SP |
47 | { |
48 | compl->flags = 0; | |
49 | } | |
50 | ||
8788fdc2 | 51 | static int be_mcc_compl_process(struct be_adapter *adapter, |
efd2e40a | 52 | struct be_mcc_compl *compl) |
5fb379ee SP |
53 | { |
54 | u16 compl_status, extd_status; | |
55 | ||
56 | /* Just swap the status to host endian; mcc tag is opaquely copied | |
57 | * from mcc_wrb */ | |
58 | be_dws_le_to_cpu(compl, 4); | |
59 | ||
60 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & | |
61 | CQE_STATUS_COMPL_MASK; | |
b31c50a7 SP |
62 | if (compl_status == MCC_STATUS_SUCCESS) { |
63 | if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) { | |
64 | struct be_cmd_resp_get_stats *resp = | |
65 | adapter->stats.cmd.va; | |
66 | be_dws_le_to_cpu(&resp->hw_stats, | |
67 | sizeof(resp->hw_stats)); | |
68 | netdev_stats_update(adapter); | |
69 | } | |
70 | } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) { | |
5fb379ee SP |
71 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & |
72 | CQE_STATUS_EXTD_MASK; | |
5f0b849e | 73 | dev_warn(&adapter->pdev->dev, |
d744b44e AK |
74 | "Error in cmd completion - opcode %d, compl %d, extd %d\n", |
75 | compl->tag0, compl_status, extd_status); | |
5fb379ee | 76 | } |
b31c50a7 | 77 | return compl_status; |
5fb379ee SP |
78 | } |
79 | ||
a8f447bd | 80 | /* Link state evt is a string of bytes; no need for endian swapping */ |
8788fdc2 | 81 | static void be_async_link_state_process(struct be_adapter *adapter, |
a8f447bd SP |
82 | struct be_async_event_link_state *evt) |
83 | { | |
8788fdc2 SP |
84 | be_link_status_update(adapter, |
85 | evt->port_link_status == ASYNC_EVENT_LINK_UP); | |
a8f447bd SP |
86 | } |
87 | ||
88 | static inline bool is_link_state_evt(u32 trailer) | |
89 | { | |
90 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | |
91 | ASYNC_TRAILER_EVENT_CODE_MASK) == | |
92 | ASYNC_EVENT_CODE_LINK_STATE); | |
93 | } | |
5fb379ee | 94 | |
efd2e40a | 95 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) |
5fb379ee | 96 | { |
8788fdc2 | 97 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
efd2e40a | 98 | struct be_mcc_compl *compl = queue_tail_node(mcc_cq); |
5fb379ee SP |
99 | |
100 | if (be_mcc_compl_is_new(compl)) { | |
101 | queue_tail_inc(mcc_cq); | |
102 | return compl; | |
103 | } | |
104 | return NULL; | |
105 | } | |
106 | ||
7a1e9b20 SP |
107 | void be_async_mcc_enable(struct be_adapter *adapter) |
108 | { | |
109 | spin_lock_bh(&adapter->mcc_cq_lock); | |
110 | ||
111 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); | |
112 | adapter->mcc_obj.rearm_cq = true; | |
113 | ||
114 | spin_unlock_bh(&adapter->mcc_cq_lock); | |
115 | } | |
116 | ||
117 | void be_async_mcc_disable(struct be_adapter *adapter) | |
118 | { | |
119 | adapter->mcc_obj.rearm_cq = false; | |
120 | } | |
121 | ||
b31c50a7 | 122 | int be_process_mcc(struct be_adapter *adapter) |
5fb379ee | 123 | { |
efd2e40a | 124 | struct be_mcc_compl *compl; |
b31c50a7 | 125 | int num = 0, status = 0; |
7a1e9b20 | 126 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; |
5fb379ee | 127 | |
8788fdc2 SP |
128 | spin_lock_bh(&adapter->mcc_cq_lock); |
129 | while ((compl = be_mcc_compl_get(adapter))) { | |
a8f447bd SP |
130 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { |
131 | /* Interpret flags as an async trailer */ | |
132 | BUG_ON(!is_link_state_evt(compl->flags)); | |
133 | ||
134 | /* Interpret compl as a async link evt */ | |
8788fdc2 | 135 | be_async_link_state_process(adapter, |
a8f447bd | 136 | (struct be_async_event_link_state *) compl); |
b31c50a7 SP |
137 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
138 | status = be_mcc_compl_process(adapter, compl); | |
7a1e9b20 | 139 | atomic_dec(&mcc_obj->q.used); |
5fb379ee SP |
140 | } |
141 | be_mcc_compl_use(compl); | |
142 | num++; | |
143 | } | |
b31c50a7 | 144 | |
5fb379ee | 145 | if (num) |
7a1e9b20 | 146 | be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); |
b31c50a7 | 147 | |
8788fdc2 | 148 | spin_unlock_bh(&adapter->mcc_cq_lock); |
b31c50a7 | 149 | return status; |
5fb379ee SP |
150 | } |
151 | ||
6ac7b687 | 152 | /* Wait till no more pending mcc requests are present */ |
b31c50a7 | 153 | static int be_mcc_wait_compl(struct be_adapter *adapter) |
6ac7b687 | 154 | { |
b31c50a7 SP |
155 | #define mcc_timeout 120000 /* 12s timeout */ |
156 | int i, status; | |
6ac7b687 | 157 | for (i = 0; i < mcc_timeout; i++) { |
b31c50a7 SP |
158 | status = be_process_mcc(adapter); |
159 | if (status) | |
160 | return status; | |
161 | ||
8788fdc2 | 162 | if (atomic_read(&adapter->mcc_obj.q.used) == 0) |
6ac7b687 SP |
163 | break; |
164 | udelay(100); | |
165 | } | |
b31c50a7 | 166 | if (i == mcc_timeout) { |
5f0b849e | 167 | dev_err(&adapter->pdev->dev, "mccq poll timed out\n"); |
b31c50a7 SP |
168 | return -1; |
169 | } | |
170 | return 0; | |
6ac7b687 SP |
171 | } |
172 | ||
173 | /* Notify MCC requests and wait for completion */ | |
b31c50a7 | 174 | static int be_mcc_notify_wait(struct be_adapter *adapter) |
6ac7b687 | 175 | { |
8788fdc2 | 176 | be_mcc_notify(adapter); |
b31c50a7 | 177 | return be_mcc_wait_compl(adapter); |
6ac7b687 SP |
178 | } |
179 | ||
5f0b849e | 180 | static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) |
6b7c5b94 SP |
181 | { |
182 | int cnt = 0, wait = 5; | |
183 | u32 ready; | |
184 | ||
185 | do { | |
cf588477 SP |
186 | ready = ioread32(db); |
187 | if (ready == 0xffffffff) { | |
188 | dev_err(&adapter->pdev->dev, | |
189 | "pci slot disconnected\n"); | |
190 | return -1; | |
191 | } | |
192 | ||
193 | ready &= MPU_MAILBOX_DB_RDY_MASK; | |
6b7c5b94 SP |
194 | if (ready) |
195 | break; | |
196 | ||
84517482 | 197 | if (cnt > 4000000) { |
5f0b849e | 198 | dev_err(&adapter->pdev->dev, "mbox poll timed out\n"); |
6b7c5b94 SP |
199 | return -1; |
200 | } | |
201 | ||
202 | if (cnt > 50) | |
203 | wait = 200; | |
204 | cnt += wait; | |
205 | udelay(wait); | |
206 | } while (true); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | /* | |
212 | * Insert the mailbox address into the doorbell in two steps | |
5fb379ee | 213 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs |
6b7c5b94 | 214 | */ |
b31c50a7 | 215 | static int be_mbox_notify_wait(struct be_adapter *adapter) |
6b7c5b94 SP |
216 | { |
217 | int status; | |
6b7c5b94 | 218 | u32 val = 0; |
8788fdc2 SP |
219 | void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; |
220 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; | |
6b7c5b94 | 221 | struct be_mcc_mailbox *mbox = mbox_mem->va; |
efd2e40a | 222 | struct be_mcc_compl *compl = &mbox->compl; |
6b7c5b94 | 223 | |
cf588477 SP |
224 | /* wait for ready to be set */ |
225 | status = be_mbox_db_ready_wait(adapter, db); | |
226 | if (status != 0) | |
227 | return status; | |
228 | ||
6b7c5b94 SP |
229 | val |= MPU_MAILBOX_DB_HI_MASK; |
230 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | |
231 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
232 | iowrite32(val, db); | |
233 | ||
234 | /* wait for ready to be set */ | |
5f0b849e | 235 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
236 | if (status != 0) |
237 | return status; | |
238 | ||
239 | val = 0; | |
6b7c5b94 SP |
240 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ |
241 | val |= (u32)(mbox_mem->dma >> 4) << 2; | |
242 | iowrite32(val, db); | |
243 | ||
5f0b849e | 244 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
245 | if (status != 0) |
246 | return status; | |
247 | ||
5fb379ee | 248 | /* A cq entry has been made now */ |
efd2e40a SP |
249 | if (be_mcc_compl_is_new(compl)) { |
250 | status = be_mcc_compl_process(adapter, &mbox->compl); | |
251 | be_mcc_compl_use(compl); | |
5fb379ee SP |
252 | if (status) |
253 | return status; | |
254 | } else { | |
5f0b849e | 255 | dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); |
6b7c5b94 SP |
256 | return -1; |
257 | } | |
5fb379ee | 258 | return 0; |
6b7c5b94 SP |
259 | } |
260 | ||
8788fdc2 | 261 | static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage) |
6b7c5b94 | 262 | { |
8788fdc2 | 263 | u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET); |
6b7c5b94 SP |
264 | |
265 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | |
266 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | |
267 | return -1; | |
268 | else | |
269 | return 0; | |
270 | } | |
271 | ||
8788fdc2 | 272 | int be_cmd_POST(struct be_adapter *adapter) |
6b7c5b94 | 273 | { |
43a04fdc SP |
274 | u16 stage; |
275 | int status, timeout = 0; | |
6b7c5b94 | 276 | |
43a04fdc SP |
277 | do { |
278 | status = be_POST_stage_get(adapter, &stage); | |
279 | if (status) { | |
280 | dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n", | |
281 | stage); | |
282 | return -1; | |
283 | } else if (stage != POST_STAGE_ARMFW_RDY) { | |
284 | set_current_state(TASK_INTERRUPTIBLE); | |
285 | schedule_timeout(2 * HZ); | |
286 | timeout += 2; | |
287 | } else { | |
288 | return 0; | |
289 | } | |
290 | } while (timeout < 20); | |
6b7c5b94 | 291 | |
43a04fdc SP |
292 | dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage); |
293 | return -1; | |
6b7c5b94 SP |
294 | } |
295 | ||
296 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) | |
297 | { | |
298 | return wrb->payload.embedded_payload; | |
299 | } | |
300 | ||
301 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | |
302 | { | |
303 | return &wrb->payload.sgl[0]; | |
304 | } | |
305 | ||
306 | /* Don't touch the hdr after it's prepared */ | |
307 | static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | |
d744b44e | 308 | bool embedded, u8 sge_cnt, u32 opcode) |
6b7c5b94 SP |
309 | { |
310 | if (embedded) | |
311 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
312 | else | |
313 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | |
314 | MCC_WRB_SGE_CNT_SHIFT; | |
315 | wrb->payload_length = payload_len; | |
d744b44e | 316 | wrb->tag0 = opcode; |
fa4281bb | 317 | be_dws_cpu_to_le(wrb, 8); |
6b7c5b94 SP |
318 | } |
319 | ||
320 | /* Don't touch the hdr after it's prepared */ | |
321 | static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
322 | u8 subsystem, u8 opcode, int cmd_len) | |
323 | { | |
324 | req_hdr->opcode = opcode; | |
325 | req_hdr->subsystem = subsystem; | |
326 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
07793d33 | 327 | req_hdr->version = 0; |
6b7c5b94 SP |
328 | } |
329 | ||
330 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
331 | struct be_dma_mem *mem) | |
332 | { | |
333 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
334 | u64 dma = (u64)mem->dma; | |
335 | ||
336 | for (i = 0; i < buf_pages; i++) { | |
337 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
338 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
339 | dma += PAGE_SIZE_4K; | |
340 | } | |
341 | } | |
342 | ||
343 | /* Converts interrupt delay in microseconds to multiplier value */ | |
344 | static u32 eq_delay_to_mult(u32 usec_delay) | |
345 | { | |
346 | #define MAX_INTR_RATE 651042 | |
347 | const u32 round = 10; | |
348 | u32 multiplier; | |
349 | ||
350 | if (usec_delay == 0) | |
351 | multiplier = 0; | |
352 | else { | |
353 | u32 interrupt_rate = 1000000 / usec_delay; | |
354 | /* Max delay, corresponding to the lowest interrupt rate */ | |
355 | if (interrupt_rate == 0) | |
356 | multiplier = 1023; | |
357 | else { | |
358 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
359 | multiplier /= interrupt_rate; | |
360 | /* Round the multiplier to the closest value.*/ | |
361 | multiplier = (multiplier + round/2) / round; | |
362 | multiplier = min(multiplier, (u32)1023); | |
363 | } | |
364 | } | |
365 | return multiplier; | |
366 | } | |
367 | ||
b31c50a7 | 368 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) |
6b7c5b94 | 369 | { |
b31c50a7 SP |
370 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; |
371 | struct be_mcc_wrb *wrb | |
372 | = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
373 | memset(wrb, 0, sizeof(*wrb)); | |
374 | return wrb; | |
6b7c5b94 SP |
375 | } |
376 | ||
b31c50a7 | 377 | static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) |
5fb379ee | 378 | { |
b31c50a7 SP |
379 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
380 | struct be_mcc_wrb *wrb; | |
381 | ||
713d0394 SP |
382 | if (atomic_read(&mccq->used) >= mccq->len) { |
383 | dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n"); | |
384 | return NULL; | |
385 | } | |
386 | ||
b31c50a7 SP |
387 | wrb = queue_head_node(mccq); |
388 | queue_head_inc(mccq); | |
389 | atomic_inc(&mccq->used); | |
390 | memset(wrb, 0, sizeof(*wrb)); | |
5fb379ee SP |
391 | return wrb; |
392 | } | |
393 | ||
2243e2e9 SP |
394 | /* Tell fw we're about to start firing cmds by writing a |
395 | * special pattern across the wrb hdr; uses mbox | |
396 | */ | |
397 | int be_cmd_fw_init(struct be_adapter *adapter) | |
398 | { | |
399 | u8 *wrb; | |
400 | int status; | |
401 | ||
402 | spin_lock(&adapter->mbox_lock); | |
403 | ||
404 | wrb = (u8 *)wrb_from_mbox(adapter); | |
405 | *wrb++ = 0xFF; | |
406 | *wrb++ = 0x12; | |
407 | *wrb++ = 0x34; | |
408 | *wrb++ = 0xFF; | |
409 | *wrb++ = 0xFF; | |
410 | *wrb++ = 0x56; | |
411 | *wrb++ = 0x78; | |
412 | *wrb = 0xFF; | |
413 | ||
414 | status = be_mbox_notify_wait(adapter); | |
415 | ||
416 | spin_unlock(&adapter->mbox_lock); | |
417 | return status; | |
418 | } | |
419 | ||
420 | /* Tell fw we're done with firing cmds by writing a | |
421 | * special pattern across the wrb hdr; uses mbox | |
422 | */ | |
423 | int be_cmd_fw_clean(struct be_adapter *adapter) | |
424 | { | |
425 | u8 *wrb; | |
426 | int status; | |
427 | ||
cf588477 SP |
428 | if (adapter->eeh_err) |
429 | return -EIO; | |
430 | ||
2243e2e9 SP |
431 | spin_lock(&adapter->mbox_lock); |
432 | ||
433 | wrb = (u8 *)wrb_from_mbox(adapter); | |
434 | *wrb++ = 0xFF; | |
435 | *wrb++ = 0xAA; | |
436 | *wrb++ = 0xBB; | |
437 | *wrb++ = 0xFF; | |
438 | *wrb++ = 0xFF; | |
439 | *wrb++ = 0xCC; | |
440 | *wrb++ = 0xDD; | |
441 | *wrb = 0xFF; | |
442 | ||
443 | status = be_mbox_notify_wait(adapter); | |
444 | ||
445 | spin_unlock(&adapter->mbox_lock); | |
446 | return status; | |
447 | } | |
8788fdc2 | 448 | int be_cmd_eq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
449 | struct be_queue_info *eq, int eq_delay) |
450 | { | |
b31c50a7 SP |
451 | struct be_mcc_wrb *wrb; |
452 | struct be_cmd_req_eq_create *req; | |
6b7c5b94 SP |
453 | struct be_dma_mem *q_mem = &eq->dma_mem; |
454 | int status; | |
455 | ||
8788fdc2 | 456 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
457 | |
458 | wrb = wrb_from_mbox(adapter); | |
459 | req = embedded_payload(wrb); | |
6b7c5b94 | 460 | |
d744b44e | 461 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE); |
6b7c5b94 SP |
462 | |
463 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
464 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | |
465 | ||
466 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
467 | ||
468 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, | |
eec368fb | 469 | be_pci_func(adapter)); |
6b7c5b94 SP |
470 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); |
471 | /* 4byte eqe*/ | |
472 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
473 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
474 | __ilog2_u32(eq->len/256)); | |
475 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
476 | eq_delay_to_mult(eq_delay)); | |
477 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
478 | ||
479 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
480 | ||
b31c50a7 | 481 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 482 | if (!status) { |
b31c50a7 | 483 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
484 | eq->id = le16_to_cpu(resp->eq_id); |
485 | eq->created = true; | |
486 | } | |
b31c50a7 | 487 | |
8788fdc2 | 488 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
489 | return status; |
490 | } | |
491 | ||
b31c50a7 | 492 | /* Uses mbox */ |
8788fdc2 | 493 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
494 | u8 type, bool permanent, u32 if_handle) |
495 | { | |
b31c50a7 SP |
496 | struct be_mcc_wrb *wrb; |
497 | struct be_cmd_req_mac_query *req; | |
6b7c5b94 SP |
498 | int status; |
499 | ||
8788fdc2 | 500 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
501 | |
502 | wrb = wrb_from_mbox(adapter); | |
503 | req = embedded_payload(wrb); | |
6b7c5b94 | 504 | |
d744b44e AK |
505 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
506 | OPCODE_COMMON_NTWK_MAC_QUERY); | |
6b7c5b94 SP |
507 | |
508 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
509 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); | |
510 | ||
511 | req->type = type; | |
512 | if (permanent) { | |
513 | req->permanent = 1; | |
514 | } else { | |
b31c50a7 | 515 | req->if_id = cpu_to_le16((u16) if_handle); |
6b7c5b94 SP |
516 | req->permanent = 0; |
517 | } | |
518 | ||
b31c50a7 SP |
519 | status = be_mbox_notify_wait(adapter); |
520 | if (!status) { | |
521 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | |
6b7c5b94 | 522 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); |
b31c50a7 | 523 | } |
6b7c5b94 | 524 | |
8788fdc2 | 525 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
526 | return status; |
527 | } | |
528 | ||
b31c50a7 | 529 | /* Uses synchronous MCCQ */ |
8788fdc2 | 530 | int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
531 | u32 if_id, u32 *pmac_id) |
532 | { | |
b31c50a7 SP |
533 | struct be_mcc_wrb *wrb; |
534 | struct be_cmd_req_pmac_add *req; | |
6b7c5b94 SP |
535 | int status; |
536 | ||
b31c50a7 SP |
537 | spin_lock_bh(&adapter->mcc_lock); |
538 | ||
539 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
540 | if (!wrb) { |
541 | status = -EBUSY; | |
542 | goto err; | |
543 | } | |
b31c50a7 | 544 | req = embedded_payload(wrb); |
6b7c5b94 | 545 | |
d744b44e AK |
546 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
547 | OPCODE_COMMON_NTWK_PMAC_ADD); | |
6b7c5b94 SP |
548 | |
549 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
550 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); | |
551 | ||
552 | req->if_id = cpu_to_le32(if_id); | |
553 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | |
554 | ||
b31c50a7 | 555 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
556 | if (!status) { |
557 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | |
558 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
559 | } | |
560 | ||
713d0394 | 561 | err: |
b31c50a7 | 562 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
563 | return status; |
564 | } | |
565 | ||
b31c50a7 | 566 | /* Uses synchronous MCCQ */ |
8788fdc2 | 567 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id) |
6b7c5b94 | 568 | { |
b31c50a7 SP |
569 | struct be_mcc_wrb *wrb; |
570 | struct be_cmd_req_pmac_del *req; | |
6b7c5b94 SP |
571 | int status; |
572 | ||
b31c50a7 SP |
573 | spin_lock_bh(&adapter->mcc_lock); |
574 | ||
575 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
576 | if (!wrb) { |
577 | status = -EBUSY; | |
578 | goto err; | |
579 | } | |
b31c50a7 | 580 | req = embedded_payload(wrb); |
6b7c5b94 | 581 | |
d744b44e AK |
582 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
583 | OPCODE_COMMON_NTWK_PMAC_DEL); | |
6b7c5b94 SP |
584 | |
585 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
586 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); | |
587 | ||
588 | req->if_id = cpu_to_le32(if_id); | |
589 | req->pmac_id = cpu_to_le32(pmac_id); | |
590 | ||
b31c50a7 SP |
591 | status = be_mcc_notify_wait(adapter); |
592 | ||
713d0394 | 593 | err: |
b31c50a7 | 594 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
595 | return status; |
596 | } | |
597 | ||
b31c50a7 | 598 | /* Uses Mbox */ |
8788fdc2 | 599 | int be_cmd_cq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
600 | struct be_queue_info *cq, struct be_queue_info *eq, |
601 | bool sol_evts, bool no_delay, int coalesce_wm) | |
602 | { | |
b31c50a7 SP |
603 | struct be_mcc_wrb *wrb; |
604 | struct be_cmd_req_cq_create *req; | |
6b7c5b94 | 605 | struct be_dma_mem *q_mem = &cq->dma_mem; |
b31c50a7 | 606 | void *ctxt; |
6b7c5b94 SP |
607 | int status; |
608 | ||
8788fdc2 | 609 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
610 | |
611 | wrb = wrb_from_mbox(adapter); | |
612 | req = embedded_payload(wrb); | |
613 | ctxt = &req->context; | |
6b7c5b94 | 614 | |
d744b44e AK |
615 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
616 | OPCODE_COMMON_CQ_CREATE); | |
6b7c5b94 SP |
617 | |
618 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
619 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | |
620 | ||
621 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
622 | ||
623 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm); | |
624 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | |
625 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | |
626 | __ilog2_u32(cq->len/256)); | |
627 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | |
628 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | |
629 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | |
630 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | |
5fb379ee | 631 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); |
eec368fb | 632 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter)); |
6b7c5b94 SP |
633 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
634 | ||
635 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
636 | ||
b31c50a7 | 637 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 638 | if (!status) { |
b31c50a7 | 639 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
640 | cq->id = le16_to_cpu(resp->cq_id); |
641 | cq->created = true; | |
642 | } | |
b31c50a7 | 643 | |
8788fdc2 | 644 | spin_unlock(&adapter->mbox_lock); |
5fb379ee SP |
645 | |
646 | return status; | |
647 | } | |
648 | ||
649 | static u32 be_encoded_q_len(int q_len) | |
650 | { | |
651 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
652 | if (len_encoded == 16) | |
653 | len_encoded = 0; | |
654 | return len_encoded; | |
655 | } | |
656 | ||
8788fdc2 | 657 | int be_cmd_mccq_create(struct be_adapter *adapter, |
5fb379ee SP |
658 | struct be_queue_info *mccq, |
659 | struct be_queue_info *cq) | |
660 | { | |
b31c50a7 SP |
661 | struct be_mcc_wrb *wrb; |
662 | struct be_cmd_req_mcc_create *req; | |
5fb379ee | 663 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
b31c50a7 | 664 | void *ctxt; |
5fb379ee SP |
665 | int status; |
666 | ||
8788fdc2 | 667 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
668 | |
669 | wrb = wrb_from_mbox(adapter); | |
670 | req = embedded_payload(wrb); | |
671 | ctxt = &req->context; | |
5fb379ee | 672 | |
d744b44e AK |
673 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
674 | OPCODE_COMMON_MCC_CREATE); | |
5fb379ee SP |
675 | |
676 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
677 | OPCODE_COMMON_MCC_CREATE, sizeof(*req)); | |
678 | ||
679 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
680 | ||
eec368fb | 681 | AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter)); |
5fb379ee SP |
682 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); |
683 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | |
684 | be_encoded_q_len(mccq->len)); | |
685 | AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); | |
686 | ||
687 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
688 | ||
689 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
690 | ||
b31c50a7 | 691 | status = be_mbox_notify_wait(adapter); |
5fb379ee SP |
692 | if (!status) { |
693 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
694 | mccq->id = le16_to_cpu(resp->id); | |
695 | mccq->created = true; | |
696 | } | |
8788fdc2 | 697 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
698 | |
699 | return status; | |
700 | } | |
701 | ||
8788fdc2 | 702 | int be_cmd_txq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
703 | struct be_queue_info *txq, |
704 | struct be_queue_info *cq) | |
705 | { | |
b31c50a7 SP |
706 | struct be_mcc_wrb *wrb; |
707 | struct be_cmd_req_eth_tx_create *req; | |
6b7c5b94 | 708 | struct be_dma_mem *q_mem = &txq->dma_mem; |
b31c50a7 | 709 | void *ctxt; |
6b7c5b94 | 710 | int status; |
6b7c5b94 | 711 | |
8788fdc2 | 712 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
713 | |
714 | wrb = wrb_from_mbox(adapter); | |
715 | req = embedded_payload(wrb); | |
716 | ctxt = &req->context; | |
6b7c5b94 | 717 | |
d744b44e AK |
718 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
719 | OPCODE_ETH_TX_CREATE); | |
6b7c5b94 SP |
720 | |
721 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, | |
722 | sizeof(*req)); | |
723 | ||
724 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
725 | req->ulp_num = BE_ULP1_NUM; | |
726 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | |
727 | ||
b31c50a7 SP |
728 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, |
729 | be_encoded_q_len(txq->len)); | |
6b7c5b94 | 730 | AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt, |
eec368fb | 731 | be_pci_func(adapter)); |
6b7c5b94 SP |
732 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); |
733 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | |
734 | ||
735 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
736 | ||
737 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
738 | ||
b31c50a7 | 739 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
740 | if (!status) { |
741 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | |
742 | txq->id = le16_to_cpu(resp->cid); | |
743 | txq->created = true; | |
744 | } | |
b31c50a7 | 745 | |
8788fdc2 | 746 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
747 | |
748 | return status; | |
749 | } | |
750 | ||
b31c50a7 | 751 | /* Uses mbox */ |
8788fdc2 | 752 | int be_cmd_rxq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
753 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, |
754 | u16 max_frame_size, u32 if_id, u32 rss) | |
755 | { | |
b31c50a7 SP |
756 | struct be_mcc_wrb *wrb; |
757 | struct be_cmd_req_eth_rx_create *req; | |
6b7c5b94 SP |
758 | struct be_dma_mem *q_mem = &rxq->dma_mem; |
759 | int status; | |
760 | ||
8788fdc2 | 761 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
762 | |
763 | wrb = wrb_from_mbox(adapter); | |
764 | req = embedded_payload(wrb); | |
6b7c5b94 | 765 | |
d744b44e AK |
766 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
767 | OPCODE_ETH_RX_CREATE); | |
6b7c5b94 SP |
768 | |
769 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, | |
770 | sizeof(*req)); | |
771 | ||
772 | req->cq_id = cpu_to_le16(cq_id); | |
773 | req->frag_size = fls(frag_size) - 1; | |
774 | req->num_pages = 2; | |
775 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
776 | req->interface_id = cpu_to_le32(if_id); | |
777 | req->max_frame_size = cpu_to_le16(max_frame_size); | |
778 | req->rss_queue = cpu_to_le32(rss); | |
779 | ||
b31c50a7 | 780 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
781 | if (!status) { |
782 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | |
783 | rxq->id = le16_to_cpu(resp->id); | |
784 | rxq->created = true; | |
785 | } | |
b31c50a7 | 786 | |
8788fdc2 | 787 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
788 | |
789 | return status; | |
790 | } | |
791 | ||
b31c50a7 SP |
792 | /* Generic destroyer function for all types of queues |
793 | * Uses Mbox | |
794 | */ | |
8788fdc2 | 795 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
6b7c5b94 SP |
796 | int queue_type) |
797 | { | |
b31c50a7 SP |
798 | struct be_mcc_wrb *wrb; |
799 | struct be_cmd_req_q_destroy *req; | |
6b7c5b94 SP |
800 | u8 subsys = 0, opcode = 0; |
801 | int status; | |
802 | ||
cf588477 SP |
803 | if (adapter->eeh_err) |
804 | return -EIO; | |
805 | ||
8788fdc2 | 806 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 807 | |
b31c50a7 SP |
808 | wrb = wrb_from_mbox(adapter); |
809 | req = embedded_payload(wrb); | |
810 | ||
6b7c5b94 SP |
811 | switch (queue_type) { |
812 | case QTYPE_EQ: | |
813 | subsys = CMD_SUBSYSTEM_COMMON; | |
814 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
815 | break; | |
816 | case QTYPE_CQ: | |
817 | subsys = CMD_SUBSYSTEM_COMMON; | |
818 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
819 | break; | |
820 | case QTYPE_TXQ: | |
821 | subsys = CMD_SUBSYSTEM_ETH; | |
822 | opcode = OPCODE_ETH_TX_DESTROY; | |
823 | break; | |
824 | case QTYPE_RXQ: | |
825 | subsys = CMD_SUBSYSTEM_ETH; | |
826 | opcode = OPCODE_ETH_RX_DESTROY; | |
827 | break; | |
5fb379ee SP |
828 | case QTYPE_MCCQ: |
829 | subsys = CMD_SUBSYSTEM_COMMON; | |
830 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
831 | break; | |
6b7c5b94 | 832 | default: |
5f0b849e | 833 | BUG(); |
6b7c5b94 | 834 | } |
d744b44e AK |
835 | |
836 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode); | |
837 | ||
6b7c5b94 SP |
838 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); |
839 | req->id = cpu_to_le16(q->id); | |
840 | ||
b31c50a7 | 841 | status = be_mbox_notify_wait(adapter); |
5f0b849e | 842 | |
8788fdc2 | 843 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
844 | |
845 | return status; | |
846 | } | |
847 | ||
b31c50a7 SP |
848 | /* Create an rx filtering policy configuration on an i/f |
849 | * Uses mbox | |
850 | */ | |
73d540f2 SP |
851 | int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, |
852 | u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id) | |
6b7c5b94 | 853 | { |
b31c50a7 SP |
854 | struct be_mcc_wrb *wrb; |
855 | struct be_cmd_req_if_create *req; | |
6b7c5b94 SP |
856 | int status; |
857 | ||
8788fdc2 | 858 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
859 | |
860 | wrb = wrb_from_mbox(adapter); | |
861 | req = embedded_payload(wrb); | |
6b7c5b94 | 862 | |
d744b44e AK |
863 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
864 | OPCODE_COMMON_NTWK_INTERFACE_CREATE); | |
6b7c5b94 SP |
865 | |
866 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
867 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); | |
868 | ||
73d540f2 SP |
869 | req->capability_flags = cpu_to_le32(cap_flags); |
870 | req->enable_flags = cpu_to_le32(en_flags); | |
b31c50a7 | 871 | req->pmac_invalid = pmac_invalid; |
6b7c5b94 SP |
872 | if (!pmac_invalid) |
873 | memcpy(req->mac_addr, mac, ETH_ALEN); | |
874 | ||
b31c50a7 | 875 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
876 | if (!status) { |
877 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | |
878 | *if_handle = le32_to_cpu(resp->interface_id); | |
879 | if (!pmac_invalid) | |
880 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
881 | } | |
882 | ||
8788fdc2 | 883 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
884 | return status; |
885 | } | |
886 | ||
b31c50a7 | 887 | /* Uses mbox */ |
8788fdc2 | 888 | int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id) |
6b7c5b94 | 889 | { |
b31c50a7 SP |
890 | struct be_mcc_wrb *wrb; |
891 | struct be_cmd_req_if_destroy *req; | |
6b7c5b94 SP |
892 | int status; |
893 | ||
cf588477 SP |
894 | if (adapter->eeh_err) |
895 | return -EIO; | |
896 | ||
8788fdc2 | 897 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
898 | |
899 | wrb = wrb_from_mbox(adapter); | |
900 | req = embedded_payload(wrb); | |
6b7c5b94 | 901 | |
d744b44e AK |
902 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
903 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY); | |
6b7c5b94 SP |
904 | |
905 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
906 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | |
907 | ||
908 | req->interface_id = cpu_to_le32(interface_id); | |
b31c50a7 SP |
909 | |
910 | status = be_mbox_notify_wait(adapter); | |
6b7c5b94 | 911 | |
8788fdc2 | 912 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
913 | |
914 | return status; | |
915 | } | |
916 | ||
917 | /* Get stats is a non embedded command: the request is not embedded inside | |
918 | * WRB but is a separate dma memory block | |
b31c50a7 | 919 | * Uses asynchronous MCC |
6b7c5b94 | 920 | */ |
8788fdc2 | 921 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) |
6b7c5b94 | 922 | { |
b31c50a7 SP |
923 | struct be_mcc_wrb *wrb; |
924 | struct be_cmd_req_get_stats *req; | |
925 | struct be_sge *sge; | |
713d0394 | 926 | int status = 0; |
6b7c5b94 | 927 | |
b31c50a7 | 928 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 929 | |
b31c50a7 | 930 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
931 | if (!wrb) { |
932 | status = -EBUSY; | |
933 | goto err; | |
934 | } | |
b31c50a7 SP |
935 | req = nonemb_cmd->va; |
936 | sge = nonembedded_sgl(wrb); | |
6b7c5b94 | 937 | |
d744b44e AK |
938 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, |
939 | OPCODE_ETH_GET_STATISTICS); | |
6b7c5b94 SP |
940 | |
941 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
942 | OPCODE_ETH_GET_STATISTICS, sizeof(*req)); | |
943 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
944 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
945 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
946 | ||
b31c50a7 | 947 | be_mcc_notify(adapter); |
6b7c5b94 | 948 | |
713d0394 | 949 | err: |
b31c50a7 | 950 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 951 | return status; |
6b7c5b94 SP |
952 | } |
953 | ||
b31c50a7 | 954 | /* Uses synchronous mcc */ |
8788fdc2 | 955 | int be_cmd_link_status_query(struct be_adapter *adapter, |
0388f251 | 956 | bool *link_up, u8 *mac_speed, u16 *link_speed) |
6b7c5b94 | 957 | { |
b31c50a7 SP |
958 | struct be_mcc_wrb *wrb; |
959 | struct be_cmd_req_link_status *req; | |
6b7c5b94 SP |
960 | int status; |
961 | ||
b31c50a7 SP |
962 | spin_lock_bh(&adapter->mcc_lock); |
963 | ||
964 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
965 | if (!wrb) { |
966 | status = -EBUSY; | |
967 | goto err; | |
968 | } | |
b31c50a7 | 969 | req = embedded_payload(wrb); |
a8f447bd SP |
970 | |
971 | *link_up = false; | |
6b7c5b94 | 972 | |
d744b44e AK |
973 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
974 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY); | |
6b7c5b94 SP |
975 | |
976 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
977 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | |
978 | ||
b31c50a7 | 979 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
980 | if (!status) { |
981 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | |
0388f251 | 982 | if (resp->mac_speed != PHY_LINK_SPEED_ZERO) { |
a8f447bd | 983 | *link_up = true; |
0388f251 SB |
984 | *link_speed = le16_to_cpu(resp->link_speed); |
985 | *mac_speed = resp->mac_speed; | |
986 | } | |
6b7c5b94 SP |
987 | } |
988 | ||
713d0394 | 989 | err: |
b31c50a7 | 990 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
991 | return status; |
992 | } | |
993 | ||
b31c50a7 | 994 | /* Uses Mbox */ |
8788fdc2 | 995 | int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver) |
6b7c5b94 | 996 | { |
b31c50a7 SP |
997 | struct be_mcc_wrb *wrb; |
998 | struct be_cmd_req_get_fw_version *req; | |
6b7c5b94 SP |
999 | int status; |
1000 | ||
8788fdc2 | 1001 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
1002 | |
1003 | wrb = wrb_from_mbox(adapter); | |
1004 | req = embedded_payload(wrb); | |
6b7c5b94 | 1005 | |
d744b44e AK |
1006 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1007 | OPCODE_COMMON_GET_FW_VERSION); | |
6b7c5b94 SP |
1008 | |
1009 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1010 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | |
1011 | ||
b31c50a7 | 1012 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1013 | if (!status) { |
1014 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | |
1015 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | |
1016 | } | |
1017 | ||
8788fdc2 | 1018 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1019 | return status; |
1020 | } | |
1021 | ||
b31c50a7 SP |
1022 | /* set the EQ delay interval of an EQ to specified value |
1023 | * Uses async mcc | |
1024 | */ | |
8788fdc2 | 1025 | int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) |
6b7c5b94 | 1026 | { |
b31c50a7 SP |
1027 | struct be_mcc_wrb *wrb; |
1028 | struct be_cmd_req_modify_eq_delay *req; | |
713d0394 | 1029 | int status = 0; |
6b7c5b94 | 1030 | |
b31c50a7 SP |
1031 | spin_lock_bh(&adapter->mcc_lock); |
1032 | ||
1033 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1034 | if (!wrb) { |
1035 | status = -EBUSY; | |
1036 | goto err; | |
1037 | } | |
b31c50a7 | 1038 | req = embedded_payload(wrb); |
6b7c5b94 | 1039 | |
d744b44e AK |
1040 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1041 | OPCODE_COMMON_MODIFY_EQ_DELAY); | |
6b7c5b94 SP |
1042 | |
1043 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1044 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); | |
1045 | ||
1046 | req->num_eq = cpu_to_le32(1); | |
1047 | req->delay[0].eq_id = cpu_to_le32(eq_id); | |
1048 | req->delay[0].phase = 0; | |
1049 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | |
1050 | ||
b31c50a7 | 1051 | be_mcc_notify(adapter); |
6b7c5b94 | 1052 | |
713d0394 | 1053 | err: |
b31c50a7 | 1054 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 1055 | return status; |
6b7c5b94 SP |
1056 | } |
1057 | ||
b31c50a7 | 1058 | /* Uses sycnhronous mcc */ |
8788fdc2 | 1059 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
6b7c5b94 SP |
1060 | u32 num, bool untagged, bool promiscuous) |
1061 | { | |
b31c50a7 SP |
1062 | struct be_mcc_wrb *wrb; |
1063 | struct be_cmd_req_vlan_config *req; | |
6b7c5b94 SP |
1064 | int status; |
1065 | ||
b31c50a7 SP |
1066 | spin_lock_bh(&adapter->mcc_lock); |
1067 | ||
1068 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1069 | if (!wrb) { |
1070 | status = -EBUSY; | |
1071 | goto err; | |
1072 | } | |
b31c50a7 | 1073 | req = embedded_payload(wrb); |
6b7c5b94 | 1074 | |
d744b44e AK |
1075 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1076 | OPCODE_COMMON_NTWK_VLAN_CONFIG); | |
6b7c5b94 SP |
1077 | |
1078 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1079 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); | |
1080 | ||
1081 | req->interface_id = if_id; | |
1082 | req->promiscuous = promiscuous; | |
1083 | req->untagged = untagged; | |
1084 | req->num_vlan = num; | |
1085 | if (!promiscuous) { | |
1086 | memcpy(req->normal_vlan, vtag_array, | |
1087 | req->num_vlan * sizeof(vtag_array[0])); | |
1088 | } | |
1089 | ||
b31c50a7 | 1090 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1091 | |
713d0394 | 1092 | err: |
b31c50a7 | 1093 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1094 | return status; |
1095 | } | |
1096 | ||
b31c50a7 SP |
1097 | /* Uses MCC for this command as it may be called in BH context |
1098 | * Uses synchronous mcc | |
1099 | */ | |
8788fdc2 | 1100 | int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en) |
6b7c5b94 | 1101 | { |
6ac7b687 SP |
1102 | struct be_mcc_wrb *wrb; |
1103 | struct be_cmd_req_promiscuous_config *req; | |
b31c50a7 | 1104 | int status; |
6b7c5b94 | 1105 | |
8788fdc2 | 1106 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1107 | |
b31c50a7 | 1108 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1109 | if (!wrb) { |
1110 | status = -EBUSY; | |
1111 | goto err; | |
1112 | } | |
6ac7b687 | 1113 | req = embedded_payload(wrb); |
6b7c5b94 | 1114 | |
d744b44e | 1115 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS); |
6b7c5b94 SP |
1116 | |
1117 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1118 | OPCODE_ETH_PROMISCUOUS, sizeof(*req)); | |
1119 | ||
1120 | if (port_num) | |
1121 | req->port1_promiscuous = en; | |
1122 | else | |
1123 | req->port0_promiscuous = en; | |
1124 | ||
b31c50a7 | 1125 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1126 | |
713d0394 | 1127 | err: |
8788fdc2 | 1128 | spin_unlock_bh(&adapter->mcc_lock); |
b31c50a7 | 1129 | return status; |
6b7c5b94 SP |
1130 | } |
1131 | ||
6ac7b687 | 1132 | /* |
b31c50a7 | 1133 | * Uses MCC for this command as it may be called in BH context |
6ac7b687 SP |
1134 | * (mc == NULL) => multicast promiscous |
1135 | */ | |
8788fdc2 | 1136 | int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, |
e7b909a6 SP |
1137 | struct dev_mc_list *mc_list, u32 mc_count, |
1138 | struct be_dma_mem *mem) | |
6b7c5b94 | 1139 | { |
6ac7b687 | 1140 | struct be_mcc_wrb *wrb; |
e7b909a6 SP |
1141 | struct be_cmd_req_mcast_mac_config *req = mem->va; |
1142 | struct be_sge *sge; | |
1143 | int status; | |
6b7c5b94 | 1144 | |
8788fdc2 | 1145 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1146 | |
b31c50a7 | 1147 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1148 | if (!wrb) { |
1149 | status = -EBUSY; | |
1150 | goto err; | |
1151 | } | |
e7b909a6 SP |
1152 | sge = nonembedded_sgl(wrb); |
1153 | memset(req, 0, sizeof(*req)); | |
6b7c5b94 | 1154 | |
d744b44e AK |
1155 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, |
1156 | OPCODE_COMMON_NTWK_MULTICAST_SET); | |
e7b909a6 SP |
1157 | sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); |
1158 | sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); | |
1159 | sge->len = cpu_to_le32(mem->size); | |
6b7c5b94 SP |
1160 | |
1161 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1162 | OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req)); | |
1163 | ||
1164 | req->interface_id = if_id; | |
e7b909a6 | 1165 | if (mc_list) { |
24307eef SP |
1166 | int i; |
1167 | struct dev_mc_list *mc; | |
1168 | ||
1169 | req->num_mac = cpu_to_le16(mc_count); | |
1170 | ||
1171 | for (mc = mc_list, i = 0; mc; mc = mc->next, i++) | |
1172 | memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN); | |
1173 | } else { | |
1174 | req->promiscuous = 1; | |
6b7c5b94 SP |
1175 | } |
1176 | ||
e7b909a6 | 1177 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1178 | |
713d0394 | 1179 | err: |
8788fdc2 | 1180 | spin_unlock_bh(&adapter->mcc_lock); |
e7b909a6 | 1181 | return status; |
6b7c5b94 SP |
1182 | } |
1183 | ||
b31c50a7 | 1184 | /* Uses synchrounous mcc */ |
8788fdc2 | 1185 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) |
6b7c5b94 | 1186 | { |
b31c50a7 SP |
1187 | struct be_mcc_wrb *wrb; |
1188 | struct be_cmd_req_set_flow_control *req; | |
6b7c5b94 SP |
1189 | int status; |
1190 | ||
b31c50a7 | 1191 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1192 | |
b31c50a7 | 1193 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1194 | if (!wrb) { |
1195 | status = -EBUSY; | |
1196 | goto err; | |
1197 | } | |
b31c50a7 | 1198 | req = embedded_payload(wrb); |
6b7c5b94 | 1199 | |
d744b44e AK |
1200 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1201 | OPCODE_COMMON_SET_FLOW_CONTROL); | |
6b7c5b94 SP |
1202 | |
1203 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1204 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); | |
1205 | ||
1206 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | |
1207 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | |
1208 | ||
b31c50a7 | 1209 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1210 | |
713d0394 | 1211 | err: |
b31c50a7 | 1212 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1213 | return status; |
1214 | } | |
1215 | ||
b31c50a7 | 1216 | /* Uses sycn mcc */ |
8788fdc2 | 1217 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) |
6b7c5b94 | 1218 | { |
b31c50a7 SP |
1219 | struct be_mcc_wrb *wrb; |
1220 | struct be_cmd_req_get_flow_control *req; | |
6b7c5b94 SP |
1221 | int status; |
1222 | ||
b31c50a7 | 1223 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1224 | |
b31c50a7 | 1225 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1226 | if (!wrb) { |
1227 | status = -EBUSY; | |
1228 | goto err; | |
1229 | } | |
b31c50a7 | 1230 | req = embedded_payload(wrb); |
6b7c5b94 | 1231 | |
d744b44e AK |
1232 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1233 | OPCODE_COMMON_GET_FLOW_CONTROL); | |
6b7c5b94 SP |
1234 | |
1235 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1236 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | |
1237 | ||
b31c50a7 | 1238 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1239 | if (!status) { |
1240 | struct be_cmd_resp_get_flow_control *resp = | |
1241 | embedded_payload(wrb); | |
1242 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | |
1243 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | |
1244 | } | |
1245 | ||
713d0394 | 1246 | err: |
b31c50a7 | 1247 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1248 | return status; |
1249 | } | |
1250 | ||
b31c50a7 | 1251 | /* Uses mbox */ |
dcb9b564 | 1252 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap) |
6b7c5b94 | 1253 | { |
b31c50a7 SP |
1254 | struct be_mcc_wrb *wrb; |
1255 | struct be_cmd_req_query_fw_cfg *req; | |
6b7c5b94 SP |
1256 | int status; |
1257 | ||
8788fdc2 | 1258 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 1259 | |
b31c50a7 SP |
1260 | wrb = wrb_from_mbox(adapter); |
1261 | req = embedded_payload(wrb); | |
6b7c5b94 | 1262 | |
d744b44e AK |
1263 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1264 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG); | |
6b7c5b94 SP |
1265 | |
1266 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1267 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | |
1268 | ||
b31c50a7 | 1269 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1270 | if (!status) { |
1271 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | |
1272 | *port_num = le32_to_cpu(resp->phys_port); | |
dcb9b564 | 1273 | *cap = le32_to_cpu(resp->function_cap); |
6b7c5b94 SP |
1274 | } |
1275 | ||
8788fdc2 | 1276 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1277 | return status; |
1278 | } | |
14074eab | 1279 | |
b31c50a7 | 1280 | /* Uses mbox */ |
14074eab | 1281 | int be_cmd_reset_function(struct be_adapter *adapter) |
1282 | { | |
b31c50a7 SP |
1283 | struct be_mcc_wrb *wrb; |
1284 | struct be_cmd_req_hdr *req; | |
14074eab | 1285 | int status; |
1286 | ||
1287 | spin_lock(&adapter->mbox_lock); | |
1288 | ||
b31c50a7 SP |
1289 | wrb = wrb_from_mbox(adapter); |
1290 | req = embedded_payload(wrb); | |
14074eab | 1291 | |
d744b44e AK |
1292 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1293 | OPCODE_COMMON_FUNCTION_RESET); | |
14074eab | 1294 | |
1295 | be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, | |
1296 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); | |
1297 | ||
b31c50a7 | 1298 | status = be_mbox_notify_wait(adapter); |
14074eab | 1299 | |
1300 | spin_unlock(&adapter->mbox_lock); | |
1301 | return status; | |
1302 | } | |
84517482 | 1303 | |
fad9ab2c SB |
1304 | /* Uses sync mcc */ |
1305 | int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, | |
1306 | u8 bcn, u8 sts, u8 state) | |
1307 | { | |
1308 | struct be_mcc_wrb *wrb; | |
1309 | struct be_cmd_req_enable_disable_beacon *req; | |
1310 | int status; | |
1311 | ||
1312 | spin_lock_bh(&adapter->mcc_lock); | |
1313 | ||
1314 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1315 | if (!wrb) { |
1316 | status = -EBUSY; | |
1317 | goto err; | |
1318 | } | |
fad9ab2c SB |
1319 | req = embedded_payload(wrb); |
1320 | ||
d744b44e AK |
1321 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1322 | OPCODE_COMMON_ENABLE_DISABLE_BEACON); | |
fad9ab2c SB |
1323 | |
1324 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1325 | OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req)); | |
1326 | ||
1327 | req->port_num = port_num; | |
1328 | req->beacon_state = state; | |
1329 | req->beacon_duration = bcn; | |
1330 | req->status_duration = sts; | |
1331 | ||
1332 | status = be_mcc_notify_wait(adapter); | |
1333 | ||
713d0394 | 1334 | err: |
fad9ab2c SB |
1335 | spin_unlock_bh(&adapter->mcc_lock); |
1336 | return status; | |
1337 | } | |
1338 | ||
1339 | /* Uses sync mcc */ | |
1340 | int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) | |
1341 | { | |
1342 | struct be_mcc_wrb *wrb; | |
1343 | struct be_cmd_req_get_beacon_state *req; | |
1344 | int status; | |
1345 | ||
1346 | spin_lock_bh(&adapter->mcc_lock); | |
1347 | ||
1348 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1349 | if (!wrb) { |
1350 | status = -EBUSY; | |
1351 | goto err; | |
1352 | } | |
fad9ab2c SB |
1353 | req = embedded_payload(wrb); |
1354 | ||
d744b44e AK |
1355 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1356 | OPCODE_COMMON_GET_BEACON_STATE); | |
fad9ab2c SB |
1357 | |
1358 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1359 | OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req)); | |
1360 | ||
1361 | req->port_num = port_num; | |
1362 | ||
1363 | status = be_mcc_notify_wait(adapter); | |
1364 | if (!status) { | |
1365 | struct be_cmd_resp_get_beacon_state *resp = | |
1366 | embedded_payload(wrb); | |
1367 | *state = resp->beacon_state; | |
1368 | } | |
1369 | ||
713d0394 | 1370 | err: |
fad9ab2c SB |
1371 | spin_unlock_bh(&adapter->mcc_lock); |
1372 | return status; | |
1373 | } | |
1374 | ||
0388f251 SB |
1375 | /* Uses sync mcc */ |
1376 | int be_cmd_read_port_type(struct be_adapter *adapter, u32 port, | |
1377 | u8 *connector) | |
1378 | { | |
1379 | struct be_mcc_wrb *wrb; | |
1380 | struct be_cmd_req_port_type *req; | |
1381 | int status; | |
1382 | ||
1383 | spin_lock_bh(&adapter->mcc_lock); | |
1384 | ||
1385 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1386 | if (!wrb) { |
1387 | status = -EBUSY; | |
1388 | goto err; | |
1389 | } | |
0388f251 SB |
1390 | req = embedded_payload(wrb); |
1391 | ||
d744b44e AK |
1392 | be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0, |
1393 | OPCODE_COMMON_READ_TRANSRECV_DATA); | |
0388f251 SB |
1394 | |
1395 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1396 | OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req)); | |
1397 | ||
1398 | req->port = cpu_to_le32(port); | |
1399 | req->page_num = cpu_to_le32(TR_PAGE_A0); | |
1400 | status = be_mcc_notify_wait(adapter); | |
1401 | if (!status) { | |
1402 | struct be_cmd_resp_port_type *resp = embedded_payload(wrb); | |
1403 | *connector = resp->data.connector; | |
1404 | } | |
1405 | ||
713d0394 | 1406 | err: |
0388f251 SB |
1407 | spin_unlock_bh(&adapter->mcc_lock); |
1408 | return status; | |
1409 | } | |
1410 | ||
84517482 AK |
1411 | int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, |
1412 | u32 flash_type, u32 flash_opcode, u32 buf_size) | |
1413 | { | |
b31c50a7 | 1414 | struct be_mcc_wrb *wrb; |
3f0d4560 | 1415 | struct be_cmd_write_flashrom *req; |
b31c50a7 | 1416 | struct be_sge *sge; |
84517482 AK |
1417 | int status; |
1418 | ||
b31c50a7 SP |
1419 | spin_lock_bh(&adapter->mcc_lock); |
1420 | ||
1421 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1422 | if (!wrb) { |
1423 | status = -EBUSY; | |
1424 | goto err; | |
1425 | } | |
1426 | req = cmd->va; | |
b31c50a7 SP |
1427 | sge = nonembedded_sgl(wrb); |
1428 | ||
d744b44e AK |
1429 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, |
1430 | OPCODE_COMMON_WRITE_FLASHROM); | |
84517482 AK |
1431 | |
1432 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1433 | OPCODE_COMMON_WRITE_FLASHROM, cmd->size); | |
1434 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1435 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1436 | sge->len = cpu_to_le32(cmd->size); | |
1437 | ||
1438 | req->params.op_type = cpu_to_le32(flash_type); | |
1439 | req->params.op_code = cpu_to_le32(flash_opcode); | |
1440 | req->params.data_buf_size = cpu_to_le32(buf_size); | |
1441 | ||
b31c50a7 | 1442 | status = be_mcc_notify_wait(adapter); |
84517482 | 1443 | |
713d0394 | 1444 | err: |
b31c50a7 | 1445 | spin_unlock_bh(&adapter->mcc_lock); |
84517482 AK |
1446 | return status; |
1447 | } | |
fa9a6fed | 1448 | |
3f0d4560 AK |
1449 | int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, |
1450 | int offset) | |
fa9a6fed SB |
1451 | { |
1452 | struct be_mcc_wrb *wrb; | |
1453 | struct be_cmd_write_flashrom *req; | |
1454 | int status; | |
1455 | ||
1456 | spin_lock_bh(&adapter->mcc_lock); | |
1457 | ||
1458 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1459 | if (!wrb) { |
1460 | status = -EBUSY; | |
1461 | goto err; | |
1462 | } | |
fa9a6fed SB |
1463 | req = embedded_payload(wrb); |
1464 | ||
d744b44e AK |
1465 | be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0, |
1466 | OPCODE_COMMON_READ_FLASHROM); | |
fa9a6fed SB |
1467 | |
1468 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1469 | OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4); | |
1470 | ||
3f0d4560 | 1471 | req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT); |
fa9a6fed | 1472 | req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); |
3f0d4560 | 1473 | req->params.offset = offset; |
fa9a6fed SB |
1474 | req->params.data_buf_size = 0x4; |
1475 | ||
1476 | status = be_mcc_notify_wait(adapter); | |
1477 | if (!status) | |
1478 | memcpy(flashed_crc, req->params.data_buf, 4); | |
1479 | ||
713d0394 | 1480 | err: |
fa9a6fed SB |
1481 | spin_unlock_bh(&adapter->mcc_lock); |
1482 | return status; | |
1483 | } | |
71d8d1b5 AK |
1484 | |
1485 | extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, | |
1486 | struct be_dma_mem *nonemb_cmd) | |
1487 | { | |
1488 | struct be_mcc_wrb *wrb; | |
1489 | struct be_cmd_req_acpi_wol_magic_config *req; | |
1490 | struct be_sge *sge; | |
1491 | int status; | |
1492 | ||
1493 | spin_lock_bh(&adapter->mcc_lock); | |
1494 | ||
1495 | wrb = wrb_from_mccq(adapter); | |
1496 | if (!wrb) { | |
1497 | status = -EBUSY; | |
1498 | goto err; | |
1499 | } | |
1500 | req = nonemb_cmd->va; | |
1501 | sge = nonembedded_sgl(wrb); | |
1502 | ||
1503 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
1504 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG); | |
1505 | ||
1506 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1507 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req)); | |
1508 | memcpy(req->magic_mac, mac, ETH_ALEN); | |
1509 | ||
1510 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
1511 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1512 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1513 | ||
1514 | status = be_mcc_notify_wait(adapter); | |
1515 | ||
1516 | err: | |
1517 | spin_unlock_bh(&adapter->mcc_lock); | |
1518 | return status; | |
1519 | } | |
ff33a6e2 | 1520 | |
fced9999 SB |
1521 | int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, |
1522 | u8 loopback_type, u8 enable) | |
1523 | { | |
1524 | struct be_mcc_wrb *wrb; | |
1525 | struct be_cmd_req_set_lmode *req; | |
1526 | int status; | |
1527 | ||
1528 | spin_lock_bh(&adapter->mcc_lock); | |
1529 | ||
1530 | wrb = wrb_from_mccq(adapter); | |
1531 | if (!wrb) { | |
1532 | status = -EBUSY; | |
1533 | goto err; | |
1534 | } | |
1535 | ||
1536 | req = embedded_payload(wrb); | |
1537 | ||
1538 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1539 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE); | |
1540 | ||
1541 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1542 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, | |
1543 | sizeof(*req)); | |
1544 | ||
1545 | req->src_port = port_num; | |
1546 | req->dest_port = port_num; | |
1547 | req->loopback_type = loopback_type; | |
1548 | req->loopback_state = enable; | |
1549 | ||
1550 | status = be_mcc_notify_wait(adapter); | |
1551 | err: | |
1552 | spin_unlock_bh(&adapter->mcc_lock); | |
1553 | return status; | |
1554 | } | |
1555 | ||
ff33a6e2 S |
1556 | int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, |
1557 | u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) | |
1558 | { | |
1559 | struct be_mcc_wrb *wrb; | |
1560 | struct be_cmd_req_loopback_test *req; | |
1561 | int status; | |
1562 | ||
1563 | spin_lock_bh(&adapter->mcc_lock); | |
1564 | ||
1565 | wrb = wrb_from_mccq(adapter); | |
1566 | if (!wrb) { | |
1567 | status = -EBUSY; | |
1568 | goto err; | |
1569 | } | |
1570 | ||
1571 | req = embedded_payload(wrb); | |
1572 | ||
1573 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1574 | OPCODE_LOWLEVEL_LOOPBACK_TEST); | |
1575 | ||
1576 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1577 | OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req)); | |
d7b90141 | 1578 | req->hdr.timeout = 4; |
ff33a6e2 S |
1579 | |
1580 | req->pattern = cpu_to_le64(pattern); | |
1581 | req->src_port = cpu_to_le32(port_num); | |
1582 | req->dest_port = cpu_to_le32(port_num); | |
1583 | req->pkt_size = cpu_to_le32(pkt_size); | |
1584 | req->num_pkts = cpu_to_le32(num_pkts); | |
1585 | req->loopback_type = cpu_to_le32(loopback_type); | |
1586 | ||
1587 | status = be_mcc_notify_wait(adapter); | |
1588 | if (!status) { | |
1589 | struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); | |
1590 | status = le32_to_cpu(resp->status); | |
1591 | } | |
1592 | ||
1593 | err: | |
1594 | spin_unlock_bh(&adapter->mcc_lock); | |
1595 | return status; | |
1596 | } | |
1597 | ||
1598 | int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, | |
1599 | u32 byte_cnt, struct be_dma_mem *cmd) | |
1600 | { | |
1601 | struct be_mcc_wrb *wrb; | |
1602 | struct be_cmd_req_ddrdma_test *req; | |
1603 | struct be_sge *sge; | |
1604 | int status; | |
1605 | int i, j = 0; | |
1606 | ||
1607 | spin_lock_bh(&adapter->mcc_lock); | |
1608 | ||
1609 | wrb = wrb_from_mccq(adapter); | |
1610 | if (!wrb) { | |
1611 | status = -EBUSY; | |
1612 | goto err; | |
1613 | } | |
1614 | req = cmd->va; | |
1615 | sge = nonembedded_sgl(wrb); | |
1616 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, | |
1617 | OPCODE_LOWLEVEL_HOST_DDR_DMA); | |
1618 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1619 | OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size); | |
1620 | ||
1621 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1622 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1623 | sge->len = cpu_to_le32(cmd->size); | |
1624 | ||
1625 | req->pattern = cpu_to_le64(pattern); | |
1626 | req->byte_count = cpu_to_le32(byte_cnt); | |
1627 | for (i = 0; i < byte_cnt; i++) { | |
1628 | req->snd_buff[i] = (u8)(pattern >> (j*8)); | |
1629 | j++; | |
1630 | if (j > 7) | |
1631 | j = 0; | |
1632 | } | |
1633 | ||
1634 | status = be_mcc_notify_wait(adapter); | |
1635 | ||
1636 | if (!status) { | |
1637 | struct be_cmd_resp_ddrdma_test *resp; | |
1638 | resp = cmd->va; | |
1639 | if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || | |
1640 | resp->snd_err) { | |
1641 | status = -1; | |
1642 | } | |
1643 | } | |
1644 | ||
1645 | err: | |
1646 | spin_unlock_bh(&adapter->mcc_lock); | |
1647 | return status; | |
1648 | } | |
368c0ca2 SB |
1649 | |
1650 | extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, | |
1651 | struct be_dma_mem *nonemb_cmd) | |
1652 | { | |
1653 | struct be_mcc_wrb *wrb; | |
1654 | struct be_cmd_req_seeprom_read *req; | |
1655 | struct be_sge *sge; | |
1656 | int status; | |
1657 | ||
1658 | spin_lock_bh(&adapter->mcc_lock); | |
1659 | ||
1660 | wrb = wrb_from_mccq(adapter); | |
1661 | req = nonemb_cmd->va; | |
1662 | sge = nonembedded_sgl(wrb); | |
1663 | ||
1664 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
1665 | OPCODE_COMMON_SEEPROM_READ); | |
1666 | ||
1667 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1668 | OPCODE_COMMON_SEEPROM_READ, sizeof(*req)); | |
1669 | ||
1670 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
1671 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1672 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1673 | ||
1674 | status = be_mcc_notify_wait(adapter); | |
1675 | ||
1676 | spin_unlock_bh(&adapter->mcc_lock); | |
1677 | return status; | |
1678 | } |