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Commit | Line | Data |
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6b7c5b94 | 1 | /* |
d2145cde | 2 | * Copyright (C) 2005 - 2011 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #include "be.h" | |
8788fdc2 | 19 | #include "be_cmds.h" |
6b7c5b94 | 20 | |
609ff3bb AK |
21 | /* Must be a power of 2 or else MODULO will BUG_ON */ |
22 | static int be_get_temp_freq = 32; | |
23 | ||
8788fdc2 | 24 | static void be_mcc_notify(struct be_adapter *adapter) |
5fb379ee | 25 | { |
8788fdc2 | 26 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
5fb379ee SP |
27 | u32 val = 0; |
28 | ||
7acc2087 AK |
29 | if (adapter->eeh_err) { |
30 | dev_info(&adapter->pdev->dev, | |
31 | "Error in Card Detected! Cannot issue commands\n"); | |
32 | return; | |
33 | } | |
34 | ||
5fb379ee SP |
35 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; |
36 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
f3eb62d2 SP |
37 | |
38 | wmb(); | |
8788fdc2 | 39 | iowrite32(val, adapter->db + DB_MCCQ_OFFSET); |
5fb379ee SP |
40 | } |
41 | ||
42 | /* To check if valid bit is set, check the entire word as we don't know | |
43 | * the endianness of the data (old entry is host endian while a new entry is | |
44 | * little endian) */ | |
efd2e40a | 45 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) |
5fb379ee SP |
46 | { |
47 | if (compl->flags != 0) { | |
48 | compl->flags = le32_to_cpu(compl->flags); | |
49 | BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); | |
50 | return true; | |
51 | } else { | |
52 | return false; | |
53 | } | |
54 | } | |
55 | ||
56 | /* Need to reset the entire word that houses the valid bit */ | |
efd2e40a | 57 | static inline void be_mcc_compl_use(struct be_mcc_compl *compl) |
5fb379ee SP |
58 | { |
59 | compl->flags = 0; | |
60 | } | |
61 | ||
8788fdc2 | 62 | static int be_mcc_compl_process(struct be_adapter *adapter, |
efd2e40a | 63 | struct be_mcc_compl *compl) |
5fb379ee SP |
64 | { |
65 | u16 compl_status, extd_status; | |
66 | ||
67 | /* Just swap the status to host endian; mcc tag is opaquely copied | |
68 | * from mcc_wrb */ | |
69 | be_dws_le_to_cpu(compl, 4); | |
70 | ||
71 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & | |
72 | CQE_STATUS_COMPL_MASK; | |
dd131e76 | 73 | |
485bf569 SN |
74 | if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) || |
75 | (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) && | |
dd131e76 SB |
76 | (compl->tag1 == CMD_SUBSYSTEM_COMMON)) { |
77 | adapter->flash_status = compl_status; | |
78 | complete(&adapter->flash_compl); | |
79 | } | |
80 | ||
b31c50a7 | 81 | if (compl_status == MCC_STATUS_SUCCESS) { |
005d5696 SX |
82 | if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) || |
83 | (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) && | |
6349935b | 84 | (compl->tag1 == CMD_SUBSYSTEM_ETH)) { |
89a88ab8 | 85 | be_parse_stats(adapter); |
b2aebe6d | 86 | adapter->stats_cmd_sent = false; |
b31c50a7 | 87 | } |
2b3f291b SP |
88 | } else { |
89 | if (compl_status == MCC_STATUS_NOT_SUPPORTED || | |
90 | compl_status == MCC_STATUS_ILLEGAL_REQUEST) | |
91 | goto done; | |
92 | ||
93 | if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { | |
94 | dev_warn(&adapter->pdev->dev, "This domain(VM) is not " | |
95 | "permitted to execute this cmd (opcode %d)\n", | |
96 | compl->tag0); | |
97 | } else { | |
98 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & | |
99 | CQE_STATUS_EXTD_MASK; | |
100 | dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:" | |
101 | "status %d, extd-status %d\n", | |
102 | compl->tag0, compl_status, extd_status); | |
103 | } | |
5fb379ee | 104 | } |
2b3f291b | 105 | done: |
b31c50a7 | 106 | return compl_status; |
5fb379ee SP |
107 | } |
108 | ||
a8f447bd | 109 | /* Link state evt is a string of bytes; no need for endian swapping */ |
8788fdc2 | 110 | static void be_async_link_state_process(struct be_adapter *adapter, |
a8f447bd SP |
111 | struct be_async_event_link_state *evt) |
112 | { | |
ea172a01 | 113 | be_link_status_update(adapter, evt->port_link_status); |
a8f447bd SP |
114 | } |
115 | ||
cc4ce020 SK |
116 | /* Grp5 CoS Priority evt */ |
117 | static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, | |
118 | struct be_async_event_grp5_cos_priority *evt) | |
119 | { | |
120 | if (evt->valid) { | |
121 | adapter->vlan_prio_bmap = evt->available_priority_bmap; | |
60964dd7 | 122 | adapter->recommended_prio &= ~VLAN_PRIO_MASK; |
cc4ce020 SK |
123 | adapter->recommended_prio = |
124 | evt->reco_default_priority << VLAN_PRIO_SHIFT; | |
125 | } | |
126 | } | |
127 | ||
128 | /* Grp5 QOS Speed evt */ | |
129 | static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, | |
130 | struct be_async_event_grp5_qos_link_speed *evt) | |
131 | { | |
132 | if (evt->physical_port == adapter->port_num) { | |
133 | /* qos_link_speed is in units of 10 Mbps */ | |
134 | adapter->link_speed = evt->qos_link_speed * 10; | |
135 | } | |
136 | } | |
137 | ||
3968fa1e AK |
138 | /*Grp5 PVID evt*/ |
139 | static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, | |
140 | struct be_async_event_grp5_pvid_state *evt) | |
141 | { | |
142 | if (evt->enabled) | |
6709d952 | 143 | adapter->pvid = le16_to_cpu(evt->tag); |
3968fa1e AK |
144 | else |
145 | adapter->pvid = 0; | |
146 | } | |
147 | ||
cc4ce020 SK |
148 | static void be_async_grp5_evt_process(struct be_adapter *adapter, |
149 | u32 trailer, struct be_mcc_compl *evt) | |
150 | { | |
151 | u8 event_type = 0; | |
152 | ||
153 | event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & | |
154 | ASYNC_TRAILER_EVENT_TYPE_MASK; | |
155 | ||
156 | switch (event_type) { | |
157 | case ASYNC_EVENT_COS_PRIORITY: | |
158 | be_async_grp5_cos_priority_process(adapter, | |
159 | (struct be_async_event_grp5_cos_priority *)evt); | |
160 | break; | |
161 | case ASYNC_EVENT_QOS_SPEED: | |
162 | be_async_grp5_qos_speed_process(adapter, | |
163 | (struct be_async_event_grp5_qos_link_speed *)evt); | |
164 | break; | |
3968fa1e AK |
165 | case ASYNC_EVENT_PVID_STATE: |
166 | be_async_grp5_pvid_state_process(adapter, | |
167 | (struct be_async_event_grp5_pvid_state *)evt); | |
168 | break; | |
cc4ce020 SK |
169 | default: |
170 | dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n"); | |
171 | break; | |
172 | } | |
173 | } | |
174 | ||
a8f447bd SP |
175 | static inline bool is_link_state_evt(u32 trailer) |
176 | { | |
807540ba | 177 | return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & |
a8f447bd | 178 | ASYNC_TRAILER_EVENT_CODE_MASK) == |
807540ba | 179 | ASYNC_EVENT_CODE_LINK_STATE; |
a8f447bd | 180 | } |
5fb379ee | 181 | |
cc4ce020 SK |
182 | static inline bool is_grp5_evt(u32 trailer) |
183 | { | |
184 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | |
185 | ASYNC_TRAILER_EVENT_CODE_MASK) == | |
186 | ASYNC_EVENT_CODE_GRP_5); | |
187 | } | |
188 | ||
efd2e40a | 189 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) |
5fb379ee | 190 | { |
8788fdc2 | 191 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
efd2e40a | 192 | struct be_mcc_compl *compl = queue_tail_node(mcc_cq); |
5fb379ee SP |
193 | |
194 | if (be_mcc_compl_is_new(compl)) { | |
195 | queue_tail_inc(mcc_cq); | |
196 | return compl; | |
197 | } | |
198 | return NULL; | |
199 | } | |
200 | ||
7a1e9b20 SP |
201 | void be_async_mcc_enable(struct be_adapter *adapter) |
202 | { | |
203 | spin_lock_bh(&adapter->mcc_cq_lock); | |
204 | ||
205 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); | |
206 | adapter->mcc_obj.rearm_cq = true; | |
207 | ||
208 | spin_unlock_bh(&adapter->mcc_cq_lock); | |
209 | } | |
210 | ||
211 | void be_async_mcc_disable(struct be_adapter *adapter) | |
212 | { | |
213 | adapter->mcc_obj.rearm_cq = false; | |
214 | } | |
215 | ||
f31e50a8 | 216 | int be_process_mcc(struct be_adapter *adapter, int *status) |
5fb379ee | 217 | { |
efd2e40a | 218 | struct be_mcc_compl *compl; |
f31e50a8 | 219 | int num = 0; |
7a1e9b20 | 220 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; |
5fb379ee | 221 | |
8788fdc2 SP |
222 | spin_lock_bh(&adapter->mcc_cq_lock); |
223 | while ((compl = be_mcc_compl_get(adapter))) { | |
a8f447bd SP |
224 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { |
225 | /* Interpret flags as an async trailer */ | |
323f30b3 AK |
226 | if (is_link_state_evt(compl->flags)) |
227 | be_async_link_state_process(adapter, | |
a8f447bd | 228 | (struct be_async_event_link_state *) compl); |
cc4ce020 SK |
229 | else if (is_grp5_evt(compl->flags)) |
230 | be_async_grp5_evt_process(adapter, | |
231 | compl->flags, compl); | |
b31c50a7 | 232 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
f31e50a8 | 233 | *status = be_mcc_compl_process(adapter, compl); |
7a1e9b20 | 234 | atomic_dec(&mcc_obj->q.used); |
5fb379ee SP |
235 | } |
236 | be_mcc_compl_use(compl); | |
237 | num++; | |
238 | } | |
b31c50a7 | 239 | |
8788fdc2 | 240 | spin_unlock_bh(&adapter->mcc_cq_lock); |
f31e50a8 | 241 | return num; |
5fb379ee SP |
242 | } |
243 | ||
6ac7b687 | 244 | /* Wait till no more pending mcc requests are present */ |
b31c50a7 | 245 | static int be_mcc_wait_compl(struct be_adapter *adapter) |
6ac7b687 | 246 | { |
b31c50a7 | 247 | #define mcc_timeout 120000 /* 12s timeout */ |
f31e50a8 SP |
248 | int i, num, status = 0; |
249 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; | |
250 | ||
7acc2087 AK |
251 | if (adapter->eeh_err) |
252 | return -EIO; | |
253 | ||
6ac7b687 | 254 | for (i = 0; i < mcc_timeout; i++) { |
f31e50a8 SP |
255 | num = be_process_mcc(adapter, &status); |
256 | if (num) | |
257 | be_cq_notify(adapter, mcc_obj->cq.id, | |
258 | mcc_obj->rearm_cq, num); | |
b31c50a7 | 259 | |
f31e50a8 | 260 | if (atomic_read(&mcc_obj->q.used) == 0) |
6ac7b687 SP |
261 | break; |
262 | udelay(100); | |
263 | } | |
b31c50a7 | 264 | if (i == mcc_timeout) { |
5f0b849e | 265 | dev_err(&adapter->pdev->dev, "mccq poll timed out\n"); |
b31c50a7 SP |
266 | return -1; |
267 | } | |
f31e50a8 | 268 | return status; |
6ac7b687 SP |
269 | } |
270 | ||
271 | /* Notify MCC requests and wait for completion */ | |
b31c50a7 | 272 | static int be_mcc_notify_wait(struct be_adapter *adapter) |
6ac7b687 | 273 | { |
8788fdc2 | 274 | be_mcc_notify(adapter); |
b31c50a7 | 275 | return be_mcc_wait_compl(adapter); |
6ac7b687 SP |
276 | } |
277 | ||
5f0b849e | 278 | static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) |
6b7c5b94 | 279 | { |
f25b03a7 | 280 | int msecs = 0; |
6b7c5b94 SP |
281 | u32 ready; |
282 | ||
7acc2087 AK |
283 | if (adapter->eeh_err) { |
284 | dev_err(&adapter->pdev->dev, | |
285 | "Error detected in card.Cannot issue commands\n"); | |
286 | return -EIO; | |
287 | } | |
288 | ||
6b7c5b94 | 289 | do { |
cf588477 SP |
290 | ready = ioread32(db); |
291 | if (ready == 0xffffffff) { | |
292 | dev_err(&adapter->pdev->dev, | |
293 | "pci slot disconnected\n"); | |
294 | return -1; | |
295 | } | |
296 | ||
297 | ready &= MPU_MAILBOX_DB_RDY_MASK; | |
6b7c5b94 SP |
298 | if (ready) |
299 | break; | |
300 | ||
f25b03a7 | 301 | if (msecs > 4000) { |
5f0b849e | 302 | dev_err(&adapter->pdev->dev, "mbox poll timed out\n"); |
18a91e60 PR |
303 | if (!lancer_chip(adapter)) |
304 | be_detect_dump_ue(adapter); | |
6b7c5b94 SP |
305 | return -1; |
306 | } | |
307 | ||
1dbf53a2 | 308 | msleep(1); |
f25b03a7 | 309 | msecs++; |
6b7c5b94 SP |
310 | } while (true); |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | /* | |
316 | * Insert the mailbox address into the doorbell in two steps | |
5fb379ee | 317 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs |
6b7c5b94 | 318 | */ |
b31c50a7 | 319 | static int be_mbox_notify_wait(struct be_adapter *adapter) |
6b7c5b94 SP |
320 | { |
321 | int status; | |
6b7c5b94 | 322 | u32 val = 0; |
8788fdc2 SP |
323 | void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; |
324 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; | |
6b7c5b94 | 325 | struct be_mcc_mailbox *mbox = mbox_mem->va; |
efd2e40a | 326 | struct be_mcc_compl *compl = &mbox->compl; |
6b7c5b94 | 327 | |
cf588477 SP |
328 | /* wait for ready to be set */ |
329 | status = be_mbox_db_ready_wait(adapter, db); | |
330 | if (status != 0) | |
331 | return status; | |
332 | ||
6b7c5b94 SP |
333 | val |= MPU_MAILBOX_DB_HI_MASK; |
334 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | |
335 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
336 | iowrite32(val, db); | |
337 | ||
338 | /* wait for ready to be set */ | |
5f0b849e | 339 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
340 | if (status != 0) |
341 | return status; | |
342 | ||
343 | val = 0; | |
6b7c5b94 SP |
344 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ |
345 | val |= (u32)(mbox_mem->dma >> 4) << 2; | |
346 | iowrite32(val, db); | |
347 | ||
5f0b849e | 348 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
349 | if (status != 0) |
350 | return status; | |
351 | ||
5fb379ee | 352 | /* A cq entry has been made now */ |
efd2e40a SP |
353 | if (be_mcc_compl_is_new(compl)) { |
354 | status = be_mcc_compl_process(adapter, &mbox->compl); | |
355 | be_mcc_compl_use(compl); | |
5fb379ee SP |
356 | if (status) |
357 | return status; | |
358 | } else { | |
5f0b849e | 359 | dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); |
6b7c5b94 SP |
360 | return -1; |
361 | } | |
5fb379ee | 362 | return 0; |
6b7c5b94 SP |
363 | } |
364 | ||
8788fdc2 | 365 | static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage) |
6b7c5b94 | 366 | { |
fe6d2a38 SP |
367 | u32 sem; |
368 | ||
369 | if (lancer_chip(adapter)) | |
370 | sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET); | |
371 | else | |
372 | sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET); | |
6b7c5b94 SP |
373 | |
374 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | |
375 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | |
376 | return -1; | |
377 | else | |
378 | return 0; | |
379 | } | |
380 | ||
8788fdc2 | 381 | int be_cmd_POST(struct be_adapter *adapter) |
6b7c5b94 | 382 | { |
43a04fdc SP |
383 | u16 stage; |
384 | int status, timeout = 0; | |
6ed35eea | 385 | struct device *dev = &adapter->pdev->dev; |
6b7c5b94 | 386 | |
43a04fdc SP |
387 | do { |
388 | status = be_POST_stage_get(adapter, &stage); | |
389 | if (status) { | |
6ed35eea | 390 | dev_err(dev, "POST error; stage=0x%x\n", stage); |
43a04fdc SP |
391 | return -1; |
392 | } else if (stage != POST_STAGE_ARMFW_RDY) { | |
6ed35eea SP |
393 | if (msleep_interruptible(2000)) { |
394 | dev_err(dev, "Waiting for POST aborted\n"); | |
395 | return -EINTR; | |
396 | } | |
43a04fdc SP |
397 | timeout += 2; |
398 | } else { | |
399 | return 0; | |
400 | } | |
d938a702 | 401 | } while (timeout < 40); |
6b7c5b94 | 402 | |
6ed35eea | 403 | dev_err(dev, "POST timeout; stage=0x%x\n", stage); |
43a04fdc | 404 | return -1; |
6b7c5b94 SP |
405 | } |
406 | ||
407 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) | |
408 | { | |
409 | return wrb->payload.embedded_payload; | |
410 | } | |
411 | ||
412 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | |
413 | { | |
414 | return &wrb->payload.sgl[0]; | |
415 | } | |
416 | ||
417 | /* Don't touch the hdr after it's prepared */ | |
418 | static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | |
d744b44e | 419 | bool embedded, u8 sge_cnt, u32 opcode) |
6b7c5b94 SP |
420 | { |
421 | if (embedded) | |
422 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
423 | else | |
424 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | |
425 | MCC_WRB_SGE_CNT_SHIFT; | |
426 | wrb->payload_length = payload_len; | |
d744b44e | 427 | wrb->tag0 = opcode; |
fa4281bb | 428 | be_dws_cpu_to_le(wrb, 8); |
6b7c5b94 SP |
429 | } |
430 | ||
431 | /* Don't touch the hdr after it's prepared */ | |
432 | static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
433 | u8 subsystem, u8 opcode, int cmd_len) | |
434 | { | |
435 | req_hdr->opcode = opcode; | |
436 | req_hdr->subsystem = subsystem; | |
437 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
07793d33 | 438 | req_hdr->version = 0; |
6b7c5b94 SP |
439 | } |
440 | ||
441 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
442 | struct be_dma_mem *mem) | |
443 | { | |
444 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
445 | u64 dma = (u64)mem->dma; | |
446 | ||
447 | for (i = 0; i < buf_pages; i++) { | |
448 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
449 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
450 | dma += PAGE_SIZE_4K; | |
451 | } | |
452 | } | |
453 | ||
454 | /* Converts interrupt delay in microseconds to multiplier value */ | |
455 | static u32 eq_delay_to_mult(u32 usec_delay) | |
456 | { | |
457 | #define MAX_INTR_RATE 651042 | |
458 | const u32 round = 10; | |
459 | u32 multiplier; | |
460 | ||
461 | if (usec_delay == 0) | |
462 | multiplier = 0; | |
463 | else { | |
464 | u32 interrupt_rate = 1000000 / usec_delay; | |
465 | /* Max delay, corresponding to the lowest interrupt rate */ | |
466 | if (interrupt_rate == 0) | |
467 | multiplier = 1023; | |
468 | else { | |
469 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
470 | multiplier /= interrupt_rate; | |
471 | /* Round the multiplier to the closest value.*/ | |
472 | multiplier = (multiplier + round/2) / round; | |
473 | multiplier = min(multiplier, (u32)1023); | |
474 | } | |
475 | } | |
476 | return multiplier; | |
477 | } | |
478 | ||
b31c50a7 | 479 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) |
6b7c5b94 | 480 | { |
b31c50a7 SP |
481 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; |
482 | struct be_mcc_wrb *wrb | |
483 | = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
484 | memset(wrb, 0, sizeof(*wrb)); | |
485 | return wrb; | |
6b7c5b94 SP |
486 | } |
487 | ||
b31c50a7 | 488 | static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) |
5fb379ee | 489 | { |
b31c50a7 SP |
490 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
491 | struct be_mcc_wrb *wrb; | |
492 | ||
713d0394 SP |
493 | if (atomic_read(&mccq->used) >= mccq->len) { |
494 | dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n"); | |
495 | return NULL; | |
496 | } | |
497 | ||
b31c50a7 SP |
498 | wrb = queue_head_node(mccq); |
499 | queue_head_inc(mccq); | |
500 | atomic_inc(&mccq->used); | |
501 | memset(wrb, 0, sizeof(*wrb)); | |
5fb379ee SP |
502 | return wrb; |
503 | } | |
504 | ||
2243e2e9 SP |
505 | /* Tell fw we're about to start firing cmds by writing a |
506 | * special pattern across the wrb hdr; uses mbox | |
507 | */ | |
508 | int be_cmd_fw_init(struct be_adapter *adapter) | |
509 | { | |
510 | u8 *wrb; | |
511 | int status; | |
512 | ||
2984961c IV |
513 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
514 | return -1; | |
2243e2e9 SP |
515 | |
516 | wrb = (u8 *)wrb_from_mbox(adapter); | |
359a972f SP |
517 | *wrb++ = 0xFF; |
518 | *wrb++ = 0x12; | |
519 | *wrb++ = 0x34; | |
520 | *wrb++ = 0xFF; | |
521 | *wrb++ = 0xFF; | |
522 | *wrb++ = 0x56; | |
523 | *wrb++ = 0x78; | |
524 | *wrb = 0xFF; | |
2243e2e9 SP |
525 | |
526 | status = be_mbox_notify_wait(adapter); | |
527 | ||
2984961c | 528 | mutex_unlock(&adapter->mbox_lock); |
2243e2e9 SP |
529 | return status; |
530 | } | |
531 | ||
532 | /* Tell fw we're done with firing cmds by writing a | |
533 | * special pattern across the wrb hdr; uses mbox | |
534 | */ | |
535 | int be_cmd_fw_clean(struct be_adapter *adapter) | |
536 | { | |
537 | u8 *wrb; | |
538 | int status; | |
539 | ||
cf588477 SP |
540 | if (adapter->eeh_err) |
541 | return -EIO; | |
542 | ||
2984961c IV |
543 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
544 | return -1; | |
2243e2e9 SP |
545 | |
546 | wrb = (u8 *)wrb_from_mbox(adapter); | |
547 | *wrb++ = 0xFF; | |
548 | *wrb++ = 0xAA; | |
549 | *wrb++ = 0xBB; | |
550 | *wrb++ = 0xFF; | |
551 | *wrb++ = 0xFF; | |
552 | *wrb++ = 0xCC; | |
553 | *wrb++ = 0xDD; | |
554 | *wrb = 0xFF; | |
555 | ||
556 | status = be_mbox_notify_wait(adapter); | |
557 | ||
2984961c | 558 | mutex_unlock(&adapter->mbox_lock); |
2243e2e9 SP |
559 | return status; |
560 | } | |
8788fdc2 | 561 | int be_cmd_eq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
562 | struct be_queue_info *eq, int eq_delay) |
563 | { | |
b31c50a7 SP |
564 | struct be_mcc_wrb *wrb; |
565 | struct be_cmd_req_eq_create *req; | |
6b7c5b94 SP |
566 | struct be_dma_mem *q_mem = &eq->dma_mem; |
567 | int status; | |
568 | ||
2984961c IV |
569 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
570 | return -1; | |
b31c50a7 SP |
571 | |
572 | wrb = wrb_from_mbox(adapter); | |
573 | req = embedded_payload(wrb); | |
6b7c5b94 | 574 | |
d744b44e | 575 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE); |
6b7c5b94 SP |
576 | |
577 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
578 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | |
579 | ||
580 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
581 | ||
6b7c5b94 SP |
582 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); |
583 | /* 4byte eqe*/ | |
584 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
585 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
586 | __ilog2_u32(eq->len/256)); | |
587 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
588 | eq_delay_to_mult(eq_delay)); | |
589 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
590 | ||
591 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
592 | ||
b31c50a7 | 593 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 594 | if (!status) { |
b31c50a7 | 595 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
596 | eq->id = le16_to_cpu(resp->eq_id); |
597 | eq->created = true; | |
598 | } | |
b31c50a7 | 599 | |
2984961c | 600 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
601 | return status; |
602 | } | |
603 | ||
b31c50a7 | 604 | /* Uses mbox */ |
8788fdc2 | 605 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
606 | u8 type, bool permanent, u32 if_handle) |
607 | { | |
b31c50a7 SP |
608 | struct be_mcc_wrb *wrb; |
609 | struct be_cmd_req_mac_query *req; | |
6b7c5b94 SP |
610 | int status; |
611 | ||
2984961c IV |
612 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
613 | return -1; | |
b31c50a7 SP |
614 | |
615 | wrb = wrb_from_mbox(adapter); | |
616 | req = embedded_payload(wrb); | |
6b7c5b94 | 617 | |
d744b44e AK |
618 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
619 | OPCODE_COMMON_NTWK_MAC_QUERY); | |
6b7c5b94 SP |
620 | |
621 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
622 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); | |
623 | ||
624 | req->type = type; | |
625 | if (permanent) { | |
626 | req->permanent = 1; | |
627 | } else { | |
b31c50a7 | 628 | req->if_id = cpu_to_le16((u16) if_handle); |
6b7c5b94 SP |
629 | req->permanent = 0; |
630 | } | |
631 | ||
b31c50a7 SP |
632 | status = be_mbox_notify_wait(adapter); |
633 | if (!status) { | |
634 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | |
6b7c5b94 | 635 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); |
b31c50a7 | 636 | } |
6b7c5b94 | 637 | |
2984961c | 638 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
639 | return status; |
640 | } | |
641 | ||
b31c50a7 | 642 | /* Uses synchronous MCCQ */ |
8788fdc2 | 643 | int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
f8617e08 | 644 | u32 if_id, u32 *pmac_id, u32 domain) |
6b7c5b94 | 645 | { |
b31c50a7 SP |
646 | struct be_mcc_wrb *wrb; |
647 | struct be_cmd_req_pmac_add *req; | |
6b7c5b94 SP |
648 | int status; |
649 | ||
b31c50a7 SP |
650 | spin_lock_bh(&adapter->mcc_lock); |
651 | ||
652 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
653 | if (!wrb) { |
654 | status = -EBUSY; | |
655 | goto err; | |
656 | } | |
b31c50a7 | 657 | req = embedded_payload(wrb); |
6b7c5b94 | 658 | |
d744b44e AK |
659 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
660 | OPCODE_COMMON_NTWK_PMAC_ADD); | |
6b7c5b94 SP |
661 | |
662 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
663 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); | |
664 | ||
f8617e08 | 665 | req->hdr.domain = domain; |
6b7c5b94 SP |
666 | req->if_id = cpu_to_le32(if_id); |
667 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | |
668 | ||
b31c50a7 | 669 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
670 | if (!status) { |
671 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | |
672 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
673 | } | |
674 | ||
713d0394 | 675 | err: |
b31c50a7 | 676 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
677 | return status; |
678 | } | |
679 | ||
b31c50a7 | 680 | /* Uses synchronous MCCQ */ |
f8617e08 | 681 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom) |
6b7c5b94 | 682 | { |
b31c50a7 SP |
683 | struct be_mcc_wrb *wrb; |
684 | struct be_cmd_req_pmac_del *req; | |
6b7c5b94 SP |
685 | int status; |
686 | ||
b31c50a7 SP |
687 | spin_lock_bh(&adapter->mcc_lock); |
688 | ||
689 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
690 | if (!wrb) { |
691 | status = -EBUSY; | |
692 | goto err; | |
693 | } | |
b31c50a7 | 694 | req = embedded_payload(wrb); |
6b7c5b94 | 695 | |
d744b44e AK |
696 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
697 | OPCODE_COMMON_NTWK_PMAC_DEL); | |
6b7c5b94 SP |
698 | |
699 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
700 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); | |
701 | ||
f8617e08 | 702 | req->hdr.domain = dom; |
6b7c5b94 SP |
703 | req->if_id = cpu_to_le32(if_id); |
704 | req->pmac_id = cpu_to_le32(pmac_id); | |
705 | ||
b31c50a7 SP |
706 | status = be_mcc_notify_wait(adapter); |
707 | ||
713d0394 | 708 | err: |
b31c50a7 | 709 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
710 | return status; |
711 | } | |
712 | ||
b31c50a7 | 713 | /* Uses Mbox */ |
8788fdc2 | 714 | int be_cmd_cq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
715 | struct be_queue_info *cq, struct be_queue_info *eq, |
716 | bool sol_evts, bool no_delay, int coalesce_wm) | |
717 | { | |
b31c50a7 SP |
718 | struct be_mcc_wrb *wrb; |
719 | struct be_cmd_req_cq_create *req; | |
6b7c5b94 | 720 | struct be_dma_mem *q_mem = &cq->dma_mem; |
b31c50a7 | 721 | void *ctxt; |
6b7c5b94 SP |
722 | int status; |
723 | ||
2984961c IV |
724 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
725 | return -1; | |
b31c50a7 SP |
726 | |
727 | wrb = wrb_from_mbox(adapter); | |
728 | req = embedded_payload(wrb); | |
729 | ctxt = &req->context; | |
6b7c5b94 | 730 | |
d744b44e AK |
731 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
732 | OPCODE_COMMON_CQ_CREATE); | |
6b7c5b94 SP |
733 | |
734 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
735 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | |
736 | ||
737 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
fe6d2a38 | 738 | if (lancer_chip(adapter)) { |
8b7756ca | 739 | req->hdr.version = 2; |
fe6d2a38 | 740 | req->page_size = 1; /* 1 for 4K */ |
fe6d2a38 SP |
741 | AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt, |
742 | no_delay); | |
743 | AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt, | |
744 | __ilog2_u32(cq->len/256)); | |
745 | AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1); | |
746 | AMAP_SET_BITS(struct amap_cq_context_lancer, eventable, | |
747 | ctxt, 1); | |
748 | AMAP_SET_BITS(struct amap_cq_context_lancer, eqid, | |
749 | ctxt, eq->id); | |
750 | AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1); | |
751 | } else { | |
752 | AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, | |
753 | coalesce_wm); | |
754 | AMAP_SET_BITS(struct amap_cq_context_be, nodelay, | |
755 | ctxt, no_delay); | |
756 | AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, | |
757 | __ilog2_u32(cq->len/256)); | |
758 | AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); | |
759 | AMAP_SET_BITS(struct amap_cq_context_be, solevent, | |
760 | ctxt, sol_evts); | |
761 | AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); | |
762 | AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); | |
763 | AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1); | |
764 | } | |
6b7c5b94 | 765 | |
6b7c5b94 SP |
766 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
767 | ||
768 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
769 | ||
b31c50a7 | 770 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 771 | if (!status) { |
b31c50a7 | 772 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
773 | cq->id = le16_to_cpu(resp->cq_id); |
774 | cq->created = true; | |
775 | } | |
b31c50a7 | 776 | |
2984961c | 777 | mutex_unlock(&adapter->mbox_lock); |
5fb379ee SP |
778 | |
779 | return status; | |
780 | } | |
781 | ||
782 | static u32 be_encoded_q_len(int q_len) | |
783 | { | |
784 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
785 | if (len_encoded == 16) | |
786 | len_encoded = 0; | |
787 | return len_encoded; | |
788 | } | |
789 | ||
34b1ef04 | 790 | int be_cmd_mccq_ext_create(struct be_adapter *adapter, |
5fb379ee SP |
791 | struct be_queue_info *mccq, |
792 | struct be_queue_info *cq) | |
793 | { | |
b31c50a7 | 794 | struct be_mcc_wrb *wrb; |
34b1ef04 | 795 | struct be_cmd_req_mcc_ext_create *req; |
5fb379ee | 796 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
b31c50a7 | 797 | void *ctxt; |
5fb379ee SP |
798 | int status; |
799 | ||
2984961c IV |
800 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
801 | return -1; | |
b31c50a7 SP |
802 | |
803 | wrb = wrb_from_mbox(adapter); | |
804 | req = embedded_payload(wrb); | |
805 | ctxt = &req->context; | |
5fb379ee | 806 | |
d744b44e | 807 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
cc4ce020 | 808 | OPCODE_COMMON_MCC_CREATE_EXT); |
5fb379ee SP |
809 | |
810 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
cc4ce020 | 811 | OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req)); |
5fb379ee | 812 | |
d4a2ac3e | 813 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); |
fe6d2a38 SP |
814 | if (lancer_chip(adapter)) { |
815 | req->hdr.version = 1; | |
816 | req->cq_id = cpu_to_le16(cq->id); | |
817 | ||
818 | AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt, | |
819 | be_encoded_q_len(mccq->len)); | |
820 | AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1); | |
821 | AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id, | |
822 | ctxt, cq->id); | |
823 | AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid, | |
824 | ctxt, 1); | |
825 | ||
826 | } else { | |
827 | AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); | |
828 | AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, | |
829 | be_encoded_q_len(mccq->len)); | |
830 | AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); | |
831 | } | |
5fb379ee | 832 | |
cc4ce020 | 833 | /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ |
fe6d2a38 | 834 | req->async_event_bitmap[0] = cpu_to_le32(0x00000022); |
5fb379ee SP |
835 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
836 | ||
837 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
838 | ||
b31c50a7 | 839 | status = be_mbox_notify_wait(adapter); |
5fb379ee SP |
840 | if (!status) { |
841 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
842 | mccq->id = le16_to_cpu(resp->id); | |
843 | mccq->created = true; | |
844 | } | |
2984961c | 845 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
846 | |
847 | return status; | |
848 | } | |
849 | ||
34b1ef04 SK |
850 | int be_cmd_mccq_org_create(struct be_adapter *adapter, |
851 | struct be_queue_info *mccq, | |
852 | struct be_queue_info *cq) | |
853 | { | |
854 | struct be_mcc_wrb *wrb; | |
855 | struct be_cmd_req_mcc_create *req; | |
856 | struct be_dma_mem *q_mem = &mccq->dma_mem; | |
857 | void *ctxt; | |
858 | int status; | |
859 | ||
860 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | |
861 | return -1; | |
862 | ||
863 | wrb = wrb_from_mbox(adapter); | |
864 | req = embedded_payload(wrb); | |
865 | ctxt = &req->context; | |
866 | ||
867 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
868 | OPCODE_COMMON_MCC_CREATE); | |
869 | ||
870 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
871 | OPCODE_COMMON_MCC_CREATE, sizeof(*req)); | |
872 | ||
873 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
874 | ||
875 | AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); | |
876 | AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, | |
877 | be_encoded_q_len(mccq->len)); | |
878 | AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); | |
879 | ||
880 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
881 | ||
882 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
883 | ||
884 | status = be_mbox_notify_wait(adapter); | |
885 | if (!status) { | |
886 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
887 | mccq->id = le16_to_cpu(resp->id); | |
888 | mccq->created = true; | |
889 | } | |
890 | ||
891 | mutex_unlock(&adapter->mbox_lock); | |
892 | return status; | |
893 | } | |
894 | ||
895 | int be_cmd_mccq_create(struct be_adapter *adapter, | |
896 | struct be_queue_info *mccq, | |
897 | struct be_queue_info *cq) | |
898 | { | |
899 | int status; | |
900 | ||
901 | status = be_cmd_mccq_ext_create(adapter, mccq, cq); | |
902 | if (status && !lancer_chip(adapter)) { | |
903 | dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 " | |
904 | "or newer to avoid conflicting priorities between NIC " | |
905 | "and FCoE traffic"); | |
906 | status = be_cmd_mccq_org_create(adapter, mccq, cq); | |
907 | } | |
908 | return status; | |
909 | } | |
910 | ||
8788fdc2 | 911 | int be_cmd_txq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
912 | struct be_queue_info *txq, |
913 | struct be_queue_info *cq) | |
914 | { | |
b31c50a7 SP |
915 | struct be_mcc_wrb *wrb; |
916 | struct be_cmd_req_eth_tx_create *req; | |
6b7c5b94 | 917 | struct be_dma_mem *q_mem = &txq->dma_mem; |
b31c50a7 | 918 | void *ctxt; |
6b7c5b94 | 919 | int status; |
6b7c5b94 | 920 | |
2984961c IV |
921 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
922 | return -1; | |
b31c50a7 SP |
923 | |
924 | wrb = wrb_from_mbox(adapter); | |
925 | req = embedded_payload(wrb); | |
926 | ctxt = &req->context; | |
6b7c5b94 | 927 | |
d744b44e AK |
928 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
929 | OPCODE_ETH_TX_CREATE); | |
6b7c5b94 SP |
930 | |
931 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, | |
932 | sizeof(*req)); | |
933 | ||
8b7756ca PR |
934 | if (lancer_chip(adapter)) { |
935 | req->hdr.version = 1; | |
936 | AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt, | |
937 | adapter->if_handle); | |
938 | } | |
939 | ||
6b7c5b94 SP |
940 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); |
941 | req->ulp_num = BE_ULP1_NUM; | |
942 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | |
943 | ||
b31c50a7 SP |
944 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, |
945 | be_encoded_q_len(txq->len)); | |
6b7c5b94 SP |
946 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); |
947 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | |
948 | ||
949 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
950 | ||
951 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
952 | ||
b31c50a7 | 953 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
954 | if (!status) { |
955 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | |
956 | txq->id = le16_to_cpu(resp->cid); | |
957 | txq->created = true; | |
958 | } | |
b31c50a7 | 959 | |
2984961c | 960 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
961 | |
962 | return status; | |
963 | } | |
964 | ||
482c9e79 | 965 | /* Uses MCC */ |
8788fdc2 | 966 | int be_cmd_rxq_create(struct be_adapter *adapter, |
6b7c5b94 | 967 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, |
3abcdeda | 968 | u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id) |
6b7c5b94 | 969 | { |
b31c50a7 SP |
970 | struct be_mcc_wrb *wrb; |
971 | struct be_cmd_req_eth_rx_create *req; | |
6b7c5b94 SP |
972 | struct be_dma_mem *q_mem = &rxq->dma_mem; |
973 | int status; | |
974 | ||
482c9e79 | 975 | spin_lock_bh(&adapter->mcc_lock); |
b31c50a7 | 976 | |
482c9e79 SP |
977 | wrb = wrb_from_mccq(adapter); |
978 | if (!wrb) { | |
979 | status = -EBUSY; | |
980 | goto err; | |
981 | } | |
b31c50a7 | 982 | req = embedded_payload(wrb); |
6b7c5b94 | 983 | |
d744b44e AK |
984 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
985 | OPCODE_ETH_RX_CREATE); | |
6b7c5b94 SP |
986 | |
987 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, | |
988 | sizeof(*req)); | |
989 | ||
990 | req->cq_id = cpu_to_le16(cq_id); | |
991 | req->frag_size = fls(frag_size) - 1; | |
992 | req->num_pages = 2; | |
993 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
994 | req->interface_id = cpu_to_le32(if_id); | |
995 | req->max_frame_size = cpu_to_le16(max_frame_size); | |
996 | req->rss_queue = cpu_to_le32(rss); | |
997 | ||
482c9e79 | 998 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
999 | if (!status) { |
1000 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | |
1001 | rxq->id = le16_to_cpu(resp->id); | |
1002 | rxq->created = true; | |
3abcdeda | 1003 | *rss_id = resp->rss_id; |
6b7c5b94 | 1004 | } |
b31c50a7 | 1005 | |
482c9e79 SP |
1006 | err: |
1007 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1008 | return status; |
1009 | } | |
1010 | ||
b31c50a7 SP |
1011 | /* Generic destroyer function for all types of queues |
1012 | * Uses Mbox | |
1013 | */ | |
8788fdc2 | 1014 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
6b7c5b94 SP |
1015 | int queue_type) |
1016 | { | |
b31c50a7 SP |
1017 | struct be_mcc_wrb *wrb; |
1018 | struct be_cmd_req_q_destroy *req; | |
6b7c5b94 SP |
1019 | u8 subsys = 0, opcode = 0; |
1020 | int status; | |
1021 | ||
cf588477 SP |
1022 | if (adapter->eeh_err) |
1023 | return -EIO; | |
1024 | ||
2984961c IV |
1025 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1026 | return -1; | |
6b7c5b94 | 1027 | |
b31c50a7 SP |
1028 | wrb = wrb_from_mbox(adapter); |
1029 | req = embedded_payload(wrb); | |
1030 | ||
6b7c5b94 SP |
1031 | switch (queue_type) { |
1032 | case QTYPE_EQ: | |
1033 | subsys = CMD_SUBSYSTEM_COMMON; | |
1034 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
1035 | break; | |
1036 | case QTYPE_CQ: | |
1037 | subsys = CMD_SUBSYSTEM_COMMON; | |
1038 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
1039 | break; | |
1040 | case QTYPE_TXQ: | |
1041 | subsys = CMD_SUBSYSTEM_ETH; | |
1042 | opcode = OPCODE_ETH_TX_DESTROY; | |
1043 | break; | |
1044 | case QTYPE_RXQ: | |
1045 | subsys = CMD_SUBSYSTEM_ETH; | |
1046 | opcode = OPCODE_ETH_RX_DESTROY; | |
1047 | break; | |
5fb379ee SP |
1048 | case QTYPE_MCCQ: |
1049 | subsys = CMD_SUBSYSTEM_COMMON; | |
1050 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
1051 | break; | |
6b7c5b94 | 1052 | default: |
5f0b849e | 1053 | BUG(); |
6b7c5b94 | 1054 | } |
d744b44e AK |
1055 | |
1056 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode); | |
1057 | ||
6b7c5b94 SP |
1058 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); |
1059 | req->id = cpu_to_le16(q->id); | |
1060 | ||
b31c50a7 | 1061 | status = be_mbox_notify_wait(adapter); |
482c9e79 SP |
1062 | if (!status) |
1063 | q->created = false; | |
5f0b849e | 1064 | |
2984961c | 1065 | mutex_unlock(&adapter->mbox_lock); |
482c9e79 SP |
1066 | return status; |
1067 | } | |
6b7c5b94 | 1068 | |
482c9e79 SP |
1069 | /* Uses MCC */ |
1070 | int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q) | |
1071 | { | |
1072 | struct be_mcc_wrb *wrb; | |
1073 | struct be_cmd_req_q_destroy *req; | |
1074 | int status; | |
1075 | ||
1076 | spin_lock_bh(&adapter->mcc_lock); | |
1077 | ||
1078 | wrb = wrb_from_mccq(adapter); | |
1079 | if (!wrb) { | |
1080 | status = -EBUSY; | |
1081 | goto err; | |
1082 | } | |
1083 | req = embedded_payload(wrb); | |
1084 | ||
1085 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_RX_DESTROY); | |
1086 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_DESTROY, | |
1087 | sizeof(*req)); | |
1088 | req->id = cpu_to_le16(q->id); | |
1089 | ||
1090 | status = be_mcc_notify_wait(adapter); | |
1091 | if (!status) | |
1092 | q->created = false; | |
1093 | ||
1094 | err: | |
1095 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1096 | return status; |
1097 | } | |
1098 | ||
b31c50a7 SP |
1099 | /* Create an rx filtering policy configuration on an i/f |
1100 | * Uses mbox | |
1101 | */ | |
73d540f2 | 1102 | int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, |
ba343c77 SB |
1103 | u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id, |
1104 | u32 domain) | |
6b7c5b94 | 1105 | { |
b31c50a7 SP |
1106 | struct be_mcc_wrb *wrb; |
1107 | struct be_cmd_req_if_create *req; | |
6b7c5b94 SP |
1108 | int status; |
1109 | ||
2984961c IV |
1110 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1111 | return -1; | |
b31c50a7 SP |
1112 | |
1113 | wrb = wrb_from_mbox(adapter); | |
1114 | req = embedded_payload(wrb); | |
6b7c5b94 | 1115 | |
d744b44e AK |
1116 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1117 | OPCODE_COMMON_NTWK_INTERFACE_CREATE); | |
6b7c5b94 SP |
1118 | |
1119 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1120 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); | |
1121 | ||
ba343c77 | 1122 | req->hdr.domain = domain; |
73d540f2 SP |
1123 | req->capability_flags = cpu_to_le32(cap_flags); |
1124 | req->enable_flags = cpu_to_le32(en_flags); | |
b31c50a7 | 1125 | req->pmac_invalid = pmac_invalid; |
6b7c5b94 SP |
1126 | if (!pmac_invalid) |
1127 | memcpy(req->mac_addr, mac, ETH_ALEN); | |
1128 | ||
b31c50a7 | 1129 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1130 | if (!status) { |
1131 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | |
1132 | *if_handle = le32_to_cpu(resp->interface_id); | |
1133 | if (!pmac_invalid) | |
1134 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
1135 | } | |
1136 | ||
2984961c | 1137 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1138 | return status; |
1139 | } | |
1140 | ||
b31c50a7 | 1141 | /* Uses mbox */ |
658681f7 | 1142 | int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain) |
6b7c5b94 | 1143 | { |
b31c50a7 SP |
1144 | struct be_mcc_wrb *wrb; |
1145 | struct be_cmd_req_if_destroy *req; | |
6b7c5b94 SP |
1146 | int status; |
1147 | ||
cf588477 SP |
1148 | if (adapter->eeh_err) |
1149 | return -EIO; | |
1150 | ||
2984961c IV |
1151 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1152 | return -1; | |
b31c50a7 SP |
1153 | |
1154 | wrb = wrb_from_mbox(adapter); | |
1155 | req = embedded_payload(wrb); | |
6b7c5b94 | 1156 | |
d744b44e AK |
1157 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1158 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY); | |
6b7c5b94 SP |
1159 | |
1160 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1161 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | |
1162 | ||
658681f7 | 1163 | req->hdr.domain = domain; |
6b7c5b94 | 1164 | req->interface_id = cpu_to_le32(interface_id); |
b31c50a7 SP |
1165 | |
1166 | status = be_mbox_notify_wait(adapter); | |
6b7c5b94 | 1167 | |
2984961c | 1168 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1169 | |
1170 | return status; | |
1171 | } | |
1172 | ||
1173 | /* Get stats is a non embedded command: the request is not embedded inside | |
1174 | * WRB but is a separate dma memory block | |
b31c50a7 | 1175 | * Uses asynchronous MCC |
6b7c5b94 | 1176 | */ |
8788fdc2 | 1177 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) |
6b7c5b94 | 1178 | { |
b31c50a7 | 1179 | struct be_mcc_wrb *wrb; |
89a88ab8 | 1180 | struct be_cmd_req_hdr *hdr; |
b31c50a7 | 1181 | struct be_sge *sge; |
713d0394 | 1182 | int status = 0; |
6b7c5b94 | 1183 | |
609ff3bb AK |
1184 | if (MODULO(adapter->work_counter, be_get_temp_freq) == 0) |
1185 | be_cmd_get_die_temperature(adapter); | |
1186 | ||
b31c50a7 | 1187 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1188 | |
b31c50a7 | 1189 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1190 | if (!wrb) { |
1191 | status = -EBUSY; | |
1192 | goto err; | |
1193 | } | |
89a88ab8 | 1194 | hdr = nonemb_cmd->va; |
b31c50a7 | 1195 | sge = nonembedded_sgl(wrb); |
6b7c5b94 | 1196 | |
89a88ab8 | 1197 | be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1, |
d744b44e | 1198 | OPCODE_ETH_GET_STATISTICS); |
6b7c5b94 | 1199 | |
89a88ab8 AK |
1200 | be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, |
1201 | OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size); | |
1202 | ||
1203 | if (adapter->generation == BE_GEN3) | |
1204 | hdr->version = 1; | |
1205 | ||
6349935b | 1206 | wrb->tag1 = CMD_SUBSYSTEM_ETH; |
6b7c5b94 SP |
1207 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); |
1208 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1209 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1210 | ||
b31c50a7 | 1211 | be_mcc_notify(adapter); |
b2aebe6d | 1212 | adapter->stats_cmd_sent = true; |
6b7c5b94 | 1213 | |
713d0394 | 1214 | err: |
b31c50a7 | 1215 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 1216 | return status; |
6b7c5b94 SP |
1217 | } |
1218 | ||
005d5696 SX |
1219 | /* Lancer Stats */ |
1220 | int lancer_cmd_get_pport_stats(struct be_adapter *adapter, | |
1221 | struct be_dma_mem *nonemb_cmd) | |
1222 | { | |
1223 | ||
1224 | struct be_mcc_wrb *wrb; | |
1225 | struct lancer_cmd_req_pport_stats *req; | |
1226 | struct be_sge *sge; | |
1227 | int status = 0; | |
1228 | ||
1229 | spin_lock_bh(&adapter->mcc_lock); | |
1230 | ||
1231 | wrb = wrb_from_mccq(adapter); | |
1232 | if (!wrb) { | |
1233 | status = -EBUSY; | |
1234 | goto err; | |
1235 | } | |
1236 | req = nonemb_cmd->va; | |
1237 | sge = nonembedded_sgl(wrb); | |
1238 | ||
1239 | be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1, | |
1240 | OPCODE_ETH_GET_PPORT_STATS); | |
1241 | ||
1242 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1243 | OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size); | |
1244 | ||
1245 | ||
1246 | req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num); | |
1247 | req->cmd_params.params.reset_stats = 0; | |
1248 | ||
1249 | wrb->tag1 = CMD_SUBSYSTEM_ETH; | |
1250 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
1251 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1252 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1253 | ||
1254 | be_mcc_notify(adapter); | |
1255 | adapter->stats_cmd_sent = true; | |
1256 | ||
1257 | err: | |
1258 | spin_unlock_bh(&adapter->mcc_lock); | |
1259 | return status; | |
1260 | } | |
1261 | ||
b31c50a7 | 1262 | /* Uses synchronous mcc */ |
ea172a01 SP |
1263 | int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, |
1264 | u16 *link_speed, u32 dom) | |
6b7c5b94 | 1265 | { |
b31c50a7 SP |
1266 | struct be_mcc_wrb *wrb; |
1267 | struct be_cmd_req_link_status *req; | |
6b7c5b94 SP |
1268 | int status; |
1269 | ||
b31c50a7 SP |
1270 | spin_lock_bh(&adapter->mcc_lock); |
1271 | ||
1272 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1273 | if (!wrb) { |
1274 | status = -EBUSY; | |
1275 | goto err; | |
1276 | } | |
b31c50a7 | 1277 | req = embedded_payload(wrb); |
a8f447bd | 1278 | |
d744b44e AK |
1279 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1280 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY); | |
6b7c5b94 SP |
1281 | |
1282 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1283 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | |
1284 | ||
b31c50a7 | 1285 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1286 | if (!status) { |
1287 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | |
0388f251 | 1288 | if (resp->mac_speed != PHY_LINK_SPEED_ZERO) { |
0388f251 SB |
1289 | *link_speed = le16_to_cpu(resp->link_speed); |
1290 | *mac_speed = resp->mac_speed; | |
1291 | } | |
6b7c5b94 SP |
1292 | } |
1293 | ||
713d0394 | 1294 | err: |
b31c50a7 | 1295 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1296 | return status; |
1297 | } | |
1298 | ||
609ff3bb AK |
1299 | /* Uses synchronous mcc */ |
1300 | int be_cmd_get_die_temperature(struct be_adapter *adapter) | |
1301 | { | |
1302 | struct be_mcc_wrb *wrb; | |
1303 | struct be_cmd_req_get_cntl_addnl_attribs *req; | |
1304 | int status; | |
1305 | ||
1306 | spin_lock_bh(&adapter->mcc_lock); | |
1307 | ||
1308 | wrb = wrb_from_mccq(adapter); | |
1309 | if (!wrb) { | |
1310 | status = -EBUSY; | |
1311 | goto err; | |
1312 | } | |
1313 | req = embedded_payload(wrb); | |
1314 | ||
1315 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1316 | OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES); | |
1317 | ||
1318 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1319 | OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req)); | |
1320 | ||
1321 | status = be_mcc_notify_wait(adapter); | |
1322 | if (!status) { | |
1323 | struct be_cmd_resp_get_cntl_addnl_attribs *resp = | |
1324 | embedded_payload(wrb); | |
1325 | adapter->drv_stats.be_on_die_temperature = | |
1326 | resp->on_die_temperature; | |
1327 | } | |
1328 | /* If IOCTL fails once, do not bother issuing it again */ | |
1329 | else | |
1330 | be_get_temp_freq = 0; | |
1331 | ||
1332 | err: | |
1333 | spin_unlock_bh(&adapter->mcc_lock); | |
1334 | return status; | |
1335 | } | |
1336 | ||
311fddc7 SK |
1337 | /* Uses synchronous mcc */ |
1338 | int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size) | |
1339 | { | |
1340 | struct be_mcc_wrb *wrb; | |
1341 | struct be_cmd_req_get_fat *req; | |
1342 | int status; | |
1343 | ||
1344 | spin_lock_bh(&adapter->mcc_lock); | |
1345 | ||
1346 | wrb = wrb_from_mccq(adapter); | |
1347 | if (!wrb) { | |
1348 | status = -EBUSY; | |
1349 | goto err; | |
1350 | } | |
1351 | req = embedded_payload(wrb); | |
1352 | ||
1353 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1354 | OPCODE_COMMON_MANAGE_FAT); | |
1355 | ||
1356 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1357 | OPCODE_COMMON_MANAGE_FAT, sizeof(*req)); | |
1358 | req->fat_operation = cpu_to_le32(QUERY_FAT); | |
1359 | status = be_mcc_notify_wait(adapter); | |
1360 | if (!status) { | |
1361 | struct be_cmd_resp_get_fat *resp = embedded_payload(wrb); | |
1362 | if (log_size && resp->log_size) | |
fe2a70ee SK |
1363 | *log_size = le32_to_cpu(resp->log_size) - |
1364 | sizeof(u32); | |
311fddc7 SK |
1365 | } |
1366 | err: | |
1367 | spin_unlock_bh(&adapter->mcc_lock); | |
1368 | return status; | |
1369 | } | |
1370 | ||
1371 | void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) | |
1372 | { | |
1373 | struct be_dma_mem get_fat_cmd; | |
1374 | struct be_mcc_wrb *wrb; | |
1375 | struct be_cmd_req_get_fat *req; | |
1376 | struct be_sge *sge; | |
fe2a70ee SK |
1377 | u32 offset = 0, total_size, buf_size, |
1378 | log_offset = sizeof(u32), payload_len; | |
311fddc7 SK |
1379 | int status; |
1380 | ||
1381 | if (buf_len == 0) | |
1382 | return; | |
1383 | ||
1384 | total_size = buf_len; | |
1385 | ||
fe2a70ee SK |
1386 | get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; |
1387 | get_fat_cmd.va = pci_alloc_consistent(adapter->pdev, | |
1388 | get_fat_cmd.size, | |
1389 | &get_fat_cmd.dma); | |
1390 | if (!get_fat_cmd.va) { | |
1391 | status = -ENOMEM; | |
1392 | dev_err(&adapter->pdev->dev, | |
1393 | "Memory allocation failure while retrieving FAT data\n"); | |
1394 | return; | |
1395 | } | |
1396 | ||
311fddc7 SK |
1397 | spin_lock_bh(&adapter->mcc_lock); |
1398 | ||
311fddc7 SK |
1399 | while (total_size) { |
1400 | buf_size = min(total_size, (u32)60*1024); | |
1401 | total_size -= buf_size; | |
1402 | ||
fe2a70ee SK |
1403 | wrb = wrb_from_mccq(adapter); |
1404 | if (!wrb) { | |
1405 | status = -EBUSY; | |
311fddc7 SK |
1406 | goto err; |
1407 | } | |
1408 | req = get_fat_cmd.va; | |
1409 | sge = nonembedded_sgl(wrb); | |
1410 | ||
fe2a70ee SK |
1411 | payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; |
1412 | be_wrb_hdr_prepare(wrb, payload_len, false, 1, | |
311fddc7 SK |
1413 | OPCODE_COMMON_MANAGE_FAT); |
1414 | ||
1415 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
fe2a70ee | 1416 | OPCODE_COMMON_MANAGE_FAT, payload_len); |
311fddc7 | 1417 | |
fe2a70ee | 1418 | sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma)); |
311fddc7 SK |
1419 | sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF); |
1420 | sge->len = cpu_to_le32(get_fat_cmd.size); | |
1421 | ||
1422 | req->fat_operation = cpu_to_le32(RETRIEVE_FAT); | |
1423 | req->read_log_offset = cpu_to_le32(log_offset); | |
1424 | req->read_log_length = cpu_to_le32(buf_size); | |
1425 | req->data_buffer_size = cpu_to_le32(buf_size); | |
1426 | ||
1427 | status = be_mcc_notify_wait(adapter); | |
1428 | if (!status) { | |
1429 | struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; | |
1430 | memcpy(buf + offset, | |
1431 | resp->data_buffer, | |
1432 | resp->read_log_length); | |
fe2a70ee | 1433 | } else { |
311fddc7 | 1434 | dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); |
fe2a70ee SK |
1435 | goto err; |
1436 | } | |
311fddc7 SK |
1437 | offset += buf_size; |
1438 | log_offset += buf_size; | |
1439 | } | |
1440 | err: | |
fe2a70ee SK |
1441 | pci_free_consistent(adapter->pdev, get_fat_cmd.size, |
1442 | get_fat_cmd.va, | |
1443 | get_fat_cmd.dma); | |
311fddc7 SK |
1444 | spin_unlock_bh(&adapter->mcc_lock); |
1445 | } | |
1446 | ||
b31c50a7 | 1447 | /* Uses Mbox */ |
8788fdc2 | 1448 | int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver) |
6b7c5b94 | 1449 | { |
b31c50a7 SP |
1450 | struct be_mcc_wrb *wrb; |
1451 | struct be_cmd_req_get_fw_version *req; | |
6b7c5b94 SP |
1452 | int status; |
1453 | ||
2984961c IV |
1454 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1455 | return -1; | |
b31c50a7 SP |
1456 | |
1457 | wrb = wrb_from_mbox(adapter); | |
1458 | req = embedded_payload(wrb); | |
6b7c5b94 | 1459 | |
d744b44e AK |
1460 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1461 | OPCODE_COMMON_GET_FW_VERSION); | |
6b7c5b94 SP |
1462 | |
1463 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1464 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | |
1465 | ||
b31c50a7 | 1466 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1467 | if (!status) { |
1468 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | |
1469 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | |
1470 | } | |
1471 | ||
2984961c | 1472 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1473 | return status; |
1474 | } | |
1475 | ||
b31c50a7 SP |
1476 | /* set the EQ delay interval of an EQ to specified value |
1477 | * Uses async mcc | |
1478 | */ | |
8788fdc2 | 1479 | int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) |
6b7c5b94 | 1480 | { |
b31c50a7 SP |
1481 | struct be_mcc_wrb *wrb; |
1482 | struct be_cmd_req_modify_eq_delay *req; | |
713d0394 | 1483 | int status = 0; |
6b7c5b94 | 1484 | |
b31c50a7 SP |
1485 | spin_lock_bh(&adapter->mcc_lock); |
1486 | ||
1487 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1488 | if (!wrb) { |
1489 | status = -EBUSY; | |
1490 | goto err; | |
1491 | } | |
b31c50a7 | 1492 | req = embedded_payload(wrb); |
6b7c5b94 | 1493 | |
d744b44e AK |
1494 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1495 | OPCODE_COMMON_MODIFY_EQ_DELAY); | |
6b7c5b94 SP |
1496 | |
1497 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1498 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); | |
1499 | ||
1500 | req->num_eq = cpu_to_le32(1); | |
1501 | req->delay[0].eq_id = cpu_to_le32(eq_id); | |
1502 | req->delay[0].phase = 0; | |
1503 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | |
1504 | ||
b31c50a7 | 1505 | be_mcc_notify(adapter); |
6b7c5b94 | 1506 | |
713d0394 | 1507 | err: |
b31c50a7 | 1508 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 1509 | return status; |
6b7c5b94 SP |
1510 | } |
1511 | ||
b31c50a7 | 1512 | /* Uses sycnhronous mcc */ |
8788fdc2 | 1513 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
6b7c5b94 SP |
1514 | u32 num, bool untagged, bool promiscuous) |
1515 | { | |
b31c50a7 SP |
1516 | struct be_mcc_wrb *wrb; |
1517 | struct be_cmd_req_vlan_config *req; | |
6b7c5b94 SP |
1518 | int status; |
1519 | ||
b31c50a7 SP |
1520 | spin_lock_bh(&adapter->mcc_lock); |
1521 | ||
1522 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1523 | if (!wrb) { |
1524 | status = -EBUSY; | |
1525 | goto err; | |
1526 | } | |
b31c50a7 | 1527 | req = embedded_payload(wrb); |
6b7c5b94 | 1528 | |
d744b44e AK |
1529 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1530 | OPCODE_COMMON_NTWK_VLAN_CONFIG); | |
6b7c5b94 SP |
1531 | |
1532 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1533 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); | |
1534 | ||
1535 | req->interface_id = if_id; | |
1536 | req->promiscuous = promiscuous; | |
1537 | req->untagged = untagged; | |
1538 | req->num_vlan = num; | |
1539 | if (!promiscuous) { | |
1540 | memcpy(req->normal_vlan, vtag_array, | |
1541 | req->num_vlan * sizeof(vtag_array[0])); | |
1542 | } | |
1543 | ||
b31c50a7 | 1544 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1545 | |
713d0394 | 1546 | err: |
b31c50a7 | 1547 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1548 | return status; |
1549 | } | |
1550 | ||
5b8821b7 | 1551 | int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) |
6b7c5b94 | 1552 | { |
6ac7b687 | 1553 | struct be_mcc_wrb *wrb; |
5b8821b7 SP |
1554 | struct be_dma_mem *mem = &adapter->rx_filter; |
1555 | struct be_cmd_req_rx_filter *req = mem->va; | |
e7b909a6 SP |
1556 | struct be_sge *sge; |
1557 | int status; | |
6b7c5b94 | 1558 | |
8788fdc2 | 1559 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1560 | |
b31c50a7 | 1561 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1562 | if (!wrb) { |
1563 | status = -EBUSY; | |
1564 | goto err; | |
1565 | } | |
e7b909a6 | 1566 | sge = nonembedded_sgl(wrb); |
e7b909a6 SP |
1567 | sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); |
1568 | sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); | |
1569 | sge->len = cpu_to_le32(mem->size); | |
5b8821b7 SP |
1570 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, |
1571 | OPCODE_COMMON_NTWK_RX_FILTER); | |
6b7c5b94 | 1572 | |
5b8821b7 | 1573 | memset(req, 0, sizeof(*req)); |
6b7c5b94 | 1574 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
5b8821b7 | 1575 | OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req)); |
6b7c5b94 | 1576 | |
5b8821b7 SP |
1577 | req->if_id = cpu_to_le32(adapter->if_handle); |
1578 | if (flags & IFF_PROMISC) { | |
1579 | req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | | |
1580 | BE_IF_FLAGS_VLAN_PROMISCUOUS); | |
1581 | if (value == ON) | |
1582 | req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | | |
1583 | BE_IF_FLAGS_VLAN_PROMISCUOUS); | |
1584 | } else if (flags & IFF_ALLMULTI) { | |
1585 | req->if_flags_mask = req->if_flags = | |
1586 | cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS); | |
1587 | } else { | |
22bedad3 | 1588 | struct netdev_hw_addr *ha; |
5b8821b7 | 1589 | int i = 0; |
24307eef | 1590 | |
5b8821b7 SP |
1591 | req->mcast_num = cpu_to_le16(netdev_mc_count(adapter->netdev)); |
1592 | netdev_for_each_mc_addr(ha, adapter->netdev) | |
1593 | memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN); | |
6b7c5b94 SP |
1594 | } |
1595 | ||
713d0394 | 1596 | err: |
8788fdc2 | 1597 | spin_unlock_bh(&adapter->mcc_lock); |
e7b909a6 | 1598 | return status; |
6b7c5b94 SP |
1599 | } |
1600 | ||
b31c50a7 | 1601 | /* Uses synchrounous mcc */ |
8788fdc2 | 1602 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) |
6b7c5b94 | 1603 | { |
b31c50a7 SP |
1604 | struct be_mcc_wrb *wrb; |
1605 | struct be_cmd_req_set_flow_control *req; | |
6b7c5b94 SP |
1606 | int status; |
1607 | ||
b31c50a7 | 1608 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1609 | |
b31c50a7 | 1610 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1611 | if (!wrb) { |
1612 | status = -EBUSY; | |
1613 | goto err; | |
1614 | } | |
b31c50a7 | 1615 | req = embedded_payload(wrb); |
6b7c5b94 | 1616 | |
d744b44e AK |
1617 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1618 | OPCODE_COMMON_SET_FLOW_CONTROL); | |
6b7c5b94 SP |
1619 | |
1620 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1621 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); | |
1622 | ||
1623 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | |
1624 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | |
1625 | ||
b31c50a7 | 1626 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1627 | |
713d0394 | 1628 | err: |
b31c50a7 | 1629 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1630 | return status; |
1631 | } | |
1632 | ||
b31c50a7 | 1633 | /* Uses sycn mcc */ |
8788fdc2 | 1634 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) |
6b7c5b94 | 1635 | { |
b31c50a7 SP |
1636 | struct be_mcc_wrb *wrb; |
1637 | struct be_cmd_req_get_flow_control *req; | |
6b7c5b94 SP |
1638 | int status; |
1639 | ||
b31c50a7 | 1640 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1641 | |
b31c50a7 | 1642 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1643 | if (!wrb) { |
1644 | status = -EBUSY; | |
1645 | goto err; | |
1646 | } | |
b31c50a7 | 1647 | req = embedded_payload(wrb); |
6b7c5b94 | 1648 | |
d744b44e AK |
1649 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1650 | OPCODE_COMMON_GET_FLOW_CONTROL); | |
6b7c5b94 SP |
1651 | |
1652 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1653 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | |
1654 | ||
b31c50a7 | 1655 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1656 | if (!status) { |
1657 | struct be_cmd_resp_get_flow_control *resp = | |
1658 | embedded_payload(wrb); | |
1659 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | |
1660 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | |
1661 | } | |
1662 | ||
713d0394 | 1663 | err: |
b31c50a7 | 1664 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1665 | return status; |
1666 | } | |
1667 | ||
b31c50a7 | 1668 | /* Uses mbox */ |
3abcdeda SP |
1669 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, |
1670 | u32 *mode, u32 *caps) | |
6b7c5b94 | 1671 | { |
b31c50a7 SP |
1672 | struct be_mcc_wrb *wrb; |
1673 | struct be_cmd_req_query_fw_cfg *req; | |
6b7c5b94 SP |
1674 | int status; |
1675 | ||
2984961c IV |
1676 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1677 | return -1; | |
6b7c5b94 | 1678 | |
b31c50a7 SP |
1679 | wrb = wrb_from_mbox(adapter); |
1680 | req = embedded_payload(wrb); | |
6b7c5b94 | 1681 | |
d744b44e AK |
1682 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1683 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG); | |
6b7c5b94 SP |
1684 | |
1685 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1686 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | |
1687 | ||
b31c50a7 | 1688 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1689 | if (!status) { |
1690 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | |
1691 | *port_num = le32_to_cpu(resp->phys_port); | |
3486be29 | 1692 | *mode = le32_to_cpu(resp->function_mode); |
3abcdeda | 1693 | *caps = le32_to_cpu(resp->function_caps); |
6b7c5b94 SP |
1694 | } |
1695 | ||
2984961c | 1696 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1697 | return status; |
1698 | } | |
14074eab | 1699 | |
b31c50a7 | 1700 | /* Uses mbox */ |
14074eab | 1701 | int be_cmd_reset_function(struct be_adapter *adapter) |
1702 | { | |
b31c50a7 SP |
1703 | struct be_mcc_wrb *wrb; |
1704 | struct be_cmd_req_hdr *req; | |
14074eab | 1705 | int status; |
1706 | ||
2984961c IV |
1707 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1708 | return -1; | |
14074eab | 1709 | |
b31c50a7 SP |
1710 | wrb = wrb_from_mbox(adapter); |
1711 | req = embedded_payload(wrb); | |
14074eab | 1712 | |
d744b44e AK |
1713 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1714 | OPCODE_COMMON_FUNCTION_RESET); | |
14074eab | 1715 | |
1716 | be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, | |
1717 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); | |
1718 | ||
b31c50a7 | 1719 | status = be_mbox_notify_wait(adapter); |
14074eab | 1720 | |
2984961c | 1721 | mutex_unlock(&adapter->mbox_lock); |
14074eab | 1722 | return status; |
1723 | } | |
84517482 | 1724 | |
3abcdeda SP |
1725 | int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size) |
1726 | { | |
1727 | struct be_mcc_wrb *wrb; | |
1728 | struct be_cmd_req_rss_config *req; | |
5d8bee67 SP |
1729 | u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF, |
1730 | 0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF}; | |
3abcdeda SP |
1731 | int status; |
1732 | ||
2984961c IV |
1733 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1734 | return -1; | |
3abcdeda SP |
1735 | |
1736 | wrb = wrb_from_mbox(adapter); | |
1737 | req = embedded_payload(wrb); | |
1738 | ||
1739 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1740 | OPCODE_ETH_RSS_CONFIG); | |
1741 | ||
1742 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1743 | OPCODE_ETH_RSS_CONFIG, sizeof(*req)); | |
1744 | ||
1745 | req->if_id = cpu_to_le32(adapter->if_handle); | |
1746 | req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4); | |
1747 | req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); | |
1748 | memcpy(req->cpu_table, rsstable, table_size); | |
1749 | memcpy(req->hash, myhash, sizeof(myhash)); | |
1750 | be_dws_cpu_to_le(req->hash, sizeof(req->hash)); | |
1751 | ||
1752 | status = be_mbox_notify_wait(adapter); | |
1753 | ||
2984961c | 1754 | mutex_unlock(&adapter->mbox_lock); |
3abcdeda SP |
1755 | return status; |
1756 | } | |
1757 | ||
fad9ab2c SB |
1758 | /* Uses sync mcc */ |
1759 | int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, | |
1760 | u8 bcn, u8 sts, u8 state) | |
1761 | { | |
1762 | struct be_mcc_wrb *wrb; | |
1763 | struct be_cmd_req_enable_disable_beacon *req; | |
1764 | int status; | |
1765 | ||
1766 | spin_lock_bh(&adapter->mcc_lock); | |
1767 | ||
1768 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1769 | if (!wrb) { |
1770 | status = -EBUSY; | |
1771 | goto err; | |
1772 | } | |
fad9ab2c SB |
1773 | req = embedded_payload(wrb); |
1774 | ||
d744b44e AK |
1775 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1776 | OPCODE_COMMON_ENABLE_DISABLE_BEACON); | |
fad9ab2c SB |
1777 | |
1778 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1779 | OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req)); | |
1780 | ||
1781 | req->port_num = port_num; | |
1782 | req->beacon_state = state; | |
1783 | req->beacon_duration = bcn; | |
1784 | req->status_duration = sts; | |
1785 | ||
1786 | status = be_mcc_notify_wait(adapter); | |
1787 | ||
713d0394 | 1788 | err: |
fad9ab2c SB |
1789 | spin_unlock_bh(&adapter->mcc_lock); |
1790 | return status; | |
1791 | } | |
1792 | ||
1793 | /* Uses sync mcc */ | |
1794 | int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) | |
1795 | { | |
1796 | struct be_mcc_wrb *wrb; | |
1797 | struct be_cmd_req_get_beacon_state *req; | |
1798 | int status; | |
1799 | ||
1800 | spin_lock_bh(&adapter->mcc_lock); | |
1801 | ||
1802 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1803 | if (!wrb) { |
1804 | status = -EBUSY; | |
1805 | goto err; | |
1806 | } | |
fad9ab2c SB |
1807 | req = embedded_payload(wrb); |
1808 | ||
d744b44e AK |
1809 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1810 | OPCODE_COMMON_GET_BEACON_STATE); | |
fad9ab2c SB |
1811 | |
1812 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1813 | OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req)); | |
1814 | ||
1815 | req->port_num = port_num; | |
1816 | ||
1817 | status = be_mcc_notify_wait(adapter); | |
1818 | if (!status) { | |
1819 | struct be_cmd_resp_get_beacon_state *resp = | |
1820 | embedded_payload(wrb); | |
1821 | *state = resp->beacon_state; | |
1822 | } | |
1823 | ||
713d0394 | 1824 | err: |
fad9ab2c SB |
1825 | spin_unlock_bh(&adapter->mcc_lock); |
1826 | return status; | |
1827 | } | |
1828 | ||
485bf569 SN |
1829 | int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, |
1830 | u32 data_size, u32 data_offset, const char *obj_name, | |
1831 | u32 *data_written, u8 *addn_status) | |
1832 | { | |
1833 | struct be_mcc_wrb *wrb; | |
1834 | struct lancer_cmd_req_write_object *req; | |
1835 | struct lancer_cmd_resp_write_object *resp; | |
1836 | void *ctxt = NULL; | |
1837 | int status; | |
1838 | ||
1839 | spin_lock_bh(&adapter->mcc_lock); | |
1840 | adapter->flash_status = 0; | |
1841 | ||
1842 | wrb = wrb_from_mccq(adapter); | |
1843 | if (!wrb) { | |
1844 | status = -EBUSY; | |
1845 | goto err_unlock; | |
1846 | } | |
1847 | ||
1848 | req = embedded_payload(wrb); | |
1849 | ||
1850 | be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object), | |
1851 | true, 1, OPCODE_COMMON_WRITE_OBJECT); | |
1852 | wrb->tag1 = CMD_SUBSYSTEM_COMMON; | |
1853 | ||
1854 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1855 | OPCODE_COMMON_WRITE_OBJECT, | |
1856 | sizeof(struct lancer_cmd_req_write_object)); | |
1857 | ||
1858 | ctxt = &req->context; | |
1859 | AMAP_SET_BITS(struct amap_lancer_write_obj_context, | |
1860 | write_length, ctxt, data_size); | |
1861 | ||
1862 | if (data_size == 0) | |
1863 | AMAP_SET_BITS(struct amap_lancer_write_obj_context, | |
1864 | eof, ctxt, 1); | |
1865 | else | |
1866 | AMAP_SET_BITS(struct amap_lancer_write_obj_context, | |
1867 | eof, ctxt, 0); | |
1868 | ||
1869 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
1870 | req->write_offset = cpu_to_le32(data_offset); | |
1871 | strcpy(req->object_name, obj_name); | |
1872 | req->descriptor_count = cpu_to_le32(1); | |
1873 | req->buf_len = cpu_to_le32(data_size); | |
1874 | req->addr_low = cpu_to_le32((cmd->dma + | |
1875 | sizeof(struct lancer_cmd_req_write_object)) | |
1876 | & 0xFFFFFFFF); | |
1877 | req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + | |
1878 | sizeof(struct lancer_cmd_req_write_object))); | |
1879 | ||
1880 | be_mcc_notify(adapter); | |
1881 | spin_unlock_bh(&adapter->mcc_lock); | |
1882 | ||
1883 | if (!wait_for_completion_timeout(&adapter->flash_compl, | |
1884 | msecs_to_jiffies(12000))) | |
1885 | status = -1; | |
1886 | else | |
1887 | status = adapter->flash_status; | |
1888 | ||
1889 | resp = embedded_payload(wrb); | |
1890 | if (!status) { | |
1891 | *data_written = le32_to_cpu(resp->actual_write_len); | |
1892 | } else { | |
1893 | *addn_status = resp->additional_status; | |
1894 | status = resp->status; | |
1895 | } | |
1896 | ||
1897 | return status; | |
1898 | ||
1899 | err_unlock: | |
1900 | spin_unlock_bh(&adapter->mcc_lock); | |
1901 | return status; | |
1902 | } | |
1903 | ||
84517482 AK |
1904 | int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, |
1905 | u32 flash_type, u32 flash_opcode, u32 buf_size) | |
1906 | { | |
b31c50a7 | 1907 | struct be_mcc_wrb *wrb; |
3f0d4560 | 1908 | struct be_cmd_write_flashrom *req; |
b31c50a7 | 1909 | struct be_sge *sge; |
84517482 AK |
1910 | int status; |
1911 | ||
b31c50a7 | 1912 | spin_lock_bh(&adapter->mcc_lock); |
dd131e76 | 1913 | adapter->flash_status = 0; |
b31c50a7 SP |
1914 | |
1915 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1916 | if (!wrb) { |
1917 | status = -EBUSY; | |
2892d9c2 | 1918 | goto err_unlock; |
713d0394 SP |
1919 | } |
1920 | req = cmd->va; | |
b31c50a7 SP |
1921 | sge = nonembedded_sgl(wrb); |
1922 | ||
d744b44e AK |
1923 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, |
1924 | OPCODE_COMMON_WRITE_FLASHROM); | |
dd131e76 | 1925 | wrb->tag1 = CMD_SUBSYSTEM_COMMON; |
84517482 AK |
1926 | |
1927 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1928 | OPCODE_COMMON_WRITE_FLASHROM, cmd->size); | |
1929 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1930 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1931 | sge->len = cpu_to_le32(cmd->size); | |
1932 | ||
1933 | req->params.op_type = cpu_to_le32(flash_type); | |
1934 | req->params.op_code = cpu_to_le32(flash_opcode); | |
1935 | req->params.data_buf_size = cpu_to_le32(buf_size); | |
1936 | ||
dd131e76 SB |
1937 | be_mcc_notify(adapter); |
1938 | spin_unlock_bh(&adapter->mcc_lock); | |
1939 | ||
1940 | if (!wait_for_completion_timeout(&adapter->flash_compl, | |
1941 | msecs_to_jiffies(12000))) | |
1942 | status = -1; | |
1943 | else | |
1944 | status = adapter->flash_status; | |
84517482 | 1945 | |
2892d9c2 DC |
1946 | return status; |
1947 | ||
1948 | err_unlock: | |
1949 | spin_unlock_bh(&adapter->mcc_lock); | |
84517482 AK |
1950 | return status; |
1951 | } | |
fa9a6fed | 1952 | |
3f0d4560 AK |
1953 | int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, |
1954 | int offset) | |
fa9a6fed SB |
1955 | { |
1956 | struct be_mcc_wrb *wrb; | |
1957 | struct be_cmd_write_flashrom *req; | |
1958 | int status; | |
1959 | ||
1960 | spin_lock_bh(&adapter->mcc_lock); | |
1961 | ||
1962 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1963 | if (!wrb) { |
1964 | status = -EBUSY; | |
1965 | goto err; | |
1966 | } | |
fa9a6fed SB |
1967 | req = embedded_payload(wrb); |
1968 | ||
d744b44e AK |
1969 | be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0, |
1970 | OPCODE_COMMON_READ_FLASHROM); | |
fa9a6fed SB |
1971 | |
1972 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1973 | OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4); | |
1974 | ||
3f0d4560 | 1975 | req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT); |
fa9a6fed | 1976 | req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); |
8b93b710 AK |
1977 | req->params.offset = cpu_to_le32(offset); |
1978 | req->params.data_buf_size = cpu_to_le32(0x4); | |
fa9a6fed SB |
1979 | |
1980 | status = be_mcc_notify_wait(adapter); | |
1981 | if (!status) | |
1982 | memcpy(flashed_crc, req->params.data_buf, 4); | |
1983 | ||
713d0394 | 1984 | err: |
fa9a6fed SB |
1985 | spin_unlock_bh(&adapter->mcc_lock); |
1986 | return status; | |
1987 | } | |
71d8d1b5 | 1988 | |
c196b02c | 1989 | int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, |
71d8d1b5 AK |
1990 | struct be_dma_mem *nonemb_cmd) |
1991 | { | |
1992 | struct be_mcc_wrb *wrb; | |
1993 | struct be_cmd_req_acpi_wol_magic_config *req; | |
1994 | struct be_sge *sge; | |
1995 | int status; | |
1996 | ||
1997 | spin_lock_bh(&adapter->mcc_lock); | |
1998 | ||
1999 | wrb = wrb_from_mccq(adapter); | |
2000 | if (!wrb) { | |
2001 | status = -EBUSY; | |
2002 | goto err; | |
2003 | } | |
2004 | req = nonemb_cmd->va; | |
2005 | sge = nonembedded_sgl(wrb); | |
2006 | ||
2007 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
2008 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG); | |
2009 | ||
2010 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
2011 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req)); | |
2012 | memcpy(req->magic_mac, mac, ETH_ALEN); | |
2013 | ||
2014 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
2015 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
2016 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
2017 | ||
2018 | status = be_mcc_notify_wait(adapter); | |
2019 | ||
2020 | err: | |
2021 | spin_unlock_bh(&adapter->mcc_lock); | |
2022 | return status; | |
2023 | } | |
ff33a6e2 | 2024 | |
fced9999 SB |
2025 | int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, |
2026 | u8 loopback_type, u8 enable) | |
2027 | { | |
2028 | struct be_mcc_wrb *wrb; | |
2029 | struct be_cmd_req_set_lmode *req; | |
2030 | int status; | |
2031 | ||
2032 | spin_lock_bh(&adapter->mcc_lock); | |
2033 | ||
2034 | wrb = wrb_from_mccq(adapter); | |
2035 | if (!wrb) { | |
2036 | status = -EBUSY; | |
2037 | goto err; | |
2038 | } | |
2039 | ||
2040 | req = embedded_payload(wrb); | |
2041 | ||
2042 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
2043 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE); | |
2044 | ||
2045 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
2046 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, | |
2047 | sizeof(*req)); | |
2048 | ||
2049 | req->src_port = port_num; | |
2050 | req->dest_port = port_num; | |
2051 | req->loopback_type = loopback_type; | |
2052 | req->loopback_state = enable; | |
2053 | ||
2054 | status = be_mcc_notify_wait(adapter); | |
2055 | err: | |
2056 | spin_unlock_bh(&adapter->mcc_lock); | |
2057 | return status; | |
2058 | } | |
2059 | ||
ff33a6e2 S |
2060 | int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, |
2061 | u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) | |
2062 | { | |
2063 | struct be_mcc_wrb *wrb; | |
2064 | struct be_cmd_req_loopback_test *req; | |
2065 | int status; | |
2066 | ||
2067 | spin_lock_bh(&adapter->mcc_lock); | |
2068 | ||
2069 | wrb = wrb_from_mccq(adapter); | |
2070 | if (!wrb) { | |
2071 | status = -EBUSY; | |
2072 | goto err; | |
2073 | } | |
2074 | ||
2075 | req = embedded_payload(wrb); | |
2076 | ||
2077 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
2078 | OPCODE_LOWLEVEL_LOOPBACK_TEST); | |
2079 | ||
2080 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
2081 | OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req)); | |
3ffd0515 | 2082 | req->hdr.timeout = cpu_to_le32(4); |
ff33a6e2 S |
2083 | |
2084 | req->pattern = cpu_to_le64(pattern); | |
2085 | req->src_port = cpu_to_le32(port_num); | |
2086 | req->dest_port = cpu_to_le32(port_num); | |
2087 | req->pkt_size = cpu_to_le32(pkt_size); | |
2088 | req->num_pkts = cpu_to_le32(num_pkts); | |
2089 | req->loopback_type = cpu_to_le32(loopback_type); | |
2090 | ||
2091 | status = be_mcc_notify_wait(adapter); | |
2092 | if (!status) { | |
2093 | struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); | |
2094 | status = le32_to_cpu(resp->status); | |
2095 | } | |
2096 | ||
2097 | err: | |
2098 | spin_unlock_bh(&adapter->mcc_lock); | |
2099 | return status; | |
2100 | } | |
2101 | ||
2102 | int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, | |
2103 | u32 byte_cnt, struct be_dma_mem *cmd) | |
2104 | { | |
2105 | struct be_mcc_wrb *wrb; | |
2106 | struct be_cmd_req_ddrdma_test *req; | |
2107 | struct be_sge *sge; | |
2108 | int status; | |
2109 | int i, j = 0; | |
2110 | ||
2111 | spin_lock_bh(&adapter->mcc_lock); | |
2112 | ||
2113 | wrb = wrb_from_mccq(adapter); | |
2114 | if (!wrb) { | |
2115 | status = -EBUSY; | |
2116 | goto err; | |
2117 | } | |
2118 | req = cmd->va; | |
2119 | sge = nonembedded_sgl(wrb); | |
2120 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, | |
2121 | OPCODE_LOWLEVEL_HOST_DDR_DMA); | |
2122 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
2123 | OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size); | |
2124 | ||
2125 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
2126 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
2127 | sge->len = cpu_to_le32(cmd->size); | |
2128 | ||
2129 | req->pattern = cpu_to_le64(pattern); | |
2130 | req->byte_count = cpu_to_le32(byte_cnt); | |
2131 | for (i = 0; i < byte_cnt; i++) { | |
2132 | req->snd_buff[i] = (u8)(pattern >> (j*8)); | |
2133 | j++; | |
2134 | if (j > 7) | |
2135 | j = 0; | |
2136 | } | |
2137 | ||
2138 | status = be_mcc_notify_wait(adapter); | |
2139 | ||
2140 | if (!status) { | |
2141 | struct be_cmd_resp_ddrdma_test *resp; | |
2142 | resp = cmd->va; | |
2143 | if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || | |
2144 | resp->snd_err) { | |
2145 | status = -1; | |
2146 | } | |
2147 | } | |
2148 | ||
2149 | err: | |
2150 | spin_unlock_bh(&adapter->mcc_lock); | |
2151 | return status; | |
2152 | } | |
368c0ca2 | 2153 | |
c196b02c | 2154 | int be_cmd_get_seeprom_data(struct be_adapter *adapter, |
368c0ca2 SB |
2155 | struct be_dma_mem *nonemb_cmd) |
2156 | { | |
2157 | struct be_mcc_wrb *wrb; | |
2158 | struct be_cmd_req_seeprom_read *req; | |
2159 | struct be_sge *sge; | |
2160 | int status; | |
2161 | ||
2162 | spin_lock_bh(&adapter->mcc_lock); | |
2163 | ||
2164 | wrb = wrb_from_mccq(adapter); | |
e45ff01d AK |
2165 | if (!wrb) { |
2166 | status = -EBUSY; | |
2167 | goto err; | |
2168 | } | |
368c0ca2 SB |
2169 | req = nonemb_cmd->va; |
2170 | sge = nonembedded_sgl(wrb); | |
2171 | ||
2172 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
2173 | OPCODE_COMMON_SEEPROM_READ); | |
2174 | ||
2175 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2176 | OPCODE_COMMON_SEEPROM_READ, sizeof(*req)); | |
2177 | ||
2178 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
2179 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
2180 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
2181 | ||
2182 | status = be_mcc_notify_wait(adapter); | |
2183 | ||
e45ff01d | 2184 | err: |
368c0ca2 SB |
2185 | spin_unlock_bh(&adapter->mcc_lock); |
2186 | return status; | |
2187 | } | |
ee3cb629 AK |
2188 | |
2189 | int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd) | |
2190 | { | |
2191 | struct be_mcc_wrb *wrb; | |
2192 | struct be_cmd_req_get_phy_info *req; | |
2193 | struct be_sge *sge; | |
2194 | int status; | |
2195 | ||
2196 | spin_lock_bh(&adapter->mcc_lock); | |
2197 | ||
2198 | wrb = wrb_from_mccq(adapter); | |
2199 | if (!wrb) { | |
2200 | status = -EBUSY; | |
2201 | goto err; | |
2202 | } | |
2203 | ||
2204 | req = cmd->va; | |
2205 | sge = nonembedded_sgl(wrb); | |
2206 | ||
2207 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
2208 | OPCODE_COMMON_GET_PHY_DETAILS); | |
2209 | ||
2210 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2211 | OPCODE_COMMON_GET_PHY_DETAILS, | |
2212 | sizeof(*req)); | |
2213 | ||
2214 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
2215 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
2216 | sge->len = cpu_to_le32(cmd->size); | |
2217 | ||
2218 | status = be_mcc_notify_wait(adapter); | |
2219 | err: | |
2220 | spin_unlock_bh(&adapter->mcc_lock); | |
2221 | return status; | |
2222 | } | |
e1d18735 AK |
2223 | |
2224 | int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain) | |
2225 | { | |
2226 | struct be_mcc_wrb *wrb; | |
2227 | struct be_cmd_req_set_qos *req; | |
2228 | int status; | |
2229 | ||
2230 | spin_lock_bh(&adapter->mcc_lock); | |
2231 | ||
2232 | wrb = wrb_from_mccq(adapter); | |
2233 | if (!wrb) { | |
2234 | status = -EBUSY; | |
2235 | goto err; | |
2236 | } | |
2237 | ||
2238 | req = embedded_payload(wrb); | |
2239 | ||
2240 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
2241 | OPCODE_COMMON_SET_QOS); | |
2242 | ||
2243 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2244 | OPCODE_COMMON_SET_QOS, sizeof(*req)); | |
2245 | ||
2246 | req->hdr.domain = domain; | |
6bff57a7 AK |
2247 | req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); |
2248 | req->max_bps_nic = cpu_to_le32(bps); | |
e1d18735 AK |
2249 | |
2250 | status = be_mcc_notify_wait(adapter); | |
2251 | ||
2252 | err: | |
2253 | spin_unlock_bh(&adapter->mcc_lock); | |
2254 | return status; | |
2255 | } | |
9e1453c5 AK |
2256 | |
2257 | int be_cmd_get_cntl_attributes(struct be_adapter *adapter) | |
2258 | { | |
2259 | struct be_mcc_wrb *wrb; | |
2260 | struct be_cmd_req_cntl_attribs *req; | |
2261 | struct be_cmd_resp_cntl_attribs *resp; | |
2262 | struct be_sge *sge; | |
2263 | int status; | |
2264 | int payload_len = max(sizeof(*req), sizeof(*resp)); | |
2265 | struct mgmt_controller_attrib *attribs; | |
2266 | struct be_dma_mem attribs_cmd; | |
2267 | ||
2268 | memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); | |
2269 | attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); | |
2270 | attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, | |
2271 | &attribs_cmd.dma); | |
2272 | if (!attribs_cmd.va) { | |
2273 | dev_err(&adapter->pdev->dev, | |
2274 | "Memory allocation failure\n"); | |
2275 | return -ENOMEM; | |
2276 | } | |
2277 | ||
2278 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | |
2279 | return -1; | |
2280 | ||
2281 | wrb = wrb_from_mbox(adapter); | |
2282 | if (!wrb) { | |
2283 | status = -EBUSY; | |
2284 | goto err; | |
2285 | } | |
2286 | req = attribs_cmd.va; | |
2287 | sge = nonembedded_sgl(wrb); | |
2288 | ||
2289 | be_wrb_hdr_prepare(wrb, payload_len, false, 1, | |
2290 | OPCODE_COMMON_GET_CNTL_ATTRIBUTES); | |
2291 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2292 | OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len); | |
2293 | sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma)); | |
2294 | sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF); | |
2295 | sge->len = cpu_to_le32(attribs_cmd.size); | |
2296 | ||
2297 | status = be_mbox_notify_wait(adapter); | |
2298 | if (!status) { | |
43d620c8 | 2299 | attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); |
9e1453c5 AK |
2300 | adapter->hba_port_num = attribs->hba_attribs.phy_port; |
2301 | } | |
2302 | ||
2303 | err: | |
2304 | mutex_unlock(&adapter->mbox_lock); | |
2305 | pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va, | |
2306 | attribs_cmd.dma); | |
2307 | return status; | |
2308 | } | |
2e588f84 SP |
2309 | |
2310 | /* Uses mbox */ | |
2dc1deb6 | 2311 | int be_cmd_req_native_mode(struct be_adapter *adapter) |
2e588f84 SP |
2312 | { |
2313 | struct be_mcc_wrb *wrb; | |
2314 | struct be_cmd_req_set_func_cap *req; | |
2315 | int status; | |
2316 | ||
2317 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | |
2318 | return -1; | |
2319 | ||
2320 | wrb = wrb_from_mbox(adapter); | |
2321 | if (!wrb) { | |
2322 | status = -EBUSY; | |
2323 | goto err; | |
2324 | } | |
2325 | ||
2326 | req = embedded_payload(wrb); | |
2327 | ||
2328 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
2329 | OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP); | |
2330 | ||
2331 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2332 | OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req)); | |
2333 | ||
2334 | req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | | |
2335 | CAPABILITY_BE3_NATIVE_ERX_API); | |
2336 | req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API); | |
2337 | ||
2338 | status = be_mbox_notify_wait(adapter); | |
2339 | if (!status) { | |
2340 | struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb); | |
2341 | adapter->be3_native = le32_to_cpu(resp->cap_flags) & | |
2342 | CAPABILITY_BE3_NATIVE_ERX_API; | |
2343 | } | |
2344 | err: | |
2345 | mutex_unlock(&adapter->mbox_lock); | |
2346 | return status; | |
2347 | } |