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6b7c5b94 | 1 | /* |
294aedcf | 2 | * Copyright (C) 2005 - 2010 ServerEngines |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | #include "be.h" | |
8788fdc2 | 19 | #include "be_cmds.h" |
6b7c5b94 | 20 | |
8788fdc2 | 21 | static void be_mcc_notify(struct be_adapter *adapter) |
5fb379ee | 22 | { |
8788fdc2 | 23 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
5fb379ee SP |
24 | u32 val = 0; |
25 | ||
26 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | |
27 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
8788fdc2 | 28 | iowrite32(val, adapter->db + DB_MCCQ_OFFSET); |
5fb379ee SP |
29 | } |
30 | ||
31 | /* To check if valid bit is set, check the entire word as we don't know | |
32 | * the endianness of the data (old entry is host endian while a new entry is | |
33 | * little endian) */ | |
efd2e40a | 34 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) |
5fb379ee SP |
35 | { |
36 | if (compl->flags != 0) { | |
37 | compl->flags = le32_to_cpu(compl->flags); | |
38 | BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); | |
39 | return true; | |
40 | } else { | |
41 | return false; | |
42 | } | |
43 | } | |
44 | ||
45 | /* Need to reset the entire word that houses the valid bit */ | |
efd2e40a | 46 | static inline void be_mcc_compl_use(struct be_mcc_compl *compl) |
5fb379ee SP |
47 | { |
48 | compl->flags = 0; | |
49 | } | |
50 | ||
8788fdc2 | 51 | static int be_mcc_compl_process(struct be_adapter *adapter, |
efd2e40a | 52 | struct be_mcc_compl *compl) |
5fb379ee SP |
53 | { |
54 | u16 compl_status, extd_status; | |
55 | ||
56 | /* Just swap the status to host endian; mcc tag is opaquely copied | |
57 | * from mcc_wrb */ | |
58 | be_dws_le_to_cpu(compl, 4); | |
59 | ||
60 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & | |
61 | CQE_STATUS_COMPL_MASK; | |
dd131e76 SB |
62 | |
63 | if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) && | |
64 | (compl->tag1 == CMD_SUBSYSTEM_COMMON)) { | |
65 | adapter->flash_status = compl_status; | |
66 | complete(&adapter->flash_compl); | |
67 | } | |
68 | ||
b31c50a7 SP |
69 | if (compl_status == MCC_STATUS_SUCCESS) { |
70 | if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) { | |
71 | struct be_cmd_resp_get_stats *resp = | |
72 | adapter->stats.cmd.va; | |
73 | be_dws_le_to_cpu(&resp->hw_stats, | |
74 | sizeof(resp->hw_stats)); | |
75 | netdev_stats_update(adapter); | |
76 | } | |
77 | } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) { | |
5fb379ee SP |
78 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & |
79 | CQE_STATUS_EXTD_MASK; | |
5f0b849e | 80 | dev_warn(&adapter->pdev->dev, |
d744b44e AK |
81 | "Error in cmd completion - opcode %d, compl %d, extd %d\n", |
82 | compl->tag0, compl_status, extd_status); | |
5fb379ee | 83 | } |
b31c50a7 | 84 | return compl_status; |
5fb379ee SP |
85 | } |
86 | ||
a8f447bd | 87 | /* Link state evt is a string of bytes; no need for endian swapping */ |
8788fdc2 | 88 | static void be_async_link_state_process(struct be_adapter *adapter, |
a8f447bd SP |
89 | struct be_async_event_link_state *evt) |
90 | { | |
8788fdc2 SP |
91 | be_link_status_update(adapter, |
92 | evt->port_link_status == ASYNC_EVENT_LINK_UP); | |
a8f447bd SP |
93 | } |
94 | ||
95 | static inline bool is_link_state_evt(u32 trailer) | |
96 | { | |
97 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | |
98 | ASYNC_TRAILER_EVENT_CODE_MASK) == | |
99 | ASYNC_EVENT_CODE_LINK_STATE); | |
100 | } | |
5fb379ee | 101 | |
efd2e40a | 102 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) |
5fb379ee | 103 | { |
8788fdc2 | 104 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
efd2e40a | 105 | struct be_mcc_compl *compl = queue_tail_node(mcc_cq); |
5fb379ee SP |
106 | |
107 | if (be_mcc_compl_is_new(compl)) { | |
108 | queue_tail_inc(mcc_cq); | |
109 | return compl; | |
110 | } | |
111 | return NULL; | |
112 | } | |
113 | ||
7a1e9b20 SP |
114 | void be_async_mcc_enable(struct be_adapter *adapter) |
115 | { | |
116 | spin_lock_bh(&adapter->mcc_cq_lock); | |
117 | ||
118 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); | |
119 | adapter->mcc_obj.rearm_cq = true; | |
120 | ||
121 | spin_unlock_bh(&adapter->mcc_cq_lock); | |
122 | } | |
123 | ||
124 | void be_async_mcc_disable(struct be_adapter *adapter) | |
125 | { | |
126 | adapter->mcc_obj.rearm_cq = false; | |
127 | } | |
128 | ||
f31e50a8 | 129 | int be_process_mcc(struct be_adapter *adapter, int *status) |
5fb379ee | 130 | { |
efd2e40a | 131 | struct be_mcc_compl *compl; |
f31e50a8 | 132 | int num = 0; |
7a1e9b20 | 133 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; |
5fb379ee | 134 | |
8788fdc2 SP |
135 | spin_lock_bh(&adapter->mcc_cq_lock); |
136 | while ((compl = be_mcc_compl_get(adapter))) { | |
a8f447bd SP |
137 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { |
138 | /* Interpret flags as an async trailer */ | |
139 | BUG_ON(!is_link_state_evt(compl->flags)); | |
140 | ||
141 | /* Interpret compl as a async link evt */ | |
8788fdc2 | 142 | be_async_link_state_process(adapter, |
a8f447bd | 143 | (struct be_async_event_link_state *) compl); |
b31c50a7 | 144 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
f31e50a8 | 145 | *status = be_mcc_compl_process(adapter, compl); |
7a1e9b20 | 146 | atomic_dec(&mcc_obj->q.used); |
5fb379ee SP |
147 | } |
148 | be_mcc_compl_use(compl); | |
149 | num++; | |
150 | } | |
b31c50a7 | 151 | |
8788fdc2 | 152 | spin_unlock_bh(&adapter->mcc_cq_lock); |
f31e50a8 | 153 | return num; |
5fb379ee SP |
154 | } |
155 | ||
6ac7b687 | 156 | /* Wait till no more pending mcc requests are present */ |
b31c50a7 | 157 | static int be_mcc_wait_compl(struct be_adapter *adapter) |
6ac7b687 | 158 | { |
b31c50a7 | 159 | #define mcc_timeout 120000 /* 12s timeout */ |
f31e50a8 SP |
160 | int i, num, status = 0; |
161 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; | |
162 | ||
6ac7b687 | 163 | for (i = 0; i < mcc_timeout; i++) { |
f31e50a8 SP |
164 | num = be_process_mcc(adapter, &status); |
165 | if (num) | |
166 | be_cq_notify(adapter, mcc_obj->cq.id, | |
167 | mcc_obj->rearm_cq, num); | |
b31c50a7 | 168 | |
f31e50a8 | 169 | if (atomic_read(&mcc_obj->q.used) == 0) |
6ac7b687 SP |
170 | break; |
171 | udelay(100); | |
172 | } | |
b31c50a7 | 173 | if (i == mcc_timeout) { |
5f0b849e | 174 | dev_err(&adapter->pdev->dev, "mccq poll timed out\n"); |
b31c50a7 SP |
175 | return -1; |
176 | } | |
f31e50a8 | 177 | return status; |
6ac7b687 SP |
178 | } |
179 | ||
180 | /* Notify MCC requests and wait for completion */ | |
b31c50a7 | 181 | static int be_mcc_notify_wait(struct be_adapter *adapter) |
6ac7b687 | 182 | { |
8788fdc2 | 183 | be_mcc_notify(adapter); |
b31c50a7 | 184 | return be_mcc_wait_compl(adapter); |
6ac7b687 SP |
185 | } |
186 | ||
5f0b849e | 187 | static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) |
6b7c5b94 SP |
188 | { |
189 | int cnt = 0, wait = 5; | |
190 | u32 ready; | |
191 | ||
192 | do { | |
cf588477 SP |
193 | ready = ioread32(db); |
194 | if (ready == 0xffffffff) { | |
195 | dev_err(&adapter->pdev->dev, | |
196 | "pci slot disconnected\n"); | |
197 | return -1; | |
198 | } | |
199 | ||
200 | ready &= MPU_MAILBOX_DB_RDY_MASK; | |
6b7c5b94 SP |
201 | if (ready) |
202 | break; | |
203 | ||
84517482 | 204 | if (cnt > 4000000) { |
5f0b849e | 205 | dev_err(&adapter->pdev->dev, "mbox poll timed out\n"); |
6b7c5b94 SP |
206 | return -1; |
207 | } | |
208 | ||
209 | if (cnt > 50) | |
210 | wait = 200; | |
211 | cnt += wait; | |
212 | udelay(wait); | |
213 | } while (true); | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | /* | |
219 | * Insert the mailbox address into the doorbell in two steps | |
5fb379ee | 220 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs |
6b7c5b94 | 221 | */ |
b31c50a7 | 222 | static int be_mbox_notify_wait(struct be_adapter *adapter) |
6b7c5b94 SP |
223 | { |
224 | int status; | |
6b7c5b94 | 225 | u32 val = 0; |
8788fdc2 SP |
226 | void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; |
227 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; | |
6b7c5b94 | 228 | struct be_mcc_mailbox *mbox = mbox_mem->va; |
efd2e40a | 229 | struct be_mcc_compl *compl = &mbox->compl; |
6b7c5b94 | 230 | |
cf588477 SP |
231 | /* wait for ready to be set */ |
232 | status = be_mbox_db_ready_wait(adapter, db); | |
233 | if (status != 0) | |
234 | return status; | |
235 | ||
6b7c5b94 SP |
236 | val |= MPU_MAILBOX_DB_HI_MASK; |
237 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | |
238 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
239 | iowrite32(val, db); | |
240 | ||
241 | /* wait for ready to be set */ | |
5f0b849e | 242 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
243 | if (status != 0) |
244 | return status; | |
245 | ||
246 | val = 0; | |
6b7c5b94 SP |
247 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ |
248 | val |= (u32)(mbox_mem->dma >> 4) << 2; | |
249 | iowrite32(val, db); | |
250 | ||
5f0b849e | 251 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
252 | if (status != 0) |
253 | return status; | |
254 | ||
5fb379ee | 255 | /* A cq entry has been made now */ |
efd2e40a SP |
256 | if (be_mcc_compl_is_new(compl)) { |
257 | status = be_mcc_compl_process(adapter, &mbox->compl); | |
258 | be_mcc_compl_use(compl); | |
5fb379ee SP |
259 | if (status) |
260 | return status; | |
261 | } else { | |
5f0b849e | 262 | dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); |
6b7c5b94 SP |
263 | return -1; |
264 | } | |
5fb379ee | 265 | return 0; |
6b7c5b94 SP |
266 | } |
267 | ||
8788fdc2 | 268 | static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage) |
6b7c5b94 | 269 | { |
8788fdc2 | 270 | u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET); |
6b7c5b94 SP |
271 | |
272 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | |
273 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | |
274 | return -1; | |
275 | else | |
276 | return 0; | |
277 | } | |
278 | ||
8788fdc2 | 279 | int be_cmd_POST(struct be_adapter *adapter) |
6b7c5b94 | 280 | { |
43a04fdc SP |
281 | u16 stage; |
282 | int status, timeout = 0; | |
6b7c5b94 | 283 | |
43a04fdc SP |
284 | do { |
285 | status = be_POST_stage_get(adapter, &stage); | |
286 | if (status) { | |
287 | dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n", | |
288 | stage); | |
289 | return -1; | |
290 | } else if (stage != POST_STAGE_ARMFW_RDY) { | |
291 | set_current_state(TASK_INTERRUPTIBLE); | |
292 | schedule_timeout(2 * HZ); | |
293 | timeout += 2; | |
294 | } else { | |
295 | return 0; | |
296 | } | |
d938a702 | 297 | } while (timeout < 40); |
6b7c5b94 | 298 | |
43a04fdc SP |
299 | dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage); |
300 | return -1; | |
6b7c5b94 SP |
301 | } |
302 | ||
303 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) | |
304 | { | |
305 | return wrb->payload.embedded_payload; | |
306 | } | |
307 | ||
308 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | |
309 | { | |
310 | return &wrb->payload.sgl[0]; | |
311 | } | |
312 | ||
313 | /* Don't touch the hdr after it's prepared */ | |
314 | static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | |
d744b44e | 315 | bool embedded, u8 sge_cnt, u32 opcode) |
6b7c5b94 SP |
316 | { |
317 | if (embedded) | |
318 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
319 | else | |
320 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | |
321 | MCC_WRB_SGE_CNT_SHIFT; | |
322 | wrb->payload_length = payload_len; | |
d744b44e | 323 | wrb->tag0 = opcode; |
fa4281bb | 324 | be_dws_cpu_to_le(wrb, 8); |
6b7c5b94 SP |
325 | } |
326 | ||
327 | /* Don't touch the hdr after it's prepared */ | |
328 | static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
329 | u8 subsystem, u8 opcode, int cmd_len) | |
330 | { | |
331 | req_hdr->opcode = opcode; | |
332 | req_hdr->subsystem = subsystem; | |
333 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
07793d33 | 334 | req_hdr->version = 0; |
6b7c5b94 SP |
335 | } |
336 | ||
337 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
338 | struct be_dma_mem *mem) | |
339 | { | |
340 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
341 | u64 dma = (u64)mem->dma; | |
342 | ||
343 | for (i = 0; i < buf_pages; i++) { | |
344 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
345 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
346 | dma += PAGE_SIZE_4K; | |
347 | } | |
348 | } | |
349 | ||
350 | /* Converts interrupt delay in microseconds to multiplier value */ | |
351 | static u32 eq_delay_to_mult(u32 usec_delay) | |
352 | { | |
353 | #define MAX_INTR_RATE 651042 | |
354 | const u32 round = 10; | |
355 | u32 multiplier; | |
356 | ||
357 | if (usec_delay == 0) | |
358 | multiplier = 0; | |
359 | else { | |
360 | u32 interrupt_rate = 1000000 / usec_delay; | |
361 | /* Max delay, corresponding to the lowest interrupt rate */ | |
362 | if (interrupt_rate == 0) | |
363 | multiplier = 1023; | |
364 | else { | |
365 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
366 | multiplier /= interrupt_rate; | |
367 | /* Round the multiplier to the closest value.*/ | |
368 | multiplier = (multiplier + round/2) / round; | |
369 | multiplier = min(multiplier, (u32)1023); | |
370 | } | |
371 | } | |
372 | return multiplier; | |
373 | } | |
374 | ||
b31c50a7 | 375 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) |
6b7c5b94 | 376 | { |
b31c50a7 SP |
377 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; |
378 | struct be_mcc_wrb *wrb | |
379 | = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
380 | memset(wrb, 0, sizeof(*wrb)); | |
381 | return wrb; | |
6b7c5b94 SP |
382 | } |
383 | ||
b31c50a7 | 384 | static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) |
5fb379ee | 385 | { |
b31c50a7 SP |
386 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
387 | struct be_mcc_wrb *wrb; | |
388 | ||
713d0394 SP |
389 | if (atomic_read(&mccq->used) >= mccq->len) { |
390 | dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n"); | |
391 | return NULL; | |
392 | } | |
393 | ||
b31c50a7 SP |
394 | wrb = queue_head_node(mccq); |
395 | queue_head_inc(mccq); | |
396 | atomic_inc(&mccq->used); | |
397 | memset(wrb, 0, sizeof(*wrb)); | |
5fb379ee SP |
398 | return wrb; |
399 | } | |
400 | ||
2243e2e9 SP |
401 | /* Tell fw we're about to start firing cmds by writing a |
402 | * special pattern across the wrb hdr; uses mbox | |
403 | */ | |
404 | int be_cmd_fw_init(struct be_adapter *adapter) | |
405 | { | |
406 | u8 *wrb; | |
407 | int status; | |
408 | ||
409 | spin_lock(&adapter->mbox_lock); | |
410 | ||
411 | wrb = (u8 *)wrb_from_mbox(adapter); | |
412 | *wrb++ = 0xFF; | |
413 | *wrb++ = 0x12; | |
414 | *wrb++ = 0x34; | |
415 | *wrb++ = 0xFF; | |
416 | *wrb++ = 0xFF; | |
417 | *wrb++ = 0x56; | |
418 | *wrb++ = 0x78; | |
419 | *wrb = 0xFF; | |
420 | ||
421 | status = be_mbox_notify_wait(adapter); | |
422 | ||
423 | spin_unlock(&adapter->mbox_lock); | |
424 | return status; | |
425 | } | |
426 | ||
427 | /* Tell fw we're done with firing cmds by writing a | |
428 | * special pattern across the wrb hdr; uses mbox | |
429 | */ | |
430 | int be_cmd_fw_clean(struct be_adapter *adapter) | |
431 | { | |
432 | u8 *wrb; | |
433 | int status; | |
434 | ||
cf588477 SP |
435 | if (adapter->eeh_err) |
436 | return -EIO; | |
437 | ||
2243e2e9 SP |
438 | spin_lock(&adapter->mbox_lock); |
439 | ||
440 | wrb = (u8 *)wrb_from_mbox(adapter); | |
441 | *wrb++ = 0xFF; | |
442 | *wrb++ = 0xAA; | |
443 | *wrb++ = 0xBB; | |
444 | *wrb++ = 0xFF; | |
445 | *wrb++ = 0xFF; | |
446 | *wrb++ = 0xCC; | |
447 | *wrb++ = 0xDD; | |
448 | *wrb = 0xFF; | |
449 | ||
450 | status = be_mbox_notify_wait(adapter); | |
451 | ||
452 | spin_unlock(&adapter->mbox_lock); | |
453 | return status; | |
454 | } | |
8788fdc2 | 455 | int be_cmd_eq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
456 | struct be_queue_info *eq, int eq_delay) |
457 | { | |
b31c50a7 SP |
458 | struct be_mcc_wrb *wrb; |
459 | struct be_cmd_req_eq_create *req; | |
6b7c5b94 SP |
460 | struct be_dma_mem *q_mem = &eq->dma_mem; |
461 | int status; | |
462 | ||
8788fdc2 | 463 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
464 | |
465 | wrb = wrb_from_mbox(adapter); | |
466 | req = embedded_payload(wrb); | |
6b7c5b94 | 467 | |
d744b44e | 468 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE); |
6b7c5b94 SP |
469 | |
470 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
471 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | |
472 | ||
473 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
474 | ||
6b7c5b94 SP |
475 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); |
476 | /* 4byte eqe*/ | |
477 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
478 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
479 | __ilog2_u32(eq->len/256)); | |
480 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
481 | eq_delay_to_mult(eq_delay)); | |
482 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
483 | ||
484 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
485 | ||
b31c50a7 | 486 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 487 | if (!status) { |
b31c50a7 | 488 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
489 | eq->id = le16_to_cpu(resp->eq_id); |
490 | eq->created = true; | |
491 | } | |
b31c50a7 | 492 | |
8788fdc2 | 493 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
494 | return status; |
495 | } | |
496 | ||
b31c50a7 | 497 | /* Uses mbox */ |
8788fdc2 | 498 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
499 | u8 type, bool permanent, u32 if_handle) |
500 | { | |
b31c50a7 SP |
501 | struct be_mcc_wrb *wrb; |
502 | struct be_cmd_req_mac_query *req; | |
6b7c5b94 SP |
503 | int status; |
504 | ||
8788fdc2 | 505 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
506 | |
507 | wrb = wrb_from_mbox(adapter); | |
508 | req = embedded_payload(wrb); | |
6b7c5b94 | 509 | |
d744b44e AK |
510 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
511 | OPCODE_COMMON_NTWK_MAC_QUERY); | |
6b7c5b94 SP |
512 | |
513 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
514 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); | |
515 | ||
516 | req->type = type; | |
517 | if (permanent) { | |
518 | req->permanent = 1; | |
519 | } else { | |
b31c50a7 | 520 | req->if_id = cpu_to_le16((u16) if_handle); |
6b7c5b94 SP |
521 | req->permanent = 0; |
522 | } | |
523 | ||
b31c50a7 SP |
524 | status = be_mbox_notify_wait(adapter); |
525 | if (!status) { | |
526 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | |
6b7c5b94 | 527 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); |
b31c50a7 | 528 | } |
6b7c5b94 | 529 | |
8788fdc2 | 530 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
531 | return status; |
532 | } | |
533 | ||
b31c50a7 | 534 | /* Uses synchronous MCCQ */ |
8788fdc2 | 535 | int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
536 | u32 if_id, u32 *pmac_id) |
537 | { | |
b31c50a7 SP |
538 | struct be_mcc_wrb *wrb; |
539 | struct be_cmd_req_pmac_add *req; | |
6b7c5b94 SP |
540 | int status; |
541 | ||
b31c50a7 SP |
542 | spin_lock_bh(&adapter->mcc_lock); |
543 | ||
544 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
545 | if (!wrb) { |
546 | status = -EBUSY; | |
547 | goto err; | |
548 | } | |
b31c50a7 | 549 | req = embedded_payload(wrb); |
6b7c5b94 | 550 | |
d744b44e AK |
551 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
552 | OPCODE_COMMON_NTWK_PMAC_ADD); | |
6b7c5b94 SP |
553 | |
554 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
555 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); | |
556 | ||
557 | req->if_id = cpu_to_le32(if_id); | |
558 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | |
559 | ||
b31c50a7 | 560 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
561 | if (!status) { |
562 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | |
563 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
564 | } | |
565 | ||
713d0394 | 566 | err: |
b31c50a7 | 567 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
568 | return status; |
569 | } | |
570 | ||
b31c50a7 | 571 | /* Uses synchronous MCCQ */ |
8788fdc2 | 572 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id) |
6b7c5b94 | 573 | { |
b31c50a7 SP |
574 | struct be_mcc_wrb *wrb; |
575 | struct be_cmd_req_pmac_del *req; | |
6b7c5b94 SP |
576 | int status; |
577 | ||
b31c50a7 SP |
578 | spin_lock_bh(&adapter->mcc_lock); |
579 | ||
580 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
581 | if (!wrb) { |
582 | status = -EBUSY; | |
583 | goto err; | |
584 | } | |
b31c50a7 | 585 | req = embedded_payload(wrb); |
6b7c5b94 | 586 | |
d744b44e AK |
587 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
588 | OPCODE_COMMON_NTWK_PMAC_DEL); | |
6b7c5b94 SP |
589 | |
590 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
591 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); | |
592 | ||
593 | req->if_id = cpu_to_le32(if_id); | |
594 | req->pmac_id = cpu_to_le32(pmac_id); | |
595 | ||
b31c50a7 SP |
596 | status = be_mcc_notify_wait(adapter); |
597 | ||
713d0394 | 598 | err: |
b31c50a7 | 599 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
600 | return status; |
601 | } | |
602 | ||
b31c50a7 | 603 | /* Uses Mbox */ |
8788fdc2 | 604 | int be_cmd_cq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
605 | struct be_queue_info *cq, struct be_queue_info *eq, |
606 | bool sol_evts, bool no_delay, int coalesce_wm) | |
607 | { | |
b31c50a7 SP |
608 | struct be_mcc_wrb *wrb; |
609 | struct be_cmd_req_cq_create *req; | |
6b7c5b94 | 610 | struct be_dma_mem *q_mem = &cq->dma_mem; |
b31c50a7 | 611 | void *ctxt; |
6b7c5b94 SP |
612 | int status; |
613 | ||
8788fdc2 | 614 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
615 | |
616 | wrb = wrb_from_mbox(adapter); | |
617 | req = embedded_payload(wrb); | |
618 | ctxt = &req->context; | |
6b7c5b94 | 619 | |
d744b44e AK |
620 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
621 | OPCODE_COMMON_CQ_CREATE); | |
6b7c5b94 SP |
622 | |
623 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
624 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | |
625 | ||
626 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
627 | ||
628 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm); | |
629 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | |
630 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | |
631 | __ilog2_u32(cq->len/256)); | |
632 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | |
633 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | |
634 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | |
635 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | |
5fb379ee | 636 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); |
6b7c5b94 SP |
637 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
638 | ||
639 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
640 | ||
b31c50a7 | 641 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 642 | if (!status) { |
b31c50a7 | 643 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
644 | cq->id = le16_to_cpu(resp->cq_id); |
645 | cq->created = true; | |
646 | } | |
b31c50a7 | 647 | |
8788fdc2 | 648 | spin_unlock(&adapter->mbox_lock); |
5fb379ee SP |
649 | |
650 | return status; | |
651 | } | |
652 | ||
653 | static u32 be_encoded_q_len(int q_len) | |
654 | { | |
655 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
656 | if (len_encoded == 16) | |
657 | len_encoded = 0; | |
658 | return len_encoded; | |
659 | } | |
660 | ||
8788fdc2 | 661 | int be_cmd_mccq_create(struct be_adapter *adapter, |
5fb379ee SP |
662 | struct be_queue_info *mccq, |
663 | struct be_queue_info *cq) | |
664 | { | |
b31c50a7 SP |
665 | struct be_mcc_wrb *wrb; |
666 | struct be_cmd_req_mcc_create *req; | |
5fb379ee | 667 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
b31c50a7 | 668 | void *ctxt; |
5fb379ee SP |
669 | int status; |
670 | ||
8788fdc2 | 671 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
672 | |
673 | wrb = wrb_from_mbox(adapter); | |
674 | req = embedded_payload(wrb); | |
675 | ctxt = &req->context; | |
5fb379ee | 676 | |
d744b44e AK |
677 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
678 | OPCODE_COMMON_MCC_CREATE); | |
5fb379ee SP |
679 | |
680 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
681 | OPCODE_COMMON_MCC_CREATE, sizeof(*req)); | |
682 | ||
d4a2ac3e | 683 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); |
5fb379ee | 684 | |
5fb379ee SP |
685 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); |
686 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | |
687 | be_encoded_q_len(mccq->len)); | |
688 | AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); | |
689 | ||
690 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
691 | ||
692 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
693 | ||
b31c50a7 | 694 | status = be_mbox_notify_wait(adapter); |
5fb379ee SP |
695 | if (!status) { |
696 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
697 | mccq->id = le16_to_cpu(resp->id); | |
698 | mccq->created = true; | |
699 | } | |
8788fdc2 | 700 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
701 | |
702 | return status; | |
703 | } | |
704 | ||
8788fdc2 | 705 | int be_cmd_txq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
706 | struct be_queue_info *txq, |
707 | struct be_queue_info *cq) | |
708 | { | |
b31c50a7 SP |
709 | struct be_mcc_wrb *wrb; |
710 | struct be_cmd_req_eth_tx_create *req; | |
6b7c5b94 | 711 | struct be_dma_mem *q_mem = &txq->dma_mem; |
b31c50a7 | 712 | void *ctxt; |
6b7c5b94 | 713 | int status; |
6b7c5b94 | 714 | |
8788fdc2 | 715 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
716 | |
717 | wrb = wrb_from_mbox(adapter); | |
718 | req = embedded_payload(wrb); | |
719 | ctxt = &req->context; | |
6b7c5b94 | 720 | |
d744b44e AK |
721 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
722 | OPCODE_ETH_TX_CREATE); | |
6b7c5b94 SP |
723 | |
724 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, | |
725 | sizeof(*req)); | |
726 | ||
727 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
728 | req->ulp_num = BE_ULP1_NUM; | |
729 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | |
730 | ||
b31c50a7 SP |
731 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, |
732 | be_encoded_q_len(txq->len)); | |
6b7c5b94 SP |
733 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); |
734 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | |
735 | ||
736 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
737 | ||
738 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
739 | ||
b31c50a7 | 740 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
741 | if (!status) { |
742 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | |
743 | txq->id = le16_to_cpu(resp->cid); | |
744 | txq->created = true; | |
745 | } | |
b31c50a7 | 746 | |
8788fdc2 | 747 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
748 | |
749 | return status; | |
750 | } | |
751 | ||
b31c50a7 | 752 | /* Uses mbox */ |
8788fdc2 | 753 | int be_cmd_rxq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
754 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, |
755 | u16 max_frame_size, u32 if_id, u32 rss) | |
756 | { | |
b31c50a7 SP |
757 | struct be_mcc_wrb *wrb; |
758 | struct be_cmd_req_eth_rx_create *req; | |
6b7c5b94 SP |
759 | struct be_dma_mem *q_mem = &rxq->dma_mem; |
760 | int status; | |
761 | ||
8788fdc2 | 762 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
763 | |
764 | wrb = wrb_from_mbox(adapter); | |
765 | req = embedded_payload(wrb); | |
6b7c5b94 | 766 | |
d744b44e AK |
767 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
768 | OPCODE_ETH_RX_CREATE); | |
6b7c5b94 SP |
769 | |
770 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, | |
771 | sizeof(*req)); | |
772 | ||
773 | req->cq_id = cpu_to_le16(cq_id); | |
774 | req->frag_size = fls(frag_size) - 1; | |
775 | req->num_pages = 2; | |
776 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
777 | req->interface_id = cpu_to_le32(if_id); | |
778 | req->max_frame_size = cpu_to_le16(max_frame_size); | |
779 | req->rss_queue = cpu_to_le32(rss); | |
780 | ||
b31c50a7 | 781 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
782 | if (!status) { |
783 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | |
784 | rxq->id = le16_to_cpu(resp->id); | |
785 | rxq->created = true; | |
786 | } | |
b31c50a7 | 787 | |
8788fdc2 | 788 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
789 | |
790 | return status; | |
791 | } | |
792 | ||
b31c50a7 SP |
793 | /* Generic destroyer function for all types of queues |
794 | * Uses Mbox | |
795 | */ | |
8788fdc2 | 796 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
6b7c5b94 SP |
797 | int queue_type) |
798 | { | |
b31c50a7 SP |
799 | struct be_mcc_wrb *wrb; |
800 | struct be_cmd_req_q_destroy *req; | |
6b7c5b94 SP |
801 | u8 subsys = 0, opcode = 0; |
802 | int status; | |
803 | ||
cf588477 SP |
804 | if (adapter->eeh_err) |
805 | return -EIO; | |
806 | ||
8788fdc2 | 807 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 808 | |
b31c50a7 SP |
809 | wrb = wrb_from_mbox(adapter); |
810 | req = embedded_payload(wrb); | |
811 | ||
6b7c5b94 SP |
812 | switch (queue_type) { |
813 | case QTYPE_EQ: | |
814 | subsys = CMD_SUBSYSTEM_COMMON; | |
815 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
816 | break; | |
817 | case QTYPE_CQ: | |
818 | subsys = CMD_SUBSYSTEM_COMMON; | |
819 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
820 | break; | |
821 | case QTYPE_TXQ: | |
822 | subsys = CMD_SUBSYSTEM_ETH; | |
823 | opcode = OPCODE_ETH_TX_DESTROY; | |
824 | break; | |
825 | case QTYPE_RXQ: | |
826 | subsys = CMD_SUBSYSTEM_ETH; | |
827 | opcode = OPCODE_ETH_RX_DESTROY; | |
828 | break; | |
5fb379ee SP |
829 | case QTYPE_MCCQ: |
830 | subsys = CMD_SUBSYSTEM_COMMON; | |
831 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
832 | break; | |
6b7c5b94 | 833 | default: |
5f0b849e | 834 | BUG(); |
6b7c5b94 | 835 | } |
d744b44e AK |
836 | |
837 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode); | |
838 | ||
6b7c5b94 SP |
839 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); |
840 | req->id = cpu_to_le16(q->id); | |
841 | ||
b31c50a7 | 842 | status = be_mbox_notify_wait(adapter); |
5f0b849e | 843 | |
8788fdc2 | 844 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
845 | |
846 | return status; | |
847 | } | |
848 | ||
b31c50a7 SP |
849 | /* Create an rx filtering policy configuration on an i/f |
850 | * Uses mbox | |
851 | */ | |
73d540f2 | 852 | int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, |
ba343c77 SB |
853 | u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id, |
854 | u32 domain) | |
6b7c5b94 | 855 | { |
b31c50a7 SP |
856 | struct be_mcc_wrb *wrb; |
857 | struct be_cmd_req_if_create *req; | |
6b7c5b94 SP |
858 | int status; |
859 | ||
8788fdc2 | 860 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
861 | |
862 | wrb = wrb_from_mbox(adapter); | |
863 | req = embedded_payload(wrb); | |
6b7c5b94 | 864 | |
d744b44e AK |
865 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
866 | OPCODE_COMMON_NTWK_INTERFACE_CREATE); | |
6b7c5b94 SP |
867 | |
868 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
869 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); | |
870 | ||
ba343c77 | 871 | req->hdr.domain = domain; |
73d540f2 SP |
872 | req->capability_flags = cpu_to_le32(cap_flags); |
873 | req->enable_flags = cpu_to_le32(en_flags); | |
b31c50a7 | 874 | req->pmac_invalid = pmac_invalid; |
6b7c5b94 SP |
875 | if (!pmac_invalid) |
876 | memcpy(req->mac_addr, mac, ETH_ALEN); | |
877 | ||
b31c50a7 | 878 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
879 | if (!status) { |
880 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | |
881 | *if_handle = le32_to_cpu(resp->interface_id); | |
882 | if (!pmac_invalid) | |
883 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
884 | } | |
885 | ||
8788fdc2 | 886 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
887 | return status; |
888 | } | |
889 | ||
b31c50a7 | 890 | /* Uses mbox */ |
8788fdc2 | 891 | int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id) |
6b7c5b94 | 892 | { |
b31c50a7 SP |
893 | struct be_mcc_wrb *wrb; |
894 | struct be_cmd_req_if_destroy *req; | |
6b7c5b94 SP |
895 | int status; |
896 | ||
cf588477 SP |
897 | if (adapter->eeh_err) |
898 | return -EIO; | |
899 | ||
8788fdc2 | 900 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
901 | |
902 | wrb = wrb_from_mbox(adapter); | |
903 | req = embedded_payload(wrb); | |
6b7c5b94 | 904 | |
d744b44e AK |
905 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
906 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY); | |
6b7c5b94 SP |
907 | |
908 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
909 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | |
910 | ||
911 | req->interface_id = cpu_to_le32(interface_id); | |
b31c50a7 SP |
912 | |
913 | status = be_mbox_notify_wait(adapter); | |
6b7c5b94 | 914 | |
8788fdc2 | 915 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
916 | |
917 | return status; | |
918 | } | |
919 | ||
920 | /* Get stats is a non embedded command: the request is not embedded inside | |
921 | * WRB but is a separate dma memory block | |
b31c50a7 | 922 | * Uses asynchronous MCC |
6b7c5b94 | 923 | */ |
8788fdc2 | 924 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) |
6b7c5b94 | 925 | { |
b31c50a7 SP |
926 | struct be_mcc_wrb *wrb; |
927 | struct be_cmd_req_get_stats *req; | |
928 | struct be_sge *sge; | |
713d0394 | 929 | int status = 0; |
6b7c5b94 | 930 | |
b31c50a7 | 931 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 932 | |
b31c50a7 | 933 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
934 | if (!wrb) { |
935 | status = -EBUSY; | |
936 | goto err; | |
937 | } | |
b31c50a7 SP |
938 | req = nonemb_cmd->va; |
939 | sge = nonembedded_sgl(wrb); | |
6b7c5b94 | 940 | |
d744b44e AK |
941 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, |
942 | OPCODE_ETH_GET_STATISTICS); | |
6b7c5b94 SP |
943 | |
944 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
945 | OPCODE_ETH_GET_STATISTICS, sizeof(*req)); | |
946 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
947 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
948 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
949 | ||
b31c50a7 | 950 | be_mcc_notify(adapter); |
6b7c5b94 | 951 | |
713d0394 | 952 | err: |
b31c50a7 | 953 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 954 | return status; |
6b7c5b94 SP |
955 | } |
956 | ||
b31c50a7 | 957 | /* Uses synchronous mcc */ |
8788fdc2 | 958 | int be_cmd_link_status_query(struct be_adapter *adapter, |
0388f251 | 959 | bool *link_up, u8 *mac_speed, u16 *link_speed) |
6b7c5b94 | 960 | { |
b31c50a7 SP |
961 | struct be_mcc_wrb *wrb; |
962 | struct be_cmd_req_link_status *req; | |
6b7c5b94 SP |
963 | int status; |
964 | ||
b31c50a7 SP |
965 | spin_lock_bh(&adapter->mcc_lock); |
966 | ||
967 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
968 | if (!wrb) { |
969 | status = -EBUSY; | |
970 | goto err; | |
971 | } | |
b31c50a7 | 972 | req = embedded_payload(wrb); |
a8f447bd SP |
973 | |
974 | *link_up = false; | |
6b7c5b94 | 975 | |
d744b44e AK |
976 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
977 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY); | |
6b7c5b94 SP |
978 | |
979 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
980 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | |
981 | ||
b31c50a7 | 982 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
983 | if (!status) { |
984 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | |
0388f251 | 985 | if (resp->mac_speed != PHY_LINK_SPEED_ZERO) { |
a8f447bd | 986 | *link_up = true; |
0388f251 SB |
987 | *link_speed = le16_to_cpu(resp->link_speed); |
988 | *mac_speed = resp->mac_speed; | |
989 | } | |
6b7c5b94 SP |
990 | } |
991 | ||
713d0394 | 992 | err: |
b31c50a7 | 993 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
994 | return status; |
995 | } | |
996 | ||
b31c50a7 | 997 | /* Uses Mbox */ |
8788fdc2 | 998 | int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver) |
6b7c5b94 | 999 | { |
b31c50a7 SP |
1000 | struct be_mcc_wrb *wrb; |
1001 | struct be_cmd_req_get_fw_version *req; | |
6b7c5b94 SP |
1002 | int status; |
1003 | ||
8788fdc2 | 1004 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
1005 | |
1006 | wrb = wrb_from_mbox(adapter); | |
1007 | req = embedded_payload(wrb); | |
6b7c5b94 | 1008 | |
d744b44e AK |
1009 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1010 | OPCODE_COMMON_GET_FW_VERSION); | |
6b7c5b94 SP |
1011 | |
1012 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1013 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | |
1014 | ||
b31c50a7 | 1015 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1016 | if (!status) { |
1017 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | |
1018 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | |
1019 | } | |
1020 | ||
8788fdc2 | 1021 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1022 | return status; |
1023 | } | |
1024 | ||
b31c50a7 SP |
1025 | /* set the EQ delay interval of an EQ to specified value |
1026 | * Uses async mcc | |
1027 | */ | |
8788fdc2 | 1028 | int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) |
6b7c5b94 | 1029 | { |
b31c50a7 SP |
1030 | struct be_mcc_wrb *wrb; |
1031 | struct be_cmd_req_modify_eq_delay *req; | |
713d0394 | 1032 | int status = 0; |
6b7c5b94 | 1033 | |
b31c50a7 SP |
1034 | spin_lock_bh(&adapter->mcc_lock); |
1035 | ||
1036 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1037 | if (!wrb) { |
1038 | status = -EBUSY; | |
1039 | goto err; | |
1040 | } | |
b31c50a7 | 1041 | req = embedded_payload(wrb); |
6b7c5b94 | 1042 | |
d744b44e AK |
1043 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1044 | OPCODE_COMMON_MODIFY_EQ_DELAY); | |
6b7c5b94 SP |
1045 | |
1046 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1047 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); | |
1048 | ||
1049 | req->num_eq = cpu_to_le32(1); | |
1050 | req->delay[0].eq_id = cpu_to_le32(eq_id); | |
1051 | req->delay[0].phase = 0; | |
1052 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | |
1053 | ||
b31c50a7 | 1054 | be_mcc_notify(adapter); |
6b7c5b94 | 1055 | |
713d0394 | 1056 | err: |
b31c50a7 | 1057 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 1058 | return status; |
6b7c5b94 SP |
1059 | } |
1060 | ||
b31c50a7 | 1061 | /* Uses sycnhronous mcc */ |
8788fdc2 | 1062 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
6b7c5b94 SP |
1063 | u32 num, bool untagged, bool promiscuous) |
1064 | { | |
b31c50a7 SP |
1065 | struct be_mcc_wrb *wrb; |
1066 | struct be_cmd_req_vlan_config *req; | |
6b7c5b94 SP |
1067 | int status; |
1068 | ||
b31c50a7 SP |
1069 | spin_lock_bh(&adapter->mcc_lock); |
1070 | ||
1071 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1072 | if (!wrb) { |
1073 | status = -EBUSY; | |
1074 | goto err; | |
1075 | } | |
b31c50a7 | 1076 | req = embedded_payload(wrb); |
6b7c5b94 | 1077 | |
d744b44e AK |
1078 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1079 | OPCODE_COMMON_NTWK_VLAN_CONFIG); | |
6b7c5b94 SP |
1080 | |
1081 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1082 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); | |
1083 | ||
1084 | req->interface_id = if_id; | |
1085 | req->promiscuous = promiscuous; | |
1086 | req->untagged = untagged; | |
1087 | req->num_vlan = num; | |
1088 | if (!promiscuous) { | |
1089 | memcpy(req->normal_vlan, vtag_array, | |
1090 | req->num_vlan * sizeof(vtag_array[0])); | |
1091 | } | |
1092 | ||
b31c50a7 | 1093 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1094 | |
713d0394 | 1095 | err: |
b31c50a7 | 1096 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1097 | return status; |
1098 | } | |
1099 | ||
b31c50a7 SP |
1100 | /* Uses MCC for this command as it may be called in BH context |
1101 | * Uses synchronous mcc | |
1102 | */ | |
8788fdc2 | 1103 | int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en) |
6b7c5b94 | 1104 | { |
6ac7b687 SP |
1105 | struct be_mcc_wrb *wrb; |
1106 | struct be_cmd_req_promiscuous_config *req; | |
b31c50a7 | 1107 | int status; |
6b7c5b94 | 1108 | |
8788fdc2 | 1109 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1110 | |
b31c50a7 | 1111 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1112 | if (!wrb) { |
1113 | status = -EBUSY; | |
1114 | goto err; | |
1115 | } | |
6ac7b687 | 1116 | req = embedded_payload(wrb); |
6b7c5b94 | 1117 | |
d744b44e | 1118 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS); |
6b7c5b94 SP |
1119 | |
1120 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1121 | OPCODE_ETH_PROMISCUOUS, sizeof(*req)); | |
1122 | ||
69d7ce72 SP |
1123 | /* In FW versions X.102.149/X.101.487 and later, |
1124 | * the port setting associated only with the | |
1125 | * issuing pci function will take effect | |
1126 | */ | |
6b7c5b94 SP |
1127 | if (port_num) |
1128 | req->port1_promiscuous = en; | |
1129 | else | |
1130 | req->port0_promiscuous = en; | |
1131 | ||
b31c50a7 | 1132 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1133 | |
713d0394 | 1134 | err: |
8788fdc2 | 1135 | spin_unlock_bh(&adapter->mcc_lock); |
b31c50a7 | 1136 | return status; |
6b7c5b94 SP |
1137 | } |
1138 | ||
6ac7b687 | 1139 | /* |
b31c50a7 | 1140 | * Uses MCC for this command as it may be called in BH context |
6ac7b687 SP |
1141 | * (mc == NULL) => multicast promiscous |
1142 | */ | |
8788fdc2 | 1143 | int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, |
0ddf477b | 1144 | struct net_device *netdev, struct be_dma_mem *mem) |
6b7c5b94 | 1145 | { |
6ac7b687 | 1146 | struct be_mcc_wrb *wrb; |
e7b909a6 SP |
1147 | struct be_cmd_req_mcast_mac_config *req = mem->va; |
1148 | struct be_sge *sge; | |
1149 | int status; | |
6b7c5b94 | 1150 | |
8788fdc2 | 1151 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1152 | |
b31c50a7 | 1153 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1154 | if (!wrb) { |
1155 | status = -EBUSY; | |
1156 | goto err; | |
1157 | } | |
e7b909a6 SP |
1158 | sge = nonembedded_sgl(wrb); |
1159 | memset(req, 0, sizeof(*req)); | |
6b7c5b94 | 1160 | |
d744b44e AK |
1161 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, |
1162 | OPCODE_COMMON_NTWK_MULTICAST_SET); | |
e7b909a6 SP |
1163 | sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); |
1164 | sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); | |
1165 | sge->len = cpu_to_le32(mem->size); | |
6b7c5b94 SP |
1166 | |
1167 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1168 | OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req)); | |
1169 | ||
1170 | req->interface_id = if_id; | |
0ddf477b | 1171 | if (netdev) { |
24307eef | 1172 | int i; |
22bedad3 | 1173 | struct netdev_hw_addr *ha; |
24307eef | 1174 | |
0ddf477b | 1175 | req->num_mac = cpu_to_le16(netdev_mc_count(netdev)); |
24307eef | 1176 | |
0ddf477b | 1177 | i = 0; |
22bedad3 JP |
1178 | netdev_for_each_mc_addr(ha, netdev) |
1179 | memcpy(req->mac[i].byte, ha->addr, ETH_ALEN); | |
24307eef SP |
1180 | } else { |
1181 | req->promiscuous = 1; | |
6b7c5b94 SP |
1182 | } |
1183 | ||
e7b909a6 | 1184 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1185 | |
713d0394 | 1186 | err: |
8788fdc2 | 1187 | spin_unlock_bh(&adapter->mcc_lock); |
e7b909a6 | 1188 | return status; |
6b7c5b94 SP |
1189 | } |
1190 | ||
b31c50a7 | 1191 | /* Uses synchrounous mcc */ |
8788fdc2 | 1192 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) |
6b7c5b94 | 1193 | { |
b31c50a7 SP |
1194 | struct be_mcc_wrb *wrb; |
1195 | struct be_cmd_req_set_flow_control *req; | |
6b7c5b94 SP |
1196 | int status; |
1197 | ||
b31c50a7 | 1198 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1199 | |
b31c50a7 | 1200 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1201 | if (!wrb) { |
1202 | status = -EBUSY; | |
1203 | goto err; | |
1204 | } | |
b31c50a7 | 1205 | req = embedded_payload(wrb); |
6b7c5b94 | 1206 | |
d744b44e AK |
1207 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1208 | OPCODE_COMMON_SET_FLOW_CONTROL); | |
6b7c5b94 SP |
1209 | |
1210 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1211 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); | |
1212 | ||
1213 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | |
1214 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | |
1215 | ||
b31c50a7 | 1216 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1217 | |
713d0394 | 1218 | err: |
b31c50a7 | 1219 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1220 | return status; |
1221 | } | |
1222 | ||
b31c50a7 | 1223 | /* Uses sycn mcc */ |
8788fdc2 | 1224 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) |
6b7c5b94 | 1225 | { |
b31c50a7 SP |
1226 | struct be_mcc_wrb *wrb; |
1227 | struct be_cmd_req_get_flow_control *req; | |
6b7c5b94 SP |
1228 | int status; |
1229 | ||
b31c50a7 | 1230 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1231 | |
b31c50a7 | 1232 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1233 | if (!wrb) { |
1234 | status = -EBUSY; | |
1235 | goto err; | |
1236 | } | |
b31c50a7 | 1237 | req = embedded_payload(wrb); |
6b7c5b94 | 1238 | |
d744b44e AK |
1239 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1240 | OPCODE_COMMON_GET_FLOW_CONTROL); | |
6b7c5b94 SP |
1241 | |
1242 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1243 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | |
1244 | ||
b31c50a7 | 1245 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1246 | if (!status) { |
1247 | struct be_cmd_resp_get_flow_control *resp = | |
1248 | embedded_payload(wrb); | |
1249 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | |
1250 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | |
1251 | } | |
1252 | ||
713d0394 | 1253 | err: |
b31c50a7 | 1254 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1255 | return status; |
1256 | } | |
1257 | ||
b31c50a7 | 1258 | /* Uses mbox */ |
dcb9b564 | 1259 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap) |
6b7c5b94 | 1260 | { |
b31c50a7 SP |
1261 | struct be_mcc_wrb *wrb; |
1262 | struct be_cmd_req_query_fw_cfg *req; | |
6b7c5b94 SP |
1263 | int status; |
1264 | ||
8788fdc2 | 1265 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 1266 | |
b31c50a7 SP |
1267 | wrb = wrb_from_mbox(adapter); |
1268 | req = embedded_payload(wrb); | |
6b7c5b94 | 1269 | |
d744b44e AK |
1270 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1271 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG); | |
6b7c5b94 SP |
1272 | |
1273 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1274 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | |
1275 | ||
b31c50a7 | 1276 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1277 | if (!status) { |
1278 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | |
1279 | *port_num = le32_to_cpu(resp->phys_port); | |
dcb9b564 | 1280 | *cap = le32_to_cpu(resp->function_cap); |
6b7c5b94 SP |
1281 | } |
1282 | ||
8788fdc2 | 1283 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1284 | return status; |
1285 | } | |
14074eab | 1286 | |
b31c50a7 | 1287 | /* Uses mbox */ |
14074eab | 1288 | int be_cmd_reset_function(struct be_adapter *adapter) |
1289 | { | |
b31c50a7 SP |
1290 | struct be_mcc_wrb *wrb; |
1291 | struct be_cmd_req_hdr *req; | |
14074eab | 1292 | int status; |
1293 | ||
1294 | spin_lock(&adapter->mbox_lock); | |
1295 | ||
b31c50a7 SP |
1296 | wrb = wrb_from_mbox(adapter); |
1297 | req = embedded_payload(wrb); | |
14074eab | 1298 | |
d744b44e AK |
1299 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1300 | OPCODE_COMMON_FUNCTION_RESET); | |
14074eab | 1301 | |
1302 | be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, | |
1303 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); | |
1304 | ||
b31c50a7 | 1305 | status = be_mbox_notify_wait(adapter); |
14074eab | 1306 | |
1307 | spin_unlock(&adapter->mbox_lock); | |
1308 | return status; | |
1309 | } | |
84517482 | 1310 | |
fad9ab2c SB |
1311 | /* Uses sync mcc */ |
1312 | int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, | |
1313 | u8 bcn, u8 sts, u8 state) | |
1314 | { | |
1315 | struct be_mcc_wrb *wrb; | |
1316 | struct be_cmd_req_enable_disable_beacon *req; | |
1317 | int status; | |
1318 | ||
1319 | spin_lock_bh(&adapter->mcc_lock); | |
1320 | ||
1321 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1322 | if (!wrb) { |
1323 | status = -EBUSY; | |
1324 | goto err; | |
1325 | } | |
fad9ab2c SB |
1326 | req = embedded_payload(wrb); |
1327 | ||
d744b44e AK |
1328 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1329 | OPCODE_COMMON_ENABLE_DISABLE_BEACON); | |
fad9ab2c SB |
1330 | |
1331 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1332 | OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req)); | |
1333 | ||
1334 | req->port_num = port_num; | |
1335 | req->beacon_state = state; | |
1336 | req->beacon_duration = bcn; | |
1337 | req->status_duration = sts; | |
1338 | ||
1339 | status = be_mcc_notify_wait(adapter); | |
1340 | ||
713d0394 | 1341 | err: |
fad9ab2c SB |
1342 | spin_unlock_bh(&adapter->mcc_lock); |
1343 | return status; | |
1344 | } | |
1345 | ||
1346 | /* Uses sync mcc */ | |
1347 | int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) | |
1348 | { | |
1349 | struct be_mcc_wrb *wrb; | |
1350 | struct be_cmd_req_get_beacon_state *req; | |
1351 | int status; | |
1352 | ||
1353 | spin_lock_bh(&adapter->mcc_lock); | |
1354 | ||
1355 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1356 | if (!wrb) { |
1357 | status = -EBUSY; | |
1358 | goto err; | |
1359 | } | |
fad9ab2c SB |
1360 | req = embedded_payload(wrb); |
1361 | ||
d744b44e AK |
1362 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1363 | OPCODE_COMMON_GET_BEACON_STATE); | |
fad9ab2c SB |
1364 | |
1365 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1366 | OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req)); | |
1367 | ||
1368 | req->port_num = port_num; | |
1369 | ||
1370 | status = be_mcc_notify_wait(adapter); | |
1371 | if (!status) { | |
1372 | struct be_cmd_resp_get_beacon_state *resp = | |
1373 | embedded_payload(wrb); | |
1374 | *state = resp->beacon_state; | |
1375 | } | |
1376 | ||
713d0394 | 1377 | err: |
fad9ab2c SB |
1378 | spin_unlock_bh(&adapter->mcc_lock); |
1379 | return status; | |
1380 | } | |
1381 | ||
0388f251 SB |
1382 | /* Uses sync mcc */ |
1383 | int be_cmd_read_port_type(struct be_adapter *adapter, u32 port, | |
1384 | u8 *connector) | |
1385 | { | |
1386 | struct be_mcc_wrb *wrb; | |
1387 | struct be_cmd_req_port_type *req; | |
1388 | int status; | |
1389 | ||
1390 | spin_lock_bh(&adapter->mcc_lock); | |
1391 | ||
1392 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1393 | if (!wrb) { |
1394 | status = -EBUSY; | |
1395 | goto err; | |
1396 | } | |
0388f251 SB |
1397 | req = embedded_payload(wrb); |
1398 | ||
d744b44e AK |
1399 | be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0, |
1400 | OPCODE_COMMON_READ_TRANSRECV_DATA); | |
0388f251 SB |
1401 | |
1402 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1403 | OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req)); | |
1404 | ||
1405 | req->port = cpu_to_le32(port); | |
1406 | req->page_num = cpu_to_le32(TR_PAGE_A0); | |
1407 | status = be_mcc_notify_wait(adapter); | |
1408 | if (!status) { | |
1409 | struct be_cmd_resp_port_type *resp = embedded_payload(wrb); | |
1410 | *connector = resp->data.connector; | |
1411 | } | |
1412 | ||
713d0394 | 1413 | err: |
0388f251 SB |
1414 | spin_unlock_bh(&adapter->mcc_lock); |
1415 | return status; | |
1416 | } | |
1417 | ||
84517482 AK |
1418 | int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, |
1419 | u32 flash_type, u32 flash_opcode, u32 buf_size) | |
1420 | { | |
b31c50a7 | 1421 | struct be_mcc_wrb *wrb; |
3f0d4560 | 1422 | struct be_cmd_write_flashrom *req; |
b31c50a7 | 1423 | struct be_sge *sge; |
84517482 AK |
1424 | int status; |
1425 | ||
b31c50a7 | 1426 | spin_lock_bh(&adapter->mcc_lock); |
dd131e76 | 1427 | adapter->flash_status = 0; |
b31c50a7 SP |
1428 | |
1429 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1430 | if (!wrb) { |
1431 | status = -EBUSY; | |
1432 | goto err; | |
1433 | } | |
1434 | req = cmd->va; | |
b31c50a7 SP |
1435 | sge = nonembedded_sgl(wrb); |
1436 | ||
d744b44e AK |
1437 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, |
1438 | OPCODE_COMMON_WRITE_FLASHROM); | |
dd131e76 | 1439 | wrb->tag1 = CMD_SUBSYSTEM_COMMON; |
84517482 AK |
1440 | |
1441 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1442 | OPCODE_COMMON_WRITE_FLASHROM, cmd->size); | |
1443 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1444 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1445 | sge->len = cpu_to_le32(cmd->size); | |
1446 | ||
1447 | req->params.op_type = cpu_to_le32(flash_type); | |
1448 | req->params.op_code = cpu_to_le32(flash_opcode); | |
1449 | req->params.data_buf_size = cpu_to_le32(buf_size); | |
1450 | ||
dd131e76 SB |
1451 | be_mcc_notify(adapter); |
1452 | spin_unlock_bh(&adapter->mcc_lock); | |
1453 | ||
1454 | if (!wait_for_completion_timeout(&adapter->flash_compl, | |
1455 | msecs_to_jiffies(12000))) | |
1456 | status = -1; | |
1457 | else | |
1458 | status = adapter->flash_status; | |
84517482 | 1459 | |
713d0394 | 1460 | err: |
84517482 AK |
1461 | return status; |
1462 | } | |
fa9a6fed | 1463 | |
3f0d4560 AK |
1464 | int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, |
1465 | int offset) | |
fa9a6fed SB |
1466 | { |
1467 | struct be_mcc_wrb *wrb; | |
1468 | struct be_cmd_write_flashrom *req; | |
1469 | int status; | |
1470 | ||
1471 | spin_lock_bh(&adapter->mcc_lock); | |
1472 | ||
1473 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1474 | if (!wrb) { |
1475 | status = -EBUSY; | |
1476 | goto err; | |
1477 | } | |
fa9a6fed SB |
1478 | req = embedded_payload(wrb); |
1479 | ||
d744b44e AK |
1480 | be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0, |
1481 | OPCODE_COMMON_READ_FLASHROM); | |
fa9a6fed SB |
1482 | |
1483 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1484 | OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4); | |
1485 | ||
3f0d4560 | 1486 | req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT); |
fa9a6fed | 1487 | req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); |
8b93b710 AK |
1488 | req->params.offset = cpu_to_le32(offset); |
1489 | req->params.data_buf_size = cpu_to_le32(0x4); | |
fa9a6fed SB |
1490 | |
1491 | status = be_mcc_notify_wait(adapter); | |
1492 | if (!status) | |
1493 | memcpy(flashed_crc, req->params.data_buf, 4); | |
1494 | ||
713d0394 | 1495 | err: |
fa9a6fed SB |
1496 | spin_unlock_bh(&adapter->mcc_lock); |
1497 | return status; | |
1498 | } | |
71d8d1b5 AK |
1499 | |
1500 | extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, | |
1501 | struct be_dma_mem *nonemb_cmd) | |
1502 | { | |
1503 | struct be_mcc_wrb *wrb; | |
1504 | struct be_cmd_req_acpi_wol_magic_config *req; | |
1505 | struct be_sge *sge; | |
1506 | int status; | |
1507 | ||
1508 | spin_lock_bh(&adapter->mcc_lock); | |
1509 | ||
1510 | wrb = wrb_from_mccq(adapter); | |
1511 | if (!wrb) { | |
1512 | status = -EBUSY; | |
1513 | goto err; | |
1514 | } | |
1515 | req = nonemb_cmd->va; | |
1516 | sge = nonembedded_sgl(wrb); | |
1517 | ||
1518 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
1519 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG); | |
1520 | ||
1521 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1522 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req)); | |
1523 | memcpy(req->magic_mac, mac, ETH_ALEN); | |
1524 | ||
1525 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
1526 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1527 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1528 | ||
1529 | status = be_mcc_notify_wait(adapter); | |
1530 | ||
1531 | err: | |
1532 | spin_unlock_bh(&adapter->mcc_lock); | |
1533 | return status; | |
1534 | } | |
ff33a6e2 | 1535 | |
fced9999 SB |
1536 | int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, |
1537 | u8 loopback_type, u8 enable) | |
1538 | { | |
1539 | struct be_mcc_wrb *wrb; | |
1540 | struct be_cmd_req_set_lmode *req; | |
1541 | int status; | |
1542 | ||
1543 | spin_lock_bh(&adapter->mcc_lock); | |
1544 | ||
1545 | wrb = wrb_from_mccq(adapter); | |
1546 | if (!wrb) { | |
1547 | status = -EBUSY; | |
1548 | goto err; | |
1549 | } | |
1550 | ||
1551 | req = embedded_payload(wrb); | |
1552 | ||
1553 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1554 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE); | |
1555 | ||
1556 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1557 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, | |
1558 | sizeof(*req)); | |
1559 | ||
1560 | req->src_port = port_num; | |
1561 | req->dest_port = port_num; | |
1562 | req->loopback_type = loopback_type; | |
1563 | req->loopback_state = enable; | |
1564 | ||
1565 | status = be_mcc_notify_wait(adapter); | |
1566 | err: | |
1567 | spin_unlock_bh(&adapter->mcc_lock); | |
1568 | return status; | |
1569 | } | |
1570 | ||
ff33a6e2 S |
1571 | int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, |
1572 | u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) | |
1573 | { | |
1574 | struct be_mcc_wrb *wrb; | |
1575 | struct be_cmd_req_loopback_test *req; | |
1576 | int status; | |
1577 | ||
1578 | spin_lock_bh(&adapter->mcc_lock); | |
1579 | ||
1580 | wrb = wrb_from_mccq(adapter); | |
1581 | if (!wrb) { | |
1582 | status = -EBUSY; | |
1583 | goto err; | |
1584 | } | |
1585 | ||
1586 | req = embedded_payload(wrb); | |
1587 | ||
1588 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1589 | OPCODE_LOWLEVEL_LOOPBACK_TEST); | |
1590 | ||
1591 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1592 | OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req)); | |
d7b90141 | 1593 | req->hdr.timeout = 4; |
ff33a6e2 S |
1594 | |
1595 | req->pattern = cpu_to_le64(pattern); | |
1596 | req->src_port = cpu_to_le32(port_num); | |
1597 | req->dest_port = cpu_to_le32(port_num); | |
1598 | req->pkt_size = cpu_to_le32(pkt_size); | |
1599 | req->num_pkts = cpu_to_le32(num_pkts); | |
1600 | req->loopback_type = cpu_to_le32(loopback_type); | |
1601 | ||
1602 | status = be_mcc_notify_wait(adapter); | |
1603 | if (!status) { | |
1604 | struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); | |
1605 | status = le32_to_cpu(resp->status); | |
1606 | } | |
1607 | ||
1608 | err: | |
1609 | spin_unlock_bh(&adapter->mcc_lock); | |
1610 | return status; | |
1611 | } | |
1612 | ||
1613 | int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, | |
1614 | u32 byte_cnt, struct be_dma_mem *cmd) | |
1615 | { | |
1616 | struct be_mcc_wrb *wrb; | |
1617 | struct be_cmd_req_ddrdma_test *req; | |
1618 | struct be_sge *sge; | |
1619 | int status; | |
1620 | int i, j = 0; | |
1621 | ||
1622 | spin_lock_bh(&adapter->mcc_lock); | |
1623 | ||
1624 | wrb = wrb_from_mccq(adapter); | |
1625 | if (!wrb) { | |
1626 | status = -EBUSY; | |
1627 | goto err; | |
1628 | } | |
1629 | req = cmd->va; | |
1630 | sge = nonembedded_sgl(wrb); | |
1631 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, | |
1632 | OPCODE_LOWLEVEL_HOST_DDR_DMA); | |
1633 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1634 | OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size); | |
1635 | ||
1636 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1637 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1638 | sge->len = cpu_to_le32(cmd->size); | |
1639 | ||
1640 | req->pattern = cpu_to_le64(pattern); | |
1641 | req->byte_count = cpu_to_le32(byte_cnt); | |
1642 | for (i = 0; i < byte_cnt; i++) { | |
1643 | req->snd_buff[i] = (u8)(pattern >> (j*8)); | |
1644 | j++; | |
1645 | if (j > 7) | |
1646 | j = 0; | |
1647 | } | |
1648 | ||
1649 | status = be_mcc_notify_wait(adapter); | |
1650 | ||
1651 | if (!status) { | |
1652 | struct be_cmd_resp_ddrdma_test *resp; | |
1653 | resp = cmd->va; | |
1654 | if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || | |
1655 | resp->snd_err) { | |
1656 | status = -1; | |
1657 | } | |
1658 | } | |
1659 | ||
1660 | err: | |
1661 | spin_unlock_bh(&adapter->mcc_lock); | |
1662 | return status; | |
1663 | } | |
368c0ca2 SB |
1664 | |
1665 | extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, | |
1666 | struct be_dma_mem *nonemb_cmd) | |
1667 | { | |
1668 | struct be_mcc_wrb *wrb; | |
1669 | struct be_cmd_req_seeprom_read *req; | |
1670 | struct be_sge *sge; | |
1671 | int status; | |
1672 | ||
1673 | spin_lock_bh(&adapter->mcc_lock); | |
1674 | ||
1675 | wrb = wrb_from_mccq(adapter); | |
1676 | req = nonemb_cmd->va; | |
1677 | sge = nonembedded_sgl(wrb); | |
1678 | ||
1679 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
1680 | OPCODE_COMMON_SEEPROM_READ); | |
1681 | ||
1682 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1683 | OPCODE_COMMON_SEEPROM_READ, sizeof(*req)); | |
1684 | ||
1685 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
1686 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1687 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1688 | ||
1689 | status = be_mcc_notify_wait(adapter); | |
1690 | ||
1691 | spin_unlock_bh(&adapter->mcc_lock); | |
1692 | return status; | |
1693 | } |