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6b7c5b94 SP |
1 | /* |
2 | * Copyright (C) 2005 - 2009 ServerEngines | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | #include "be.h" | |
8788fdc2 | 19 | #include "be_cmds.h" |
6b7c5b94 | 20 | |
8788fdc2 | 21 | static void be_mcc_notify(struct be_adapter *adapter) |
5fb379ee | 22 | { |
8788fdc2 | 23 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
5fb379ee SP |
24 | u32 val = 0; |
25 | ||
26 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | |
27 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
8788fdc2 | 28 | iowrite32(val, adapter->db + DB_MCCQ_OFFSET); |
5fb379ee SP |
29 | } |
30 | ||
31 | /* To check if valid bit is set, check the entire word as we don't know | |
32 | * the endianness of the data (old entry is host endian while a new entry is | |
33 | * little endian) */ | |
efd2e40a | 34 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) |
5fb379ee SP |
35 | { |
36 | if (compl->flags != 0) { | |
37 | compl->flags = le32_to_cpu(compl->flags); | |
38 | BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); | |
39 | return true; | |
40 | } else { | |
41 | return false; | |
42 | } | |
43 | } | |
44 | ||
45 | /* Need to reset the entire word that houses the valid bit */ | |
efd2e40a | 46 | static inline void be_mcc_compl_use(struct be_mcc_compl *compl) |
5fb379ee SP |
47 | { |
48 | compl->flags = 0; | |
49 | } | |
50 | ||
8788fdc2 | 51 | static int be_mcc_compl_process(struct be_adapter *adapter, |
efd2e40a | 52 | struct be_mcc_compl *compl) |
5fb379ee SP |
53 | { |
54 | u16 compl_status, extd_status; | |
55 | ||
56 | /* Just swap the status to host endian; mcc tag is opaquely copied | |
57 | * from mcc_wrb */ | |
58 | be_dws_le_to_cpu(compl, 4); | |
59 | ||
60 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & | |
61 | CQE_STATUS_COMPL_MASK; | |
b31c50a7 SP |
62 | if (compl_status == MCC_STATUS_SUCCESS) { |
63 | if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) { | |
64 | struct be_cmd_resp_get_stats *resp = | |
65 | adapter->stats.cmd.va; | |
66 | be_dws_le_to_cpu(&resp->hw_stats, | |
67 | sizeof(resp->hw_stats)); | |
68 | netdev_stats_update(adapter); | |
69 | } | |
70 | } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) { | |
5fb379ee SP |
71 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & |
72 | CQE_STATUS_EXTD_MASK; | |
5f0b849e SP |
73 | dev_warn(&adapter->pdev->dev, |
74 | "Error in cmd completion: status(compl/extd)=%d/%d\n", | |
5fb379ee | 75 | compl_status, extd_status); |
5fb379ee | 76 | } |
b31c50a7 | 77 | return compl_status; |
5fb379ee SP |
78 | } |
79 | ||
a8f447bd | 80 | /* Link state evt is a string of bytes; no need for endian swapping */ |
8788fdc2 | 81 | static void be_async_link_state_process(struct be_adapter *adapter, |
a8f447bd SP |
82 | struct be_async_event_link_state *evt) |
83 | { | |
8788fdc2 SP |
84 | be_link_status_update(adapter, |
85 | evt->port_link_status == ASYNC_EVENT_LINK_UP); | |
a8f447bd SP |
86 | } |
87 | ||
88 | static inline bool is_link_state_evt(u32 trailer) | |
89 | { | |
90 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | |
91 | ASYNC_TRAILER_EVENT_CODE_MASK) == | |
92 | ASYNC_EVENT_CODE_LINK_STATE); | |
93 | } | |
5fb379ee | 94 | |
efd2e40a | 95 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) |
5fb379ee | 96 | { |
8788fdc2 | 97 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
efd2e40a | 98 | struct be_mcc_compl *compl = queue_tail_node(mcc_cq); |
5fb379ee SP |
99 | |
100 | if (be_mcc_compl_is_new(compl)) { | |
101 | queue_tail_inc(mcc_cq); | |
102 | return compl; | |
103 | } | |
104 | return NULL; | |
105 | } | |
106 | ||
b31c50a7 | 107 | int be_process_mcc(struct be_adapter *adapter) |
5fb379ee | 108 | { |
efd2e40a | 109 | struct be_mcc_compl *compl; |
b31c50a7 | 110 | int num = 0, status = 0; |
5fb379ee | 111 | |
8788fdc2 SP |
112 | spin_lock_bh(&adapter->mcc_cq_lock); |
113 | while ((compl = be_mcc_compl_get(adapter))) { | |
a8f447bd SP |
114 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { |
115 | /* Interpret flags as an async trailer */ | |
116 | BUG_ON(!is_link_state_evt(compl->flags)); | |
117 | ||
118 | /* Interpret compl as a async link evt */ | |
8788fdc2 | 119 | be_async_link_state_process(adapter, |
a8f447bd | 120 | (struct be_async_event_link_state *) compl); |
b31c50a7 SP |
121 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
122 | status = be_mcc_compl_process(adapter, compl); | |
123 | atomic_dec(&adapter->mcc_obj.q.used); | |
5fb379ee SP |
124 | } |
125 | be_mcc_compl_use(compl); | |
126 | num++; | |
127 | } | |
b31c50a7 | 128 | |
5fb379ee | 129 | if (num) |
8788fdc2 | 130 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, num); |
b31c50a7 | 131 | |
8788fdc2 | 132 | spin_unlock_bh(&adapter->mcc_cq_lock); |
b31c50a7 | 133 | return status; |
5fb379ee SP |
134 | } |
135 | ||
6ac7b687 | 136 | /* Wait till no more pending mcc requests are present */ |
b31c50a7 | 137 | static int be_mcc_wait_compl(struct be_adapter *adapter) |
6ac7b687 | 138 | { |
b31c50a7 SP |
139 | #define mcc_timeout 120000 /* 12s timeout */ |
140 | int i, status; | |
6ac7b687 | 141 | for (i = 0; i < mcc_timeout; i++) { |
b31c50a7 SP |
142 | status = be_process_mcc(adapter); |
143 | if (status) | |
144 | return status; | |
145 | ||
8788fdc2 | 146 | if (atomic_read(&adapter->mcc_obj.q.used) == 0) |
6ac7b687 SP |
147 | break; |
148 | udelay(100); | |
149 | } | |
b31c50a7 | 150 | if (i == mcc_timeout) { |
5f0b849e | 151 | dev_err(&adapter->pdev->dev, "mccq poll timed out\n"); |
b31c50a7 SP |
152 | return -1; |
153 | } | |
154 | return 0; | |
6ac7b687 SP |
155 | } |
156 | ||
157 | /* Notify MCC requests and wait for completion */ | |
b31c50a7 | 158 | static int be_mcc_notify_wait(struct be_adapter *adapter) |
6ac7b687 | 159 | { |
8788fdc2 | 160 | be_mcc_notify(adapter); |
b31c50a7 | 161 | return be_mcc_wait_compl(adapter); |
6ac7b687 SP |
162 | } |
163 | ||
5f0b849e | 164 | static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) |
6b7c5b94 SP |
165 | { |
166 | int cnt = 0, wait = 5; | |
167 | u32 ready; | |
168 | ||
169 | do { | |
170 | ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK; | |
171 | if (ready) | |
172 | break; | |
173 | ||
84517482 | 174 | if (cnt > 4000000) { |
5f0b849e | 175 | dev_err(&adapter->pdev->dev, "mbox poll timed out\n"); |
6b7c5b94 SP |
176 | return -1; |
177 | } | |
178 | ||
179 | if (cnt > 50) | |
180 | wait = 200; | |
181 | cnt += wait; | |
182 | udelay(wait); | |
183 | } while (true); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | /* | |
189 | * Insert the mailbox address into the doorbell in two steps | |
5fb379ee | 190 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs |
6b7c5b94 | 191 | */ |
b31c50a7 | 192 | static int be_mbox_notify_wait(struct be_adapter *adapter) |
6b7c5b94 SP |
193 | { |
194 | int status; | |
6b7c5b94 | 195 | u32 val = 0; |
8788fdc2 SP |
196 | void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; |
197 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; | |
6b7c5b94 | 198 | struct be_mcc_mailbox *mbox = mbox_mem->va; |
efd2e40a | 199 | struct be_mcc_compl *compl = &mbox->compl; |
6b7c5b94 | 200 | |
6b7c5b94 SP |
201 | val |= MPU_MAILBOX_DB_HI_MASK; |
202 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | |
203 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
204 | iowrite32(val, db); | |
205 | ||
206 | /* wait for ready to be set */ | |
5f0b849e | 207 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
208 | if (status != 0) |
209 | return status; | |
210 | ||
211 | val = 0; | |
6b7c5b94 SP |
212 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ |
213 | val |= (u32)(mbox_mem->dma >> 4) << 2; | |
214 | iowrite32(val, db); | |
215 | ||
5f0b849e | 216 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
217 | if (status != 0) |
218 | return status; | |
219 | ||
5fb379ee | 220 | /* A cq entry has been made now */ |
efd2e40a SP |
221 | if (be_mcc_compl_is_new(compl)) { |
222 | status = be_mcc_compl_process(adapter, &mbox->compl); | |
223 | be_mcc_compl_use(compl); | |
5fb379ee SP |
224 | if (status) |
225 | return status; | |
226 | } else { | |
5f0b849e | 227 | dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); |
6b7c5b94 SP |
228 | return -1; |
229 | } | |
5fb379ee | 230 | return 0; |
6b7c5b94 SP |
231 | } |
232 | ||
8788fdc2 | 233 | static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage) |
6b7c5b94 | 234 | { |
8788fdc2 | 235 | u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET); |
6b7c5b94 SP |
236 | |
237 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | |
238 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | |
239 | return -1; | |
240 | else | |
241 | return 0; | |
242 | } | |
243 | ||
8788fdc2 | 244 | int be_cmd_POST(struct be_adapter *adapter) |
6b7c5b94 SP |
245 | { |
246 | u16 stage, error; | |
247 | ||
8788fdc2 | 248 | error = be_POST_stage_get(adapter, &stage); |
d9509ac1 SP |
249 | if (error || stage != POST_STAGE_ARMFW_RDY) { |
250 | dev_err(&adapter->pdev->dev, "POST failed.\n"); | |
251 | return -1; | |
252 | } | |
6b7c5b94 SP |
253 | |
254 | return 0; | |
6b7c5b94 SP |
255 | } |
256 | ||
257 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) | |
258 | { | |
259 | return wrb->payload.embedded_payload; | |
260 | } | |
261 | ||
262 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | |
263 | { | |
264 | return &wrb->payload.sgl[0]; | |
265 | } | |
266 | ||
267 | /* Don't touch the hdr after it's prepared */ | |
268 | static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | |
269 | bool embedded, u8 sge_cnt) | |
270 | { | |
271 | if (embedded) | |
272 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
273 | else | |
274 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | |
275 | MCC_WRB_SGE_CNT_SHIFT; | |
276 | wrb->payload_length = payload_len; | |
277 | be_dws_cpu_to_le(wrb, 20); | |
278 | } | |
279 | ||
280 | /* Don't touch the hdr after it's prepared */ | |
281 | static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
282 | u8 subsystem, u8 opcode, int cmd_len) | |
283 | { | |
284 | req_hdr->opcode = opcode; | |
285 | req_hdr->subsystem = subsystem; | |
286 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
287 | } | |
288 | ||
289 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
290 | struct be_dma_mem *mem) | |
291 | { | |
292 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
293 | u64 dma = (u64)mem->dma; | |
294 | ||
295 | for (i = 0; i < buf_pages; i++) { | |
296 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
297 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
298 | dma += PAGE_SIZE_4K; | |
299 | } | |
300 | } | |
301 | ||
302 | /* Converts interrupt delay in microseconds to multiplier value */ | |
303 | static u32 eq_delay_to_mult(u32 usec_delay) | |
304 | { | |
305 | #define MAX_INTR_RATE 651042 | |
306 | const u32 round = 10; | |
307 | u32 multiplier; | |
308 | ||
309 | if (usec_delay == 0) | |
310 | multiplier = 0; | |
311 | else { | |
312 | u32 interrupt_rate = 1000000 / usec_delay; | |
313 | /* Max delay, corresponding to the lowest interrupt rate */ | |
314 | if (interrupt_rate == 0) | |
315 | multiplier = 1023; | |
316 | else { | |
317 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
318 | multiplier /= interrupt_rate; | |
319 | /* Round the multiplier to the closest value.*/ | |
320 | multiplier = (multiplier + round/2) / round; | |
321 | multiplier = min(multiplier, (u32)1023); | |
322 | } | |
323 | } | |
324 | return multiplier; | |
325 | } | |
326 | ||
b31c50a7 | 327 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) |
6b7c5b94 | 328 | { |
b31c50a7 SP |
329 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; |
330 | struct be_mcc_wrb *wrb | |
331 | = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
332 | memset(wrb, 0, sizeof(*wrb)); | |
333 | return wrb; | |
6b7c5b94 SP |
334 | } |
335 | ||
b31c50a7 | 336 | static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) |
5fb379ee | 337 | { |
b31c50a7 SP |
338 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
339 | struct be_mcc_wrb *wrb; | |
340 | ||
341 | BUG_ON(atomic_read(&mccq->used) >= mccq->len); | |
342 | wrb = queue_head_node(mccq); | |
343 | queue_head_inc(mccq); | |
344 | atomic_inc(&mccq->used); | |
345 | memset(wrb, 0, sizeof(*wrb)); | |
5fb379ee SP |
346 | return wrb; |
347 | } | |
348 | ||
8788fdc2 | 349 | int be_cmd_eq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
350 | struct be_queue_info *eq, int eq_delay) |
351 | { | |
b31c50a7 SP |
352 | struct be_mcc_wrb *wrb; |
353 | struct be_cmd_req_eq_create *req; | |
6b7c5b94 SP |
354 | struct be_dma_mem *q_mem = &eq->dma_mem; |
355 | int status; | |
356 | ||
8788fdc2 | 357 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
358 | |
359 | wrb = wrb_from_mbox(adapter); | |
360 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
361 | |
362 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
363 | ||
364 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
365 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | |
366 | ||
367 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
368 | ||
369 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, | |
eec368fb | 370 | be_pci_func(adapter)); |
6b7c5b94 SP |
371 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); |
372 | /* 4byte eqe*/ | |
373 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
374 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
375 | __ilog2_u32(eq->len/256)); | |
376 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
377 | eq_delay_to_mult(eq_delay)); | |
378 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
379 | ||
380 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
381 | ||
b31c50a7 | 382 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 383 | if (!status) { |
b31c50a7 | 384 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
385 | eq->id = le16_to_cpu(resp->eq_id); |
386 | eq->created = true; | |
387 | } | |
b31c50a7 | 388 | |
8788fdc2 | 389 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
390 | return status; |
391 | } | |
392 | ||
b31c50a7 | 393 | /* Uses mbox */ |
8788fdc2 | 394 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
395 | u8 type, bool permanent, u32 if_handle) |
396 | { | |
b31c50a7 SP |
397 | struct be_mcc_wrb *wrb; |
398 | struct be_cmd_req_mac_query *req; | |
6b7c5b94 SP |
399 | int status; |
400 | ||
8788fdc2 | 401 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
402 | |
403 | wrb = wrb_from_mbox(adapter); | |
404 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
405 | |
406 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
407 | ||
408 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
409 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); | |
410 | ||
411 | req->type = type; | |
412 | if (permanent) { | |
413 | req->permanent = 1; | |
414 | } else { | |
b31c50a7 | 415 | req->if_id = cpu_to_le16((u16) if_handle); |
6b7c5b94 SP |
416 | req->permanent = 0; |
417 | } | |
418 | ||
b31c50a7 SP |
419 | status = be_mbox_notify_wait(adapter); |
420 | if (!status) { | |
421 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | |
6b7c5b94 | 422 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); |
b31c50a7 | 423 | } |
6b7c5b94 | 424 | |
8788fdc2 | 425 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
426 | return status; |
427 | } | |
428 | ||
b31c50a7 | 429 | /* Uses synchronous MCCQ */ |
8788fdc2 | 430 | int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
431 | u32 if_id, u32 *pmac_id) |
432 | { | |
b31c50a7 SP |
433 | struct be_mcc_wrb *wrb; |
434 | struct be_cmd_req_pmac_add *req; | |
6b7c5b94 SP |
435 | int status; |
436 | ||
b31c50a7 SP |
437 | spin_lock_bh(&adapter->mcc_lock); |
438 | ||
439 | wrb = wrb_from_mccq(adapter); | |
440 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
441 | |
442 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
443 | ||
444 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
445 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); | |
446 | ||
447 | req->if_id = cpu_to_le32(if_id); | |
448 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | |
449 | ||
b31c50a7 | 450 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
451 | if (!status) { |
452 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | |
453 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
454 | } | |
455 | ||
b31c50a7 | 456 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
457 | return status; |
458 | } | |
459 | ||
b31c50a7 | 460 | /* Uses synchronous MCCQ */ |
8788fdc2 | 461 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id) |
6b7c5b94 | 462 | { |
b31c50a7 SP |
463 | struct be_mcc_wrb *wrb; |
464 | struct be_cmd_req_pmac_del *req; | |
6b7c5b94 SP |
465 | int status; |
466 | ||
b31c50a7 SP |
467 | spin_lock_bh(&adapter->mcc_lock); |
468 | ||
469 | wrb = wrb_from_mccq(adapter); | |
470 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
471 | |
472 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
473 | ||
474 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
475 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); | |
476 | ||
477 | req->if_id = cpu_to_le32(if_id); | |
478 | req->pmac_id = cpu_to_le32(pmac_id); | |
479 | ||
b31c50a7 SP |
480 | status = be_mcc_notify_wait(adapter); |
481 | ||
482 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
483 | |
484 | return status; | |
485 | } | |
486 | ||
b31c50a7 | 487 | /* Uses Mbox */ |
8788fdc2 | 488 | int be_cmd_cq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
489 | struct be_queue_info *cq, struct be_queue_info *eq, |
490 | bool sol_evts, bool no_delay, int coalesce_wm) | |
491 | { | |
b31c50a7 SP |
492 | struct be_mcc_wrb *wrb; |
493 | struct be_cmd_req_cq_create *req; | |
6b7c5b94 | 494 | struct be_dma_mem *q_mem = &cq->dma_mem; |
b31c50a7 | 495 | void *ctxt; |
6b7c5b94 SP |
496 | int status; |
497 | ||
8788fdc2 | 498 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
499 | |
500 | wrb = wrb_from_mbox(adapter); | |
501 | req = embedded_payload(wrb); | |
502 | ctxt = &req->context; | |
6b7c5b94 SP |
503 | |
504 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
505 | ||
506 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
507 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | |
508 | ||
509 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
510 | ||
511 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm); | |
512 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | |
513 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | |
514 | __ilog2_u32(cq->len/256)); | |
515 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | |
516 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | |
517 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | |
518 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | |
5fb379ee | 519 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); |
eec368fb | 520 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter)); |
6b7c5b94 SP |
521 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
522 | ||
523 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
524 | ||
b31c50a7 | 525 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 526 | if (!status) { |
b31c50a7 | 527 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
528 | cq->id = le16_to_cpu(resp->cq_id); |
529 | cq->created = true; | |
530 | } | |
b31c50a7 | 531 | |
8788fdc2 | 532 | spin_unlock(&adapter->mbox_lock); |
5fb379ee SP |
533 | |
534 | return status; | |
535 | } | |
536 | ||
537 | static u32 be_encoded_q_len(int q_len) | |
538 | { | |
539 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
540 | if (len_encoded == 16) | |
541 | len_encoded = 0; | |
542 | return len_encoded; | |
543 | } | |
544 | ||
8788fdc2 | 545 | int be_cmd_mccq_create(struct be_adapter *adapter, |
5fb379ee SP |
546 | struct be_queue_info *mccq, |
547 | struct be_queue_info *cq) | |
548 | { | |
b31c50a7 SP |
549 | struct be_mcc_wrb *wrb; |
550 | struct be_cmd_req_mcc_create *req; | |
5fb379ee | 551 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
b31c50a7 | 552 | void *ctxt; |
5fb379ee SP |
553 | int status; |
554 | ||
8788fdc2 | 555 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
556 | |
557 | wrb = wrb_from_mbox(adapter); | |
558 | req = embedded_payload(wrb); | |
559 | ctxt = &req->context; | |
5fb379ee SP |
560 | |
561 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
562 | ||
563 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
564 | OPCODE_COMMON_MCC_CREATE, sizeof(*req)); | |
565 | ||
566 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
567 | ||
eec368fb | 568 | AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter)); |
5fb379ee SP |
569 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); |
570 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | |
571 | be_encoded_q_len(mccq->len)); | |
572 | AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); | |
573 | ||
574 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
575 | ||
576 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
577 | ||
b31c50a7 | 578 | status = be_mbox_notify_wait(adapter); |
5fb379ee SP |
579 | if (!status) { |
580 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
581 | mccq->id = le16_to_cpu(resp->id); | |
582 | mccq->created = true; | |
583 | } | |
8788fdc2 | 584 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
585 | |
586 | return status; | |
587 | } | |
588 | ||
8788fdc2 | 589 | int be_cmd_txq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
590 | struct be_queue_info *txq, |
591 | struct be_queue_info *cq) | |
592 | { | |
b31c50a7 SP |
593 | struct be_mcc_wrb *wrb; |
594 | struct be_cmd_req_eth_tx_create *req; | |
6b7c5b94 | 595 | struct be_dma_mem *q_mem = &txq->dma_mem; |
b31c50a7 | 596 | void *ctxt; |
6b7c5b94 | 597 | int status; |
6b7c5b94 | 598 | |
8788fdc2 | 599 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
600 | |
601 | wrb = wrb_from_mbox(adapter); | |
602 | req = embedded_payload(wrb); | |
603 | ctxt = &req->context; | |
6b7c5b94 SP |
604 | |
605 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
606 | ||
607 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, | |
608 | sizeof(*req)); | |
609 | ||
610 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
611 | req->ulp_num = BE_ULP1_NUM; | |
612 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | |
613 | ||
b31c50a7 SP |
614 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, |
615 | be_encoded_q_len(txq->len)); | |
6b7c5b94 | 616 | AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt, |
eec368fb | 617 | be_pci_func(adapter)); |
6b7c5b94 SP |
618 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); |
619 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | |
620 | ||
621 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
622 | ||
623 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
624 | ||
b31c50a7 | 625 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
626 | if (!status) { |
627 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | |
628 | txq->id = le16_to_cpu(resp->cid); | |
629 | txq->created = true; | |
630 | } | |
b31c50a7 | 631 | |
8788fdc2 | 632 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
633 | |
634 | return status; | |
635 | } | |
636 | ||
b31c50a7 | 637 | /* Uses mbox */ |
8788fdc2 | 638 | int be_cmd_rxq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
639 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, |
640 | u16 max_frame_size, u32 if_id, u32 rss) | |
641 | { | |
b31c50a7 SP |
642 | struct be_mcc_wrb *wrb; |
643 | struct be_cmd_req_eth_rx_create *req; | |
6b7c5b94 SP |
644 | struct be_dma_mem *q_mem = &rxq->dma_mem; |
645 | int status; | |
646 | ||
8788fdc2 | 647 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
648 | |
649 | wrb = wrb_from_mbox(adapter); | |
650 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
651 | |
652 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
653 | ||
654 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, | |
655 | sizeof(*req)); | |
656 | ||
657 | req->cq_id = cpu_to_le16(cq_id); | |
658 | req->frag_size = fls(frag_size) - 1; | |
659 | req->num_pages = 2; | |
660 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
661 | req->interface_id = cpu_to_le32(if_id); | |
662 | req->max_frame_size = cpu_to_le16(max_frame_size); | |
663 | req->rss_queue = cpu_to_le32(rss); | |
664 | ||
b31c50a7 | 665 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
666 | if (!status) { |
667 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | |
668 | rxq->id = le16_to_cpu(resp->id); | |
669 | rxq->created = true; | |
670 | } | |
b31c50a7 | 671 | |
8788fdc2 | 672 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
673 | |
674 | return status; | |
675 | } | |
676 | ||
b31c50a7 SP |
677 | /* Generic destroyer function for all types of queues |
678 | * Uses Mbox | |
679 | */ | |
8788fdc2 | 680 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
6b7c5b94 SP |
681 | int queue_type) |
682 | { | |
b31c50a7 SP |
683 | struct be_mcc_wrb *wrb; |
684 | struct be_cmd_req_q_destroy *req; | |
6b7c5b94 SP |
685 | u8 subsys = 0, opcode = 0; |
686 | int status; | |
687 | ||
8788fdc2 | 688 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 689 | |
b31c50a7 SP |
690 | wrb = wrb_from_mbox(adapter); |
691 | req = embedded_payload(wrb); | |
692 | ||
6b7c5b94 SP |
693 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
694 | ||
695 | switch (queue_type) { | |
696 | case QTYPE_EQ: | |
697 | subsys = CMD_SUBSYSTEM_COMMON; | |
698 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
699 | break; | |
700 | case QTYPE_CQ: | |
701 | subsys = CMD_SUBSYSTEM_COMMON; | |
702 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
703 | break; | |
704 | case QTYPE_TXQ: | |
705 | subsys = CMD_SUBSYSTEM_ETH; | |
706 | opcode = OPCODE_ETH_TX_DESTROY; | |
707 | break; | |
708 | case QTYPE_RXQ: | |
709 | subsys = CMD_SUBSYSTEM_ETH; | |
710 | opcode = OPCODE_ETH_RX_DESTROY; | |
711 | break; | |
5fb379ee SP |
712 | case QTYPE_MCCQ: |
713 | subsys = CMD_SUBSYSTEM_COMMON; | |
714 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
715 | break; | |
6b7c5b94 | 716 | default: |
5f0b849e | 717 | BUG(); |
6b7c5b94 SP |
718 | } |
719 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); | |
720 | req->id = cpu_to_le16(q->id); | |
721 | ||
b31c50a7 | 722 | status = be_mbox_notify_wait(adapter); |
5f0b849e | 723 | |
8788fdc2 | 724 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
725 | |
726 | return status; | |
727 | } | |
728 | ||
b31c50a7 SP |
729 | /* Create an rx filtering policy configuration on an i/f |
730 | * Uses mbox | |
731 | */ | |
8788fdc2 | 732 | int be_cmd_if_create(struct be_adapter *adapter, u32 flags, u8 *mac, |
6b7c5b94 SP |
733 | bool pmac_invalid, u32 *if_handle, u32 *pmac_id) |
734 | { | |
b31c50a7 SP |
735 | struct be_mcc_wrb *wrb; |
736 | struct be_cmd_req_if_create *req; | |
6b7c5b94 SP |
737 | int status; |
738 | ||
8788fdc2 | 739 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
740 | |
741 | wrb = wrb_from_mbox(adapter); | |
742 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
743 | |
744 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
745 | ||
746 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
747 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); | |
748 | ||
749 | req->capability_flags = cpu_to_le32(flags); | |
750 | req->enable_flags = cpu_to_le32(flags); | |
b31c50a7 | 751 | req->pmac_invalid = pmac_invalid; |
6b7c5b94 SP |
752 | if (!pmac_invalid) |
753 | memcpy(req->mac_addr, mac, ETH_ALEN); | |
754 | ||
b31c50a7 | 755 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
756 | if (!status) { |
757 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | |
758 | *if_handle = le32_to_cpu(resp->interface_id); | |
759 | if (!pmac_invalid) | |
760 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
761 | } | |
762 | ||
8788fdc2 | 763 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
764 | return status; |
765 | } | |
766 | ||
b31c50a7 | 767 | /* Uses mbox */ |
8788fdc2 | 768 | int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id) |
6b7c5b94 | 769 | { |
b31c50a7 SP |
770 | struct be_mcc_wrb *wrb; |
771 | struct be_cmd_req_if_destroy *req; | |
6b7c5b94 SP |
772 | int status; |
773 | ||
8788fdc2 | 774 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
775 | |
776 | wrb = wrb_from_mbox(adapter); | |
777 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
778 | |
779 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
780 | ||
781 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
782 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | |
783 | ||
784 | req->interface_id = cpu_to_le32(interface_id); | |
b31c50a7 SP |
785 | |
786 | status = be_mbox_notify_wait(adapter); | |
6b7c5b94 | 787 | |
8788fdc2 | 788 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
789 | |
790 | return status; | |
791 | } | |
792 | ||
793 | /* Get stats is a non embedded command: the request is not embedded inside | |
794 | * WRB but is a separate dma memory block | |
b31c50a7 | 795 | * Uses asynchronous MCC |
6b7c5b94 | 796 | */ |
8788fdc2 | 797 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) |
6b7c5b94 | 798 | { |
b31c50a7 SP |
799 | struct be_mcc_wrb *wrb; |
800 | struct be_cmd_req_get_stats *req; | |
801 | struct be_sge *sge; | |
6b7c5b94 | 802 | |
b31c50a7 | 803 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 804 | |
b31c50a7 SP |
805 | wrb = wrb_from_mccq(adapter); |
806 | req = nonemb_cmd->va; | |
807 | sge = nonembedded_sgl(wrb); | |
6b7c5b94 SP |
808 | |
809 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1); | |
b31c50a7 | 810 | wrb->tag0 = OPCODE_ETH_GET_STATISTICS; |
6b7c5b94 SP |
811 | |
812 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
813 | OPCODE_ETH_GET_STATISTICS, sizeof(*req)); | |
814 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
815 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
816 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
817 | ||
b31c50a7 | 818 | be_mcc_notify(adapter); |
6b7c5b94 | 819 | |
b31c50a7 SP |
820 | spin_unlock_bh(&adapter->mcc_lock); |
821 | return 0; | |
6b7c5b94 SP |
822 | } |
823 | ||
b31c50a7 | 824 | /* Uses synchronous mcc */ |
8788fdc2 | 825 | int be_cmd_link_status_query(struct be_adapter *adapter, |
a8f447bd | 826 | bool *link_up) |
6b7c5b94 | 827 | { |
b31c50a7 SP |
828 | struct be_mcc_wrb *wrb; |
829 | struct be_cmd_req_link_status *req; | |
6b7c5b94 SP |
830 | int status; |
831 | ||
b31c50a7 SP |
832 | spin_lock_bh(&adapter->mcc_lock); |
833 | ||
834 | wrb = wrb_from_mccq(adapter); | |
835 | req = embedded_payload(wrb); | |
a8f447bd SP |
836 | |
837 | *link_up = false; | |
6b7c5b94 SP |
838 | |
839 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
840 | ||
841 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
842 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | |
843 | ||
b31c50a7 | 844 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
845 | if (!status) { |
846 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | |
a8f447bd SP |
847 | if (resp->mac_speed != PHY_LINK_SPEED_ZERO) |
848 | *link_up = true; | |
6b7c5b94 SP |
849 | } |
850 | ||
b31c50a7 | 851 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
852 | return status; |
853 | } | |
854 | ||
b31c50a7 | 855 | /* Uses Mbox */ |
8788fdc2 | 856 | int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver) |
6b7c5b94 | 857 | { |
b31c50a7 SP |
858 | struct be_mcc_wrb *wrb; |
859 | struct be_cmd_req_get_fw_version *req; | |
6b7c5b94 SP |
860 | int status; |
861 | ||
8788fdc2 | 862 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
863 | |
864 | wrb = wrb_from_mbox(adapter); | |
865 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
866 | |
867 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
868 | ||
869 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
870 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | |
871 | ||
b31c50a7 | 872 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
873 | if (!status) { |
874 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | |
875 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | |
876 | } | |
877 | ||
8788fdc2 | 878 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
879 | return status; |
880 | } | |
881 | ||
b31c50a7 SP |
882 | /* set the EQ delay interval of an EQ to specified value |
883 | * Uses async mcc | |
884 | */ | |
8788fdc2 | 885 | int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) |
6b7c5b94 | 886 | { |
b31c50a7 SP |
887 | struct be_mcc_wrb *wrb; |
888 | struct be_cmd_req_modify_eq_delay *req; | |
6b7c5b94 | 889 | |
b31c50a7 SP |
890 | spin_lock_bh(&adapter->mcc_lock); |
891 | ||
892 | wrb = wrb_from_mccq(adapter); | |
893 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
894 | |
895 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
896 | ||
897 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
898 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); | |
899 | ||
900 | req->num_eq = cpu_to_le32(1); | |
901 | req->delay[0].eq_id = cpu_to_le32(eq_id); | |
902 | req->delay[0].phase = 0; | |
903 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | |
904 | ||
b31c50a7 | 905 | be_mcc_notify(adapter); |
6b7c5b94 | 906 | |
b31c50a7 SP |
907 | spin_unlock_bh(&adapter->mcc_lock); |
908 | return 0; | |
6b7c5b94 SP |
909 | } |
910 | ||
b31c50a7 | 911 | /* Uses sycnhronous mcc */ |
8788fdc2 | 912 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
6b7c5b94 SP |
913 | u32 num, bool untagged, bool promiscuous) |
914 | { | |
b31c50a7 SP |
915 | struct be_mcc_wrb *wrb; |
916 | struct be_cmd_req_vlan_config *req; | |
6b7c5b94 SP |
917 | int status; |
918 | ||
b31c50a7 SP |
919 | spin_lock_bh(&adapter->mcc_lock); |
920 | ||
921 | wrb = wrb_from_mccq(adapter); | |
922 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
923 | |
924 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
925 | ||
926 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
927 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); | |
928 | ||
929 | req->interface_id = if_id; | |
930 | req->promiscuous = promiscuous; | |
931 | req->untagged = untagged; | |
932 | req->num_vlan = num; | |
933 | if (!promiscuous) { | |
934 | memcpy(req->normal_vlan, vtag_array, | |
935 | req->num_vlan * sizeof(vtag_array[0])); | |
936 | } | |
937 | ||
b31c50a7 | 938 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 939 | |
b31c50a7 | 940 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
941 | return status; |
942 | } | |
943 | ||
b31c50a7 SP |
944 | /* Uses MCC for this command as it may be called in BH context |
945 | * Uses synchronous mcc | |
946 | */ | |
8788fdc2 | 947 | int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en) |
6b7c5b94 | 948 | { |
6ac7b687 SP |
949 | struct be_mcc_wrb *wrb; |
950 | struct be_cmd_req_promiscuous_config *req; | |
b31c50a7 | 951 | int status; |
6b7c5b94 | 952 | |
8788fdc2 | 953 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 954 | |
b31c50a7 | 955 | wrb = wrb_from_mccq(adapter); |
6ac7b687 | 956 | req = embedded_payload(wrb); |
6b7c5b94 SP |
957 | |
958 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
959 | ||
960 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
961 | OPCODE_ETH_PROMISCUOUS, sizeof(*req)); | |
962 | ||
963 | if (port_num) | |
964 | req->port1_promiscuous = en; | |
965 | else | |
966 | req->port0_promiscuous = en; | |
967 | ||
b31c50a7 | 968 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 969 | |
8788fdc2 | 970 | spin_unlock_bh(&adapter->mcc_lock); |
b31c50a7 | 971 | return status; |
6b7c5b94 SP |
972 | } |
973 | ||
6ac7b687 | 974 | /* |
b31c50a7 | 975 | * Uses MCC for this command as it may be called in BH context |
6ac7b687 SP |
976 | * (mc == NULL) => multicast promiscous |
977 | */ | |
8788fdc2 | 978 | int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, |
24307eef | 979 | struct dev_mc_list *mc_list, u32 mc_count) |
6b7c5b94 | 980 | { |
6ac7b687 SP |
981 | #define BE_MAX_MC 32 /* set mcast promisc if > 32 */ |
982 | struct be_mcc_wrb *wrb; | |
983 | struct be_cmd_req_mcast_mac_config *req; | |
6b7c5b94 | 984 | |
8788fdc2 | 985 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 986 | |
b31c50a7 | 987 | wrb = wrb_from_mccq(adapter); |
6ac7b687 | 988 | req = embedded_payload(wrb); |
6b7c5b94 SP |
989 | |
990 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
991 | ||
992 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
993 | OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req)); | |
994 | ||
995 | req->interface_id = if_id; | |
24307eef SP |
996 | if (mc_list && mc_count <= BE_MAX_MC) { |
997 | int i; | |
998 | struct dev_mc_list *mc; | |
999 | ||
1000 | req->num_mac = cpu_to_le16(mc_count); | |
1001 | ||
1002 | for (mc = mc_list, i = 0; mc; mc = mc->next, i++) | |
1003 | memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN); | |
1004 | } else { | |
1005 | req->promiscuous = 1; | |
6b7c5b94 SP |
1006 | } |
1007 | ||
8788fdc2 | 1008 | be_mcc_notify_wait(adapter); |
6b7c5b94 | 1009 | |
8788fdc2 | 1010 | spin_unlock_bh(&adapter->mcc_lock); |
6ac7b687 SP |
1011 | |
1012 | return 0; | |
6b7c5b94 SP |
1013 | } |
1014 | ||
b31c50a7 | 1015 | /* Uses synchrounous mcc */ |
8788fdc2 | 1016 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) |
6b7c5b94 | 1017 | { |
b31c50a7 SP |
1018 | struct be_mcc_wrb *wrb; |
1019 | struct be_cmd_req_set_flow_control *req; | |
6b7c5b94 SP |
1020 | int status; |
1021 | ||
b31c50a7 | 1022 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1023 | |
b31c50a7 SP |
1024 | wrb = wrb_from_mccq(adapter); |
1025 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
1026 | |
1027 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1028 | ||
1029 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1030 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); | |
1031 | ||
1032 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | |
1033 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | |
1034 | ||
b31c50a7 | 1035 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1036 | |
b31c50a7 | 1037 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1038 | return status; |
1039 | } | |
1040 | ||
b31c50a7 | 1041 | /* Uses sycn mcc */ |
8788fdc2 | 1042 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) |
6b7c5b94 | 1043 | { |
b31c50a7 SP |
1044 | struct be_mcc_wrb *wrb; |
1045 | struct be_cmd_req_get_flow_control *req; | |
6b7c5b94 SP |
1046 | int status; |
1047 | ||
b31c50a7 | 1048 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1049 | |
b31c50a7 SP |
1050 | wrb = wrb_from_mccq(adapter); |
1051 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
1052 | |
1053 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1054 | ||
1055 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1056 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | |
1057 | ||
b31c50a7 | 1058 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1059 | if (!status) { |
1060 | struct be_cmd_resp_get_flow_control *resp = | |
1061 | embedded_payload(wrb); | |
1062 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | |
1063 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | |
1064 | } | |
1065 | ||
b31c50a7 | 1066 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1067 | return status; |
1068 | } | |
1069 | ||
b31c50a7 | 1070 | /* Uses mbox */ |
8788fdc2 | 1071 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num) |
6b7c5b94 | 1072 | { |
b31c50a7 SP |
1073 | struct be_mcc_wrb *wrb; |
1074 | struct be_cmd_req_query_fw_cfg *req; | |
6b7c5b94 SP |
1075 | int status; |
1076 | ||
8788fdc2 | 1077 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 1078 | |
b31c50a7 SP |
1079 | wrb = wrb_from_mbox(adapter); |
1080 | req = embedded_payload(wrb); | |
6b7c5b94 SP |
1081 | |
1082 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1083 | ||
1084 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1085 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | |
1086 | ||
b31c50a7 | 1087 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1088 | if (!status) { |
1089 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | |
1090 | *port_num = le32_to_cpu(resp->phys_port); | |
1091 | } | |
1092 | ||
8788fdc2 | 1093 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1094 | return status; |
1095 | } | |
14074eab | 1096 | |
b31c50a7 | 1097 | /* Uses mbox */ |
14074eab | 1098 | int be_cmd_reset_function(struct be_adapter *adapter) |
1099 | { | |
b31c50a7 SP |
1100 | struct be_mcc_wrb *wrb; |
1101 | struct be_cmd_req_hdr *req; | |
14074eab | 1102 | int status; |
1103 | ||
1104 | spin_lock(&adapter->mbox_lock); | |
1105 | ||
b31c50a7 SP |
1106 | wrb = wrb_from_mbox(adapter); |
1107 | req = embedded_payload(wrb); | |
14074eab | 1108 | |
1109 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | |
1110 | ||
1111 | be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, | |
1112 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); | |
1113 | ||
b31c50a7 | 1114 | status = be_mbox_notify_wait(adapter); |
14074eab | 1115 | |
1116 | spin_unlock(&adapter->mbox_lock); | |
1117 | return status; | |
1118 | } | |
84517482 AK |
1119 | |
1120 | int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, | |
1121 | u32 flash_type, u32 flash_opcode, u32 buf_size) | |
1122 | { | |
b31c50a7 | 1123 | struct be_mcc_wrb *wrb; |
84517482 | 1124 | struct be_cmd_write_flashrom *req = cmd->va; |
b31c50a7 | 1125 | struct be_sge *sge; |
84517482 AK |
1126 | int status; |
1127 | ||
b31c50a7 SP |
1128 | spin_lock_bh(&adapter->mcc_lock); |
1129 | ||
1130 | wrb = wrb_from_mccq(adapter); | |
1131 | req = embedded_payload(wrb); | |
1132 | sge = nonembedded_sgl(wrb); | |
1133 | ||
84517482 AK |
1134 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1); |
1135 | ||
1136 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1137 | OPCODE_COMMON_WRITE_FLASHROM, cmd->size); | |
1138 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1139 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1140 | sge->len = cpu_to_le32(cmd->size); | |
1141 | ||
1142 | req->params.op_type = cpu_to_le32(flash_type); | |
1143 | req->params.op_code = cpu_to_le32(flash_opcode); | |
1144 | req->params.data_buf_size = cpu_to_le32(buf_size); | |
1145 | ||
b31c50a7 | 1146 | status = be_mcc_notify_wait(adapter); |
84517482 | 1147 | |
b31c50a7 | 1148 | spin_unlock_bh(&adapter->mcc_lock); |
84517482 AK |
1149 | return status; |
1150 | } |