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Commit | Line | Data |
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e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
2fb9d6f5 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/crc32.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/ethtool.h> | |
26 | #include <linux/mii.h> | |
4ae5a3ad | 27 | #include <linux/phy.h> |
e190d6b1 BW |
28 | #include <linux/netdevice.h> |
29 | #include <linux/etherdevice.h> | |
679dce39 | 30 | #include <linux/ethtool.h> |
e190d6b1 | 31 | #include <linux/skbuff.h> |
e190d6b1 | 32 | #include <linux/platform_device.h> |
e190d6b1 BW |
33 | |
34 | #include <asm/dma.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | ||
37 | #include <asm/blackfin.h> | |
38 | #include <asm/cacheflush.h> | |
39 | #include <asm/portmux.h> | |
40 | ||
41 | #include "bfin_mac.h" | |
42 | ||
43 | #define DRV_NAME "bfin_mac" | |
44 | #define DRV_VERSION "1.1" | |
45 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
7ef0a7ee | 46 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" |
e190d6b1 BW |
47 | |
48 | MODULE_AUTHOR(DRV_AUTHOR); | |
49 | MODULE_LICENSE("GPL"); | |
50 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 51 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
52 | |
53 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
54 | # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size) | |
55 | # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr) | |
56 | #else | |
57 | # define bfin_mac_alloc(dma_handle, size) \ | |
58 | dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL) | |
59 | # define bfin_mac_free(dma_handle, ptr) \ | |
60 | dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle) | |
61 | #endif | |
62 | ||
63 | #define PKT_BUF_SZ 1580 | |
64 | ||
65 | #define MAX_TIMEOUT_CNT 500 | |
66 | ||
67 | /* pointers to maintain transmit list */ | |
68 | static struct net_dma_desc_tx *tx_list_head; | |
69 | static struct net_dma_desc_tx *tx_list_tail; | |
70 | static struct net_dma_desc_rx *rx_list_head; | |
71 | static struct net_dma_desc_rx *rx_list_tail; | |
72 | static struct net_dma_desc_rx *current_rx_ptr; | |
73 | static struct net_dma_desc_tx *current_tx_ptr; | |
74 | static struct net_dma_desc_tx *tx_desc; | |
75 | static struct net_dma_desc_rx *rx_desc; | |
76 | ||
7ef0a7ee BW |
77 | #if defined(CONFIG_BFIN_MAC_RMII) |
78 | static u16 pin_req[] = P_RMII0; | |
79 | #else | |
80 | static u16 pin_req[] = P_MII0; | |
81 | #endif | |
82 | ||
83 | static void bfin_mac_disable(void); | |
84 | static void bfin_mac_enable(void); | |
4ae5a3ad | 85 | |
e190d6b1 BW |
86 | static void desc_list_free(void) |
87 | { | |
88 | struct net_dma_desc_rx *r; | |
89 | struct net_dma_desc_tx *t; | |
90 | int i; | |
91 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
92 | dma_addr_t dma_handle = 0; | |
93 | #endif | |
94 | ||
95 | if (tx_desc) { | |
96 | t = tx_list_head; | |
97 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
98 | if (t) { | |
99 | if (t->skb) { | |
100 | dev_kfree_skb(t->skb); | |
101 | t->skb = NULL; | |
102 | } | |
103 | t = t->next; | |
104 | } | |
105 | } | |
106 | bfin_mac_free(dma_handle, tx_desc); | |
107 | } | |
108 | ||
109 | if (rx_desc) { | |
110 | r = rx_list_head; | |
111 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
112 | if (r) { | |
113 | if (r->skb) { | |
114 | dev_kfree_skb(r->skb); | |
115 | r->skb = NULL; | |
116 | } | |
117 | r = r->next; | |
118 | } | |
119 | } | |
120 | bfin_mac_free(dma_handle, rx_desc); | |
121 | } | |
122 | } | |
123 | ||
124 | static int desc_list_init(void) | |
125 | { | |
126 | int i; | |
127 | struct sk_buff *new_skb; | |
128 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
129 | /* | |
130 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
131 | * The real dma handler is the return value of dma_alloc_coherent(). | |
132 | */ | |
133 | dma_addr_t dma_handle; | |
134 | #endif | |
135 | ||
136 | tx_desc = bfin_mac_alloc(&dma_handle, | |
137 | sizeof(struct net_dma_desc_tx) * | |
138 | CONFIG_BFIN_TX_DESC_NUM); | |
139 | if (tx_desc == NULL) | |
140 | goto init_error; | |
141 | ||
142 | rx_desc = bfin_mac_alloc(&dma_handle, | |
143 | sizeof(struct net_dma_desc_rx) * | |
144 | CONFIG_BFIN_RX_DESC_NUM); | |
145 | if (rx_desc == NULL) | |
146 | goto init_error; | |
147 | ||
148 | /* init tx_list */ | |
149 | tx_list_head = tx_list_tail = tx_desc; | |
150 | ||
151 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
152 | struct net_dma_desc_tx *t = tx_desc + i; | |
153 | struct dma_descriptor *a = &(t->desc_a); | |
154 | struct dma_descriptor *b = &(t->desc_b); | |
155 | ||
156 | /* | |
157 | * disable DMA | |
158 | * read from memory WNR = 0 | |
159 | * wordsize is 32 bits | |
160 | * 6 half words is desc size | |
161 | * large desc flow | |
162 | */ | |
163 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
164 | a->start_addr = (unsigned long)t->packet; | |
165 | a->x_count = 0; | |
166 | a->next_dma_desc = b; | |
167 | ||
168 | /* | |
169 | * enabled DMA | |
170 | * write to memory WNR = 1 | |
171 | * wordsize is 32 bits | |
172 | * disable interrupt | |
173 | * 6 half words is desc size | |
174 | * large desc flow | |
175 | */ | |
176 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
177 | b->start_addr = (unsigned long)(&(t->status)); | |
178 | b->x_count = 0; | |
179 | ||
180 | t->skb = NULL; | |
181 | tx_list_tail->desc_b.next_dma_desc = a; | |
182 | tx_list_tail->next = t; | |
183 | tx_list_tail = t; | |
184 | } | |
185 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
186 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
187 | current_tx_ptr = tx_list_head; | |
188 | ||
189 | /* init rx_list */ | |
190 | rx_list_head = rx_list_tail = rx_desc; | |
191 | ||
192 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
193 | struct net_dma_desc_rx *r = rx_desc + i; | |
194 | struct dma_descriptor *a = &(r->desc_a); | |
195 | struct dma_descriptor *b = &(r->desc_b); | |
196 | ||
197 | /* allocate a new skb for next time receive */ | |
198 | new_skb = dev_alloc_skb(PKT_BUF_SZ + 2); | |
199 | if (!new_skb) { | |
200 | printk(KERN_NOTICE DRV_NAME | |
201 | ": init: low on mem - packet dropped\n"); | |
202 | goto init_error; | |
203 | } | |
204 | skb_reserve(new_skb, 2); | |
205 | r->skb = new_skb; | |
206 | ||
207 | /* | |
208 | * enabled DMA | |
209 | * write to memory WNR = 1 | |
210 | * wordsize is 32 bits | |
211 | * disable interrupt | |
212 | * 6 half words is desc size | |
213 | * large desc flow | |
214 | */ | |
215 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
216 | /* since RXDWA is enabled */ | |
217 | a->start_addr = (unsigned long)new_skb->data - 2; | |
218 | a->x_count = 0; | |
219 | a->next_dma_desc = b; | |
220 | ||
221 | /* | |
222 | * enabled DMA | |
223 | * write to memory WNR = 1 | |
224 | * wordsize is 32 bits | |
225 | * enable interrupt | |
226 | * 6 half words is desc size | |
227 | * large desc flow | |
228 | */ | |
229 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
230 | NDSIZE_6 | DMAFLOW_LARGE; | |
231 | b->start_addr = (unsigned long)(&(r->status)); | |
232 | b->x_count = 0; | |
233 | ||
234 | rx_list_tail->desc_b.next_dma_desc = a; | |
235 | rx_list_tail->next = r; | |
236 | rx_list_tail = r; | |
237 | } | |
238 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
239 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
240 | current_rx_ptr = rx_list_head; | |
241 | ||
242 | return 0; | |
243 | ||
244 | init_error: | |
245 | desc_list_free(); | |
246 | printk(KERN_ERR DRV_NAME ": kmalloc failed\n"); | |
247 | return -ENOMEM; | |
248 | } | |
249 | ||
250 | ||
251 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
252 | ||
4ae5a3ad BW |
253 | /* |
254 | * MII operations | |
255 | */ | |
e190d6b1 | 256 | /* Wait until the previous MDC/MDIO transaction has completed */ |
4ae5a3ad | 257 | static void mdio_poll(void) |
e190d6b1 BW |
258 | { |
259 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
260 | ||
261 | /* poll the STABUSY bit */ | |
262 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 263 | udelay(1); |
e190d6b1 BW |
264 | if (timeout_cnt-- < 0) { |
265 | printk(KERN_ERR DRV_NAME | |
266 | ": wait MDC/MDIO transaction to complete timeout\n"); | |
267 | break; | |
268 | } | |
269 | } | |
270 | } | |
271 | ||
272 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
4ae5a3ad | 273 | static int mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 274 | { |
4ae5a3ad BW |
275 | mdio_poll(); |
276 | ||
e190d6b1 | 277 | /* read mode */ |
4ae5a3ad BW |
278 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
279 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 280 | STABUSY); |
e190d6b1 | 281 | |
4ae5a3ad BW |
282 | mdio_poll(); |
283 | ||
284 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
285 | } |
286 | ||
287 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
4ae5a3ad BW |
288 | static int mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
289 | u16 value) | |
e190d6b1 | 290 | { |
4ae5a3ad BW |
291 | mdio_poll(); |
292 | ||
293 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
294 | |
295 | /* write mode */ | |
4ae5a3ad BW |
296 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
297 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
298 | STAOP | |
299 | STABUSY); | |
300 | ||
4ae5a3ad BW |
301 | mdio_poll(); |
302 | ||
303 | return 0; | |
e190d6b1 BW |
304 | } |
305 | ||
4ae5a3ad | 306 | static int mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 307 | { |
4ae5a3ad | 308 | return 0; |
e190d6b1 BW |
309 | } |
310 | ||
7ef0a7ee | 311 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 312 | { |
7ef0a7ee | 313 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
314 | struct phy_device *phydev = lp->phydev; |
315 | unsigned long flags; | |
316 | int new_state = 0; | |
317 | ||
318 | spin_lock_irqsave(&lp->lock, flags); | |
319 | if (phydev->link) { | |
320 | /* Now we make sure that we can be in full duplex mode. | |
321 | * If not, we operate in half-duplex mode. */ | |
322 | if (phydev->duplex != lp->old_duplex) { | |
323 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
324 | new_state = 1; | |
325 | ||
326 | if (phydev->duplex) | |
327 | opmode |= FDMODE; | |
328 | else | |
329 | opmode &= ~(FDMODE); | |
330 | ||
331 | bfin_write_EMAC_OPMODE(opmode); | |
332 | lp->old_duplex = phydev->duplex; | |
333 | } | |
e190d6b1 | 334 | |
4ae5a3ad BW |
335 | if (phydev->speed != lp->old_speed) { |
336 | #if defined(CONFIG_BFIN_MAC_RMII) | |
337 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
4ae5a3ad BW |
338 | switch (phydev->speed) { |
339 | case 10: | |
340 | opmode |= RMII_10; | |
341 | break; | |
342 | case 100: | |
343 | opmode &= ~(RMII_10); | |
344 | break; | |
345 | default: | |
346 | printk(KERN_WARNING | |
347 | "%s: Ack! Speed (%d) is not 10/100!\n", | |
348 | DRV_NAME, phydev->speed); | |
349 | break; | |
350 | } | |
351 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 352 | #endif |
e190d6b1 | 353 | |
4ae5a3ad BW |
354 | new_state = 1; |
355 | lp->old_speed = phydev->speed; | |
356 | } | |
e190d6b1 | 357 | |
4ae5a3ad BW |
358 | if (!lp->old_link) { |
359 | new_state = 1; | |
360 | lp->old_link = 1; | |
361 | netif_schedule(dev); | |
362 | } | |
363 | } else if (lp->old_link) { | |
364 | new_state = 1; | |
365 | lp->old_link = 0; | |
366 | lp->old_speed = 0; | |
367 | lp->old_duplex = -1; | |
e190d6b1 BW |
368 | } |
369 | ||
4ae5a3ad BW |
370 | if (new_state) { |
371 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
372 | phy_print_status(phydev); | |
373 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 374 | } |
4ae5a3ad BW |
375 | |
376 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
377 | } |
378 | ||
7cc8f381 BW |
379 | /* MDC = 2.5 MHz */ |
380 | #define MDC_CLK 2500000 | |
381 | ||
4ae5a3ad | 382 | static int mii_probe(struct net_device *dev) |
e190d6b1 | 383 | { |
7ef0a7ee | 384 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
385 | struct phy_device *phydev = NULL; |
386 | unsigned short sysctl; | |
387 | int i; | |
7cc8f381 | 388 | u32 sclk, mdc_div; |
e190d6b1 | 389 | |
4ae5a3ad | 390 | /* Enable PHY output early */ |
e190d6b1 BW |
391 | if (!(bfin_read_VR_CTL() & PHYCLKOE)) |
392 | bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE); | |
393 | ||
7cc8f381 BW |
394 | sclk = get_sclk(); |
395 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
396 | ||
4ae5a3ad | 397 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 398 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 399 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 400 | |
4ae5a3ad BW |
401 | /* search for connect PHY device */ |
402 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
403 | struct phy_device *const tmp_phydev = lp->mii_bus.phy_map[i]; | |
e190d6b1 | 404 | |
4ae5a3ad BW |
405 | if (!tmp_phydev) |
406 | continue; /* no PHY here... */ | |
e190d6b1 | 407 | |
4ae5a3ad BW |
408 | phydev = tmp_phydev; |
409 | break; /* found it */ | |
410 | } | |
411 | ||
412 | /* now we are supposed to have a proper phydev, to attach to... */ | |
413 | if (!phydev) { | |
414 | printk(KERN_INFO "%s: Don't found any phy device at all\n", | |
415 | dev->name); | |
416 | return -ENODEV; | |
e190d6b1 BW |
417 | } |
418 | ||
419 | #if defined(CONFIG_BFIN_MAC_RMII) | |
7ef0a7ee | 420 | phydev = phy_connect(dev, phydev->dev.bus_id, &bfin_mac_adjust_link, 0, |
4ae5a3ad BW |
421 | PHY_INTERFACE_MODE_RMII); |
422 | #else | |
7ef0a7ee | 423 | phydev = phy_connect(dev, phydev->dev.bus_id, &bfin_mac_adjust_link, 0, |
4ae5a3ad | 424 | PHY_INTERFACE_MODE_MII); |
e190d6b1 BW |
425 | #endif |
426 | ||
4ae5a3ad BW |
427 | if (IS_ERR(phydev)) { |
428 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
429 | return PTR_ERR(phydev); | |
430 | } | |
431 | ||
432 | /* mask with MAC supported features */ | |
433 | phydev->supported &= (SUPPORTED_10baseT_Half | |
434 | | SUPPORTED_10baseT_Full | |
435 | | SUPPORTED_100baseT_Half | |
436 | | SUPPORTED_100baseT_Full | |
437 | | SUPPORTED_Autoneg | |
438 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
439 | | SUPPORTED_MII | |
440 | | SUPPORTED_TP); | |
441 | ||
442 | phydev->advertising = phydev->supported; | |
443 | ||
444 | lp->old_link = 0; | |
445 | lp->old_speed = 0; | |
446 | lp->old_duplex = -1; | |
447 | lp->phydev = phydev; | |
448 | ||
449 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
7cc8f381 BW |
450 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" |
451 | "@sclk=%dMHz)\n", | |
452 | DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq, | |
453 | MDC_CLK, mdc_div, sclk/1000000); | |
4ae5a3ad BW |
454 | |
455 | return 0; | |
456 | } | |
457 | ||
679dce39 BW |
458 | /* |
459 | * Ethtool support | |
460 | */ | |
461 | ||
462 | static int | |
463 | bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
464 | { | |
465 | struct bfin_mac_local *lp = netdev_priv(dev); | |
466 | ||
467 | if (lp->phydev) | |
468 | return phy_ethtool_gset(lp->phydev, cmd); | |
469 | ||
470 | return -EINVAL; | |
471 | } | |
472 | ||
473 | static int | |
474 | bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
475 | { | |
476 | struct bfin_mac_local *lp = netdev_priv(dev); | |
477 | ||
478 | if (!capable(CAP_NET_ADMIN)) | |
479 | return -EPERM; | |
480 | ||
481 | if (lp->phydev) | |
482 | return phy_ethtool_sset(lp->phydev, cmd); | |
483 | ||
484 | return -EINVAL; | |
485 | } | |
486 | ||
487 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, | |
488 | struct ethtool_drvinfo *info) | |
489 | { | |
490 | strcpy(info->driver, DRV_NAME); | |
491 | strcpy(info->version, DRV_VERSION); | |
492 | strcpy(info->fw_version, "N/A"); | |
493 | strcpy(info->bus_info, dev->dev.bus_id); | |
494 | } | |
495 | ||
496 | static struct ethtool_ops bfin_mac_ethtool_ops = { | |
497 | .get_settings = bfin_mac_ethtool_getsettings, | |
498 | .set_settings = bfin_mac_ethtool_setsettings, | |
499 | .get_link = ethtool_op_get_link, | |
500 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, | |
501 | }; | |
502 | ||
4ae5a3ad BW |
503 | /**************************************************************************/ |
504 | void setup_system_regs(struct net_device *dev) | |
505 | { | |
506 | unsigned short sysctl; | |
507 | ||
508 | /* | |
509 | * Odd word alignment for Receive Frame DMA word | |
510 | * Configure checksum support and rcve frame word alignment | |
511 | */ | |
512 | sysctl = bfin_read_EMAC_SYSCTL(); | |
513 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
514 | sysctl |= RXDWA | RXCKS; | |
515 | #else | |
516 | sysctl |= RXDWA; | |
517 | #endif | |
518 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
519 | |
520 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
521 | ||
522 | /* Initialize the TX DMA channel registers */ | |
523 | bfin_write_DMA2_X_COUNT(0); | |
524 | bfin_write_DMA2_X_MODIFY(4); | |
525 | bfin_write_DMA2_Y_COUNT(0); | |
526 | bfin_write_DMA2_Y_MODIFY(0); | |
527 | ||
528 | /* Initialize the RX DMA channel registers */ | |
529 | bfin_write_DMA1_X_COUNT(0); | |
530 | bfin_write_DMA1_X_MODIFY(4); | |
531 | bfin_write_DMA1_Y_COUNT(0); | |
532 | bfin_write_DMA1_Y_MODIFY(0); | |
533 | } | |
534 | ||
73f83182 | 535 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
536 | { |
537 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
538 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
539 | ||
540 | /* this depends on a little-endian machine */ | |
541 | bfin_write_EMAC_ADDRLO(addr_low); | |
542 | bfin_write_EMAC_ADDRHI(addr_hi); | |
543 | } | |
544 | ||
7ef0a7ee | 545 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
546 | { |
547 | struct sockaddr *addr = p; | |
548 | if (netif_running(dev)) | |
549 | return -EBUSY; | |
550 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
551 | setup_mac_addr(dev->dev_addr); | |
552 | return 0; | |
553 | } | |
554 | ||
e190d6b1 BW |
555 | static void adjust_tx_list(void) |
556 | { | |
557 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
558 | ||
559 | if (tx_list_head->status.status_word != 0 | |
560 | && current_tx_ptr != tx_list_head) { | |
561 | goto adjust_head; /* released something, just return; */ | |
562 | } | |
563 | ||
564 | /* | |
565 | * if nothing released, check wait condition | |
566 | * current's next can not be the head, | |
567 | * otherwise the dma will not stop as we want | |
568 | */ | |
569 | if (current_tx_ptr->next->next == tx_list_head) { | |
570 | while (tx_list_head->status.status_word == 0) { | |
6db9e461 | 571 | mdelay(1); |
e190d6b1 BW |
572 | if (tx_list_head->status.status_word != 0 |
573 | || !(bfin_read_DMA2_IRQ_STATUS() & 0x08)) { | |
574 | goto adjust_head; | |
575 | } | |
576 | if (timeout_cnt-- < 0) { | |
577 | printk(KERN_ERR DRV_NAME | |
578 | ": wait for adjust tx list head timeout\n"); | |
579 | break; | |
580 | } | |
581 | } | |
582 | if (tx_list_head->status.status_word != 0) { | |
583 | goto adjust_head; | |
584 | } | |
585 | } | |
586 | ||
587 | return; | |
588 | ||
589 | adjust_head: | |
590 | do { | |
591 | tx_list_head->desc_a.config &= ~DMAEN; | |
592 | tx_list_head->status.status_word = 0; | |
593 | if (tx_list_head->skb) { | |
594 | dev_kfree_skb(tx_list_head->skb); | |
595 | tx_list_head->skb = NULL; | |
596 | } else { | |
597 | printk(KERN_ERR DRV_NAME | |
598 | ": no sk_buff in a transmitted frame!\n"); | |
599 | } | |
600 | tx_list_head = tx_list_head->next; | |
601 | } while (tx_list_head->status.status_word != 0 | |
602 | && current_tx_ptr != tx_list_head); | |
603 | return; | |
604 | ||
605 | } | |
606 | ||
7ef0a7ee | 607 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
608 | struct net_device *dev) |
609 | { | |
e190d6b1 BW |
610 | unsigned int data; |
611 | ||
612 | current_tx_ptr->skb = skb; | |
613 | ||
614 | /* | |
615 | * Is skb->data always 16-bit aligned? | |
616 | * Do we need to memcpy((char *)(tail->packet + 2), skb->data, len)? | |
617 | */ | |
618 | if ((((unsigned int)(skb->data)) & 0x02) == 2) { | |
619 | /* move skb->data to current_tx_ptr payload */ | |
620 | data = (unsigned int)(skb->data) - 2; | |
621 | *((unsigned short *)data) = (unsigned short)(skb->len); | |
622 | current_tx_ptr->desc_a.start_addr = (unsigned long)data; | |
623 | /* this is important! */ | |
624 | blackfin_dcache_flush_range(data, (data + (skb->len)) + 2); | |
625 | ||
626 | } else { | |
627 | *((unsigned short *)(current_tx_ptr->packet)) = | |
628 | (unsigned short)(skb->len); | |
629 | memcpy((char *)(current_tx_ptr->packet + 2), skb->data, | |
630 | (skb->len)); | |
631 | current_tx_ptr->desc_a.start_addr = | |
632 | (unsigned long)current_tx_ptr->packet; | |
633 | if (current_tx_ptr->status.status_word != 0) | |
634 | current_tx_ptr->status.status_word = 0; | |
635 | blackfin_dcache_flush_range((unsigned int)current_tx_ptr-> | |
636 | packet, | |
637 | (unsigned int)(current_tx_ptr-> | |
638 | packet + skb->len) + | |
639 | 2); | |
640 | } | |
641 | ||
642 | /* enable this packet's dma */ | |
643 | current_tx_ptr->desc_a.config |= DMAEN; | |
644 | ||
645 | /* tx dma is running, just return */ | |
646 | if (bfin_read_DMA2_IRQ_STATUS() & 0x08) | |
647 | goto out; | |
648 | ||
649 | /* tx dma is not running */ | |
650 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
651 | /* dma enabled, read from memory, size is 6 */ | |
652 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
653 | /* Turn on the EMAC tx */ | |
654 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
655 | ||
656 | out: | |
657 | adjust_tx_list(); | |
658 | current_tx_ptr = current_tx_ptr->next; | |
659 | dev->trans_start = jiffies; | |
09f75cd7 JG |
660 | dev->stats.tx_packets++; |
661 | dev->stats.tx_bytes += (skb->len); | |
e190d6b1 BW |
662 | return 0; |
663 | } | |
664 | ||
7ef0a7ee | 665 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
666 | { |
667 | struct sk_buff *skb, *new_skb; | |
e190d6b1 BW |
668 | unsigned short len; |
669 | ||
670 | /* allocate a new skb for next time receive */ | |
671 | skb = current_rx_ptr->skb; | |
672 | new_skb = dev_alloc_skb(PKT_BUF_SZ + 2); | |
673 | if (!new_skb) { | |
674 | printk(KERN_NOTICE DRV_NAME | |
675 | ": rx: low on mem - packet dropped\n"); | |
09f75cd7 | 676 | dev->stats.rx_dropped++; |
e190d6b1 BW |
677 | goto out; |
678 | } | |
679 | /* reserve 2 bytes for RXDWA padding */ | |
680 | skb_reserve(new_skb, 2); | |
681 | current_rx_ptr->skb = new_skb; | |
682 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
683 | ||
6e01d1a4 AD |
684 | /* Invidate the data cache of skb->data range when it is write back |
685 | * cache. It will prevent overwritting the new data from DMA | |
686 | */ | |
687 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
688 | (unsigned long)new_skb->end); | |
689 | ||
e190d6b1 BW |
690 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
691 | skb_put(skb, len); | |
692 | blackfin_dcache_invalidate_range((unsigned long)skb->head, | |
693 | (unsigned long)skb->tail); | |
694 | ||
695 | dev->last_rx = jiffies; | |
696 | skb->dev = dev; | |
697 | skb->protocol = eth_type_trans(skb, dev); | |
698 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
699 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
00ff49a9 | 700 | skb->ip_summed = CHECKSUM_COMPLETE; |
e190d6b1 BW |
701 | #endif |
702 | ||
703 | netif_rx(skb); | |
09f75cd7 JG |
704 | dev->stats.rx_packets++; |
705 | dev->stats.rx_bytes += len; | |
e190d6b1 BW |
706 | current_rx_ptr->status.status_word = 0x00000000; |
707 | current_rx_ptr = current_rx_ptr->next; | |
708 | ||
709 | out: | |
710 | return; | |
711 | } | |
712 | ||
713 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 714 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
715 | { |
716 | struct net_device *dev = dev_id; | |
717 | int number = 0; | |
718 | ||
719 | get_one_packet: | |
720 | if (current_rx_ptr->status.status_word == 0) { | |
721 | /* no more new packet received */ | |
722 | if (number == 0) { | |
723 | if (current_rx_ptr->next->status.status_word != 0) { | |
724 | current_rx_ptr = current_rx_ptr->next; | |
725 | goto real_rx; | |
726 | } | |
727 | } | |
728 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
729 | DMA_DONE | DMA_ERR); | |
730 | return IRQ_HANDLED; | |
731 | } | |
732 | ||
733 | real_rx: | |
7ef0a7ee | 734 | bfin_mac_rx(dev); |
e190d6b1 BW |
735 | number++; |
736 | goto get_one_packet; | |
737 | } | |
738 | ||
739 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 740 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 BW |
741 | { |
742 | disable_irq(IRQ_MAC_RX); | |
7ef0a7ee | 743 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
e190d6b1 BW |
744 | enable_irq(IRQ_MAC_RX); |
745 | } | |
746 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
747 | ||
7ef0a7ee | 748 | static void bfin_mac_disable(void) |
e190d6b1 BW |
749 | { |
750 | unsigned int opmode; | |
751 | ||
752 | opmode = bfin_read_EMAC_OPMODE(); | |
753 | opmode &= (~RE); | |
754 | opmode &= (~TE); | |
755 | /* Turn off the EMAC */ | |
756 | bfin_write_EMAC_OPMODE(opmode); | |
757 | } | |
758 | ||
759 | /* | |
760 | * Enable Interrupts, Receive, and Transmit | |
761 | */ | |
7ef0a7ee | 762 | static void bfin_mac_enable(void) |
e190d6b1 BW |
763 | { |
764 | u32 opmode; | |
765 | ||
4ae5a3ad | 766 | pr_debug("%s: %s\n", DRV_NAME, __FUNCTION__); |
e190d6b1 BW |
767 | |
768 | /* Set RX DMA */ | |
769 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
770 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
771 | ||
772 | /* Wait MII done */ | |
4ae5a3ad | 773 | mdio_poll(); |
e190d6b1 BW |
774 | |
775 | /* We enable only RX here */ | |
776 | /* ASTP : Enable Automatic Pad Stripping | |
777 | PR : Promiscuous Mode for test | |
778 | PSF : Receive frames with total length less than 64 bytes. | |
779 | FDMODE : Full Duplex Mode | |
780 | LB : Internal Loopback for test | |
781 | RE : Receiver Enable */ | |
782 | opmode = bfin_read_EMAC_OPMODE(); | |
783 | if (opmode & FDMODE) | |
784 | opmode |= PSF; | |
785 | else | |
786 | opmode |= DRO | DC | PSF; | |
787 | opmode |= RE; | |
788 | ||
789 | #if defined(CONFIG_BFIN_MAC_RMII) | |
790 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
6893ff1c | 791 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2 |
e190d6b1 BW |
792 | opmode |= TE; |
793 | #endif | |
794 | #endif | |
795 | /* Turn on the EMAC rx */ | |
796 | bfin_write_EMAC_OPMODE(opmode); | |
e190d6b1 BW |
797 | } |
798 | ||
799 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 800 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 BW |
801 | { |
802 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); | |
803 | ||
7ef0a7ee | 804 | bfin_mac_disable(); |
e190d6b1 BW |
805 | |
806 | /* reset tx queue */ | |
807 | tx_list_tail = tx_list_head->next; | |
808 | ||
7ef0a7ee | 809 | bfin_mac_enable(); |
e190d6b1 BW |
810 | |
811 | /* We can accept TX packets again */ | |
812 | dev->trans_start = jiffies; | |
813 | netif_wake_queue(dev); | |
814 | } | |
815 | ||
7ef0a7ee | 816 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
817 | { |
818 | u32 emac_hashhi, emac_hashlo; | |
819 | struct dev_mc_list *dmi = dev->mc_list; | |
820 | char *addrs; | |
821 | int i; | |
822 | u32 crc; | |
823 | ||
824 | emac_hashhi = emac_hashlo = 0; | |
825 | ||
826 | for (i = 0; i < dev->mc_count; i++) { | |
827 | addrs = dmi->dmi_addr; | |
828 | dmi = dmi->next; | |
829 | ||
830 | /* skip non-multicast addresses */ | |
831 | if (!(*addrs & 1)) | |
832 | continue; | |
833 | ||
834 | crc = ether_crc(ETH_ALEN, addrs); | |
835 | crc >>= 26; | |
836 | ||
837 | if (crc & 0x20) | |
838 | emac_hashhi |= 1 << (crc & 0x1f); | |
839 | else | |
840 | emac_hashlo |= 1 << (crc & 0x1f); | |
841 | } | |
842 | ||
843 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
844 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
845 | ||
846 | return; | |
847 | } | |
848 | ||
e190d6b1 BW |
849 | /* |
850 | * This routine will, depending on the values passed to it, | |
851 | * either make it accept multicast packets, go into | |
852 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
853 | * a select set of multicast packets | |
854 | */ | |
7ef0a7ee | 855 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
856 | { |
857 | u32 sysctl; | |
858 | ||
859 | if (dev->flags & IFF_PROMISC) { | |
860 | printk(KERN_INFO "%s: set to promisc mode\n", dev->name); | |
861 | sysctl = bfin_read_EMAC_OPMODE(); | |
862 | sysctl |= RAF; | |
863 | bfin_write_EMAC_OPMODE(sysctl); | |
775919bc | 864 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
865 | /* accept all multicast */ |
866 | sysctl = bfin_read_EMAC_OPMODE(); | |
867 | sysctl |= PAM; | |
868 | bfin_write_EMAC_OPMODE(sysctl); | |
775919bc AW |
869 | } else if (dev->mc_count) { |
870 | /* set up multicast hash table */ | |
871 | sysctl = bfin_read_EMAC_OPMODE(); | |
872 | sysctl |= HM; | |
873 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 874 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
875 | } else { |
876 | /* clear promisc or multicast mode */ | |
877 | sysctl = bfin_read_EMAC_OPMODE(); | |
878 | sysctl &= ~(RAF | PAM); | |
879 | bfin_write_EMAC_OPMODE(sysctl); | |
880 | } | |
881 | } | |
882 | ||
883 | /* | |
884 | * this puts the device in an inactive state | |
885 | */ | |
7ef0a7ee | 886 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
887 | { |
888 | /* Turn off the EMAC */ | |
889 | bfin_write_EMAC_OPMODE(0x00000000); | |
890 | /* Turn off the EMAC RX DMA */ | |
891 | bfin_write_DMA1_CONFIG(0x0000); | |
892 | bfin_write_DMA2_CONFIG(0x0000); | |
893 | } | |
894 | ||
895 | /* | |
896 | * Open and Initialize the interface | |
897 | * | |
898 | * Set up everything, reset the card, etc.. | |
899 | */ | |
7ef0a7ee | 900 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 901 | { |
7ef0a7ee | 902 | struct bfin_mac_local *lp = netdev_priv(dev); |
4af4b840 | 903 | int retval; |
e190d6b1 BW |
904 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); |
905 | ||
906 | /* | |
907 | * Check that the address is valid. If its not, refuse | |
908 | * to bring the device up. The user must specify an | |
909 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
910 | */ | |
911 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
912 | printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n"); | |
913 | return -EINVAL; | |
914 | } | |
915 | ||
916 | /* initial rx and tx list */ | |
4af4b840 MH |
917 | retval = desc_list_init(); |
918 | ||
919 | if (retval) | |
920 | return retval; | |
e190d6b1 | 921 | |
4ae5a3ad | 922 | phy_start(lp->phydev); |
136492b2 | 923 | phy_write(lp->phydev, MII_BMCR, BMCR_RESET); |
e190d6b1 | 924 | setup_system_regs(dev); |
7ef0a7ee BW |
925 | bfin_mac_disable(); |
926 | bfin_mac_enable(); | |
e190d6b1 BW |
927 | pr_debug("hardware init finished\n"); |
928 | netif_start_queue(dev); | |
929 | netif_carrier_on(dev); | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | /* | |
935 | * | |
936 | * this makes the board clean up everything that it can | |
937 | * and not talk to the outside world. Caused by | |
938 | * an 'ifconfig ethX down' | |
939 | */ | |
7ef0a7ee | 940 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 941 | { |
7ef0a7ee | 942 | struct bfin_mac_local *lp = netdev_priv(dev); |
e190d6b1 BW |
943 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); |
944 | ||
945 | netif_stop_queue(dev); | |
946 | netif_carrier_off(dev); | |
947 | ||
4ae5a3ad | 948 | phy_stop(lp->phydev); |
136492b2 | 949 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 950 | |
e190d6b1 | 951 | /* clear everything */ |
7ef0a7ee | 952 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
953 | |
954 | /* free the rx/tx buffers */ | |
955 | desc_list_free(); | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
7ef0a7ee | 960 | static int __init bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 961 | { |
7ef0a7ee BW |
962 | struct net_device *ndev; |
963 | struct bfin_mac_local *lp; | |
964 | int rc, i; | |
965 | ||
966 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
967 | if (!ndev) { | |
968 | dev_err(&pdev->dev, "Cannot allocate net device!\n"); | |
969 | return -ENOMEM; | |
970 | } | |
971 | ||
972 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
973 | platform_set_drvdata(pdev, ndev); | |
974 | lp = netdev_priv(ndev); | |
e190d6b1 BW |
975 | |
976 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
977 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
978 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
979 | |
980 | /* probe mac */ | |
981 | /*todo: how to proble? which is revision_register */ | |
982 | bfin_write_EMAC_ADDRLO(0x12345678); | |
983 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
984 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
985 | rc = -ENODEV; | |
986 | goto out_err_probe_mac; | |
e190d6b1 BW |
987 | } |
988 | ||
989 | /* set the GPIO pins to Ethernet mode */ | |
7ef0a7ee BW |
990 | rc = peripheral_request_list(pin_req, DRV_NAME); |
991 | if (rc) { | |
992 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
993 | rc = -EFAULT; | |
994 | goto out_err_setup_pin_mux; | |
e190d6b1 BW |
995 | } |
996 | ||
7ef0a7ee BW |
997 | /* |
998 | * Is it valid? (Did bootloader initialize it?) | |
999 | * Grab the MAC from the board somehow | |
1000 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
1001 | */ | |
1002 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1003 | bfin_get_ether_addr(ndev->dev_addr); | |
1004 | ||
e190d6b1 | 1005 | /* If still not valid, get a random one */ |
7ef0a7ee BW |
1006 | if (!is_valid_ether_addr(ndev->dev_addr)) |
1007 | random_ether_addr(ndev->dev_addr); | |
e190d6b1 | 1008 | |
7ef0a7ee | 1009 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 1010 | |
4ae5a3ad | 1011 | /* MDIO bus initial */ |
7ef0a7ee | 1012 | lp->mii_bus.priv = ndev; |
4ae5a3ad BW |
1013 | lp->mii_bus.read = mdiobus_read; |
1014 | lp->mii_bus.write = mdiobus_write; | |
1015 | lp->mii_bus.reset = mdiobus_reset; | |
1016 | lp->mii_bus.name = "bfin_mac_mdio"; | |
9d9326d3 | 1017 | snprintf(lp->mii_bus.id, MII_BUS_ID_SIZE, "0"); |
4ae5a3ad BW |
1018 | lp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
1019 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1020 | lp->mii_bus.irq[i] = PHY_POLL; | |
1021 | ||
7ef0a7ee BW |
1022 | rc = mdiobus_register(&lp->mii_bus); |
1023 | if (rc) { | |
1024 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1025 | goto out_err_mdiobus_register; | |
1026 | } | |
4ae5a3ad | 1027 | |
7ef0a7ee BW |
1028 | rc = mii_probe(ndev); |
1029 | if (rc) { | |
1030 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1031 | goto out_err_mii_probe; | |
1032 | } | |
4ae5a3ad | 1033 | |
e190d6b1 | 1034 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
1035 | ether_setup(ndev); |
1036 | ||
1037 | ndev->open = bfin_mac_open; | |
1038 | ndev->stop = bfin_mac_close; | |
1039 | ndev->hard_start_xmit = bfin_mac_hard_start_xmit; | |
1040 | ndev->set_mac_address = bfin_mac_set_mac_address; | |
1041 | ndev->tx_timeout = bfin_mac_timeout; | |
1042 | ndev->set_multicast_list = bfin_mac_set_multicast_list; | |
e190d6b1 | 1043 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7ef0a7ee | 1044 | ndev->poll_controller = bfin_mac_poll; |
e190d6b1 | 1045 | #endif |
679dce39 | 1046 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
e190d6b1 | 1047 | |
e190d6b1 BW |
1048 | spin_lock_init(&lp->lock); |
1049 | ||
1050 | /* now, enable interrupts */ | |
1051 | /* register irq handler */ | |
7ef0a7ee BW |
1052 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
1053 | IRQF_DISABLED | IRQF_SHARED, "EMAC_RX", ndev); | |
1054 | if (rc) { | |
1055 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1056 | rc = -EBUSY; | |
1057 | goto out_err_request_irq; | |
e190d6b1 BW |
1058 | } |
1059 | ||
7ef0a7ee BW |
1060 | rc = register_netdev(ndev); |
1061 | if (rc) { | |
1062 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1063 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1064 | } |
1065 | ||
7ef0a7ee BW |
1066 | /* now, print out the card info, in a short format.. */ |
1067 | dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); | |
e190d6b1 | 1068 | |
7ef0a7ee | 1069 | return 0; |
e190d6b1 | 1070 | |
7ef0a7ee BW |
1071 | out_err_reg_ndev: |
1072 | free_irq(IRQ_MAC_RX, ndev); | |
1073 | out_err_request_irq: | |
1074 | out_err_mii_probe: | |
1075 | mdiobus_unregister(&lp->mii_bus); | |
1076 | out_err_mdiobus_register: | |
1077 | peripheral_free_list(pin_req); | |
1078 | out_err_setup_pin_mux: | |
1079 | out_err_probe_mac: | |
1080 | platform_set_drvdata(pdev, NULL); | |
1081 | free_netdev(ndev); | |
e190d6b1 | 1082 | |
7ef0a7ee | 1083 | return rc; |
e190d6b1 BW |
1084 | } |
1085 | ||
1086 | static int bfin_mac_remove(struct platform_device *pdev) | |
1087 | { | |
1088 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1089 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 BW |
1090 | |
1091 | platform_set_drvdata(pdev, NULL); | |
1092 | ||
7ef0a7ee BW |
1093 | mdiobus_unregister(&lp->mii_bus); |
1094 | ||
e190d6b1 BW |
1095 | unregister_netdev(ndev); |
1096 | ||
1097 | free_irq(IRQ_MAC_RX, ndev); | |
1098 | ||
1099 | free_netdev(ndev); | |
1100 | ||
7ef0a7ee | 1101 | peripheral_free_list(pin_req); |
e190d6b1 BW |
1102 | |
1103 | return 0; | |
1104 | } | |
1105 | ||
496a34c2 BW |
1106 | #ifdef CONFIG_PM |
1107 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1108 | { |
496a34c2 BW |
1109 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1110 | ||
1111 | if (netif_running(net_dev)) | |
7ef0a7ee | 1112 | bfin_mac_close(net_dev); |
496a34c2 | 1113 | |
e190d6b1 BW |
1114 | return 0; |
1115 | } | |
1116 | ||
1117 | static int bfin_mac_resume(struct platform_device *pdev) | |
1118 | { | |
496a34c2 BW |
1119 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1120 | ||
1121 | if (netif_running(net_dev)) | |
7ef0a7ee | 1122 | bfin_mac_open(net_dev); |
496a34c2 | 1123 | |
e190d6b1 BW |
1124 | return 0; |
1125 | } | |
496a34c2 BW |
1126 | #else |
1127 | #define bfin_mac_suspend NULL | |
1128 | #define bfin_mac_resume NULL | |
1129 | #endif /* CONFIG_PM */ | |
e190d6b1 BW |
1130 | |
1131 | static struct platform_driver bfin_mac_driver = { | |
1132 | .probe = bfin_mac_probe, | |
1133 | .remove = bfin_mac_remove, | |
1134 | .resume = bfin_mac_resume, | |
1135 | .suspend = bfin_mac_suspend, | |
1136 | .driver = { | |
72abb461 KS |
1137 | .name = DRV_NAME, |
1138 | .owner = THIS_MODULE, | |
1139 | }, | |
e190d6b1 BW |
1140 | }; |
1141 | ||
1142 | static int __init bfin_mac_init(void) | |
1143 | { | |
1144 | return platform_driver_register(&bfin_mac_driver); | |
1145 | } | |
1146 | ||
1147 | module_init(bfin_mac_init); | |
1148 | ||
1149 | static void __exit bfin_mac_cleanup(void) | |
1150 | { | |
1151 | platform_driver_unregister(&bfin_mac_driver); | |
1152 | } | |
1153 | ||
1154 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1155 |