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8b230ed8 RM |
1 | /* |
2 | * Linux network driver for Brocade Converged Network Adapter. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
6 | * published by the Free Software Foundation | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
13 | /* | |
14 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. | |
15 | * All rights reserved | |
16 | * www.brocade.com | |
17 | * | |
18 | * File for interrupt macros and functions | |
19 | */ | |
20 | ||
21 | #ifndef __BNA_HW_H__ | |
22 | #define __BNA_HW_H__ | |
23 | ||
24 | #include "bfi_ctreg.h" | |
25 | ||
26 | /** | |
27 | * | |
28 | * SW imposed limits | |
29 | * | |
30 | */ | |
31 | ||
32 | #ifndef BNA_BIOS_BUILD | |
33 | ||
34 | #define BFI_MAX_TXQ 64 | |
35 | #define BFI_MAX_RXQ 64 | |
36 | #define BFI_MAX_RXF 64 | |
37 | #define BFI_MAX_IB 128 | |
38 | #define BFI_MAX_RIT_SIZE 256 | |
39 | #define BFI_RSS_RIT_SIZE 64 | |
40 | #define BFI_NONRSS_RIT_SIZE 1 | |
41 | #define BFI_MAX_UCMAC 256 | |
42 | #define BFI_MAX_MCMAC 512 | |
43 | #define BFI_IBIDX_SIZE 4 | |
44 | #define BFI_MAX_VLAN 4095 | |
45 | ||
46 | /** | |
47 | * There are 2 free IB index pools: | |
48 | * pool1: 120 segments of 1 index each | |
49 | * pool8: 1 segment of 8 indexes | |
50 | */ | |
51 | #define BFI_IBIDX_POOL1_SIZE 116 | |
52 | #define BFI_IBIDX_POOL1_ENTRY_SIZE 1 | |
53 | #define BFI_IBIDX_POOL2_SIZE 2 | |
54 | #define BFI_IBIDX_POOL2_ENTRY_SIZE 2 | |
55 | #define BFI_IBIDX_POOL8_SIZE 1 | |
56 | #define BFI_IBIDX_POOL8_ENTRY_SIZE 8 | |
57 | #define BFI_IBIDX_TOTAL_POOLS 3 | |
58 | #define BFI_IBIDX_TOTAL_SEGS 119 /* (POOL1 + POOL2 + POOL8)_SIZE */ | |
59 | #define BFI_IBIDX_MAX_SEGSIZE 8 | |
60 | #define init_ibidx_pool(name) \ | |
61 | static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \ | |
62 | { \ | |
63 | { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE }, \ | |
64 | { BFI_IBIDX_POOL2_SIZE, BFI_IBIDX_POOL2_ENTRY_SIZE }, \ | |
65 | { BFI_IBIDX_POOL8_SIZE, BFI_IBIDX_POOL8_ENTRY_SIZE } \ | |
66 | } | |
67 | ||
68 | /** | |
69 | * There are 2 free RIT segment pools: | |
70 | * Pool1: 192 segments of 1 RIT entry each | |
71 | * Pool2: 1 segment of 64 RIT entry | |
72 | */ | |
73 | #define BFI_RIT_SEG_POOL1_SIZE 192 | |
74 | #define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1 | |
75 | #define BFI_RIT_SEG_POOLRSS_SIZE 1 | |
76 | #define BFI_RIT_SEG_POOLRSS_ENTRY_SIZE 64 | |
77 | #define BFI_RIT_SEG_TOTAL_POOLS 2 | |
78 | #define BFI_RIT_TOTAL_SEGS 193 /* POOL1_SIZE + POOLRSS_SIZE */ | |
79 | #define init_ritseg_pool(name) \ | |
80 | static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \ | |
81 | { \ | |
82 | { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE }, \ | |
83 | { BFI_RIT_SEG_POOLRSS_SIZE, BFI_RIT_SEG_POOLRSS_ENTRY_SIZE } \ | |
84 | } | |
85 | ||
86 | #else /* BNA_BIOS_BUILD */ | |
87 | ||
88 | #define BFI_MAX_TXQ 1 | |
89 | #define BFI_MAX_RXQ 1 | |
90 | #define BFI_MAX_RXF 1 | |
91 | #define BFI_MAX_IB 2 | |
92 | #define BFI_MAX_RIT_SIZE 2 | |
93 | #define BFI_RSS_RIT_SIZE 64 | |
94 | #define BFI_NONRSS_RIT_SIZE 1 | |
95 | #define BFI_MAX_UCMAC 1 | |
96 | #define BFI_MAX_MCMAC 8 | |
97 | #define BFI_IBIDX_SIZE 4 | |
98 | #define BFI_MAX_VLAN 4095 | |
99 | /* There is one free pool: 2 segments of 1 index each */ | |
100 | #define BFI_IBIDX_POOL1_SIZE 2 | |
101 | #define BFI_IBIDX_POOL1_ENTRY_SIZE 1 | |
102 | #define BFI_IBIDX_TOTAL_POOLS 1 | |
103 | #define BFI_IBIDX_TOTAL_SEGS 2 /* POOL1_SIZE */ | |
104 | #define BFI_IBIDX_MAX_SEGSIZE 1 | |
105 | #define init_ibidx_pool(name) \ | |
106 | static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \ | |
107 | { \ | |
108 | { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE } \ | |
109 | } | |
110 | ||
111 | #define BFI_RIT_SEG_POOL1_SIZE 1 | |
112 | #define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1 | |
113 | #define BFI_RIT_SEG_TOTAL_POOLS 1 | |
114 | #define BFI_RIT_TOTAL_SEGS 1 /* POOL1_SIZE */ | |
115 | #define init_ritseg_pool(name) \ | |
116 | static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \ | |
117 | { \ | |
118 | { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE } \ | |
119 | } | |
120 | ||
121 | #endif /* BNA_BIOS_BUILD */ | |
122 | ||
123 | #define BFI_RSS_HASH_KEY_LEN 10 | |
124 | ||
125 | #define BFI_COALESCING_TIMER_UNIT 5 /* 5us */ | |
126 | #define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */ | |
127 | #define BFI_MAX_INTERPKT_COUNT 0xFF | |
128 | #define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */ | |
129 | #define BFI_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */ | |
130 | #define BFI_TX_INTERPKT_COUNT 32 | |
131 | #define BFI_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */ | |
132 | #define BFI_RX_INTERPKT_COUNT 6 /* Pkt Cnt = 6 */ | |
133 | #define BFI_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */ | |
134 | ||
135 | #define BFI_TXQ_WI_SIZE 64 /* bytes */ | |
136 | #define BFI_RXQ_WI_SIZE 8 /* bytes */ | |
137 | #define BFI_CQ_WI_SIZE 16 /* bytes */ | |
138 | #define BFI_TX_MAX_WRR_QUOTA 0xFFF | |
139 | ||
140 | #define BFI_TX_MAX_VECTORS_PER_WI 4 | |
141 | #define BFI_TX_MAX_VECTORS_PER_PKT 0xFF | |
142 | #define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF | |
143 | #define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF | |
144 | ||
145 | /* Small Q buffer size */ | |
146 | #define BFI_SMALL_RXBUF_SIZE 128 | |
147 | ||
148 | /* Defined separately since BFA_FLASH_DMA_BUF_SZ is in bfa_flash.c */ | |
149 | #define BFI_FLASH_DMA_BUF_SZ 0x010000 /* 64K DMA */ | |
150 | #define BFI_HW_STATS_SIZE 0x4000 /* 16K DMA */ | |
151 | ||
152 | /** | |
153 | * | |
154 | * HW register offsets, macros | |
155 | * | |
156 | */ | |
157 | ||
158 | /* DMA Block Register Host Window Start Address */ | |
159 | #define DMA_BLK_REG_ADDR 0x00013000 | |
160 | ||
161 | /* DMA Block Internal Registers */ | |
162 | #define DMA_CTRL_REG0 (DMA_BLK_REG_ADDR + 0x000) | |
163 | #define DMA_CTRL_REG1 (DMA_BLK_REG_ADDR + 0x004) | |
164 | #define DMA_ERR_INT_STATUS (DMA_BLK_REG_ADDR + 0x008) | |
165 | #define DMA_ERR_INT_ENABLE (DMA_BLK_REG_ADDR + 0x00c) | |
166 | #define DMA_ERR_INT_STATUS_SET (DMA_BLK_REG_ADDR + 0x010) | |
167 | ||
168 | /* APP Block Register Address Offset from BAR0 */ | |
169 | #define APP_BLK_REG_ADDR 0x00014000 | |
170 | ||
171 | /* Host Function Interrupt Mask Registers */ | |
172 | #define HOSTFN0_INT_MASK (APP_BLK_REG_ADDR + 0x004) | |
173 | #define HOSTFN1_INT_MASK (APP_BLK_REG_ADDR + 0x104) | |
174 | #define HOSTFN2_INT_MASK (APP_BLK_REG_ADDR + 0x304) | |
175 | #define HOSTFN3_INT_MASK (APP_BLK_REG_ADDR + 0x404) | |
176 | ||
177 | /** | |
178 | * Host Function PCIe Error Registers | |
179 | * Duplicates "Correctable" & "Uncorrectable" | |
180 | * registers in PCIe Config space. | |
181 | */ | |
182 | #define FN0_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x014) | |
183 | #define FN1_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x114) | |
184 | #define FN2_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x314) | |
185 | #define FN3_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x414) | |
186 | ||
187 | /* Host Function Error Type Status Registers */ | |
188 | #define FN0_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x018) | |
189 | #define FN1_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x118) | |
190 | #define FN2_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x318) | |
191 | #define FN3_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x418) | |
192 | ||
193 | /* Host Function Error Type Mask Registers */ | |
194 | #define FN0_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x01c) | |
195 | #define FN1_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x11c) | |
196 | #define FN2_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x31c) | |
197 | #define FN3_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x41c) | |
198 | ||
199 | /* Catapult Host Semaphore Status Registers (App block) */ | |
200 | #define HOST_SEM_STS0_REG (APP_BLK_REG_ADDR + 0x630) | |
201 | #define HOST_SEM_STS1_REG (APP_BLK_REG_ADDR + 0x634) | |
202 | #define HOST_SEM_STS2_REG (APP_BLK_REG_ADDR + 0x638) | |
203 | #define HOST_SEM_STS3_REG (APP_BLK_REG_ADDR + 0x63c) | |
204 | #define HOST_SEM_STS4_REG (APP_BLK_REG_ADDR + 0x640) | |
205 | #define HOST_SEM_STS5_REG (APP_BLK_REG_ADDR + 0x644) | |
206 | #define HOST_SEM_STS6_REG (APP_BLK_REG_ADDR + 0x648) | |
207 | #define HOST_SEM_STS7_REG (APP_BLK_REG_ADDR + 0x64c) | |
208 | ||
209 | /* PCIe Misc Register */ | |
210 | #define PCIE_MISC_REG (APP_BLK_REG_ADDR + 0x200) | |
211 | ||
212 | /* Temp Sensor Control Registers */ | |
213 | #define TEMPSENSE_CNTL_REG (APP_BLK_REG_ADDR + 0x250) | |
214 | #define TEMPSENSE_STAT_REG (APP_BLK_REG_ADDR + 0x254) | |
215 | ||
216 | /* APP Block local error registers */ | |
217 | #define APP_LOCAL_ERR_STAT (APP_BLK_REG_ADDR + 0x258) | |
218 | #define APP_LOCAL_ERR_MSK (APP_BLK_REG_ADDR + 0x25c) | |
219 | ||
220 | /* PCIe Link Error registers */ | |
221 | #define PCIE_LNK_ERR_STAT (APP_BLK_REG_ADDR + 0x260) | |
222 | #define PCIE_LNK_ERR_MSK (APP_BLK_REG_ADDR + 0x264) | |
223 | ||
224 | /** | |
225 | * FCoE/FIP Ethertype Register | |
226 | * 31:16 -- Chip wide value for FIP type | |
227 | * 15:0 -- Chip wide value for FCoE type | |
228 | */ | |
229 | #define FCOE_FIP_ETH_TYPE (APP_BLK_REG_ADDR + 0x280) | |
230 | ||
231 | /** | |
232 | * Reserved Ethertype Register | |
233 | * 31:16 -- Reserved | |
234 | * 15:0 -- Other ethertype | |
235 | */ | |
236 | #define RESV_ETH_TYPE (APP_BLK_REG_ADDR + 0x284) | |
237 | ||
238 | /** | |
239 | * Host Command Status Registers | |
240 | * Each set consists of 3 registers : | |
241 | * clear, set, cmd | |
242 | * 16 such register sets in all | |
243 | * See catapult_spec.pdf for detailed functionality | |
244 | * Put each type in a single macro accessed by _num ? | |
245 | */ | |
246 | #define HOST_CMDSTS0_CLR_REG (APP_BLK_REG_ADDR + 0x500) | |
247 | #define HOST_CMDSTS0_SET_REG (APP_BLK_REG_ADDR + 0x504) | |
248 | #define HOST_CMDSTS0_REG (APP_BLK_REG_ADDR + 0x508) | |
249 | #define HOST_CMDSTS1_CLR_REG (APP_BLK_REG_ADDR + 0x510) | |
250 | #define HOST_CMDSTS1_SET_REG (APP_BLK_REG_ADDR + 0x514) | |
251 | #define HOST_CMDSTS1_REG (APP_BLK_REG_ADDR + 0x518) | |
252 | #define HOST_CMDSTS2_CLR_REG (APP_BLK_REG_ADDR + 0x520) | |
253 | #define HOST_CMDSTS2_SET_REG (APP_BLK_REG_ADDR + 0x524) | |
254 | #define HOST_CMDSTS2_REG (APP_BLK_REG_ADDR + 0x528) | |
255 | #define HOST_CMDSTS3_CLR_REG (APP_BLK_REG_ADDR + 0x530) | |
256 | #define HOST_CMDSTS3_SET_REG (APP_BLK_REG_ADDR + 0x534) | |
257 | #define HOST_CMDSTS3_REG (APP_BLK_REG_ADDR + 0x538) | |
258 | #define HOST_CMDSTS4_CLR_REG (APP_BLK_REG_ADDR + 0x540) | |
259 | #define HOST_CMDSTS4_SET_REG (APP_BLK_REG_ADDR + 0x544) | |
260 | #define HOST_CMDSTS4_REG (APP_BLK_REG_ADDR + 0x548) | |
261 | #define HOST_CMDSTS5_CLR_REG (APP_BLK_REG_ADDR + 0x550) | |
262 | #define HOST_CMDSTS5_SET_REG (APP_BLK_REG_ADDR + 0x554) | |
263 | #define HOST_CMDSTS5_REG (APP_BLK_REG_ADDR + 0x558) | |
264 | #define HOST_CMDSTS6_CLR_REG (APP_BLK_REG_ADDR + 0x560) | |
265 | #define HOST_CMDSTS6_SET_REG (APP_BLK_REG_ADDR + 0x564) | |
266 | #define HOST_CMDSTS6_REG (APP_BLK_REG_ADDR + 0x568) | |
267 | #define HOST_CMDSTS7_CLR_REG (APP_BLK_REG_ADDR + 0x570) | |
268 | #define HOST_CMDSTS7_SET_REG (APP_BLK_REG_ADDR + 0x574) | |
269 | #define HOST_CMDSTS7_REG (APP_BLK_REG_ADDR + 0x578) | |
270 | #define HOST_CMDSTS8_CLR_REG (APP_BLK_REG_ADDR + 0x580) | |
271 | #define HOST_CMDSTS8_SET_REG (APP_BLK_REG_ADDR + 0x584) | |
272 | #define HOST_CMDSTS8_REG (APP_BLK_REG_ADDR + 0x588) | |
273 | #define HOST_CMDSTS9_CLR_REG (APP_BLK_REG_ADDR + 0x590) | |
274 | #define HOST_CMDSTS9_SET_REG (APP_BLK_REG_ADDR + 0x594) | |
275 | #define HOST_CMDSTS9_REG (APP_BLK_REG_ADDR + 0x598) | |
276 | #define HOST_CMDSTS10_CLR_REG (APP_BLK_REG_ADDR + 0x5A0) | |
277 | #define HOST_CMDSTS10_SET_REG (APP_BLK_REG_ADDR + 0x5A4) | |
278 | #define HOST_CMDSTS10_REG (APP_BLK_REG_ADDR + 0x5A8) | |
279 | #define HOST_CMDSTS11_CLR_REG (APP_BLK_REG_ADDR + 0x5B0) | |
280 | #define HOST_CMDSTS11_SET_REG (APP_BLK_REG_ADDR + 0x5B4) | |
281 | #define HOST_CMDSTS11_REG (APP_BLK_REG_ADDR + 0x5B8) | |
282 | #define HOST_CMDSTS12_CLR_REG (APP_BLK_REG_ADDR + 0x5C0) | |
283 | #define HOST_CMDSTS12_SET_REG (APP_BLK_REG_ADDR + 0x5C4) | |
284 | #define HOST_CMDSTS12_REG (APP_BLK_REG_ADDR + 0x5C8) | |
285 | #define HOST_CMDSTS13_CLR_REG (APP_BLK_REG_ADDR + 0x5D0) | |
286 | #define HOST_CMDSTS13_SET_REG (APP_BLK_REG_ADDR + 0x5D4) | |
287 | #define HOST_CMDSTS13_REG (APP_BLK_REG_ADDR + 0x5D8) | |
288 | #define HOST_CMDSTS14_CLR_REG (APP_BLK_REG_ADDR + 0x5E0) | |
289 | #define HOST_CMDSTS14_SET_REG (APP_BLK_REG_ADDR + 0x5E4) | |
290 | #define HOST_CMDSTS14_REG (APP_BLK_REG_ADDR + 0x5E8) | |
291 | #define HOST_CMDSTS15_CLR_REG (APP_BLK_REG_ADDR + 0x5F0) | |
292 | #define HOST_CMDSTS15_SET_REG (APP_BLK_REG_ADDR + 0x5F4) | |
293 | #define HOST_CMDSTS15_REG (APP_BLK_REG_ADDR + 0x5F8) | |
294 | ||
295 | /** | |
296 | * LPU0 Block Register Address Offset from BAR0 | |
297 | * Range 0x18000 - 0x18033 | |
298 | */ | |
299 | #define LPU0_BLK_REG_ADDR 0x00018000 | |
300 | ||
301 | /** | |
302 | * LPU0 Registers | |
303 | * Should they be directly used from host, | |
304 | * except for diagnostics ? | |
305 | * CTL_REG : Control register | |
306 | * CMD_REG : Triggers exec. of cmd. in | |
307 | * Mailbox memory | |
308 | */ | |
309 | #define LPU0_MBOX_CTL_REG (LPU0_BLK_REG_ADDR + 0x000) | |
310 | #define LPU0_MBOX_CMD_REG (LPU0_BLK_REG_ADDR + 0x004) | |
311 | #define LPU0_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x008) | |
312 | #define LPU1_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x00c) | |
313 | #define LPU0_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x010) | |
314 | #define LPU1_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x014) | |
315 | #define LPU0_ERR_STATUS_REG (LPU0_BLK_REG_ADDR + 0x018) | |
316 | #define LPU0_ERR_SET_REG (LPU0_BLK_REG_ADDR + 0x020) | |
317 | ||
318 | /** | |
319 | * LPU1 Block Register Address Offset from BAR0 | |
320 | * Range 0x18400 - 0x18433 | |
321 | */ | |
322 | #define LPU1_BLK_REG_ADDR 0x00018400 | |
323 | ||
324 | /** | |
325 | * LPU1 Registers | |
326 | * Same as LPU0 registers above | |
327 | */ | |
328 | #define LPU1_MBOX_CTL_REG (LPU1_BLK_REG_ADDR + 0x000) | |
329 | #define LPU1_MBOX_CMD_REG (LPU1_BLK_REG_ADDR + 0x004) | |
330 | #define LPU0_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x008) | |
331 | #define LPU1_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x00c) | |
332 | #define LPU0_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x010) | |
333 | #define LPU1_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x014) | |
334 | #define LPU1_ERR_STATUS_REG (LPU1_BLK_REG_ADDR + 0x018) | |
335 | #define LPU1_ERR_SET_REG (LPU1_BLK_REG_ADDR + 0x020) | |
336 | ||
337 | /** | |
338 | * PSS Block Register Address Offset from BAR0 | |
339 | * Range 0x18800 - 0x188DB | |
340 | */ | |
341 | #define PSS_BLK_REG_ADDR 0x00018800 | |
342 | ||
343 | /** | |
344 | * PSS Registers | |
345 | * For details, see catapult_spec.pdf | |
346 | * ERR_STATUS_REG : Indicates error in PSS module | |
347 | * RAM_ERR_STATUS_REG : Indicates RAM module that detected error | |
348 | */ | |
349 | #define ERR_STATUS_SET (PSS_BLK_REG_ADDR + 0x018) | |
350 | #define PSS_RAM_ERR_STATUS_REG (PSS_BLK_REG_ADDR + 0x01C) | |
351 | ||
352 | /** | |
353 | * PSS Semaphore Lock Registers, total 16 | |
354 | * First read when unlocked returns 0, | |
355 | * and is set to 1, atomically. | |
356 | * Subsequent reads returns 1. | |
357 | * To clear set the value to 0. | |
358 | * Range : 0x20 to 0x5c | |
359 | */ | |
360 | #define PSS_SEM_LOCK_REG(_num) \ | |
361 | (PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2)) | |
362 | ||
363 | /** | |
364 | * PSS Semaphore Status Registers, | |
365 | * corresponding to the lock registers above | |
366 | */ | |
367 | #define PSS_SEM_STATUS_REG(_num) \ | |
368 | (PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2)) | |
369 | ||
370 | /** | |
371 | * Catapult CPQ Registers | |
372 | * Defines for Mailbox Registers | |
373 | * Used to send mailbox commands to firmware from | |
374 | * host. The data part is written to the MBox | |
375 | * memory, registers are used to indicate that | |
376 | * a commnad is resident in memory. | |
377 | * | |
378 | * Note : LPU0<->LPU1 mailboxes are not listed here | |
379 | */ | |
380 | #define CPQ_BLK_REG_ADDR 0x00019000 | |
381 | ||
382 | #define HOSTFN0_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x130) | |
383 | #define HOSTFN0_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x134) | |
384 | #define LPU0_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x138) | |
385 | #define LPU1_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x13C) | |
386 | ||
387 | #define HOSTFN1_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x140) | |
388 | #define HOSTFN1_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x144) | |
389 | #define LPU0_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x148) | |
390 | #define LPU1_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x14C) | |
391 | ||
392 | #define HOSTFN2_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x170) | |
393 | #define HOSTFN2_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x174) | |
394 | #define LPU0_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x178) | |
395 | #define LPU1_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x17C) | |
396 | ||
397 | #define HOSTFN3_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x180) | |
398 | #define HOSTFN3_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x184) | |
399 | #define LPU0_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x188) | |
400 | #define LPU1_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x18C) | |
401 | ||
402 | /* Host Function Force Parity Error Registers */ | |
403 | #define HOSTFN0_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x120) | |
404 | #define HOSTFN1_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x124) | |
405 | #define HOSTFN2_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x128) | |
406 | #define HOSTFN3_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x12C) | |
407 | ||
408 | /* LL Port[0|1] Halt Mask Registers */ | |
409 | #define LL_HALT_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1A0) | |
410 | #define LL_HALT_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1B0) | |
411 | ||
412 | /* LL Port[0|1] Error Mask Registers */ | |
413 | #define LL_ERR_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1D0) | |
414 | #define LL_ERR_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1D4) | |
415 | ||
416 | /* EMC FLI (Flash Controller) Block Register Address Offset from BAR0 */ | |
417 | #define FLI_BLK_REG_ADDR 0x0001D000 | |
418 | ||
419 | /* EMC FLI Registers */ | |
420 | #define FLI_CMD_REG (FLI_BLK_REG_ADDR + 0x000) | |
421 | #define FLI_ADDR_REG (FLI_BLK_REG_ADDR + 0x004) | |
422 | #define FLI_CTL_REG (FLI_BLK_REG_ADDR + 0x008) | |
423 | #define FLI_WRDATA_REG (FLI_BLK_REG_ADDR + 0x00C) | |
424 | #define FLI_RDDATA_REG (FLI_BLK_REG_ADDR + 0x010) | |
425 | #define FLI_DEV_STATUS_REG (FLI_BLK_REG_ADDR + 0x014) | |
426 | #define FLI_SIG_WD_REG (FLI_BLK_REG_ADDR + 0x018) | |
427 | ||
428 | /** | |
429 | * RO register | |
430 | * 31:16 -- Vendor Id | |
431 | * 15:0 -- Device Id | |
432 | */ | |
433 | #define FLI_DEV_VENDOR_REG (FLI_BLK_REG_ADDR + 0x01C) | |
434 | #define FLI_ERR_STATUS_REG (FLI_BLK_REG_ADDR + 0x020) | |
435 | ||
436 | /** | |
437 | * RAD (RxAdm) Block Register Address Offset from BAR0 | |
438 | * RAD0 Range : 0x20000 - 0x203FF | |
439 | * RAD1 Range : 0x20400 - 0x207FF | |
440 | */ | |
441 | #define RAD0_BLK_REG_ADDR 0x00020000 | |
442 | #define RAD1_BLK_REG_ADDR 0x00020400 | |
443 | ||
444 | /* RAD0 Registers */ | |
445 | #define RAD0_CTL_REG (RAD0_BLK_REG_ADDR + 0x000) | |
446 | #define RAD0_PE_PARM_REG (RAD0_BLK_REG_ADDR + 0x004) | |
447 | #define RAD0_BCN_REG (RAD0_BLK_REG_ADDR + 0x008) | |
448 | ||
449 | /* Default function ID register */ | |
450 | #define RAD0_DEFAULT_REG (RAD0_BLK_REG_ADDR + 0x00C) | |
451 | ||
452 | /* Default promiscuous ID register */ | |
453 | #define RAD0_PROMISC_REG (RAD0_BLK_REG_ADDR + 0x010) | |
454 | ||
455 | #define RAD0_BCNQ_REG (RAD0_BLK_REG_ADDR + 0x014) | |
456 | ||
457 | /* | |
458 | * This register selects 1 of 8 PM Q's using | |
459 | * VLAN pri, for non-BCN packets without a VLAN tag | |
460 | */ | |
461 | #define RAD0_DEFAULTQ_REG (RAD0_BLK_REG_ADDR + 0x018) | |
462 | ||
463 | #define RAD0_ERR_STS (RAD0_BLK_REG_ADDR + 0x01C) | |
464 | #define RAD0_SET_ERR_STS (RAD0_BLK_REG_ADDR + 0x020) | |
465 | #define RAD0_ERR_INT_EN (RAD0_BLK_REG_ADDR + 0x024) | |
466 | #define RAD0_FIRST_ERR (RAD0_BLK_REG_ADDR + 0x028) | |
467 | #define RAD0_FORCE_ERR (RAD0_BLK_REG_ADDR + 0x02C) | |
468 | ||
469 | #define RAD0_IF_RCVD (RAD0_BLK_REG_ADDR + 0x030) | |
470 | #define RAD0_IF_RCVD_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x034) | |
471 | #define RAD0_IF_RCVD_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x038) | |
472 | #define RAD0_IF_RCVD_VLAN (RAD0_BLK_REG_ADDR + 0x03C) | |
473 | #define RAD0_IF_RCVD_UCAST (RAD0_BLK_REG_ADDR + 0x040) | |
474 | #define RAD0_IF_RCVD_UCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x044) | |
475 | #define RAD0_IF_RCVD_UCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x048) | |
476 | #define RAD0_IF_RCVD_UCAST_VLAN (RAD0_BLK_REG_ADDR + 0x04C) | |
477 | #define RAD0_IF_RCVD_MCAST (RAD0_BLK_REG_ADDR + 0x050) | |
478 | #define RAD0_IF_RCVD_MCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x054) | |
479 | #define RAD0_IF_RCVD_MCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x058) | |
480 | #define RAD0_IF_RCVD_MCAST_VLAN (RAD0_BLK_REG_ADDR + 0x05C) | |
481 | #define RAD0_IF_RCVD_BCAST (RAD0_BLK_REG_ADDR + 0x060) | |
482 | #define RAD0_IF_RCVD_BCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x064) | |
483 | #define RAD0_IF_RCVD_BCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x068) | |
484 | #define RAD0_IF_RCVD_BCAST_VLAN (RAD0_BLK_REG_ADDR + 0x06C) | |
485 | #define RAD0_DROPPED_FRAMES (RAD0_BLK_REG_ADDR + 0x070) | |
486 | ||
487 | #define RAD0_MAC_MAN_1H (RAD0_BLK_REG_ADDR + 0x080) | |
488 | #define RAD0_MAC_MAN_1L (RAD0_BLK_REG_ADDR + 0x084) | |
489 | #define RAD0_MAC_MAN_2H (RAD0_BLK_REG_ADDR + 0x088) | |
490 | #define RAD0_MAC_MAN_2L (RAD0_BLK_REG_ADDR + 0x08C) | |
491 | #define RAD0_MAC_MAN_3H (RAD0_BLK_REG_ADDR + 0x090) | |
492 | #define RAD0_MAC_MAN_3L (RAD0_BLK_REG_ADDR + 0x094) | |
493 | #define RAD0_MAC_MAN_4H (RAD0_BLK_REG_ADDR + 0x098) | |
494 | #define RAD0_MAC_MAN_4L (RAD0_BLK_REG_ADDR + 0x09C) | |
495 | ||
496 | #define RAD0_LAST4_IP (RAD0_BLK_REG_ADDR + 0x100) | |
497 | ||
498 | /* RAD1 Registers */ | |
499 | #define RAD1_CTL_REG (RAD1_BLK_REG_ADDR + 0x000) | |
500 | #define RAD1_PE_PARM_REG (RAD1_BLK_REG_ADDR + 0x004) | |
501 | #define RAD1_BCN_REG (RAD1_BLK_REG_ADDR + 0x008) | |
502 | ||
503 | /* Default function ID register */ | |
504 | #define RAD1_DEFAULT_REG (RAD1_BLK_REG_ADDR + 0x00C) | |
505 | ||
506 | /* Promiscuous function ID register */ | |
507 | #define RAD1_PROMISC_REG (RAD1_BLK_REG_ADDR + 0x010) | |
508 | ||
509 | #define RAD1_BCNQ_REG (RAD1_BLK_REG_ADDR + 0x014) | |
510 | ||
511 | /* | |
512 | * This register selects 1 of 8 PM Q's using | |
513 | * VLAN pri, for non-BCN packets without a VLAN tag | |
514 | */ | |
515 | #define RAD1_DEFAULTQ_REG (RAD1_BLK_REG_ADDR + 0x018) | |
516 | ||
517 | #define RAD1_ERR_STS (RAD1_BLK_REG_ADDR + 0x01C) | |
518 | #define RAD1_SET_ERR_STS (RAD1_BLK_REG_ADDR + 0x020) | |
519 | #define RAD1_ERR_INT_EN (RAD1_BLK_REG_ADDR + 0x024) | |
520 | ||
521 | /** | |
522 | * TXA Block Register Address Offset from BAR0 | |
523 | * TXA0 Range : 0x21000 - 0x213FF | |
524 | * TXA1 Range : 0x21400 - 0x217FF | |
525 | */ | |
526 | #define TXA0_BLK_REG_ADDR 0x00021000 | |
527 | #define TXA1_BLK_REG_ADDR 0x00021400 | |
528 | ||
529 | /* TXA Registers */ | |
530 | #define TXA0_CTRL_REG (TXA0_BLK_REG_ADDR + 0x000) | |
531 | #define TXA1_CTRL_REG (TXA1_BLK_REG_ADDR + 0x000) | |
532 | ||
533 | /** | |
534 | * TSO Sequence # Registers (RO) | |
535 | * Total 8 (for 8 queues) | |
536 | * Holds the last seq.# for TSO frames | |
537 | * See catapult_spec.pdf for more details | |
538 | */ | |
539 | #define TXA0_TSO_TCP_SEQ_REG(_num) \ | |
540 | (TXA0_BLK_REG_ADDR + 0x020 + ((_num) << 2)) | |
541 | ||
542 | #define TXA1_TSO_TCP_SEQ_REG(_num) \ | |
543 | (TXA1_BLK_REG_ADDR + 0x020 + ((_num) << 2)) | |
544 | ||
545 | /** | |
546 | * TSO IP ID # Registers (RO) | |
547 | * Total 8 (for 8 queues) | |
548 | * Holds the last IP ID for TSO frames | |
549 | * See catapult_spec.pdf for more details | |
550 | */ | |
551 | #define TXA0_TSO_IP_INFO_REG(_num) \ | |
552 | (TXA0_BLK_REG_ADDR + 0x040 + ((_num) << 2)) | |
553 | ||
554 | #define TXA1_TSO_IP_INFO_REG(_num) \ | |
555 | (TXA1_BLK_REG_ADDR + 0x040 + ((_num) << 2)) | |
556 | ||
557 | /** | |
558 | * RXA Block Register Address Offset from BAR0 | |
559 | * RXA0 Range : 0x21800 - 0x21BFF | |
560 | * RXA1 Range : 0x21C00 - 0x21FFF | |
561 | */ | |
562 | #define RXA0_BLK_REG_ADDR 0x00021800 | |
563 | #define RXA1_BLK_REG_ADDR 0x00021C00 | |
564 | ||
565 | /* RXA Registers */ | |
566 | #define RXA0_CTL_REG (RXA0_BLK_REG_ADDR + 0x040) | |
567 | #define RXA1_CTL_REG (RXA1_BLK_REG_ADDR + 0x040) | |
568 | ||
569 | /** | |
570 | * PPLB Block Register Address Offset from BAR0 | |
571 | * PPLB0 Range : 0x22000 - 0x223FF | |
572 | * PPLB1 Range : 0x22400 - 0x227FF | |
573 | */ | |
574 | #define PLB0_BLK_REG_ADDR 0x00022000 | |
575 | #define PLB1_BLK_REG_ADDR 0x00022400 | |
576 | ||
577 | /** | |
578 | * PLB Registers | |
579 | * Holds RL timer used time stamps in RLT tagged frames | |
580 | */ | |
581 | #define PLB0_ECM_TIMER_REG (PLB0_BLK_REG_ADDR + 0x05C) | |
582 | #define PLB1_ECM_TIMER_REG (PLB1_BLK_REG_ADDR + 0x05C) | |
583 | ||
584 | /* Controls the rate-limiter on each of the priority class */ | |
585 | #define PLB0_RL_CTL (PLB0_BLK_REG_ADDR + 0x060) | |
586 | #define PLB1_RL_CTL (PLB1_BLK_REG_ADDR + 0x060) | |
587 | ||
588 | /** | |
589 | * Max byte register, total 8, 0-7 | |
590 | * see catapult_spec.pdf for details | |
591 | */ | |
592 | #define PLB0_RL_MAX_BC(_num) \ | |
593 | (PLB0_BLK_REG_ADDR + 0x064 + ((_num) << 2)) | |
594 | #define PLB1_RL_MAX_BC(_num) \ | |
595 | (PLB1_BLK_REG_ADDR + 0x064 + ((_num) << 2)) | |
596 | ||
597 | /** | |
598 | * RL Time Unit Register for priority 0-7 | |
599 | * 4 bits per priority | |
600 | * (2^rl_unit)*1us is the actual time period | |
601 | */ | |
602 | #define PLB0_RL_TU_PRIO (PLB0_BLK_REG_ADDR + 0x084) | |
603 | #define PLB1_RL_TU_PRIO (PLB1_BLK_REG_ADDR + 0x084) | |
604 | ||
605 | /** | |
606 | * RL byte count register, | |
607 | * bytes transmitted in (rl_unit*1)us time period | |
608 | * 1 per priority, 8 in all, 0-7. | |
609 | */ | |
610 | #define PLB0_RL_BYTE_CNT(_num) \ | |
611 | (PLB0_BLK_REG_ADDR + 0x088 + ((_num) << 2)) | |
612 | #define PLB1_RL_BYTE_CNT(_num) \ | |
613 | (PLB1_BLK_REG_ADDR + 0x088 + ((_num) << 2)) | |
614 | ||
615 | /** | |
616 | * RL Min factor register | |
617 | * 2 bits per priority, | |
618 | * 4 factors possible: 1, 0.5, 0.25, 0 | |
619 | * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1 | |
620 | */ | |
621 | #define PLB0_RL_MIN_REG (PLB0_BLK_REG_ADDR + 0x0A8) | |
622 | #define PLB1_RL_MIN_REG (PLB1_BLK_REG_ADDR + 0x0A8) | |
623 | ||
624 | /** | |
625 | * RL Max factor register | |
626 | * 2 bits per priority, | |
627 | * 4 factors possible: 1, 0.5, 0.25, 0 | |
628 | * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1 | |
629 | */ | |
630 | #define PLB0_RL_MAX_REG (PLB0_BLK_REG_ADDR + 0x0AC) | |
631 | #define PLB1_RL_MAX_REG (PLB1_BLK_REG_ADDR + 0x0AC) | |
632 | ||
633 | /* MAC SERDES Address Paging register */ | |
634 | #define PLB0_EMS_ADD_REG (PLB0_BLK_REG_ADDR + 0xD0) | |
635 | #define PLB1_EMS_ADD_REG (PLB1_BLK_REG_ADDR + 0xD0) | |
636 | ||
637 | /* LL EMS Registers */ | |
638 | #define LL_EMS0_BLK_REG_ADDR 0x00026800 | |
639 | #define LL_EMS1_BLK_REG_ADDR 0x00026C00 | |
640 | ||
641 | /** | |
642 | * BPC Block Register Address Offset from BAR0 | |
643 | * BPC0 Range : 0x23000 - 0x233FF | |
644 | * BPC1 Range : 0x23400 - 0x237FF | |
645 | */ | |
646 | #define BPC0_BLK_REG_ADDR 0x00023000 | |
647 | #define BPC1_BLK_REG_ADDR 0x00023400 | |
648 | ||
649 | /** | |
650 | * PMM Block Register Address Offset from BAR0 | |
651 | * PMM0 Range : 0x23800 - 0x23BFF | |
652 | * PMM1 Range : 0x23C00 - 0x23FFF | |
653 | */ | |
654 | #define PMM0_BLK_REG_ADDR 0x00023800 | |
655 | #define PMM1_BLK_REG_ADDR 0x00023C00 | |
656 | ||
657 | /** | |
658 | * HQM Block Register Address Offset from BAR0 | |
659 | * HQM0 Range : 0x24000 - 0x243FF | |
660 | * HQM1 Range : 0x24400 - 0x247FF | |
661 | */ | |
662 | #define HQM0_BLK_REG_ADDR 0x00024000 | |
663 | #define HQM1_BLK_REG_ADDR 0x00024400 | |
664 | ||
665 | /** | |
666 | * HQM Control Register | |
667 | * Controls some aspects of IB | |
668 | * See catapult_spec.pdf for details | |
669 | */ | |
670 | #define HQM0_CTL_REG (HQM0_BLK_REG_ADDR + 0x000) | |
671 | #define HQM1_CTL_REG (HQM1_BLK_REG_ADDR + 0x000) | |
672 | ||
673 | /** | |
674 | * HQM Stop Q Semaphore Registers. | |
675 | * Only one Queue resource can be stopped at | |
676 | * any given time. This register controls access | |
677 | * to the single stop Q resource. | |
678 | * See catapult_spec.pdf for details | |
679 | */ | |
680 | #define HQM0_RXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x028) | |
681 | #define HQM0_TXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x02C) | |
682 | #define HQM1_RXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x028) | |
683 | #define HQM1_TXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x02C) | |
684 | ||
685 | /** | |
686 | * LUT Block Register Address Offset from BAR0 | |
687 | * LUT0 Range : 0x25800 - 0x25BFF | |
688 | * LUT1 Range : 0x25C00 - 0x25FFF | |
689 | */ | |
690 | #define LUT0_BLK_REG_ADDR 0x00025800 | |
691 | #define LUT1_BLK_REG_ADDR 0x00025C00 | |
692 | ||
693 | /** | |
694 | * LUT Registers | |
695 | * See catapult_spec.pdf for details | |
696 | */ | |
697 | #define LUT0_ERR_STS (LUT0_BLK_REG_ADDR + 0x000) | |
698 | #define LUT1_ERR_STS (LUT1_BLK_REG_ADDR + 0x000) | |
699 | #define LUT0_SET_ERR_STS (LUT0_BLK_REG_ADDR + 0x004) | |
700 | #define LUT1_SET_ERR_STS (LUT1_BLK_REG_ADDR + 0x004) | |
701 | ||
702 | /** | |
703 | * TRC (Debug/Trace) Register Offset from BAR0 | |
704 | * Range : 0x26000 -- 0x263FFF | |
705 | */ | |
706 | #define TRC_BLK_REG_ADDR 0x00026000 | |
707 | ||
708 | /** | |
709 | * TRC Registers | |
710 | * See catapult_spec.pdf for details of each | |
711 | */ | |
712 | #define TRC_CTL_REG (TRC_BLK_REG_ADDR + 0x000) | |
713 | #define TRC_MODS_REG (TRC_BLK_REG_ADDR + 0x004) | |
714 | #define TRC_TRGC_REG (TRC_BLK_REG_ADDR + 0x008) | |
715 | #define TRC_CNT1_REG (TRC_BLK_REG_ADDR + 0x010) | |
716 | #define TRC_CNT2_REG (TRC_BLK_REG_ADDR + 0x014) | |
717 | #define TRC_NXTS_REG (TRC_BLK_REG_ADDR + 0x018) | |
718 | #define TRC_DIRR_REG (TRC_BLK_REG_ADDR + 0x01C) | |
719 | ||
720 | /** | |
721 | * TRC Trigger match filters, total 10 | |
722 | * Determines the trigger condition | |
723 | */ | |
724 | #define TRC_TRGM_REG(_num) \ | |
725 | (TRC_BLK_REG_ADDR + 0x040 + ((_num) << 2)) | |
726 | ||
727 | /** | |
728 | * TRC Next State filters, total 10 | |
729 | * Determines the next state conditions | |
730 | */ | |
731 | #define TRC_NXTM_REG(_num) \ | |
732 | (TRC_BLK_REG_ADDR + 0x080 + ((_num) << 2)) | |
733 | ||
734 | /** | |
735 | * TRC Store Match filters, total 10 | |
736 | * Determines the store conditions | |
737 | */ | |
738 | #define TRC_STRM_REG(_num) \ | |
739 | (TRC_BLK_REG_ADDR + 0x0C0 + ((_num) << 2)) | |
740 | ||
741 | /* DOORBELLS ACCESS */ | |
742 | ||
743 | /** | |
744 | * Catapult doorbells | |
745 | * Each doorbell-queue set has | |
746 | * 1 RxQ, 1 TxQ, 2 IBs in that order | |
747 | * Size of each entry in 32 bytes, even though only 1 word | |
748 | * is used. For Non-VM case each doorbell-q set is | |
749 | * separated by 128 bytes, for VM case it is separated | |
750 | * by 4K bytes | |
751 | * Non VM case Range : 0x38000 - 0x39FFF | |
752 | * VM case Range : 0x100000 - 0x11FFFF | |
753 | * The range applies to both HQMs | |
754 | */ | |
755 | #define HQM_DOORBELL_BLK_BASE_ADDR 0x00038000 | |
756 | #define HQM_DOORBELL_VM_BLK_BASE_ADDR 0x00100000 | |
757 | ||
758 | /* MEMORY ACCESS */ | |
759 | ||
760 | /** | |
761 | * Catapult H/W Block Memory Access Address | |
762 | * To the host a memory space of 32K (page) is visible | |
763 | * at a time. The address range is from 0x08000 to 0x0FFFF | |
764 | */ | |
765 | #define HW_BLK_HOST_MEM_ADDR 0x08000 | |
766 | ||
767 | /** | |
768 | * Catapult LUT Memory Access Page Numbers | |
769 | * Range : LUT0 0xa0-0xa1 | |
770 | * LUT1 0xa2-0xa3 | |
771 | */ | |
772 | #define LUT0_MEM_BLK_BASE_PG_NUM 0x000000A0 | |
773 | #define LUT1_MEM_BLK_BASE_PG_NUM 0x000000A2 | |
774 | ||
775 | /** | |
776 | * Catapult RxFn Database Memory Block Base Offset | |
777 | * | |
778 | * The Rx function database exists in LUT block. | |
779 | * In PCIe space this is accessible as a 256x32 | |
780 | * bit block. Each entry in this database is 4 | |
781 | * (4 byte) words. Max. entries is 64. | |
782 | * Address of an entry corresponding to a function | |
783 | * = base_addr + (function_no. * 16) | |
784 | */ | |
785 | #define RX_FNDB_RAM_BASE_OFFSET 0x0000B400 | |
786 | ||
787 | /** | |
788 | * Catapult TxFn Database Memory Block Base Offset Address | |
789 | * | |
790 | * The Tx function database exists in LUT block. | |
791 | * In PCIe space this is accessible as a 64x32 | |
792 | * bit block. Each entry in this database is 1 | |
793 | * (4 byte) word. Max. entries is 64. | |
794 | * Address of an entry corresponding to a function | |
795 | * = base_addr + (function_no. * 4) | |
796 | */ | |
797 | #define TX_FNDB_RAM_BASE_OFFSET 0x0000B800 | |
798 | ||
799 | /** | |
800 | * Catapult Unicast CAM Base Offset Address | |
801 | * | |
802 | * Exists in LUT memory space. | |
803 | * Shared by both the LL & FCoE driver. | |
804 | * Size is 256x48 bits; mapped to PCIe space | |
805 | * 512x32 bit blocks. For each address, bits | |
806 | * are written in the order : [47:32] and then | |
807 | * [31:0]. | |
808 | */ | |
809 | #define UCAST_CAM_BASE_OFFSET 0x0000A800 | |
810 | ||
811 | /** | |
812 | * Catapult Unicast RAM Base Offset Address | |
813 | * | |
814 | * Exists in LUT memory space. | |
815 | * Shared by both the LL & FCoE driver. | |
816 | * Size is 256x9 bits. | |
817 | */ | |
818 | #define UCAST_RAM_BASE_OFFSET 0x0000B000 | |
819 | ||
820 | /** | |
821 | * Catapult Mulicast CAM Base Offset Address | |
822 | * | |
823 | * Exists in LUT memory space. | |
824 | * Shared by both the LL & FCoE driver. | |
825 | * Size is 256x48 bits; mapped to PCIe space | |
826 | * 512x32 bit blocks. For each address, bits | |
827 | * are written in the order : [47:32] and then | |
828 | * [31:0]. | |
829 | */ | |
830 | #define MCAST_CAM_BASE_OFFSET 0x0000A000 | |
831 | ||
832 | /** | |
833 | * Catapult VLAN RAM Base Offset Address | |
834 | * | |
835 | * Exists in LUT memory space. | |
836 | * Size is 4096x66 bits; mapped to PCIe space as | |
837 | * 8192x32 bit blocks. | |
838 | * All the 4K entries are within the address range | |
839 | * 0x0000 to 0x8000, so in the first LUT page. | |
840 | */ | |
841 | #define VLAN_RAM_BASE_OFFSET 0x00000000 | |
842 | ||
843 | /** | |
844 | * Catapult Tx Stats RAM Base Offset Address | |
845 | * | |
846 | * Exists in LUT memory space. | |
847 | * Size is 1024x33 bits; | |
848 | * Each Tx function has 64 bytes of space | |
849 | */ | |
850 | #define TX_STATS_RAM_BASE_OFFSET 0x00009000 | |
851 | ||
852 | /** | |
853 | * Catapult Rx Stats RAM Base Offset Address | |
854 | * | |
855 | * Exists in LUT memory space. | |
856 | * Size is 1024x33 bits; | |
857 | * Each Rx function has 64 bytes of space | |
858 | */ | |
859 | #define RX_STATS_RAM_BASE_OFFSET 0x00008000 | |
860 | ||
861 | /* Catapult RXA Memory Access Page Numbers */ | |
862 | #define RXA0_MEM_BLK_BASE_PG_NUM 0x0000008C | |
863 | #define RXA1_MEM_BLK_BASE_PG_NUM 0x0000008D | |
864 | ||
865 | /** | |
866 | * Catapult Multicast Vector Table Base Offset Address | |
867 | * | |
868 | * Exists in RxA memory space. | |
869 | * Organized as 512x65 bit block. | |
870 | * However for each entry 16 bytes allocated (power of 2) | |
871 | * Total size 512*16 bytes. | |
872 | * There are two logical divisions, 256 entries each : | |
873 | * a) Entries 0x00 to 0xff (256) -- Approx. MVT | |
874 | * Offset 0x000 to 0xFFF | |
875 | * b) Entries 0x100 to 0x1ff (256) -- Exact MVT | |
876 | * Offsets 0x1000 to 0x1FFF | |
877 | */ | |
878 | #define MCAST_APPROX_MVT_BASE_OFFSET 0x00000000 | |
879 | #define MCAST_EXACT_MVT_BASE_OFFSET 0x00001000 | |
880 | ||
881 | /** | |
882 | * Catapult RxQ Translate Table (RIT) Base Offset Address | |
883 | * | |
884 | * Exists in RxA memory space | |
885 | * Total no. of entries 64 | |
886 | * Each entry is 1 (4 byte) word. | |
887 | * 31:12 -- Reserved | |
888 | * 11:0 -- Two 6 bit RxQ Ids | |
889 | */ | |
890 | #define FUNCTION_TO_RXQ_TRANSLATE 0x00002000 | |
891 | ||
892 | /* Catapult RxAdm (RAD) Memory Access Page Numbers */ | |
893 | #define RAD0_MEM_BLK_BASE_PG_NUM 0x00000086 | |
894 | #define RAD1_MEM_BLK_BASE_PG_NUM 0x00000087 | |
895 | ||
896 | /** | |
897 | * Catapult RSS Table Base Offset Address | |
898 | * | |
899 | * Exists in RAD memory space. | |
25985edc | 900 | * Each entry is 352 bits, but aligned on |
8b230ed8 RM |
901 | * 64 byte (512 bit) boundary. Accessed |
902 | * 4 byte words, the whole entry can be | |
903 | * broken into 11 word accesses. | |
904 | */ | |
905 | #define RSS_TABLE_BASE_OFFSET 0x00000800 | |
906 | ||
907 | /** | |
908 | * Catapult CPQ Block Page Number | |
909 | * This value is written to the page number registers | |
910 | * to access the memory associated with the mailboxes. | |
911 | */ | |
912 | #define CPQ_BLK_PG_NUM 0x00000005 | |
913 | ||
914 | /** | |
915 | * Clarification : | |
916 | * LL functions are 2 & 3; can HostFn0/HostFn1 | |
917 | * <-> LPU0/LPU1 memories be used ? | |
918 | */ | |
919 | /** | |
920 | * Catapult HostFn0/HostFn1 to LPU0/LPU1 Mbox memory | |
921 | * Per catapult_spec.pdf, the offset of the mbox | |
922 | * memory is in the register space at an offset of 0x200 | |
923 | */ | |
924 | #define CPQ_BLK_REG_MBOX_ADDR (CPQ_BLK_REG_ADDR + 0x200) | |
925 | ||
926 | #define HOSTFN_LPU_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x000) | |
927 | ||
928 | /* Catapult LPU0/LPU1 to HostFn0/HostFn1 Mbox memory */ | |
929 | #define LPU_HOSTFN_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x080) | |
930 | ||
931 | /** | |
932 | * Catapult HQM Block Page Number | |
933 | * This is written to the page number register for | |
934 | * the appropriate function to access the memory | |
935 | * associated with HQM | |
936 | */ | |
937 | #define HQM0_BLK_PG_NUM 0x00000096 | |
938 | #define HQM1_BLK_PG_NUM 0x00000097 | |
939 | ||
940 | /** | |
941 | * Note that TxQ and RxQ entries are interlaced | |
942 | * the HQM memory, i.e RXQ0, TXQ0, RXQ1, TXQ1.. etc. | |
943 | */ | |
944 | ||
945 | #define HQM_RXTX_Q_RAM_BASE_OFFSET 0x00004000 | |
946 | ||
947 | /** | |
948 | * CQ Memory | |
949 | * Exists in HQM Memory space | |
950 | * Each entry is 16 (4 byte) words of which | |
951 | * only 12 words are used for configuration | |
952 | * Total 64 entries per HQM memory space | |
953 | */ | |
954 | #define HQM_CQ_RAM_BASE_OFFSET 0x00006000 | |
955 | ||
956 | /** | |
957 | * Interrupt Block (IB) Memory | |
958 | * Exists in HQM Memory space | |
959 | * Each entry is 8 (4 byte) words of which | |
960 | * only 5 words are used for configuration | |
961 | * Total 128 entries per HQM memory space | |
962 | */ | |
963 | #define HQM_IB_RAM_BASE_OFFSET 0x00001000 | |
964 | ||
965 | /** | |
966 | * Index Table (IT) Memory | |
967 | * Exists in HQM Memory space | |
968 | * Each entry is 1 (4 byte) word which | |
969 | * is used for configuration | |
970 | * Total 128 entries per HQM memory space | |
971 | */ | |
972 | #define HQM_INDX_TBL_RAM_BASE_OFFSET 0x00002000 | |
973 | ||
974 | /** | |
975 | * PSS Block Memory Page Number | |
976 | * This is written to the appropriate page number | |
977 | * register to access the CPU memory. | |
978 | * Also known as the PSS secondary memory (SMEM). | |
979 | * Range : 0x180 to 0x1CF | |
980 | * See catapult_spec.pdf for details | |
981 | */ | |
982 | #define PSS_BLK_PG_NUM 0x00000180 | |
983 | ||
984 | /** | |
985 | * Offsets of different instances of PSS SMEM | |
986 | * 2.5M of continuous 1T memory space : 2 blocks | |
987 | * of 1M each (32 pages each, page=32KB) and 4 smaller | |
988 | * blocks of 128K each (4 pages each, page=32KB) | |
989 | * PSS_LMEM_INST0 is used for firmware download | |
990 | */ | |
991 | #define PSS_LMEM_INST0 0x00000000 | |
992 | #define PSS_LMEM_INST1 0x00100000 | |
993 | #define PSS_LMEM_INST2 0x00200000 | |
994 | #define PSS_LMEM_INST3 0x00220000 | |
995 | #define PSS_LMEM_INST4 0x00240000 | |
996 | #define PSS_LMEM_INST5 0x00260000 | |
997 | ||
998 | #define BNA_PCI_REG_CT_ADDRSZ (0x40000) | |
999 | ||
1000 | #define BNA_GET_PAGE_NUM(_base_page, _offset) \ | |
1001 | ((_base_page) + ((_offset) >> 15)) | |
1002 | ||
1003 | #define BNA_GET_PAGE_OFFSET(_offset) \ | |
1004 | ((_offset) & 0x7fff) | |
1005 | ||
1006 | #define BNA_GET_MEM_BASE_ADDR(_bar0, _base_offset) \ | |
1007 | ((_bar0) + HW_BLK_HOST_MEM_ADDR \ | |
1008 | + BNA_GET_PAGE_OFFSET((_base_offset))) | |
1009 | ||
1010 | #define BNA_GET_VLAN_MEM_ENTRY_ADDR(_bar0, _fn_id, _vlan_id)\ | |
1011 | (_bar0 + (HW_BLK_HOST_MEM_ADDR) \ | |
1012 | + (BNA_GET_PAGE_OFFSET(VLAN_RAM_BASE_OFFSET)) \ | |
1013 | + (((_fn_id) & 0x3f) << 9) \ | |
1014 | + (((_vlan_id) & 0xfe0) >> 3)) | |
1015 | ||
1016 | /** | |
1017 | * | |
1018 | * Interrupt related bits, flags and macros | |
1019 | * | |
1020 | */ | |
1021 | ||
1022 | #define __LPU02HOST_MBOX0_STATUS_BITS 0x00100000 | |
1023 | #define __LPU12HOST_MBOX0_STATUS_BITS 0x00200000 | |
1024 | #define __LPU02HOST_MBOX1_STATUS_BITS 0x00400000 | |
1025 | #define __LPU12HOST_MBOX1_STATUS_BITS 0x00800000 | |
1026 | ||
1027 | #define __LPU02HOST_MBOX0_MASK_BITS 0x00100000 | |
1028 | #define __LPU12HOST_MBOX0_MASK_BITS 0x00200000 | |
1029 | #define __LPU02HOST_MBOX1_MASK_BITS 0x00400000 | |
1030 | #define __LPU12HOST_MBOX1_MASK_BITS 0x00800000 | |
1031 | ||
1032 | #define __LPU2HOST_MBOX_MASK_BITS \ | |
1033 | (__LPU02HOST_MBOX0_MASK_BITS | __LPU02HOST_MBOX1_MASK_BITS | \ | |
1034 | __LPU12HOST_MBOX0_MASK_BITS | __LPU12HOST_MBOX1_MASK_BITS) | |
1035 | ||
1036 | #define __LPU2HOST_IB_STATUS_BITS 0x0000ffff | |
1037 | ||
1038 | #define BNA_IS_LPU0_MBOX_INTR(_intr_status) \ | |
1039 | ((_intr_status) & (__LPU02HOST_MBOX0_STATUS_BITS | \ | |
1040 | __LPU02HOST_MBOX1_STATUS_BITS)) | |
1041 | ||
1042 | #define BNA_IS_LPU1_MBOX_INTR(_intr_status) \ | |
1043 | ((_intr_status) & (__LPU12HOST_MBOX0_STATUS_BITS | \ | |
1044 | __LPU12HOST_MBOX1_STATUS_BITS)) | |
1045 | ||
1046 | #define BNA_IS_MBOX_INTR(_intr_status) \ | |
1047 | ((_intr_status) & \ | |
1048 | (__LPU02HOST_MBOX0_STATUS_BITS | \ | |
1049 | __LPU02HOST_MBOX1_STATUS_BITS | \ | |
1050 | __LPU12HOST_MBOX0_STATUS_BITS | \ | |
1051 | __LPU12HOST_MBOX1_STATUS_BITS)) | |
1052 | ||
1053 | #define __EMC_ERROR_STATUS_BITS 0x00010000 | |
1054 | #define __LPU0_ERROR_STATUS_BITS 0x00020000 | |
1055 | #define __LPU1_ERROR_STATUS_BITS 0x00040000 | |
1056 | #define __PSS_ERROR_STATUS_BITS 0x00080000 | |
1057 | ||
1058 | #define __HALT_STATUS_BITS 0x01000000 | |
1059 | ||
1060 | #define __EMC_ERROR_MASK_BITS 0x00010000 | |
1061 | #define __LPU0_ERROR_MASK_BITS 0x00020000 | |
1062 | #define __LPU1_ERROR_MASK_BITS 0x00040000 | |
1063 | #define __PSS_ERROR_MASK_BITS 0x00080000 | |
1064 | ||
1065 | #define __HALT_MASK_BITS 0x01000000 | |
1066 | ||
1067 | #define __ERROR_MASK_BITS \ | |
1068 | (__EMC_ERROR_MASK_BITS | __LPU0_ERROR_MASK_BITS | \ | |
1069 | __LPU1_ERROR_MASK_BITS | __PSS_ERROR_MASK_BITS | \ | |
1070 | __HALT_MASK_BITS) | |
1071 | ||
1072 | #define BNA_IS_ERR_INTR(_intr_status) \ | |
1073 | ((_intr_status) & \ | |
1074 | (__EMC_ERROR_STATUS_BITS | \ | |
1075 | __LPU0_ERROR_STATUS_BITS | \ | |
1076 | __LPU1_ERROR_STATUS_BITS | \ | |
1077 | __PSS_ERROR_STATUS_BITS | \ | |
1078 | __HALT_STATUS_BITS)) | |
1079 | ||
1080 | #define BNA_IS_MBOX_ERR_INTR(_intr_status) \ | |
1081 | (BNA_IS_MBOX_INTR((_intr_status)) | \ | |
1082 | BNA_IS_ERR_INTR((_intr_status))) | |
1083 | ||
1084 | #define BNA_IS_INTX_DATA_INTR(_intr_status) \ | |
1085 | ((_intr_status) & __LPU2HOST_IB_STATUS_BITS) | |
1086 | ||
1087 | #define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \ | |
1088 | do { \ | |
1089 | (_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \ | |
1090 | __LPU02HOST_MBOX1_STATUS_BITS | \ | |
1091 | __LPU12HOST_MBOX0_STATUS_BITS | \ | |
1092 | __LPU12HOST_MBOX1_STATUS_BITS); \ | |
1093 | } while (0) | |
1094 | ||
1095 | #define BNA_INTR_STATUS_ERR_CLR(_intr_status) \ | |
1096 | do { \ | |
1097 | (_intr_status) &= ~(__EMC_ERROR_STATUS_BITS | \ | |
1098 | __LPU0_ERROR_STATUS_BITS | \ | |
1099 | __LPU1_ERROR_STATUS_BITS | \ | |
1100 | __PSS_ERROR_STATUS_BITS | \ | |
1101 | __HALT_STATUS_BITS); \ | |
1102 | } while (0) | |
1103 | ||
1104 | #define bna_intx_disable(_bna, _cur_mask) \ | |
1105 | { \ | |
1106 | (_cur_mask) = readl((_bna)->regs.fn_int_mask);\ | |
1107 | writel(0xffffffff, (_bna)->regs.fn_int_mask);\ | |
1108 | } | |
1109 | ||
1110 | #define bna_intx_enable(bna, new_mask) \ | |
1111 | writel((new_mask), (bna)->regs.fn_int_mask) | |
1112 | ||
1113 | #define bna_mbox_intr_disable(bna) \ | |
1114 | writel((readl((bna)->regs.fn_int_mask) | \ | |
1115 | (__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \ | |
1116 | (bna)->regs.fn_int_mask) | |
1117 | ||
1118 | #define bna_mbox_intr_enable(bna) \ | |
1119 | writel((readl((bna)->regs.fn_int_mask) & \ | |
1120 | ~(__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \ | |
1121 | (bna)->regs.fn_int_mask) | |
1122 | ||
1123 | #define bna_intr_status_get(_bna, _status) \ | |
1124 | { \ | |
1125 | (_status) = readl((_bna)->regs.fn_int_status); \ | |
1126 | if ((_status)) { \ | |
1127 | writel((_status) & ~(__LPU02HOST_MBOX0_STATUS_BITS |\ | |
1128 | __LPU02HOST_MBOX1_STATUS_BITS |\ | |
1129 | __LPU12HOST_MBOX0_STATUS_BITS |\ | |
1130 | __LPU12HOST_MBOX1_STATUS_BITS), \ | |
1131 | (_bna)->regs.fn_int_status);\ | |
1132 | } \ | |
1133 | } | |
1134 | ||
1135 | #define bna_intr_status_get_no_clr(_bna, _status) \ | |
1136 | (_status) = readl((_bna)->regs.fn_int_status) | |
1137 | ||
1138 | #define bna_intr_mask_get(bna, mask) \ | |
1139 | (*mask) = readl((bna)->regs.fn_int_mask) | |
1140 | ||
1141 | #define bna_intr_ack(bna, intr_bmap) \ | |
1142 | writel((intr_bmap), (bna)->regs.fn_int_status) | |
1143 | ||
1144 | #define bna_ib_intx_disable(bna, ib_id) \ | |
1145 | writel(readl((bna)->regs.fn_int_mask) | \ | |
1146 | (1 << (ib_id)), \ | |
1147 | (bna)->regs.fn_int_mask) | |
1148 | ||
1149 | #define bna_ib_intx_enable(bna, ib_id) \ | |
1150 | writel(readl((bna)->regs.fn_int_mask) & \ | |
1151 | ~(1 << (ib_id)), \ | |
1152 | (bna)->regs.fn_int_mask) | |
1153 | ||
1154 | #define bna_mbox_msix_idx_set(_device) \ | |
1155 | do {\ | |
1156 | writel(((_device)->vector & 0x000001FF), \ | |
1157 | (_device)->bna->pcidev.pci_bar_kva + \ | |
1158 | reg_offset[(_device)->bna->pcidev.pci_func].msix_idx);\ | |
1159 | } while (0) | |
1160 | ||
1161 | /** | |
1162 | * | |
1163 | * TxQ, RxQ, CQ related bits, offsets, macros | |
1164 | * | |
1165 | */ | |
1166 | ||
1167 | #define BNA_Q_IDLE_STATE 0x00008001 | |
1168 | ||
1169 | #define BNA_GET_DOORBELL_BASE_ADDR(_bar0) \ | |
1170 | ((_bar0) + HQM_DOORBELL_BLK_BASE_ADDR) | |
1171 | ||
1172 | #define BNA_GET_DOORBELL_ENTRY_OFFSET(_entry) \ | |
1173 | ((HQM_DOORBELL_BLK_BASE_ADDR) \ | |
1174 | + (_entry << 7)) | |
1175 | ||
1176 | #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \ | |
1177 | (0x80000000 | ((_timeout) << 16) | (_events)) | |
1178 | ||
1179 | #define BNA_DOORBELL_IB_INT_DISABLE (0x40000000) | |
1180 | ||
1181 | /* TxQ Entry Opcodes */ | |
1182 | #define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */ | |
1183 | #define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */ | |
1184 | #define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */ | |
1185 | ||
1186 | /* TxQ Entry Control Flags */ | |
1187 | #define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8) | |
1188 | #define BNA_TXQ_WI_CF_IPID_MODE (1 << 5) | |
1189 | #define BNA_TXQ_WI_CF_INS_PRIO (1 << 4) | |
1190 | #define BNA_TXQ_WI_CF_INS_VLAN (1 << 3) | |
1191 | #define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2) | |
1192 | #define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1) | |
1193 | #define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0) | |
1194 | ||
1195 | #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \ | |
1196 | (((_hdr_size) << 10) | ((_offset) & 0x3FF)) | |
1197 | ||
1198 | /* | |
1199 | * Completion Q defines | |
1200 | */ | |
1201 | /* CQ Entry Flags */ | |
1202 | #define BNA_CQ_EF_MAC_ERROR (1 << 0) | |
1203 | #define BNA_CQ_EF_FCS_ERROR (1 << 1) | |
1204 | #define BNA_CQ_EF_TOO_LONG (1 << 2) | |
1205 | #define BNA_CQ_EF_FC_CRC_OK (1 << 3) | |
1206 | ||
1207 | #define BNA_CQ_EF_RSVD1 (1 << 4) | |
1208 | #define BNA_CQ_EF_L4_CKSUM_OK (1 << 5) | |
1209 | #define BNA_CQ_EF_L3_CKSUM_OK (1 << 6) | |
1210 | #define BNA_CQ_EF_HDS_HEADER (1 << 7) | |
1211 | ||
1212 | #define BNA_CQ_EF_UDP (1 << 8) | |
1213 | #define BNA_CQ_EF_TCP (1 << 9) | |
1214 | #define BNA_CQ_EF_IP_OPTIONS (1 << 10) | |
1215 | #define BNA_CQ_EF_IPV6 (1 << 11) | |
1216 | ||
1217 | #define BNA_CQ_EF_IPV4 (1 << 12) | |
1218 | #define BNA_CQ_EF_VLAN (1 << 13) | |
1219 | #define BNA_CQ_EF_RSS (1 << 14) | |
1220 | #define BNA_CQ_EF_RSVD2 (1 << 15) | |
1221 | ||
1222 | #define BNA_CQ_EF_MCAST_MATCH (1 << 16) | |
1223 | #define BNA_CQ_EF_MCAST (1 << 17) | |
1224 | #define BNA_CQ_EF_BCAST (1 << 18) | |
1225 | #define BNA_CQ_EF_REMOTE (1 << 19) | |
1226 | ||
1227 | #define BNA_CQ_EF_LOCAL (1 << 20) | |
1228 | ||
1229 | /** | |
1230 | * | |
1231 | * Data structures | |
1232 | * | |
1233 | */ | |
1234 | ||
1235 | enum txf_flags { | |
1236 | BFI_TXF_CF_ENABLE = 1 << 0, | |
1237 | BFI_TXF_CF_VLAN_FILTER = 1 << 8, | |
1238 | BFI_TXF_CF_VLAN_ADMIT = 1 << 9, | |
1239 | BFI_TXF_CF_VLAN_INSERT = 1 << 10, | |
1240 | BFI_TXF_CF_RSVD1 = 1 << 11, | |
1241 | BFI_TXF_CF_MAC_SA_CHECK = 1 << 12, | |
1242 | BFI_TXF_CF_VLAN_WI_BASED = 1 << 13, | |
1243 | BFI_TXF_CF_VSWITCH_MCAST = 1 << 14, | |
1244 | BFI_TXF_CF_VSWITCH_UCAST = 1 << 15, | |
1245 | BFI_TXF_CF_RSVD2 = 0x7F << 1 | |
1246 | }; | |
1247 | ||
1248 | enum ib_flags { | |
1249 | BFI_IB_CF_MASTER_ENABLE = (1 << 0), | |
1250 | BFI_IB_CF_MSIX_MODE = (1 << 1), | |
1251 | BFI_IB_CF_COALESCING_MODE = (1 << 2), | |
1252 | BFI_IB_CF_INTER_PKT_ENABLE = (1 << 3), | |
1253 | BFI_IB_CF_INT_ENABLE = (1 << 4), | |
1254 | BFI_IB_CF_INTER_PKT_DMA = (1 << 5), | |
1255 | BFI_IB_CF_ACK_PENDING = (1 << 6), | |
1256 | BFI_IB_CF_RESERVED1 = (1 << 7) | |
1257 | }; | |
1258 | ||
1259 | enum rss_hash_type { | |
1260 | BFI_RSS_T_V4_TCP = (1 << 11), | |
1261 | BFI_RSS_T_V4_IP = (1 << 10), | |
1262 | BFI_RSS_T_V6_TCP = (1 << 9), | |
1263 | BFI_RSS_T_V6_IP = (1 << 8) | |
1264 | }; | |
1265 | enum hds_header_type { | |
1266 | BNA_HDS_T_V4_TCP = (1 << 11), | |
1267 | BNA_HDS_T_V4_UDP = (1 << 10), | |
1268 | BNA_HDS_T_V6_TCP = (1 << 9), | |
1269 | BNA_HDS_T_V6_UDP = (1 << 8), | |
1270 | BNA_HDS_FORCED = (1 << 7), | |
1271 | }; | |
1272 | enum rxf_flags { | |
1273 | BNA_RXF_CF_SM_LG_RXQ = (1 << 15), | |
1274 | BNA_RXF_CF_DEFAULT_VLAN = (1 << 14), | |
1275 | BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE = (1 << 13), | |
1276 | BNA_RXF_CF_VLAN_STRIP = (1 << 12), | |
1277 | BNA_RXF_CF_RSS_ENABLE = (1 << 8) | |
1278 | }; | |
1279 | struct bna_chip_regs_offset { | |
1280 | u32 page_addr; | |
1281 | u32 fn_int_status; | |
1282 | u32 fn_int_mask; | |
1283 | u32 msix_idx; | |
1284 | }; | |
8b230ed8 RM |
1285 | |
1286 | struct bna_chip_regs { | |
1287 | void __iomem *page_addr; | |
1288 | void __iomem *fn_int_status; | |
1289 | void __iomem *fn_int_mask; | |
1290 | }; | |
1291 | ||
1292 | struct bna_txq_mem { | |
1293 | u32 pg_tbl_addr_lo; | |
1294 | u32 pg_tbl_addr_hi; | |
1295 | u32 cur_q_entry_lo; | |
1296 | u32 cur_q_entry_hi; | |
1297 | u32 reserved1; | |
1298 | u32 reserved2; | |
1299 | u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */ | |
1300 | /* 15:0 ->producer pointer (index?) */ | |
1301 | u32 entry_n_pg_size; /* 31:16->entry size */ | |
1302 | /* 15:0 ->page size */ | |
1303 | u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */ | |
1304 | /* 23:16->Int Blk Offset */ | |
1305 | /* 15:0 ->consumer pointer(index?) */ | |
1306 | u32 cns_ptr2_n_q_state; /* 31:16->cons. ptr 2; 15:0-> Q state */ | |
1307 | u32 nxt_qid_n_fid_n_pri; /* 17:10->next */ | |
1308 | /* QId;9:3->FID;2:0->Priority */ | |
1309 | u32 wvc_n_cquota_n_rquota; /* 31:24->WI Vector Count; */ | |
1310 | /* 23:12->Cfg Quota; */ | |
1311 | /* 11:0 ->Run Quota */ | |
1312 | u32 reserved3[4]; | |
1313 | }; | |
1314 | ||
1315 | struct bna_rxq_mem { | |
1316 | u32 pg_tbl_addr_lo; | |
1317 | u32 pg_tbl_addr_hi; | |
1318 | u32 cur_q_entry_lo; | |
1319 | u32 cur_q_entry_hi; | |
1320 | u32 reserved1; | |
1321 | u32 reserved2; | |
1322 | u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */ | |
1323 | /* 15:0 ->producer pointer (index?) */ | |
1324 | u32 entry_n_pg_size; /* 31:16->entry size */ | |
1325 | /* 15:0 ->page size */ | |
1326 | u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */ | |
1327 | /* 23:16->CQ; */ | |
1328 | /* 15:0->consumer pointer(index?) */ | |
1329 | u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */ | |
1330 | u32 next_qid; /* 17:10->next QId */ | |
1331 | u32 reserved3; | |
1332 | u32 reserved4[4]; | |
1333 | }; | |
1334 | ||
1335 | struct bna_rxtx_q_mem { | |
1336 | struct bna_rxq_mem rxq; | |
1337 | struct bna_txq_mem txq; | |
1338 | }; | |
1339 | ||
1340 | struct bna_cq_mem { | |
1341 | u32 pg_tbl_addr_lo; | |
1342 | u32 pg_tbl_addr_hi; | |
1343 | u32 cur_q_entry_lo; | |
1344 | u32 cur_q_entry_hi; | |
1345 | ||
1346 | u32 reserved1; | |
1347 | u32 reserved2; | |
1348 | u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */ | |
1349 | /* 15:0 ->producer pointer (index?) */ | |
1350 | u32 entry_n_pg_size; /* 31:16->entry size */ | |
1351 | /* 15:0 ->page size */ | |
1352 | u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */ | |
1353 | /* 23:16->Int Blk Offset */ | |
1354 | /* 15:0 ->consumer pointer(index?) */ | |
1355 | u32 q_state; /* 31:16->reserved; 15:0-> Q state */ | |
1356 | u32 reserved3[2]; | |
1357 | u32 reserved4[4]; | |
1358 | }; | |
1359 | ||
1360 | struct bna_ib_blk_mem { | |
1361 | u32 host_addr_lo; | |
1362 | u32 host_addr_hi; | |
1363 | u32 clsc_n_ctrl_n_msix; /* 31:24->coalescing; */ | |
1364 | /* 23:16->coalescing cfg; */ | |
1365 | /* 15:8 ->control; */ | |
1366 | /* 7:0 ->msix; */ | |
1367 | u32 ipkt_n_ent_n_idxof; | |
1368 | u32 ipkt_cnt_cfg_n_unacked; | |
1369 | ||
1370 | u32 reserved[3]; | |
1371 | }; | |
1372 | ||
1373 | struct bna_idx_tbl_mem { | |
1374 | u32 idx; /* !< 31:16->res;15:0->idx; */ | |
1375 | }; | |
1376 | ||
1377 | struct bna_doorbell_qset { | |
1378 | u32 rxq[0x20 >> 2]; | |
1379 | u32 txq[0x20 >> 2]; | |
1380 | u32 ib0[0x20 >> 2]; | |
1381 | u32 ib1[0x20 >> 2]; | |
1382 | }; | |
1383 | ||
1384 | struct bna_rx_fndb_ram { | |
1385 | u32 rss_prop; | |
1386 | u32 size_routing_props; | |
1387 | u32 rit_hds_mcastq; | |
1388 | u32 control_flags; | |
1389 | }; | |
1390 | ||
1391 | struct bna_tx_fndb_ram { | |
1392 | u32 vlan_n_ctrl_flags; | |
1393 | }; | |
1394 | ||
1395 | /** | |
1396 | * @brief | |
1397 | * Structure which maps to RxFn Indirection Table (RIT) | |
1398 | * Size : 1 word | |
1399 | * See catapult_spec.pdf, RxA for details | |
1400 | */ | |
1401 | struct bna_rit_mem { | |
1402 | u32 rxq_ids; /* !< 31:12->res;11:0->two 6 bit RxQ Ids */ | |
1403 | }; | |
1404 | ||
1405 | /** | |
1406 | * @brief | |
1407 | * Structure which maps to RSS Table entry | |
1408 | * Size : 16 words | |
1409 | * See catapult_spec.pdf, RAD for details | |
1410 | */ | |
1411 | struct bna_rss_mem { | |
1412 | /* | |
1413 | * 31:12-> res | |
1414 | * 11:8 -> protocol type | |
1415 | * 7:0 -> hash index | |
1416 | */ | |
1417 | u32 type_n_hash; | |
1418 | u32 hash_key[10]; /* !< 40 byte Toeplitz hash key */ | |
1419 | u32 reserved[5]; | |
1420 | }; | |
1421 | ||
1422 | /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */ | |
1423 | struct bna_dma_addr { | |
1424 | u32 msb; | |
1425 | u32 lsb; | |
1426 | }; | |
1427 | ||
1428 | struct bna_txq_wi_vector { | |
1429 | u16 reserved; | |
1430 | u16 length; /* Only 14 LSB are valid */ | |
1431 | struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */ | |
1432 | }; | |
1433 | ||
1434 | typedef u16 bna_txq_wi_opcode_t; | |
1435 | ||
1436 | typedef u16 bna_txq_wi_ctrl_flag_t; | |
1437 | ||
1438 | /** | |
1439 | * TxQ Entry Structure | |
1440 | * | |
1441 | * BEWARE: Load values into this structure with correct endianess. | |
1442 | */ | |
1443 | struct bna_txq_entry { | |
1444 | union { | |
1445 | struct { | |
1446 | u8 reserved; | |
1447 | u8 num_vectors; /* number of vectors present */ | |
1448 | bna_txq_wi_opcode_t opcode; /* Either */ | |
1449 | /* BNA_TXQ_WI_SEND or */ | |
1450 | /* BNA_TXQ_WI_SEND_LSO */ | |
1451 | bna_txq_wi_ctrl_flag_t flags; /* OR of all the flags */ | |
1452 | u16 l4_hdr_size_n_offset; | |
1453 | u16 vlan_tag; | |
1454 | u16 lso_mss; /* Only 14 LSB are valid */ | |
1455 | u32 frame_length; /* Only 24 LSB are valid */ | |
1456 | } wi; | |
1457 | ||
1458 | struct { | |
1459 | u16 reserved; | |
1460 | bna_txq_wi_opcode_t opcode; /* Must be */ | |
1461 | /* BNA_TXQ_WI_EXTENSION */ | |
1462 | u32 reserved2[3]; /* Place holder for */ | |
1463 | /* removed vector (12 bytes) */ | |
1464 | } wi_ext; | |
1465 | } hdr; | |
1466 | struct bna_txq_wi_vector vector[4]; | |
1467 | }; | |
1468 | #define wi_hdr hdr.wi | |
1469 | #define wi_ext_hdr hdr.wi_ext | |
1470 | ||
1471 | /* RxQ Entry Structure */ | |
1472 | struct bna_rxq_entry { /* Rx-Buffer */ | |
1473 | struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */ | |
1474 | }; | |
1475 | ||
1476 | typedef u32 bna_cq_e_flag_t; | |
1477 | ||
1478 | /* CQ Entry Structure */ | |
1479 | struct bna_cq_entry { | |
1480 | bna_cq_e_flag_t flags; | |
1481 | u16 vlan_tag; | |
1482 | u16 length; | |
1483 | u32 rss_hash; | |
1484 | u8 valid; | |
1485 | u8 reserved1; | |
1486 | u8 reserved2; | |
1487 | u8 rxq_id; | |
1488 | }; | |
1489 | ||
1490 | #endif /* __BNA_HW_H__ */ |