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bna: Restore VLAN filter table
[mirror_ubuntu-zesty-kernel.git] / drivers / net / bna / bnad.c
CommitLineData
8b230ed8
RM		 1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include <linux/netdevice.h>
19#include <linux/skbuff.h>
20#include <linux/etherdevice.h>
21#include <linux/in.h>
22#include <linux/ethtool.h>
23#include <linux/if_vlan.h>
24#include <linux/if_ether.h>
25#include <linux/ip.h>
26
27#include "bnad.h"
28#include "bna.h"
29#include "cna.h"
30
b7ee31c5 31static DEFINE_MUTEX(bnad_fwimg_mutex);
8b230ed8
RM		 32
33/*
34 * Module params
35 */
36static uint bnad_msix_disable;
37module_param(bnad_msix_disable, uint, 0444);
38MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
39
40static uint bnad_ioc_auto_recover = 1;
41module_param(bnad_ioc_auto_recover, uint, 0444);
42MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
43
44/*
45 * Global variables
46 */
47u32 bnad_rxqs_per_cq = 2;
48
b7ee31c5 49static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
8b230ed8
RM		 50
51/*
52 * Local MACROS
53 */
54#define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
55
56#define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
57
58#define BNAD_GET_MBOX_IRQ(_bnad) \
59 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
60 ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
61 ((_bnad)->pcidev->irq))
62
63#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
64do { \
65 (_res_info)->res_type = BNA_RES_T_MEM; \
66 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
67 (_res_info)->res_u.mem_info.num = (_num); \
68 (_res_info)->res_u.mem_info.len = \
69 sizeof(struct bnad_unmap_q) + \
70 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
71} while (0)
72
be7fa326
RM		 73#define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
74
8b230ed8
RM		 75/*
76 * Reinitialize completions in CQ, once Rx is taken down
77 */
78static void
79bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
80{
81 struct bna_cq_entry *cmpl, *next_cmpl;
82 unsigned int wi_range, wis = 0, ccb_prod = 0;
83 int i;
84
85 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
86 wi_range);
87
88 for (i = 0; i < ccb->q_depth; i++) {
89 wis++;
90 if (likely(--wi_range))
91 next_cmpl = cmpl + 1;
92 else {
93 BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
94 wis = 0;
95 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
96 next_cmpl, wi_range);
97 }
98 cmpl->valid = 0;
99 cmpl = next_cmpl;
100 }
101}
102
103/*
104 * Frees all pending Tx Bufs
105 * At this point no activity is expected on the Q,
106 * so DMA unmap & freeing is fine.
107 */
108static void
109bnad_free_all_txbufs(struct bnad *bnad,
110 struct bna_tcb *tcb)
111{
f7c0fa4c 112 u32 unmap_cons;
8b230ed8
RM		 113 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
114 struct bnad_skb_unmap *unmap_array;
115 struct sk_buff *skb = NULL;
116 int i;
117
118 unmap_array = unmap_q->unmap_array;
119
120 unmap_cons = 0;
121 while (unmap_cons < unmap_q->q_depth) {
122 skb = unmap_array[unmap_cons].skb;
123 if (!skb) {
124 unmap_cons++;
125 continue;
126 }
127 unmap_array[unmap_cons].skb = NULL;
128
129 pci_unmap_single(bnad->pcidev,
130 pci_unmap_addr(&unmap_array[unmap_cons],
131 dma_addr), skb_headlen(skb),
132 PCI_DMA_TODEVICE);
133
134 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
be7fa326
RM		 135 if (++unmap_cons >= unmap_q->q_depth)
136 break;
137
8b230ed8
RM		 138 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
139 pci_unmap_page(bnad->pcidev,
140 pci_unmap_addr(&unmap_array[unmap_cons],
141 dma_addr),
142 skb_shinfo(skb)->frags[i].size,
143 PCI_DMA_TODEVICE);
144 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
145 0);
be7fa326
RM		 146 if (++unmap_cons >= unmap_q->q_depth)
147 break;
8b230ed8
RM		 148 }
149 dev_kfree_skb_any(skb);
150 }
151}
152
153/* Data Path Handlers */
154
155/*
156 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
157 * Can be called in a) Interrupt context
158 * b) Sending context
159 * c) Tasklet context
160 */
161static u32
162bnad_free_txbufs(struct bnad *bnad,
163 struct bna_tcb *tcb)
164{
165 u32 sent_packets = 0, sent_bytes = 0;
166 u16 wis, unmap_cons, updated_hw_cons;
167 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
168 struct bnad_skb_unmap *unmap_array;
169 struct sk_buff *skb;
170 int i;
171
172 /*
173 * Just return if TX is stopped. This check is useful
174 * when bnad_free_txbufs() runs out of a tasklet scheduled
be7fa326 175 * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
8b230ed8
RM		 176 * but this routine runs actually after the cleanup has been
177 * executed.
178 */
be7fa326 179 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
8b230ed8
RM		 180 return 0;
181
182 updated_hw_cons = *(tcb->hw_consumer_index);
183
184 wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
185 updated_hw_cons, tcb->q_depth);
186
187 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
188
189 unmap_array = unmap_q->unmap_array;
190 unmap_cons = unmap_q->consumer_index;
191
192 prefetch(&unmap_array[unmap_cons + 1]);
193 while (wis) {
194 skb = unmap_array[unmap_cons].skb;
195
196 unmap_array[unmap_cons].skb = NULL;
197
198 sent_packets++;
199 sent_bytes += skb->len;
200 wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
201
202 pci_unmap_single(bnad->pcidev,
203 pci_unmap_addr(&unmap_array[unmap_cons],
204 dma_addr), skb_headlen(skb),
205 PCI_DMA_TODEVICE);
206 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
207 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
208
209 prefetch(&unmap_array[unmap_cons + 1]);
210 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
211 prefetch(&unmap_array[unmap_cons + 1]);
212
213 pci_unmap_page(bnad->pcidev,
214 pci_unmap_addr(&unmap_array[unmap_cons],
215 dma_addr),
216 skb_shinfo(skb)->frags[i].size,
217 PCI_DMA_TODEVICE);
218 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
219 0);
220 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
221 }
222 dev_kfree_skb_any(skb);
223 }
224
225 /* Update consumer pointers. */
226 tcb->consumer_index = updated_hw_cons;
227 unmap_q->consumer_index = unmap_cons;
228
229 tcb->txq->tx_packets += sent_packets;
230 tcb->txq->tx_bytes += sent_bytes;
231
232 return sent_packets;
233}
234
235/* Tx Free Tasklet function */
236/* Frees for all the tcb's in all the Tx's */
237/*
238 * Scheduled from sending context, so that
239 * the fat Tx lock is not held for too long
240 * in the sending context.
241 */
242static void
243bnad_tx_free_tasklet(unsigned long bnad_ptr)
244{
245 struct bnad *bnad = (struct bnad *)bnad_ptr;
246 struct bna_tcb *tcb;
f7c0fa4c 247 u32 acked = 0;
8b230ed8
RM		 248 int i, j;
249
250 for (i = 0; i < bnad->num_tx; i++) {
251 for (j = 0; j < bnad->num_txq_per_tx; j++) {
252 tcb = bnad->tx_info[i].tcb[j];
253 if (!tcb)
254 continue;
255 if (((u16) (*tcb->hw_consumer_index) !=
256 tcb->consumer_index) &&
257 (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
258 &tcb->flags))) {
259 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 260 if (likely(test_bit(BNAD_TXQ_TX_STARTED,
261 &tcb->flags)))
262 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 263 smp_mb__before_clear_bit();
264 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
265 }
f7c0fa4c
RM		 266 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
267 &tcb->flags)))
268 continue;
269 if (netif_queue_stopped(bnad->netdev)) {
270 if (acked && netif_carrier_ok(bnad->netdev) &&
271 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
272 BNAD_NETIF_WAKE_THRESHOLD) {
273 netif_wake_queue(bnad->netdev);
274 /* TODO */
275 /* Counters for individual TxQs? */
276 BNAD_UPDATE_CTR(bnad,
277 netif_queue_wakeup);
278 }
279 }
8b230ed8
RM		 280 }
281 }
282}
283
284static u32
285bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
286{
287 struct net_device *netdev = bnad->netdev;
be7fa326 288 u32 sent = 0;
8b230ed8
RM		 289
290 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
291 return 0;
292
293 sent = bnad_free_txbufs(bnad, tcb);
294 if (sent) {
295 if (netif_queue_stopped(netdev) &&
296 netif_carrier_ok(netdev) &&
297 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
298 BNAD_NETIF_WAKE_THRESHOLD) {
be7fa326
RM		 299 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
300 netif_wake_queue(netdev);
301 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
302 }
8b230ed8 303 }
be7fa326
RM		 304 }
305
306 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
8b230ed8 307 bna_ib_ack(tcb->i_dbell, sent);
8b230ed8
RM		 308
309 smp_mb__before_clear_bit();
310 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
311
312 return sent;
313}
314
315/* MSIX Tx Completion Handler */
316static irqreturn_t
317bnad_msix_tx(int irq, void *data)
318{
319 struct bna_tcb *tcb = (struct bna_tcb *)data;
320 struct bnad *bnad = tcb->bnad;
321
322 bnad_tx(bnad, tcb);
323
324 return IRQ_HANDLED;
325}
326
327static void
328bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
329{
330 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
331
332 rcb->producer_index = 0;
333 rcb->consumer_index = 0;
334
335 unmap_q->producer_index = 0;
336 unmap_q->consumer_index = 0;
337}
338
339static void
be7fa326 340bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
8b230ed8
RM		 341{
342 struct bnad_unmap_q *unmap_q;
343 struct sk_buff *skb;
be7fa326 344 int unmap_cons;
8b230ed8
RM		 345
346 unmap_q = rcb->unmap_q;
be7fa326
RM		 347 for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
348 skb = unmap_q->unmap_array[unmap_cons].skb;
349 if (!skb)
350 continue;
be7fa326 351 unmap_q->unmap_array[unmap_cons].skb = NULL;
8b230ed8 352 pci_unmap_single(bnad->pcidev, pci_unmap_addr(&unmap_q->
be7fa326
RM		 353 unmap_array[unmap_cons],
354 dma_addr), rcb->rxq->buffer_size,
355 PCI_DMA_FROMDEVICE);
8b230ed8 356 dev_kfree_skb(skb);
8b230ed8 357 }
8b230ed8
RM		 358 bnad_reset_rcb(bnad, rcb);
359}
360
361static void
362bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
363{
364 u16 to_alloc, alloced, unmap_prod, wi_range;
365 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
366 struct bnad_skb_unmap *unmap_array;
367 struct bna_rxq_entry *rxent;
368 struct sk_buff *skb;
369 dma_addr_t dma_addr;
370
371 alloced = 0;
372 to_alloc =
373 BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
374
375 unmap_array = unmap_q->unmap_array;
376 unmap_prod = unmap_q->producer_index;
377
378 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
379
380 while (to_alloc--) {
381 if (!wi_range) {
382 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
383 wi_range);
384 }
385 skb = alloc_skb(rcb->rxq->buffer_size + NET_IP_ALIGN,
386 GFP_ATOMIC);
387 if (unlikely(!skb)) {
388 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
389 goto finishing;
390 }
391 skb->dev = bnad->netdev;
392 skb_reserve(skb, NET_IP_ALIGN);
393 unmap_array[unmap_prod].skb = skb;
394 dma_addr = pci_map_single(bnad->pcidev, skb->data,
395 rcb->rxq->buffer_size, PCI_DMA_FROMDEVICE);
396 pci_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
397 dma_addr);
398 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
399 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
400
401 rxent++;
402 wi_range--;
403 alloced++;
404 }
405
406finishing:
407 if (likely(alloced)) {
408 unmap_q->producer_index = unmap_prod;
409 rcb->producer_index = unmap_prod;
410 smp_mb();
be7fa326
RM		 411 if (likely(test_bit(BNAD_RXQ_STARTED, &rcb->flags)))
412 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 413 }
8b230ed8
RM		 414}
415
416static inline void
417bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
418{
419 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
420
421 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
422 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
423 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
424 bnad_alloc_n_post_rxbufs(bnad, rcb);
425 smp_mb__before_clear_bit();
426 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
427 }
428}
429
430static u32
431bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
432{
433 struct bna_cq_entry *cmpl, *next_cmpl;
434 struct bna_rcb *rcb = NULL;
435 unsigned int wi_range, packets = 0, wis = 0;
436 struct bnad_unmap_q *unmap_q;
437 struct sk_buff *skb;
438 u32 flags;
439 u32 qid0 = ccb->rcb[0]->rxq->rxq_id;
440 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
441
be7fa326
RM		 442 if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))
443 return 0;
444
8b230ed8
RM		 445 prefetch(bnad->netdev);
446 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
447 wi_range);
448 BUG_ON(!(wi_range <= ccb->q_depth));
449 while (cmpl->valid && packets < budget) {
450 packets++;
451 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
452
453 if (qid0 == cmpl->rxq_id)
454 rcb = ccb->rcb[0];
455 else
456 rcb = ccb->rcb[1];
457
458 unmap_q = rcb->unmap_q;
459
460 skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
461 BUG_ON(!(skb));
462 unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
463 pci_unmap_single(bnad->pcidev,
464 pci_unmap_addr(&unmap_q->
465 unmap_array[unmap_q->
466 consumer_index],
467 dma_addr),
468 rcb->rxq->buffer_size,
469 PCI_DMA_FROMDEVICE);
470 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
471
472 /* Should be more efficient ? Performance ? */
473 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
474
475 wis++;
476 if (likely(--wi_range))
477 next_cmpl = cmpl + 1;
478 else {
479 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
480 wis = 0;
481 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
482 next_cmpl, wi_range);
483 BUG_ON(!(wi_range <= ccb->q_depth));
484 }
485 prefetch(next_cmpl);
486
487 flags = ntohl(cmpl->flags);
488 if (unlikely
489 (flags &
490 (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
491 BNA_CQ_EF_TOO_LONG))) {
492 dev_kfree_skb_any(skb);
493 rcb->rxq->rx_packets_with_error++;
494 goto next;
495 }
496
497 skb_put(skb, ntohs(cmpl->length));
498 if (likely
499 (bnad->rx_csum &&
500 (((flags & BNA_CQ_EF_IPV4) &&
501 (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
502 (flags & BNA_CQ_EF_IPV6)) &&
503 (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
504 (flags & BNA_CQ_EF_L4_CKSUM_OK)))
505 skb->ip_summed = CHECKSUM_UNNECESSARY;
506 else
bc8acf2c 507 skb_checksum_none_assert(skb);
8b230ed8
RM		 508
509 rcb->rxq->rx_packets++;
510 rcb->rxq->rx_bytes += skb->len;
511 skb->protocol = eth_type_trans(skb, bnad->netdev);
512
513 if (bnad->vlan_grp && (flags & BNA_CQ_EF_VLAN)) {
514 struct bnad_rx_ctrl *rx_ctrl =
515 (struct bnad_rx_ctrl *)ccb->ctrl;
516 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
517 vlan_gro_receive(&rx_ctrl->napi, bnad->vlan_grp,
518 ntohs(cmpl->vlan_tag), skb);
519 else
520 vlan_hwaccel_receive_skb(skb,
521 bnad->vlan_grp,
522 ntohs(cmpl->vlan_tag));
523
524 } else { /* Not VLAN tagged/stripped */
525 struct bnad_rx_ctrl *rx_ctrl =
526 (struct bnad_rx_ctrl *)ccb->ctrl;
527 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
528 napi_gro_receive(&rx_ctrl->napi, skb);
529 else
530 netif_receive_skb(skb);
531 }
532
533next:
534 cmpl->valid = 0;
535 cmpl = next_cmpl;
536 }
537
538 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
539
540 if (likely(ccb)) {
be7fa326
RM		 541 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
542 bna_ib_ack(ccb->i_dbell, packets);
8b230ed8
RM		 543 bnad_refill_rxq(bnad, ccb->rcb[0]);
544 if (ccb->rcb[1])
545 bnad_refill_rxq(bnad, ccb->rcb[1]);
be7fa326
RM		 546 } else {
547 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
548 bna_ib_ack(ccb->i_dbell, 0);
549 }
8b230ed8
RM		 550
551 return packets;
552}
553
554static void
555bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
556{
be7fa326
RM		 557 if (unlikely(!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
558 return;
559
8b230ed8
RM		 560 bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
561 bna_ib_ack(ccb->i_dbell, 0);
562}
563
564static void
565bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
566{
e2fa6f2e
RM		 567 unsigned long flags;
568
aad75b66
RM		 569 /* Because of polling context */
570 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 571 bnad_enable_rx_irq_unsafe(ccb);
e2fa6f2e 572 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 573}
574
575static void
576bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
577{
578 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
be7fa326
RM		 579 struct napi_struct *napi = &rx_ctrl->napi;
580
581 if (likely(napi_schedule_prep(napi))) {
8b230ed8 582 bnad_disable_rx_irq(bnad, ccb);
be7fa326 583 __napi_schedule(napi);
8b230ed8
RM		 584 }
585 BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
586}
587
588/* MSIX Rx Path Handler */
589static irqreturn_t
590bnad_msix_rx(int irq, void *data)
591{
592 struct bna_ccb *ccb = (struct bna_ccb *)data;
593 struct bnad *bnad = ccb->bnad;
594
595 bnad_netif_rx_schedule_poll(bnad, ccb);
596
597 return IRQ_HANDLED;
598}
599
600/* Interrupt handlers */
601
602/* Mbox Interrupt Handlers */
603static irqreturn_t
604bnad_msix_mbox_handler(int irq, void *data)
605{
606 u32 intr_status;
e2fa6f2e 607 unsigned long flags;
be7fa326 608 struct bnad *bnad = (struct bnad *)data;
8b230ed8 609
be7fa326
RM		 610 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
611 return IRQ_HANDLED;
8b230ed8 612
8b230ed8
RM		 613 spin_lock_irqsave(&bnad->bna_lock, flags);
614
615 bna_intr_status_get(&bnad->bna, intr_status);
616
617 if (BNA_IS_MBOX_ERR_INTR(intr_status))
618 bna_mbox_handler(&bnad->bna, intr_status);
619
620 spin_unlock_irqrestore(&bnad->bna_lock, flags);
621
8b230ed8
RM		 622 return IRQ_HANDLED;
623}
624
625static irqreturn_t
626bnad_isr(int irq, void *data)
627{
628 int i, j;
629 u32 intr_status;
630 unsigned long flags;
be7fa326 631 struct bnad *bnad = (struct bnad *)data;
8b230ed8
RM		 632 struct bnad_rx_info *rx_info;
633 struct bnad_rx_ctrl *rx_ctrl;
634
e2fa6f2e
RM		 635 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
636 return IRQ_NONE;
8b230ed8
RM		 637
638 bna_intr_status_get(&bnad->bna, intr_status);
e2fa6f2e
RM		 639
640 if (unlikely(!intr_status))
8b230ed8 641 return IRQ_NONE;
e2fa6f2e
RM		 642
643 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 644
be7fa326 645 if (BNA_IS_MBOX_ERR_INTR(intr_status))
8b230ed8 646 bna_mbox_handler(&bnad->bna, intr_status);
be7fa326 647
8b230ed8
RM		 648 spin_unlock_irqrestore(&bnad->bna_lock, flags);
649
be7fa326
RM		 650 if (!BNA_IS_INTX_DATA_INTR(intr_status))
651 return IRQ_HANDLED;
652
8b230ed8 653 /* Process data interrupts */
be7fa326
RM		 654 /* Tx processing */
655 for (i = 0; i < bnad->num_tx; i++) {
656 for (j = 0; j < bnad->num_txq_per_tx; j++)
657 bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
658 }
659 /* Rx processing */
8b230ed8
RM		 660 for (i = 0; i < bnad->num_rx; i++) {
661 rx_info = &bnad->rx_info[i];
662 if (!rx_info->rx)
663 continue;
664 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
665 rx_ctrl = &rx_info->rx_ctrl[j];
666 if (rx_ctrl->ccb)
667 bnad_netif_rx_schedule_poll(bnad,
668 rx_ctrl->ccb);
669 }
670 }
8b230ed8
RM		 671 return IRQ_HANDLED;
672}
673
674/*
675 * Called in interrupt / callback context
676 * with bna_lock held, so cfg_flags access is OK
677 */
678static void
679bnad_enable_mbox_irq(struct bnad *bnad)
680{
be7fa326 681 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
e2fa6f2e 682
8b230ed8
RM		 683 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
684}
685
686/*
687 * Called with bnad->bna_lock held b'cos of
688 * bnad->cfg_flags access.
689 */
b7ee31c5 690static void
8b230ed8
RM		 691bnad_disable_mbox_irq(struct bnad *bnad)
692{
be7fa326 693 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
8b230ed8 694
be7fa326
RM		 695 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
696}
8b230ed8 697
be7fa326
RM		 698static void
699bnad_set_netdev_perm_addr(struct bnad *bnad)
700{
701 struct net_device *netdev = bnad->netdev;
e2fa6f2e 702
be7fa326
RM		 703 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
704 if (is_zero_ether_addr(netdev->dev_addr))
705 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
8b230ed8
RM		 706}
707
708/* Control Path Handlers */
709
710/* Callbacks */
711void
712bnad_cb_device_enable_mbox_intr(struct bnad *bnad)
713{
714 bnad_enable_mbox_irq(bnad);
715}
716
717void
718bnad_cb_device_disable_mbox_intr(struct bnad *bnad)
719{
720 bnad_disable_mbox_irq(bnad);
721}
722
723void
724bnad_cb_device_enabled(struct bnad *bnad, enum bna_cb_status status)
725{
726 complete(&bnad->bnad_completions.ioc_comp);
727 bnad->bnad_completions.ioc_comp_status = status;
728}
729
730void
731bnad_cb_device_disabled(struct bnad *bnad, enum bna_cb_status status)
732{
733 complete(&bnad->bnad_completions.ioc_comp);
734 bnad->bnad_completions.ioc_comp_status = status;
735}
736
737static void
738bnad_cb_port_disabled(void *arg, enum bna_cb_status status)
739{
740 struct bnad *bnad = (struct bnad *)arg;
741
742 complete(&bnad->bnad_completions.port_comp);
743
744 netif_carrier_off(bnad->netdev);
745}
746
747void
748bnad_cb_port_link_status(struct bnad *bnad,
749 enum bna_link_status link_status)
750{
751 bool link_up = 0;
752
753 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
754
755 if (link_status == BNA_CEE_UP) {
756 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
757 BNAD_UPDATE_CTR(bnad, cee_up);
758 } else
759 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
760
761 if (link_up) {
762 if (!netif_carrier_ok(bnad->netdev)) {
be7fa326
RM		 763 struct bna_tcb *tcb = bnad->tx_info[0].tcb[0];
764 if (!tcb)
765 return;
8b230ed8
RM		 766 pr_warn("bna: %s link up\n",
767 bnad->netdev->name);
768 netif_carrier_on(bnad->netdev);
769 BNAD_UPDATE_CTR(bnad, link_toggle);
be7fa326 770 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
8b230ed8
RM		 771 /* Force an immediate Transmit Schedule */
772 pr_info("bna: %s TX_STARTED\n",
773 bnad->netdev->name);
774 netif_wake_queue(bnad->netdev);
775 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
776 } else {
777 netif_stop_queue(bnad->netdev);
778 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
779 }
780 }
781 } else {
782 if (netif_carrier_ok(bnad->netdev)) {
783 pr_warn("bna: %s link down\n",
784 bnad->netdev->name);
785 netif_carrier_off(bnad->netdev);
786 BNAD_UPDATE_CTR(bnad, link_toggle);
787 }
788 }
789}
790
791static void
792bnad_cb_tx_disabled(void *arg, struct bna_tx *tx,
793 enum bna_cb_status status)
794{
795 struct bnad *bnad = (struct bnad *)arg;
796
797 complete(&bnad->bnad_completions.tx_comp);
798}
799
800static void
801bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
802{
803 struct bnad_tx_info *tx_info =
804 (struct bnad_tx_info *)tcb->txq->tx->priv;
805 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
806
807 tx_info->tcb[tcb->id] = tcb;
808 unmap_q->producer_index = 0;
809 unmap_q->consumer_index = 0;
810 unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
811}
812
813static void
814bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
815{
816 struct bnad_tx_info *tx_info =
817 (struct bnad_tx_info *)tcb->txq->tx->priv;
be7fa326
RM		 818 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
819
820 while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
821 cpu_relax();
822
823 bnad_free_all_txbufs(bnad, tcb);
824
825 unmap_q->producer_index = 0;
826 unmap_q->consumer_index = 0;
827
828 smp_mb__before_clear_bit();
829 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
8b230ed8
RM		 830
831 tx_info->tcb[tcb->id] = NULL;
832}
833
834static void
835bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
836{
837 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
838
839 unmap_q->producer_index = 0;
840 unmap_q->consumer_index = 0;
841 unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
842}
843
be7fa326
RM		 844static void
845bnad_cb_rcb_destroy(struct bnad *bnad, struct bna_rcb *rcb)
846{
847 bnad_free_all_rxbufs(bnad, rcb);
848}
849
8b230ed8
RM		 850static void
851bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
852{
853 struct bnad_rx_info *rx_info =
854 (struct bnad_rx_info *)ccb->cq->rx->priv;
855
856 rx_info->rx_ctrl[ccb->id].ccb = ccb;
857 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
858}
859
860static void
861bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
862{
863 struct bnad_rx_info *rx_info =
864 (struct bnad_rx_info *)ccb->cq->rx->priv;
865
866 rx_info->rx_ctrl[ccb->id].ccb = NULL;
867}
868
869static void
870bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb)
871{
872 struct bnad_tx_info *tx_info =
873 (struct bnad_tx_info *)tcb->txq->tx->priv;
874
875 if (tx_info != &bnad->tx_info[0])
876 return;
877
be7fa326 878 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
8b230ed8
RM		 879 netif_stop_queue(bnad->netdev);
880 pr_info("bna: %s TX_STOPPED\n", bnad->netdev->name);
881}
882
883static void
884bnad_cb_tx_resume(struct bnad *bnad, struct bna_tcb *tcb)
885{
be7fa326 886 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
8b230ed8 887
be7fa326 888 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
8b230ed8
RM		 889 return;
890
be7fa326 891 clear_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags);
8b230ed8 892
be7fa326
RM		 893 while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
894 cpu_relax();
8b230ed8
RM		 895
896 bnad_free_all_txbufs(bnad, tcb);
897
898 unmap_q->producer_index = 0;
899 unmap_q->consumer_index = 0;
900
901 smp_mb__before_clear_bit();
902 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
be7fa326
RM		 903
904 /*
905 * Workaround for first device enable failure & we
906 * get a 0 MAC address. We try to get the MAC address
907 * again here.
908 */
909 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
910 bna_port_mac_get(&bnad->bna.port, &bnad->perm_addr);
911 bnad_set_netdev_perm_addr(bnad);
912 }
913
914 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
915
916 if (netif_carrier_ok(bnad->netdev)) {
917 pr_info("bna: %s TX_STARTED\n", bnad->netdev->name);
918 netif_wake_queue(bnad->netdev);
919 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
920 }
921}
922
923static void
924bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
925{
926 /* Delay only once for the whole Tx Path Shutdown */
927 if (!test_and_set_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags))
928 mdelay(BNAD_TXRX_SYNC_MDELAY);
8b230ed8
RM		 929}
930
931static void
932bnad_cb_rx_cleanup(struct bnad *bnad,
933 struct bna_ccb *ccb)
934{
8b230ed8
RM		 935 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
936
be7fa326 937 if (ccb->rcb[1])
8b230ed8 938 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
be7fa326
RM		 939
940 if (!test_and_set_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags))
941 mdelay(BNAD_TXRX_SYNC_MDELAY);
8b230ed8
RM		 942}
943
944static void
945bnad_cb_rx_post(struct bnad *bnad, struct bna_rcb *rcb)
946{
947 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
948
be7fa326
RM		 949 clear_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags);
950
951 if (rcb == rcb->cq->ccb->rcb[0])
952 bnad_cq_cmpl_init(bnad, rcb->cq->ccb);
953
954 bnad_free_all_rxbufs(bnad, rcb);
955
8b230ed8
RM		 956 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
957
958 /* Now allocate & post buffers for this RCB */
959 /* !!Allocation in callback context */
960 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
961 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
962 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
963 bnad_alloc_n_post_rxbufs(bnad, rcb);
964 smp_mb__before_clear_bit();
965 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
966 }
967}
968
969static void
970bnad_cb_rx_disabled(void *arg, struct bna_rx *rx,
971 enum bna_cb_status status)
972{
973 struct bnad *bnad = (struct bnad *)arg;
974
975 complete(&bnad->bnad_completions.rx_comp);
976}
977
978static void
979bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx,
980 enum bna_cb_status status)
981{
982 bnad->bnad_completions.mcast_comp_status = status;
983 complete(&bnad->bnad_completions.mcast_comp);
984}
985
986void
987bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
988 struct bna_stats *stats)
989{
990 if (status == BNA_CB_SUCCESS)
991 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
992
993 if (!netif_running(bnad->netdev) ||
994 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
995 return;
996
997 mod_timer(&bnad->stats_timer,
998 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
999}
1000
8b230ed8
RM		 1001/* Resource allocation, free functions */
1002
1003static void
1004bnad_mem_free(struct bnad *bnad,
1005 struct bna_mem_info *mem_info)
1006{
1007 int i;
1008 dma_addr_t dma_pa;
1009
1010 if (mem_info->mdl == NULL)
1011 return;
1012
1013 for (i = 0; i < mem_info->num; i++) {
1014 if (mem_info->mdl[i].kva != NULL) {
1015 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1016 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1017 dma_pa);
1018 pci_free_consistent(bnad->pcidev,
1019 mem_info->mdl[i].len,
1020 mem_info->mdl[i].kva, dma_pa);
1021 } else
1022 kfree(mem_info->mdl[i].kva);
1023 }
1024 }
1025 kfree(mem_info->mdl);
1026 mem_info->mdl = NULL;
1027}
1028
1029static int
1030bnad_mem_alloc(struct bnad *bnad,
1031 struct bna_mem_info *mem_info)
1032{
1033 int i;
1034 dma_addr_t dma_pa;
1035
1036 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1037 mem_info->mdl = NULL;
1038 return 0;
1039 }
1040
1041 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1042 GFP_KERNEL);
1043 if (mem_info->mdl == NULL)
1044 return -ENOMEM;
1045
1046 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1047 for (i = 0; i < mem_info->num; i++) {
1048 mem_info->mdl[i].len = mem_info->len;
1049 mem_info->mdl[i].kva =
1050 pci_alloc_consistent(bnad->pcidev,
1051 mem_info->len, &dma_pa);
1052
1053 if (mem_info->mdl[i].kva == NULL)
1054 goto err_return;
1055
1056 BNA_SET_DMA_ADDR(dma_pa,
1057 &(mem_info->mdl[i].dma));
1058 }
1059 } else {
1060 for (i = 0; i < mem_info->num; i++) {
1061 mem_info->mdl[i].len = mem_info->len;
1062 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1063 GFP_KERNEL);
1064 if (mem_info->mdl[i].kva == NULL)
1065 goto err_return;
1066 }
1067 }
1068
1069 return 0;
1070
1071err_return:
1072 bnad_mem_free(bnad, mem_info);
1073 return -ENOMEM;
1074}
1075
1076/* Free IRQ for Mailbox */
1077static void
1078bnad_mbox_irq_free(struct bnad *bnad,
1079 struct bna_intr_info *intr_info)
1080{
1081 int irq;
1082 unsigned long flags;
1083
1084 if (intr_info->idl == NULL)
1085 return;
1086
1087 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 1088 bnad_disable_mbox_irq(bnad);
e2fa6f2e 1089 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1090
1091 irq = BNAD_GET_MBOX_IRQ(bnad);
be7fa326 1092 free_irq(irq, bnad);
8b230ed8 1093
8b230ed8
RM		 1094 kfree(intr_info->idl);
1095}
1096
1097/*
1098 * Allocates IRQ for Mailbox, but keep it disabled
1099 * This will be enabled once we get the mbox enable callback
1100 * from bna
1101 */
1102static int
1103bnad_mbox_irq_alloc(struct bnad *bnad,
1104 struct bna_intr_info *intr_info)
1105{
be7fa326 1106 int err = 0;
8b230ed8
RM		 1107 unsigned long flags;
1108 u32 irq;
1109 irq_handler_t irq_handler;
1110
1111 /* Mbox should use only 1 vector */
1112
1113 intr_info->idl = kzalloc(sizeof(*(intr_info->idl)), GFP_KERNEL);
1114 if (!intr_info->idl)
1115 return -ENOMEM;
1116
1117 spin_lock_irqsave(&bnad->bna_lock, flags);
1118 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1119 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1120 irq = bnad->msix_table[bnad->msix_num - 1].vector;
1121 flags = 0;
1122 intr_info->intr_type = BNA_INTR_T_MSIX;
1123 intr_info->idl[0].vector = bnad->msix_num - 1;
1124 } else {
1125 irq_handler = (irq_handler_t)bnad_isr;
1126 irq = bnad->pcidev->irq;
1127 flags = IRQF_SHARED;
1128 intr_info->intr_type = BNA_INTR_T_INTX;
1129 /* intr_info->idl.vector = 0 ? */
1130 }
1131 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1132
1133 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1134
e2fa6f2e
RM		 1135 /*
1136 * Set the Mbox IRQ disable flag, so that the IRQ handler
1137 * called from request_irq() for SHARED IRQs do not execute
1138 */
1139 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1140
be7fa326
RM		 1141 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1142
8b230ed8 1143 err = request_irq(irq, irq_handler, flags,
be7fa326 1144 bnad->mbox_irq_name, bnad);
e2fa6f2e 1145
8b230ed8
RM		 1146 if (err) {
1147 kfree(intr_info->idl);
1148 intr_info->idl = NULL;
8b230ed8
RM		 1149 }
1150
be7fa326 1151 return err;
8b230ed8
RM		 1152}
1153
1154static void
1155bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1156{
1157 kfree(intr_info->idl);
1158 intr_info->idl = NULL;
1159}
1160
1161/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1162static int
1163bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1164 uint txrx_id, struct bna_intr_info *intr_info)
1165{
1166 int i, vector_start = 0;
1167 u32 cfg_flags;
1168 unsigned long flags;
1169
1170 spin_lock_irqsave(&bnad->bna_lock, flags);
1171 cfg_flags = bnad->cfg_flags;
1172 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1173
1174 if (cfg_flags & BNAD_CF_MSIX) {
1175 intr_info->intr_type = BNA_INTR_T_MSIX;
1176 intr_info->idl = kcalloc(intr_info->num,
1177 sizeof(struct bna_intr_descr),
1178 GFP_KERNEL);
1179 if (!intr_info->idl)
1180 return -ENOMEM;
1181
1182 switch (src) {
1183 case BNAD_INTR_TX:
1184 vector_start = txrx_id;
1185 break;
1186
1187 case BNAD_INTR_RX:
1188 vector_start = bnad->num_tx * bnad->num_txq_per_tx +
1189 txrx_id;
1190 break;
1191
1192 default:
1193 BUG();
1194 }
1195
1196 for (i = 0; i < intr_info->num; i++)
1197 intr_info->idl[i].vector = vector_start + i;
1198 } else {
1199 intr_info->intr_type = BNA_INTR_T_INTX;
1200 intr_info->num = 1;
1201 intr_info->idl = kcalloc(intr_info->num,
1202 sizeof(struct bna_intr_descr),
1203 GFP_KERNEL);
1204 if (!intr_info->idl)
1205 return -ENOMEM;
1206
1207 switch (src) {
1208 case BNAD_INTR_TX:
1209 intr_info->idl[0].vector = 0x1; /* Bit mask : Tx IB */
1210 break;
1211
1212 case BNAD_INTR_RX:
1213 intr_info->idl[0].vector = 0x2; /* Bit mask : Rx IB */
1214 break;
1215 }
1216 }
1217 return 0;
1218}
1219
1220/**
1221 * NOTE: Should be called for MSIX only
1222 * Unregisters Tx MSIX vector(s) from the kernel
1223 */
1224static void
1225bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1226 int num_txqs)
1227{
1228 int i;
1229 int vector_num;
1230
1231 for (i = 0; i < num_txqs; i++) {
1232 if (tx_info->tcb[i] == NULL)
1233 continue;
1234
1235 vector_num = tx_info->tcb[i]->intr_vector;
1236 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1237 }
1238}
1239
1240/**
1241 * NOTE: Should be called for MSIX only
1242 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1243 */
1244static int
1245bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1246 uint tx_id, int num_txqs)
1247{
1248 int i;
1249 int err;
1250 int vector_num;
1251
1252 for (i = 0; i < num_txqs; i++) {
1253 vector_num = tx_info->tcb[i]->intr_vector;
1254 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1255 tx_id + tx_info->tcb[i]->id);
1256 err = request_irq(bnad->msix_table[vector_num].vector,
1257 (irq_handler_t)bnad_msix_tx, 0,
1258 tx_info->tcb[i]->name,
1259 tx_info->tcb[i]);
1260 if (err)
1261 goto err_return;
1262 }
1263
1264 return 0;
1265
1266err_return:
1267 if (i > 0)
1268 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1269 return -1;
1270}
1271
1272/**
1273 * NOTE: Should be called for MSIX only
1274 * Unregisters Rx MSIX vector(s) from the kernel
1275 */
1276static void
1277bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1278 int num_rxps)
1279{
1280 int i;
1281 int vector_num;
1282
1283 for (i = 0; i < num_rxps; i++) {
1284 if (rx_info->rx_ctrl[i].ccb == NULL)
1285 continue;
1286
1287 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1288 free_irq(bnad->msix_table[vector_num].vector,
1289 rx_info->rx_ctrl[i].ccb);
1290 }
1291}
1292
1293/**
1294 * NOTE: Should be called for MSIX only
1295 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1296 */
1297static int
1298bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1299 uint rx_id, int num_rxps)
1300{
1301 int i;
1302 int err;
1303 int vector_num;
1304
1305 for (i = 0; i < num_rxps; i++) {
1306 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1307 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1308 bnad->netdev->name,
1309 rx_id + rx_info->rx_ctrl[i].ccb->id);
1310 err = request_irq(bnad->msix_table[vector_num].vector,
1311 (irq_handler_t)bnad_msix_rx, 0,
1312 rx_info->rx_ctrl[i].ccb->name,
1313 rx_info->rx_ctrl[i].ccb);
1314 if (err)
1315 goto err_return;
1316 }
1317
1318 return 0;
1319
1320err_return:
1321 if (i > 0)
1322 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1323 return -1;
1324}
1325
1326/* Free Tx object Resources */
1327static void
1328bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1329{
1330 int i;
1331
1332 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1333 if (res_info[i].res_type == BNA_RES_T_MEM)
1334 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1335 else if (res_info[i].res_type == BNA_RES_T_INTR)
1336 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1337 }
1338}
1339
1340/* Allocates memory and interrupt resources for Tx object */
1341static int
1342bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1343 uint tx_id)
1344{
1345 int i, err = 0;
1346
1347 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1348 if (res_info[i].res_type == BNA_RES_T_MEM)
1349 err = bnad_mem_alloc(bnad,
1350 &res_info[i].res_u.mem_info);
1351 else if (res_info[i].res_type == BNA_RES_T_INTR)
1352 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1353 &res_info[i].res_u.intr_info);
1354 if (err)
1355 goto err_return;
1356 }
1357 return 0;
1358
1359err_return:
1360 bnad_tx_res_free(bnad, res_info);
1361 return err;
1362}
1363
1364/* Free Rx object Resources */
1365static void
1366bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1367{
1368 int i;
1369
1370 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1371 if (res_info[i].res_type == BNA_RES_T_MEM)
1372 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1373 else if (res_info[i].res_type == BNA_RES_T_INTR)
1374 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1375 }
1376}
1377
1378/* Allocates memory and interrupt resources for Rx object */
1379static int
1380bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1381 uint rx_id)
1382{
1383 int i, err = 0;
1384
1385 /* All memory needs to be allocated before setup_ccbs */
1386 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1387 if (res_info[i].res_type == BNA_RES_T_MEM)
1388 err = bnad_mem_alloc(bnad,
1389 &res_info[i].res_u.mem_info);
1390 else if (res_info[i].res_type == BNA_RES_T_INTR)
1391 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1392 &res_info[i].res_u.intr_info);
1393 if (err)
1394 goto err_return;
1395 }
1396 return 0;
1397
1398err_return:
1399 bnad_rx_res_free(bnad, res_info);
1400 return err;
1401}
1402
1403/* Timer callbacks */
1404/* a) IOC timer */
1405static void
1406bnad_ioc_timeout(unsigned long data)
1407{
1408 struct bnad *bnad = (struct bnad *)data;
1409 unsigned long flags;
1410
1411 spin_lock_irqsave(&bnad->bna_lock, flags);
8a891429 1412 bfa_nw_ioc_timeout((void *) &bnad->bna.device.ioc);
8b230ed8
RM		 1413 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1414}
1415
1416static void
1417bnad_ioc_hb_check(unsigned long data)
1418{
1419 struct bnad *bnad = (struct bnad *)data;
1420 unsigned long flags;
1421
1422 spin_lock_irqsave(&bnad->bna_lock, flags);
8a891429 1423 bfa_nw_ioc_hb_check((void *) &bnad->bna.device.ioc);
8b230ed8
RM		 1424 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1425}
1426
1427static void
1428bnad_ioc_sem_timeout(unsigned long data)
1429{
1430 struct bnad *bnad = (struct bnad *)data;
1431 unsigned long flags;
1432
1433 spin_lock_irqsave(&bnad->bna_lock, flags);
8a891429 1434 bfa_nw_ioc_sem_timeout((void *) &bnad->bna.device.ioc);
8b230ed8
RM		 1435 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1436}
1437
1438/*
1439 * All timer routines use bnad->bna_lock to protect against
1440 * the following race, which may occur in case of no locking:
1441 * Time CPU m CPU n
1442 * 0 1 = test_bit
1443 * 1 clear_bit
1444 * 2 del_timer_sync
1445 * 3 mod_timer
1446 */
1447
1448/* b) Dynamic Interrupt Moderation Timer */
1449static void
1450bnad_dim_timeout(unsigned long data)
1451{
1452 struct bnad *bnad = (struct bnad *)data;
1453 struct bnad_rx_info *rx_info;
1454 struct bnad_rx_ctrl *rx_ctrl;
1455 int i, j;
1456 unsigned long flags;
1457
1458 if (!netif_carrier_ok(bnad->netdev))
1459 return;
1460
1461 spin_lock_irqsave(&bnad->bna_lock, flags);
1462 for (i = 0; i < bnad->num_rx; i++) {
1463 rx_info = &bnad->rx_info[i];
1464 if (!rx_info->rx)
1465 continue;
1466 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1467 rx_ctrl = &rx_info->rx_ctrl[j];
1468 if (!rx_ctrl->ccb)
1469 continue;
1470 bna_rx_dim_update(rx_ctrl->ccb);
1471 }
1472 }
1473
1474 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1475 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1476 mod_timer(&bnad->dim_timer,
1477 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1478 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1479}
1480
1481/* c) Statistics Timer */
1482static void
1483bnad_stats_timeout(unsigned long data)
1484{
1485 struct bnad *bnad = (struct bnad *)data;
1486 unsigned long flags;
1487
1488 if (!netif_running(bnad->netdev) ||
1489 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1490 return;
1491
1492 spin_lock_irqsave(&bnad->bna_lock, flags);
1493 bna_stats_get(&bnad->bna);
1494 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1495}
1496
1497/*
1498 * Set up timer for DIM
1499 * Called with bnad->bna_lock held
1500 */
1501void
1502bnad_dim_timer_start(struct bnad *bnad)
1503{
1504 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1505 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1506 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1507 (unsigned long)bnad);
1508 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1509 mod_timer(&bnad->dim_timer,
1510 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1511 }
1512}
1513
1514/*
1515 * Set up timer for statistics
1516 * Called with mutex_lock(&bnad->conf_mutex) held
1517 */
1518static void
1519bnad_stats_timer_start(struct bnad *bnad)
1520{
1521 unsigned long flags;
1522
1523 spin_lock_irqsave(&bnad->bna_lock, flags);
1524 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1525 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1526 (unsigned long)bnad);
1527 mod_timer(&bnad->stats_timer,
1528 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1529 }
1530 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1531}
1532
1533/*
1534 * Stops the stats timer
1535 * Called with mutex_lock(&bnad->conf_mutex) held
1536 */
1537static void
1538bnad_stats_timer_stop(struct bnad *bnad)
1539{
1540 int to_del = 0;
1541 unsigned long flags;
1542
1543 spin_lock_irqsave(&bnad->bna_lock, flags);
1544 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1545 to_del = 1;
1546 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1547 if (to_del)
1548 del_timer_sync(&bnad->stats_timer);
1549}
1550
1551/* Utilities */
1552
1553static void
1554bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1555{
1556 int i = 1; /* Index 0 has broadcast address */
1557 struct netdev_hw_addr *mc_addr;
1558
1559 netdev_for_each_mc_addr(mc_addr, netdev) {
1560 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1561 ETH_ALEN);
1562 i++;
1563 }
1564}
1565
1566static int
1567bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1568{
1569 struct bnad_rx_ctrl *rx_ctrl =
1570 container_of(napi, struct bnad_rx_ctrl, napi);
1571 struct bna_ccb *ccb;
1572 struct bnad *bnad;
1573 int rcvd = 0;
1574
1575 ccb = rx_ctrl->ccb;
1576
1577 bnad = ccb->bnad;
1578
1579 if (!netif_carrier_ok(bnad->netdev))
1580 goto poll_exit;
1581
1582 rcvd = bnad_poll_cq(bnad, ccb, budget);
1583 if (rcvd == budget)
1584 return rcvd;
1585
1586poll_exit:
1587 napi_complete((napi));
1588
1589 BNAD_UPDATE_CTR(bnad, netif_rx_complete);
1590
1591 bnad_enable_rx_irq(bnad, ccb);
1592 return rcvd;
1593}
1594
8b230ed8
RM		 1595static void
1596bnad_napi_enable(struct bnad *bnad, u32 rx_id)
1597{
8b230ed8
RM		 1598 struct bnad_rx_ctrl *rx_ctrl;
1599 int i;
8b230ed8
RM		 1600
1601 /* Initialize & enable NAPI */
1602 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1603 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
be7fa326 1604
8b230ed8 1605 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
be7fa326
RM		 1606 bnad_napi_poll_rx, 64);
1607
8b230ed8
RM		 1608 napi_enable(&rx_ctrl->napi);
1609 }
1610}
1611
1612static void
1613bnad_napi_disable(struct bnad *bnad, u32 rx_id)
1614{
1615 int i;
1616
1617 /* First disable and then clean up */
1618 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1619 napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1620 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1621 }
1622}
1623
1624/* Should be held with conf_lock held */
1625void
1626bnad_cleanup_tx(struct bnad *bnad, uint tx_id)
1627{
1628 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1629 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1630 unsigned long flags;
1631
1632 if (!tx_info->tx)
1633 return;
1634
1635 init_completion(&bnad->bnad_completions.tx_comp);
1636 spin_lock_irqsave(&bnad->bna_lock, flags);
1637 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1638 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1639 wait_for_completion(&bnad->bnad_completions.tx_comp);
1640
1641 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1642 bnad_tx_msix_unregister(bnad, tx_info,
1643 bnad->num_txq_per_tx);
1644
1645 spin_lock_irqsave(&bnad->bna_lock, flags);
1646 bna_tx_destroy(tx_info->tx);
1647 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1648
1649 tx_info->tx = NULL;
1650
1651 if (0 == tx_id)
1652 tasklet_kill(&bnad->tx_free_tasklet);
1653
1654 bnad_tx_res_free(bnad, res_info);
1655}
1656
1657/* Should be held with conf_lock held */
1658int
1659bnad_setup_tx(struct bnad *bnad, uint tx_id)
1660{
1661 int err;
1662 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1663 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1664 struct bna_intr_info *intr_info =
1665 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1666 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1667 struct bna_tx_event_cbfn tx_cbfn;
1668 struct bna_tx *tx;
1669 unsigned long flags;
1670
1671 /* Initialize the Tx object configuration */
1672 tx_config->num_txq = bnad->num_txq_per_tx;
1673 tx_config->txq_depth = bnad->txq_depth;
1674 tx_config->tx_type = BNA_TX_T_REGULAR;
1675
1676 /* Initialize the tx event handlers */
1677 tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup;
1678 tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy;
1679 tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall;
1680 tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume;
1681 tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup;
1682
1683 /* Get BNA's resource requirement for one tx object */
1684 spin_lock_irqsave(&bnad->bna_lock, flags);
1685 bna_tx_res_req(bnad->num_txq_per_tx,
1686 bnad->txq_depth, res_info);
1687 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1688
1689 /* Fill Unmap Q memory requirements */
1690 BNAD_FILL_UNMAPQ_MEM_REQ(
1691 &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1692 bnad->num_txq_per_tx,
1693 BNAD_TX_UNMAPQ_DEPTH);
1694
1695 /* Allocate resources */
1696 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1697 if (err)
1698 return err;
1699
1700 /* Ask BNA to create one Tx object, supplying required resources */
1701 spin_lock_irqsave(&bnad->bna_lock, flags);
1702 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1703 tx_info);
1704 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1705 if (!tx)
1706 goto err_return;
1707 tx_info->tx = tx;
1708
1709 /* Register ISR for the Tx object */
1710 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1711 err = bnad_tx_msix_register(bnad, tx_info,
1712 tx_id, bnad->num_txq_per_tx);
1713 if (err)
1714 goto err_return;
1715 }
1716
1717 spin_lock_irqsave(&bnad->bna_lock, flags);
1718 bna_tx_enable(tx);
1719 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1720
1721 return 0;
1722
1723err_return:
1724 bnad_tx_res_free(bnad, res_info);
1725 return err;
1726}
1727
1728/* Setup the rx config for bna_rx_create */
1729/* bnad decides the configuration */
1730static void
1731bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
1732{
1733 rx_config->rx_type = BNA_RX_T_REGULAR;
1734 rx_config->num_paths = bnad->num_rxp_per_rx;
1735
1736 if (bnad->num_rxp_per_rx > 1) {
1737 rx_config->rss_status = BNA_STATUS_T_ENABLED;
1738 rx_config->rss_config.hash_type =
1739 (BFI_RSS_T_V4_TCP |
1740 BFI_RSS_T_V6_TCP |
1741 BFI_RSS_T_V4_IP |
1742 BFI_RSS_T_V6_IP);
1743 rx_config->rss_config.hash_mask =
1744 bnad->num_rxp_per_rx - 1;
1745 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
1746 sizeof(rx_config->rss_config.toeplitz_hash_key));
1747 } else {
1748 rx_config->rss_status = BNA_STATUS_T_DISABLED;
1749 memset(&rx_config->rss_config, 0,
1750 sizeof(rx_config->rss_config));
1751 }
1752 rx_config->rxp_type = BNA_RXP_SLR;
1753 rx_config->q_depth = bnad->rxq_depth;
1754
1755 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
1756
1757 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
1758}
1759
1760/* Called with mutex_lock(&bnad->conf_mutex) held */
1761void
1762bnad_cleanup_rx(struct bnad *bnad, uint rx_id)
1763{
1764 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1765 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1766 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1767 unsigned long flags;
1768 int dim_timer_del = 0;
1769
1770 if (!rx_info->rx)
1771 return;
1772
1773 if (0 == rx_id) {
1774 spin_lock_irqsave(&bnad->bna_lock, flags);
1775 dim_timer_del = bnad_dim_timer_running(bnad);
1776 if (dim_timer_del)
1777 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1778 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1779 if (dim_timer_del)
1780 del_timer_sync(&bnad->dim_timer);
1781 }
1782
1783 bnad_napi_disable(bnad, rx_id);
1784
1785 init_completion(&bnad->bnad_completions.rx_comp);
1786 spin_lock_irqsave(&bnad->bna_lock, flags);
1787 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
1788 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1789 wait_for_completion(&bnad->bnad_completions.rx_comp);
1790
1791 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
1792 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
1793
1794 spin_lock_irqsave(&bnad->bna_lock, flags);
1795 bna_rx_destroy(rx_info->rx);
1796 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1797
1798 rx_info->rx = NULL;
1799
1800 bnad_rx_res_free(bnad, res_info);
1801}
1802
1803/* Called with mutex_lock(&bnad->conf_mutex) held */
1804int
1805bnad_setup_rx(struct bnad *bnad, uint rx_id)
1806{
1807 int err;
1808 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1809 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1810 struct bna_intr_info *intr_info =
1811 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
1812 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1813 struct bna_rx_event_cbfn rx_cbfn;
1814 struct bna_rx *rx;
1815 unsigned long flags;
1816
1817 /* Initialize the Rx object configuration */
1818 bnad_init_rx_config(bnad, rx_config);
1819
1820 /* Initialize the Rx event handlers */
1821 rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
be7fa326 1822 rx_cbfn.rcb_destroy_cbfn = bnad_cb_rcb_destroy;
8b230ed8
RM		 1823 rx_cbfn.rcb_destroy_cbfn = NULL;
1824 rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
1825 rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
1826 rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup;
1827 rx_cbfn.rx_post_cbfn = bnad_cb_rx_post;
1828
1829 /* Get BNA's resource requirement for one Rx object */
1830 spin_lock_irqsave(&bnad->bna_lock, flags);
1831 bna_rx_res_req(rx_config, res_info);
1832 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1833
1834 /* Fill Unmap Q memory requirements */
1835 BNAD_FILL_UNMAPQ_MEM_REQ(
1836 &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
1837 rx_config->num_paths +
1838 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
1839 rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
1840
1841 /* Allocate resource */
1842 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
1843 if (err)
1844 return err;
1845
1846 /* Ask BNA to create one Rx object, supplying required resources */
1847 spin_lock_irqsave(&bnad->bna_lock, flags);
1848 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
1849 rx_info);
1850 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1851 if (!rx)
1852 goto err_return;
1853 rx_info->rx = rx;
1854
1855 /* Register ISR for the Rx object */
1856 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1857 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
1858 rx_config->num_paths);
1859 if (err)
1860 goto err_return;
1861 }
1862
1863 /* Enable NAPI */
1864 bnad_napi_enable(bnad, rx_id);
1865
1866 spin_lock_irqsave(&bnad->bna_lock, flags);
1867 if (0 == rx_id) {
1868 /* Set up Dynamic Interrupt Moderation Vector */
1869 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
1870 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
1871
1872 /* Enable VLAN filtering only on the default Rx */
1873 bna_rx_vlanfilter_enable(rx);
1874
1875 /* Start the DIM timer */
1876 bnad_dim_timer_start(bnad);
1877 }
1878
1879 bna_rx_enable(rx);
1880 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1881
1882 return 0;
1883
1884err_return:
1885 bnad_cleanup_rx(bnad, rx_id);
1886 return err;
1887}
1888
1889/* Called with conf_lock & bnad->bna_lock held */
1890void
1891bnad_tx_coalescing_timeo_set(struct bnad *bnad)
1892{
1893 struct bnad_tx_info *tx_info;
1894
1895 tx_info = &bnad->tx_info[0];
1896 if (!tx_info->tx)
1897 return;
1898
1899 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
1900}
1901
1902/* Called with conf_lock & bnad->bna_lock held */
1903void
1904bnad_rx_coalescing_timeo_set(struct bnad *bnad)
1905{
1906 struct bnad_rx_info *rx_info;
1907 int i;
1908
1909 for (i = 0; i < bnad->num_rx; i++) {
1910 rx_info = &bnad->rx_info[i];
1911 if (!rx_info->rx)
1912 continue;
1913 bna_rx_coalescing_timeo_set(rx_info->rx,
1914 bnad->rx_coalescing_timeo);
1915 }
1916}
1917
1918/*
1919 * Called with bnad->bna_lock held
1920 */
1921static int
1922bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
1923{
1924 int ret;
1925
1926 if (!is_valid_ether_addr(mac_addr))
1927 return -EADDRNOTAVAIL;
1928
1929 /* If datapath is down, pretend everything went through */
1930 if (!bnad->rx_info[0].rx)
1931 return 0;
1932
1933 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
1934 if (ret != BNA_CB_SUCCESS)
1935 return -EADDRNOTAVAIL;
1936
1937 return 0;
1938}
1939
1940/* Should be called with conf_lock held */
1941static int
1942bnad_enable_default_bcast(struct bnad *bnad)
1943{
1944 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
1945 int ret;
1946 unsigned long flags;
1947
1948 init_completion(&bnad->bnad_completions.mcast_comp);
1949
1950 spin_lock_irqsave(&bnad->bna_lock, flags);
1951 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
1952 bnad_cb_rx_mcast_add);
1953 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1954
1955 if (ret == BNA_CB_SUCCESS)
1956 wait_for_completion(&bnad->bnad_completions.mcast_comp);
1957 else
1958 return -ENODEV;
1959
1960 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
1961 return -ENODEV;
1962
1963 return 0;
1964}
1965
aad75b66
RM		 1966/* Called with bnad_conf_lock() held */
1967static void
1968bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
1969{
1970 u16 vlan_id;
1971 unsigned long flags;
1972
1973 if (!bnad->vlan_grp)
1974 return;
1975
1976 BUG_ON(!(VLAN_N_VID == (BFI_MAX_VLAN + 1)));
1977
1978 for (vlan_id = 0; vlan_id < VLAN_N_VID; vlan_id++) {
1979 if (!vlan_group_get_device(bnad->vlan_grp, vlan_id))
1980 continue;
1981 spin_lock_irqsave(&bnad->bna_lock, flags);
1982 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vlan_id);
1983 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1984 }
1985}
1986
8b230ed8
RM		 1987/* Statistics utilities */
1988void
250e061e 1989bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 1990{
8b230ed8
RM		 1991 int i, j;
1992
1993 for (i = 0; i < bnad->num_rx; i++) {
1994 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1995 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
250e061e 1996 stats->rx_packets += bnad->rx_info[i].
8b230ed8 1997 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
250e061e 1998 stats->rx_bytes += bnad->rx_info[i].
8b230ed8
RM		 1999 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2000 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2001 bnad->rx_info[i].rx_ctrl[j].ccb->
2002 rcb[1]->rxq) {
250e061e 2003 stats->rx_packets +=
8b230ed8
RM		 2004 bnad->rx_info[i].rx_ctrl[j].
2005 ccb->rcb[1]->rxq->rx_packets;
250e061e 2006 stats->rx_bytes +=
8b230ed8
RM		 2007 bnad->rx_info[i].rx_ctrl[j].
2008 ccb->rcb[1]->rxq->rx_bytes;
2009 }
2010 }
2011 }
2012 }
2013 for (i = 0; i < bnad->num_tx; i++) {
2014 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2015 if (bnad->tx_info[i].tcb[j]) {
250e061e 2016 stats->tx_packets +=
8b230ed8 2017 bnad->tx_info[i].tcb[j]->txq->tx_packets;
250e061e 2018 stats->tx_bytes +=
8b230ed8
RM		 2019 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2020 }
2021 }
2022 }
2023}
2024
2025/*
2026 * Must be called with the bna_lock held.
2027 */
2028void
250e061e 2029bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8
RM		 2030{
2031 struct bfi_ll_stats_mac *mac_stats;
8b230ed8
RM		 2032 u64 bmap;
2033 int i;
2034
2035 mac_stats = &bnad->stats.bna_stats->hw_stats->mac_stats;
250e061e 2036 stats->rx_errors =
8b230ed8
RM		 2037 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2038 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2039 mac_stats->rx_undersize;
250e061e 2040 stats->tx_errors = mac_stats->tx_fcs_error +
8b230ed8 2041 mac_stats->tx_undersize;
250e061e
ED		 2042 stats->rx_dropped = mac_stats->rx_drop;
2043 stats->tx_dropped = mac_stats->tx_drop;
2044 stats->multicast = mac_stats->rx_multicast;
2045 stats->collisions = mac_stats->tx_total_collision;
8b230ed8 2046
250e061e 2047 stats->rx_length_errors = mac_stats->rx_frame_length_error;
8b230ed8
RM		 2048
2049 /* receive ring buffer overflow ?? */
2050
250e061e
ED		 2051 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2052 stats->rx_frame_errors = mac_stats->rx_alignment_error;
8b230ed8
RM		 2053 /* recv'r fifo overrun */
2054 bmap = (u64)bnad->stats.bna_stats->rxf_bmap[0] |
2055 ((u64)bnad->stats.bna_stats->rxf_bmap[1] << 32);
2056 for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
2057 if (bmap & 1) {
250e061e 2058 stats->rx_fifo_errors +=
8b230ed8
RM		 2059 bnad->stats.bna_stats->
2060 hw_stats->rxf_stats[i].frame_drops;
2061 break;
2062 }
2063 bmap >>= 1;
2064 }
2065}
2066
2067static void
2068bnad_mbox_irq_sync(struct bnad *bnad)
2069{
2070 u32 irq;
2071 unsigned long flags;
2072
2073 spin_lock_irqsave(&bnad->bna_lock, flags);
2074 if (bnad->cfg_flags & BNAD_CF_MSIX)
2075 irq = bnad->msix_table[bnad->msix_num - 1].vector;
2076 else
2077 irq = bnad->pcidev->irq;
2078 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2079
2080 synchronize_irq(irq);
2081}
2082
2083/* Utility used by bnad_start_xmit, for doing TSO */
2084static int
2085bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2086{
2087 int err;
2088
2089 /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */
2090 BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
2091 skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6));
2092 if (skb_header_cloned(skb)) {
2093 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2094 if (err) {
2095 BNAD_UPDATE_CTR(bnad, tso_err);
2096 return err;
2097 }
2098 }
2099
2100 /*
2101 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2102 * excluding the length field.
2103 */
2104 if (skb->protocol == htons(ETH_P_IP)) {
2105 struct iphdr *iph = ip_hdr(skb);
2106
2107 /* Do we really need these? */
2108 iph->tot_len = 0;
2109 iph->check = 0;
2110
2111 tcp_hdr(skb)->check =
2112 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2113 IPPROTO_TCP, 0);
2114 BNAD_UPDATE_CTR(bnad, tso4);
2115 } else {
2116 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2117
2118 BUG_ON(!(skb->protocol == htons(ETH_P_IPV6)));
2119 ipv6h->payload_len = 0;
2120 tcp_hdr(skb)->check =
2121 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2122 IPPROTO_TCP, 0);
2123 BNAD_UPDATE_CTR(bnad, tso6);
2124 }
2125
2126 return 0;
2127}
2128
2129/*
2130 * Initialize Q numbers depending on Rx Paths
2131 * Called with bnad->bna_lock held, because of cfg_flags
2132 * access.
2133 */
2134static void
2135bnad_q_num_init(struct bnad *bnad)
2136{
2137 int rxps;
2138
2139 rxps = min((uint)num_online_cpus(),
2140 (uint)(BNAD_MAX_RXS * BNAD_MAX_RXPS_PER_RX));
2141
2142 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2143 rxps = 1; /* INTx */
2144
2145 bnad->num_rx = 1;
2146 bnad->num_tx = 1;
2147 bnad->num_rxp_per_rx = rxps;
2148 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2149}
2150
2151/*
2152 * Adjusts the Q numbers, given a number of msix vectors
2153 * Give preference to RSS as opposed to Tx priority Queues,
2154 * in such a case, just use 1 Tx Q
2155 * Called with bnad->bna_lock held b'cos of cfg_flags access
2156 */
2157static void
2158bnad_q_num_adjust(struct bnad *bnad, int msix_vectors)
2159{
2160 bnad->num_txq_per_tx = 1;
2161 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2162 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2163 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2164 bnad->num_rxp_per_rx = msix_vectors -
2165 (bnad->num_tx * bnad->num_txq_per_tx) -
2166 BNAD_MAILBOX_MSIX_VECTORS;
2167 } else
2168 bnad->num_rxp_per_rx = 1;
2169}
2170
8b230ed8
RM		 2171/* Enable / disable device */
2172static void
2173bnad_device_disable(struct bnad *bnad)
2174{
2175 unsigned long flags;
2176
2177 init_completion(&bnad->bnad_completions.ioc_comp);
2178
2179 spin_lock_irqsave(&bnad->bna_lock, flags);
2180 bna_device_disable(&bnad->bna.device, BNA_HARD_CLEANUP);
2181 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2182
2183 wait_for_completion(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 2184}
2185
2186static int
2187bnad_device_enable(struct bnad *bnad)
2188{
2189 int err = 0;
2190 unsigned long flags;
2191
2192 init_completion(&bnad->bnad_completions.ioc_comp);
2193
2194 spin_lock_irqsave(&bnad->bna_lock, flags);
2195 bna_device_enable(&bnad->bna.device);
2196 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2197
2198 wait_for_completion(&bnad->bnad_completions.ioc_comp);
2199
2200 if (bnad->bnad_completions.ioc_comp_status)
2201 err = bnad->bnad_completions.ioc_comp_status;
2202
2203 return err;
2204}
2205
2206/* Free BNA resources */
2207static void
2208bnad_res_free(struct bnad *bnad)
2209{
2210 int i;
2211 struct bna_res_info *res_info = &bnad->res_info[0];
2212
2213 for (i = 0; i < BNA_RES_T_MAX; i++) {
2214 if (res_info[i].res_type == BNA_RES_T_MEM)
2215 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2216 else
2217 bnad_mbox_irq_free(bnad, &res_info[i].res_u.intr_info);
2218 }
2219}
2220
2221/* Allocates memory and interrupt resources for BNA */
2222static int
2223bnad_res_alloc(struct bnad *bnad)
2224{
2225 int i, err;
2226 struct bna_res_info *res_info = &bnad->res_info[0];
2227
2228 for (i = 0; i < BNA_RES_T_MAX; i++) {
2229 if (res_info[i].res_type == BNA_RES_T_MEM)
2230 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2231 else
2232 err = bnad_mbox_irq_alloc(bnad,
2233 &res_info[i].res_u.intr_info);
2234 if (err)
2235 goto err_return;
2236 }
2237 return 0;
2238
2239err_return:
2240 bnad_res_free(bnad);
2241 return err;
2242}
2243
2244/* Interrupt enable / disable */
2245static void
2246bnad_enable_msix(struct bnad *bnad)
2247{
2248 int i, ret;
8b230ed8
RM		 2249 unsigned long flags;
2250
2251 spin_lock_irqsave(&bnad->bna_lock, flags);
2252 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2253 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2254 return;
2255 }
2256 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2257
2258 if (bnad->msix_table)
2259 return;
2260
8b230ed8 2261 bnad->msix_table =
b7ee31c5 2262 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
8b230ed8
RM		 2263
2264 if (!bnad->msix_table)
2265 goto intx_mode;
2266
b7ee31c5 2267 for (i = 0; i < bnad->msix_num; i++)
8b230ed8
RM		 2268 bnad->msix_table[i].entry = i;
2269
b7ee31c5 2270 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
8b230ed8
RM		 2271 if (ret > 0) {
2272 /* Not enough MSI-X vectors. */
2273
2274 spin_lock_irqsave(&bnad->bna_lock, flags);
2275 /* ret = #of vectors that we got */
2276 bnad_q_num_adjust(bnad, ret);
2277 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2278
2279 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx)
2280 + (bnad->num_rx
2281 * bnad->num_rxp_per_rx) +
2282 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8
RM		 2283
2284 /* Try once more with adjusted numbers */
2285 /* If this fails, fall back to INTx */
2286 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
b7ee31c5 2287 bnad->msix_num);
8b230ed8
RM		 2288 if (ret)
2289 goto intx_mode;
2290
2291 } else if (ret < 0)
2292 goto intx_mode;
2293 return;
2294
2295intx_mode:
2296
2297 kfree(bnad->msix_table);
2298 bnad->msix_table = NULL;
2299 bnad->msix_num = 0;
8b230ed8
RM		 2300 spin_lock_irqsave(&bnad->bna_lock, flags);
2301 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2302 bnad_q_num_init(bnad);
2303 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2304}
2305
2306static void
2307bnad_disable_msix(struct bnad *bnad)
2308{
2309 u32 cfg_flags;
2310 unsigned long flags;
2311
2312 spin_lock_irqsave(&bnad->bna_lock, flags);
2313 cfg_flags = bnad->cfg_flags;
2314 if (bnad->cfg_flags & BNAD_CF_MSIX)
2315 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2316 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2317
2318 if (cfg_flags & BNAD_CF_MSIX) {
2319 pci_disable_msix(bnad->pcidev);
2320 kfree(bnad->msix_table);
2321 bnad->msix_table = NULL;
2322 }
2323}
2324
2325/* Netdev entry points */
2326static int
2327bnad_open(struct net_device *netdev)
2328{
2329 int err;
2330 struct bnad *bnad = netdev_priv(netdev);
2331 struct bna_pause_config pause_config;
2332 int mtu;
2333 unsigned long flags;
2334
2335 mutex_lock(&bnad->conf_mutex);
2336
2337 /* Tx */
2338 err = bnad_setup_tx(bnad, 0);
2339 if (err)
2340 goto err_return;
2341
2342 /* Rx */
2343 err = bnad_setup_rx(bnad, 0);
2344 if (err)
2345 goto cleanup_tx;
2346
2347 /* Port */
2348 pause_config.tx_pause = 0;
2349 pause_config.rx_pause = 0;
2350
2351 mtu = ETH_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
2352
2353 spin_lock_irqsave(&bnad->bna_lock, flags);
2354 bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
2355 bna_port_pause_config(&bnad->bna.port, &pause_config, NULL);
2356 bna_port_enable(&bnad->bna.port);
2357 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2358
2359 /* Enable broadcast */
2360 bnad_enable_default_bcast(bnad);
2361
aad75b66
RM		 2362 /* Restore VLANs, if any */
2363 bnad_restore_vlans(bnad, 0);
2364
8b230ed8
RM		 2365 /* Set the UCAST address */
2366 spin_lock_irqsave(&bnad->bna_lock, flags);
2367 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2368 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2369
2370 /* Start the stats timer */
2371 bnad_stats_timer_start(bnad);
2372
2373 mutex_unlock(&bnad->conf_mutex);
2374
2375 return 0;
2376
2377cleanup_tx:
2378 bnad_cleanup_tx(bnad, 0);
2379
2380err_return:
2381 mutex_unlock(&bnad->conf_mutex);
2382 return err;
2383}
2384
2385static int
2386bnad_stop(struct net_device *netdev)
2387{
2388 struct bnad *bnad = netdev_priv(netdev);
2389 unsigned long flags;
2390
2391 mutex_lock(&bnad->conf_mutex);
2392
2393 /* Stop the stats timer */
2394 bnad_stats_timer_stop(bnad);
2395
2396 init_completion(&bnad->bnad_completions.port_comp);
2397
2398 spin_lock_irqsave(&bnad->bna_lock, flags);
2399 bna_port_disable(&bnad->bna.port, BNA_HARD_CLEANUP,
2400 bnad_cb_port_disabled);
2401 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2402
2403 wait_for_completion(&bnad->bnad_completions.port_comp);
2404
2405 bnad_cleanup_tx(bnad, 0);
2406 bnad_cleanup_rx(bnad, 0);
2407
2408 /* Synchronize mailbox IRQ */
2409 bnad_mbox_irq_sync(bnad);
2410
2411 mutex_unlock(&bnad->conf_mutex);
2412
2413 return 0;
2414}
2415
2416/* TX */
2417/*
2418 * bnad_start_xmit : Netdev entry point for Transmit
2419 * Called under lock held by net_device
2420 */
2421static netdev_tx_t
2422bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2423{
2424 struct bnad *bnad = netdev_priv(netdev);
2425
2426 u16 txq_prod, vlan_tag = 0;
2427 u32 unmap_prod, wis, wis_used, wi_range;
2428 u32 vectors, vect_id, i, acked;
2429 u32 tx_id;
2430 int err;
2431
2432 struct bnad_tx_info *tx_info;
2433 struct bna_tcb *tcb;
2434 struct bnad_unmap_q *unmap_q;
2435 dma_addr_t dma_addr;
2436 struct bna_txq_entry *txqent;
2437 bna_txq_wi_ctrl_flag_t flags;
2438
2439 if (unlikely
2440 (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
2441 dev_kfree_skb(skb);
2442 return NETDEV_TX_OK;
2443 }
2444
be7fa326
RM		 2445 tx_id = 0;
2446
2447 tx_info = &bnad->tx_info[tx_id];
2448 tcb = tx_info->tcb[tx_id];
2449 unmap_q = tcb->unmap_q;
2450
8b230ed8
RM		 2451 /*
2452 * Takes care of the Tx that is scheduled between clearing the flag
2453 * and the netif_stop_queue() call.
2454 */
be7fa326 2455 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
8b230ed8
RM		 2456 dev_kfree_skb(skb);
2457 return NETDEV_TX_OK;
2458 }
2459
8b230ed8
RM		 2460 vectors = 1 + skb_shinfo(skb)->nr_frags;
2461 if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
2462 dev_kfree_skb(skb);
2463 return NETDEV_TX_OK;
2464 }
2465 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2466 acked = 0;
2467 if (unlikely
2468 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2469 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2470 if ((u16) (*tcb->hw_consumer_index) !=
2471 tcb->consumer_index &&
2472 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2473 acked = bnad_free_txbufs(bnad, tcb);
be7fa326
RM		 2474 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2475 bna_ib_ack(tcb->i_dbell, acked);
8b230ed8
RM		 2476 smp_mb__before_clear_bit();
2477 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2478 } else {
2479 netif_stop_queue(netdev);
2480 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2481 }
2482
2483 smp_mb();
2484 /*
2485 * Check again to deal with race condition between
2486 * netif_stop_queue here, and netif_wake_queue in
2487 * interrupt handler which is not inside netif tx lock.
2488 */
2489 if (likely
2490 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2491 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2492 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2493 return NETDEV_TX_BUSY;
2494 } else {
2495 netif_wake_queue(netdev);
2496 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2497 }
2498 }
2499
2500 unmap_prod = unmap_q->producer_index;
2501 wis_used = 1;
2502 vect_id = 0;
2503 flags = 0;
2504
2505 txq_prod = tcb->producer_index;
2506 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
2507 BUG_ON(!(wi_range <= tcb->q_depth));
2508 txqent->hdr.wi.reserved = 0;
2509 txqent->hdr.wi.num_vectors = vectors;
2510 txqent->hdr.wi.opcode =
2511 htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
2512 BNA_TXQ_WI_SEND));
2513
eab6d18d 2514 if (vlan_tx_tag_present(skb)) {
8b230ed8
RM		 2515 vlan_tag = (u16) vlan_tx_tag_get(skb);
2516 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2517 }
2518 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2519 vlan_tag =
2520 (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
2521 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2522 }
2523
2524 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2525
2526 if (skb_is_gso(skb)) {
2527 err = bnad_tso_prepare(bnad, skb);
2528 if (err) {
2529 dev_kfree_skb(skb);
2530 return NETDEV_TX_OK;
2531 }
2532 txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
2533 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2534 txqent->hdr.wi.l4_hdr_size_n_offset =
2535 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2536 (tcp_hdrlen(skb) >> 2,
2537 skb_transport_offset(skb)));
2538 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2539 u8 proto = 0;
2540
2541 txqent->hdr.wi.lso_mss = 0;
2542
2543 if (skb->protocol == htons(ETH_P_IP))
2544 proto = ip_hdr(skb)->protocol;
2545 else if (skb->protocol == htons(ETH_P_IPV6)) {
2546 /* nexthdr may not be TCP immediately. */
2547 proto = ipv6_hdr(skb)->nexthdr;
2548 }
2549 if (proto == IPPROTO_TCP) {
2550 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2551 txqent->hdr.wi.l4_hdr_size_n_offset =
2552 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2553 (0, skb_transport_offset(skb)));
2554
2555 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2556
2557 BUG_ON(!(skb_headlen(skb) >=
2558 skb_transport_offset(skb) + tcp_hdrlen(skb)));
2559
2560 } else if (proto == IPPROTO_UDP) {
2561 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2562 txqent->hdr.wi.l4_hdr_size_n_offset =
2563 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2564 (0, skb_transport_offset(skb)));
2565
2566 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2567
2568 BUG_ON(!(skb_headlen(skb) >=
2569 skb_transport_offset(skb) +
2570 sizeof(struct udphdr)));
2571 } else {
2572 err = skb_checksum_help(skb);
2573 BNAD_UPDATE_CTR(bnad, csum_help);
2574 if (err) {
2575 dev_kfree_skb(skb);
2576 BNAD_UPDATE_CTR(bnad, csum_help_err);
2577 return NETDEV_TX_OK;
2578 }
2579 }
2580 } else {
2581 txqent->hdr.wi.lso_mss = 0;
2582 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2583 }
2584
2585 txqent->hdr.wi.flags = htons(flags);
2586
2587 txqent->hdr.wi.frame_length = htonl(skb->len);
2588
2589 unmap_q->unmap_array[unmap_prod].skb = skb;
2590 BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR));
2591 txqent->vector[vect_id].length = htons(skb_headlen(skb));
2592 dma_addr = pci_map_single(bnad->pcidev, skb->data, skb_headlen(skb),
2593 PCI_DMA_TODEVICE);
2594 pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2595 dma_addr);
2596
2597 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2598 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2599
2600 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2601 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
2602 u32 size = frag->size;
2603
2604 if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
2605 vect_id = 0;
2606 if (--wi_range)
2607 txqent++;
2608 else {
2609 BNA_QE_INDX_ADD(txq_prod, wis_used,
2610 tcb->q_depth);
2611 wis_used = 0;
2612 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
2613 txqent, wi_range);
2614 BUG_ON(!(wi_range <= tcb->q_depth));
2615 }
2616 wis_used++;
2617 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
2618 }
2619
2620 BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
2621 txqent->vector[vect_id].length = htons(size);
2622 dma_addr =
2623 pci_map_page(bnad->pcidev, frag->page,
2624 frag->page_offset, size,
2625 PCI_DMA_TODEVICE);
2626 pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2627 dma_addr);
2628 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2629 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2630 }
2631
2632 unmap_q->producer_index = unmap_prod;
2633 BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
2634 tcb->producer_index = txq_prod;
2635
2636 smp_mb();
be7fa326
RM		 2637
2638 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2639 return NETDEV_TX_OK;
2640
8b230ed8
RM		 2641 bna_txq_prod_indx_doorbell(tcb);
2642
2643 if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
2644 tasklet_schedule(&bnad->tx_free_tasklet);
2645
2646 return NETDEV_TX_OK;
2647}
2648
2649/*
2650 * Used spin_lock to synchronize reading of stats structures, which
2651 * is written by BNA under the same lock.
2652 */
250e061e
ED		 2653static struct rtnl_link_stats64 *
2654bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
8b230ed8
RM		 2655{
2656 struct bnad *bnad = netdev_priv(netdev);
2657 unsigned long flags;
2658
2659 spin_lock_irqsave(&bnad->bna_lock, flags);
2660
250e061e
ED		 2661 bnad_netdev_qstats_fill(bnad, stats);
2662 bnad_netdev_hwstats_fill(bnad, stats);
8b230ed8
RM		 2663
2664 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2665
250e061e 2666 return stats;
8b230ed8
RM		 2667}
2668
2669static void
2670bnad_set_rx_mode(struct net_device *netdev)
2671{
2672 struct bnad *bnad = netdev_priv(netdev);
2673 u32 new_mask, valid_mask;
2674 unsigned long flags;
2675
2676 spin_lock_irqsave(&bnad->bna_lock, flags);
2677
2678 new_mask = valid_mask = 0;
2679
2680 if (netdev->flags & IFF_PROMISC) {
2681 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
2682 new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2683 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2684 bnad->cfg_flags |= BNAD_CF_PROMISC;
2685 }
2686 } else {
2687 if (bnad->cfg_flags & BNAD_CF_PROMISC) {
2688 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
2689 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2690 bnad->cfg_flags &= ~BNAD_CF_PROMISC;
2691 }
2692 }
2693
2694 if (netdev->flags & IFF_ALLMULTI) {
2695 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
2696 new_mask |= BNA_RXMODE_ALLMULTI;
2697 valid_mask |= BNA_RXMODE_ALLMULTI;
2698 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
2699 }
2700 } else {
2701 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
2702 new_mask &= ~BNA_RXMODE_ALLMULTI;
2703 valid_mask |= BNA_RXMODE_ALLMULTI;
2704 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
2705 }
2706 }
2707
2708 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
2709
2710 if (!netdev_mc_empty(netdev)) {
2711 u8 *mcaddr_list;
2712 int mc_count = netdev_mc_count(netdev);
2713
2714 /* Index 0 holds the broadcast address */
2715 mcaddr_list =
2716 kzalloc((mc_count + 1) * ETH_ALEN,
2717 GFP_ATOMIC);
2718 if (!mcaddr_list)
ca1cef3a 2719 goto unlock;
8b230ed8
RM		 2720
2721 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
2722
2723 /* Copy rest of the MC addresses */
2724 bnad_netdev_mc_list_get(netdev, mcaddr_list);
2725
2726 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
2727 mcaddr_list, NULL);
2728
2729 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2730 kfree(mcaddr_list);
2731 }
ca1cef3a 2732unlock:
8b230ed8
RM		 2733 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2734}
2735
2736/*
2737 * bna_lock is used to sync writes to netdev->addr
2738 * conf_lock cannot be used since this call may be made
2739 * in a non-blocking context.
2740 */
2741static int
2742bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
2743{
2744 int err;
2745 struct bnad *bnad = netdev_priv(netdev);
2746 struct sockaddr *sa = (struct sockaddr *)mac_addr;
2747 unsigned long flags;
2748
2749 spin_lock_irqsave(&bnad->bna_lock, flags);
2750
2751 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
2752
2753 if (!err)
2754 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
2755
2756 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2757
2758 return err;
2759}
2760
2761static int
2762bnad_change_mtu(struct net_device *netdev, int new_mtu)
2763{
2764 int mtu, err = 0;
2765 unsigned long flags;
2766
2767 struct bnad *bnad = netdev_priv(netdev);
2768
2769 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
2770 return -EINVAL;
2771
2772 mutex_lock(&bnad->conf_mutex);
2773
2774 netdev->mtu = new_mtu;
2775
2776 mtu = ETH_HLEN + new_mtu + ETH_FCS_LEN;
2777
2778 spin_lock_irqsave(&bnad->bna_lock, flags);
2779 bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
2780 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2781
2782 mutex_unlock(&bnad->conf_mutex);
2783 return err;
2784}
2785
2786static void
2787bnad_vlan_rx_register(struct net_device *netdev,
2788 struct vlan_group *vlan_grp)
2789{
2790 struct bnad *bnad = netdev_priv(netdev);
2791
2792 mutex_lock(&bnad->conf_mutex);
2793 bnad->vlan_grp = vlan_grp;
2794 mutex_unlock(&bnad->conf_mutex);
2795}
2796
2797static void
2798bnad_vlan_rx_add_vid(struct net_device *netdev,
2799 unsigned short vid)
2800{
2801 struct bnad *bnad = netdev_priv(netdev);
2802 unsigned long flags;
2803
2804 if (!bnad->rx_info[0].rx)
2805 return;
2806
2807 mutex_lock(&bnad->conf_mutex);
2808
2809 spin_lock_irqsave(&bnad->bna_lock, flags);
2810 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
2811 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2812
2813 mutex_unlock(&bnad->conf_mutex);
2814}
2815
2816static void
2817bnad_vlan_rx_kill_vid(struct net_device *netdev,
2818 unsigned short vid)
2819{
2820 struct bnad *bnad = netdev_priv(netdev);
2821 unsigned long flags;
2822
2823 if (!bnad->rx_info[0].rx)
2824 return;
2825
2826 mutex_lock(&bnad->conf_mutex);
2827
2828 spin_lock_irqsave(&bnad->bna_lock, flags);
2829 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
2830 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2831
2832 mutex_unlock(&bnad->conf_mutex);
2833}
2834
2835#ifdef CONFIG_NET_POLL_CONTROLLER
2836static void
2837bnad_netpoll(struct net_device *netdev)
2838{
2839 struct bnad *bnad = netdev_priv(netdev);
2840 struct bnad_rx_info *rx_info;
2841 struct bnad_rx_ctrl *rx_ctrl;
2842 u32 curr_mask;
2843 int i, j;
2844
2845 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2846 bna_intx_disable(&bnad->bna, curr_mask);
2847 bnad_isr(bnad->pcidev->irq, netdev);
2848 bna_intx_enable(&bnad->bna, curr_mask);
2849 } else {
2850 for (i = 0; i < bnad->num_rx; i++) {
2851 rx_info = &bnad->rx_info[i];
2852 if (!rx_info->rx)
2853 continue;
2854 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2855 rx_ctrl = &rx_info->rx_ctrl[j];
2856 if (rx_ctrl->ccb) {
2857 bnad_disable_rx_irq(bnad,
2858 rx_ctrl->ccb);
2859 bnad_netif_rx_schedule_poll(bnad,
2860 rx_ctrl->ccb);
2861 }
2862 }
2863 }
2864 }
2865}
2866#endif
2867
2868static const struct net_device_ops bnad_netdev_ops = {
2869 .ndo_open = bnad_open,
2870 .ndo_stop = bnad_stop,
2871 .ndo_start_xmit = bnad_start_xmit,
250e061e 2872 .ndo_get_stats64 = bnad_get_stats64,
8b230ed8
RM		 2873 .ndo_set_rx_mode = bnad_set_rx_mode,
2874 .ndo_set_multicast_list = bnad_set_rx_mode,
2875 .ndo_validate_addr = eth_validate_addr,
2876 .ndo_set_mac_address = bnad_set_mac_address,
2877 .ndo_change_mtu = bnad_change_mtu,
2878 .ndo_vlan_rx_register = bnad_vlan_rx_register,
2879 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
2880 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
2881#ifdef CONFIG_NET_POLL_CONTROLLER
2882 .ndo_poll_controller = bnad_netpoll
2883#endif
2884};
2885
2886static void
2887bnad_netdev_init(struct bnad *bnad, bool using_dac)
2888{
2889 struct net_device *netdev = bnad->netdev;
2890
2891 netdev->features |= NETIF_F_IPV6_CSUM;
2892 netdev->features |= NETIF_F_TSO;
2893 netdev->features |= NETIF_F_TSO6;
2894
2895 netdev->features |= NETIF_F_GRO;
2896 pr_warn("bna: GRO enabled, using kernel stack GRO\n");
2897
2898 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2899
2900 if (using_dac)
2901 netdev->features |= NETIF_F_HIGHDMA;
2902
2903 netdev->features |=
2904 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2905 NETIF_F_HW_VLAN_FILTER;
2906
2907 netdev->vlan_features = netdev->features;
2908 netdev->mem_start = bnad->mmio_start;
2909 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
2910
2911 netdev->netdev_ops = &bnad_netdev_ops;
2912 bnad_set_ethtool_ops(netdev);
2913}
2914
2915/*
2916 * 1. Initialize the bnad structure
2917 * 2. Setup netdev pointer in pci_dev
2918 * 3. Initialze Tx free tasklet
2919 * 4. Initialize no. of TxQ & CQs & MSIX vectors
2920 */
2921static int
2922bnad_init(struct bnad *bnad,
2923 struct pci_dev *pdev, struct net_device *netdev)
2924{
2925 unsigned long flags;
2926
2927 SET_NETDEV_DEV(netdev, &pdev->dev);
2928 pci_set_drvdata(pdev, netdev);
2929
2930 bnad->netdev = netdev;
2931 bnad->pcidev = pdev;
2932 bnad->mmio_start = pci_resource_start(pdev, 0);
2933 bnad->mmio_len = pci_resource_len(pdev, 0);
2934 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
2935 if (!bnad->bar0) {
2936 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
2937 pci_set_drvdata(pdev, NULL);
2938 return -ENOMEM;
2939 }
2940 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
2941 (unsigned long long) bnad->mmio_len);
2942
2943 spin_lock_irqsave(&bnad->bna_lock, flags);
2944 if (!bnad_msix_disable)
2945 bnad->cfg_flags = BNAD_CF_MSIX;
2946
2947 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
2948
2949 bnad_q_num_init(bnad);
2950 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2951
2952 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
2953 (bnad->num_rx * bnad->num_rxp_per_rx) +
2954 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8
RM		 2955
2956 bnad->txq_depth = BNAD_TXQ_DEPTH;
2957 bnad->rxq_depth = BNAD_RXQ_DEPTH;
2958 bnad->rx_csum = true;
2959
2960 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
2961 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
2962
2963 tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
2964 (unsigned long)bnad);
2965
2966 return 0;
2967}
2968
2969/*
2970 * Must be called after bnad_pci_uninit()
2971 * so that iounmap() and pci_set_drvdata(NULL)
2972 * happens only after PCI uninitialization.
2973 */
2974static void
2975bnad_uninit(struct bnad *bnad)
2976{
2977 if (bnad->bar0)
2978 iounmap(bnad->bar0);
2979 pci_set_drvdata(bnad->pcidev, NULL);
2980}
2981
2982/*
2983 * Initialize locks
2984 a) Per device mutes used for serializing configuration
2985 changes from OS interface
2986 b) spin lock used to protect bna state machine
2987 */
2988static void
2989bnad_lock_init(struct bnad *bnad)
2990{
2991 spin_lock_init(&bnad->bna_lock);
2992 mutex_init(&bnad->conf_mutex);
2993}
2994
2995static void
2996bnad_lock_uninit(struct bnad *bnad)
2997{
2998 mutex_destroy(&bnad->conf_mutex);
2999}
3000
3001/* PCI Initialization */
3002static int
3003bnad_pci_init(struct bnad *bnad,
3004 struct pci_dev *pdev, bool *using_dac)
3005{
3006 int err;
3007
3008 err = pci_enable_device(pdev);
3009 if (err)
3010 return err;
3011 err = pci_request_regions(pdev, BNAD_NAME);
3012 if (err)
3013 goto disable_device;
3014 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
3015 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
3016 *using_dac = 1;
3017 } else {
3018 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3019 if (err) {
3020 err = pci_set_consistent_dma_mask(pdev,
3021 DMA_BIT_MASK(32));
3022 if (err)
3023 goto release_regions;
3024 }
3025 *using_dac = 0;
3026 }
3027 pci_set_master(pdev);
3028 return 0;
3029
3030release_regions:
3031 pci_release_regions(pdev);
3032disable_device:
3033 pci_disable_device(pdev);
3034
3035 return err;
3036}
3037
3038static void
3039bnad_pci_uninit(struct pci_dev *pdev)
3040{
3041 pci_release_regions(pdev);
3042 pci_disable_device(pdev);
3043}
3044
3045static int __devinit
3046bnad_pci_probe(struct pci_dev *pdev,
3047 const struct pci_device_id *pcidev_id)
3048{
aad75b66 3049 bool using_dac = false;
8b230ed8
RM		 3050 int err;
3051 struct bnad *bnad;
3052 struct bna *bna;
3053 struct net_device *netdev;
3054 struct bfa_pcidev pcidev_info;
3055 unsigned long flags;
3056
3057 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3058 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3059
3060 mutex_lock(&bnad_fwimg_mutex);
3061 if (!cna_get_firmware_buf(pdev)) {
3062 mutex_unlock(&bnad_fwimg_mutex);
3063 pr_warn("Failed to load Firmware Image!\n");
3064 return -ENODEV;
3065 }
3066 mutex_unlock(&bnad_fwimg_mutex);
3067
3068 /*
3069 * Allocates sizeof(struct net_device + struct bnad)
3070 * bnad = netdev->priv
3071 */
3072 netdev = alloc_etherdev(sizeof(struct bnad));
3073 if (!netdev) {
3074 dev_err(&pdev->dev, "alloc_etherdev failed\n");
3075 err = -ENOMEM;
3076 return err;
3077 }
3078 bnad = netdev_priv(netdev);
3079
8b230ed8
RM		 3080 /*
3081 * PCI initialization
3082 * Output : using_dac = 1 for 64 bit DMA
be7fa326 3083 * = 0 for 32 bit DMA
8b230ed8
RM		 3084 */
3085 err = bnad_pci_init(bnad, pdev, &using_dac);
3086 if (err)
3087 goto free_netdev;
3088
3089 bnad_lock_init(bnad);
3090 /*
3091 * Initialize bnad structure
3092 * Setup relation between pci_dev & netdev
3093 * Init Tx free tasklet
3094 */
3095 err = bnad_init(bnad, pdev, netdev);
3096 if (err)
3097 goto pci_uninit;
3098 /* Initialize netdev structure, set up ethtool ops */
3099 bnad_netdev_init(bnad, using_dac);
3100
815f41e7
RM		 3101 /* Set link to down state */
3102 netif_carrier_off(netdev);
3103
8b230ed8
RM		 3104 bnad_enable_msix(bnad);
3105
3106 /* Get resource requirement form bna */
3107 bna_res_req(&bnad->res_info[0]);
3108
3109 /* Allocate resources from bna */
3110 err = bnad_res_alloc(bnad);
3111 if (err)
3112 goto free_netdev;
3113
3114 bna = &bnad->bna;
3115
3116 /* Setup pcidev_info for bna_init() */
3117 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3118 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3119 pcidev_info.device_id = bnad->pcidev->device;
3120 pcidev_info.pci_bar_kva = bnad->bar0;
3121
3122 mutex_lock(&bnad->conf_mutex);
3123
3124 spin_lock_irqsave(&bnad->bna_lock, flags);
3125 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
8b230ed8
RM		 3126 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3127
3128 bnad->stats.bna_stats = &bna->stats;
3129
3130 /* Set up timers */
3131 setup_timer(&bnad->bna.device.ioc.ioc_timer, bnad_ioc_timeout,
3132 ((unsigned long)bnad));
3133 setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check,
3134 ((unsigned long)bnad));
3135 setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_ioc_sem_timeout,
3136 ((unsigned long)bnad));
3137
3138 /* Now start the timer before calling IOC */
3139 mod_timer(&bnad->bna.device.ioc.ioc_timer,
3140 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3141
3142 /*
3143 * Start the chip
3144 * Don't care even if err != 0, bna state machine will
3145 * deal with it
3146 */
3147 err = bnad_device_enable(bnad);
3148
3149 /* Get the burnt-in mac */
3150 spin_lock_irqsave(&bnad->bna_lock, flags);
3151 bna_port_mac_get(&bna->port, &bnad->perm_addr);
3152 bnad_set_netdev_perm_addr(bnad);
3153 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3154
3155 mutex_unlock(&bnad->conf_mutex);
3156
8b230ed8
RM		 3157 /* Finally, reguister with net_device layer */
3158 err = register_netdev(netdev);
3159 if (err) {
3160 pr_err("BNA : Registering with netdev failed\n");
3161 goto disable_device;
3162 }
3163
3164 return 0;
3165
3166disable_device:
3167 mutex_lock(&bnad->conf_mutex);
3168 bnad_device_disable(bnad);
3169 del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
3170 del_timer_sync(&bnad->bna.device.ioc.sem_timer);
3171 del_timer_sync(&bnad->bna.device.ioc.hb_timer);
3172 spin_lock_irqsave(&bnad->bna_lock, flags);
3173 bna_uninit(bna);
3174 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3175 mutex_unlock(&bnad->conf_mutex);
3176
3177 bnad_res_free(bnad);
3178 bnad_disable_msix(bnad);
3179pci_uninit:
3180 bnad_pci_uninit(pdev);
3181 bnad_lock_uninit(bnad);
3182 bnad_uninit(bnad);
3183free_netdev:
3184 free_netdev(netdev);
3185 return err;
3186}
3187
3188static void __devexit
3189bnad_pci_remove(struct pci_dev *pdev)
3190{
3191 struct net_device *netdev = pci_get_drvdata(pdev);
3192 struct bnad *bnad;
3193 struct bna *bna;
3194 unsigned long flags;
3195
3196 if (!netdev)
3197 return;
3198
3199 pr_info("%s bnad_pci_remove\n", netdev->name);
3200 bnad = netdev_priv(netdev);
3201 bna = &bnad->bna;
3202
3203 unregister_netdev(netdev);
3204
3205 mutex_lock(&bnad->conf_mutex);
3206 bnad_device_disable(bnad);
3207 del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
3208 del_timer_sync(&bnad->bna.device.ioc.sem_timer);
3209 del_timer_sync(&bnad->bna.device.ioc.hb_timer);
3210 spin_lock_irqsave(&bnad->bna_lock, flags);
3211 bna_uninit(bna);
3212 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3213 mutex_unlock(&bnad->conf_mutex);
3214
3215 bnad_res_free(bnad);
3216 bnad_disable_msix(bnad);
3217 bnad_pci_uninit(pdev);
3218 bnad_lock_uninit(bnad);
3219 bnad_uninit(bnad);
3220 free_netdev(netdev);
3221}
3222
b7ee31c5 3223static const struct pci_device_id bnad_pci_id_table[] = {
8b230ed8
RM		 3224 {
3225 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3226 PCI_DEVICE_ID_BROCADE_CT),
3227 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3228 .class_mask = 0xffff00
3229 }, {0, }
3230};
3231
3232MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3233
3234static struct pci_driver bnad_pci_driver = {
3235 .name = BNAD_NAME,
3236 .id_table = bnad_pci_id_table,
3237 .probe = bnad_pci_probe,
3238 .remove = __devexit_p(bnad_pci_remove),
3239};
3240
3241static int __init
3242bnad_module_init(void)
3243{
3244 int err;
3245
3246 pr_info("Brocade 10G Ethernet driver\n");
3247
8a891429 3248 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
8b230ed8
RM		 3249
3250 err = pci_register_driver(&bnad_pci_driver);
3251 if (err < 0) {
3252 pr_err("bna : PCI registration failed in module init "
3253 "(%d)\n", err);
3254 return err;
3255 }
3256
3257 return 0;
3258}
3259
3260static void __exit
3261bnad_module_exit(void)
3262{
3263 pci_unregister_driver(&bnad_pci_driver);
3264
3265 if (bfi_fw)
3266 release_firmware(bfi_fw);
3267}
3268
3269module_init(bnad_module_init);
3270module_exit(bnad_module_exit);
3271
3272MODULE_AUTHOR("Brocade");
3273MODULE_LICENSE("GPL");
3274MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3275MODULE_VERSION(BNAD_VERSION);
3276MODULE_FIRMWARE(CNA_FW_FILE_CT);
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