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[BNX2]: Allow WoL settings on new 5708 chips
[mirror_ubuntu-artful-kernel.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
206cc83c 3 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12#include <linux/config.h>
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
17#include <linux/kernel.h>
18#include <linux/timer.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/slab.h>
22#include <linux/vmalloc.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/dma-mapping.h>
30#include <asm/bitops.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/delay.h>
34#include <asm/byteorder.h>
35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h>
40#define BCM_VLAN 1
41#endif
42#ifdef NETIF_F_TSO
43#include <net/ip.h>
44#include <net/tcp.h>
45#include <net/checksum.h>
46#define BCM_TSO 1
47#endif
48#include <linux/workqueue.h>
49#include <linux/crc32.h>
50#include <linux/prefetch.h>
29b12174 51#include <linux/cache.h>
f2a4f052 52
b6016b76
MC		 53#include "bnx2.h"
54#include "bnx2_fw.h"
55
56#define DRV_MODULE_NAME "bnx2"
57#define PFX DRV_MODULE_NAME ": "
ae181bc4
MC		 58#define DRV_MODULE_VERSION "1.4.40"
59#define DRV_MODULE_RELDATE "May 22, 2006"
b6016b76
MC		 60
61#define RUN_AT(x) (jiffies + (x))
62
63/* Time in jiffies before concluding the transmitter is hung. */
64#define TX_TIMEOUT (5*HZ)
65
e19360f2 66static const char version[] __devinitdata =
b6016b76
MC		 67 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
68
69MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 70MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 71MODULE_LICENSE("GPL");
72MODULE_VERSION(DRV_MODULE_VERSION);
73
74static int disable_msi = 0;
75
76module_param(disable_msi, int, 0);
77MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
78
79typedef enum {
80 BCM5706 = 0,
81 NC370T,
82 NC370I,
83 BCM5706S,
84 NC370F,
5b0c76ad
MC		 85 BCM5708,
86 BCM5708S,
b6016b76
MC		 87} board_t;
88
89/* indexed by board_t, above */
f71e1309 90static const struct {
b6016b76
MC		 91 char *name;
92} board_info[] __devinitdata = {
93 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
94 { "HP NC370T Multifunction Gigabit Server Adapter" },
95 { "HP NC370i Multifunction Gigabit Server Adapter" },
96 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
97 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 98 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
99 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
b6016b76
MC		 100 };
101
102static struct pci_device_id bnx2_pci_tbl[] = {
103 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
104 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
105 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
106 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
107 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 109 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 111 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
112 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
b6016b76
MC		 117 { 0, }
118};
119
120static struct flash_spec flash_table[] =
121{
122 /* Slow EEPROM */
37137709 123 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
b6016b76
MC		 124 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
125 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
126 "EEPROM - slow"},
37137709
MC		 127 /* Expansion entry 0001 */
128 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76 129 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 130 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
131 "Entry 0001"},
b6016b76
MC		 132 /* Saifun SA25F010 (non-buffered flash) */
133 /* strap, cfg1, & write1 need updates */
37137709 134 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 135 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
136 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
137 "Non-buffered flash (128kB)"},
138 /* Saifun SA25F020 (non-buffered flash) */
139 /* strap, cfg1, & write1 need updates */
37137709 140 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 141 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
142 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
143 "Non-buffered flash (256kB)"},
37137709
MC		 144 /* Expansion entry 0100 */
145 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 "Entry 0100"},
149 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
150 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
151 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
152 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
153 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
154 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
155 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
156 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
157 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
158 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
159 /* Saifun SA25F005 (non-buffered flash) */
160 /* strap, cfg1, & write1 need updates */
161 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
162 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
163 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
164 "Non-buffered flash (64kB)"},
165 /* Fast EEPROM */
166 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
167 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
168 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
169 "EEPROM - fast"},
170 /* Expansion entry 1001 */
171 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
172 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
173 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
174 "Entry 1001"},
175 /* Expansion entry 1010 */
176 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
177 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 1010"},
180 /* ATMEL AT45DB011B (buffered flash) */
181 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
182 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
183 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
184 "Buffered flash (128kB)"},
185 /* Expansion entry 1100 */
186 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
187 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
188 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
189 "Entry 1100"},
190 /* Expansion entry 1101 */
191 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
192 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
194 "Entry 1101"},
195 /* Ateml Expansion entry 1110 */
196 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
197 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
198 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
199 "Entry 1110 (Atmel)"},
200 /* ATMEL AT45DB021B (buffered flash) */
201 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
202 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
203 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
204 "Buffered flash (256kB)"},
b6016b76
MC		 205};
206
207MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
208
e89bbf10
MC		 209static inline u32 bnx2_tx_avail(struct bnx2 *bp)
210{
211 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
212
213 if (diff > MAX_TX_DESC_CNT)
214 diff = (diff & MAX_TX_DESC_CNT) - 1;
215 return (bp->tx_ring_size - diff);
216}
217
b6016b76
MC		 218static u32
219bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
220{
221 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
222 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
223}
224
225static void
226bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
227{
228 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
229 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
230}
231
232static void
233bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
234{
235 offset += cid_addr;
236 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
237 REG_WR(bp, BNX2_CTX_DATA, val);
238}
239
240static int
241bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
242{
243 u32 val1;
244 int i, ret;
245
246 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
247 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
248 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
249
250 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
251 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
252
253 udelay(40);
254 }
255
256 val1 = (bp->phy_addr << 21) | (reg << 16) |
257 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
258 BNX2_EMAC_MDIO_COMM_START_BUSY;
259 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
260
261 for (i = 0; i < 50; i++) {
262 udelay(10);
263
264 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
265 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
266 udelay(5);
267
268 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
269 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
270
271 break;
272 }
273 }
274
275 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
276 *val = 0x0;
277 ret = -EBUSY;
278 }
279 else {
280 *val = val1;
281 ret = 0;
282 }
283
284 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
285 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
286 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
287
288 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
289 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
290
291 udelay(40);
292 }
293
294 return ret;
295}
296
297static int
298bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
299{
300 u32 val1;
301 int i, ret;
302
303 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
304 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
305 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
306
307 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
308 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
309
310 udelay(40);
311 }
312
313 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
314 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
315 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
316 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
317
318 for (i = 0; i < 50; i++) {
319 udelay(10);
320
321 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
322 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
323 udelay(5);
324 break;
325 }
326 }
327
328 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
329 ret = -EBUSY;
330 else
331 ret = 0;
332
333 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
334 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
335 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
336
337 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
338 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
339
340 udelay(40);
341 }
342
343 return ret;
344}
345
346static void
347bnx2_disable_int(struct bnx2 *bp)
348{
349 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
350 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
351 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
352}
353
354static void
355bnx2_enable_int(struct bnx2 *bp)
356{
1269a8a6
MC		 357 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
358 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
359 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
360
b6016b76
MC		 361 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
362 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
363
bf5295bb 364 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 365}
366
367static void
368bnx2_disable_int_sync(struct bnx2 *bp)
369{
370 atomic_inc(&bp->intr_sem);
371 bnx2_disable_int(bp);
372 synchronize_irq(bp->pdev->irq);
373}
374
375static void
376bnx2_netif_stop(struct bnx2 *bp)
377{
378 bnx2_disable_int_sync(bp);
379 if (netif_running(bp->dev)) {
380 netif_poll_disable(bp->dev);
381 netif_tx_disable(bp->dev);
382 bp->dev->trans_start = jiffies; /* prevent tx timeout */
383 }
384}
385
386static void
387bnx2_netif_start(struct bnx2 *bp)
388{
389 if (atomic_dec_and_test(&bp->intr_sem)) {
390 if (netif_running(bp->dev)) {
391 netif_wake_queue(bp->dev);
392 netif_poll_enable(bp->dev);
393 bnx2_enable_int(bp);
394 }
395 }
396}
397
398static void
399bnx2_free_mem(struct bnx2 *bp)
400{
13daffa2
MC		 401 int i;
402
b6016b76 403 if (bp->status_blk) {
0f31f994 404 pci_free_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 405 bp->status_blk, bp->status_blk_mapping);
406 bp->status_blk = NULL;
0f31f994 407 bp->stats_blk = NULL;
b6016b76
MC		 408 }
409 if (bp->tx_desc_ring) {
410 pci_free_consistent(bp->pdev,
411 sizeof(struct tx_bd) * TX_DESC_CNT,
412 bp->tx_desc_ring, bp->tx_desc_mapping);
413 bp->tx_desc_ring = NULL;
414 }
b4558ea9
JJ		 415 kfree(bp->tx_buf_ring);
416 bp->tx_buf_ring = NULL;
13daffa2
MC		 417 for (i = 0; i < bp->rx_max_ring; i++) {
418 if (bp->rx_desc_ring[i])
419 pci_free_consistent(bp->pdev,
420 sizeof(struct rx_bd) * RX_DESC_CNT,
421 bp->rx_desc_ring[i],
422 bp->rx_desc_mapping[i]);
423 bp->rx_desc_ring[i] = NULL;
424 }
425 vfree(bp->rx_buf_ring);
b4558ea9 426 bp->rx_buf_ring = NULL;
b6016b76
MC		 427}
428
429static int
430bnx2_alloc_mem(struct bnx2 *bp)
431{
0f31f994 432 int i, status_blk_size;
13daffa2 433
0f31f994
MC		 434 bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
435 GFP_KERNEL);
b6016b76
MC		 436 if (bp->tx_buf_ring == NULL)
437 return -ENOMEM;
438
b6016b76
MC		 439 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
440 sizeof(struct tx_bd) *
441 TX_DESC_CNT,
442 &bp->tx_desc_mapping);
443 if (bp->tx_desc_ring == NULL)
444 goto alloc_mem_err;
445
13daffa2
MC		 446 bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
447 bp->rx_max_ring);
b6016b76
MC		 448 if (bp->rx_buf_ring == NULL)
449 goto alloc_mem_err;
450
13daffa2
MC		 451 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
452 bp->rx_max_ring);
453
454 for (i = 0; i < bp->rx_max_ring; i++) {
455 bp->rx_desc_ring[i] =
456 pci_alloc_consistent(bp->pdev,
457 sizeof(struct rx_bd) * RX_DESC_CNT,
458 &bp->rx_desc_mapping[i]);
459 if (bp->rx_desc_ring[i] == NULL)
460 goto alloc_mem_err;
461
462 }
b6016b76 463
0f31f994
MC		 464 /* Combine status and statistics blocks into one allocation. */
465 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
466 bp->status_stats_size = status_blk_size +
467 sizeof(struct statistics_block);
468
469 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 470 &bp->status_blk_mapping);
471 if (bp->status_blk == NULL)
472 goto alloc_mem_err;
473
0f31f994 474 memset(bp->status_blk, 0, bp->status_stats_size);
b6016b76 475
0f31f994
MC		 476 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
477 status_blk_size);
b6016b76 478
0f31f994 479 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76
MC		 480
481 return 0;
482
483alloc_mem_err:
484 bnx2_free_mem(bp);
485 return -ENOMEM;
486}
487
e3648b3d
MC		 488static void
489bnx2_report_fw_link(struct bnx2 *bp)
490{
491 u32 fw_link_status = 0;
492
493 if (bp->link_up) {
494 u32 bmsr;
495
496 switch (bp->line_speed) {
497 case SPEED_10:
498 if (bp->duplex == DUPLEX_HALF)
499 fw_link_status = BNX2_LINK_STATUS_10HALF;
500 else
501 fw_link_status = BNX2_LINK_STATUS_10FULL;
502 break;
503 case SPEED_100:
504 if (bp->duplex == DUPLEX_HALF)
505 fw_link_status = BNX2_LINK_STATUS_100HALF;
506 else
507 fw_link_status = BNX2_LINK_STATUS_100FULL;
508 break;
509 case SPEED_1000:
510 if (bp->duplex == DUPLEX_HALF)
511 fw_link_status = BNX2_LINK_STATUS_1000HALF;
512 else
513 fw_link_status = BNX2_LINK_STATUS_1000FULL;
514 break;
515 case SPEED_2500:
516 if (bp->duplex == DUPLEX_HALF)
517 fw_link_status = BNX2_LINK_STATUS_2500HALF;
518 else
519 fw_link_status = BNX2_LINK_STATUS_2500FULL;
520 break;
521 }
522
523 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
524
525 if (bp->autoneg) {
526 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
527
528 bnx2_read_phy(bp, MII_BMSR, &bmsr);
529 bnx2_read_phy(bp, MII_BMSR, &bmsr);
530
531 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
532 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
533 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
534 else
535 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
536 }
537 }
538 else
539 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
540
541 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
542}
543
b6016b76
MC		 544static void
545bnx2_report_link(struct bnx2 *bp)
546{
547 if (bp->link_up) {
548 netif_carrier_on(bp->dev);
549 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
550
551 printk("%d Mbps ", bp->line_speed);
552
553 if (bp->duplex == DUPLEX_FULL)
554 printk("full duplex");
555 else
556 printk("half duplex");
557
558 if (bp->flow_ctrl) {
559 if (bp->flow_ctrl & FLOW_CTRL_RX) {
560 printk(", receive ");
561 if (bp->flow_ctrl & FLOW_CTRL_TX)
562 printk("& transmit ");
563 }
564 else {
565 printk(", transmit ");
566 }
567 printk("flow control ON");
568 }
569 printk("\n");
570 }
571 else {
572 netif_carrier_off(bp->dev);
573 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
574 }
e3648b3d
MC		 575
576 bnx2_report_fw_link(bp);
b6016b76
MC		 577}
578
579static void
580bnx2_resolve_flow_ctrl(struct bnx2 *bp)
581{
582 u32 local_adv, remote_adv;
583
584 bp->flow_ctrl = 0;
585 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
586 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
587
588 if (bp->duplex == DUPLEX_FULL) {
589 bp->flow_ctrl = bp->req_flow_ctrl;
590 }
591 return;
592 }
593
594 if (bp->duplex != DUPLEX_FULL) {
595 return;
596 }
597
5b0c76ad
MC		 598 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
599 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
600 u32 val;
601
602 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
603 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
604 bp->flow_ctrl |= FLOW_CTRL_TX;
605 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
606 bp->flow_ctrl |= FLOW_CTRL_RX;
607 return;
608 }
609
b6016b76
MC		 610 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
611 bnx2_read_phy(bp, MII_LPA, &remote_adv);
612
613 if (bp->phy_flags & PHY_SERDES_FLAG) {
614 u32 new_local_adv = 0;
615 u32 new_remote_adv = 0;
616
617 if (local_adv & ADVERTISE_1000XPAUSE)
618 new_local_adv |= ADVERTISE_PAUSE_CAP;
619 if (local_adv & ADVERTISE_1000XPSE_ASYM)
620 new_local_adv |= ADVERTISE_PAUSE_ASYM;
621 if (remote_adv & ADVERTISE_1000XPAUSE)
622 new_remote_adv |= ADVERTISE_PAUSE_CAP;
623 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
624 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
625
626 local_adv = new_local_adv;
627 remote_adv = new_remote_adv;
628 }
629
630 /* See Table 28B-3 of 802.3ab-1999 spec. */
631 if (local_adv & ADVERTISE_PAUSE_CAP) {
632 if(local_adv & ADVERTISE_PAUSE_ASYM) {
633 if (remote_adv & ADVERTISE_PAUSE_CAP) {
634 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
635 }
636 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
637 bp->flow_ctrl = FLOW_CTRL_RX;
638 }
639 }
640 else {
641 if (remote_adv & ADVERTISE_PAUSE_CAP) {
642 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
643 }
644 }
645 }
646 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
647 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
648 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
649
650 bp->flow_ctrl = FLOW_CTRL_TX;
651 }
652 }
653}
654
655static int
5b0c76ad
MC		 656bnx2_5708s_linkup(struct bnx2 *bp)
657{
658 u32 val;
659
660 bp->link_up = 1;
661 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
662 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
663 case BCM5708S_1000X_STAT1_SPEED_10:
664 bp->line_speed = SPEED_10;
665 break;
666 case BCM5708S_1000X_STAT1_SPEED_100:
667 bp->line_speed = SPEED_100;
668 break;
669 case BCM5708S_1000X_STAT1_SPEED_1G:
670 bp->line_speed = SPEED_1000;
671 break;
672 case BCM5708S_1000X_STAT1_SPEED_2G5:
673 bp->line_speed = SPEED_2500;
674 break;
675 }
676 if (val & BCM5708S_1000X_STAT1_FD)
677 bp->duplex = DUPLEX_FULL;
678 else
679 bp->duplex = DUPLEX_HALF;
680
681 return 0;
682}
683
684static int
685bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 686{
687 u32 bmcr, local_adv, remote_adv, common;
688
689 bp->link_up = 1;
690 bp->line_speed = SPEED_1000;
691
692 bnx2_read_phy(bp, MII_BMCR, &bmcr);
693 if (bmcr & BMCR_FULLDPLX) {
694 bp->duplex = DUPLEX_FULL;
695 }
696 else {
697 bp->duplex = DUPLEX_HALF;
698 }
699
700 if (!(bmcr & BMCR_ANENABLE)) {
701 return 0;
702 }
703
704 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
705 bnx2_read_phy(bp, MII_LPA, &remote_adv);
706
707 common = local_adv & remote_adv;
708 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
709
710 if (common & ADVERTISE_1000XFULL) {
711 bp->duplex = DUPLEX_FULL;
712 }
713 else {
714 bp->duplex = DUPLEX_HALF;
715 }
716 }
717
718 return 0;
719}
720
721static int
722bnx2_copper_linkup(struct bnx2 *bp)
723{
724 u32 bmcr;
725
726 bnx2_read_phy(bp, MII_BMCR, &bmcr);
727 if (bmcr & BMCR_ANENABLE) {
728 u32 local_adv, remote_adv, common;
729
730 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
731 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
732
733 common = local_adv & (remote_adv >> 2);
734 if (common & ADVERTISE_1000FULL) {
735 bp->line_speed = SPEED_1000;
736 bp->duplex = DUPLEX_FULL;
737 }
738 else if (common & ADVERTISE_1000HALF) {
739 bp->line_speed = SPEED_1000;
740 bp->duplex = DUPLEX_HALF;
741 }
742 else {
743 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
744 bnx2_read_phy(bp, MII_LPA, &remote_adv);
745
746 common = local_adv & remote_adv;
747 if (common & ADVERTISE_100FULL) {
748 bp->line_speed = SPEED_100;
749 bp->duplex = DUPLEX_FULL;
750 }
751 else if (common & ADVERTISE_100HALF) {
752 bp->line_speed = SPEED_100;
753 bp->duplex = DUPLEX_HALF;
754 }
755 else if (common & ADVERTISE_10FULL) {
756 bp->line_speed = SPEED_10;
757 bp->duplex = DUPLEX_FULL;
758 }
759 else if (common & ADVERTISE_10HALF) {
760 bp->line_speed = SPEED_10;
761 bp->duplex = DUPLEX_HALF;
762 }
763 else {
764 bp->line_speed = 0;
765 bp->link_up = 0;
766 }
767 }
768 }
769 else {
770 if (bmcr & BMCR_SPEED100) {
771 bp->line_speed = SPEED_100;
772 }
773 else {
774 bp->line_speed = SPEED_10;
775 }
776 if (bmcr & BMCR_FULLDPLX) {
777 bp->duplex = DUPLEX_FULL;
778 }
779 else {
780 bp->duplex = DUPLEX_HALF;
781 }
782 }
783
784 return 0;
785}
786
787static int
788bnx2_set_mac_link(struct bnx2 *bp)
789{
790 u32 val;
791
792 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
793 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
794 (bp->duplex == DUPLEX_HALF)) {
795 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
796 }
797
798 /* Configure the EMAC mode register. */
799 val = REG_RD(bp, BNX2_EMAC_MODE);
800
801 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad
MC		 802 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
803 BNX2_EMAC_MODE_25G);
b6016b76
MC		 804
805 if (bp->link_up) {
5b0c76ad
MC		 806 switch (bp->line_speed) {
807 case SPEED_10:
808 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
809 val |= BNX2_EMAC_MODE_PORT_MII_10;
810 break;
811 }
812 /* fall through */
813 case SPEED_100:
814 val |= BNX2_EMAC_MODE_PORT_MII;
815 break;
816 case SPEED_2500:
817 val |= BNX2_EMAC_MODE_25G;
818 /* fall through */
819 case SPEED_1000:
820 val |= BNX2_EMAC_MODE_PORT_GMII;
821 break;
822 }
b6016b76
MC		 823 }
824 else {
825 val |= BNX2_EMAC_MODE_PORT_GMII;
826 }
827
828 /* Set the MAC to operate in the appropriate duplex mode. */
829 if (bp->duplex == DUPLEX_HALF)
830 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
831 REG_WR(bp, BNX2_EMAC_MODE, val);
832
833 /* Enable/disable rx PAUSE. */
834 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
835
836 if (bp->flow_ctrl & FLOW_CTRL_RX)
837 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
838 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
839
840 /* Enable/disable tx PAUSE. */
841 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
842 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
843
844 if (bp->flow_ctrl & FLOW_CTRL_TX)
845 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
846 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
847
848 /* Acknowledge the interrupt. */
849 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
850
851 return 0;
852}
853
854static int
855bnx2_set_link(struct bnx2 *bp)
856{
857 u32 bmsr;
858 u8 link_up;
859
860 if (bp->loopback == MAC_LOOPBACK) {
861 bp->link_up = 1;
862 return 0;
863 }
864
865 link_up = bp->link_up;
866
867 bnx2_read_phy(bp, MII_BMSR, &bmsr);
868 bnx2_read_phy(bp, MII_BMSR, &bmsr);
869
870 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
871 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
872 u32 val;
873
874 val = REG_RD(bp, BNX2_EMAC_STATUS);
875 if (val & BNX2_EMAC_STATUS_LINK)
876 bmsr |= BMSR_LSTATUS;
877 else
878 bmsr &= ~BMSR_LSTATUS;
879 }
880
881 if (bmsr & BMSR_LSTATUS) {
882 bp->link_up = 1;
883
884 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 885 if (CHIP_NUM(bp) == CHIP_NUM_5706)
886 bnx2_5706s_linkup(bp);
887 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
888 bnx2_5708s_linkup(bp);
b6016b76
MC		 889 }
890 else {
891 bnx2_copper_linkup(bp);
892 }
893 bnx2_resolve_flow_ctrl(bp);
894 }
895 else {
896 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
897 (bp->autoneg & AUTONEG_SPEED)) {
898
899 u32 bmcr;
900
901 bnx2_read_phy(bp, MII_BMCR, &bmcr);
902 if (!(bmcr & BMCR_ANENABLE)) {
903 bnx2_write_phy(bp, MII_BMCR, bmcr |
904 BMCR_ANENABLE);
905 }
906 }
907 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
908 bp->link_up = 0;
909 }
910
911 if (bp->link_up != link_up) {
912 bnx2_report_link(bp);
913 }
914
915 bnx2_set_mac_link(bp);
916
917 return 0;
918}
919
920static int
921bnx2_reset_phy(struct bnx2 *bp)
922{
923 int i;
924 u32 reg;
925
926 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
927
928#define PHY_RESET_MAX_WAIT 100
929 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
930 udelay(10);
931
932 bnx2_read_phy(bp, MII_BMCR, &reg);
933 if (!(reg & BMCR_RESET)) {
934 udelay(20);
935 break;
936 }
937 }
938 if (i == PHY_RESET_MAX_WAIT) {
939 return -EBUSY;
940 }
941 return 0;
942}
943
944static u32
945bnx2_phy_get_pause_adv(struct bnx2 *bp)
946{
947 u32 adv = 0;
948
949 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
950 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
951
952 if (bp->phy_flags & PHY_SERDES_FLAG) {
953 adv = ADVERTISE_1000XPAUSE;
954 }
955 else {
956 adv = ADVERTISE_PAUSE_CAP;
957 }
958 }
959 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
960 if (bp->phy_flags & PHY_SERDES_FLAG) {
961 adv = ADVERTISE_1000XPSE_ASYM;
962 }
963 else {
964 adv = ADVERTISE_PAUSE_ASYM;
965 }
966 }
967 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
968 if (bp->phy_flags & PHY_SERDES_FLAG) {
969 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
970 }
971 else {
972 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
973 }
974 }
975 return adv;
976}
977
978static int
979bnx2_setup_serdes_phy(struct bnx2 *bp)
980{
5b0c76ad 981 u32 adv, bmcr, up1;
b6016b76
MC		 982 u32 new_adv = 0;
983
984 if (!(bp->autoneg & AUTONEG_SPEED)) {
985 u32 new_bmcr;
5b0c76ad
MC		 986 int force_link_down = 0;
987
988 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
989 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
990 if (up1 & BCM5708S_UP1_2G5) {
991 up1 &= ~BCM5708S_UP1_2G5;
992 bnx2_write_phy(bp, BCM5708S_UP1, up1);
993 force_link_down = 1;
994 }
995 }
996
997 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
998 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
b6016b76
MC		 999
1000 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1001 new_bmcr = bmcr & ~BMCR_ANENABLE;
1002 new_bmcr |= BMCR_SPEED1000;
1003 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1004 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1005 new_bmcr |= BMCR_FULLDPLX;
1006 }
1007 else {
5b0c76ad 1008 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1009 new_bmcr &= ~BMCR_FULLDPLX;
1010 }
5b0c76ad 1011 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1012 /* Force a link down visible on the other side */
1013 if (bp->link_up) {
5b0c76ad
MC		 1014 bnx2_write_phy(bp, MII_ADVERTISE, adv &
1015 ~(ADVERTISE_1000XFULL |
1016 ADVERTISE_1000XHALF));
b6016b76
MC		 1017 bnx2_write_phy(bp, MII_BMCR, bmcr |
1018 BMCR_ANRESTART | BMCR_ANENABLE);
1019
1020 bp->link_up = 0;
1021 netif_carrier_off(bp->dev);
5b0c76ad 1022 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
b6016b76 1023 }
5b0c76ad 1024 bnx2_write_phy(bp, MII_ADVERTISE, adv);
b6016b76
MC		 1025 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1026 }
1027 return 0;
1028 }
1029
5b0c76ad
MC		 1030 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1031 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1032 up1 |= BCM5708S_UP1_2G5;
1033 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1034 }
1035
b6016b76
MC		 1036 if (bp->advertising & ADVERTISED_1000baseT_Full)
1037 new_adv |= ADVERTISE_1000XFULL;
1038
1039 new_adv |= bnx2_phy_get_pause_adv(bp);
1040
1041 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1042 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1043
1044 bp->serdes_an_pending = 0;
1045 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1046 /* Force a link down visible on the other side */
1047 if (bp->link_up) {
1048 int i;
1049
1050 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1051 for (i = 0; i < 110; i++) {
1052 udelay(100);
1053 }
1054 }
1055
1056 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1057 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1058 BMCR_ANENABLE);
cd339a0e
MC		 1059 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1060 /* Speed up link-up time when the link partner
1061 * does not autonegotiate which is very common
1062 * in blade servers. Some blade servers use
1063 * IPMI for kerboard input and it's important
1064 * to minimize link disruptions. Autoneg. involves
1065 * exchanging base pages plus 3 next pages and
1066 * normally completes in about 120 msec.
1067 */
1068 bp->current_interval = SERDES_AN_TIMEOUT;
1069 bp->serdes_an_pending = 1;
1070 mod_timer(&bp->timer, jiffies + bp->current_interval);
1071 }
b6016b76
MC		 1072 }
1073
1074 return 0;
1075}
1076
1077#define ETHTOOL_ALL_FIBRE_SPEED \
1078 (ADVERTISED_1000baseT_Full)
1079
1080#define ETHTOOL_ALL_COPPER_SPEED \
1081 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1082 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1083 ADVERTISED_1000baseT_Full)
1084
1085#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1086 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1087
1088#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1089
1090static int
1091bnx2_setup_copper_phy(struct bnx2 *bp)
1092{
1093 u32 bmcr;
1094 u32 new_bmcr;
1095
1096 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1097
1098 if (bp->autoneg & AUTONEG_SPEED) {
1099 u32 adv_reg, adv1000_reg;
1100 u32 new_adv_reg = 0;
1101 u32 new_adv1000_reg = 0;
1102
1103 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1104 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1105 ADVERTISE_PAUSE_ASYM);
1106
1107 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1108 adv1000_reg &= PHY_ALL_1000_SPEED;
1109
1110 if (bp->advertising & ADVERTISED_10baseT_Half)
1111 new_adv_reg |= ADVERTISE_10HALF;
1112 if (bp->advertising & ADVERTISED_10baseT_Full)
1113 new_adv_reg |= ADVERTISE_10FULL;
1114 if (bp->advertising & ADVERTISED_100baseT_Half)
1115 new_adv_reg |= ADVERTISE_100HALF;
1116 if (bp->advertising & ADVERTISED_100baseT_Full)
1117 new_adv_reg |= ADVERTISE_100FULL;
1118 if (bp->advertising & ADVERTISED_1000baseT_Full)
1119 new_adv1000_reg |= ADVERTISE_1000FULL;
1120
1121 new_adv_reg |= ADVERTISE_CSMA;
1122
1123 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1124
1125 if ((adv1000_reg != new_adv1000_reg) ||
1126 (adv_reg != new_adv_reg) ||
1127 ((bmcr & BMCR_ANENABLE) == 0)) {
1128
1129 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1130 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1131 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1132 BMCR_ANENABLE);
1133 }
1134 else if (bp->link_up) {
1135 /* Flow ctrl may have changed from auto to forced */
1136 /* or vice-versa. */
1137
1138 bnx2_resolve_flow_ctrl(bp);
1139 bnx2_set_mac_link(bp);
1140 }
1141 return 0;
1142 }
1143
1144 new_bmcr = 0;
1145 if (bp->req_line_speed == SPEED_100) {
1146 new_bmcr |= BMCR_SPEED100;
1147 }
1148 if (bp->req_duplex == DUPLEX_FULL) {
1149 new_bmcr |= BMCR_FULLDPLX;
1150 }
1151 if (new_bmcr != bmcr) {
1152 u32 bmsr;
1153 int i = 0;
1154
1155 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1156 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1157
1158 if (bmsr & BMSR_LSTATUS) {
1159 /* Force link down */
1160 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1161 do {
1162 udelay(100);
1163 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1164 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1165 i++;
1166 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1167 }
1168
1169 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1170
1171 /* Normally, the new speed is setup after the link has
1172 * gone down and up again. In some cases, link will not go
1173 * down so we need to set up the new speed here.
1174 */
1175 if (bmsr & BMSR_LSTATUS) {
1176 bp->line_speed = bp->req_line_speed;
1177 bp->duplex = bp->req_duplex;
1178 bnx2_resolve_flow_ctrl(bp);
1179 bnx2_set_mac_link(bp);
1180 }
1181 }
1182 return 0;
1183}
1184
1185static int
1186bnx2_setup_phy(struct bnx2 *bp)
1187{
1188 if (bp->loopback == MAC_LOOPBACK)
1189 return 0;
1190
1191 if (bp->phy_flags & PHY_SERDES_FLAG) {
1192 return (bnx2_setup_serdes_phy(bp));
1193 }
1194 else {
1195 return (bnx2_setup_copper_phy(bp));
1196 }
1197}
1198
1199static int
5b0c76ad
MC		 1200bnx2_init_5708s_phy(struct bnx2 *bp)
1201{
1202 u32 val;
1203
1204 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1205 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1206 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1207
1208 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1209 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1210 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1211
1212 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1213 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1214 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1215
1216 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1217 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1218 val |= BCM5708S_UP1_2G5;
1219 bnx2_write_phy(bp, BCM5708S_UP1, val);
1220 }
1221
1222 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1223 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1224 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1225 /* increase tx signal amplitude */
1226 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1227 BCM5708S_BLK_ADDR_TX_MISC);
1228 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1229 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1230 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1231 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1232 }
1233
e3648b3d 1234 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1235 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1236
1237 if (val) {
1238 u32 is_backplane;
1239
e3648b3d 1240 is_backplane = REG_RD_IND(bp, bp->shmem_base +
5b0c76ad
MC		 1241 BNX2_SHARED_HW_CFG_CONFIG);
1242 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1243 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1244 BCM5708S_BLK_ADDR_TX_MISC);
1245 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1246 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1247 BCM5708S_BLK_ADDR_DIG);
1248 }
1249 }
1250 return 0;
1251}
1252
1253static int
1254bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76
MC		 1255{
1256 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1257
1258 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1259 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1260 }
1261
1262 if (bp->dev->mtu > 1500) {
1263 u32 val;
1264
1265 /* Set extended packet length bit */
1266 bnx2_write_phy(bp, 0x18, 0x7);
1267 bnx2_read_phy(bp, 0x18, &val);
1268 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1269
1270 bnx2_write_phy(bp, 0x1c, 0x6c00);
1271 bnx2_read_phy(bp, 0x1c, &val);
1272 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1273 }
1274 else {
1275 u32 val;
1276
1277 bnx2_write_phy(bp, 0x18, 0x7);
1278 bnx2_read_phy(bp, 0x18, &val);
1279 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1280
1281 bnx2_write_phy(bp, 0x1c, 0x6c00);
1282 bnx2_read_phy(bp, 0x1c, &val);
1283 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1284 }
1285
1286 return 0;
1287}
1288
1289static int
1290bnx2_init_copper_phy(struct bnx2 *bp)
1291{
5b0c76ad
MC		 1292 u32 val;
1293
b6016b76
MC		 1294 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1295
1296 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1297 bnx2_write_phy(bp, 0x18, 0x0c00);
1298 bnx2_write_phy(bp, 0x17, 0x000a);
1299 bnx2_write_phy(bp, 0x15, 0x310b);
1300 bnx2_write_phy(bp, 0x17, 0x201f);
1301 bnx2_write_phy(bp, 0x15, 0x9506);
1302 bnx2_write_phy(bp, 0x17, 0x401f);
1303 bnx2_write_phy(bp, 0x15, 0x14e2);
1304 bnx2_write_phy(bp, 0x18, 0x0400);
1305 }
1306
1307 if (bp->dev->mtu > 1500) {
b6016b76
MC		 1308 /* Set extended packet length bit */
1309 bnx2_write_phy(bp, 0x18, 0x7);
1310 bnx2_read_phy(bp, 0x18, &val);
1311 bnx2_write_phy(bp, 0x18, val | 0x4000);
1312
1313 bnx2_read_phy(bp, 0x10, &val);
1314 bnx2_write_phy(bp, 0x10, val | 0x1);
1315 }
1316 else {
b6016b76
MC		 1317 bnx2_write_phy(bp, 0x18, 0x7);
1318 bnx2_read_phy(bp, 0x18, &val);
1319 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1320
1321 bnx2_read_phy(bp, 0x10, &val);
1322 bnx2_write_phy(bp, 0x10, val & ~0x1);
1323 }
1324
5b0c76ad
MC		 1325 /* ethernet@wirespeed */
1326 bnx2_write_phy(bp, 0x18, 0x7007);
1327 bnx2_read_phy(bp, 0x18, &val);
1328 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 1329 return 0;
1330}
1331
1332
1333static int
1334bnx2_init_phy(struct bnx2 *bp)
1335{
1336 u32 val;
1337 int rc = 0;
1338
1339 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1340 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1341
1342 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1343
1344 bnx2_reset_phy(bp);
1345
1346 bnx2_read_phy(bp, MII_PHYSID1, &val);
1347 bp->phy_id = val << 16;
1348 bnx2_read_phy(bp, MII_PHYSID2, &val);
1349 bp->phy_id |= val & 0xffff;
1350
1351 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 1352 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1353 rc = bnx2_init_5706s_phy(bp);
1354 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1355 rc = bnx2_init_5708s_phy(bp);
b6016b76
MC		 1356 }
1357 else {
1358 rc = bnx2_init_copper_phy(bp);
1359 }
1360
1361 bnx2_setup_phy(bp);
1362
1363 return rc;
1364}
1365
1366static int
1367bnx2_set_mac_loopback(struct bnx2 *bp)
1368{
1369 u32 mac_mode;
1370
1371 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1372 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1373 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1374 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1375 bp->link_up = 1;
1376 return 0;
1377}
1378
bc5a0690
MC		 1379static int bnx2_test_link(struct bnx2 *);
1380
1381static int
1382bnx2_set_phy_loopback(struct bnx2 *bp)
1383{
1384 u32 mac_mode;
1385 int rc, i;
1386
1387 spin_lock_bh(&bp->phy_lock);
1388 rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1389 BMCR_SPEED1000);
1390 spin_unlock_bh(&bp->phy_lock);
1391 if (rc)
1392 return rc;
1393
1394 for (i = 0; i < 10; i++) {
1395 if (bnx2_test_link(bp) == 0)
1396 break;
1397 udelay(10);
1398 }
1399
1400 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1401 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1402 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1403 BNX2_EMAC_MODE_25G);
1404
1405 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1406 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1407 bp->link_up = 1;
1408 return 0;
1409}
1410
b6016b76 1411static int
b090ae2b 1412bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 1413{
1414 int i;
1415 u32 val;
1416
b6016b76
MC		 1417 bp->fw_wr_seq++;
1418 msg_data |= bp->fw_wr_seq;
1419
e3648b3d 1420 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76
MC		 1421
1422 /* wait for an acknowledgement. */
b090ae2b
MC		 1423 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1424 msleep(10);
b6016b76 1425
e3648b3d 1426 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
b6016b76
MC		 1427
1428 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1429 break;
1430 }
b090ae2b
MC		 1431 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1432 return 0;
b6016b76
MC		 1433
1434 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 1435 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1436 if (!silent)
1437 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1438 "%x\n", msg_data);
b6016b76
MC		 1439
1440 msg_data &= ~BNX2_DRV_MSG_CODE;
1441 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1442
e3648b3d 1443 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76 1444
b6016b76
MC		 1445 return -EBUSY;
1446 }
1447
b090ae2b
MC		 1448 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1449 return -EIO;
1450
b6016b76
MC		 1451 return 0;
1452}
1453
1454static void
1455bnx2_init_context(struct bnx2 *bp)
1456{
1457 u32 vcid;
1458
1459 vcid = 96;
1460 while (vcid) {
1461 u32 vcid_addr, pcid_addr, offset;
1462
1463 vcid--;
1464
1465 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1466 u32 new_vcid;
1467
1468 vcid_addr = GET_PCID_ADDR(vcid);
1469 if (vcid & 0x8) {
1470 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1471 }
1472 else {
1473 new_vcid = vcid;
1474 }
1475 pcid_addr = GET_PCID_ADDR(new_vcid);
1476 }
1477 else {
1478 vcid_addr = GET_CID_ADDR(vcid);
1479 pcid_addr = vcid_addr;
1480 }
1481
1482 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1483 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1484
1485 /* Zero out the context. */
1486 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1487 CTX_WR(bp, 0x00, offset, 0);
1488 }
1489
1490 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1491 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1492 }
1493}
1494
1495static int
1496bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1497{
1498 u16 *good_mbuf;
1499 u32 good_mbuf_cnt;
1500 u32 val;
1501
1502 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1503 if (good_mbuf == NULL) {
1504 printk(KERN_ERR PFX "Failed to allocate memory in "
1505 "bnx2_alloc_bad_rbuf\n");
1506 return -ENOMEM;
1507 }
1508
1509 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1510 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1511
1512 good_mbuf_cnt = 0;
1513
1514 /* Allocate a bunch of mbufs and save the good ones in an array. */
1515 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1516 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1517 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1518
1519 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1520
1521 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1522
1523 /* The addresses with Bit 9 set are bad memory blocks. */
1524 if (!(val & (1 << 9))) {
1525 good_mbuf[good_mbuf_cnt] = (u16) val;
1526 good_mbuf_cnt++;
1527 }
1528
1529 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1530 }
1531
1532 /* Free the good ones back to the mbuf pool thus discarding
1533 * all the bad ones. */
1534 while (good_mbuf_cnt) {
1535 good_mbuf_cnt--;
1536
1537 val = good_mbuf[good_mbuf_cnt];
1538 val = (val << 9) | val | 1;
1539
1540 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1541 }
1542 kfree(good_mbuf);
1543 return 0;
1544}
1545
1546static void
1547bnx2_set_mac_addr(struct bnx2 *bp)
1548{
1549 u32 val;
1550 u8 *mac_addr = bp->dev->dev_addr;
1551
1552 val = (mac_addr[0] << 8) | mac_addr[1];
1553
1554 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1555
1556 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1557 (mac_addr[4] << 8) | mac_addr[5];
1558
1559 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1560}
1561
1562static inline int
1563bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1564{
1565 struct sk_buff *skb;
1566 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1567 dma_addr_t mapping;
13daffa2 1568 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 1569 unsigned long align;
1570
1571 skb = dev_alloc_skb(bp->rx_buf_size);
1572 if (skb == NULL) {
1573 return -ENOMEM;
1574 }
1575
1576 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1577 skb_reserve(skb, 8 - align);
1578 }
1579
1580 skb->dev = bp->dev;
1581 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1582 PCI_DMA_FROMDEVICE);
1583
1584 rx_buf->skb = skb;
1585 pci_unmap_addr_set(rx_buf, mapping, mapping);
1586
1587 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1588 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1589
1590 bp->rx_prod_bseq += bp->rx_buf_use_size;
1591
1592 return 0;
1593}
1594
1595static void
1596bnx2_phy_int(struct bnx2 *bp)
1597{
1598 u32 new_link_state, old_link_state;
1599
1600 new_link_state = bp->status_blk->status_attn_bits &
1601 STATUS_ATTN_BITS_LINK_STATE;
1602 old_link_state = bp->status_blk->status_attn_bits_ack &
1603 STATUS_ATTN_BITS_LINK_STATE;
1604 if (new_link_state != old_link_state) {
1605 if (new_link_state) {
1606 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1607 STATUS_ATTN_BITS_LINK_STATE);
1608 }
1609 else {
1610 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1611 STATUS_ATTN_BITS_LINK_STATE);
1612 }
1613 bnx2_set_link(bp);
1614 }
1615}
1616
1617static void
1618bnx2_tx_int(struct bnx2 *bp)
1619{
f4e418f7 1620 struct status_block *sblk = bp->status_blk;
b6016b76
MC		 1621 u16 hw_cons, sw_cons, sw_ring_cons;
1622 int tx_free_bd = 0;
1623
f4e418f7 1624 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
b6016b76
MC		 1625 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1626 hw_cons++;
1627 }
1628 sw_cons = bp->tx_cons;
1629
1630 while (sw_cons != hw_cons) {
1631 struct sw_bd *tx_buf;
1632 struct sk_buff *skb;
1633 int i, last;
1634
1635 sw_ring_cons = TX_RING_IDX(sw_cons);
1636
1637 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1638 skb = tx_buf->skb;
1639#ifdef BCM_TSO
1640 /* partial BD completions possible with TSO packets */
1641 if (skb_shinfo(skb)->tso_size) {
1642 u16 last_idx, last_ring_idx;
1643
1644 last_idx = sw_cons +
1645 skb_shinfo(skb)->nr_frags + 1;
1646 last_ring_idx = sw_ring_cons +
1647 skb_shinfo(skb)->nr_frags + 1;
1648 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1649 last_idx++;
1650 }
1651 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1652 break;
1653 }
1654 }
1655#endif
1656 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1657 skb_headlen(skb), PCI_DMA_TODEVICE);
1658
1659 tx_buf->skb = NULL;
1660 last = skb_shinfo(skb)->nr_frags;
1661
1662 for (i = 0; i < last; i++) {
1663 sw_cons = NEXT_TX_BD(sw_cons);
1664
1665 pci_unmap_page(bp->pdev,
1666 pci_unmap_addr(
1667 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1668 mapping),
1669 skb_shinfo(skb)->frags[i].size,
1670 PCI_DMA_TODEVICE);
1671 }
1672
1673 sw_cons = NEXT_TX_BD(sw_cons);
1674
1675 tx_free_bd += last + 1;
1676
1677 dev_kfree_skb_irq(skb);
1678
f4e418f7
MC		 1679 hw_cons = bp->hw_tx_cons =
1680 sblk->status_tx_quick_consumer_index0;
1681
b6016b76
MC		 1682 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1683 hw_cons++;
1684 }
1685 }
1686
e89bbf10 1687 bp->tx_cons = sw_cons;
b6016b76
MC		 1688
1689 if (unlikely(netif_queue_stopped(bp->dev))) {
c770a65c 1690 spin_lock(&bp->tx_lock);
b6016b76 1691 if ((netif_queue_stopped(bp->dev)) &&
e89bbf10 1692 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
b6016b76
MC		 1693
1694 netif_wake_queue(bp->dev);
1695 }
c770a65c 1696 spin_unlock(&bp->tx_lock);
b6016b76 1697 }
b6016b76
MC		 1698}
1699
1700static inline void
1701bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1702 u16 cons, u16 prod)
1703{
236b6394
MC		 1704 struct sw_bd *cons_rx_buf, *prod_rx_buf;
1705 struct rx_bd *cons_bd, *prod_bd;
1706
1707 cons_rx_buf = &bp->rx_buf_ring[cons];
1708 prod_rx_buf = &bp->rx_buf_ring[prod];
b6016b76
MC		 1709
1710 pci_dma_sync_single_for_device(bp->pdev,
1711 pci_unmap_addr(cons_rx_buf, mapping),
1712 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1713
236b6394 1714 bp->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 1715
236b6394 1716 prod_rx_buf->skb = skb;
b6016b76 1717
236b6394
MC		 1718 if (cons == prod)
1719 return;
b6016b76 1720
236b6394
MC		 1721 pci_unmap_addr_set(prod_rx_buf, mapping,
1722 pci_unmap_addr(cons_rx_buf, mapping));
1723
3fdfcc2c
MC		 1724 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
1725 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 1726 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
1727 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 1728}
1729
1730static int
1731bnx2_rx_int(struct bnx2 *bp, int budget)
1732{
f4e418f7 1733 struct status_block *sblk = bp->status_blk;
b6016b76
MC		 1734 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1735 struct l2_fhdr *rx_hdr;
1736 int rx_pkt = 0;
1737
f4e418f7 1738 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
b6016b76
MC		 1739 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1740 hw_cons++;
1741 }
1742 sw_cons = bp->rx_cons;
1743 sw_prod = bp->rx_prod;
1744
1745 /* Memory barrier necessary as speculative reads of the rx
1746 * buffer can be ahead of the index in the status block
1747 */
1748 rmb();
1749 while (sw_cons != hw_cons) {
1750 unsigned int len;
ade2bfe7 1751 u32 status;
b6016b76
MC		 1752 struct sw_bd *rx_buf;
1753 struct sk_buff *skb;
236b6394 1754 dma_addr_t dma_addr;
b6016b76
MC		 1755
1756 sw_ring_cons = RX_RING_IDX(sw_cons);
1757 sw_ring_prod = RX_RING_IDX(sw_prod);
1758
1759 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1760 skb = rx_buf->skb;
236b6394
MC		 1761
1762 rx_buf->skb = NULL;
1763
1764 dma_addr = pci_unmap_addr(rx_buf, mapping);
1765
1766 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
b6016b76
MC		 1767 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1768
1769 rx_hdr = (struct l2_fhdr *) skb->data;
1770 len = rx_hdr->l2_fhdr_pkt_len - 4;
1771
ade2bfe7 1772 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 1773 (L2_FHDR_ERRORS_BAD_CRC |
1774 L2_FHDR_ERRORS_PHY_DECODE |
1775 L2_FHDR_ERRORS_ALIGNMENT |
1776 L2_FHDR_ERRORS_TOO_SHORT |
1777 L2_FHDR_ERRORS_GIANT_FRAME)) {
1778
1779 goto reuse_rx;
1780 }
1781
1782 /* Since we don't have a jumbo ring, copy small packets
1783 * if mtu > 1500
1784 */
1785 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1786 struct sk_buff *new_skb;
1787
1788 new_skb = dev_alloc_skb(len + 2);
1789 if (new_skb == NULL)
1790 goto reuse_rx;
1791
1792 /* aligned copy */
1793 memcpy(new_skb->data,
1794 skb->data + bp->rx_offset - 2,
1795 len + 2);
1796
1797 skb_reserve(new_skb, 2);
1798 skb_put(new_skb, len);
1799 new_skb->dev = bp->dev;
1800
1801 bnx2_reuse_rx_skb(bp, skb,
1802 sw_ring_cons, sw_ring_prod);
1803
1804 skb = new_skb;
1805 }
1806 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
236b6394 1807 pci_unmap_single(bp->pdev, dma_addr,
b6016b76
MC		 1808 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1809
1810 skb_reserve(skb, bp->rx_offset);
1811 skb_put(skb, len);
1812 }
1813 else {
1814reuse_rx:
1815 bnx2_reuse_rx_skb(bp, skb,
1816 sw_ring_cons, sw_ring_prod);
1817 goto next_rx;
1818 }
1819
1820 skb->protocol = eth_type_trans(skb, bp->dev);
1821
1822 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 1823 (ntohs(skb->protocol) != 0x8100)) {
b6016b76
MC		 1824
1825 dev_kfree_skb_irq(skb);
1826 goto next_rx;
1827
1828 }
1829
b6016b76
MC		 1830 skb->ip_summed = CHECKSUM_NONE;
1831 if (bp->rx_csum &&
1832 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1833 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1834
ade2bfe7
MC		 1835 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1836 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 1837 skb->ip_summed = CHECKSUM_UNNECESSARY;
1838 }
1839
1840#ifdef BCM_VLAN
1841 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1842 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1843 rx_hdr->l2_fhdr_vlan_tag);
1844 }
1845 else
1846#endif
1847 netif_receive_skb(skb);
1848
1849 bp->dev->last_rx = jiffies;
1850 rx_pkt++;
1851
1852next_rx:
b6016b76
MC		 1853 sw_cons = NEXT_RX_BD(sw_cons);
1854 sw_prod = NEXT_RX_BD(sw_prod);
1855
1856 if ((rx_pkt == budget))
1857 break;
f4e418f7
MC		 1858
1859 /* Refresh hw_cons to see if there is new work */
1860 if (sw_cons == hw_cons) {
1861 hw_cons = bp->hw_rx_cons =
1862 sblk->status_rx_quick_consumer_index0;
1863 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1864 hw_cons++;
1865 rmb();
1866 }
b6016b76
MC		 1867 }
1868 bp->rx_cons = sw_cons;
1869 bp->rx_prod = sw_prod;
1870
1871 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1872
1873 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1874
1875 mmiowb();
1876
1877 return rx_pkt;
1878
1879}
1880
1881/* MSI ISR - The only difference between this and the INTx ISR
1882 * is that the MSI interrupt is always serviced.
1883 */
1884static irqreturn_t
1885bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1886{
1887 struct net_device *dev = dev_instance;
972ec0d4 1888 struct bnx2 *bp = netdev_priv(dev);
b6016b76 1889
c921e4c4 1890 prefetch(bp->status_blk);
b6016b76
MC		 1891 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1892 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1893 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1894
1895 /* Return here if interrupt is disabled. */
73eef4cd
MC		 1896 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1897 return IRQ_HANDLED;
b6016b76 1898
73eef4cd 1899 netif_rx_schedule(dev);
b6016b76 1900
73eef4cd 1901 return IRQ_HANDLED;
b6016b76
MC		 1902}
1903
1904static irqreturn_t
1905bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1906{
1907 struct net_device *dev = dev_instance;
972ec0d4 1908 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 1909
1910 /* When using INTx, it is possible for the interrupt to arrive
1911 * at the CPU before the status block posted prior to the
1912 * interrupt. Reading a register will flush the status block.
1913 * When using MSI, the MSI message will always complete after
1914 * the status block write.
1915 */
c921e4c4 1916 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
b6016b76
MC		 1917 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1918 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 1919 return IRQ_NONE;
b6016b76
MC		 1920
1921 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1922 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1923 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1924
1925 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 1926 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1927 return IRQ_HANDLED;
b6016b76 1928
73eef4cd 1929 netif_rx_schedule(dev);
b6016b76 1930
73eef4cd 1931 return IRQ_HANDLED;
b6016b76
MC		 1932}
1933
f4e418f7
MC		 1934static inline int
1935bnx2_has_work(struct bnx2 *bp)
1936{
1937 struct status_block *sblk = bp->status_blk;
1938
1939 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1940 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1941 return 1;
1942
1943 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1944 bp->link_up)
1945 return 1;
1946
1947 return 0;
1948}
1949
b6016b76
MC		 1950static int
1951bnx2_poll(struct net_device *dev, int *budget)
1952{
972ec0d4 1953 struct bnx2 *bp = netdev_priv(dev);
b6016b76 1954
b6016b76
MC		 1955 if ((bp->status_blk->status_attn_bits &
1956 STATUS_ATTN_BITS_LINK_STATE) !=
1957 (bp->status_blk->status_attn_bits_ack &
1958 STATUS_ATTN_BITS_LINK_STATE)) {
1959
c770a65c 1960 spin_lock(&bp->phy_lock);
b6016b76 1961 bnx2_phy_int(bp);
c770a65c 1962 spin_unlock(&bp->phy_lock);
bf5295bb
MC		 1963
1964 /* This is needed to take care of transient status
1965 * during link changes.
1966 */
1967 REG_WR(bp, BNX2_HC_COMMAND,
1968 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
1969 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 1970 }
1971
f4e418f7 1972 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
b6016b76 1973 bnx2_tx_int(bp);
b6016b76 1974
f4e418f7 1975 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
b6016b76
MC		 1976 int orig_budget = *budget;
1977 int work_done;
1978
1979 if (orig_budget > dev->quota)
1980 orig_budget = dev->quota;
1981
1982 work_done = bnx2_rx_int(bp, orig_budget);
1983 *budget -= work_done;
1984 dev->quota -= work_done;
b6016b76
MC		 1985 }
1986
f4e418f7
MC		 1987 bp->last_status_idx = bp->status_blk->status_idx;
1988 rmb();
1989
1990 if (!bnx2_has_work(bp)) {
b6016b76 1991 netif_rx_complete(dev);
1269a8a6
MC		 1992 if (likely(bp->flags & USING_MSI_FLAG)) {
1993 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1994 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1995 bp->last_status_idx);
1996 return 0;
1997 }
1998 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1999 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2000 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2001 bp->last_status_idx);
2002
b6016b76 2003 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1269a8a6
MC		 2004 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2005 bp->last_status_idx);
b6016b76
MC		 2006 return 0;
2007 }
2008
2009 return 1;
2010}
2011
932ff279 2012/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 2013 * from set_multicast.
2014 */
2015static void
2016bnx2_set_rx_mode(struct net_device *dev)
2017{
972ec0d4 2018 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 2019 u32 rx_mode, sort_mode;
2020 int i;
b6016b76 2021
c770a65c 2022 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 2023
2024 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2025 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2026 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2027#ifdef BCM_VLAN
e29054f9 2028 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
b6016b76 2029 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 2030#else
e29054f9
MC		 2031 if (!(bp->flags & ASF_ENABLE_FLAG))
2032 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 2033#endif
2034 if (dev->flags & IFF_PROMISC) {
2035 /* Promiscuous mode. */
2036 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2037 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
2038 }
2039 else if (dev->flags & IFF_ALLMULTI) {
2040 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2041 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2042 0xffffffff);
2043 }
2044 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2045 }
2046 else {
2047 /* Accept one or more multicast(s). */
2048 struct dev_mc_list *mclist;
2049 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2050 u32 regidx;
2051 u32 bit;
2052 u32 crc;
2053
2054 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2055
2056 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2057 i++, mclist = mclist->next) {
2058
2059 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2060 bit = crc & 0xff;
2061 regidx = (bit & 0xe0) >> 5;
2062 bit &= 0x1f;
2063 mc_filter[regidx] |= (1 << bit);
2064 }
2065
2066 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2067 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2068 mc_filter[i]);
2069 }
2070
2071 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2072 }
2073
2074 if (rx_mode != bp->rx_mode) {
2075 bp->rx_mode = rx_mode;
2076 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2077 }
2078
2079 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2080 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2081 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2082
c770a65c 2083 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 2084}
2085
2086static void
2087load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2088 u32 rv2p_proc)
2089{
2090 int i;
2091 u32 val;
2092
2093
2094 for (i = 0; i < rv2p_code_len; i += 8) {
2095 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
2096 rv2p_code++;
2097 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
2098 rv2p_code++;
2099
2100 if (rv2p_proc == RV2P_PROC1) {
2101 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2102 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2103 }
2104 else {
2105 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2106 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2107 }
2108 }
2109
2110 /* Reset the processor, un-stall is done later. */
2111 if (rv2p_proc == RV2P_PROC1) {
2112 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2113 }
2114 else {
2115 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2116 }
2117}
2118
2119static void
2120load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2121{
2122 u32 offset;
2123 u32 val;
2124
2125 /* Halt the CPU. */
2126 val = REG_RD_IND(bp, cpu_reg->mode);
2127 val |= cpu_reg->mode_value_halt;
2128 REG_WR_IND(bp, cpu_reg->mode, val);
2129 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2130
2131 /* Load the Text area. */
2132 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2133 if (fw->text) {
2134 int j;
2135
2136 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2137 REG_WR_IND(bp, offset, fw->text[j]);
2138 }
2139 }
2140
2141 /* Load the Data area. */
2142 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2143 if (fw->data) {
2144 int j;
2145
2146 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2147 REG_WR_IND(bp, offset, fw->data[j]);
2148 }
2149 }
2150
2151 /* Load the SBSS area. */
2152 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2153 if (fw->sbss) {
2154 int j;
2155
2156 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2157 REG_WR_IND(bp, offset, fw->sbss[j]);
2158 }
2159 }
2160
2161 /* Load the BSS area. */
2162 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2163 if (fw->bss) {
2164 int j;
2165
2166 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2167 REG_WR_IND(bp, offset, fw->bss[j]);
2168 }
2169 }
2170
2171 /* Load the Read-Only area. */
2172 offset = cpu_reg->spad_base +
2173 (fw->rodata_addr - cpu_reg->mips_view_base);
2174 if (fw->rodata) {
2175 int j;
2176
2177 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2178 REG_WR_IND(bp, offset, fw->rodata[j]);
2179 }
2180 }
2181
2182 /* Clear the pre-fetch instruction. */
2183 REG_WR_IND(bp, cpu_reg->inst, 0);
2184 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2185
2186 /* Start the CPU. */
2187 val = REG_RD_IND(bp, cpu_reg->mode);
2188 val &= ~cpu_reg->mode_value_halt;
2189 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2190 REG_WR_IND(bp, cpu_reg->mode, val);
2191}
2192
2193static void
2194bnx2_init_cpus(struct bnx2 *bp)
2195{
2196 struct cpu_reg cpu_reg;
2197 struct fw_info fw;
2198
2199 /* Initialize the RV2P processor. */
2200 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2201 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2202
2203 /* Initialize the RX Processor. */
2204 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2205 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2206 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2207 cpu_reg.state = BNX2_RXP_CPU_STATE;
2208 cpu_reg.state_value_clear = 0xffffff;
2209 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2210 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2211 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2212 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2213 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2214 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2215 cpu_reg.mips_view_base = 0x8000000;
2216
2217 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2218 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2219 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2220 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2221
2222 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2223 fw.text_len = bnx2_RXP_b06FwTextLen;
2224 fw.text_index = 0;
2225 fw.text = bnx2_RXP_b06FwText;
2226
2227 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2228 fw.data_len = bnx2_RXP_b06FwDataLen;
2229 fw.data_index = 0;
2230 fw.data = bnx2_RXP_b06FwData;
2231
2232 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2233 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2234 fw.sbss_index = 0;
2235 fw.sbss = bnx2_RXP_b06FwSbss;
2236
2237 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2238 fw.bss_len = bnx2_RXP_b06FwBssLen;
2239 fw.bss_index = 0;
2240 fw.bss = bnx2_RXP_b06FwBss;
2241
2242 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2243 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2244 fw.rodata_index = 0;
2245 fw.rodata = bnx2_RXP_b06FwRodata;
2246
2247 load_cpu_fw(bp, &cpu_reg, &fw);
2248
2249 /* Initialize the TX Processor. */
2250 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2251 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2252 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2253 cpu_reg.state = BNX2_TXP_CPU_STATE;
2254 cpu_reg.state_value_clear = 0xffffff;
2255 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2256 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2257 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2258 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2259 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2260 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2261 cpu_reg.mips_view_base = 0x8000000;
2262
2263 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2264 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2265 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2266 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2267
2268 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2269 fw.text_len = bnx2_TXP_b06FwTextLen;
2270 fw.text_index = 0;
2271 fw.text = bnx2_TXP_b06FwText;
2272
2273 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2274 fw.data_len = bnx2_TXP_b06FwDataLen;
2275 fw.data_index = 0;
2276 fw.data = bnx2_TXP_b06FwData;
2277
2278 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2279 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2280 fw.sbss_index = 0;
2281 fw.sbss = bnx2_TXP_b06FwSbss;
2282
2283 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2284 fw.bss_len = bnx2_TXP_b06FwBssLen;
2285 fw.bss_index = 0;
2286 fw.bss = bnx2_TXP_b06FwBss;
2287
2288 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2289 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2290 fw.rodata_index = 0;
2291 fw.rodata = bnx2_TXP_b06FwRodata;
2292
2293 load_cpu_fw(bp, &cpu_reg, &fw);
2294
2295 /* Initialize the TX Patch-up Processor. */
2296 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2297 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2298 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2299 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2300 cpu_reg.state_value_clear = 0xffffff;
2301 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2302 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2303 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2304 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2305 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2306 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2307 cpu_reg.mips_view_base = 0x8000000;
2308
2309 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2310 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2311 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2312 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2313
2314 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2315 fw.text_len = bnx2_TPAT_b06FwTextLen;
2316 fw.text_index = 0;
2317 fw.text = bnx2_TPAT_b06FwText;
2318
2319 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2320 fw.data_len = bnx2_TPAT_b06FwDataLen;
2321 fw.data_index = 0;
2322 fw.data = bnx2_TPAT_b06FwData;
2323
2324 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2325 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2326 fw.sbss_index = 0;
2327 fw.sbss = bnx2_TPAT_b06FwSbss;
2328
2329 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2330 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2331 fw.bss_index = 0;
2332 fw.bss = bnx2_TPAT_b06FwBss;
2333
2334 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2335 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2336 fw.rodata_index = 0;
2337 fw.rodata = bnx2_TPAT_b06FwRodata;
2338
2339 load_cpu_fw(bp, &cpu_reg, &fw);
2340
2341 /* Initialize the Completion Processor. */
2342 cpu_reg.mode = BNX2_COM_CPU_MODE;
2343 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2344 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2345 cpu_reg.state = BNX2_COM_CPU_STATE;
2346 cpu_reg.state_value_clear = 0xffffff;
2347 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2348 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2349 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2350 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2351 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2352 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2353 cpu_reg.mips_view_base = 0x8000000;
2354
2355 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2356 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2357 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2358 fw.start_addr = bnx2_COM_b06FwStartAddr;
2359
2360 fw.text_addr = bnx2_COM_b06FwTextAddr;
2361 fw.text_len = bnx2_COM_b06FwTextLen;
2362 fw.text_index = 0;
2363 fw.text = bnx2_COM_b06FwText;
2364
2365 fw.data_addr = bnx2_COM_b06FwDataAddr;
2366 fw.data_len = bnx2_COM_b06FwDataLen;
2367 fw.data_index = 0;
2368 fw.data = bnx2_COM_b06FwData;
2369
2370 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2371 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2372 fw.sbss_index = 0;
2373 fw.sbss = bnx2_COM_b06FwSbss;
2374
2375 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2376 fw.bss_len = bnx2_COM_b06FwBssLen;
2377 fw.bss_index = 0;
2378 fw.bss = bnx2_COM_b06FwBss;
2379
2380 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2381 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2382 fw.rodata_index = 0;
2383 fw.rodata = bnx2_COM_b06FwRodata;
2384
2385 load_cpu_fw(bp, &cpu_reg, &fw);
2386
2387}
2388
2389static int
829ca9a3 2390bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 2391{
2392 u16 pmcsr;
2393
2394 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2395
2396 switch (state) {
829ca9a3 2397 case PCI_D0: {
b6016b76
MC		 2398 u32 val;
2399
2400 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2401 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2402 PCI_PM_CTRL_PME_STATUS);
2403
2404 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2405 /* delay required during transition out of D3hot */
2406 msleep(20);
2407
2408 val = REG_RD(bp, BNX2_EMAC_MODE);
2409 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2410 val &= ~BNX2_EMAC_MODE_MPKT;
2411 REG_WR(bp, BNX2_EMAC_MODE, val);
2412
2413 val = REG_RD(bp, BNX2_RPM_CONFIG);
2414 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2415 REG_WR(bp, BNX2_RPM_CONFIG, val);
2416 break;
2417 }
829ca9a3 2418 case PCI_D3hot: {
b6016b76
MC		 2419 int i;
2420 u32 val, wol_msg;
2421
2422 if (bp->wol) {
2423 u32 advertising;
2424 u8 autoneg;
2425
2426 autoneg = bp->autoneg;
2427 advertising = bp->advertising;
2428
2429 bp->autoneg = AUTONEG_SPEED;
2430 bp->advertising = ADVERTISED_10baseT_Half |
2431 ADVERTISED_10baseT_Full |
2432 ADVERTISED_100baseT_Half |
2433 ADVERTISED_100baseT_Full |
2434 ADVERTISED_Autoneg;
2435
2436 bnx2_setup_copper_phy(bp);
2437
2438 bp->autoneg = autoneg;
2439 bp->advertising = advertising;
2440
2441 bnx2_set_mac_addr(bp);
2442
2443 val = REG_RD(bp, BNX2_EMAC_MODE);
2444
2445 /* Enable port mode. */
2446 val &= ~BNX2_EMAC_MODE_PORT;
2447 val |= BNX2_EMAC_MODE_PORT_MII |
2448 BNX2_EMAC_MODE_MPKT_RCVD |
2449 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76
MC		 2450 BNX2_EMAC_MODE_MPKT;
2451
2452 REG_WR(bp, BNX2_EMAC_MODE, val);
2453
2454 /* receive all multicast */
2455 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2456 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2457 0xffffffff);
2458 }
2459 REG_WR(bp, BNX2_EMAC_RX_MODE,
2460 BNX2_EMAC_RX_MODE_SORT_MODE);
2461
2462 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2463 BNX2_RPM_SORT_USER0_MC_EN;
2464 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2465 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2466 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2467 BNX2_RPM_SORT_USER0_ENA);
2468
2469 /* Need to enable EMAC and RPM for WOL. */
2470 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2471 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2472 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2473 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2474
2475 val = REG_RD(bp, BNX2_RPM_CONFIG);
2476 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2477 REG_WR(bp, BNX2_RPM_CONFIG, val);
2478
2479 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2480 }
2481 else {
2482 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2483 }
2484
dda1e390
MC		 2485 if (!(bp->flags & NO_WOL_FLAG))
2486 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 2487
2488 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2489 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2490 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2491
2492 if (bp->wol)
2493 pmcsr |= 3;
2494 }
2495 else {
2496 pmcsr |= 3;
2497 }
2498 if (bp->wol) {
2499 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2500 }
2501 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2502 pmcsr);
2503
2504 /* No more memory access after this point until
2505 * device is brought back to D0.
2506 */
2507 udelay(50);
2508 break;
2509 }
2510 default:
2511 return -EINVAL;
2512 }
2513 return 0;
2514}
2515
2516static int
2517bnx2_acquire_nvram_lock(struct bnx2 *bp)
2518{
2519 u32 val;
2520 int j;
2521
2522 /* Request access to the flash interface. */
2523 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2524 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2525 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2526 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2527 break;
2528
2529 udelay(5);
2530 }
2531
2532 if (j >= NVRAM_TIMEOUT_COUNT)
2533 return -EBUSY;
2534
2535 return 0;
2536}
2537
2538static int
2539bnx2_release_nvram_lock(struct bnx2 *bp)
2540{
2541 int j;
2542 u32 val;
2543
2544 /* Relinquish nvram interface. */
2545 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2546
2547 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2548 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2549 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2550 break;
2551
2552 udelay(5);
2553 }
2554
2555 if (j >= NVRAM_TIMEOUT_COUNT)
2556 return -EBUSY;
2557
2558 return 0;
2559}
2560
2561
2562static int
2563bnx2_enable_nvram_write(struct bnx2 *bp)
2564{
2565 u32 val;
2566
2567 val = REG_RD(bp, BNX2_MISC_CFG);
2568 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2569
2570 if (!bp->flash_info->buffered) {
2571 int j;
2572
2573 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2574 REG_WR(bp, BNX2_NVM_COMMAND,
2575 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2576
2577 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2578 udelay(5);
2579
2580 val = REG_RD(bp, BNX2_NVM_COMMAND);
2581 if (val & BNX2_NVM_COMMAND_DONE)
2582 break;
2583 }
2584
2585 if (j >= NVRAM_TIMEOUT_COUNT)
2586 return -EBUSY;
2587 }
2588 return 0;
2589}
2590
2591static void
2592bnx2_disable_nvram_write(struct bnx2 *bp)
2593{
2594 u32 val;
2595
2596 val = REG_RD(bp, BNX2_MISC_CFG);
2597 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2598}
2599
2600
2601static void
2602bnx2_enable_nvram_access(struct bnx2 *bp)
2603{
2604 u32 val;
2605
2606 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2607 /* Enable both bits, even on read. */
2608 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2609 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2610}
2611
2612static void
2613bnx2_disable_nvram_access(struct bnx2 *bp)
2614{
2615 u32 val;
2616
2617 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2618 /* Disable both bits, even after read. */
2619 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2620 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2621 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2622}
2623
2624static int
2625bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2626{
2627 u32 cmd;
2628 int j;
2629
2630 if (bp->flash_info->buffered)
2631 /* Buffered flash, no erase needed */
2632 return 0;
2633
2634 /* Build an erase command */
2635 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2636 BNX2_NVM_COMMAND_DOIT;
2637
2638 /* Need to clear DONE bit separately. */
2639 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2640
2641 /* Address of the NVRAM to read from. */
2642 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2643
2644 /* Issue an erase command. */
2645 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2646
2647 /* Wait for completion. */
2648 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2649 u32 val;
2650
2651 udelay(5);
2652
2653 val = REG_RD(bp, BNX2_NVM_COMMAND);
2654 if (val & BNX2_NVM_COMMAND_DONE)
2655 break;
2656 }
2657
2658 if (j >= NVRAM_TIMEOUT_COUNT)
2659 return -EBUSY;
2660
2661 return 0;
2662}
2663
2664static int
2665bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2666{
2667 u32 cmd;
2668 int j;
2669
2670 /* Build the command word. */
2671 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2672
2673 /* Calculate an offset of a buffered flash. */
2674 if (bp->flash_info->buffered) {
2675 offset = ((offset / bp->flash_info->page_size) <<
2676 bp->flash_info->page_bits) +
2677 (offset % bp->flash_info->page_size);
2678 }
2679
2680 /* Need to clear DONE bit separately. */
2681 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2682
2683 /* Address of the NVRAM to read from. */
2684 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2685
2686 /* Issue a read command. */
2687 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2688
2689 /* Wait for completion. */
2690 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2691 u32 val;
2692
2693 udelay(5);
2694
2695 val = REG_RD(bp, BNX2_NVM_COMMAND);
2696 if (val & BNX2_NVM_COMMAND_DONE) {
2697 val = REG_RD(bp, BNX2_NVM_READ);
2698
2699 val = be32_to_cpu(val);
2700 memcpy(ret_val, &val, 4);
2701 break;
2702 }
2703 }
2704 if (j >= NVRAM_TIMEOUT_COUNT)
2705 return -EBUSY;
2706
2707 return 0;
2708}
2709
2710
2711static int
2712bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2713{
2714 u32 cmd, val32;
2715 int j;
2716
2717 /* Build the command word. */
2718 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2719
2720 /* Calculate an offset of a buffered flash. */
2721 if (bp->flash_info->buffered) {
2722 offset = ((offset / bp->flash_info->page_size) <<
2723 bp->flash_info->page_bits) +
2724 (offset % bp->flash_info->page_size);
2725 }
2726
2727 /* Need to clear DONE bit separately. */
2728 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2729
2730 memcpy(&val32, val, 4);
2731 val32 = cpu_to_be32(val32);
2732
2733 /* Write the data. */
2734 REG_WR(bp, BNX2_NVM_WRITE, val32);
2735
2736 /* Address of the NVRAM to write to. */
2737 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2738
2739 /* Issue the write command. */
2740 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2741
2742 /* Wait for completion. */
2743 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2744 udelay(5);
2745
2746 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2747 break;
2748 }
2749 if (j >= NVRAM_TIMEOUT_COUNT)
2750 return -EBUSY;
2751
2752 return 0;
2753}
2754
2755static int
2756bnx2_init_nvram(struct bnx2 *bp)
2757{
2758 u32 val;
2759 int j, entry_count, rc;
2760 struct flash_spec *flash;
2761
2762 /* Determine the selected interface. */
2763 val = REG_RD(bp, BNX2_NVM_CFG1);
2764
2765 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2766
2767 rc = 0;
2768 if (val & 0x40000000) {
2769
2770 /* Flash interface has been reconfigured */
2771 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 2772 j++, flash++) {
2773 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2774 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 2775 bp->flash_info = flash;
2776 break;
2777 }
2778 }
2779 }
2780 else {
37137709 2781 u32 mask;
b6016b76
MC		 2782 /* Not yet been reconfigured */
2783
37137709
MC		 2784 if (val & (1 << 23))
2785 mask = FLASH_BACKUP_STRAP_MASK;
2786 else
2787 mask = FLASH_STRAP_MASK;
2788
b6016b76
MC		 2789 for (j = 0, flash = &flash_table[0]; j < entry_count;
2790 j++, flash++) {
2791
37137709 2792 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 2793 bp->flash_info = flash;
2794
2795 /* Request access to the flash interface. */
2796 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2797 return rc;
2798
2799 /* Enable access to flash interface */
2800 bnx2_enable_nvram_access(bp);
2801
2802 /* Reconfigure the flash interface */
2803 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2804 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2805 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2806 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2807
2808 /* Disable access to flash interface */
2809 bnx2_disable_nvram_access(bp);
2810 bnx2_release_nvram_lock(bp);
2811
2812 break;
2813 }
2814 }
2815 } /* if (val & 0x40000000) */
2816
2817 if (j == entry_count) {
2818 bp->flash_info = NULL;
2f23c523 2819 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 2820 return -ENODEV;
b6016b76
MC		 2821 }
2822
1122db71
MC		 2823 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2824 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2825 if (val)
2826 bp->flash_size = val;
2827 else
2828 bp->flash_size = bp->flash_info->total_size;
2829
b6016b76
MC		 2830 return rc;
2831}
2832
2833static int
2834bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2835 int buf_size)
2836{
2837 int rc = 0;
2838 u32 cmd_flags, offset32, len32, extra;
2839
2840 if (buf_size == 0)
2841 return 0;
2842
2843 /* Request access to the flash interface. */
2844 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2845 return rc;
2846
2847 /* Enable access to flash interface */
2848 bnx2_enable_nvram_access(bp);
2849
2850 len32 = buf_size;
2851 offset32 = offset;
2852 extra = 0;
2853
2854 cmd_flags = 0;
2855
2856 if (offset32 & 3) {
2857 u8 buf[4];
2858 u32 pre_len;
2859
2860 offset32 &= ~3;
2861 pre_len = 4 - (offset & 3);
2862
2863 if (pre_len >= len32) {
2864 pre_len = len32;
2865 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2866 BNX2_NVM_COMMAND_LAST;
2867 }
2868 else {
2869 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2870 }
2871
2872 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2873
2874 if (rc)
2875 return rc;
2876
2877 memcpy(ret_buf, buf + (offset & 3), pre_len);
2878
2879 offset32 += 4;
2880 ret_buf += pre_len;
2881 len32 -= pre_len;
2882 }
2883 if (len32 & 3) {
2884 extra = 4 - (len32 & 3);
2885 len32 = (len32 + 4) & ~3;
2886 }
2887
2888 if (len32 == 4) {
2889 u8 buf[4];
2890
2891 if (cmd_flags)
2892 cmd_flags = BNX2_NVM_COMMAND_LAST;
2893 else
2894 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2895 BNX2_NVM_COMMAND_LAST;
2896
2897 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2898
2899 memcpy(ret_buf, buf, 4 - extra);
2900 }
2901 else if (len32 > 0) {
2902 u8 buf[4];
2903
2904 /* Read the first word. */
2905 if (cmd_flags)
2906 cmd_flags = 0;
2907 else
2908 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2909
2910 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2911
2912 /* Advance to the next dword. */
2913 offset32 += 4;
2914 ret_buf += 4;
2915 len32 -= 4;
2916
2917 while (len32 > 4 && rc == 0) {
2918 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2919
2920 /* Advance to the next dword. */
2921 offset32 += 4;
2922 ret_buf += 4;
2923 len32 -= 4;
2924 }
2925
2926 if (rc)
2927 return rc;
2928
2929 cmd_flags = BNX2_NVM_COMMAND_LAST;
2930 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2931
2932 memcpy(ret_buf, buf, 4 - extra);
2933 }
2934
2935 /* Disable access to flash interface */
2936 bnx2_disable_nvram_access(bp);
2937
2938 bnx2_release_nvram_lock(bp);
2939
2940 return rc;
2941}
2942
2943static int
2944bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2945 int buf_size)
2946{
2947 u32 written, offset32, len32;
ae181bc4 2948 u8 *buf, start[4], end[4], *flash_buffer = NULL;
b6016b76
MC		 2949 int rc = 0;
2950 int align_start, align_end;
2951
2952 buf = data_buf;
2953 offset32 = offset;
2954 len32 = buf_size;
2955 align_start = align_end = 0;
2956
2957 if ((align_start = (offset32 & 3))) {
2958 offset32 &= ~3;
2959 len32 += align_start;
2960 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2961 return rc;
2962 }
2963
2964 if (len32 & 3) {
2965 if ((len32 > 4) || !align_start) {
2966 align_end = 4 - (len32 & 3);
2967 len32 += align_end;
2968 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2969 end, 4))) {
2970 return rc;
2971 }
2972 }
2973 }
2974
2975 if (align_start || align_end) {
2976 buf = kmalloc(len32, GFP_KERNEL);
2977 if (buf == 0)
2978 return -ENOMEM;
2979 if (align_start) {
2980 memcpy(buf, start, 4);
2981 }
2982 if (align_end) {
2983 memcpy(buf + len32 - 4, end, 4);
2984 }
2985 memcpy(buf + align_start, data_buf, buf_size);
2986 }
2987
ae181bc4
MC		 2988 if (bp->flash_info->buffered == 0) {
2989 flash_buffer = kmalloc(264, GFP_KERNEL);
2990 if (flash_buffer == NULL) {
2991 rc = -ENOMEM;
2992 goto nvram_write_end;
2993 }
2994 }
2995
b6016b76
MC		 2996 written = 0;
2997 while ((written < len32) && (rc == 0)) {
2998 u32 page_start, page_end, data_start, data_end;
2999 u32 addr, cmd_flags;
3000 int i;
b6016b76
MC		 3001
3002 /* Find the page_start addr */
3003 page_start = offset32 + written;
3004 page_start -= (page_start % bp->flash_info->page_size);
3005 /* Find the page_end addr */
3006 page_end = page_start + bp->flash_info->page_size;
3007 /* Find the data_start addr */
3008 data_start = (written == 0) ? offset32 : page_start;
3009 /* Find the data_end addr */
3010 data_end = (page_end > offset32 + len32) ?
3011 (offset32 + len32) : page_end;
3012
3013 /* Request access to the flash interface. */
3014 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3015 goto nvram_write_end;
3016
3017 /* Enable access to flash interface */
3018 bnx2_enable_nvram_access(bp);
3019
3020 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3021 if (bp->flash_info->buffered == 0) {
3022 int j;
3023
3024 /* Read the whole page into the buffer
3025 * (non-buffer flash only) */
3026 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3027 if (j == (bp->flash_info->page_size - 4)) {
3028 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3029 }
3030 rc = bnx2_nvram_read_dword(bp,
3031 page_start + j,
3032 &flash_buffer[j],
3033 cmd_flags);
3034
3035 if (rc)
3036 goto nvram_write_end;
3037
3038 cmd_flags = 0;
3039 }
3040 }
3041
3042 /* Enable writes to flash interface (unlock write-protect) */
3043 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3044 goto nvram_write_end;
3045
3046 /* Erase the page */
3047 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3048 goto nvram_write_end;
3049
3050 /* Re-enable the write again for the actual write */
3051 bnx2_enable_nvram_write(bp);
3052
3053 /* Loop to write back the buffer data from page_start to
3054 * data_start */
3055 i = 0;
3056 if (bp->flash_info->buffered == 0) {
3057 for (addr = page_start; addr < data_start;
3058 addr += 4, i += 4) {
3059
3060 rc = bnx2_nvram_write_dword(bp, addr,
3061 &flash_buffer[i], cmd_flags);
3062
3063 if (rc != 0)
3064 goto nvram_write_end;
3065
3066 cmd_flags = 0;
3067 }
3068 }
3069
3070 /* Loop to write the new data from data_start to data_end */
bae25761 3071 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76
MC		 3072 if ((addr == page_end - 4) ||
3073 ((bp->flash_info->buffered) &&
3074 (addr == data_end - 4))) {
3075
3076 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3077 }
3078 rc = bnx2_nvram_write_dword(bp, addr, buf,
3079 cmd_flags);
3080
3081 if (rc != 0)
3082 goto nvram_write_end;
3083
3084 cmd_flags = 0;
3085 buf += 4;
3086 }
3087
3088 /* Loop to write back the buffer data from data_end
3089 * to page_end */
3090 if (bp->flash_info->buffered == 0) {
3091 for (addr = data_end; addr < page_end;
3092 addr += 4, i += 4) {
3093
3094 if (addr == page_end-4) {
3095 cmd_flags = BNX2_NVM_COMMAND_LAST;
3096 }
3097 rc = bnx2_nvram_write_dword(bp, addr,
3098 &flash_buffer[i], cmd_flags);
3099
3100 if (rc != 0)
3101 goto nvram_write_end;
3102
3103 cmd_flags = 0;
3104 }
3105 }
3106
3107 /* Disable writes to flash interface (lock write-protect) */
3108 bnx2_disable_nvram_write(bp);
3109
3110 /* Disable access to flash interface */
3111 bnx2_disable_nvram_access(bp);
3112 bnx2_release_nvram_lock(bp);
3113
3114 /* Increment written */
3115 written += data_end - data_start;
3116 }
3117
3118nvram_write_end:
ae181bc4
MC		 3119 if (bp->flash_info->buffered == 0)
3120 kfree(flash_buffer);
3121
b6016b76
MC		 3122 if (align_start || align_end)
3123 kfree(buf);
3124 return rc;
3125}
3126
3127static int
3128bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3129{
3130 u32 val;
3131 int i, rc = 0;
3132
3133 /* Wait for the current PCI transaction to complete before
3134 * issuing a reset. */
3135 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3136 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3137 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3138 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3139 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3140 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3141 udelay(5);
3142
b090ae2b
MC		 3143 /* Wait for the firmware to tell us it is ok to issue a reset. */
3144 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3145
b6016b76
MC		 3146 /* Deposit a driver reset signature so the firmware knows that
3147 * this is a soft reset. */
e3648b3d 3148 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
b6016b76
MC		 3149 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3150
b6016b76
MC		 3151 /* Do a dummy read to force the chip to complete all current transaction
3152 * before we issue a reset. */
3153 val = REG_RD(bp, BNX2_MISC_ID);
3154
3155 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3156 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3157 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3158
3159 /* Chip reset. */
3160 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3161
3162 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3163 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3164 msleep(15);
3165
3166 /* Reset takes approximate 30 usec */
3167 for (i = 0; i < 10; i++) {
3168 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3169 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3170 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3171 break;
3172 }
3173 udelay(10);
3174 }
3175
3176 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3177 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3178 printk(KERN_ERR PFX "Chip reset did not complete\n");
3179 return -EBUSY;
3180 }
3181
3182 /* Make sure byte swapping is properly configured. */
3183 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3184 if (val != 0x01020304) {
3185 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3186 return -ENODEV;
3187 }
3188
b6016b76 3189 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 3190 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3191 if (rc)
3192 return rc;
b6016b76
MC		 3193
3194 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3195 /* Adjust the voltage regular to two steps lower. The default
3196 * of this register is 0x0000000e. */
3197 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3198
3199 /* Remove bad rbuf memory from the free pool. */
3200 rc = bnx2_alloc_bad_rbuf(bp);
3201 }
3202
3203 return rc;
3204}
3205
3206static int
3207bnx2_init_chip(struct bnx2 *bp)
3208{
3209 u32 val;
b090ae2b 3210 int rc;
b6016b76
MC		 3211
3212 /* Make sure the interrupt is not active. */
3213 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3214
3215 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3216 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3217#ifdef __BIG_ENDIAN
3218 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3219#endif
3220 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3221 DMA_READ_CHANS << 12 |
3222 DMA_WRITE_CHANS << 16;
3223
3224 val |= (0x2 << 20) | (1 << 11);
3225
dda1e390 3226 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 3227 val |= (1 << 23);
3228
3229 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3230 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3231 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3232
3233 REG_WR(bp, BNX2_DMA_CONFIG, val);
3234
3235 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3236 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3237 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3238 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3239 }
3240
3241 if (bp->flags & PCIX_FLAG) {
3242 u16 val16;
3243
3244 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3245 &val16);
3246 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3247 val16 & ~PCI_X_CMD_ERO);
3248 }
3249
3250 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3251 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3252 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3253 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3254
3255 /* Initialize context mapping and zero out the quick contexts. The
3256 * context block must have already been enabled. */
3257 bnx2_init_context(bp);
3258
3259 bnx2_init_cpus(bp);
3260 bnx2_init_nvram(bp);
3261
3262 bnx2_set_mac_addr(bp);
3263
3264 val = REG_RD(bp, BNX2_MQ_CONFIG);
3265 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3266 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3267 REG_WR(bp, BNX2_MQ_CONFIG, val);
3268
3269 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3270 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3271 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3272
3273 val = (BCM_PAGE_BITS - 8) << 24;
3274 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3275
3276 /* Configure page size. */
3277 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3278 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3279 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3280 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3281
3282 val = bp->mac_addr[0] +
3283 (bp->mac_addr[1] << 8) +
3284 (bp->mac_addr[2] << 16) +
3285 bp->mac_addr[3] +
3286 (bp->mac_addr[4] << 8) +
3287 (bp->mac_addr[5] << 16);
3288 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3289
3290 /* Program the MTU. Also include 4 bytes for CRC32. */
3291 val = bp->dev->mtu + ETH_HLEN + 4;
3292 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3293 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3294 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3295
3296 bp->last_status_idx = 0;
3297 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3298
3299 /* Set up how to generate a link change interrupt. */
3300 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3301
3302 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3303 (u64) bp->status_blk_mapping & 0xffffffff);
3304 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3305
3306 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3307 (u64) bp->stats_blk_mapping & 0xffffffff);
3308 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3309 (u64) bp->stats_blk_mapping >> 32);
3310
3311 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3312 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3313
3314 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3315 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3316
3317 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3318 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3319
3320 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3321
3322 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3323
3324 REG_WR(bp, BNX2_HC_COM_TICKS,
3325 (bp->com_ticks_int << 16) | bp->com_ticks);
3326
3327 REG_WR(bp, BNX2_HC_CMD_TICKS,
3328 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3329
3330 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3331 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3332
3333 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3334 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3335 else {
3336 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3337 BNX2_HC_CONFIG_TX_TMR_MODE |
3338 BNX2_HC_CONFIG_COLLECT_STATS);
3339 }
3340
3341 /* Clear internal stats counters. */
3342 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3343
3344 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3345
e29054f9
MC		 3346 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3347 BNX2_PORT_FEATURE_ASF_ENABLED)
3348 bp->flags |= ASF_ENABLE_FLAG;
3349
b6016b76
MC		 3350 /* Initialize the receive filter. */
3351 bnx2_set_rx_mode(bp->dev);
3352
b090ae2b
MC		 3353 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3354 0);
b6016b76
MC		 3355
3356 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3357 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3358
3359 udelay(20);
3360
bf5295bb
MC		 3361 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
3362
b090ae2b 3363 return rc;
b6016b76
MC		 3364}
3365
3366
3367static void
3368bnx2_init_tx_ring(struct bnx2 *bp)
3369{
3370 struct tx_bd *txbd;
3371 u32 val;
3372
3373 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3374
3375 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3376 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3377
3378 bp->tx_prod = 0;
3379 bp->tx_cons = 0;
f4e418f7 3380 bp->hw_tx_cons = 0;
b6016b76 3381 bp->tx_prod_bseq = 0;
b6016b76
MC		 3382
3383 val = BNX2_L2CTX_TYPE_TYPE_L2;
3384 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3385 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3386
3387 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3388 val |= 8 << 16;
3389 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3390
3391 val = (u64) bp->tx_desc_mapping >> 32;
3392 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3393
3394 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3395 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3396}
3397
3398static void
3399bnx2_init_rx_ring(struct bnx2 *bp)
3400{
3401 struct rx_bd *rxbd;
3402 int i;
3403 u16 prod, ring_prod;
3404 u32 val;
3405
3406 /* 8 for CRC and VLAN */
3407 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3408 /* 8 for alignment */
3409 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3410
3411 ring_prod = prod = bp->rx_prod = 0;
3412 bp->rx_cons = 0;
f4e418f7 3413 bp->hw_rx_cons = 0;
b6016b76
MC		 3414 bp->rx_prod_bseq = 0;
3415
13daffa2
MC		 3416 for (i = 0; i < bp->rx_max_ring; i++) {
3417 int j;
b6016b76 3418
13daffa2
MC		 3419 rxbd = &bp->rx_desc_ring[i][0];
3420 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
3421 rxbd->rx_bd_len = bp->rx_buf_use_size;
3422 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3423 }
3424 if (i == (bp->rx_max_ring - 1))
3425 j = 0;
3426 else
3427 j = i + 1;
3428 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
3429 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
3430 0xffffffff;
3431 }
b6016b76
MC		 3432
3433 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3434 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3435 val |= 0x02 << 8;
3436 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3437
13daffa2 3438 val = (u64) bp->rx_desc_mapping[0] >> 32;
b6016b76
MC		 3439 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3440
13daffa2 3441 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
b6016b76
MC		 3442 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3443
236b6394 3444 for (i = 0; i < bp->rx_ring_size; i++) {
b6016b76
MC		 3445 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3446 break;
3447 }
3448 prod = NEXT_RX_BD(prod);
3449 ring_prod = RX_RING_IDX(prod);
3450 }
3451 bp->rx_prod = prod;
3452
3453 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3454
3455 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3456}
3457
13daffa2
MC		 3458static void
3459bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
3460{
3461 u32 num_rings, max;
3462
3463 bp->rx_ring_size = size;
3464 num_rings = 1;
3465 while (size > MAX_RX_DESC_CNT) {
3466 size -= MAX_RX_DESC_CNT;
3467 num_rings++;
3468 }
3469 /* round to next power of 2 */
3470 max = MAX_RX_RINGS;
3471 while ((max & num_rings) == 0)
3472 max >>= 1;
3473
3474 if (num_rings != max)
3475 max <<= 1;
3476
3477 bp->rx_max_ring = max;
3478 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
3479}
3480
b6016b76
MC		 3481static void
3482bnx2_free_tx_skbs(struct bnx2 *bp)
3483{
3484 int i;
3485
3486 if (bp->tx_buf_ring == NULL)
3487 return;
3488
3489 for (i = 0; i < TX_DESC_CNT; ) {
3490 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3491 struct sk_buff *skb = tx_buf->skb;
3492 int j, last;
3493
3494 if (skb == NULL) {
3495 i++;
3496 continue;
3497 }
3498
3499 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3500 skb_headlen(skb), PCI_DMA_TODEVICE);
3501
3502 tx_buf->skb = NULL;
3503
3504 last = skb_shinfo(skb)->nr_frags;
3505 for (j = 0; j < last; j++) {
3506 tx_buf = &bp->tx_buf_ring[i + j + 1];
3507 pci_unmap_page(bp->pdev,
3508 pci_unmap_addr(tx_buf, mapping),
3509 skb_shinfo(skb)->frags[j].size,
3510 PCI_DMA_TODEVICE);
3511 }
3512 dev_kfree_skb_any(skb);
3513 i += j + 1;
3514 }
3515
3516}
3517
3518static void
3519bnx2_free_rx_skbs(struct bnx2 *bp)
3520{
3521 int i;
3522
3523 if (bp->rx_buf_ring == NULL)
3524 return;
3525
13daffa2 3526 for (i = 0; i < bp->rx_max_ring_idx; i++) {
b6016b76
MC		 3527 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3528 struct sk_buff *skb = rx_buf->skb;
3529
05d0f1cf 3530 if (skb == NULL)
b6016b76
MC		 3531 continue;
3532
3533 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3534 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3535
3536 rx_buf->skb = NULL;
3537
3538 dev_kfree_skb_any(skb);
3539 }
3540}
3541
3542static void
3543bnx2_free_skbs(struct bnx2 *bp)
3544{
3545 bnx2_free_tx_skbs(bp);
3546 bnx2_free_rx_skbs(bp);
3547}
3548
3549static int
3550bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3551{
3552 int rc;
3553
3554 rc = bnx2_reset_chip(bp, reset_code);
3555 bnx2_free_skbs(bp);
3556 if (rc)
3557 return rc;
3558
3559 bnx2_init_chip(bp);
3560 bnx2_init_tx_ring(bp);
3561 bnx2_init_rx_ring(bp);
3562 return 0;
3563}
3564
3565static int
3566bnx2_init_nic(struct bnx2 *bp)
3567{
3568 int rc;
3569
3570 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3571 return rc;
3572
3573 bnx2_init_phy(bp);
3574 bnx2_set_link(bp);
3575 return 0;
3576}
3577
3578static int
3579bnx2_test_registers(struct bnx2 *bp)
3580{
3581 int ret;
3582 int i;
f71e1309 3583 static const struct {
b6016b76
MC		 3584 u16 offset;
3585 u16 flags;
3586 u32 rw_mask;
3587 u32 ro_mask;
3588 } reg_tbl[] = {
3589 { 0x006c, 0, 0x00000000, 0x0000003f },
3590 { 0x0090, 0, 0xffffffff, 0x00000000 },
3591 { 0x0094, 0, 0x00000000, 0x00000000 },
3592
3593 { 0x0404, 0, 0x00003f00, 0x00000000 },
3594 { 0x0418, 0, 0x00000000, 0xffffffff },
3595 { 0x041c, 0, 0x00000000, 0xffffffff },
3596 { 0x0420, 0, 0x00000000, 0x80ffffff },
3597 { 0x0424, 0, 0x00000000, 0x00000000 },
3598 { 0x0428, 0, 0x00000000, 0x00000001 },
3599 { 0x0450, 0, 0x00000000, 0x0000ffff },
3600 { 0x0454, 0, 0x00000000, 0xffffffff },
3601 { 0x0458, 0, 0x00000000, 0xffffffff },
3602
3603 { 0x0808, 0, 0x00000000, 0xffffffff },
3604 { 0x0854, 0, 0x00000000, 0xffffffff },
3605 { 0x0868, 0, 0x00000000, 0x77777777 },
3606 { 0x086c, 0, 0x00000000, 0x77777777 },
3607 { 0x0870, 0, 0x00000000, 0x77777777 },
3608 { 0x0874, 0, 0x00000000, 0x77777777 },
3609
3610 { 0x0c00, 0, 0x00000000, 0x00000001 },
3611 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3612 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 3613
3614 { 0x1000, 0, 0x00000000, 0x00000001 },
3615 { 0x1004, 0, 0x00000000, 0x000f0001 },
b6016b76
MC		 3616
3617 { 0x1408, 0, 0x01c00800, 0x00000000 },
3618 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3619 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 3620 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 3621 { 0x14b0, 0, 0x00000002, 0x00000001 },
3622 { 0x14b8, 0, 0x00000000, 0x00000000 },
3623 { 0x14c0, 0, 0x00000000, 0x00000009 },
3624 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3625 { 0x14cc, 0, 0x00000000, 0x00000001 },
3626 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 3627
3628 { 0x1800, 0, 0x00000000, 0x00000001 },
3629 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 3630
3631 { 0x2800, 0, 0x00000000, 0x00000001 },
3632 { 0x2804, 0, 0x00000000, 0x00003f01 },
3633 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3634 { 0x2810, 0, 0xffff0000, 0x00000000 },
3635 { 0x2814, 0, 0xffff0000, 0x00000000 },
3636 { 0x2818, 0, 0xffff0000, 0x00000000 },
3637 { 0x281c, 0, 0xffff0000, 0x00000000 },
3638 { 0x2834, 0, 0xffffffff, 0x00000000 },
3639 { 0x2840, 0, 0x00000000, 0xffffffff },
3640 { 0x2844, 0, 0x00000000, 0xffffffff },
3641 { 0x2848, 0, 0xffffffff, 0x00000000 },
3642 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3643
3644 { 0x2c00, 0, 0x00000000, 0x00000011 },
3645 { 0x2c04, 0, 0x00000000, 0x00030007 },
3646
b6016b76
MC		 3647 { 0x3c00, 0, 0x00000000, 0x00000001 },
3648 { 0x3c04, 0, 0x00000000, 0x00070000 },
3649 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3650 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3651 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3652 { 0x3c14, 0, 0x00000000, 0xffffffff },
3653 { 0x3c18, 0, 0x00000000, 0xffffffff },
3654 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3655 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 3656
3657 { 0x5004, 0, 0x00000000, 0x0000007f },
3658 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3659 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3660
b6016b76
MC		 3661 { 0x5c00, 0, 0x00000000, 0x00000001 },
3662 { 0x5c04, 0, 0x00000000, 0x0003000f },
3663 { 0x5c08, 0, 0x00000003, 0x00000000 },
3664 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3665 { 0x5c10, 0, 0x00000000, 0xffffffff },
3666 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3667 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3668 { 0x5c88, 0, 0x00000000, 0x00077373 },
3669 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3670
3671 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3672 { 0x680c, 0, 0xffffffff, 0x00000000 },
3673 { 0x6810, 0, 0xffffffff, 0x00000000 },
3674 { 0x6814, 0, 0xffffffff, 0x00000000 },
3675 { 0x6818, 0, 0xffffffff, 0x00000000 },
3676 { 0x681c, 0, 0xffffffff, 0x00000000 },
3677 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3678 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3679 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3680 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3681 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3682 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3683 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3684 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3685 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3686 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3687 { 0x684c, 0, 0xffffffff, 0x00000000 },
3688 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3689 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3690 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3691 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3692 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3693 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3694
3695 { 0xffff, 0, 0x00000000, 0x00000000 },
3696 };
3697
3698 ret = 0;
3699 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3700 u32 offset, rw_mask, ro_mask, save_val, val;
3701
3702 offset = (u32) reg_tbl[i].offset;
3703 rw_mask = reg_tbl[i].rw_mask;
3704 ro_mask = reg_tbl[i].ro_mask;
3705
14ab9b86 3706 save_val = readl(bp->regview + offset);
b6016b76 3707
14ab9b86 3708 writel(0, bp->regview + offset);
b6016b76 3709
14ab9b86 3710 val = readl(bp->regview + offset);
b6016b76
MC		 3711 if ((val & rw_mask) != 0) {
3712 goto reg_test_err;
3713 }
3714
3715 if ((val & ro_mask) != (save_val & ro_mask)) {
3716 goto reg_test_err;
3717 }
3718
14ab9b86 3719 writel(0xffffffff, bp->regview + offset);
b6016b76 3720
14ab9b86 3721 val = readl(bp->regview + offset);
b6016b76
MC		 3722 if ((val & rw_mask) != rw_mask) {
3723 goto reg_test_err;
3724 }
3725
3726 if ((val & ro_mask) != (save_val & ro_mask)) {
3727 goto reg_test_err;
3728 }
3729
14ab9b86 3730 writel(save_val, bp->regview + offset);
b6016b76
MC		 3731 continue;
3732
3733reg_test_err:
14ab9b86 3734 writel(save_val, bp->regview + offset);
b6016b76
MC		 3735 ret = -ENODEV;
3736 break;
3737 }
3738 return ret;
3739}
3740
3741static int
3742bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3743{
f71e1309 3744 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 3745 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3746 int i;
3747
3748 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3749 u32 offset;
3750
3751 for (offset = 0; offset < size; offset += 4) {
3752
3753 REG_WR_IND(bp, start + offset, test_pattern[i]);
3754
3755 if (REG_RD_IND(bp, start + offset) !=
3756 test_pattern[i]) {
3757 return -ENODEV;
3758 }
3759 }
3760 }
3761 return 0;
3762}
3763
3764static int
3765bnx2_test_memory(struct bnx2 *bp)
3766{
3767 int ret = 0;
3768 int i;
f71e1309 3769 static const struct {
b6016b76
MC		 3770 u32 offset;
3771 u32 len;
3772 } mem_tbl[] = {
3773 { 0x60000, 0x4000 },
5b0c76ad 3774 { 0xa0000, 0x3000 },
b6016b76
MC		 3775 { 0xe0000, 0x4000 },
3776 { 0x120000, 0x4000 },
3777 { 0x1a0000, 0x4000 },
3778 { 0x160000, 0x4000 },
3779 { 0xffffffff, 0 },
3780 };
3781
3782 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3783 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3784 mem_tbl[i].len)) != 0) {
3785 return ret;
3786 }
3787 }
3788
3789 return ret;
3790}
3791
bc5a0690
MC		 3792#define BNX2_MAC_LOOPBACK 0
3793#define BNX2_PHY_LOOPBACK 1
3794
b6016b76 3795static int
bc5a0690 3796bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 3797{
3798 unsigned int pkt_size, num_pkts, i;
3799 struct sk_buff *skb, *rx_skb;
3800 unsigned char *packet;
bc5a0690 3801 u16 rx_start_idx, rx_idx;
b6016b76
MC		 3802 dma_addr_t map;
3803 struct tx_bd *txbd;
3804 struct sw_bd *rx_buf;
3805 struct l2_fhdr *rx_hdr;
3806 int ret = -ENODEV;
3807
bc5a0690
MC		 3808 if (loopback_mode == BNX2_MAC_LOOPBACK) {
3809 bp->loopback = MAC_LOOPBACK;
3810 bnx2_set_mac_loopback(bp);
3811 }
3812 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
3813 bp->loopback = 0;
3814 bnx2_set_phy_loopback(bp);
3815 }
3816 else
3817 return -EINVAL;
b6016b76
MC		 3818
3819 pkt_size = 1514;
3820 skb = dev_alloc_skb(pkt_size);
b6cbc3b6
JL		 3821 if (!skb)
3822 return -ENOMEM;
b6016b76
MC		 3823 packet = skb_put(skb, pkt_size);
3824 memcpy(packet, bp->mac_addr, 6);
3825 memset(packet + 6, 0x0, 8);
3826 for (i = 14; i < pkt_size; i++)
3827 packet[i] = (unsigned char) (i & 0xff);
3828
3829 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3830 PCI_DMA_TODEVICE);
3831
bf5295bb
MC		 3832 REG_WR(bp, BNX2_HC_COMMAND,
3833 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3834
b6016b76
MC		 3835 REG_RD(bp, BNX2_HC_COMMAND);
3836
3837 udelay(5);
3838 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3839
b6016b76
MC		 3840 num_pkts = 0;
3841
bc5a0690 3842 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
b6016b76
MC		 3843
3844 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3845 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3846 txbd->tx_bd_mss_nbytes = pkt_size;
3847 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3848
3849 num_pkts++;
bc5a0690
MC		 3850 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
3851 bp->tx_prod_bseq += pkt_size;
b6016b76 3852
bc5a0690
MC		 3853 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
3854 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
b6016b76
MC		 3855
3856 udelay(100);
3857
bf5295bb
MC		 3858 REG_WR(bp, BNX2_HC_COMMAND,
3859 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3860
b6016b76
MC		 3861 REG_RD(bp, BNX2_HC_COMMAND);
3862
3863 udelay(5);
3864
3865 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3866 dev_kfree_skb_irq(skb);
3867
bc5a0690 3868 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
b6016b76
MC		 3869 goto loopback_test_done;
3870 }
3871
3872 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3873 if (rx_idx != rx_start_idx + num_pkts) {
3874 goto loopback_test_done;
3875 }
3876
3877 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3878 rx_skb = rx_buf->skb;
3879
3880 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3881 skb_reserve(rx_skb, bp->rx_offset);
3882
3883 pci_dma_sync_single_for_cpu(bp->pdev,
3884 pci_unmap_addr(rx_buf, mapping),
3885 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3886
ade2bfe7 3887 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 3888 (L2_FHDR_ERRORS_BAD_CRC |
3889 L2_FHDR_ERRORS_PHY_DECODE |
3890 L2_FHDR_ERRORS_ALIGNMENT |
3891 L2_FHDR_ERRORS_TOO_SHORT |
3892 L2_FHDR_ERRORS_GIANT_FRAME)) {
3893
3894 goto loopback_test_done;
3895 }
3896
3897 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3898 goto loopback_test_done;
3899 }
3900
3901 for (i = 14; i < pkt_size; i++) {
3902 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3903 goto loopback_test_done;
3904 }
3905 }
3906
3907 ret = 0;
3908
3909loopback_test_done:
3910 bp->loopback = 0;
3911 return ret;
3912}
3913
bc5a0690
MC		 3914#define BNX2_MAC_LOOPBACK_FAILED 1
3915#define BNX2_PHY_LOOPBACK_FAILED 2
3916#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
3917 BNX2_PHY_LOOPBACK_FAILED)
3918
3919static int
3920bnx2_test_loopback(struct bnx2 *bp)
3921{
3922 int rc = 0;
3923
3924 if (!netif_running(bp->dev))
3925 return BNX2_LOOPBACK_FAILED;
3926
3927 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
3928 spin_lock_bh(&bp->phy_lock);
3929 bnx2_init_phy(bp);
3930 spin_unlock_bh(&bp->phy_lock);
3931 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
3932 rc |= BNX2_MAC_LOOPBACK_FAILED;
3933 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
3934 rc |= BNX2_PHY_LOOPBACK_FAILED;
3935 return rc;
3936}
3937
b6016b76
MC		 3938#define NVRAM_SIZE 0x200
3939#define CRC32_RESIDUAL 0xdebb20e3
3940
3941static int
3942bnx2_test_nvram(struct bnx2 *bp)
3943{
3944 u32 buf[NVRAM_SIZE / 4];
3945 u8 *data = (u8 *) buf;
3946 int rc = 0;
3947 u32 magic, csum;
3948
3949 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3950 goto test_nvram_done;
3951
3952 magic = be32_to_cpu(buf[0]);
3953 if (magic != 0x669955aa) {
3954 rc = -ENODEV;
3955 goto test_nvram_done;
3956 }
3957
3958 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3959 goto test_nvram_done;
3960
3961 csum = ether_crc_le(0x100, data);
3962 if (csum != CRC32_RESIDUAL) {
3963 rc = -ENODEV;
3964 goto test_nvram_done;
3965 }
3966
3967 csum = ether_crc_le(0x100, data + 0x100);
3968 if (csum != CRC32_RESIDUAL) {
3969 rc = -ENODEV;
3970 }
3971
3972test_nvram_done:
3973 return rc;
3974}
3975
3976static int
3977bnx2_test_link(struct bnx2 *bp)
3978{
3979 u32 bmsr;
3980
c770a65c 3981 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3982 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3983 bnx2_read_phy(bp, MII_BMSR, &bmsr);
c770a65c 3984 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3985
3986 if (bmsr & BMSR_LSTATUS) {
3987 return 0;
3988 }
3989 return -ENODEV;
3990}
3991
3992static int
3993bnx2_test_intr(struct bnx2 *bp)
3994{
3995 int i;
b6016b76
MC		 3996 u16 status_idx;
3997
3998 if (!netif_running(bp->dev))
3999 return -ENODEV;
4000
4001 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4002
4003 /* This register is not touched during run-time. */
bf5295bb 4004 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 4005 REG_RD(bp, BNX2_HC_COMMAND);
4006
4007 for (i = 0; i < 10; i++) {
4008 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4009 status_idx) {
4010
4011 break;
4012 }
4013
4014 msleep_interruptible(10);
4015 }
4016 if (i < 10)
4017 return 0;
4018
4019 return -ENODEV;
4020}
4021
4022static void
4023bnx2_timer(unsigned long data)
4024{
4025 struct bnx2 *bp = (struct bnx2 *) data;
4026 u32 msg;
4027
cd339a0e
MC		 4028 if (!netif_running(bp->dev))
4029 return;
4030
b6016b76
MC		 4031 if (atomic_read(&bp->intr_sem) != 0)
4032 goto bnx2_restart_timer;
4033
4034 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
e3648b3d 4035 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
b6016b76 4036
cea94db9
MC		 4037 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4038
b6016b76
MC		 4039 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4040 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
b6016b76 4041
c770a65c 4042 spin_lock(&bp->phy_lock);
b6016b76
MC		 4043 if (bp->serdes_an_pending) {
4044 bp->serdes_an_pending--;
4045 }
4046 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4047 u32 bmcr;
4048
cd339a0e
MC		 4049 bp->current_interval = bp->timer_interval;
4050
b6016b76
MC		 4051 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4052
4053 if (bmcr & BMCR_ANENABLE) {
4054 u32 phy1, phy2;
4055
4056 bnx2_write_phy(bp, 0x1c, 0x7c00);
4057 bnx2_read_phy(bp, 0x1c, &phy1);
4058
4059 bnx2_write_phy(bp, 0x17, 0x0f01);
4060 bnx2_read_phy(bp, 0x15, &phy2);
4061 bnx2_write_phy(bp, 0x17, 0x0f01);
4062 bnx2_read_phy(bp, 0x15, &phy2);
4063
4064 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4065 !(phy2 & 0x20)) { /* no CONFIG */
4066
4067 bmcr &= ~BMCR_ANENABLE;
4068 bmcr |= BMCR_SPEED1000 |
4069 BMCR_FULLDPLX;
4070 bnx2_write_phy(bp, MII_BMCR, bmcr);
4071 bp->phy_flags |=
4072 PHY_PARALLEL_DETECT_FLAG;
4073 }
4074 }
4075 }
4076 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4077 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4078 u32 phy2;
4079
4080 bnx2_write_phy(bp, 0x17, 0x0f01);
4081 bnx2_read_phy(bp, 0x15, &phy2);
4082 if (phy2 & 0x20) {
4083 u32 bmcr;
4084
4085 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4086 bmcr |= BMCR_ANENABLE;
4087 bnx2_write_phy(bp, MII_BMCR, bmcr);
4088
4089 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4090
4091 }
4092 }
cd339a0e
MC		 4093 else
4094 bp->current_interval = bp->timer_interval;
b6016b76 4095
c770a65c 4096 spin_unlock(&bp->phy_lock);
b6016b76
MC		 4097 }
4098
4099bnx2_restart_timer:
cd339a0e 4100 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4101}
4102
4103/* Called with rtnl_lock */
4104static int
4105bnx2_open(struct net_device *dev)
4106{
972ec0d4 4107 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4108 int rc;
4109
829ca9a3 4110 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 4111 bnx2_disable_int(bp);
4112
4113 rc = bnx2_alloc_mem(bp);
4114 if (rc)
4115 return rc;
4116
4117 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4118 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4119 !disable_msi) {
4120
4121 if (pci_enable_msi(bp->pdev) == 0) {
4122 bp->flags |= USING_MSI_FLAG;
4123 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4124 dev);
4125 }
4126 else {
4127 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4128 SA_SHIRQ, dev->name, dev);
4129 }
4130 }
4131 else {
4132 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4133 dev->name, dev);
4134 }
4135 if (rc) {
4136 bnx2_free_mem(bp);
4137 return rc;
4138 }
4139
4140 rc = bnx2_init_nic(bp);
4141
4142 if (rc) {
4143 free_irq(bp->pdev->irq, dev);
4144 if (bp->flags & USING_MSI_FLAG) {
4145 pci_disable_msi(bp->pdev);
4146 bp->flags &= ~USING_MSI_FLAG;
4147 }
4148 bnx2_free_skbs(bp);
4149 bnx2_free_mem(bp);
4150 return rc;
4151 }
4152
cd339a0e 4153 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4154
4155 atomic_set(&bp->intr_sem, 0);
4156
4157 bnx2_enable_int(bp);
4158
4159 if (bp->flags & USING_MSI_FLAG) {
4160 /* Test MSI to make sure it is working
4161 * If MSI test fails, go back to INTx mode
4162 */
4163 if (bnx2_test_intr(bp) != 0) {
4164 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4165 " using MSI, switching to INTx mode. Please"
4166 " report this failure to the PCI maintainer"
4167 " and include system chipset information.\n",
4168 bp->dev->name);
4169
4170 bnx2_disable_int(bp);
4171 free_irq(bp->pdev->irq, dev);
4172 pci_disable_msi(bp->pdev);
4173 bp->flags &= ~USING_MSI_FLAG;
4174
4175 rc = bnx2_init_nic(bp);
4176
4177 if (!rc) {
4178 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4179 SA_SHIRQ, dev->name, dev);
4180 }
4181 if (rc) {
4182 bnx2_free_skbs(bp);
4183 bnx2_free_mem(bp);
4184 del_timer_sync(&bp->timer);
4185 return rc;
4186 }
4187 bnx2_enable_int(bp);
4188 }
4189 }
4190 if (bp->flags & USING_MSI_FLAG) {
4191 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4192 }
4193
4194 netif_start_queue(dev);
4195
4196 return 0;
4197}
4198
4199static void
4200bnx2_reset_task(void *data)
4201{
4202 struct bnx2 *bp = data;
4203
afdc08b9
MC		 4204 if (!netif_running(bp->dev))
4205 return;
4206
4207 bp->in_reset_task = 1;
b6016b76
MC		 4208 bnx2_netif_stop(bp);
4209
4210 bnx2_init_nic(bp);
4211
4212 atomic_set(&bp->intr_sem, 1);
4213 bnx2_netif_start(bp);
afdc08b9 4214 bp->in_reset_task = 0;
b6016b76
MC		 4215}
4216
4217static void
4218bnx2_tx_timeout(struct net_device *dev)
4219{
972ec0d4 4220 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4221
4222 /* This allows the netif to be shutdown gracefully before resetting */
4223 schedule_work(&bp->reset_task);
4224}
4225
4226#ifdef BCM_VLAN
4227/* Called with rtnl_lock */
4228static void
4229bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4230{
972ec0d4 4231 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4232
4233 bnx2_netif_stop(bp);
4234
4235 bp->vlgrp = vlgrp;
4236 bnx2_set_rx_mode(dev);
4237
4238 bnx2_netif_start(bp);
4239}
4240
4241/* Called with rtnl_lock */
4242static void
4243bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4244{
972ec0d4 4245 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4246
4247 bnx2_netif_stop(bp);
4248
4249 if (bp->vlgrp)
4250 bp->vlgrp->vlan_devices[vid] = NULL;
4251 bnx2_set_rx_mode(dev);
4252
4253 bnx2_netif_start(bp);
4254}
4255#endif
4256
932ff279 4257/* Called with netif_tx_lock.
b6016b76
MC		 4258 * hard_start_xmit is pseudo-lockless - a lock is only required when
4259 * the tx queue is full. This way, we get the benefit of lockless
4260 * operations most of the time without the complexities to handle
4261 * netif_stop_queue/wake_queue race conditions.
4262 */
4263static int
4264bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4265{
972ec0d4 4266 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4267 dma_addr_t mapping;
4268 struct tx_bd *txbd;
4269 struct sw_bd *tx_buf;
4270 u32 len, vlan_tag_flags, last_frag, mss;
4271 u16 prod, ring_prod;
4272 int i;
4273
e89bbf10 4274 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 4275 netif_stop_queue(dev);
4276 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4277 dev->name);
4278
4279 return NETDEV_TX_BUSY;
4280 }
4281 len = skb_headlen(skb);
4282 prod = bp->tx_prod;
4283 ring_prod = TX_RING_IDX(prod);
4284
4285 vlan_tag_flags = 0;
4286 if (skb->ip_summed == CHECKSUM_HW) {
4287 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4288 }
4289
4290 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4291 vlan_tag_flags |=
4292 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4293 }
4294#ifdef BCM_TSO
4295 if ((mss = skb_shinfo(skb)->tso_size) &&
4296 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4297 u32 tcp_opt_len, ip_tcp_len;
4298
4299 if (skb_header_cloned(skb) &&
4300 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4301 dev_kfree_skb(skb);
4302 return NETDEV_TX_OK;
4303 }
4304
4305 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4306 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4307
4308 tcp_opt_len = 0;
4309 if (skb->h.th->doff > 5) {
4310 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4311 }
4312 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4313
4314 skb->nh.iph->check = 0;
d1e100ba 4315 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b6016b76
MC		 4316 skb->h.th->check =
4317 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4318 skb->nh.iph->daddr,
4319 0, IPPROTO_TCP, 0);
4320
4321 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4322 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4323 (tcp_opt_len >> 2)) << 8;
4324 }
4325 }
4326 else
4327#endif
4328 {
4329 mss = 0;
4330 }
4331
4332 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4333
4334 tx_buf = &bp->tx_buf_ring[ring_prod];
4335 tx_buf->skb = skb;
4336 pci_unmap_addr_set(tx_buf, mapping, mapping);
4337
4338 txbd = &bp->tx_desc_ring[ring_prod];
4339
4340 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4341 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4342 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4343 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4344
4345 last_frag = skb_shinfo(skb)->nr_frags;
4346
4347 for (i = 0; i < last_frag; i++) {
4348 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4349
4350 prod = NEXT_TX_BD(prod);
4351 ring_prod = TX_RING_IDX(prod);
4352 txbd = &bp->tx_desc_ring[ring_prod];
4353
4354 len = frag->size;
4355 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4356 len, PCI_DMA_TODEVICE);
4357 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4358 mapping, mapping);
4359
4360 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4361 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4362 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4363 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4364
4365 }
4366 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4367
4368 prod = NEXT_TX_BD(prod);
4369 bp->tx_prod_bseq += skb->len;
4370
b6016b76
MC		 4371 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4372 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4373
4374 mmiowb();
4375
4376 bp->tx_prod = prod;
4377 dev->trans_start = jiffies;
4378
e89bbf10 4379 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
c770a65c 4380 spin_lock(&bp->tx_lock);
e89bbf10
MC		 4381 netif_stop_queue(dev);
4382
4383 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4384 netif_wake_queue(dev);
c770a65c 4385 spin_unlock(&bp->tx_lock);
b6016b76
MC		 4386 }
4387
4388 return NETDEV_TX_OK;
4389}
4390
4391/* Called with rtnl_lock */
4392static int
4393bnx2_close(struct net_device *dev)
4394{
972ec0d4 4395 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4396 u32 reset_code;
4397
afdc08b9
MC		 4398 /* Calling flush_scheduled_work() may deadlock because
4399 * linkwatch_event() may be on the workqueue and it will try to get
4400 * the rtnl_lock which we are holding.
4401 */
4402 while (bp->in_reset_task)
4403 msleep(1);
4404
b6016b76
MC		 4405 bnx2_netif_stop(bp);
4406 del_timer_sync(&bp->timer);
dda1e390
MC		 4407 if (bp->flags & NO_WOL_FLAG)
4408 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
4409 else if (bp->wol)
b6016b76
MC		 4410 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4411 else
4412 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4413 bnx2_reset_chip(bp, reset_code);
4414 free_irq(bp->pdev->irq, dev);
4415 if (bp->flags & USING_MSI_FLAG) {
4416 pci_disable_msi(bp->pdev);
4417 bp->flags &= ~USING_MSI_FLAG;
4418 }
4419 bnx2_free_skbs(bp);
4420 bnx2_free_mem(bp);
4421 bp->link_up = 0;
4422 netif_carrier_off(bp->dev);
829ca9a3 4423 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 4424 return 0;
4425}
4426
4427#define GET_NET_STATS64(ctr) \
4428 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4429 (unsigned long) (ctr##_lo)
4430
4431#define GET_NET_STATS32(ctr) \
4432 (ctr##_lo)
4433
4434#if (BITS_PER_LONG == 64)
4435#define GET_NET_STATS GET_NET_STATS64
4436#else
4437#define GET_NET_STATS GET_NET_STATS32
4438#endif
4439
4440static struct net_device_stats *
4441bnx2_get_stats(struct net_device *dev)
4442{
972ec0d4 4443 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4444 struct statistics_block *stats_blk = bp->stats_blk;
4445 struct net_device_stats *net_stats = &bp->net_stats;
4446
4447 if (bp->stats_blk == NULL) {
4448 return net_stats;
4449 }
4450 net_stats->rx_packets =
4451 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4452 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4453 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4454
4455 net_stats->tx_packets =
4456 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4457 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4458 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4459
4460 net_stats->rx_bytes =
4461 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4462
4463 net_stats->tx_bytes =
4464 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4465
4466 net_stats->multicast =
4467 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4468
4469 net_stats->collisions =
4470 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4471
4472 net_stats->rx_length_errors =
4473 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4474 stats_blk->stat_EtherStatsOverrsizePkts);
4475
4476 net_stats->rx_over_errors =
4477 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4478
4479 net_stats->rx_frame_errors =
4480 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4481
4482 net_stats->rx_crc_errors =
4483 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4484
4485 net_stats->rx_errors = net_stats->rx_length_errors +
4486 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4487 net_stats->rx_crc_errors;
4488
4489 net_stats->tx_aborted_errors =
4490 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4491 stats_blk->stat_Dot3StatsLateCollisions);
4492
5b0c76ad
MC		 4493 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4494 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 4495 net_stats->tx_carrier_errors = 0;
4496 else {
4497 net_stats->tx_carrier_errors =
4498 (unsigned long)
4499 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4500 }
4501
4502 net_stats->tx_errors =
4503 (unsigned long)
4504 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4505 +
4506 net_stats->tx_aborted_errors +
4507 net_stats->tx_carrier_errors;
4508
cea94db9
MC		 4509 net_stats->rx_missed_errors =
4510 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
4511 stats_blk->stat_FwRxDrop);
4512
b6016b76
MC		 4513 return net_stats;
4514}
4515
4516/* All ethtool functions called with rtnl_lock */
4517
4518static int
4519bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4520{
972ec0d4 4521 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4522
4523 cmd->supported = SUPPORTED_Autoneg;
4524 if (bp->phy_flags & PHY_SERDES_FLAG) {
4525 cmd->supported |= SUPPORTED_1000baseT_Full |
4526 SUPPORTED_FIBRE;
4527
4528 cmd->port = PORT_FIBRE;
4529 }
4530 else {
4531 cmd->supported |= SUPPORTED_10baseT_Half |
4532 SUPPORTED_10baseT_Full |
4533 SUPPORTED_100baseT_Half |
4534 SUPPORTED_100baseT_Full |
4535 SUPPORTED_1000baseT_Full |
4536 SUPPORTED_TP;
4537
4538 cmd->port = PORT_TP;
4539 }
4540
4541 cmd->advertising = bp->advertising;
4542
4543 if (bp->autoneg & AUTONEG_SPEED) {
4544 cmd->autoneg = AUTONEG_ENABLE;
4545 }
4546 else {
4547 cmd->autoneg = AUTONEG_DISABLE;
4548 }
4549
4550 if (netif_carrier_ok(dev)) {
4551 cmd->speed = bp->line_speed;
4552 cmd->duplex = bp->duplex;
4553 }
4554 else {
4555 cmd->speed = -1;
4556 cmd->duplex = -1;
4557 }
4558
4559 cmd->transceiver = XCVR_INTERNAL;
4560 cmd->phy_address = bp->phy_addr;
4561
4562 return 0;
4563}
4564
4565static int
4566bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4567{
972ec0d4 4568 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4569 u8 autoneg = bp->autoneg;
4570 u8 req_duplex = bp->req_duplex;
4571 u16 req_line_speed = bp->req_line_speed;
4572 u32 advertising = bp->advertising;
4573
4574 if (cmd->autoneg == AUTONEG_ENABLE) {
4575 autoneg |= AUTONEG_SPEED;
4576
4577 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4578
4579 /* allow advertising 1 speed */
4580 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4581 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4582 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4583 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4584
4585 if (bp->phy_flags & PHY_SERDES_FLAG)
4586 return -EINVAL;
4587
4588 advertising = cmd->advertising;
4589
4590 }
4591 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4592 advertising = cmd->advertising;
4593 }
4594 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4595 return -EINVAL;
4596 }
4597 else {
4598 if (bp->phy_flags & PHY_SERDES_FLAG) {
4599 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4600 }
4601 else {
4602 advertising = ETHTOOL_ALL_COPPER_SPEED;
4603 }
4604 }
4605 advertising |= ADVERTISED_Autoneg;
4606 }
4607 else {
4608 if (bp->phy_flags & PHY_SERDES_FLAG) {
4609 if ((cmd->speed != SPEED_1000) ||
4610 (cmd->duplex != DUPLEX_FULL)) {
4611 return -EINVAL;
4612 }
4613 }
4614 else if (cmd->speed == SPEED_1000) {
4615 return -EINVAL;
4616 }
4617 autoneg &= ~AUTONEG_SPEED;
4618 req_line_speed = cmd->speed;
4619 req_duplex = cmd->duplex;
4620 advertising = 0;
4621 }
4622
4623 bp->autoneg = autoneg;
4624 bp->advertising = advertising;
4625 bp->req_line_speed = req_line_speed;
4626 bp->req_duplex = req_duplex;
4627
c770a65c 4628 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4629
4630 bnx2_setup_phy(bp);
4631
c770a65c 4632 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4633
4634 return 0;
4635}
4636
4637static void
4638bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4639{
972ec0d4 4640 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4641
4642 strcpy(info->driver, DRV_MODULE_NAME);
4643 strcpy(info->version, DRV_MODULE_VERSION);
4644 strcpy(info->bus_info, pci_name(bp->pdev));
4645 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4646 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4647 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
206cc83c
MC		 4648 info->fw_version[1] = info->fw_version[3] = '.';
4649 info->fw_version[5] = 0;
b6016b76
MC		 4650}
4651
244ac4f4
MC		 4652#define BNX2_REGDUMP_LEN (32 * 1024)
4653
4654static int
4655bnx2_get_regs_len(struct net_device *dev)
4656{
4657 return BNX2_REGDUMP_LEN;
4658}
4659
4660static void
4661bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
4662{
4663 u32 *p = _p, i, offset;
4664 u8 *orig_p = _p;
4665 struct bnx2 *bp = netdev_priv(dev);
4666 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
4667 0x0800, 0x0880, 0x0c00, 0x0c10,
4668 0x0c30, 0x0d08, 0x1000, 0x101c,
4669 0x1040, 0x1048, 0x1080, 0x10a4,
4670 0x1400, 0x1490, 0x1498, 0x14f0,
4671 0x1500, 0x155c, 0x1580, 0x15dc,
4672 0x1600, 0x1658, 0x1680, 0x16d8,
4673 0x1800, 0x1820, 0x1840, 0x1854,
4674 0x1880, 0x1894, 0x1900, 0x1984,
4675 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
4676 0x1c80, 0x1c94, 0x1d00, 0x1d84,
4677 0x2000, 0x2030, 0x23c0, 0x2400,
4678 0x2800, 0x2820, 0x2830, 0x2850,
4679 0x2b40, 0x2c10, 0x2fc0, 0x3058,
4680 0x3c00, 0x3c94, 0x4000, 0x4010,
4681 0x4080, 0x4090, 0x43c0, 0x4458,
4682 0x4c00, 0x4c18, 0x4c40, 0x4c54,
4683 0x4fc0, 0x5010, 0x53c0, 0x5444,
4684 0x5c00, 0x5c18, 0x5c80, 0x5c90,
4685 0x5fc0, 0x6000, 0x6400, 0x6428,
4686 0x6800, 0x6848, 0x684c, 0x6860,
4687 0x6888, 0x6910, 0x8000 };
4688
4689 regs->version = 0;
4690
4691 memset(p, 0, BNX2_REGDUMP_LEN);
4692
4693 if (!netif_running(bp->dev))
4694 return;
4695
4696 i = 0;
4697 offset = reg_boundaries[0];
4698 p += offset;
4699 while (offset < BNX2_REGDUMP_LEN) {
4700 *p++ = REG_RD(bp, offset);
4701 offset += 4;
4702 if (offset == reg_boundaries[i + 1]) {
4703 offset = reg_boundaries[i + 2];
4704 p = (u32 *) (orig_p + offset);
4705 i += 2;
4706 }
4707 }
4708}
4709
b6016b76
MC		 4710static void
4711bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4712{
972ec0d4 4713 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4714
4715 if (bp->flags & NO_WOL_FLAG) {
4716 wol->supported = 0;
4717 wol->wolopts = 0;
4718 }
4719 else {
4720 wol->supported = WAKE_MAGIC;
4721 if (bp->wol)
4722 wol->wolopts = WAKE_MAGIC;
4723 else
4724 wol->wolopts = 0;
4725 }
4726 memset(&wol->sopass, 0, sizeof(wol->sopass));
4727}
4728
4729static int
4730bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4731{
972ec0d4 4732 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4733
4734 if (wol->wolopts & ~WAKE_MAGIC)
4735 return -EINVAL;
4736
4737 if (wol->wolopts & WAKE_MAGIC) {
4738 if (bp->flags & NO_WOL_FLAG)
4739 return -EINVAL;
4740
4741 bp->wol = 1;
4742 }
4743 else {
4744 bp->wol = 0;
4745 }
4746 return 0;
4747}
4748
4749static int
4750bnx2_nway_reset(struct net_device *dev)
4751{
972ec0d4 4752 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4753 u32 bmcr;
4754
4755 if (!(bp->autoneg & AUTONEG_SPEED)) {
4756 return -EINVAL;
4757 }
4758
c770a65c 4759 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4760
4761 /* Force a link down visible on the other side */
4762 if (bp->phy_flags & PHY_SERDES_FLAG) {
4763 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
c770a65c 4764 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4765
4766 msleep(20);
4767
c770a65c 4768 spin_lock_bh(&bp->phy_lock);
b6016b76 4769 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
cd339a0e
MC		 4770 bp->current_interval = SERDES_AN_TIMEOUT;
4771 bp->serdes_an_pending = 1;
4772 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4773 }
4774 }
4775
4776 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4777 bmcr &= ~BMCR_LOOPBACK;
4778 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4779
c770a65c 4780 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4781
4782 return 0;
4783}
4784
4785static int
4786bnx2_get_eeprom_len(struct net_device *dev)
4787{
972ec0d4 4788 struct bnx2 *bp = netdev_priv(dev);
b6016b76 4789
1122db71 4790 if (bp->flash_info == NULL)
b6016b76
MC		 4791 return 0;
4792
1122db71 4793 return (int) bp->flash_size;
b6016b76
MC		 4794}
4795
4796static int
4797bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4798 u8 *eebuf)
4799{
972ec0d4 4800 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4801 int rc;
4802
1064e944 4803 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 4804
4805 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4806
4807 return rc;
4808}
4809
4810static int
4811bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4812 u8 *eebuf)
4813{
972ec0d4 4814 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4815 int rc;
4816
1064e944 4817 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 4818
4819 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4820
4821 return rc;
4822}
4823
4824static int
4825bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4826{
972ec0d4 4827 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4828
4829 memset(coal, 0, sizeof(struct ethtool_coalesce));
4830
4831 coal->rx_coalesce_usecs = bp->rx_ticks;
4832 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4833 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4834 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4835
4836 coal->tx_coalesce_usecs = bp->tx_ticks;
4837 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4838 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4839 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4840
4841 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4842
4843 return 0;
4844}
4845
4846static int
4847bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4848{
972ec0d4 4849 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4850
4851 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4852 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4853
4854 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4855 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4856
4857 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4858 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4859
4860 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4861 if (bp->rx_quick_cons_trip_int > 0xff)
4862 bp->rx_quick_cons_trip_int = 0xff;
4863
4864 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4865 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4866
4867 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4868 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4869
4870 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4871 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4872
4873 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4874 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4875 0xff;
4876
4877 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4878 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4879 bp->stats_ticks &= 0xffff00;
4880
4881 if (netif_running(bp->dev)) {
4882 bnx2_netif_stop(bp);
4883 bnx2_init_nic(bp);
4884 bnx2_netif_start(bp);
4885 }
4886
4887 return 0;
4888}
4889
4890static void
4891bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4892{
972ec0d4 4893 struct bnx2 *bp = netdev_priv(dev);
b6016b76 4894
13daffa2 4895 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76
MC		 4896 ering->rx_mini_max_pending = 0;
4897 ering->rx_jumbo_max_pending = 0;
4898
4899 ering->rx_pending = bp->rx_ring_size;
4900 ering->rx_mini_pending = 0;
4901 ering->rx_jumbo_pending = 0;
4902
4903 ering->tx_max_pending = MAX_TX_DESC_CNT;
4904 ering->tx_pending = bp->tx_ring_size;
4905}
4906
4907static int
4908bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4909{
972ec0d4 4910 struct bnx2 *bp = netdev_priv(dev);
b6016b76 4911
13daffa2 4912 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
b6016b76
MC		 4913 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4914 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4915
4916 return -EINVAL;
4917 }
13daffa2
MC		 4918 if (netif_running(bp->dev)) {
4919 bnx2_netif_stop(bp);
4920 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4921 bnx2_free_skbs(bp);
4922 bnx2_free_mem(bp);
4923 }
4924
4925 bnx2_set_rx_ring_size(bp, ering->rx_pending);
b6016b76
MC		 4926 bp->tx_ring_size = ering->tx_pending;
4927
4928 if (netif_running(bp->dev)) {
13daffa2
MC		 4929 int rc;
4930
4931 rc = bnx2_alloc_mem(bp);
4932 if (rc)
4933 return rc;
b6016b76
MC		 4934 bnx2_init_nic(bp);
4935 bnx2_netif_start(bp);
4936 }
4937
4938 return 0;
4939}
4940
4941static void
4942bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4943{
972ec0d4 4944 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4945
4946 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4947 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4948 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4949}
4950
4951static int
4952bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4953{
972ec0d4 4954 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4955
4956 bp->req_flow_ctrl = 0;
4957 if (epause->rx_pause)
4958 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4959 if (epause->tx_pause)
4960 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4961
4962 if (epause->autoneg) {
4963 bp->autoneg |= AUTONEG_FLOW_CTRL;
4964 }
4965 else {
4966 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4967 }
4968
c770a65c 4969 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4970
4971 bnx2_setup_phy(bp);
4972
c770a65c 4973 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4974
4975 return 0;
4976}
4977
4978static u32
4979bnx2_get_rx_csum(struct net_device *dev)
4980{
972ec0d4 4981 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4982
4983 return bp->rx_csum;
4984}
4985
4986static int
4987bnx2_set_rx_csum(struct net_device *dev, u32 data)
4988{
972ec0d4 4989 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4990
4991 bp->rx_csum = data;
4992 return 0;
4993}
4994
cea94db9 4995#define BNX2_NUM_STATS 46
b6016b76 4996
14ab9b86 4997static struct {
b6016b76
MC		 4998 char string[ETH_GSTRING_LEN];
4999} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5000 { "rx_bytes" },
5001 { "rx_error_bytes" },
5002 { "tx_bytes" },
5003 { "tx_error_bytes" },
5004 { "rx_ucast_packets" },
5005 { "rx_mcast_packets" },
5006 { "rx_bcast_packets" },
5007 { "tx_ucast_packets" },
5008 { "tx_mcast_packets" },
5009 { "tx_bcast_packets" },
5010 { "tx_mac_errors" },
5011 { "tx_carrier_errors" },
5012 { "rx_crc_errors" },
5013 { "rx_align_errors" },
5014 { "tx_single_collisions" },
5015 { "tx_multi_collisions" },
5016 { "tx_deferred" },
5017 { "tx_excess_collisions" },
5018 { "tx_late_collisions" },
5019 { "tx_total_collisions" },
5020 { "rx_fragments" },
5021 { "rx_jabbers" },
5022 { "rx_undersize_packets" },
5023 { "rx_oversize_packets" },
5024 { "rx_64_byte_packets" },
5025 { "rx_65_to_127_byte_packets" },
5026 { "rx_128_to_255_byte_packets" },
5027 { "rx_256_to_511_byte_packets" },
5028 { "rx_512_to_1023_byte_packets" },
5029 { "rx_1024_to_1522_byte_packets" },
5030 { "rx_1523_to_9022_byte_packets" },
5031 { "tx_64_byte_packets" },
5032 { "tx_65_to_127_byte_packets" },
5033 { "tx_128_to_255_byte_packets" },
5034 { "tx_256_to_511_byte_packets" },
5035 { "tx_512_to_1023_byte_packets" },
5036 { "tx_1024_to_1522_byte_packets" },
5037 { "tx_1523_to_9022_byte_packets" },
5038 { "rx_xon_frames" },
5039 { "rx_xoff_frames" },
5040 { "tx_xon_frames" },
5041 { "tx_xoff_frames" },
5042 { "rx_mac_ctrl_frames" },
5043 { "rx_filtered_packets" },
5044 { "rx_discards" },
cea94db9 5045 { "rx_fw_discards" },
b6016b76
MC		 5046};
5047
5048#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5049
f71e1309 5050static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 5051 STATS_OFFSET32(stat_IfHCInOctets_hi),
5052 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5053 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5054 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5055 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5056 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5057 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5058 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5059 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5060 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5061 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5062 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5063 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5064 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5065 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5066 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5067 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5068 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5069 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5070 STATS_OFFSET32(stat_EtherStatsCollisions),
5071 STATS_OFFSET32(stat_EtherStatsFragments),
5072 STATS_OFFSET32(stat_EtherStatsJabbers),
5073 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5074 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5075 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5076 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5077 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5078 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5079 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5080 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5081 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5082 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5083 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5084 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5085 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5086 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5087 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5088 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5089 STATS_OFFSET32(stat_XonPauseFramesReceived),
5090 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5091 STATS_OFFSET32(stat_OutXonSent),
5092 STATS_OFFSET32(stat_OutXoffSent),
5093 STATS_OFFSET32(stat_MacControlFramesReceived),
5094 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5095 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 5096 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 5097};
5098
5099/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5100 * skipped because of errata.
5101 */
14ab9b86 5102static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 5103 8,0,8,8,8,8,8,8,8,8,
5104 4,0,4,4,4,4,4,4,4,4,
5105 4,4,4,4,4,4,4,4,4,4,
5106 4,4,4,4,4,4,4,4,4,4,
cea94db9 5107 4,4,4,4,4,4,
b6016b76
MC		 5108};
5109
5b0c76ad
MC		 5110static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5111 8,0,8,8,8,8,8,8,8,8,
5112 4,4,4,4,4,4,4,4,4,4,
5113 4,4,4,4,4,4,4,4,4,4,
5114 4,4,4,4,4,4,4,4,4,4,
cea94db9 5115 4,4,4,4,4,4,
5b0c76ad
MC		 5116};
5117
b6016b76
MC		 5118#define BNX2_NUM_TESTS 6
5119
14ab9b86 5120static struct {
b6016b76
MC		 5121 char string[ETH_GSTRING_LEN];
5122} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5123 { "register_test (offline)" },
5124 { "memory_test (offline)" },
5125 { "loopback_test (offline)" },
5126 { "nvram_test (online)" },
5127 { "interrupt_test (online)" },
5128 { "link_test (online)" },
5129};
5130
5131static int
5132bnx2_self_test_count(struct net_device *dev)
5133{
5134 return BNX2_NUM_TESTS;
5135}
5136
5137static void
5138bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5139{
972ec0d4 5140 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5141
5142 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5143 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5144 bnx2_netif_stop(bp);
5145 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5146 bnx2_free_skbs(bp);
5147
5148 if (bnx2_test_registers(bp) != 0) {
5149 buf[0] = 1;
5150 etest->flags |= ETH_TEST_FL_FAILED;
5151 }
5152 if (bnx2_test_memory(bp) != 0) {
5153 buf[1] = 1;
5154 etest->flags |= ETH_TEST_FL_FAILED;
5155 }
bc5a0690 5156 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 5157 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76
MC		 5158
5159 if (!netif_running(bp->dev)) {
5160 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5161 }
5162 else {
5163 bnx2_init_nic(bp);
5164 bnx2_netif_start(bp);
5165 }
5166
5167 /* wait for link up */
5168 msleep_interruptible(3000);
5169 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5170 msleep_interruptible(4000);
5171 }
5172
5173 if (bnx2_test_nvram(bp) != 0) {
5174 buf[3] = 1;
5175 etest->flags |= ETH_TEST_FL_FAILED;
5176 }
5177 if (bnx2_test_intr(bp) != 0) {
5178 buf[4] = 1;
5179 etest->flags |= ETH_TEST_FL_FAILED;
5180 }
5181
5182 if (bnx2_test_link(bp) != 0) {
5183 buf[5] = 1;
5184 etest->flags |= ETH_TEST_FL_FAILED;
5185
5186 }
5187}
5188
5189static void
5190bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5191{
5192 switch (stringset) {
5193 case ETH_SS_STATS:
5194 memcpy(buf, bnx2_stats_str_arr,
5195 sizeof(bnx2_stats_str_arr));
5196 break;
5197 case ETH_SS_TEST:
5198 memcpy(buf, bnx2_tests_str_arr,
5199 sizeof(bnx2_tests_str_arr));
5200 break;
5201 }
5202}
5203
5204static int
5205bnx2_get_stats_count(struct net_device *dev)
5206{
5207 return BNX2_NUM_STATS;
5208}
5209
5210static void
5211bnx2_get_ethtool_stats(struct net_device *dev,
5212 struct ethtool_stats *stats, u64 *buf)
5213{
972ec0d4 5214 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5215 int i;
5216 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 5217 u8 *stats_len_arr = NULL;
b6016b76
MC		 5218
5219 if (hw_stats == NULL) {
5220 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5221 return;
5222 }
5223
5b0c76ad
MC		 5224 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5225 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5226 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5227 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 5228 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 5229 else
5230 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 5231
5232 for (i = 0; i < BNX2_NUM_STATS; i++) {
5233 if (stats_len_arr[i] == 0) {
5234 /* skip this counter */
5235 buf[i] = 0;
5236 continue;
5237 }
5238 if (stats_len_arr[i] == 4) {
5239 /* 4-byte counter */
5240 buf[i] = (u64)
5241 *(hw_stats + bnx2_stats_offset_arr[i]);
5242 continue;
5243 }
5244 /* 8-byte counter */
5245 buf[i] = (((u64) *(hw_stats +
5246 bnx2_stats_offset_arr[i])) << 32) +
5247 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5248 }
5249}
5250
5251static int
5252bnx2_phys_id(struct net_device *dev, u32 data)
5253{
972ec0d4 5254 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5255 int i;
5256 u32 save;
5257
5258 if (data == 0)
5259 data = 2;
5260
5261 save = REG_RD(bp, BNX2_MISC_CFG);
5262 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5263
5264 for (i = 0; i < (data * 2); i++) {
5265 if ((i % 2) == 0) {
5266 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5267 }
5268 else {
5269 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5270 BNX2_EMAC_LED_1000MB_OVERRIDE |
5271 BNX2_EMAC_LED_100MB_OVERRIDE |
5272 BNX2_EMAC_LED_10MB_OVERRIDE |
5273 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5274 BNX2_EMAC_LED_TRAFFIC);
5275 }
5276 msleep_interruptible(500);
5277 if (signal_pending(current))
5278 break;
5279 }
5280 REG_WR(bp, BNX2_EMAC_LED, 0);
5281 REG_WR(bp, BNX2_MISC_CFG, save);
5282 return 0;
5283}
5284
5285static struct ethtool_ops bnx2_ethtool_ops = {
5286 .get_settings = bnx2_get_settings,
5287 .set_settings = bnx2_set_settings,
5288 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 5289 .get_regs_len = bnx2_get_regs_len,
5290 .get_regs = bnx2_get_regs,
b6016b76
MC		 5291 .get_wol = bnx2_get_wol,
5292 .set_wol = bnx2_set_wol,
5293 .nway_reset = bnx2_nway_reset,
5294 .get_link = ethtool_op_get_link,
5295 .get_eeprom_len = bnx2_get_eeprom_len,
5296 .get_eeprom = bnx2_get_eeprom,
5297 .set_eeprom = bnx2_set_eeprom,
5298 .get_coalesce = bnx2_get_coalesce,
5299 .set_coalesce = bnx2_set_coalesce,
5300 .get_ringparam = bnx2_get_ringparam,
5301 .set_ringparam = bnx2_set_ringparam,
5302 .get_pauseparam = bnx2_get_pauseparam,
5303 .set_pauseparam = bnx2_set_pauseparam,
5304 .get_rx_csum = bnx2_get_rx_csum,
5305 .set_rx_csum = bnx2_set_rx_csum,
5306 .get_tx_csum = ethtool_op_get_tx_csum,
5307 .set_tx_csum = ethtool_op_set_tx_csum,
5308 .get_sg = ethtool_op_get_sg,
5309 .set_sg = ethtool_op_set_sg,
5310#ifdef BCM_TSO
5311 .get_tso = ethtool_op_get_tso,
5312 .set_tso = ethtool_op_set_tso,
5313#endif
5314 .self_test_count = bnx2_self_test_count,
5315 .self_test = bnx2_self_test,
5316 .get_strings = bnx2_get_strings,
5317 .phys_id = bnx2_phys_id,
5318 .get_stats_count = bnx2_get_stats_count,
5319 .get_ethtool_stats = bnx2_get_ethtool_stats,
24b8e05d 5320 .get_perm_addr = ethtool_op_get_perm_addr,
b6016b76
MC		 5321};
5322
5323/* Called with rtnl_lock */
5324static int
5325bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5326{
14ab9b86 5327 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 5328 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5329 int err;
5330
5331 switch(cmd) {
5332 case SIOCGMIIPHY:
5333 data->phy_id = bp->phy_addr;
5334
5335 /* fallthru */
5336 case SIOCGMIIREG: {
5337 u32 mii_regval;
5338
c770a65c 5339 spin_lock_bh(&bp->phy_lock);
b6016b76 5340 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 5341 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5342
5343 data->val_out = mii_regval;
5344
5345 return err;
5346 }
5347
5348 case SIOCSMIIREG:
5349 if (!capable(CAP_NET_ADMIN))
5350 return -EPERM;
5351
c770a65c 5352 spin_lock_bh(&bp->phy_lock);
b6016b76 5353 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 5354 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5355
5356 return err;
5357
5358 default:
5359 /* do nothing */
5360 break;
5361 }
5362 return -EOPNOTSUPP;
5363}
5364
5365/* Called with rtnl_lock */
5366static int
5367bnx2_change_mac_addr(struct net_device *dev, void *p)
5368{
5369 struct sockaddr *addr = p;
972ec0d4 5370 struct bnx2 *bp = netdev_priv(dev);
b6016b76 5371
73eef4cd
MC		 5372 if (!is_valid_ether_addr(addr->sa_data))
5373 return -EINVAL;
5374
b6016b76
MC		 5375 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5376 if (netif_running(dev))
5377 bnx2_set_mac_addr(bp);
5378
5379 return 0;
5380}
5381
5382/* Called with rtnl_lock */
5383static int
5384bnx2_change_mtu(struct net_device *dev, int new_mtu)
5385{
972ec0d4 5386 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5387
5388 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5389 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5390 return -EINVAL;
5391
5392 dev->mtu = new_mtu;
5393 if (netif_running(dev)) {
5394 bnx2_netif_stop(bp);
5395
5396 bnx2_init_nic(bp);
5397
5398 bnx2_netif_start(bp);
5399 }
5400 return 0;
5401}
5402
5403#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5404static void
5405poll_bnx2(struct net_device *dev)
5406{
972ec0d4 5407 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5408
5409 disable_irq(bp->pdev->irq);
5410 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5411 enable_irq(bp->pdev->irq);
5412}
5413#endif
5414
5415static int __devinit
5416bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5417{
5418 struct bnx2 *bp;
5419 unsigned long mem_len;
5420 int rc;
5421 u32 reg;
5422
5423 SET_MODULE_OWNER(dev);
5424 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 5425 bp = netdev_priv(dev);
b6016b76
MC		 5426
5427 bp->flags = 0;
5428 bp->phy_flags = 0;
5429
5430 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5431 rc = pci_enable_device(pdev);
5432 if (rc) {
5433 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5434 goto err_out;
5435 }
5436
5437 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5438 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5439 "aborting.\n");
5440 rc = -ENODEV;
5441 goto err_out_disable;
5442 }
5443
5444 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5445 if (rc) {
5446 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5447 goto err_out_disable;
5448 }
5449
5450 pci_set_master(pdev);
5451
5452 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5453 if (bp->pm_cap == 0) {
5454 printk(KERN_ERR PFX "Cannot find power management capability, "
5455 "aborting.\n");
5456 rc = -EIO;
5457 goto err_out_release;
5458 }
5459
5460 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5461 if (bp->pcix_cap == 0) {
5462 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5463 rc = -EIO;
5464 goto err_out_release;
5465 }
5466
5467 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5468 bp->flags |= USING_DAC_FLAG;
5469 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5470 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5471 "failed, aborting.\n");
5472 rc = -EIO;
5473 goto err_out_release;
5474 }
5475 }
5476 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5477 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5478 rc = -EIO;
5479 goto err_out_release;
5480 }
5481
5482 bp->dev = dev;
5483 bp->pdev = pdev;
5484
5485 spin_lock_init(&bp->phy_lock);
5486 spin_lock_init(&bp->tx_lock);
5487 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5488
5489 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5490 mem_len = MB_GET_CID_ADDR(17);
5491 dev->mem_end = dev->mem_start + mem_len;
5492 dev->irq = pdev->irq;
5493
5494 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5495
5496 if (!bp->regview) {
5497 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5498 rc = -ENOMEM;
5499 goto err_out_release;
5500 }
5501
5502 /* Configure byte swap and enable write to the reg_window registers.
5503 * Rely on CPU to do target byte swapping on big endian systems
5504 * The chip's target access swapping will not swap all accesses
5505 */
5506 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5507 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5508 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5509
829ca9a3 5510 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5511
5512 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5513
b6016b76
MC		 5514 /* Get bus information. */
5515 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5516 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5517 u32 clkreg;
5518
5519 bp->flags |= PCIX_FLAG;
5520
5521 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5522
5523 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5524 switch (clkreg) {
5525 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5526 bp->bus_speed_mhz = 133;
5527 break;
5528
5529 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5530 bp->bus_speed_mhz = 100;
5531 break;
5532
5533 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5534 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5535 bp->bus_speed_mhz = 66;
5536 break;
5537
5538 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5539 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5540 bp->bus_speed_mhz = 50;
5541 break;
5542
5543 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5544 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5545 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5546 bp->bus_speed_mhz = 33;
5547 break;
5548 }
5549 }
5550 else {
5551 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5552 bp->bus_speed_mhz = 66;
5553 else
5554 bp->bus_speed_mhz = 33;
5555 }
5556
5557 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5558 bp->flags |= PCI_32BIT_FLAG;
5559
5560 /* 5706A0 may falsely detect SERR and PERR. */
5561 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5562 reg = REG_RD(bp, PCI_COMMAND);
5563 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5564 REG_WR(bp, PCI_COMMAND, reg);
5565 }
5566 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5567 !(bp->flags & PCIX_FLAG)) {
5568
5569 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5570 "aborting.\n");
5571 goto err_out_unmap;
5572 }
5573
5574 bnx2_init_nvram(bp);
5575
e3648b3d
MC		 5576 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5577
5578 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5579 BNX2_SHM_HDR_SIGNATURE_SIG)
5580 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5581 else
5582 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5583
b6016b76
MC		 5584 /* Get the permanent MAC address. First we need to make sure the
5585 * firmware is actually running.
5586 */
e3648b3d 5587 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 5588
5589 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5590 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5591 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5592 rc = -ENODEV;
5593 goto err_out_unmap;
5594 }
5595
e3648b3d 5596 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
b6016b76 5597
e3648b3d 5598 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 5599 bp->mac_addr[0] = (u8) (reg >> 8);
5600 bp->mac_addr[1] = (u8) reg;
5601
e3648b3d 5602 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 5603 bp->mac_addr[2] = (u8) (reg >> 24);
5604 bp->mac_addr[3] = (u8) (reg >> 16);
5605 bp->mac_addr[4] = (u8) (reg >> 8);
5606 bp->mac_addr[5] = (u8) reg;
5607
5608 bp->tx_ring_size = MAX_TX_DESC_CNT;
13daffa2 5609 bnx2_set_rx_ring_size(bp, 100);
b6016b76
MC		 5610
5611 bp->rx_csum = 1;
5612
5613 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5614
5615 bp->tx_quick_cons_trip_int = 20;
5616 bp->tx_quick_cons_trip = 20;
5617 bp->tx_ticks_int = 80;
5618 bp->tx_ticks = 80;
5619
5620 bp->rx_quick_cons_trip_int = 6;
5621 bp->rx_quick_cons_trip = 6;
5622 bp->rx_ticks_int = 18;
5623 bp->rx_ticks = 18;
5624
5625 bp->stats_ticks = 1000000 & 0xffff00;
5626
5627 bp->timer_interval = HZ;
cd339a0e 5628 bp->current_interval = HZ;
b6016b76 5629
5b0c76ad
MC		 5630 bp->phy_addr = 1;
5631
b6016b76
MC		 5632 /* Disable WOL support if we are running on a SERDES chip. */
5633 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5634 bp->phy_flags |= PHY_SERDES_FLAG;
5635 bp->flags |= NO_WOL_FLAG;
5b0c76ad
MC		 5636 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5637 bp->phy_addr = 2;
e3648b3d 5638 reg = REG_RD_IND(bp, bp->shmem_base +
5b0c76ad
MC		 5639 BNX2_SHARED_HW_CFG_CONFIG);
5640 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5641 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5642 }
b6016b76
MC		 5643 }
5644
16088272
MC		 5645 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
5646 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5647 (CHIP_ID(bp) == CHIP_ID_5708_B1))
dda1e390
MC		 5648 bp->flags |= NO_WOL_FLAG;
5649
b6016b76
MC		 5650 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5651 bp->tx_quick_cons_trip_int =
5652 bp->tx_quick_cons_trip;
5653 bp->tx_ticks_int = bp->tx_ticks;
5654 bp->rx_quick_cons_trip_int =
5655 bp->rx_quick_cons_trip;
5656 bp->rx_ticks_int = bp->rx_ticks;
5657 bp->comp_prod_trip_int = bp->comp_prod_trip;
5658 bp->com_ticks_int = bp->com_ticks;
5659 bp->cmd_ticks_int = bp->cmd_ticks;
5660 }
5661
5662 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5663 bp->req_line_speed = 0;
5664 if (bp->phy_flags & PHY_SERDES_FLAG) {
5665 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
cd339a0e 5666
e3648b3d 5667 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
cd339a0e
MC		 5668 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5669 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5670 bp->autoneg = 0;
5671 bp->req_line_speed = bp->line_speed = SPEED_1000;
5672 bp->req_duplex = DUPLEX_FULL;
5673 }
b6016b76
MC		 5674 }
5675 else {
5676 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5677 }
5678
5679 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5680
cd339a0e
MC		 5681 init_timer(&bp->timer);
5682 bp->timer.expires = RUN_AT(bp->timer_interval);
5683 bp->timer.data = (unsigned long) bp;
5684 bp->timer.function = bnx2_timer;
5685
b6016b76
MC		 5686 return 0;
5687
5688err_out_unmap:
5689 if (bp->regview) {
5690 iounmap(bp->regview);
73eef4cd 5691 bp->regview = NULL;
b6016b76
MC		 5692 }
5693
5694err_out_release:
5695 pci_release_regions(pdev);
5696
5697err_out_disable:
5698 pci_disable_device(pdev);
5699 pci_set_drvdata(pdev, NULL);
5700
5701err_out:
5702 return rc;
5703}
5704
5705static int __devinit
5706bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5707{
5708 static int version_printed = 0;
5709 struct net_device *dev = NULL;
5710 struct bnx2 *bp;
5711 int rc, i;
5712
5713 if (version_printed++ == 0)
5714 printk(KERN_INFO "%s", version);
5715
5716 /* dev zeroed in init_etherdev */
5717 dev = alloc_etherdev(sizeof(*bp));
5718
5719 if (!dev)
5720 return -ENOMEM;
5721
5722 rc = bnx2_init_board(pdev, dev);
5723 if (rc < 0) {
5724 free_netdev(dev);
5725 return rc;
5726 }
5727
5728 dev->open = bnx2_open;
5729 dev->hard_start_xmit = bnx2_start_xmit;
5730 dev->stop = bnx2_close;
5731 dev->get_stats = bnx2_get_stats;
5732 dev->set_multicast_list = bnx2_set_rx_mode;
5733 dev->do_ioctl = bnx2_ioctl;
5734 dev->set_mac_address = bnx2_change_mac_addr;
5735 dev->change_mtu = bnx2_change_mtu;
5736 dev->tx_timeout = bnx2_tx_timeout;
5737 dev->watchdog_timeo = TX_TIMEOUT;
5738#ifdef BCM_VLAN
5739 dev->vlan_rx_register = bnx2_vlan_rx_register;
5740 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5741#endif
5742 dev->poll = bnx2_poll;
5743 dev->ethtool_ops = &bnx2_ethtool_ops;
5744 dev->weight = 64;
5745
972ec0d4 5746 bp = netdev_priv(dev);
b6016b76
MC		 5747
5748#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5749 dev->poll_controller = poll_bnx2;
5750#endif
5751
5752 if ((rc = register_netdev(dev))) {
5753 printk(KERN_ERR PFX "Cannot register net device\n");
5754 if (bp->regview)
5755 iounmap(bp->regview);
5756 pci_release_regions(pdev);
5757 pci_disable_device(pdev);
5758 pci_set_drvdata(pdev, NULL);
5759 free_netdev(dev);
5760 return rc;
5761 }
5762
5763 pci_set_drvdata(pdev, dev);
5764
5765 memcpy(dev->dev_addr, bp->mac_addr, 6);
24b8e05d 5766 memcpy(dev->perm_addr, bp->mac_addr, 6);
b6016b76
MC		 5767 bp->name = board_info[ent->driver_data].name,
5768 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5769 "IRQ %d, ",
5770 dev->name,
5771 bp->name,
5772 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5773 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5774 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5775 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5776 bp->bus_speed_mhz,
5777 dev->base_addr,
5778 bp->pdev->irq);
5779
5780 printk("node addr ");
5781 for (i = 0; i < 6; i++)
5782 printk("%2.2x", dev->dev_addr[i]);
5783 printk("\n");
5784
5785 dev->features |= NETIF_F_SG;
5786 if (bp->flags & USING_DAC_FLAG)
5787 dev->features |= NETIF_F_HIGHDMA;
5788 dev->features |= NETIF_F_IP_CSUM;
5789#ifdef BCM_VLAN
5790 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5791#endif
5792#ifdef BCM_TSO
5793 dev->features |= NETIF_F_TSO;
5794#endif
5795
5796 netif_carrier_off(bp->dev);
5797
5798 return 0;
5799}
5800
5801static void __devexit
5802bnx2_remove_one(struct pci_dev *pdev)
5803{
5804 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 5805 struct bnx2 *bp = netdev_priv(dev);
b6016b76 5806
afdc08b9
MC		 5807 flush_scheduled_work();
5808
b6016b76
MC		 5809 unregister_netdev(dev);
5810
5811 if (bp->regview)
5812 iounmap(bp->regview);
5813
5814 free_netdev(dev);
5815 pci_release_regions(pdev);
5816 pci_disable_device(pdev);
5817 pci_set_drvdata(pdev, NULL);
5818}
5819
5820static int
829ca9a3 5821bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 5822{
5823 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 5824 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5825 u32 reset_code;
5826
5827 if (!netif_running(dev))
5828 return 0;
5829
1d60290f 5830 flush_scheduled_work();
b6016b76
MC		 5831 bnx2_netif_stop(bp);
5832 netif_device_detach(dev);
5833 del_timer_sync(&bp->timer);
dda1e390
MC		 5834 if (bp->flags & NO_WOL_FLAG)
5835 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
5836 else if (bp->wol)
b6016b76
MC		 5837 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5838 else
5839 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5840 bnx2_reset_chip(bp, reset_code);
5841 bnx2_free_skbs(bp);
829ca9a3 5842 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 5843 return 0;
5844}
5845
5846static int
5847bnx2_resume(struct pci_dev *pdev)
5848{
5849 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 5850 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5851
5852 if (!netif_running(dev))
5853 return 0;
5854
829ca9a3 5855 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5856 netif_device_attach(dev);
5857 bnx2_init_nic(bp);
5858 bnx2_netif_start(bp);
5859 return 0;
5860}
5861
5862static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 5863 .name = DRV_MODULE_NAME,
5864 .id_table = bnx2_pci_tbl,
5865 .probe = bnx2_init_one,
5866 .remove = __devexit_p(bnx2_remove_one),
5867 .suspend = bnx2_suspend,
5868 .resume = bnx2_resume,
b6016b76
MC		 5869};
5870
5871static int __init bnx2_init(void)
5872{
5873 return pci_module_init(&bnx2_pci_driver);
5874}
5875
5876static void __exit bnx2_cleanup(void)
5877{
5878 pci_unregister_driver(&bnx2_pci_driver);
5879}
5880
5881module_init(bnx2_init);
5882module_exit(bnx2_cleanup);
5883
5884
5885
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