]>
Commit | Line | Data |
---|---|---|
b6016b76 MC |
1 | /* bnx2.c: Broadcom NX2 network driver. |
2 | * | |
bec92044 | 3 | * Copyright (c) 2004-2010 Broadcom Corporation |
b6016b76 MC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Written by: Michael Chan (mchan@broadcom.com) | |
10 | */ | |
11 | ||
f2a4f052 MC |
12 | |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/vmalloc.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/skbuff.h> | |
28 | #include <linux/dma-mapping.h> | |
1977f032 | 29 | #include <linux/bitops.h> |
f2a4f052 MC |
30 | #include <asm/io.h> |
31 | #include <asm/irq.h> | |
32 | #include <linux/delay.h> | |
33 | #include <asm/byteorder.h> | |
c86a31f4 | 34 | #include <asm/page.h> |
f2a4f052 MC |
35 | #include <linux/time.h> |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/mii.h> | |
f2a4f052 | 38 | #include <linux/if_vlan.h> |
08013fa3 | 39 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
f2a4f052 MC |
40 | #define BCM_VLAN 1 |
41 | #endif | |
f2a4f052 | 42 | #include <net/ip.h> |
de081fa5 | 43 | #include <net/tcp.h> |
f2a4f052 | 44 | #include <net/checksum.h> |
f2a4f052 MC |
45 | #include <linux/workqueue.h> |
46 | #include <linux/crc32.h> | |
47 | #include <linux/prefetch.h> | |
29b12174 | 48 | #include <linux/cache.h> |
57579f76 | 49 | #include <linux/firmware.h> |
706bf240 | 50 | #include <linux/log2.h> |
f2a4f052 | 51 | |
4edd473f MC |
52 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
53 | #define BCM_CNIC 1 | |
54 | #include "cnic_if.h" | |
55 | #endif | |
b6016b76 MC |
56 | #include "bnx2.h" |
57 | #include "bnx2_fw.h" | |
b3448b0b | 58 | |
b6016b76 MC |
59 | #define DRV_MODULE_NAME "bnx2" |
60 | #define PFX DRV_MODULE_NAME ": " | |
bec92044 MC |
61 | #define DRV_MODULE_VERSION "2.0.8" |
62 | #define DRV_MODULE_RELDATE "Feb 15, 2010" | |
63 | #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw" | |
078b0735 | 64 | #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw" |
bec92044 MC |
65 | #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j9.fw" |
66 | #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw" | |
67 | #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw" | |
b6016b76 MC |
68 | |
69 | #define RUN_AT(x) (jiffies + (x)) | |
70 | ||
71 | /* Time in jiffies before concluding the transmitter is hung. */ | |
72 | #define TX_TIMEOUT (5*HZ) | |
73 | ||
fefa8645 | 74 | static char version[] __devinitdata = |
b6016b76 MC |
75 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
76 | ||
77 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); | |
453a9c6e | 78 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver"); |
b6016b76 MC |
79 | MODULE_LICENSE("GPL"); |
80 | MODULE_VERSION(DRV_MODULE_VERSION); | |
57579f76 MC |
81 | MODULE_FIRMWARE(FW_MIPS_FILE_06); |
82 | MODULE_FIRMWARE(FW_RV2P_FILE_06); | |
83 | MODULE_FIRMWARE(FW_MIPS_FILE_09); | |
84 | MODULE_FIRMWARE(FW_RV2P_FILE_09); | |
078b0735 | 85 | MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax); |
b6016b76 MC |
86 | |
87 | static int disable_msi = 0; | |
88 | ||
89 | module_param(disable_msi, int, 0); | |
90 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
91 | ||
92 | typedef enum { | |
93 | BCM5706 = 0, | |
94 | NC370T, | |
95 | NC370I, | |
96 | BCM5706S, | |
97 | NC370F, | |
5b0c76ad MC |
98 | BCM5708, |
99 | BCM5708S, | |
bac0dff6 | 100 | BCM5709, |
27a005b8 | 101 | BCM5709S, |
7bb0a04f | 102 | BCM5716, |
1caacecb | 103 | BCM5716S, |
b6016b76 MC |
104 | } board_t; |
105 | ||
106 | /* indexed by board_t, above */ | |
fefa8645 | 107 | static struct { |
b6016b76 MC |
108 | char *name; |
109 | } board_info[] __devinitdata = { | |
110 | { "Broadcom NetXtreme II BCM5706 1000Base-T" }, | |
111 | { "HP NC370T Multifunction Gigabit Server Adapter" }, | |
112 | { "HP NC370i Multifunction Gigabit Server Adapter" }, | |
113 | { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, | |
114 | { "HP NC370F Multifunction Gigabit Server Adapter" }, | |
5b0c76ad MC |
115 | { "Broadcom NetXtreme II BCM5708 1000Base-T" }, |
116 | { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, | |
bac0dff6 | 117 | { "Broadcom NetXtreme II BCM5709 1000Base-T" }, |
27a005b8 | 118 | { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, |
7bb0a04f | 119 | { "Broadcom NetXtreme II BCM5716 1000Base-T" }, |
1caacecb | 120 | { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, |
b6016b76 MC |
121 | }; |
122 | ||
7bb0a04f | 123 | static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { |
b6016b76 MC |
124 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, |
125 | PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, | |
126 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
127 | PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, | |
128 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
129 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, | |
5b0c76ad MC |
130 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, |
131 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 }, | |
b6016b76 MC |
132 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, |
133 | PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, | |
134 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | |
135 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, | |
5b0c76ad MC |
136 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, |
137 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, | |
bac0dff6 MC |
138 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, |
139 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, | |
27a005b8 MC |
140 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, |
141 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, | |
7bb0a04f MC |
142 | { PCI_VENDOR_ID_BROADCOM, 0x163b, |
143 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, | |
1caacecb | 144 | { PCI_VENDOR_ID_BROADCOM, 0x163c, |
1f2435e5 | 145 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, |
b6016b76 MC |
146 | { 0, } |
147 | }; | |
148 | ||
0ced9d01 | 149 | static const struct flash_spec flash_table[] = |
b6016b76 | 150 | { |
e30372c9 MC |
151 | #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) |
152 | #define NONBUFFERED_FLAGS (BNX2_NV_WREN) | |
b6016b76 | 153 | /* Slow EEPROM */ |
37137709 | 154 | {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, |
e30372c9 | 155 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
b6016b76 MC |
156 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
157 | "EEPROM - slow"}, | |
37137709 MC |
158 | /* Expansion entry 0001 */ |
159 | {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 160 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
161 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
162 | "Entry 0001"}, | |
b6016b76 MC |
163 | /* Saifun SA25F010 (non-buffered flash) */ |
164 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 165 | {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 166 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
167 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, |
168 | "Non-buffered flash (128kB)"}, | |
169 | /* Saifun SA25F020 (non-buffered flash) */ | |
170 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 171 | {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 172 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
173 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, |
174 | "Non-buffered flash (256kB)"}, | |
37137709 MC |
175 | /* Expansion entry 0100 */ |
176 | {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 177 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
178 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
179 | "Entry 0100"}, | |
180 | /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ | |
6aa20a22 | 181 | {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, |
e30372c9 | 182 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
183 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, |
184 | "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, | |
185 | /* Entry 0110: ST M45PE20 (non-buffered flash)*/ | |
186 | {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, | |
e30372c9 | 187 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
188 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, |
189 | "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, | |
190 | /* Saifun SA25F005 (non-buffered flash) */ | |
191 | /* strap, cfg1, & write1 need updates */ | |
192 | {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 193 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
194 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, |
195 | "Non-buffered flash (64kB)"}, | |
196 | /* Fast EEPROM */ | |
197 | {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, | |
e30372c9 | 198 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
37137709 MC |
199 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
200 | "EEPROM - fast"}, | |
201 | /* Expansion entry 1001 */ | |
202 | {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 203 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
204 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
205 | "Entry 1001"}, | |
206 | /* Expansion entry 1010 */ | |
207 | {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 208 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
209 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
210 | "Entry 1010"}, | |
211 | /* ATMEL AT45DB011B (buffered flash) */ | |
212 | {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 213 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
214 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, |
215 | "Buffered flash (128kB)"}, | |
216 | /* Expansion entry 1100 */ | |
217 | {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 218 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
219 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
220 | "Entry 1100"}, | |
221 | /* Expansion entry 1101 */ | |
222 | {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 223 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
224 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
225 | "Entry 1101"}, | |
226 | /* Ateml Expansion entry 1110 */ | |
227 | {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 228 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
229 | BUFFERED_FLASH_BYTE_ADDR_MASK, 0, |
230 | "Entry 1110 (Atmel)"}, | |
231 | /* ATMEL AT45DB021B (buffered flash) */ | |
232 | {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 233 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
234 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, |
235 | "Buffered flash (256kB)"}, | |
b6016b76 MC |
236 | }; |
237 | ||
0ced9d01 | 238 | static const struct flash_spec flash_5709 = { |
e30372c9 MC |
239 | .flags = BNX2_NV_BUFFERED, |
240 | .page_bits = BCM5709_FLASH_PAGE_BITS, | |
241 | .page_size = BCM5709_FLASH_PAGE_SIZE, | |
242 | .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, | |
243 | .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, | |
244 | .name = "5709 Buffered flash (256kB)", | |
245 | }; | |
246 | ||
b6016b76 MC |
247 | MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); |
248 | ||
35e9010b | 249 | static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) |
e89bbf10 | 250 | { |
2f8af120 | 251 | u32 diff; |
e89bbf10 | 252 | |
2f8af120 | 253 | smp_mb(); |
faac9c4b MC |
254 | |
255 | /* The ring uses 256 indices for 255 entries, one of them | |
256 | * needs to be skipped. | |
257 | */ | |
35e9010b | 258 | diff = txr->tx_prod - txr->tx_cons; |
faac9c4b MC |
259 | if (unlikely(diff >= TX_DESC_CNT)) { |
260 | diff &= 0xffff; | |
261 | if (diff == TX_DESC_CNT) | |
262 | diff = MAX_TX_DESC_CNT; | |
263 | } | |
e89bbf10 MC |
264 | return (bp->tx_ring_size - diff); |
265 | } | |
266 | ||
b6016b76 MC |
267 | static u32 |
268 | bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) | |
269 | { | |
1b8227c4 MC |
270 | u32 val; |
271 | ||
272 | spin_lock_bh(&bp->indirect_lock); | |
b6016b76 | 273 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
1b8227c4 MC |
274 | val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW); |
275 | spin_unlock_bh(&bp->indirect_lock); | |
276 | return val; | |
b6016b76 MC |
277 | } |
278 | ||
279 | static void | |
280 | bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) | |
281 | { | |
1b8227c4 | 282 | spin_lock_bh(&bp->indirect_lock); |
b6016b76 MC |
283 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
284 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); | |
1b8227c4 | 285 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
286 | } |
287 | ||
2726d6e1 MC |
288 | static void |
289 | bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) | |
290 | { | |
291 | bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); | |
292 | } | |
293 | ||
294 | static u32 | |
295 | bnx2_shmem_rd(struct bnx2 *bp, u32 offset) | |
296 | { | |
297 | return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset)); | |
298 | } | |
299 | ||
b6016b76 MC |
300 | static void |
301 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) | |
302 | { | |
303 | offset += cid_addr; | |
1b8227c4 | 304 | spin_lock_bh(&bp->indirect_lock); |
59b47d8a MC |
305 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
306 | int i; | |
307 | ||
308 | REG_WR(bp, BNX2_CTX_CTX_DATA, val); | |
309 | REG_WR(bp, BNX2_CTX_CTX_CTRL, | |
310 | offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); | |
311 | for (i = 0; i < 5; i++) { | |
59b47d8a MC |
312 | val = REG_RD(bp, BNX2_CTX_CTX_CTRL); |
313 | if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) | |
314 | break; | |
315 | udelay(5); | |
316 | } | |
317 | } else { | |
318 | REG_WR(bp, BNX2_CTX_DATA_ADR, offset); | |
319 | REG_WR(bp, BNX2_CTX_DATA, val); | |
320 | } | |
1b8227c4 | 321 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
322 | } |
323 | ||
4edd473f MC |
324 | #ifdef BCM_CNIC |
325 | static int | |
326 | bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) | |
327 | { | |
328 | struct bnx2 *bp = netdev_priv(dev); | |
329 | struct drv_ctl_io *io = &info->data.io; | |
330 | ||
331 | switch (info->cmd) { | |
332 | case DRV_CTL_IO_WR_CMD: | |
333 | bnx2_reg_wr_ind(bp, io->offset, io->data); | |
334 | break; | |
335 | case DRV_CTL_IO_RD_CMD: | |
336 | io->data = bnx2_reg_rd_ind(bp, io->offset); | |
337 | break; | |
338 | case DRV_CTL_CTX_WR_CMD: | |
339 | bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); | |
340 | break; | |
341 | default: | |
342 | return -EINVAL; | |
343 | } | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) | |
348 | { | |
349 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
350 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
351 | int sb_id; | |
352 | ||
353 | if (bp->flags & BNX2_FLAG_USING_MSIX) { | |
354 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
355 | bnapi->cnic_present = 0; | |
356 | sb_id = bp->irq_nvecs; | |
357 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
358 | } else { | |
359 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
360 | bnapi->cnic_tag = bnapi->last_status_idx; | |
361 | bnapi->cnic_present = 1; | |
362 | sb_id = 0; | |
363 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
364 | } | |
365 | ||
366 | cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; | |
367 | cp->irq_arr[0].status_blk = (void *) | |
368 | ((unsigned long) bnapi->status_blk.msi + | |
369 | (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); | |
370 | cp->irq_arr[0].status_blk_num = sb_id; | |
371 | cp->num_irq = 1; | |
372 | } | |
373 | ||
374 | static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
375 | void *data) | |
376 | { | |
377 | struct bnx2 *bp = netdev_priv(dev); | |
378 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
379 | ||
380 | if (ops == NULL) | |
381 | return -EINVAL; | |
382 | ||
383 | if (cp->drv_state & CNIC_DRV_STATE_REGD) | |
384 | return -EBUSY; | |
385 | ||
386 | bp->cnic_data = data; | |
387 | rcu_assign_pointer(bp->cnic_ops, ops); | |
388 | ||
389 | cp->num_irq = 0; | |
390 | cp->drv_state = CNIC_DRV_STATE_REGD; | |
391 | ||
392 | bnx2_setup_cnic_irq_info(bp); | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | static int bnx2_unregister_cnic(struct net_device *dev) | |
398 | { | |
399 | struct bnx2 *bp = netdev_priv(dev); | |
400 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
401 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
402 | ||
c5a88950 | 403 | mutex_lock(&bp->cnic_lock); |
4edd473f MC |
404 | cp->drv_state = 0; |
405 | bnapi->cnic_present = 0; | |
406 | rcu_assign_pointer(bp->cnic_ops, NULL); | |
c5a88950 | 407 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
408 | synchronize_rcu(); |
409 | return 0; | |
410 | } | |
411 | ||
412 | struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) | |
413 | { | |
414 | struct bnx2 *bp = netdev_priv(dev); | |
415 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
416 | ||
417 | cp->drv_owner = THIS_MODULE; | |
418 | cp->chip_id = bp->chip_id; | |
419 | cp->pdev = bp->pdev; | |
420 | cp->io_base = bp->regview; | |
421 | cp->drv_ctl = bnx2_drv_ctl; | |
422 | cp->drv_register_cnic = bnx2_register_cnic; | |
423 | cp->drv_unregister_cnic = bnx2_unregister_cnic; | |
424 | ||
425 | return cp; | |
426 | } | |
427 | EXPORT_SYMBOL(bnx2_cnic_probe); | |
428 | ||
429 | static void | |
430 | bnx2_cnic_stop(struct bnx2 *bp) | |
431 | { | |
432 | struct cnic_ops *c_ops; | |
433 | struct cnic_ctl_info info; | |
434 | ||
c5a88950 MC |
435 | mutex_lock(&bp->cnic_lock); |
436 | c_ops = bp->cnic_ops; | |
4edd473f MC |
437 | if (c_ops) { |
438 | info.cmd = CNIC_CTL_STOP_CMD; | |
439 | c_ops->cnic_ctl(bp->cnic_data, &info); | |
440 | } | |
c5a88950 | 441 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
442 | } |
443 | ||
444 | static void | |
445 | bnx2_cnic_start(struct bnx2 *bp) | |
446 | { | |
447 | struct cnic_ops *c_ops; | |
448 | struct cnic_ctl_info info; | |
449 | ||
c5a88950 MC |
450 | mutex_lock(&bp->cnic_lock); |
451 | c_ops = bp->cnic_ops; | |
4edd473f MC |
452 | if (c_ops) { |
453 | if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { | |
454 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
455 | ||
456 | bnapi->cnic_tag = bnapi->last_status_idx; | |
457 | } | |
458 | info.cmd = CNIC_CTL_START_CMD; | |
459 | c_ops->cnic_ctl(bp->cnic_data, &info); | |
460 | } | |
c5a88950 | 461 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
462 | } |
463 | ||
464 | #else | |
465 | ||
466 | static void | |
467 | bnx2_cnic_stop(struct bnx2 *bp) | |
468 | { | |
469 | } | |
470 | ||
471 | static void | |
472 | bnx2_cnic_start(struct bnx2 *bp) | |
473 | { | |
474 | } | |
475 | ||
476 | #endif | |
477 | ||
b6016b76 MC |
478 | static int |
479 | bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | |
480 | { | |
481 | u32 val1; | |
482 | int i, ret; | |
483 | ||
583c28e5 | 484 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
b6016b76 MC |
485 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
486 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
487 | ||
488 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
489 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
490 | ||
491 | udelay(40); | |
492 | } | |
493 | ||
494 | val1 = (bp->phy_addr << 21) | (reg << 16) | | |
495 | BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | | |
496 | BNX2_EMAC_MDIO_COMM_START_BUSY; | |
497 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | |
498 | ||
499 | for (i = 0; i < 50; i++) { | |
500 | udelay(10); | |
501 | ||
502 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
503 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | |
504 | udelay(5); | |
505 | ||
506 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
507 | val1 &= BNX2_EMAC_MDIO_COMM_DATA; | |
508 | ||
509 | break; | |
510 | } | |
511 | } | |
512 | ||
513 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { | |
514 | *val = 0x0; | |
515 | ret = -EBUSY; | |
516 | } | |
517 | else { | |
518 | *val = val1; | |
519 | ret = 0; | |
520 | } | |
521 | ||
583c28e5 | 522 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
b6016b76 MC |
523 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
524 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
525 | ||
526 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
527 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
528 | ||
529 | udelay(40); | |
530 | } | |
531 | ||
532 | return ret; | |
533 | } | |
534 | ||
535 | static int | |
536 | bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | |
537 | { | |
538 | u32 val1; | |
539 | int i, ret; | |
540 | ||
583c28e5 | 541 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
b6016b76 MC |
542 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
543 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
544 | ||
545 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
546 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
547 | ||
548 | udelay(40); | |
549 | } | |
550 | ||
551 | val1 = (bp->phy_addr << 21) | (reg << 16) | val | | |
552 | BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | | |
553 | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; | |
554 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | |
6aa20a22 | 555 | |
b6016b76 MC |
556 | for (i = 0; i < 50; i++) { |
557 | udelay(10); | |
558 | ||
559 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
560 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | |
561 | udelay(5); | |
562 | break; | |
563 | } | |
564 | } | |
565 | ||
566 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) | |
567 | ret = -EBUSY; | |
568 | else | |
569 | ret = 0; | |
570 | ||
583c28e5 | 571 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
b6016b76 MC |
572 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
573 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
574 | ||
575 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
576 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
577 | ||
578 | udelay(40); | |
579 | } | |
580 | ||
581 | return ret; | |
582 | } | |
583 | ||
584 | static void | |
585 | bnx2_disable_int(struct bnx2 *bp) | |
586 | { | |
b4b36042 MC |
587 | int i; |
588 | struct bnx2_napi *bnapi; | |
589 | ||
590 | for (i = 0; i < bp->irq_nvecs; i++) { | |
591 | bnapi = &bp->bnx2_napi[i]; | |
592 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | | |
593 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
594 | } | |
b6016b76 MC |
595 | REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); |
596 | } | |
597 | ||
598 | static void | |
599 | bnx2_enable_int(struct bnx2 *bp) | |
600 | { | |
b4b36042 MC |
601 | int i; |
602 | struct bnx2_napi *bnapi; | |
35efa7c1 | 603 | |
b4b36042 MC |
604 | for (i = 0; i < bp->irq_nvecs; i++) { |
605 | bnapi = &bp->bnx2_napi[i]; | |
1269a8a6 | 606 | |
b4b36042 MC |
607 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
608 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
609 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | | |
610 | bnapi->last_status_idx); | |
b6016b76 | 611 | |
b4b36042 MC |
612 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
613 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
614 | bnapi->last_status_idx); | |
615 | } | |
bf5295bb | 616 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
b6016b76 MC |
617 | } |
618 | ||
619 | static void | |
620 | bnx2_disable_int_sync(struct bnx2 *bp) | |
621 | { | |
b4b36042 MC |
622 | int i; |
623 | ||
b6016b76 | 624 | atomic_inc(&bp->intr_sem); |
3767546c MC |
625 | if (!netif_running(bp->dev)) |
626 | return; | |
627 | ||
b6016b76 | 628 | bnx2_disable_int(bp); |
b4b36042 MC |
629 | for (i = 0; i < bp->irq_nvecs; i++) |
630 | synchronize_irq(bp->irq_tbl[i].vector); | |
b6016b76 MC |
631 | } |
632 | ||
35efa7c1 MC |
633 | static void |
634 | bnx2_napi_disable(struct bnx2 *bp) | |
635 | { | |
b4b36042 MC |
636 | int i; |
637 | ||
638 | for (i = 0; i < bp->irq_nvecs; i++) | |
639 | napi_disable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
640 | } |
641 | ||
642 | static void | |
643 | bnx2_napi_enable(struct bnx2 *bp) | |
644 | { | |
b4b36042 MC |
645 | int i; |
646 | ||
647 | for (i = 0; i < bp->irq_nvecs; i++) | |
648 | napi_enable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
649 | } |
650 | ||
b6016b76 MC |
651 | static void |
652 | bnx2_netif_stop(struct bnx2 *bp) | |
653 | { | |
4edd473f | 654 | bnx2_cnic_stop(bp); |
b6016b76 | 655 | if (netif_running(bp->dev)) { |
e6bf95ff BL |
656 | int i; |
657 | ||
35efa7c1 | 658 | bnx2_napi_disable(bp); |
b6016b76 | 659 | netif_tx_disable(bp->dev); |
e6bf95ff BL |
660 | /* prevent tx timeout */ |
661 | for (i = 0; i < bp->dev->num_tx_queues; i++) { | |
662 | struct netdev_queue *txq; | |
663 | ||
664 | txq = netdev_get_tx_queue(bp->dev, i); | |
665 | txq->trans_start = jiffies; | |
666 | } | |
b6016b76 | 667 | } |
b7466560 | 668 | bnx2_disable_int_sync(bp); |
b6016b76 MC |
669 | } |
670 | ||
671 | static void | |
672 | bnx2_netif_start(struct bnx2 *bp) | |
673 | { | |
674 | if (atomic_dec_and_test(&bp->intr_sem)) { | |
675 | if (netif_running(bp->dev)) { | |
706bf240 | 676 | netif_tx_wake_all_queues(bp->dev); |
35efa7c1 | 677 | bnx2_napi_enable(bp); |
b6016b76 | 678 | bnx2_enable_int(bp); |
4edd473f | 679 | bnx2_cnic_start(bp); |
b6016b76 MC |
680 | } |
681 | } | |
682 | } | |
683 | ||
35e9010b MC |
684 | static void |
685 | bnx2_free_tx_mem(struct bnx2 *bp) | |
686 | { | |
687 | int i; | |
688 | ||
689 | for (i = 0; i < bp->num_tx_rings; i++) { | |
690 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
691 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
692 | ||
693 | if (txr->tx_desc_ring) { | |
694 | pci_free_consistent(bp->pdev, TXBD_RING_SIZE, | |
695 | txr->tx_desc_ring, | |
696 | txr->tx_desc_mapping); | |
697 | txr->tx_desc_ring = NULL; | |
698 | } | |
699 | kfree(txr->tx_buf_ring); | |
700 | txr->tx_buf_ring = NULL; | |
701 | } | |
702 | } | |
703 | ||
bb4f98ab MC |
704 | static void |
705 | bnx2_free_rx_mem(struct bnx2 *bp) | |
706 | { | |
707 | int i; | |
708 | ||
709 | for (i = 0; i < bp->num_rx_rings; i++) { | |
710 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
711 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
712 | int j; | |
713 | ||
714 | for (j = 0; j < bp->rx_max_ring; j++) { | |
715 | if (rxr->rx_desc_ring[j]) | |
716 | pci_free_consistent(bp->pdev, RXBD_RING_SIZE, | |
717 | rxr->rx_desc_ring[j], | |
718 | rxr->rx_desc_mapping[j]); | |
719 | rxr->rx_desc_ring[j] = NULL; | |
720 | } | |
25b0b999 | 721 | vfree(rxr->rx_buf_ring); |
bb4f98ab MC |
722 | rxr->rx_buf_ring = NULL; |
723 | ||
724 | for (j = 0; j < bp->rx_max_pg_ring; j++) { | |
725 | if (rxr->rx_pg_desc_ring[j]) | |
726 | pci_free_consistent(bp->pdev, RXBD_RING_SIZE, | |
3298a738 MC |
727 | rxr->rx_pg_desc_ring[j], |
728 | rxr->rx_pg_desc_mapping[j]); | |
729 | rxr->rx_pg_desc_ring[j] = NULL; | |
bb4f98ab | 730 | } |
25b0b999 | 731 | vfree(rxr->rx_pg_ring); |
bb4f98ab MC |
732 | rxr->rx_pg_ring = NULL; |
733 | } | |
734 | } | |
735 | ||
35e9010b MC |
736 | static int |
737 | bnx2_alloc_tx_mem(struct bnx2 *bp) | |
738 | { | |
739 | int i; | |
740 | ||
741 | for (i = 0; i < bp->num_tx_rings; i++) { | |
742 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
743 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
744 | ||
745 | txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); | |
746 | if (txr->tx_buf_ring == NULL) | |
747 | return -ENOMEM; | |
748 | ||
749 | txr->tx_desc_ring = | |
750 | pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE, | |
751 | &txr->tx_desc_mapping); | |
752 | if (txr->tx_desc_ring == NULL) | |
753 | return -ENOMEM; | |
754 | } | |
755 | return 0; | |
756 | } | |
757 | ||
bb4f98ab MC |
758 | static int |
759 | bnx2_alloc_rx_mem(struct bnx2 *bp) | |
760 | { | |
761 | int i; | |
762 | ||
763 | for (i = 0; i < bp->num_rx_rings; i++) { | |
764 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
765 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
766 | int j; | |
767 | ||
768 | rxr->rx_buf_ring = | |
769 | vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); | |
770 | if (rxr->rx_buf_ring == NULL) | |
771 | return -ENOMEM; | |
772 | ||
773 | memset(rxr->rx_buf_ring, 0, | |
774 | SW_RXBD_RING_SIZE * bp->rx_max_ring); | |
775 | ||
776 | for (j = 0; j < bp->rx_max_ring; j++) { | |
777 | rxr->rx_desc_ring[j] = | |
778 | pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, | |
779 | &rxr->rx_desc_mapping[j]); | |
780 | if (rxr->rx_desc_ring[j] == NULL) | |
781 | return -ENOMEM; | |
782 | ||
783 | } | |
784 | ||
785 | if (bp->rx_pg_ring_size) { | |
786 | rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE * | |
787 | bp->rx_max_pg_ring); | |
788 | if (rxr->rx_pg_ring == NULL) | |
789 | return -ENOMEM; | |
790 | ||
791 | memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE * | |
792 | bp->rx_max_pg_ring); | |
793 | } | |
794 | ||
795 | for (j = 0; j < bp->rx_max_pg_ring; j++) { | |
796 | rxr->rx_pg_desc_ring[j] = | |
797 | pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, | |
798 | &rxr->rx_pg_desc_mapping[j]); | |
799 | if (rxr->rx_pg_desc_ring[j] == NULL) | |
800 | return -ENOMEM; | |
801 | ||
802 | } | |
803 | } | |
804 | return 0; | |
805 | } | |
806 | ||
b6016b76 MC |
807 | static void |
808 | bnx2_free_mem(struct bnx2 *bp) | |
809 | { | |
13daffa2 | 810 | int i; |
43e80b89 | 811 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
13daffa2 | 812 | |
35e9010b | 813 | bnx2_free_tx_mem(bp); |
bb4f98ab | 814 | bnx2_free_rx_mem(bp); |
35e9010b | 815 | |
59b47d8a MC |
816 | for (i = 0; i < bp->ctx_pages; i++) { |
817 | if (bp->ctx_blk[i]) { | |
818 | pci_free_consistent(bp->pdev, BCM_PAGE_SIZE, | |
819 | bp->ctx_blk[i], | |
820 | bp->ctx_blk_mapping[i]); | |
821 | bp->ctx_blk[i] = NULL; | |
822 | } | |
823 | } | |
43e80b89 | 824 | if (bnapi->status_blk.msi) { |
0f31f994 | 825 | pci_free_consistent(bp->pdev, bp->status_stats_size, |
43e80b89 MC |
826 | bnapi->status_blk.msi, |
827 | bp->status_blk_mapping); | |
828 | bnapi->status_blk.msi = NULL; | |
0f31f994 | 829 | bp->stats_blk = NULL; |
b6016b76 | 830 | } |
b6016b76 MC |
831 | } |
832 | ||
833 | static int | |
834 | bnx2_alloc_mem(struct bnx2 *bp) | |
835 | { | |
35e9010b | 836 | int i, status_blk_size, err; |
43e80b89 MC |
837 | struct bnx2_napi *bnapi; |
838 | void *status_blk; | |
b6016b76 | 839 | |
0f31f994 MC |
840 | /* Combine status and statistics blocks into one allocation. */ |
841 | status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); | |
f86e82fb | 842 | if (bp->flags & BNX2_FLAG_MSIX_CAP) |
b4b36042 MC |
843 | status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * |
844 | BNX2_SBLK_MSIX_ALIGN_SIZE); | |
0f31f994 MC |
845 | bp->status_stats_size = status_blk_size + |
846 | sizeof(struct statistics_block); | |
847 | ||
43e80b89 MC |
848 | status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size, |
849 | &bp->status_blk_mapping); | |
850 | if (status_blk == NULL) | |
b6016b76 MC |
851 | goto alloc_mem_err; |
852 | ||
43e80b89 | 853 | memset(status_blk, 0, bp->status_stats_size); |
b6016b76 | 854 | |
43e80b89 MC |
855 | bnapi = &bp->bnx2_napi[0]; |
856 | bnapi->status_blk.msi = status_blk; | |
857 | bnapi->hw_tx_cons_ptr = | |
858 | &bnapi->status_blk.msi->status_tx_quick_consumer_index0; | |
859 | bnapi->hw_rx_cons_ptr = | |
860 | &bnapi->status_blk.msi->status_rx_quick_consumer_index0; | |
f86e82fb | 861 | if (bp->flags & BNX2_FLAG_MSIX_CAP) { |
b4b36042 | 862 | for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) { |
43e80b89 MC |
863 | struct status_block_msix *sblk; |
864 | ||
865 | bnapi = &bp->bnx2_napi[i]; | |
b4b36042 | 866 | |
43e80b89 MC |
867 | sblk = (void *) (status_blk + |
868 | BNX2_SBLK_MSIX_ALIGN_SIZE * i); | |
869 | bnapi->status_blk.msix = sblk; | |
870 | bnapi->hw_tx_cons_ptr = | |
871 | &sblk->status_tx_quick_consumer_index; | |
872 | bnapi->hw_rx_cons_ptr = | |
873 | &sblk->status_rx_quick_consumer_index; | |
b4b36042 MC |
874 | bnapi->int_num = i << 24; |
875 | } | |
876 | } | |
35efa7c1 | 877 | |
43e80b89 | 878 | bp->stats_blk = status_blk + status_blk_size; |
b6016b76 | 879 | |
0f31f994 | 880 | bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; |
b6016b76 | 881 | |
59b47d8a MC |
882 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
883 | bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE; | |
884 | if (bp->ctx_pages == 0) | |
885 | bp->ctx_pages = 1; | |
886 | for (i = 0; i < bp->ctx_pages; i++) { | |
887 | bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev, | |
888 | BCM_PAGE_SIZE, | |
889 | &bp->ctx_blk_mapping[i]); | |
890 | if (bp->ctx_blk[i] == NULL) | |
891 | goto alloc_mem_err; | |
892 | } | |
893 | } | |
35e9010b | 894 | |
bb4f98ab MC |
895 | err = bnx2_alloc_rx_mem(bp); |
896 | if (err) | |
897 | goto alloc_mem_err; | |
898 | ||
35e9010b MC |
899 | err = bnx2_alloc_tx_mem(bp); |
900 | if (err) | |
901 | goto alloc_mem_err; | |
902 | ||
b6016b76 MC |
903 | return 0; |
904 | ||
905 | alloc_mem_err: | |
906 | bnx2_free_mem(bp); | |
907 | return -ENOMEM; | |
908 | } | |
909 | ||
e3648b3d MC |
910 | static void |
911 | bnx2_report_fw_link(struct bnx2 *bp) | |
912 | { | |
913 | u32 fw_link_status = 0; | |
914 | ||
583c28e5 | 915 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
916 | return; |
917 | ||
e3648b3d MC |
918 | if (bp->link_up) { |
919 | u32 bmsr; | |
920 | ||
921 | switch (bp->line_speed) { | |
922 | case SPEED_10: | |
923 | if (bp->duplex == DUPLEX_HALF) | |
924 | fw_link_status = BNX2_LINK_STATUS_10HALF; | |
925 | else | |
926 | fw_link_status = BNX2_LINK_STATUS_10FULL; | |
927 | break; | |
928 | case SPEED_100: | |
929 | if (bp->duplex == DUPLEX_HALF) | |
930 | fw_link_status = BNX2_LINK_STATUS_100HALF; | |
931 | else | |
932 | fw_link_status = BNX2_LINK_STATUS_100FULL; | |
933 | break; | |
934 | case SPEED_1000: | |
935 | if (bp->duplex == DUPLEX_HALF) | |
936 | fw_link_status = BNX2_LINK_STATUS_1000HALF; | |
937 | else | |
938 | fw_link_status = BNX2_LINK_STATUS_1000FULL; | |
939 | break; | |
940 | case SPEED_2500: | |
941 | if (bp->duplex == DUPLEX_HALF) | |
942 | fw_link_status = BNX2_LINK_STATUS_2500HALF; | |
943 | else | |
944 | fw_link_status = BNX2_LINK_STATUS_2500FULL; | |
945 | break; | |
946 | } | |
947 | ||
948 | fw_link_status |= BNX2_LINK_STATUS_LINK_UP; | |
949 | ||
950 | if (bp->autoneg) { | |
951 | fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; | |
952 | ||
ca58c3af MC |
953 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
954 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
e3648b3d MC |
955 | |
956 | if (!(bmsr & BMSR_ANEGCOMPLETE) || | |
583c28e5 | 957 | bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) |
e3648b3d MC |
958 | fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; |
959 | else | |
960 | fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; | |
961 | } | |
962 | } | |
963 | else | |
964 | fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; | |
965 | ||
2726d6e1 | 966 | bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); |
e3648b3d MC |
967 | } |
968 | ||
9b1084b8 MC |
969 | static char * |
970 | bnx2_xceiver_str(struct bnx2 *bp) | |
971 | { | |
972 | return ((bp->phy_port == PORT_FIBRE) ? "SerDes" : | |
583c28e5 | 973 | ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : |
9b1084b8 MC |
974 | "Copper")); |
975 | } | |
976 | ||
b6016b76 MC |
977 | static void |
978 | bnx2_report_link(struct bnx2 *bp) | |
979 | { | |
980 | if (bp->link_up) { | |
981 | netif_carrier_on(bp->dev); | |
9b1084b8 MC |
982 | printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name, |
983 | bnx2_xceiver_str(bp)); | |
b6016b76 MC |
984 | |
985 | printk("%d Mbps ", bp->line_speed); | |
986 | ||
987 | if (bp->duplex == DUPLEX_FULL) | |
988 | printk("full duplex"); | |
989 | else | |
990 | printk("half duplex"); | |
991 | ||
992 | if (bp->flow_ctrl) { | |
993 | if (bp->flow_ctrl & FLOW_CTRL_RX) { | |
994 | printk(", receive "); | |
995 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
996 | printk("& transmit "); | |
997 | } | |
998 | else { | |
999 | printk(", transmit "); | |
1000 | } | |
1001 | printk("flow control ON"); | |
1002 | } | |
1003 | printk("\n"); | |
1004 | } | |
1005 | else { | |
1006 | netif_carrier_off(bp->dev); | |
9b1084b8 MC |
1007 | printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name, |
1008 | bnx2_xceiver_str(bp)); | |
b6016b76 | 1009 | } |
e3648b3d MC |
1010 | |
1011 | bnx2_report_fw_link(bp); | |
b6016b76 MC |
1012 | } |
1013 | ||
1014 | static void | |
1015 | bnx2_resolve_flow_ctrl(struct bnx2 *bp) | |
1016 | { | |
1017 | u32 local_adv, remote_adv; | |
1018 | ||
1019 | bp->flow_ctrl = 0; | |
6aa20a22 | 1020 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != |
b6016b76 MC |
1021 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { |
1022 | ||
1023 | if (bp->duplex == DUPLEX_FULL) { | |
1024 | bp->flow_ctrl = bp->req_flow_ctrl; | |
1025 | } | |
1026 | return; | |
1027 | } | |
1028 | ||
1029 | if (bp->duplex != DUPLEX_FULL) { | |
1030 | return; | |
1031 | } | |
1032 | ||
583c28e5 | 1033 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
5b0c76ad MC |
1034 | (CHIP_NUM(bp) == CHIP_NUM_5708)) { |
1035 | u32 val; | |
1036 | ||
1037 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
1038 | if (val & BCM5708S_1000X_STAT1_TX_PAUSE) | |
1039 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
1040 | if (val & BCM5708S_1000X_STAT1_RX_PAUSE) | |
1041 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
1042 | return; | |
1043 | } | |
1044 | ||
ca58c3af MC |
1045 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1046 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 | 1047 | |
583c28e5 | 1048 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1049 | u32 new_local_adv = 0; |
1050 | u32 new_remote_adv = 0; | |
1051 | ||
1052 | if (local_adv & ADVERTISE_1000XPAUSE) | |
1053 | new_local_adv |= ADVERTISE_PAUSE_CAP; | |
1054 | if (local_adv & ADVERTISE_1000XPSE_ASYM) | |
1055 | new_local_adv |= ADVERTISE_PAUSE_ASYM; | |
1056 | if (remote_adv & ADVERTISE_1000XPAUSE) | |
1057 | new_remote_adv |= ADVERTISE_PAUSE_CAP; | |
1058 | if (remote_adv & ADVERTISE_1000XPSE_ASYM) | |
1059 | new_remote_adv |= ADVERTISE_PAUSE_ASYM; | |
1060 | ||
1061 | local_adv = new_local_adv; | |
1062 | remote_adv = new_remote_adv; | |
1063 | } | |
1064 | ||
1065 | /* See Table 28B-3 of 802.3ab-1999 spec. */ | |
1066 | if (local_adv & ADVERTISE_PAUSE_CAP) { | |
1067 | if(local_adv & ADVERTISE_PAUSE_ASYM) { | |
1068 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
1069 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1070 | } | |
1071 | else if (remote_adv & ADVERTISE_PAUSE_ASYM) { | |
1072 | bp->flow_ctrl = FLOW_CTRL_RX; | |
1073 | } | |
1074 | } | |
1075 | else { | |
1076 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
1077 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1078 | } | |
1079 | } | |
1080 | } | |
1081 | else if (local_adv & ADVERTISE_PAUSE_ASYM) { | |
1082 | if ((remote_adv & ADVERTISE_PAUSE_CAP) && | |
1083 | (remote_adv & ADVERTISE_PAUSE_ASYM)) { | |
1084 | ||
1085 | bp->flow_ctrl = FLOW_CTRL_TX; | |
1086 | } | |
1087 | } | |
1088 | } | |
1089 | ||
27a005b8 MC |
1090 | static int |
1091 | bnx2_5709s_linkup(struct bnx2 *bp) | |
1092 | { | |
1093 | u32 val, speed; | |
1094 | ||
1095 | bp->link_up = 1; | |
1096 | ||
1097 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); | |
1098 | bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); | |
1099 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1100 | ||
1101 | if ((bp->autoneg & AUTONEG_SPEED) == 0) { | |
1102 | bp->line_speed = bp->req_line_speed; | |
1103 | bp->duplex = bp->req_duplex; | |
1104 | return 0; | |
1105 | } | |
1106 | speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; | |
1107 | switch (speed) { | |
1108 | case MII_BNX2_GP_TOP_AN_SPEED_10: | |
1109 | bp->line_speed = SPEED_10; | |
1110 | break; | |
1111 | case MII_BNX2_GP_TOP_AN_SPEED_100: | |
1112 | bp->line_speed = SPEED_100; | |
1113 | break; | |
1114 | case MII_BNX2_GP_TOP_AN_SPEED_1G: | |
1115 | case MII_BNX2_GP_TOP_AN_SPEED_1GKV: | |
1116 | bp->line_speed = SPEED_1000; | |
1117 | break; | |
1118 | case MII_BNX2_GP_TOP_AN_SPEED_2_5G: | |
1119 | bp->line_speed = SPEED_2500; | |
1120 | break; | |
1121 | } | |
1122 | if (val & MII_BNX2_GP_TOP_AN_FD) | |
1123 | bp->duplex = DUPLEX_FULL; | |
1124 | else | |
1125 | bp->duplex = DUPLEX_HALF; | |
1126 | return 0; | |
1127 | } | |
1128 | ||
b6016b76 | 1129 | static int |
5b0c76ad MC |
1130 | bnx2_5708s_linkup(struct bnx2 *bp) |
1131 | { | |
1132 | u32 val; | |
1133 | ||
1134 | bp->link_up = 1; | |
1135 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
1136 | switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { | |
1137 | case BCM5708S_1000X_STAT1_SPEED_10: | |
1138 | bp->line_speed = SPEED_10; | |
1139 | break; | |
1140 | case BCM5708S_1000X_STAT1_SPEED_100: | |
1141 | bp->line_speed = SPEED_100; | |
1142 | break; | |
1143 | case BCM5708S_1000X_STAT1_SPEED_1G: | |
1144 | bp->line_speed = SPEED_1000; | |
1145 | break; | |
1146 | case BCM5708S_1000X_STAT1_SPEED_2G5: | |
1147 | bp->line_speed = SPEED_2500; | |
1148 | break; | |
1149 | } | |
1150 | if (val & BCM5708S_1000X_STAT1_FD) | |
1151 | bp->duplex = DUPLEX_FULL; | |
1152 | else | |
1153 | bp->duplex = DUPLEX_HALF; | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | static int | |
1159 | bnx2_5706s_linkup(struct bnx2 *bp) | |
b6016b76 MC |
1160 | { |
1161 | u32 bmcr, local_adv, remote_adv, common; | |
1162 | ||
1163 | bp->link_up = 1; | |
1164 | bp->line_speed = SPEED_1000; | |
1165 | ||
ca58c3af | 1166 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
1167 | if (bmcr & BMCR_FULLDPLX) { |
1168 | bp->duplex = DUPLEX_FULL; | |
1169 | } | |
1170 | else { | |
1171 | bp->duplex = DUPLEX_HALF; | |
1172 | } | |
1173 | ||
1174 | if (!(bmcr & BMCR_ANENABLE)) { | |
1175 | return 0; | |
1176 | } | |
1177 | ||
ca58c3af MC |
1178 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1179 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
1180 | |
1181 | common = local_adv & remote_adv; | |
1182 | if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { | |
1183 | ||
1184 | if (common & ADVERTISE_1000XFULL) { | |
1185 | bp->duplex = DUPLEX_FULL; | |
1186 | } | |
1187 | else { | |
1188 | bp->duplex = DUPLEX_HALF; | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | static int | |
1196 | bnx2_copper_linkup(struct bnx2 *bp) | |
1197 | { | |
1198 | u32 bmcr; | |
1199 | ||
ca58c3af | 1200 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
1201 | if (bmcr & BMCR_ANENABLE) { |
1202 | u32 local_adv, remote_adv, common; | |
1203 | ||
1204 | bnx2_read_phy(bp, MII_CTRL1000, &local_adv); | |
1205 | bnx2_read_phy(bp, MII_STAT1000, &remote_adv); | |
1206 | ||
1207 | common = local_adv & (remote_adv >> 2); | |
1208 | if (common & ADVERTISE_1000FULL) { | |
1209 | bp->line_speed = SPEED_1000; | |
1210 | bp->duplex = DUPLEX_FULL; | |
1211 | } | |
1212 | else if (common & ADVERTISE_1000HALF) { | |
1213 | bp->line_speed = SPEED_1000; | |
1214 | bp->duplex = DUPLEX_HALF; | |
1215 | } | |
1216 | else { | |
ca58c3af MC |
1217 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1218 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
1219 | |
1220 | common = local_adv & remote_adv; | |
1221 | if (common & ADVERTISE_100FULL) { | |
1222 | bp->line_speed = SPEED_100; | |
1223 | bp->duplex = DUPLEX_FULL; | |
1224 | } | |
1225 | else if (common & ADVERTISE_100HALF) { | |
1226 | bp->line_speed = SPEED_100; | |
1227 | bp->duplex = DUPLEX_HALF; | |
1228 | } | |
1229 | else if (common & ADVERTISE_10FULL) { | |
1230 | bp->line_speed = SPEED_10; | |
1231 | bp->duplex = DUPLEX_FULL; | |
1232 | } | |
1233 | else if (common & ADVERTISE_10HALF) { | |
1234 | bp->line_speed = SPEED_10; | |
1235 | bp->duplex = DUPLEX_HALF; | |
1236 | } | |
1237 | else { | |
1238 | bp->line_speed = 0; | |
1239 | bp->link_up = 0; | |
1240 | } | |
1241 | } | |
1242 | } | |
1243 | else { | |
1244 | if (bmcr & BMCR_SPEED100) { | |
1245 | bp->line_speed = SPEED_100; | |
1246 | } | |
1247 | else { | |
1248 | bp->line_speed = SPEED_10; | |
1249 | } | |
1250 | if (bmcr & BMCR_FULLDPLX) { | |
1251 | bp->duplex = DUPLEX_FULL; | |
1252 | } | |
1253 | else { | |
1254 | bp->duplex = DUPLEX_HALF; | |
1255 | } | |
1256 | } | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
83e3fc89 | 1261 | static void |
bb4f98ab | 1262 | bnx2_init_rx_context(struct bnx2 *bp, u32 cid) |
83e3fc89 | 1263 | { |
bb4f98ab | 1264 | u32 val, rx_cid_addr = GET_CID_ADDR(cid); |
83e3fc89 MC |
1265 | |
1266 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; | |
1267 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; | |
1268 | val |= 0x02 << 8; | |
1269 | ||
1270 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
1271 | u32 lo_water, hi_water; | |
1272 | ||
1273 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
1274 | lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT; | |
1275 | else | |
1276 | lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS; | |
1277 | if (lo_water >= bp->rx_ring_size) | |
1278 | lo_water = 0; | |
1279 | ||
5726026b | 1280 | hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16); |
83e3fc89 MC |
1281 | |
1282 | if (hi_water <= lo_water) | |
1283 | lo_water = 0; | |
1284 | ||
1285 | hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE; | |
1286 | lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE; | |
1287 | ||
1288 | if (hi_water > 0xf) | |
1289 | hi_water = 0xf; | |
1290 | else if (hi_water == 0) | |
1291 | lo_water = 0; | |
1292 | val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT); | |
1293 | } | |
1294 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); | |
1295 | } | |
1296 | ||
bb4f98ab MC |
1297 | static void |
1298 | bnx2_init_all_rx_contexts(struct bnx2 *bp) | |
1299 | { | |
1300 | int i; | |
1301 | u32 cid; | |
1302 | ||
1303 | for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { | |
1304 | if (i == 1) | |
1305 | cid = RX_RSS_CID; | |
1306 | bnx2_init_rx_context(bp, cid); | |
1307 | } | |
1308 | } | |
1309 | ||
344478db | 1310 | static void |
b6016b76 MC |
1311 | bnx2_set_mac_link(struct bnx2 *bp) |
1312 | { | |
1313 | u32 val; | |
1314 | ||
1315 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); | |
1316 | if (bp->link_up && (bp->line_speed == SPEED_1000) && | |
1317 | (bp->duplex == DUPLEX_HALF)) { | |
1318 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); | |
1319 | } | |
1320 | ||
1321 | /* Configure the EMAC mode register. */ | |
1322 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
1323 | ||
1324 | val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | |
5b0c76ad | 1325 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | |
59b47d8a | 1326 | BNX2_EMAC_MODE_25G_MODE); |
b6016b76 MC |
1327 | |
1328 | if (bp->link_up) { | |
5b0c76ad MC |
1329 | switch (bp->line_speed) { |
1330 | case SPEED_10: | |
59b47d8a MC |
1331 | if (CHIP_NUM(bp) != CHIP_NUM_5706) { |
1332 | val |= BNX2_EMAC_MODE_PORT_MII_10M; | |
5b0c76ad MC |
1333 | break; |
1334 | } | |
1335 | /* fall through */ | |
1336 | case SPEED_100: | |
1337 | val |= BNX2_EMAC_MODE_PORT_MII; | |
1338 | break; | |
1339 | case SPEED_2500: | |
59b47d8a | 1340 | val |= BNX2_EMAC_MODE_25G_MODE; |
5b0c76ad MC |
1341 | /* fall through */ |
1342 | case SPEED_1000: | |
1343 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1344 | break; | |
1345 | } | |
b6016b76 MC |
1346 | } |
1347 | else { | |
1348 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1349 | } | |
1350 | ||
1351 | /* Set the MAC to operate in the appropriate duplex mode. */ | |
1352 | if (bp->duplex == DUPLEX_HALF) | |
1353 | val |= BNX2_EMAC_MODE_HALF_DUPLEX; | |
1354 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
1355 | ||
1356 | /* Enable/disable rx PAUSE. */ | |
1357 | bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; | |
1358 | ||
1359 | if (bp->flow_ctrl & FLOW_CTRL_RX) | |
1360 | bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; | |
1361 | REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); | |
1362 | ||
1363 | /* Enable/disable tx PAUSE. */ | |
1364 | val = REG_RD(bp, BNX2_EMAC_TX_MODE); | |
1365 | val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; | |
1366 | ||
1367 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
1368 | val |= BNX2_EMAC_TX_MODE_FLOW_EN; | |
1369 | REG_WR(bp, BNX2_EMAC_TX_MODE, val); | |
1370 | ||
1371 | /* Acknowledge the interrupt. */ | |
1372 | REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); | |
1373 | ||
83e3fc89 | 1374 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
bb4f98ab | 1375 | bnx2_init_all_rx_contexts(bp); |
b6016b76 MC |
1376 | } |
1377 | ||
27a005b8 MC |
1378 | static void |
1379 | bnx2_enable_bmsr1(struct bnx2 *bp) | |
1380 | { | |
583c28e5 | 1381 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
27a005b8 MC |
1382 | (CHIP_NUM(bp) == CHIP_NUM_5709)) |
1383 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1384 | MII_BNX2_BLK_ADDR_GP_STATUS); | |
1385 | } | |
1386 | ||
1387 | static void | |
1388 | bnx2_disable_bmsr1(struct bnx2 *bp) | |
1389 | { | |
583c28e5 | 1390 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
27a005b8 MC |
1391 | (CHIP_NUM(bp) == CHIP_NUM_5709)) |
1392 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1393 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1394 | } | |
1395 | ||
605a9e20 MC |
1396 | static int |
1397 | bnx2_test_and_enable_2g5(struct bnx2 *bp) | |
1398 | { | |
1399 | u32 up1; | |
1400 | int ret = 1; | |
1401 | ||
583c28e5 | 1402 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1403 | return 0; |
1404 | ||
1405 | if (bp->autoneg & AUTONEG_SPEED) | |
1406 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1407 | ||
27a005b8 MC |
1408 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1409 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
1410 | ||
605a9e20 MC |
1411 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1412 | if (!(up1 & BCM5708S_UP1_2G5)) { | |
1413 | up1 |= BCM5708S_UP1_2G5; | |
1414 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1415 | ret = 0; | |
1416 | } | |
1417 | ||
27a005b8 MC |
1418 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1419 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1420 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1421 | ||
605a9e20 MC |
1422 | return ret; |
1423 | } | |
1424 | ||
1425 | static int | |
1426 | bnx2_test_and_disable_2g5(struct bnx2 *bp) | |
1427 | { | |
1428 | u32 up1; | |
1429 | int ret = 0; | |
1430 | ||
583c28e5 | 1431 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1432 | return 0; |
1433 | ||
27a005b8 MC |
1434 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1435 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
1436 | ||
605a9e20 MC |
1437 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1438 | if (up1 & BCM5708S_UP1_2G5) { | |
1439 | up1 &= ~BCM5708S_UP1_2G5; | |
1440 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1441 | ret = 1; | |
1442 | } | |
1443 | ||
27a005b8 MC |
1444 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1445 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1446 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1447 | ||
605a9e20 MC |
1448 | return ret; |
1449 | } | |
1450 | ||
1451 | static void | |
1452 | bnx2_enable_forced_2g5(struct bnx2 *bp) | |
1453 | { | |
1454 | u32 bmcr; | |
1455 | ||
583c28e5 | 1456 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1457 | return; |
1458 | ||
27a005b8 MC |
1459 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
1460 | u32 val; | |
1461 | ||
1462 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1463 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
1464 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); | |
1465 | val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; | |
1466 | val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G; | |
1467 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1468 | ||
1469 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1470 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1471 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
1472 | ||
1473 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | |
605a9e20 MC |
1474 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1475 | bmcr |= BCM5708S_BMCR_FORCE_2500; | |
c7079857 ED |
1476 | } else { |
1477 | return; | |
605a9e20 MC |
1478 | } |
1479 | ||
1480 | if (bp->autoneg & AUTONEG_SPEED) { | |
1481 | bmcr &= ~BMCR_ANENABLE; | |
1482 | if (bp->req_duplex == DUPLEX_FULL) | |
1483 | bmcr |= BMCR_FULLDPLX; | |
1484 | } | |
1485 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1486 | } | |
1487 | ||
1488 | static void | |
1489 | bnx2_disable_forced_2g5(struct bnx2 *bp) | |
1490 | { | |
1491 | u32 bmcr; | |
1492 | ||
583c28e5 | 1493 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1494 | return; |
1495 | ||
27a005b8 MC |
1496 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
1497 | u32 val; | |
1498 | ||
1499 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1500 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
1501 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); | |
1502 | val &= ~MII_BNX2_SD_MISC1_FORCE; | |
1503 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1504 | ||
1505 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1506 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1507 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
1508 | ||
1509 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | |
605a9e20 MC |
1510 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1511 | bmcr &= ~BCM5708S_BMCR_FORCE_2500; | |
c7079857 ED |
1512 | } else { |
1513 | return; | |
605a9e20 MC |
1514 | } |
1515 | ||
1516 | if (bp->autoneg & AUTONEG_SPEED) | |
1517 | bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; | |
1518 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1519 | } | |
1520 | ||
b2fadeae MC |
1521 | static void |
1522 | bnx2_5706s_force_link_dn(struct bnx2 *bp, int start) | |
1523 | { | |
1524 | u32 val; | |
1525 | ||
1526 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); | |
1527 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
1528 | if (start) | |
1529 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); | |
1530 | else | |
1531 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); | |
1532 | } | |
1533 | ||
b6016b76 MC |
1534 | static int |
1535 | bnx2_set_link(struct bnx2 *bp) | |
1536 | { | |
1537 | u32 bmsr; | |
1538 | u8 link_up; | |
1539 | ||
80be4434 | 1540 | if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { |
b6016b76 MC |
1541 | bp->link_up = 1; |
1542 | return 0; | |
1543 | } | |
1544 | ||
583c28e5 | 1545 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
1546 | return 0; |
1547 | ||
b6016b76 MC |
1548 | link_up = bp->link_up; |
1549 | ||
27a005b8 MC |
1550 | bnx2_enable_bmsr1(bp); |
1551 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1552 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1553 | bnx2_disable_bmsr1(bp); | |
b6016b76 | 1554 | |
583c28e5 | 1555 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
b6016b76 | 1556 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { |
a2724e25 | 1557 | u32 val, an_dbg; |
b6016b76 | 1558 | |
583c28e5 | 1559 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { |
b2fadeae | 1560 | bnx2_5706s_force_link_dn(bp, 0); |
583c28e5 | 1561 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; |
b2fadeae | 1562 | } |
b6016b76 | 1563 | val = REG_RD(bp, BNX2_EMAC_STATUS); |
a2724e25 MC |
1564 | |
1565 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
1566 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
1567 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
1568 | ||
1569 | if ((val & BNX2_EMAC_STATUS_LINK) && | |
1570 | !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) | |
b6016b76 MC |
1571 | bmsr |= BMSR_LSTATUS; |
1572 | else | |
1573 | bmsr &= ~BMSR_LSTATUS; | |
1574 | } | |
1575 | ||
1576 | if (bmsr & BMSR_LSTATUS) { | |
1577 | bp->link_up = 1; | |
1578 | ||
583c28e5 | 1579 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
5b0c76ad MC |
1580 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
1581 | bnx2_5706s_linkup(bp); | |
1582 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) | |
1583 | bnx2_5708s_linkup(bp); | |
27a005b8 MC |
1584 | else if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1585 | bnx2_5709s_linkup(bp); | |
b6016b76 MC |
1586 | } |
1587 | else { | |
1588 | bnx2_copper_linkup(bp); | |
1589 | } | |
1590 | bnx2_resolve_flow_ctrl(bp); | |
1591 | } | |
1592 | else { | |
583c28e5 | 1593 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
605a9e20 MC |
1594 | (bp->autoneg & AUTONEG_SPEED)) |
1595 | bnx2_disable_forced_2g5(bp); | |
b6016b76 | 1596 | |
583c28e5 | 1597 | if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { |
b2fadeae MC |
1598 | u32 bmcr; |
1599 | ||
1600 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
1601 | bmcr |= BMCR_ANENABLE; | |
1602 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1603 | ||
583c28e5 | 1604 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
b2fadeae | 1605 | } |
b6016b76 MC |
1606 | bp->link_up = 0; |
1607 | } | |
1608 | ||
1609 | if (bp->link_up != link_up) { | |
1610 | bnx2_report_link(bp); | |
1611 | } | |
1612 | ||
1613 | bnx2_set_mac_link(bp); | |
1614 | ||
1615 | return 0; | |
1616 | } | |
1617 | ||
1618 | static int | |
1619 | bnx2_reset_phy(struct bnx2 *bp) | |
1620 | { | |
1621 | int i; | |
1622 | u32 reg; | |
1623 | ||
ca58c3af | 1624 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); |
b6016b76 MC |
1625 | |
1626 | #define PHY_RESET_MAX_WAIT 100 | |
1627 | for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { | |
1628 | udelay(10); | |
1629 | ||
ca58c3af | 1630 | bnx2_read_phy(bp, bp->mii_bmcr, ®); |
b6016b76 MC |
1631 | if (!(reg & BMCR_RESET)) { |
1632 | udelay(20); | |
1633 | break; | |
1634 | } | |
1635 | } | |
1636 | if (i == PHY_RESET_MAX_WAIT) { | |
1637 | return -EBUSY; | |
1638 | } | |
1639 | return 0; | |
1640 | } | |
1641 | ||
1642 | static u32 | |
1643 | bnx2_phy_get_pause_adv(struct bnx2 *bp) | |
1644 | { | |
1645 | u32 adv = 0; | |
1646 | ||
1647 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == | |
1648 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { | |
1649 | ||
583c28e5 | 1650 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1651 | adv = ADVERTISE_1000XPAUSE; |
1652 | } | |
1653 | else { | |
1654 | adv = ADVERTISE_PAUSE_CAP; | |
1655 | } | |
1656 | } | |
1657 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { | |
583c28e5 | 1658 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1659 | adv = ADVERTISE_1000XPSE_ASYM; |
1660 | } | |
1661 | else { | |
1662 | adv = ADVERTISE_PAUSE_ASYM; | |
1663 | } | |
1664 | } | |
1665 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { | |
583c28e5 | 1666 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1667 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1668 | } | |
1669 | else { | |
1670 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1671 | } | |
1672 | } | |
1673 | return adv; | |
1674 | } | |
1675 | ||
a2f13890 | 1676 | static int bnx2_fw_sync(struct bnx2 *, u32, int, int); |
0d8a6571 | 1677 | |
b6016b76 | 1678 | static int |
0d8a6571 | 1679 | bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) |
52d07b1f HH |
1680 | __releases(&bp->phy_lock) |
1681 | __acquires(&bp->phy_lock) | |
0d8a6571 MC |
1682 | { |
1683 | u32 speed_arg = 0, pause_adv; | |
1684 | ||
1685 | pause_adv = bnx2_phy_get_pause_adv(bp); | |
1686 | ||
1687 | if (bp->autoneg & AUTONEG_SPEED) { | |
1688 | speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; | |
1689 | if (bp->advertising & ADVERTISED_10baseT_Half) | |
1690 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1691 | if (bp->advertising & ADVERTISED_10baseT_Full) | |
1692 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1693 | if (bp->advertising & ADVERTISED_100baseT_Half) | |
1694 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1695 | if (bp->advertising & ADVERTISED_100baseT_Full) | |
1696 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1697 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
1698 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1699 | if (bp->advertising & ADVERTISED_2500baseX_Full) | |
1700 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1701 | } else { | |
1702 | if (bp->req_line_speed == SPEED_2500) | |
1703 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1704 | else if (bp->req_line_speed == SPEED_1000) | |
1705 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1706 | else if (bp->req_line_speed == SPEED_100) { | |
1707 | if (bp->req_duplex == DUPLEX_FULL) | |
1708 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1709 | else | |
1710 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1711 | } else if (bp->req_line_speed == SPEED_10) { | |
1712 | if (bp->req_duplex == DUPLEX_FULL) | |
1713 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1714 | else | |
1715 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) | |
1720 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; | |
c26736ec | 1721 | if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) |
0d8a6571 MC |
1722 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; |
1723 | ||
1724 | if (port == PORT_TP) | |
1725 | speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | | |
1726 | BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; | |
1727 | ||
2726d6e1 | 1728 | bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); |
0d8a6571 MC |
1729 | |
1730 | spin_unlock_bh(&bp->phy_lock); | |
a2f13890 | 1731 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); |
0d8a6571 MC |
1732 | spin_lock_bh(&bp->phy_lock); |
1733 | ||
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | static int | |
1738 | bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) | |
52d07b1f HH |
1739 | __releases(&bp->phy_lock) |
1740 | __acquires(&bp->phy_lock) | |
b6016b76 | 1741 | { |
605a9e20 | 1742 | u32 adv, bmcr; |
b6016b76 MC |
1743 | u32 new_adv = 0; |
1744 | ||
583c28e5 | 1745 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
1746 | return (bnx2_setup_remote_phy(bp, port)); |
1747 | ||
b6016b76 MC |
1748 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
1749 | u32 new_bmcr; | |
5b0c76ad MC |
1750 | int force_link_down = 0; |
1751 | ||
605a9e20 MC |
1752 | if (bp->req_line_speed == SPEED_2500) { |
1753 | if (!bnx2_test_and_enable_2g5(bp)) | |
1754 | force_link_down = 1; | |
1755 | } else if (bp->req_line_speed == SPEED_1000) { | |
1756 | if (bnx2_test_and_disable_2g5(bp)) | |
1757 | force_link_down = 1; | |
1758 | } | |
ca58c3af | 1759 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
80be4434 MC |
1760 | adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); |
1761 | ||
ca58c3af | 1762 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
605a9e20 | 1763 | new_bmcr = bmcr & ~BMCR_ANENABLE; |
80be4434 | 1764 | new_bmcr |= BMCR_SPEED1000; |
605a9e20 | 1765 | |
27a005b8 MC |
1766 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
1767 | if (bp->req_line_speed == SPEED_2500) | |
1768 | bnx2_enable_forced_2g5(bp); | |
1769 | else if (bp->req_line_speed == SPEED_1000) { | |
1770 | bnx2_disable_forced_2g5(bp); | |
1771 | new_bmcr &= ~0x2000; | |
1772 | } | |
1773 | ||
1774 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | |
605a9e20 MC |
1775 | if (bp->req_line_speed == SPEED_2500) |
1776 | new_bmcr |= BCM5708S_BMCR_FORCE_2500; | |
1777 | else | |
1778 | new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; | |
5b0c76ad MC |
1779 | } |
1780 | ||
b6016b76 | 1781 | if (bp->req_duplex == DUPLEX_FULL) { |
5b0c76ad | 1782 | adv |= ADVERTISE_1000XFULL; |
b6016b76 MC |
1783 | new_bmcr |= BMCR_FULLDPLX; |
1784 | } | |
1785 | else { | |
5b0c76ad | 1786 | adv |= ADVERTISE_1000XHALF; |
b6016b76 MC |
1787 | new_bmcr &= ~BMCR_FULLDPLX; |
1788 | } | |
5b0c76ad | 1789 | if ((new_bmcr != bmcr) || (force_link_down)) { |
b6016b76 MC |
1790 | /* Force a link down visible on the other side */ |
1791 | if (bp->link_up) { | |
ca58c3af | 1792 | bnx2_write_phy(bp, bp->mii_adv, adv & |
5b0c76ad MC |
1793 | ~(ADVERTISE_1000XFULL | |
1794 | ADVERTISE_1000XHALF)); | |
ca58c3af | 1795 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | |
b6016b76 MC |
1796 | BMCR_ANRESTART | BMCR_ANENABLE); |
1797 | ||
1798 | bp->link_up = 0; | |
1799 | netif_carrier_off(bp->dev); | |
ca58c3af | 1800 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
80be4434 | 1801 | bnx2_report_link(bp); |
b6016b76 | 1802 | } |
ca58c3af MC |
1803 | bnx2_write_phy(bp, bp->mii_adv, adv); |
1804 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); | |
605a9e20 MC |
1805 | } else { |
1806 | bnx2_resolve_flow_ctrl(bp); | |
1807 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1808 | } |
1809 | return 0; | |
1810 | } | |
1811 | ||
605a9e20 | 1812 | bnx2_test_and_enable_2g5(bp); |
5b0c76ad | 1813 | |
b6016b76 MC |
1814 | if (bp->advertising & ADVERTISED_1000baseT_Full) |
1815 | new_adv |= ADVERTISE_1000XFULL; | |
1816 | ||
1817 | new_adv |= bnx2_phy_get_pause_adv(bp); | |
1818 | ||
ca58c3af MC |
1819 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
1820 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
b6016b76 MC |
1821 | |
1822 | bp->serdes_an_pending = 0; | |
1823 | if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { | |
1824 | /* Force a link down visible on the other side */ | |
1825 | if (bp->link_up) { | |
ca58c3af | 1826 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
80be4434 MC |
1827 | spin_unlock_bh(&bp->phy_lock); |
1828 | msleep(20); | |
1829 | spin_lock_bh(&bp->phy_lock); | |
b6016b76 MC |
1830 | } |
1831 | ||
ca58c3af MC |
1832 | bnx2_write_phy(bp, bp->mii_adv, new_adv); |
1833 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | | |
b6016b76 | 1834 | BMCR_ANENABLE); |
f8dd064e MC |
1835 | /* Speed up link-up time when the link partner |
1836 | * does not autonegotiate which is very common | |
1837 | * in blade servers. Some blade servers use | |
1838 | * IPMI for kerboard input and it's important | |
1839 | * to minimize link disruptions. Autoneg. involves | |
1840 | * exchanging base pages plus 3 next pages and | |
1841 | * normally completes in about 120 msec. | |
1842 | */ | |
40105c0b | 1843 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
f8dd064e MC |
1844 | bp->serdes_an_pending = 1; |
1845 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
605a9e20 MC |
1846 | } else { |
1847 | bnx2_resolve_flow_ctrl(bp); | |
1848 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1849 | } |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
1854 | #define ETHTOOL_ALL_FIBRE_SPEED \ | |
583c28e5 | 1855 | (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ |
deaf391b MC |
1856 | (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ |
1857 | (ADVERTISED_1000baseT_Full) | |
b6016b76 MC |
1858 | |
1859 | #define ETHTOOL_ALL_COPPER_SPEED \ | |
1860 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ | |
1861 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ | |
1862 | ADVERTISED_1000baseT_Full) | |
1863 | ||
1864 | #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ | |
1865 | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) | |
6aa20a22 | 1866 | |
b6016b76 MC |
1867 | #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) |
1868 | ||
0d8a6571 MC |
1869 | static void |
1870 | bnx2_set_default_remote_link(struct bnx2 *bp) | |
1871 | { | |
1872 | u32 link; | |
1873 | ||
1874 | if (bp->phy_port == PORT_TP) | |
2726d6e1 | 1875 | link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); |
0d8a6571 | 1876 | else |
2726d6e1 | 1877 | link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); |
0d8a6571 MC |
1878 | |
1879 | if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { | |
1880 | bp->req_line_speed = 0; | |
1881 | bp->autoneg |= AUTONEG_SPEED; | |
1882 | bp->advertising = ADVERTISED_Autoneg; | |
1883 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1884 | bp->advertising |= ADVERTISED_10baseT_Half; | |
1885 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) | |
1886 | bp->advertising |= ADVERTISED_10baseT_Full; | |
1887 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1888 | bp->advertising |= ADVERTISED_100baseT_Half; | |
1889 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) | |
1890 | bp->advertising |= ADVERTISED_100baseT_Full; | |
1891 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1892 | bp->advertising |= ADVERTISED_1000baseT_Full; | |
1893 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1894 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1895 | } else { | |
1896 | bp->autoneg = 0; | |
1897 | bp->advertising = 0; | |
1898 | bp->req_duplex = DUPLEX_FULL; | |
1899 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { | |
1900 | bp->req_line_speed = SPEED_10; | |
1901 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1902 | bp->req_duplex = DUPLEX_HALF; | |
1903 | } | |
1904 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { | |
1905 | bp->req_line_speed = SPEED_100; | |
1906 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1907 | bp->req_duplex = DUPLEX_HALF; | |
1908 | } | |
1909 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1910 | bp->req_line_speed = SPEED_1000; | |
1911 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1912 | bp->req_line_speed = SPEED_2500; | |
1913 | } | |
1914 | } | |
1915 | ||
deaf391b MC |
1916 | static void |
1917 | bnx2_set_default_link(struct bnx2 *bp) | |
1918 | { | |
ab59859d HH |
1919 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
1920 | bnx2_set_default_remote_link(bp); | |
1921 | return; | |
1922 | } | |
0d8a6571 | 1923 | |
deaf391b MC |
1924 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; |
1925 | bp->req_line_speed = 0; | |
583c28e5 | 1926 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
deaf391b MC |
1927 | u32 reg; |
1928 | ||
1929 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | |
1930 | ||
2726d6e1 | 1931 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); |
deaf391b MC |
1932 | reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; |
1933 | if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { | |
1934 | bp->autoneg = 0; | |
1935 | bp->req_line_speed = bp->line_speed = SPEED_1000; | |
1936 | bp->req_duplex = DUPLEX_FULL; | |
1937 | } | |
1938 | } else | |
1939 | bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; | |
1940 | } | |
1941 | ||
df149d70 MC |
1942 | static void |
1943 | bnx2_send_heart_beat(struct bnx2 *bp) | |
1944 | { | |
1945 | u32 msg; | |
1946 | u32 addr; | |
1947 | ||
1948 | spin_lock(&bp->indirect_lock); | |
1949 | msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); | |
1950 | addr = bp->shmem_base + BNX2_DRV_PULSE_MB; | |
1951 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); | |
1952 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); | |
1953 | spin_unlock(&bp->indirect_lock); | |
1954 | } | |
1955 | ||
0d8a6571 MC |
1956 | static void |
1957 | bnx2_remote_phy_event(struct bnx2 *bp) | |
1958 | { | |
1959 | u32 msg; | |
1960 | u8 link_up = bp->link_up; | |
1961 | u8 old_port; | |
1962 | ||
2726d6e1 | 1963 | msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
0d8a6571 | 1964 | |
df149d70 MC |
1965 | if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) |
1966 | bnx2_send_heart_beat(bp); | |
1967 | ||
1968 | msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; | |
1969 | ||
0d8a6571 MC |
1970 | if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) |
1971 | bp->link_up = 0; | |
1972 | else { | |
1973 | u32 speed; | |
1974 | ||
1975 | bp->link_up = 1; | |
1976 | speed = msg & BNX2_LINK_STATUS_SPEED_MASK; | |
1977 | bp->duplex = DUPLEX_FULL; | |
1978 | switch (speed) { | |
1979 | case BNX2_LINK_STATUS_10HALF: | |
1980 | bp->duplex = DUPLEX_HALF; | |
1981 | case BNX2_LINK_STATUS_10FULL: | |
1982 | bp->line_speed = SPEED_10; | |
1983 | break; | |
1984 | case BNX2_LINK_STATUS_100HALF: | |
1985 | bp->duplex = DUPLEX_HALF; | |
1986 | case BNX2_LINK_STATUS_100BASE_T4: | |
1987 | case BNX2_LINK_STATUS_100FULL: | |
1988 | bp->line_speed = SPEED_100; | |
1989 | break; | |
1990 | case BNX2_LINK_STATUS_1000HALF: | |
1991 | bp->duplex = DUPLEX_HALF; | |
1992 | case BNX2_LINK_STATUS_1000FULL: | |
1993 | bp->line_speed = SPEED_1000; | |
1994 | break; | |
1995 | case BNX2_LINK_STATUS_2500HALF: | |
1996 | bp->duplex = DUPLEX_HALF; | |
1997 | case BNX2_LINK_STATUS_2500FULL: | |
1998 | bp->line_speed = SPEED_2500; | |
1999 | break; | |
2000 | default: | |
2001 | bp->line_speed = 0; | |
2002 | break; | |
2003 | } | |
2004 | ||
0d8a6571 MC |
2005 | bp->flow_ctrl = 0; |
2006 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != | |
2007 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { | |
2008 | if (bp->duplex == DUPLEX_FULL) | |
2009 | bp->flow_ctrl = bp->req_flow_ctrl; | |
2010 | } else { | |
2011 | if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED) | |
2012 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
2013 | if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED) | |
2014 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
2015 | } | |
2016 | ||
2017 | old_port = bp->phy_port; | |
2018 | if (msg & BNX2_LINK_STATUS_SERDES_LINK) | |
2019 | bp->phy_port = PORT_FIBRE; | |
2020 | else | |
2021 | bp->phy_port = PORT_TP; | |
2022 | ||
2023 | if (old_port != bp->phy_port) | |
2024 | bnx2_set_default_link(bp); | |
2025 | ||
0d8a6571 MC |
2026 | } |
2027 | if (bp->link_up != link_up) | |
2028 | bnx2_report_link(bp); | |
2029 | ||
2030 | bnx2_set_mac_link(bp); | |
2031 | } | |
2032 | ||
2033 | static int | |
2034 | bnx2_set_remote_link(struct bnx2 *bp) | |
2035 | { | |
2036 | u32 evt_code; | |
2037 | ||
2726d6e1 | 2038 | evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); |
0d8a6571 MC |
2039 | switch (evt_code) { |
2040 | case BNX2_FW_EVT_CODE_LINK_EVENT: | |
2041 | bnx2_remote_phy_event(bp); | |
2042 | break; | |
2043 | case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: | |
2044 | default: | |
df149d70 | 2045 | bnx2_send_heart_beat(bp); |
0d8a6571 MC |
2046 | break; |
2047 | } | |
2048 | return 0; | |
2049 | } | |
2050 | ||
b6016b76 MC |
2051 | static int |
2052 | bnx2_setup_copper_phy(struct bnx2 *bp) | |
52d07b1f HH |
2053 | __releases(&bp->phy_lock) |
2054 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2055 | { |
2056 | u32 bmcr; | |
2057 | u32 new_bmcr; | |
2058 | ||
ca58c3af | 2059 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
2060 | |
2061 | if (bp->autoneg & AUTONEG_SPEED) { | |
2062 | u32 adv_reg, adv1000_reg; | |
2063 | u32 new_adv_reg = 0; | |
2064 | u32 new_adv1000_reg = 0; | |
2065 | ||
ca58c3af | 2066 | bnx2_read_phy(bp, bp->mii_adv, &adv_reg); |
b6016b76 MC |
2067 | adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | |
2068 | ADVERTISE_PAUSE_ASYM); | |
2069 | ||
2070 | bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); | |
2071 | adv1000_reg &= PHY_ALL_1000_SPEED; | |
2072 | ||
2073 | if (bp->advertising & ADVERTISED_10baseT_Half) | |
2074 | new_adv_reg |= ADVERTISE_10HALF; | |
2075 | if (bp->advertising & ADVERTISED_10baseT_Full) | |
2076 | new_adv_reg |= ADVERTISE_10FULL; | |
2077 | if (bp->advertising & ADVERTISED_100baseT_Half) | |
2078 | new_adv_reg |= ADVERTISE_100HALF; | |
2079 | if (bp->advertising & ADVERTISED_100baseT_Full) | |
2080 | new_adv_reg |= ADVERTISE_100FULL; | |
2081 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
2082 | new_adv1000_reg |= ADVERTISE_1000FULL; | |
6aa20a22 | 2083 | |
b6016b76 MC |
2084 | new_adv_reg |= ADVERTISE_CSMA; |
2085 | ||
2086 | new_adv_reg |= bnx2_phy_get_pause_adv(bp); | |
2087 | ||
2088 | if ((adv1000_reg != new_adv1000_reg) || | |
2089 | (adv_reg != new_adv_reg) || | |
2090 | ((bmcr & BMCR_ANENABLE) == 0)) { | |
2091 | ||
ca58c3af | 2092 | bnx2_write_phy(bp, bp->mii_adv, new_adv_reg); |
b6016b76 | 2093 | bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg); |
ca58c3af | 2094 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | |
b6016b76 MC |
2095 | BMCR_ANENABLE); |
2096 | } | |
2097 | else if (bp->link_up) { | |
2098 | /* Flow ctrl may have changed from auto to forced */ | |
2099 | /* or vice-versa. */ | |
2100 | ||
2101 | bnx2_resolve_flow_ctrl(bp); | |
2102 | bnx2_set_mac_link(bp); | |
2103 | } | |
2104 | return 0; | |
2105 | } | |
2106 | ||
2107 | new_bmcr = 0; | |
2108 | if (bp->req_line_speed == SPEED_100) { | |
2109 | new_bmcr |= BMCR_SPEED100; | |
2110 | } | |
2111 | if (bp->req_duplex == DUPLEX_FULL) { | |
2112 | new_bmcr |= BMCR_FULLDPLX; | |
2113 | } | |
2114 | if (new_bmcr != bmcr) { | |
2115 | u32 bmsr; | |
b6016b76 | 2116 | |
ca58c3af MC |
2117 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
2118 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
6aa20a22 | 2119 | |
b6016b76 MC |
2120 | if (bmsr & BMSR_LSTATUS) { |
2121 | /* Force link down */ | |
ca58c3af | 2122 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
a16dda0e MC |
2123 | spin_unlock_bh(&bp->phy_lock); |
2124 | msleep(50); | |
2125 | spin_lock_bh(&bp->phy_lock); | |
2126 | ||
ca58c3af MC |
2127 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
2128 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
b6016b76 MC |
2129 | } |
2130 | ||
ca58c3af | 2131 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
b6016b76 MC |
2132 | |
2133 | /* Normally, the new speed is setup after the link has | |
2134 | * gone down and up again. In some cases, link will not go | |
2135 | * down so we need to set up the new speed here. | |
2136 | */ | |
2137 | if (bmsr & BMSR_LSTATUS) { | |
2138 | bp->line_speed = bp->req_line_speed; | |
2139 | bp->duplex = bp->req_duplex; | |
2140 | bnx2_resolve_flow_ctrl(bp); | |
2141 | bnx2_set_mac_link(bp); | |
2142 | } | |
27a005b8 MC |
2143 | } else { |
2144 | bnx2_resolve_flow_ctrl(bp); | |
2145 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
2146 | } |
2147 | return 0; | |
2148 | } | |
2149 | ||
2150 | static int | |
0d8a6571 | 2151 | bnx2_setup_phy(struct bnx2 *bp, u8 port) |
52d07b1f HH |
2152 | __releases(&bp->phy_lock) |
2153 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2154 | { |
2155 | if (bp->loopback == MAC_LOOPBACK) | |
2156 | return 0; | |
2157 | ||
583c28e5 | 2158 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
0d8a6571 | 2159 | return (bnx2_setup_serdes_phy(bp, port)); |
b6016b76 MC |
2160 | } |
2161 | else { | |
2162 | return (bnx2_setup_copper_phy(bp)); | |
2163 | } | |
2164 | } | |
2165 | ||
27a005b8 | 2166 | static int |
9a120bc5 | 2167 | bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy) |
27a005b8 MC |
2168 | { |
2169 | u32 val; | |
2170 | ||
2171 | bp->mii_bmcr = MII_BMCR + 0x10; | |
2172 | bp->mii_bmsr = MII_BMSR + 0x10; | |
2173 | bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; | |
2174 | bp->mii_adv = MII_ADVERTISE + 0x10; | |
2175 | bp->mii_lpa = MII_LPA + 0x10; | |
2176 | bp->mii_up1 = MII_BNX2_OVER1G_UP1; | |
2177 | ||
2178 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); | |
2179 | bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); | |
2180 | ||
2181 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
9a120bc5 MC |
2182 | if (reset_phy) |
2183 | bnx2_reset_phy(bp); | |
27a005b8 MC |
2184 | |
2185 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); | |
2186 | ||
2187 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); | |
2188 | val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; | |
2189 | val |= MII_BNX2_SD_1000XCTL1_FIBER; | |
2190 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); | |
2191 | ||
2192 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
2193 | bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); | |
583c28e5 | 2194 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
27a005b8 MC |
2195 | val |= BCM5708S_UP1_2G5; |
2196 | else | |
2197 | val &= ~BCM5708S_UP1_2G5; | |
2198 | bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); | |
2199 | ||
2200 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); | |
2201 | bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); | |
2202 | val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; | |
2203 | bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); | |
2204 | ||
2205 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); | |
2206 | ||
2207 | val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | | |
2208 | MII_BNX2_CL73_BAM_NP_AFT_BP_EN; | |
2209 | bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); | |
2210 | ||
2211 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
2212 | ||
2213 | return 0; | |
2214 | } | |
2215 | ||
b6016b76 | 2216 | static int |
9a120bc5 | 2217 | bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) |
5b0c76ad MC |
2218 | { |
2219 | u32 val; | |
2220 | ||
9a120bc5 MC |
2221 | if (reset_phy) |
2222 | bnx2_reset_phy(bp); | |
27a005b8 MC |
2223 | |
2224 | bp->mii_up1 = BCM5708S_UP1; | |
2225 | ||
5b0c76ad MC |
2226 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); |
2227 | bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); | |
2228 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
2229 | ||
2230 | bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); | |
2231 | val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; | |
2232 | bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); | |
2233 | ||
2234 | bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); | |
2235 | val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; | |
2236 | bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); | |
2237 | ||
583c28e5 | 2238 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { |
5b0c76ad MC |
2239 | bnx2_read_phy(bp, BCM5708S_UP1, &val); |
2240 | val |= BCM5708S_UP1_2G5; | |
2241 | bnx2_write_phy(bp, BCM5708S_UP1, val); | |
2242 | } | |
2243 | ||
2244 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || | |
dda1e390 MC |
2245 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || |
2246 | (CHIP_ID(bp) == CHIP_ID_5708_B1)) { | |
5b0c76ad MC |
2247 | /* increase tx signal amplitude */ |
2248 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2249 | BCM5708S_BLK_ADDR_TX_MISC); | |
2250 | bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); | |
2251 | val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; | |
2252 | bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); | |
2253 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
2254 | } | |
2255 | ||
2726d6e1 | 2256 | val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & |
5b0c76ad MC |
2257 | BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; |
2258 | ||
2259 | if (val) { | |
2260 | u32 is_backplane; | |
2261 | ||
2726d6e1 | 2262 | is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
5b0c76ad MC |
2263 | if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { |
2264 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2265 | BCM5708S_BLK_ADDR_TX_MISC); | |
2266 | bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); | |
2267 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2268 | BCM5708S_BLK_ADDR_DIG); | |
2269 | } | |
2270 | } | |
2271 | return 0; | |
2272 | } | |
2273 | ||
2274 | static int | |
9a120bc5 | 2275 | bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) |
b6016b76 | 2276 | { |
9a120bc5 MC |
2277 | if (reset_phy) |
2278 | bnx2_reset_phy(bp); | |
27a005b8 | 2279 | |
583c28e5 | 2280 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
b6016b76 | 2281 | |
59b47d8a MC |
2282 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
2283 | REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); | |
b6016b76 MC |
2284 | |
2285 | if (bp->dev->mtu > 1500) { | |
2286 | u32 val; | |
2287 | ||
2288 | /* Set extended packet length bit */ | |
2289 | bnx2_write_phy(bp, 0x18, 0x7); | |
2290 | bnx2_read_phy(bp, 0x18, &val); | |
2291 | bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); | |
2292 | ||
2293 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
2294 | bnx2_read_phy(bp, 0x1c, &val); | |
2295 | bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); | |
2296 | } | |
2297 | else { | |
2298 | u32 val; | |
2299 | ||
2300 | bnx2_write_phy(bp, 0x18, 0x7); | |
2301 | bnx2_read_phy(bp, 0x18, &val); | |
2302 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
2303 | ||
2304 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
2305 | bnx2_read_phy(bp, 0x1c, &val); | |
2306 | bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); | |
2307 | } | |
2308 | ||
2309 | return 0; | |
2310 | } | |
2311 | ||
2312 | static int | |
9a120bc5 | 2313 | bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) |
b6016b76 | 2314 | { |
5b0c76ad MC |
2315 | u32 val; |
2316 | ||
9a120bc5 MC |
2317 | if (reset_phy) |
2318 | bnx2_reset_phy(bp); | |
27a005b8 | 2319 | |
583c28e5 | 2320 | if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { |
b6016b76 MC |
2321 | bnx2_write_phy(bp, 0x18, 0x0c00); |
2322 | bnx2_write_phy(bp, 0x17, 0x000a); | |
2323 | bnx2_write_phy(bp, 0x15, 0x310b); | |
2324 | bnx2_write_phy(bp, 0x17, 0x201f); | |
2325 | bnx2_write_phy(bp, 0x15, 0x9506); | |
2326 | bnx2_write_phy(bp, 0x17, 0x401f); | |
2327 | bnx2_write_phy(bp, 0x15, 0x14e2); | |
2328 | bnx2_write_phy(bp, 0x18, 0x0400); | |
2329 | } | |
2330 | ||
583c28e5 | 2331 | if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { |
b659f44e MC |
2332 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, |
2333 | MII_BNX2_DSP_EXPAND_REG | 0x8); | |
2334 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
2335 | val &= ~(1 << 8); | |
2336 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); | |
2337 | } | |
2338 | ||
b6016b76 | 2339 | if (bp->dev->mtu > 1500) { |
b6016b76 MC |
2340 | /* Set extended packet length bit */ |
2341 | bnx2_write_phy(bp, 0x18, 0x7); | |
2342 | bnx2_read_phy(bp, 0x18, &val); | |
2343 | bnx2_write_phy(bp, 0x18, val | 0x4000); | |
2344 | ||
2345 | bnx2_read_phy(bp, 0x10, &val); | |
2346 | bnx2_write_phy(bp, 0x10, val | 0x1); | |
2347 | } | |
2348 | else { | |
b6016b76 MC |
2349 | bnx2_write_phy(bp, 0x18, 0x7); |
2350 | bnx2_read_phy(bp, 0x18, &val); | |
2351 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
2352 | ||
2353 | bnx2_read_phy(bp, 0x10, &val); | |
2354 | bnx2_write_phy(bp, 0x10, val & ~0x1); | |
2355 | } | |
2356 | ||
5b0c76ad MC |
2357 | /* ethernet@wirespeed */ |
2358 | bnx2_write_phy(bp, 0x18, 0x7007); | |
2359 | bnx2_read_phy(bp, 0x18, &val); | |
2360 | bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4)); | |
b6016b76 MC |
2361 | return 0; |
2362 | } | |
2363 | ||
2364 | ||
2365 | static int | |
9a120bc5 | 2366 | bnx2_init_phy(struct bnx2 *bp, int reset_phy) |
52d07b1f HH |
2367 | __releases(&bp->phy_lock) |
2368 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2369 | { |
2370 | u32 val; | |
2371 | int rc = 0; | |
2372 | ||
583c28e5 MC |
2373 | bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; |
2374 | bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; | |
b6016b76 | 2375 | |
ca58c3af MC |
2376 | bp->mii_bmcr = MII_BMCR; |
2377 | bp->mii_bmsr = MII_BMSR; | |
27a005b8 | 2378 | bp->mii_bmsr1 = MII_BMSR; |
ca58c3af MC |
2379 | bp->mii_adv = MII_ADVERTISE; |
2380 | bp->mii_lpa = MII_LPA; | |
2381 | ||
b6016b76 MC |
2382 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); |
2383 | ||
583c28e5 | 2384 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
2385 | goto setup_phy; |
2386 | ||
b6016b76 MC |
2387 | bnx2_read_phy(bp, MII_PHYSID1, &val); |
2388 | bp->phy_id = val << 16; | |
2389 | bnx2_read_phy(bp, MII_PHYSID2, &val); | |
2390 | bp->phy_id |= val & 0xffff; | |
2391 | ||
583c28e5 | 2392 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
5b0c76ad | 2393 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
9a120bc5 | 2394 | rc = bnx2_init_5706s_phy(bp, reset_phy); |
5b0c76ad | 2395 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) |
9a120bc5 | 2396 | rc = bnx2_init_5708s_phy(bp, reset_phy); |
27a005b8 | 2397 | else if (CHIP_NUM(bp) == CHIP_NUM_5709) |
9a120bc5 | 2398 | rc = bnx2_init_5709s_phy(bp, reset_phy); |
b6016b76 MC |
2399 | } |
2400 | else { | |
9a120bc5 | 2401 | rc = bnx2_init_copper_phy(bp, reset_phy); |
b6016b76 MC |
2402 | } |
2403 | ||
0d8a6571 MC |
2404 | setup_phy: |
2405 | if (!rc) | |
2406 | rc = bnx2_setup_phy(bp, bp->phy_port); | |
b6016b76 MC |
2407 | |
2408 | return rc; | |
2409 | } | |
2410 | ||
2411 | static int | |
2412 | bnx2_set_mac_loopback(struct bnx2 *bp) | |
2413 | { | |
2414 | u32 mac_mode; | |
2415 | ||
2416 | mac_mode = REG_RD(bp, BNX2_EMAC_MODE); | |
2417 | mac_mode &= ~BNX2_EMAC_MODE_PORT; | |
2418 | mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; | |
2419 | REG_WR(bp, BNX2_EMAC_MODE, mac_mode); | |
2420 | bp->link_up = 1; | |
2421 | return 0; | |
2422 | } | |
2423 | ||
bc5a0690 MC |
2424 | static int bnx2_test_link(struct bnx2 *); |
2425 | ||
2426 | static int | |
2427 | bnx2_set_phy_loopback(struct bnx2 *bp) | |
2428 | { | |
2429 | u32 mac_mode; | |
2430 | int rc, i; | |
2431 | ||
2432 | spin_lock_bh(&bp->phy_lock); | |
ca58c3af | 2433 | rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | |
bc5a0690 MC |
2434 | BMCR_SPEED1000); |
2435 | spin_unlock_bh(&bp->phy_lock); | |
2436 | if (rc) | |
2437 | return rc; | |
2438 | ||
2439 | for (i = 0; i < 10; i++) { | |
2440 | if (bnx2_test_link(bp) == 0) | |
2441 | break; | |
80be4434 | 2442 | msleep(100); |
bc5a0690 MC |
2443 | } |
2444 | ||
2445 | mac_mode = REG_RD(bp, BNX2_EMAC_MODE); | |
2446 | mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | |
2447 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | | |
59b47d8a | 2448 | BNX2_EMAC_MODE_25G_MODE); |
bc5a0690 MC |
2449 | |
2450 | mac_mode |= BNX2_EMAC_MODE_PORT_GMII; | |
2451 | REG_WR(bp, BNX2_EMAC_MODE, mac_mode); | |
2452 | bp->link_up = 1; | |
2453 | return 0; | |
2454 | } | |
2455 | ||
b6016b76 | 2456 | static int |
a2f13890 | 2457 | bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent) |
b6016b76 MC |
2458 | { |
2459 | int i; | |
2460 | u32 val; | |
2461 | ||
b6016b76 MC |
2462 | bp->fw_wr_seq++; |
2463 | msg_data |= bp->fw_wr_seq; | |
2464 | ||
2726d6e1 | 2465 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
b6016b76 | 2466 | |
a2f13890 MC |
2467 | if (!ack) |
2468 | return 0; | |
2469 | ||
b6016b76 | 2470 | /* wait for an acknowledgement. */ |
40105c0b | 2471 | for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { |
b090ae2b | 2472 | msleep(10); |
b6016b76 | 2473 | |
2726d6e1 | 2474 | val = bnx2_shmem_rd(bp, BNX2_FW_MB); |
b6016b76 MC |
2475 | |
2476 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) | |
2477 | break; | |
2478 | } | |
b090ae2b MC |
2479 | if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) |
2480 | return 0; | |
b6016b76 MC |
2481 | |
2482 | /* If we timed out, inform the firmware that this is the case. */ | |
b090ae2b MC |
2483 | if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { |
2484 | if (!silent) | |
2485 | printk(KERN_ERR PFX "fw sync timeout, reset code = " | |
2486 | "%x\n", msg_data); | |
b6016b76 MC |
2487 | |
2488 | msg_data &= ~BNX2_DRV_MSG_CODE; | |
2489 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; | |
2490 | ||
2726d6e1 | 2491 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
b6016b76 | 2492 | |
b6016b76 MC |
2493 | return -EBUSY; |
2494 | } | |
2495 | ||
b090ae2b MC |
2496 | if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) |
2497 | return -EIO; | |
2498 | ||
b6016b76 MC |
2499 | return 0; |
2500 | } | |
2501 | ||
59b47d8a MC |
2502 | static int |
2503 | bnx2_init_5709_context(struct bnx2 *bp) | |
2504 | { | |
2505 | int i, ret = 0; | |
2506 | u32 val; | |
2507 | ||
2508 | val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); | |
2509 | val |= (BCM_PAGE_BITS - 8) << 16; | |
2510 | REG_WR(bp, BNX2_CTX_COMMAND, val); | |
641bdcd5 MC |
2511 | for (i = 0; i < 10; i++) { |
2512 | val = REG_RD(bp, BNX2_CTX_COMMAND); | |
2513 | if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) | |
2514 | break; | |
2515 | udelay(2); | |
2516 | } | |
2517 | if (val & BNX2_CTX_COMMAND_MEM_INIT) | |
2518 | return -EBUSY; | |
2519 | ||
59b47d8a MC |
2520 | for (i = 0; i < bp->ctx_pages; i++) { |
2521 | int j; | |
2522 | ||
352f7687 MC |
2523 | if (bp->ctx_blk[i]) |
2524 | memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE); | |
2525 | else | |
2526 | return -ENOMEM; | |
2527 | ||
59b47d8a MC |
2528 | REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, |
2529 | (bp->ctx_blk_mapping[i] & 0xffffffff) | | |
2530 | BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); | |
2531 | REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, | |
2532 | (u64) bp->ctx_blk_mapping[i] >> 32); | |
2533 | REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | | |
2534 | BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); | |
2535 | for (j = 0; j < 10; j++) { | |
2536 | ||
2537 | val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); | |
2538 | if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) | |
2539 | break; | |
2540 | udelay(5); | |
2541 | } | |
2542 | if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { | |
2543 | ret = -EBUSY; | |
2544 | break; | |
2545 | } | |
2546 | } | |
2547 | return ret; | |
2548 | } | |
2549 | ||
b6016b76 MC |
2550 | static void |
2551 | bnx2_init_context(struct bnx2 *bp) | |
2552 | { | |
2553 | u32 vcid; | |
2554 | ||
2555 | vcid = 96; | |
2556 | while (vcid) { | |
2557 | u32 vcid_addr, pcid_addr, offset; | |
7947b20e | 2558 | int i; |
b6016b76 MC |
2559 | |
2560 | vcid--; | |
2561 | ||
2562 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
2563 | u32 new_vcid; | |
2564 | ||
2565 | vcid_addr = GET_PCID_ADDR(vcid); | |
2566 | if (vcid & 0x8) { | |
2567 | new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); | |
2568 | } | |
2569 | else { | |
2570 | new_vcid = vcid; | |
2571 | } | |
2572 | pcid_addr = GET_PCID_ADDR(new_vcid); | |
2573 | } | |
2574 | else { | |
2575 | vcid_addr = GET_CID_ADDR(vcid); | |
2576 | pcid_addr = vcid_addr; | |
2577 | } | |
2578 | ||
7947b20e MC |
2579 | for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { |
2580 | vcid_addr += (i << PHY_CTX_SHIFT); | |
2581 | pcid_addr += (i << PHY_CTX_SHIFT); | |
b6016b76 | 2582 | |
5d5d0015 | 2583 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); |
7947b20e | 2584 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); |
b6016b76 | 2585 | |
7947b20e MC |
2586 | /* Zero out the context. */ |
2587 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) | |
62a8313c | 2588 | bnx2_ctx_wr(bp, vcid_addr, offset, 0); |
7947b20e | 2589 | } |
b6016b76 MC |
2590 | } |
2591 | } | |
2592 | ||
2593 | static int | |
2594 | bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |
2595 | { | |
2596 | u16 *good_mbuf; | |
2597 | u32 good_mbuf_cnt; | |
2598 | u32 val; | |
2599 | ||
2600 | good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); | |
2601 | if (good_mbuf == NULL) { | |
2602 | printk(KERN_ERR PFX "Failed to allocate memory in " | |
2603 | "bnx2_alloc_bad_rbuf\n"); | |
2604 | return -ENOMEM; | |
2605 | } | |
2606 | ||
2607 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
2608 | BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); | |
2609 | ||
2610 | good_mbuf_cnt = 0; | |
2611 | ||
2612 | /* Allocate a bunch of mbufs and save the good ones in an array. */ | |
2726d6e1 | 2613 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
b6016b76 | 2614 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { |
2726d6e1 MC |
2615 | bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, |
2616 | BNX2_RBUF_COMMAND_ALLOC_REQ); | |
b6016b76 | 2617 | |
2726d6e1 | 2618 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); |
b6016b76 MC |
2619 | |
2620 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; | |
2621 | ||
2622 | /* The addresses with Bit 9 set are bad memory blocks. */ | |
2623 | if (!(val & (1 << 9))) { | |
2624 | good_mbuf[good_mbuf_cnt] = (u16) val; | |
2625 | good_mbuf_cnt++; | |
2626 | } | |
2627 | ||
2726d6e1 | 2628 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
b6016b76 MC |
2629 | } |
2630 | ||
2631 | /* Free the good ones back to the mbuf pool thus discarding | |
2632 | * all the bad ones. */ | |
2633 | while (good_mbuf_cnt) { | |
2634 | good_mbuf_cnt--; | |
2635 | ||
2636 | val = good_mbuf[good_mbuf_cnt]; | |
2637 | val = (val << 9) | val | 1; | |
2638 | ||
2726d6e1 | 2639 | bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); |
b6016b76 MC |
2640 | } |
2641 | kfree(good_mbuf); | |
2642 | return 0; | |
2643 | } | |
2644 | ||
2645 | static void | |
5fcaed01 | 2646 | bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos) |
b6016b76 MC |
2647 | { |
2648 | u32 val; | |
b6016b76 MC |
2649 | |
2650 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
2651 | ||
5fcaed01 | 2652 | REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); |
b6016b76 | 2653 | |
6aa20a22 | 2654 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | |
b6016b76 MC |
2655 | (mac_addr[4] << 8) | mac_addr[5]; |
2656 | ||
5fcaed01 | 2657 | REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); |
b6016b76 MC |
2658 | } |
2659 | ||
47bf4246 | 2660 | static inline int |
bb4f98ab | 2661 | bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) |
47bf4246 MC |
2662 | { |
2663 | dma_addr_t mapping; | |
bb4f98ab | 2664 | struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; |
47bf4246 | 2665 | struct rx_bd *rxbd = |
bb4f98ab | 2666 | &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; |
47bf4246 MC |
2667 | struct page *page = alloc_page(GFP_ATOMIC); |
2668 | ||
2669 | if (!page) | |
2670 | return -ENOMEM; | |
2671 | mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE, | |
2672 | PCI_DMA_FROMDEVICE); | |
3d16af86 BL |
2673 | if (pci_dma_mapping_error(bp->pdev, mapping)) { |
2674 | __free_page(page); | |
2675 | return -EIO; | |
2676 | } | |
2677 | ||
47bf4246 MC |
2678 | rx_pg->page = page; |
2679 | pci_unmap_addr_set(rx_pg, mapping, mapping); | |
2680 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | |
2681 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2682 | return 0; | |
2683 | } | |
2684 | ||
2685 | static void | |
bb4f98ab | 2686 | bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) |
47bf4246 | 2687 | { |
bb4f98ab | 2688 | struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; |
47bf4246 MC |
2689 | struct page *page = rx_pg->page; |
2690 | ||
2691 | if (!page) | |
2692 | return; | |
2693 | ||
2694 | pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE, | |
2695 | PCI_DMA_FROMDEVICE); | |
2696 | ||
2697 | __free_page(page); | |
2698 | rx_pg->page = NULL; | |
2699 | } | |
2700 | ||
b6016b76 | 2701 | static inline int |
bb4f98ab | 2702 | bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) |
b6016b76 MC |
2703 | { |
2704 | struct sk_buff *skb; | |
bb4f98ab | 2705 | struct sw_bd *rx_buf = &rxr->rx_buf_ring[index]; |
b6016b76 | 2706 | dma_addr_t mapping; |
bb4f98ab | 2707 | struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; |
b6016b76 MC |
2708 | unsigned long align; |
2709 | ||
932f3772 | 2710 | skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); |
b6016b76 MC |
2711 | if (skb == NULL) { |
2712 | return -ENOMEM; | |
2713 | } | |
2714 | ||
59b47d8a MC |
2715 | if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1)))) |
2716 | skb_reserve(skb, BNX2_RX_ALIGN - align); | |
b6016b76 | 2717 | |
b6016b76 MC |
2718 | mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, |
2719 | PCI_DMA_FROMDEVICE); | |
3d16af86 BL |
2720 | if (pci_dma_mapping_error(bp->pdev, mapping)) { |
2721 | dev_kfree_skb(skb); | |
2722 | return -EIO; | |
2723 | } | |
b6016b76 MC |
2724 | |
2725 | rx_buf->skb = skb; | |
2726 | pci_unmap_addr_set(rx_buf, mapping, mapping); | |
2727 | ||
2728 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | |
2729 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2730 | ||
bb4f98ab | 2731 | rxr->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 MC |
2732 | |
2733 | return 0; | |
2734 | } | |
2735 | ||
da3e4fbe | 2736 | static int |
35efa7c1 | 2737 | bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) |
b6016b76 | 2738 | { |
43e80b89 | 2739 | struct status_block *sblk = bnapi->status_blk.msi; |
b6016b76 | 2740 | u32 new_link_state, old_link_state; |
da3e4fbe | 2741 | int is_set = 1; |
b6016b76 | 2742 | |
da3e4fbe MC |
2743 | new_link_state = sblk->status_attn_bits & event; |
2744 | old_link_state = sblk->status_attn_bits_ack & event; | |
b6016b76 | 2745 | if (new_link_state != old_link_state) { |
da3e4fbe MC |
2746 | if (new_link_state) |
2747 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); | |
2748 | else | |
2749 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); | |
2750 | } else | |
2751 | is_set = 0; | |
2752 | ||
2753 | return is_set; | |
2754 | } | |
2755 | ||
2756 | static void | |
35efa7c1 | 2757 | bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi) |
da3e4fbe | 2758 | { |
74ecc62d MC |
2759 | spin_lock(&bp->phy_lock); |
2760 | ||
2761 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) | |
b6016b76 | 2762 | bnx2_set_link(bp); |
35efa7c1 | 2763 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT)) |
0d8a6571 MC |
2764 | bnx2_set_remote_link(bp); |
2765 | ||
74ecc62d MC |
2766 | spin_unlock(&bp->phy_lock); |
2767 | ||
b6016b76 MC |
2768 | } |
2769 | ||
ead7270b | 2770 | static inline u16 |
35efa7c1 | 2771 | bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) |
ead7270b MC |
2772 | { |
2773 | u16 cons; | |
2774 | ||
43e80b89 MC |
2775 | /* Tell compiler that status block fields can change. */ |
2776 | barrier(); | |
2777 | cons = *bnapi->hw_tx_cons_ptr; | |
581daf7e | 2778 | barrier(); |
ead7270b MC |
2779 | if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) |
2780 | cons++; | |
2781 | return cons; | |
2782 | } | |
2783 | ||
57851d84 MC |
2784 | static int |
2785 | bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) | |
b6016b76 | 2786 | { |
35e9010b | 2787 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
b6016b76 | 2788 | u16 hw_cons, sw_cons, sw_ring_cons; |
706bf240 BL |
2789 | int tx_pkt = 0, index; |
2790 | struct netdev_queue *txq; | |
2791 | ||
2792 | index = (bnapi - bp->bnx2_napi); | |
2793 | txq = netdev_get_tx_queue(bp->dev, index); | |
b6016b76 | 2794 | |
35efa7c1 | 2795 | hw_cons = bnx2_get_hw_tx_cons(bnapi); |
35e9010b | 2796 | sw_cons = txr->tx_cons; |
b6016b76 MC |
2797 | |
2798 | while (sw_cons != hw_cons) { | |
3d16af86 | 2799 | struct sw_tx_bd *tx_buf; |
b6016b76 MC |
2800 | struct sk_buff *skb; |
2801 | int i, last; | |
2802 | ||
2803 | sw_ring_cons = TX_RING_IDX(sw_cons); | |
2804 | ||
35e9010b | 2805 | tx_buf = &txr->tx_buf_ring[sw_ring_cons]; |
b6016b76 | 2806 | skb = tx_buf->skb; |
1d39ed56 | 2807 | |
d62fda08 ED |
2808 | /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ |
2809 | prefetch(&skb->end); | |
2810 | ||
b6016b76 | 2811 | /* partial BD completions possible with TSO packets */ |
d62fda08 | 2812 | if (tx_buf->is_gso) { |
b6016b76 MC |
2813 | u16 last_idx, last_ring_idx; |
2814 | ||
d62fda08 ED |
2815 | last_idx = sw_cons + tx_buf->nr_frags + 1; |
2816 | last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; | |
b6016b76 MC |
2817 | if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) { |
2818 | last_idx++; | |
2819 | } | |
2820 | if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { | |
2821 | break; | |
2822 | } | |
2823 | } | |
1d39ed56 | 2824 | |
e95524a7 AD |
2825 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), |
2826 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
b6016b76 MC |
2827 | |
2828 | tx_buf->skb = NULL; | |
d62fda08 | 2829 | last = tx_buf->nr_frags; |
b6016b76 MC |
2830 | |
2831 | for (i = 0; i < last; i++) { | |
2832 | sw_cons = NEXT_TX_BD(sw_cons); | |
e95524a7 AD |
2833 | |
2834 | pci_unmap_page(bp->pdev, | |
2835 | pci_unmap_addr( | |
2836 | &txr->tx_buf_ring[TX_RING_IDX(sw_cons)], | |
2837 | mapping), | |
2838 | skb_shinfo(skb)->frags[i].size, | |
2839 | PCI_DMA_TODEVICE); | |
b6016b76 MC |
2840 | } |
2841 | ||
2842 | sw_cons = NEXT_TX_BD(sw_cons); | |
2843 | ||
745720e5 | 2844 | dev_kfree_skb(skb); |
57851d84 MC |
2845 | tx_pkt++; |
2846 | if (tx_pkt == budget) | |
2847 | break; | |
b6016b76 | 2848 | |
d62fda08 ED |
2849 | if (hw_cons == sw_cons) |
2850 | hw_cons = bnx2_get_hw_tx_cons(bnapi); | |
b6016b76 MC |
2851 | } |
2852 | ||
35e9010b MC |
2853 | txr->hw_tx_cons = hw_cons; |
2854 | txr->tx_cons = sw_cons; | |
706bf240 | 2855 | |
2f8af120 | 2856 | /* Need to make the tx_cons update visible to bnx2_start_xmit() |
706bf240 | 2857 | * before checking for netif_tx_queue_stopped(). Without the |
2f8af120 MC |
2858 | * memory barrier, there is a small possibility that bnx2_start_xmit() |
2859 | * will miss it and cause the queue to be stopped forever. | |
2860 | */ | |
2861 | smp_mb(); | |
b6016b76 | 2862 | |
706bf240 | 2863 | if (unlikely(netif_tx_queue_stopped(txq)) && |
35e9010b | 2864 | (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { |
706bf240 BL |
2865 | __netif_tx_lock(txq, smp_processor_id()); |
2866 | if ((netif_tx_queue_stopped(txq)) && | |
35e9010b | 2867 | (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) |
706bf240 BL |
2868 | netif_tx_wake_queue(txq); |
2869 | __netif_tx_unlock(txq); | |
b6016b76 | 2870 | } |
706bf240 | 2871 | |
57851d84 | 2872 | return tx_pkt; |
b6016b76 MC |
2873 | } |
2874 | ||
1db82f2a | 2875 | static void |
bb4f98ab | 2876 | bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, |
a1f60190 | 2877 | struct sk_buff *skb, int count) |
1db82f2a MC |
2878 | { |
2879 | struct sw_pg *cons_rx_pg, *prod_rx_pg; | |
2880 | struct rx_bd *cons_bd, *prod_bd; | |
1db82f2a | 2881 | int i; |
3d16af86 | 2882 | u16 hw_prod, prod; |
bb4f98ab | 2883 | u16 cons = rxr->rx_pg_cons; |
1db82f2a | 2884 | |
3d16af86 BL |
2885 | cons_rx_pg = &rxr->rx_pg_ring[cons]; |
2886 | ||
2887 | /* The caller was unable to allocate a new page to replace the | |
2888 | * last one in the frags array, so we need to recycle that page | |
2889 | * and then free the skb. | |
2890 | */ | |
2891 | if (skb) { | |
2892 | struct page *page; | |
2893 | struct skb_shared_info *shinfo; | |
2894 | ||
2895 | shinfo = skb_shinfo(skb); | |
2896 | shinfo->nr_frags--; | |
2897 | page = shinfo->frags[shinfo->nr_frags].page; | |
2898 | shinfo->frags[shinfo->nr_frags].page = NULL; | |
2899 | ||
2900 | cons_rx_pg->page = page; | |
2901 | dev_kfree_skb(skb); | |
2902 | } | |
2903 | ||
2904 | hw_prod = rxr->rx_pg_prod; | |
2905 | ||
1db82f2a MC |
2906 | for (i = 0; i < count; i++) { |
2907 | prod = RX_PG_RING_IDX(hw_prod); | |
2908 | ||
bb4f98ab MC |
2909 | prod_rx_pg = &rxr->rx_pg_ring[prod]; |
2910 | cons_rx_pg = &rxr->rx_pg_ring[cons]; | |
2911 | cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; | |
2912 | prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
1db82f2a | 2913 | |
1db82f2a MC |
2914 | if (prod != cons) { |
2915 | prod_rx_pg->page = cons_rx_pg->page; | |
2916 | cons_rx_pg->page = NULL; | |
2917 | pci_unmap_addr_set(prod_rx_pg, mapping, | |
2918 | pci_unmap_addr(cons_rx_pg, mapping)); | |
2919 | ||
2920 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; | |
2921 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
2922 | ||
2923 | } | |
2924 | cons = RX_PG_RING_IDX(NEXT_RX_BD(cons)); | |
2925 | hw_prod = NEXT_RX_BD(hw_prod); | |
2926 | } | |
bb4f98ab MC |
2927 | rxr->rx_pg_prod = hw_prod; |
2928 | rxr->rx_pg_cons = cons; | |
1db82f2a MC |
2929 | } |
2930 | ||
b6016b76 | 2931 | static inline void |
bb4f98ab MC |
2932 | bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, |
2933 | struct sk_buff *skb, u16 cons, u16 prod) | |
b6016b76 | 2934 | { |
236b6394 MC |
2935 | struct sw_bd *cons_rx_buf, *prod_rx_buf; |
2936 | struct rx_bd *cons_bd, *prod_bd; | |
2937 | ||
bb4f98ab MC |
2938 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
2939 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
b6016b76 MC |
2940 | |
2941 | pci_dma_sync_single_for_device(bp->pdev, | |
2942 | pci_unmap_addr(cons_rx_buf, mapping), | |
601d3d18 | 2943 | BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE); |
b6016b76 | 2944 | |
bb4f98ab | 2945 | rxr->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 | 2946 | |
236b6394 | 2947 | prod_rx_buf->skb = skb; |
b6016b76 | 2948 | |
236b6394 MC |
2949 | if (cons == prod) |
2950 | return; | |
b6016b76 | 2951 | |
236b6394 MC |
2952 | pci_unmap_addr_set(prod_rx_buf, mapping, |
2953 | pci_unmap_addr(cons_rx_buf, mapping)); | |
2954 | ||
bb4f98ab MC |
2955 | cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; |
2956 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
236b6394 MC |
2957 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; |
2958 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
b6016b76 MC |
2959 | } |
2960 | ||
85833c62 | 2961 | static int |
bb4f98ab | 2962 | bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb, |
a1f60190 MC |
2963 | unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, |
2964 | u32 ring_idx) | |
85833c62 MC |
2965 | { |
2966 | int err; | |
2967 | u16 prod = ring_idx & 0xffff; | |
2968 | ||
bb4f98ab | 2969 | err = bnx2_alloc_rx_skb(bp, rxr, prod); |
85833c62 | 2970 | if (unlikely(err)) { |
bb4f98ab | 2971 | bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod); |
1db82f2a MC |
2972 | if (hdr_len) { |
2973 | unsigned int raw_len = len + 4; | |
2974 | int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; | |
2975 | ||
bb4f98ab | 2976 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); |
1db82f2a | 2977 | } |
85833c62 MC |
2978 | return err; |
2979 | } | |
2980 | ||
d89cb6af | 2981 | skb_reserve(skb, BNX2_RX_OFFSET); |
85833c62 MC |
2982 | pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size, |
2983 | PCI_DMA_FROMDEVICE); | |
2984 | ||
1db82f2a MC |
2985 | if (hdr_len == 0) { |
2986 | skb_put(skb, len); | |
2987 | return 0; | |
2988 | } else { | |
2989 | unsigned int i, frag_len, frag_size, pages; | |
2990 | struct sw_pg *rx_pg; | |
bb4f98ab MC |
2991 | u16 pg_cons = rxr->rx_pg_cons; |
2992 | u16 pg_prod = rxr->rx_pg_prod; | |
1db82f2a MC |
2993 | |
2994 | frag_size = len + 4 - hdr_len; | |
2995 | pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; | |
2996 | skb_put(skb, hdr_len); | |
2997 | ||
2998 | for (i = 0; i < pages; i++) { | |
3d16af86 BL |
2999 | dma_addr_t mapping_old; |
3000 | ||
1db82f2a MC |
3001 | frag_len = min(frag_size, (unsigned int) PAGE_SIZE); |
3002 | if (unlikely(frag_len <= 4)) { | |
3003 | unsigned int tail = 4 - frag_len; | |
3004 | ||
bb4f98ab MC |
3005 | rxr->rx_pg_cons = pg_cons; |
3006 | rxr->rx_pg_prod = pg_prod; | |
3007 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, | |
a1f60190 | 3008 | pages - i); |
1db82f2a MC |
3009 | skb->len -= tail; |
3010 | if (i == 0) { | |
3011 | skb->tail -= tail; | |
3012 | } else { | |
3013 | skb_frag_t *frag = | |
3014 | &skb_shinfo(skb)->frags[i - 1]; | |
3015 | frag->size -= tail; | |
3016 | skb->data_len -= tail; | |
3017 | skb->truesize -= tail; | |
3018 | } | |
3019 | return 0; | |
3020 | } | |
bb4f98ab | 3021 | rx_pg = &rxr->rx_pg_ring[pg_cons]; |
1db82f2a | 3022 | |
3d16af86 BL |
3023 | /* Don't unmap yet. If we're unable to allocate a new |
3024 | * page, we need to recycle the page and the DMA addr. | |
3025 | */ | |
3026 | mapping_old = pci_unmap_addr(rx_pg, mapping); | |
1db82f2a MC |
3027 | if (i == pages - 1) |
3028 | frag_len -= 4; | |
3029 | ||
3030 | skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); | |
3031 | rx_pg->page = NULL; | |
3032 | ||
bb4f98ab MC |
3033 | err = bnx2_alloc_rx_page(bp, rxr, |
3034 | RX_PG_RING_IDX(pg_prod)); | |
1db82f2a | 3035 | if (unlikely(err)) { |
bb4f98ab MC |
3036 | rxr->rx_pg_cons = pg_cons; |
3037 | rxr->rx_pg_prod = pg_prod; | |
3038 | bnx2_reuse_rx_skb_pages(bp, rxr, skb, | |
a1f60190 | 3039 | pages - i); |
1db82f2a MC |
3040 | return err; |
3041 | } | |
3042 | ||
3d16af86 BL |
3043 | pci_unmap_page(bp->pdev, mapping_old, |
3044 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | |
3045 | ||
1db82f2a MC |
3046 | frag_size -= frag_len; |
3047 | skb->data_len += frag_len; | |
3048 | skb->truesize += frag_len; | |
3049 | skb->len += frag_len; | |
3050 | ||
3051 | pg_prod = NEXT_RX_BD(pg_prod); | |
3052 | pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); | |
3053 | } | |
bb4f98ab MC |
3054 | rxr->rx_pg_prod = pg_prod; |
3055 | rxr->rx_pg_cons = pg_cons; | |
1db82f2a | 3056 | } |
85833c62 MC |
3057 | return 0; |
3058 | } | |
3059 | ||
c09c2627 | 3060 | static inline u16 |
35efa7c1 | 3061 | bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) |
c09c2627 | 3062 | { |
bb4f98ab MC |
3063 | u16 cons; |
3064 | ||
43e80b89 MC |
3065 | /* Tell compiler that status block fields can change. */ |
3066 | barrier(); | |
3067 | cons = *bnapi->hw_rx_cons_ptr; | |
581daf7e | 3068 | barrier(); |
c09c2627 MC |
3069 | if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) |
3070 | cons++; | |
3071 | return cons; | |
3072 | } | |
3073 | ||
b6016b76 | 3074 | static int |
35efa7c1 | 3075 | bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) |
b6016b76 | 3076 | { |
bb4f98ab | 3077 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
b6016b76 MC |
3078 | u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; |
3079 | struct l2_fhdr *rx_hdr; | |
1db82f2a | 3080 | int rx_pkt = 0, pg_ring_used = 0; |
b6016b76 | 3081 | |
35efa7c1 | 3082 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
bb4f98ab MC |
3083 | sw_cons = rxr->rx_cons; |
3084 | sw_prod = rxr->rx_prod; | |
b6016b76 MC |
3085 | |
3086 | /* Memory barrier necessary as speculative reads of the rx | |
3087 | * buffer can be ahead of the index in the status block | |
3088 | */ | |
3089 | rmb(); | |
3090 | while (sw_cons != hw_cons) { | |
1db82f2a | 3091 | unsigned int len, hdr_len; |
ade2bfe7 | 3092 | u32 status; |
b6016b76 MC |
3093 | struct sw_bd *rx_buf; |
3094 | struct sk_buff *skb; | |
236b6394 | 3095 | dma_addr_t dma_addr; |
f22828e8 MC |
3096 | u16 vtag = 0; |
3097 | int hw_vlan __maybe_unused = 0; | |
b6016b76 MC |
3098 | |
3099 | sw_ring_cons = RX_RING_IDX(sw_cons); | |
3100 | sw_ring_prod = RX_RING_IDX(sw_prod); | |
3101 | ||
bb4f98ab | 3102 | rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; |
b6016b76 | 3103 | skb = rx_buf->skb; |
236b6394 MC |
3104 | |
3105 | rx_buf->skb = NULL; | |
3106 | ||
3107 | dma_addr = pci_unmap_addr(rx_buf, mapping); | |
3108 | ||
3109 | pci_dma_sync_single_for_cpu(bp->pdev, dma_addr, | |
601d3d18 BL |
3110 | BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, |
3111 | PCI_DMA_FROMDEVICE); | |
b6016b76 MC |
3112 | |
3113 | rx_hdr = (struct l2_fhdr *) skb->data; | |
1db82f2a | 3114 | len = rx_hdr->l2_fhdr_pkt_len; |
990ec380 | 3115 | status = rx_hdr->l2_fhdr_status; |
b6016b76 | 3116 | |
1db82f2a MC |
3117 | hdr_len = 0; |
3118 | if (status & L2_FHDR_STATUS_SPLIT) { | |
3119 | hdr_len = rx_hdr->l2_fhdr_ip_xsum; | |
3120 | pg_ring_used = 1; | |
3121 | } else if (len > bp->rx_jumbo_thresh) { | |
3122 | hdr_len = bp->rx_jumbo_thresh; | |
3123 | pg_ring_used = 1; | |
3124 | } | |
3125 | ||
990ec380 MC |
3126 | if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC | |
3127 | L2_FHDR_ERRORS_PHY_DECODE | | |
3128 | L2_FHDR_ERRORS_ALIGNMENT | | |
3129 | L2_FHDR_ERRORS_TOO_SHORT | | |
3130 | L2_FHDR_ERRORS_GIANT_FRAME))) { | |
3131 | ||
3132 | bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, | |
3133 | sw_ring_prod); | |
3134 | if (pg_ring_used) { | |
3135 | int pages; | |
3136 | ||
3137 | pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; | |
3138 | ||
3139 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); | |
3140 | } | |
3141 | goto next_rx; | |
3142 | } | |
3143 | ||
1db82f2a | 3144 | len -= 4; |
b6016b76 | 3145 | |
5d5d0015 | 3146 | if (len <= bp->rx_copy_thresh) { |
b6016b76 MC |
3147 | struct sk_buff *new_skb; |
3148 | ||
f22828e8 | 3149 | new_skb = netdev_alloc_skb(bp->dev, len + 6); |
85833c62 | 3150 | if (new_skb == NULL) { |
bb4f98ab | 3151 | bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, |
85833c62 MC |
3152 | sw_ring_prod); |
3153 | goto next_rx; | |
3154 | } | |
b6016b76 MC |
3155 | |
3156 | /* aligned copy */ | |
d89cb6af | 3157 | skb_copy_from_linear_data_offset(skb, |
f22828e8 MC |
3158 | BNX2_RX_OFFSET - 6, |
3159 | new_skb->data, len + 6); | |
3160 | skb_reserve(new_skb, 6); | |
b6016b76 | 3161 | skb_put(new_skb, len); |
b6016b76 | 3162 | |
bb4f98ab | 3163 | bnx2_reuse_rx_skb(bp, rxr, skb, |
b6016b76 MC |
3164 | sw_ring_cons, sw_ring_prod); |
3165 | ||
3166 | skb = new_skb; | |
bb4f98ab | 3167 | } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len, |
a1f60190 | 3168 | dma_addr, (sw_ring_cons << 16) | sw_ring_prod))) |
b6016b76 | 3169 | goto next_rx; |
b6016b76 | 3170 | |
f22828e8 MC |
3171 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && |
3172 | !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) { | |
3173 | vtag = rx_hdr->l2_fhdr_vlan_tag; | |
3174 | #ifdef BCM_VLAN | |
3175 | if (bp->vlgrp) | |
3176 | hw_vlan = 1; | |
3177 | else | |
3178 | #endif | |
3179 | { | |
3180 | struct vlan_ethhdr *ve = (struct vlan_ethhdr *) | |
3181 | __skb_push(skb, 4); | |
3182 | ||
3183 | memmove(ve, skb->data + 4, ETH_ALEN * 2); | |
3184 | ve->h_vlan_proto = htons(ETH_P_8021Q); | |
3185 | ve->h_vlan_TCI = htons(vtag); | |
3186 | len += 4; | |
3187 | } | |
3188 | } | |
3189 | ||
b6016b76 MC |
3190 | skb->protocol = eth_type_trans(skb, bp->dev); |
3191 | ||
3192 | if ((len > (bp->dev->mtu + ETH_HLEN)) && | |
d1e100ba | 3193 | (ntohs(skb->protocol) != 0x8100)) { |
b6016b76 | 3194 | |
745720e5 | 3195 | dev_kfree_skb(skb); |
b6016b76 MC |
3196 | goto next_rx; |
3197 | ||
3198 | } | |
3199 | ||
b6016b76 MC |
3200 | skb->ip_summed = CHECKSUM_NONE; |
3201 | if (bp->rx_csum && | |
3202 | (status & (L2_FHDR_STATUS_TCP_SEGMENT | | |
3203 | L2_FHDR_STATUS_UDP_DATAGRAM))) { | |
3204 | ||
ade2bfe7 MC |
3205 | if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM | |
3206 | L2_FHDR_ERRORS_UDP_XSUM)) == 0)) | |
b6016b76 MC |
3207 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
3208 | } | |
3209 | ||
0c8dfc83 DM |
3210 | skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); |
3211 | ||
b6016b76 | 3212 | #ifdef BCM_VLAN |
f22828e8 MC |
3213 | if (hw_vlan) |
3214 | vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag); | |
b6016b76 MC |
3215 | else |
3216 | #endif | |
3217 | netif_receive_skb(skb); | |
3218 | ||
b6016b76 MC |
3219 | rx_pkt++; |
3220 | ||
3221 | next_rx: | |
b6016b76 MC |
3222 | sw_cons = NEXT_RX_BD(sw_cons); |
3223 | sw_prod = NEXT_RX_BD(sw_prod); | |
3224 | ||
3225 | if ((rx_pkt == budget)) | |
3226 | break; | |
f4e418f7 MC |
3227 | |
3228 | /* Refresh hw_cons to see if there is new work */ | |
3229 | if (sw_cons == hw_cons) { | |
35efa7c1 | 3230 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
f4e418f7 MC |
3231 | rmb(); |
3232 | } | |
b6016b76 | 3233 | } |
bb4f98ab MC |
3234 | rxr->rx_cons = sw_cons; |
3235 | rxr->rx_prod = sw_prod; | |
b6016b76 | 3236 | |
1db82f2a | 3237 | if (pg_ring_used) |
bb4f98ab | 3238 | REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); |
1db82f2a | 3239 | |
bb4f98ab | 3240 | REG_WR16(bp, rxr->rx_bidx_addr, sw_prod); |
b6016b76 | 3241 | |
bb4f98ab | 3242 | REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); |
b6016b76 MC |
3243 | |
3244 | mmiowb(); | |
3245 | ||
3246 | return rx_pkt; | |
3247 | ||
3248 | } | |
3249 | ||
3250 | /* MSI ISR - The only difference between this and the INTx ISR | |
3251 | * is that the MSI interrupt is always serviced. | |
3252 | */ | |
3253 | static irqreturn_t | |
7d12e780 | 3254 | bnx2_msi(int irq, void *dev_instance) |
b6016b76 | 3255 | { |
f0ea2e63 MC |
3256 | struct bnx2_napi *bnapi = dev_instance; |
3257 | struct bnx2 *bp = bnapi->bp; | |
b6016b76 | 3258 | |
43e80b89 | 3259 | prefetch(bnapi->status_blk.msi); |
b6016b76 MC |
3260 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3261 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | |
3262 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
3263 | ||
3264 | /* Return here if interrupt is disabled. */ | |
73eef4cd MC |
3265 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3266 | return IRQ_HANDLED; | |
b6016b76 | 3267 | |
288379f0 | 3268 | napi_schedule(&bnapi->napi); |
b6016b76 | 3269 | |
73eef4cd | 3270 | return IRQ_HANDLED; |
b6016b76 MC |
3271 | } |
3272 | ||
8e6a72c4 MC |
3273 | static irqreturn_t |
3274 | bnx2_msi_1shot(int irq, void *dev_instance) | |
3275 | { | |
f0ea2e63 MC |
3276 | struct bnx2_napi *bnapi = dev_instance; |
3277 | struct bnx2 *bp = bnapi->bp; | |
8e6a72c4 | 3278 | |
43e80b89 | 3279 | prefetch(bnapi->status_blk.msi); |
8e6a72c4 MC |
3280 | |
3281 | /* Return here if interrupt is disabled. */ | |
3282 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
3283 | return IRQ_HANDLED; | |
3284 | ||
288379f0 | 3285 | napi_schedule(&bnapi->napi); |
8e6a72c4 MC |
3286 | |
3287 | return IRQ_HANDLED; | |
3288 | } | |
3289 | ||
b6016b76 | 3290 | static irqreturn_t |
7d12e780 | 3291 | bnx2_interrupt(int irq, void *dev_instance) |
b6016b76 | 3292 | { |
f0ea2e63 MC |
3293 | struct bnx2_napi *bnapi = dev_instance; |
3294 | struct bnx2 *bp = bnapi->bp; | |
43e80b89 | 3295 | struct status_block *sblk = bnapi->status_blk.msi; |
b6016b76 MC |
3296 | |
3297 | /* When using INTx, it is possible for the interrupt to arrive | |
3298 | * at the CPU before the status block posted prior to the | |
3299 | * interrupt. Reading a register will flush the status block. | |
3300 | * When using MSI, the MSI message will always complete after | |
3301 | * the status block write. | |
3302 | */ | |
35efa7c1 | 3303 | if ((sblk->status_idx == bnapi->last_status_idx) && |
b6016b76 MC |
3304 | (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & |
3305 | BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) | |
73eef4cd | 3306 | return IRQ_NONE; |
b6016b76 MC |
3307 | |
3308 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
3309 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | |
3310 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
3311 | ||
b8a7ce7b MC |
3312 | /* Read back to deassert IRQ immediately to avoid too many |
3313 | * spurious interrupts. | |
3314 | */ | |
3315 | REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); | |
3316 | ||
b6016b76 | 3317 | /* Return here if interrupt is shared and is disabled. */ |
73eef4cd MC |
3318 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3319 | return IRQ_HANDLED; | |
b6016b76 | 3320 | |
288379f0 | 3321 | if (napi_schedule_prep(&bnapi->napi)) { |
35efa7c1 | 3322 | bnapi->last_status_idx = sblk->status_idx; |
288379f0 | 3323 | __napi_schedule(&bnapi->napi); |
b8a7ce7b | 3324 | } |
b6016b76 | 3325 | |
73eef4cd | 3326 | return IRQ_HANDLED; |
b6016b76 MC |
3327 | } |
3328 | ||
f4e418f7 | 3329 | static inline int |
43e80b89 | 3330 | bnx2_has_fast_work(struct bnx2_napi *bnapi) |
f4e418f7 | 3331 | { |
35e9010b | 3332 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
bb4f98ab | 3333 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
f4e418f7 | 3334 | |
bb4f98ab | 3335 | if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || |
35e9010b | 3336 | (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) |
f4e418f7 | 3337 | return 1; |
43e80b89 MC |
3338 | return 0; |
3339 | } | |
3340 | ||
3341 | #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ | |
3342 | STATUS_ATTN_BITS_TIMER_ABORT) | |
3343 | ||
3344 | static inline int | |
3345 | bnx2_has_work(struct bnx2_napi *bnapi) | |
3346 | { | |
3347 | struct status_block *sblk = bnapi->status_blk.msi; | |
3348 | ||
3349 | if (bnx2_has_fast_work(bnapi)) | |
3350 | return 1; | |
f4e418f7 | 3351 | |
4edd473f MC |
3352 | #ifdef BCM_CNIC |
3353 | if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) | |
3354 | return 1; | |
3355 | #endif | |
3356 | ||
da3e4fbe MC |
3357 | if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != |
3358 | (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) | |
f4e418f7 MC |
3359 | return 1; |
3360 | ||
3361 | return 0; | |
3362 | } | |
3363 | ||
efba0180 MC |
3364 | static void |
3365 | bnx2_chk_missed_msi(struct bnx2 *bp) | |
3366 | { | |
3367 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
3368 | u32 msi_ctrl; | |
3369 | ||
3370 | if (bnx2_has_work(bnapi)) { | |
3371 | msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL); | |
3372 | if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) | |
3373 | return; | |
3374 | ||
3375 | if (bnapi->last_status_idx == bp->idle_chk_status_idx) { | |
3376 | REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & | |
3377 | ~BNX2_PCICFG_MSI_CONTROL_ENABLE); | |
3378 | REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); | |
3379 | bnx2_msi(bp->irq_tbl[0].vector, bnapi); | |
3380 | } | |
3381 | } | |
3382 | ||
3383 | bp->idle_chk_status_idx = bnapi->last_status_idx; | |
3384 | } | |
3385 | ||
4edd473f MC |
3386 | #ifdef BCM_CNIC |
3387 | static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi) | |
3388 | { | |
3389 | struct cnic_ops *c_ops; | |
3390 | ||
3391 | if (!bnapi->cnic_present) | |
3392 | return; | |
3393 | ||
3394 | rcu_read_lock(); | |
3395 | c_ops = rcu_dereference(bp->cnic_ops); | |
3396 | if (c_ops) | |
3397 | bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, | |
3398 | bnapi->status_blk.msi); | |
3399 | rcu_read_unlock(); | |
3400 | } | |
3401 | #endif | |
3402 | ||
43e80b89 | 3403 | static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) |
b6016b76 | 3404 | { |
43e80b89 | 3405 | struct status_block *sblk = bnapi->status_blk.msi; |
da3e4fbe MC |
3406 | u32 status_attn_bits = sblk->status_attn_bits; |
3407 | u32 status_attn_bits_ack = sblk->status_attn_bits_ack; | |
b6016b76 | 3408 | |
da3e4fbe MC |
3409 | if ((status_attn_bits & STATUS_ATTN_EVENTS) != |
3410 | (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { | |
b6016b76 | 3411 | |
35efa7c1 | 3412 | bnx2_phy_int(bp, bnapi); |
bf5295bb MC |
3413 | |
3414 | /* This is needed to take care of transient status | |
3415 | * during link changes. | |
3416 | */ | |
3417 | REG_WR(bp, BNX2_HC_COMMAND, | |
3418 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
3419 | REG_RD(bp, BNX2_HC_COMMAND); | |
b6016b76 | 3420 | } |
43e80b89 MC |
3421 | } |
3422 | ||
3423 | static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, | |
3424 | int work_done, int budget) | |
3425 | { | |
3426 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
3427 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
b6016b76 | 3428 | |
35e9010b | 3429 | if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) |
57851d84 | 3430 | bnx2_tx_int(bp, bnapi, 0); |
b6016b76 | 3431 | |
bb4f98ab | 3432 | if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) |
35efa7c1 | 3433 | work_done += bnx2_rx_int(bp, bnapi, budget - work_done); |
6aa20a22 | 3434 | |
6f535763 DM |
3435 | return work_done; |
3436 | } | |
3437 | ||
f0ea2e63 MC |
3438 | static int bnx2_poll_msix(struct napi_struct *napi, int budget) |
3439 | { | |
3440 | struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); | |
3441 | struct bnx2 *bp = bnapi->bp; | |
3442 | int work_done = 0; | |
3443 | struct status_block_msix *sblk = bnapi->status_blk.msix; | |
3444 | ||
3445 | while (1) { | |
3446 | work_done = bnx2_poll_work(bp, bnapi, work_done, budget); | |
3447 | if (unlikely(work_done >= budget)) | |
3448 | break; | |
3449 | ||
3450 | bnapi->last_status_idx = sblk->status_idx; | |
3451 | /* status idx must be read before checking for more work. */ | |
3452 | rmb(); | |
3453 | if (likely(!bnx2_has_fast_work(bnapi))) { | |
3454 | ||
288379f0 | 3455 | napi_complete(napi); |
f0ea2e63 MC |
3456 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
3457 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3458 | bnapi->last_status_idx); | |
3459 | break; | |
3460 | } | |
3461 | } | |
3462 | return work_done; | |
3463 | } | |
3464 | ||
6f535763 DM |
3465 | static int bnx2_poll(struct napi_struct *napi, int budget) |
3466 | { | |
35efa7c1 MC |
3467 | struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); |
3468 | struct bnx2 *bp = bnapi->bp; | |
6f535763 | 3469 | int work_done = 0; |
43e80b89 | 3470 | struct status_block *sblk = bnapi->status_blk.msi; |
6f535763 DM |
3471 | |
3472 | while (1) { | |
43e80b89 MC |
3473 | bnx2_poll_link(bp, bnapi); |
3474 | ||
35efa7c1 | 3475 | work_done = bnx2_poll_work(bp, bnapi, work_done, budget); |
f4e418f7 | 3476 | |
4edd473f MC |
3477 | #ifdef BCM_CNIC |
3478 | bnx2_poll_cnic(bp, bnapi); | |
3479 | #endif | |
3480 | ||
35efa7c1 | 3481 | /* bnapi->last_status_idx is used below to tell the hw how |
6dee6421 MC |
3482 | * much work has been processed, so we must read it before |
3483 | * checking for more work. | |
3484 | */ | |
35efa7c1 | 3485 | bnapi->last_status_idx = sblk->status_idx; |
efba0180 MC |
3486 | |
3487 | if (unlikely(work_done >= budget)) | |
3488 | break; | |
3489 | ||
6dee6421 | 3490 | rmb(); |
35efa7c1 | 3491 | if (likely(!bnx2_has_work(bnapi))) { |
288379f0 | 3492 | napi_complete(napi); |
f86e82fb | 3493 | if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { |
6f535763 DM |
3494 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3495 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
35efa7c1 | 3496 | bnapi->last_status_idx); |
6dee6421 | 3497 | break; |
6f535763 | 3498 | } |
1269a8a6 MC |
3499 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3500 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
6f535763 | 3501 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | |
35efa7c1 | 3502 | bnapi->last_status_idx); |
1269a8a6 | 3503 | |
6f535763 DM |
3504 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3505 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
35efa7c1 | 3506 | bnapi->last_status_idx); |
6f535763 DM |
3507 | break; |
3508 | } | |
b6016b76 MC |
3509 | } |
3510 | ||
bea3348e | 3511 | return work_done; |
b6016b76 MC |
3512 | } |
3513 | ||
932ff279 | 3514 | /* Called with rtnl_lock from vlan functions and also netif_tx_lock |
b6016b76 MC |
3515 | * from set_multicast. |
3516 | */ | |
3517 | static void | |
3518 | bnx2_set_rx_mode(struct net_device *dev) | |
3519 | { | |
972ec0d4 | 3520 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 3521 | u32 rx_mode, sort_mode; |
ccffad25 | 3522 | struct netdev_hw_addr *ha; |
b6016b76 | 3523 | int i; |
b6016b76 | 3524 | |
9f52b564 MC |
3525 | if (!netif_running(dev)) |
3526 | return; | |
3527 | ||
c770a65c | 3528 | spin_lock_bh(&bp->phy_lock); |
b6016b76 MC |
3529 | |
3530 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | | |
3531 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); | |
3532 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; | |
3533 | #ifdef BCM_VLAN | |
7c6337a1 | 3534 | if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) |
b6016b76 | 3535 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; |
b6016b76 | 3536 | #else |
7c6337a1 | 3537 | if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN) |
e29054f9 | 3538 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; |
b6016b76 MC |
3539 | #endif |
3540 | if (dev->flags & IFF_PROMISC) { | |
3541 | /* Promiscuous mode. */ | |
3542 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; | |
7510873d MC |
3543 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | |
3544 | BNX2_RPM_SORT_USER0_PROM_VLAN; | |
b6016b76 MC |
3545 | } |
3546 | else if (dev->flags & IFF_ALLMULTI) { | |
3547 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
3548 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
3549 | 0xffffffff); | |
3550 | } | |
3551 | sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; | |
3552 | } | |
3553 | else { | |
3554 | /* Accept one or more multicast(s). */ | |
3555 | struct dev_mc_list *mclist; | |
3556 | u32 mc_filter[NUM_MC_HASH_REGISTERS]; | |
3557 | u32 regidx; | |
3558 | u32 bit; | |
3559 | u32 crc; | |
3560 | ||
3561 | memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); | |
3562 | ||
4cd24eaf | 3563 | for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev); |
b6016b76 MC |
3564 | i++, mclist = mclist->next) { |
3565 | ||
3566 | crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr); | |
3567 | bit = crc & 0xff; | |
3568 | regidx = (bit & 0xe0) >> 5; | |
3569 | bit &= 0x1f; | |
3570 | mc_filter[regidx] |= (1 << bit); | |
3571 | } | |
3572 | ||
3573 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
3574 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
3575 | mc_filter[i]); | |
3576 | } | |
3577 | ||
3578 | sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; | |
3579 | } | |
3580 | ||
32e7bfc4 | 3581 | if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) { |
5fcaed01 BL |
3582 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; |
3583 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | | |
3584 | BNX2_RPM_SORT_USER0_PROM_VLAN; | |
3585 | } else if (!(dev->flags & IFF_PROMISC)) { | |
5fcaed01 | 3586 | /* Add all entries into to the match filter list */ |
ccffad25 | 3587 | i = 0; |
32e7bfc4 | 3588 | netdev_for_each_uc_addr(ha, dev) { |
ccffad25 | 3589 | bnx2_set_mac_addr(bp, ha->addr, |
5fcaed01 BL |
3590 | i + BNX2_START_UNICAST_ADDRESS_INDEX); |
3591 | sort_mode |= (1 << | |
3592 | (i + BNX2_START_UNICAST_ADDRESS_INDEX)); | |
ccffad25 | 3593 | i++; |
5fcaed01 BL |
3594 | } |
3595 | ||
3596 | } | |
3597 | ||
b6016b76 MC |
3598 | if (rx_mode != bp->rx_mode) { |
3599 | bp->rx_mode = rx_mode; | |
3600 | REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); | |
3601 | } | |
3602 | ||
3603 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | |
3604 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); | |
3605 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); | |
3606 | ||
c770a65c | 3607 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
3608 | } |
3609 | ||
57579f76 MC |
3610 | static int __devinit |
3611 | check_fw_section(const struct firmware *fw, | |
3612 | const struct bnx2_fw_file_section *section, | |
3613 | u32 alignment, bool non_empty) | |
3614 | { | |
3615 | u32 offset = be32_to_cpu(section->offset); | |
3616 | u32 len = be32_to_cpu(section->len); | |
3617 | ||
3618 | if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) | |
3619 | return -EINVAL; | |
3620 | if ((non_empty && len == 0) || len > fw->size - offset || | |
3621 | len & (alignment - 1)) | |
3622 | return -EINVAL; | |
3623 | return 0; | |
3624 | } | |
3625 | ||
3626 | static int __devinit | |
3627 | check_mips_fw_entry(const struct firmware *fw, | |
3628 | const struct bnx2_mips_fw_file_entry *entry) | |
3629 | { | |
3630 | if (check_fw_section(fw, &entry->text, 4, true) || | |
3631 | check_fw_section(fw, &entry->data, 4, false) || | |
3632 | check_fw_section(fw, &entry->rodata, 4, false)) | |
3633 | return -EINVAL; | |
3634 | return 0; | |
3635 | } | |
3636 | ||
3637 | static int __devinit | |
3638 | bnx2_request_firmware(struct bnx2 *bp) | |
b6016b76 | 3639 | { |
57579f76 | 3640 | const char *mips_fw_file, *rv2p_fw_file; |
5ee1c326 BB |
3641 | const struct bnx2_mips_fw_file *mips_fw; |
3642 | const struct bnx2_rv2p_fw_file *rv2p_fw; | |
57579f76 MC |
3643 | int rc; |
3644 | ||
3645 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
3646 | mips_fw_file = FW_MIPS_FILE_09; | |
078b0735 MC |
3647 | if ((CHIP_ID(bp) == CHIP_ID_5709_A0) || |
3648 | (CHIP_ID(bp) == CHIP_ID_5709_A1)) | |
3649 | rv2p_fw_file = FW_RV2P_FILE_09_Ax; | |
3650 | else | |
3651 | rv2p_fw_file = FW_RV2P_FILE_09; | |
57579f76 MC |
3652 | } else { |
3653 | mips_fw_file = FW_MIPS_FILE_06; | |
3654 | rv2p_fw_file = FW_RV2P_FILE_06; | |
3655 | } | |
3656 | ||
3657 | rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); | |
3658 | if (rc) { | |
3659 | printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n", | |
3660 | mips_fw_file); | |
3661 | return rc; | |
3662 | } | |
3663 | ||
3664 | rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); | |
3665 | if (rc) { | |
3666 | printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n", | |
3667 | rv2p_fw_file); | |
3668 | return rc; | |
3669 | } | |
5ee1c326 BB |
3670 | mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; |
3671 | rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; | |
3672 | if (bp->mips_firmware->size < sizeof(*mips_fw) || | |
3673 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || | |
3674 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || | |
3675 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || | |
3676 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || | |
3677 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { | |
57579f76 MC |
3678 | printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n", |
3679 | mips_fw_file); | |
3680 | return -EINVAL; | |
3681 | } | |
5ee1c326 BB |
3682 | if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || |
3683 | check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || | |
3684 | check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { | |
57579f76 MC |
3685 | printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n", |
3686 | rv2p_fw_file); | |
3687 | return -EINVAL; | |
3688 | } | |
3689 | ||
3690 | return 0; | |
3691 | } | |
3692 | ||
3693 | static u32 | |
3694 | rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code) | |
3695 | { | |
3696 | switch (idx) { | |
3697 | case RV2P_P1_FIXUP_PAGE_SIZE_IDX: | |
3698 | rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK; | |
3699 | rv2p_code |= RV2P_BD_PAGE_SIZE; | |
3700 | break; | |
3701 | } | |
3702 | return rv2p_code; | |
3703 | } | |
3704 | ||
3705 | static int | |
3706 | load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, | |
3707 | const struct bnx2_rv2p_fw_file_entry *fw_entry) | |
3708 | { | |
3709 | u32 rv2p_code_len, file_offset; | |
3710 | __be32 *rv2p_code; | |
b6016b76 | 3711 | int i; |
57579f76 MC |
3712 | u32 val, cmd, addr; |
3713 | ||
3714 | rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); | |
3715 | file_offset = be32_to_cpu(fw_entry->rv2p.offset); | |
3716 | ||
3717 | rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); | |
b6016b76 | 3718 | |
57579f76 MC |
3719 | if (rv2p_proc == RV2P_PROC1) { |
3720 | cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR; | |
3721 | addr = BNX2_RV2P_PROC1_ADDR_CMD; | |
3722 | } else { | |
3723 | cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR; | |
3724 | addr = BNX2_RV2P_PROC2_ADDR_CMD; | |
d25be1d3 | 3725 | } |
b6016b76 MC |
3726 | |
3727 | for (i = 0; i < rv2p_code_len; i += 8) { | |
57579f76 | 3728 | REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); |
b6016b76 | 3729 | rv2p_code++; |
57579f76 | 3730 | REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); |
b6016b76 MC |
3731 | rv2p_code++; |
3732 | ||
57579f76 MC |
3733 | val = (i / 8) | cmd; |
3734 | REG_WR(bp, addr, val); | |
3735 | } | |
3736 | ||
3737 | rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); | |
3738 | for (i = 0; i < 8; i++) { | |
3739 | u32 loc, code; | |
3740 | ||
3741 | loc = be32_to_cpu(fw_entry->fixup[i]); | |
3742 | if (loc && ((loc * 4) < rv2p_code_len)) { | |
3743 | code = be32_to_cpu(*(rv2p_code + loc - 1)); | |
3744 | REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code); | |
3745 | code = be32_to_cpu(*(rv2p_code + loc)); | |
3746 | code = rv2p_fw_fixup(rv2p_proc, i, loc, code); | |
3747 | REG_WR(bp, BNX2_RV2P_INSTR_LOW, code); | |
3748 | ||
3749 | val = (loc / 2) | cmd; | |
3750 | REG_WR(bp, addr, val); | |
b6016b76 MC |
3751 | } |
3752 | } | |
3753 | ||
3754 | /* Reset the processor, un-stall is done later. */ | |
3755 | if (rv2p_proc == RV2P_PROC1) { | |
3756 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); | |
3757 | } | |
3758 | else { | |
3759 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); | |
3760 | } | |
57579f76 MC |
3761 | |
3762 | return 0; | |
b6016b76 MC |
3763 | } |
3764 | ||
af3ee519 | 3765 | static int |
57579f76 MC |
3766 | load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, |
3767 | const struct bnx2_mips_fw_file_entry *fw_entry) | |
b6016b76 | 3768 | { |
57579f76 MC |
3769 | u32 addr, len, file_offset; |
3770 | __be32 *data; | |
b6016b76 MC |
3771 | u32 offset; |
3772 | u32 val; | |
3773 | ||
3774 | /* Halt the CPU. */ | |
2726d6e1 | 3775 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
b6016b76 | 3776 | val |= cpu_reg->mode_value_halt; |
2726d6e1 MC |
3777 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); |
3778 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); | |
b6016b76 MC |
3779 | |
3780 | /* Load the Text area. */ | |
57579f76 MC |
3781 | addr = be32_to_cpu(fw_entry->text.addr); |
3782 | len = be32_to_cpu(fw_entry->text.len); | |
3783 | file_offset = be32_to_cpu(fw_entry->text.offset); | |
3784 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
ea1f8d5c | 3785 | |
57579f76 MC |
3786 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); |
3787 | if (len) { | |
b6016b76 MC |
3788 | int j; |
3789 | ||
57579f76 MC |
3790 | for (j = 0; j < (len / 4); j++, offset += 4) |
3791 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3792 | } |
3793 | ||
57579f76 MC |
3794 | /* Load the Data area. */ |
3795 | addr = be32_to_cpu(fw_entry->data.addr); | |
3796 | len = be32_to_cpu(fw_entry->data.len); | |
3797 | file_offset = be32_to_cpu(fw_entry->data.offset); | |
3798 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
b6016b76 | 3799 | |
57579f76 MC |
3800 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); |
3801 | if (len) { | |
b6016b76 MC |
3802 | int j; |
3803 | ||
57579f76 MC |
3804 | for (j = 0; j < (len / 4); j++, offset += 4) |
3805 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3806 | } |
3807 | ||
3808 | /* Load the Read-Only area. */ | |
57579f76 MC |
3809 | addr = be32_to_cpu(fw_entry->rodata.addr); |
3810 | len = be32_to_cpu(fw_entry->rodata.len); | |
3811 | file_offset = be32_to_cpu(fw_entry->rodata.offset); | |
3812 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
3813 | ||
3814 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); | |
3815 | if (len) { | |
b6016b76 MC |
3816 | int j; |
3817 | ||
57579f76 MC |
3818 | for (j = 0; j < (len / 4); j++, offset += 4) |
3819 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3820 | } |
3821 | ||
3822 | /* Clear the pre-fetch instruction. */ | |
2726d6e1 | 3823 | bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); |
57579f76 MC |
3824 | |
3825 | val = be32_to_cpu(fw_entry->start_addr); | |
3826 | bnx2_reg_wr_ind(bp, cpu_reg->pc, val); | |
b6016b76 MC |
3827 | |
3828 | /* Start the CPU. */ | |
2726d6e1 | 3829 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
b6016b76 | 3830 | val &= ~cpu_reg->mode_value_halt; |
2726d6e1 MC |
3831 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); |
3832 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); | |
af3ee519 MC |
3833 | |
3834 | return 0; | |
b6016b76 MC |
3835 | } |
3836 | ||
fba9fe91 | 3837 | static int |
b6016b76 MC |
3838 | bnx2_init_cpus(struct bnx2 *bp) |
3839 | { | |
57579f76 MC |
3840 | const struct bnx2_mips_fw_file *mips_fw = |
3841 | (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; | |
3842 | const struct bnx2_rv2p_fw_file *rv2p_fw = | |
3843 | (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; | |
3844 | int rc; | |
b6016b76 MC |
3845 | |
3846 | /* Initialize the RV2P processor. */ | |
57579f76 MC |
3847 | load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); |
3848 | load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); | |
b6016b76 MC |
3849 | |
3850 | /* Initialize the RX Processor. */ | |
57579f76 | 3851 | rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); |
fba9fe91 MC |
3852 | if (rc) |
3853 | goto init_cpu_err; | |
3854 | ||
b6016b76 | 3855 | /* Initialize the TX Processor. */ |
57579f76 | 3856 | rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); |
fba9fe91 MC |
3857 | if (rc) |
3858 | goto init_cpu_err; | |
3859 | ||
b6016b76 | 3860 | /* Initialize the TX Patch-up Processor. */ |
57579f76 | 3861 | rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); |
fba9fe91 MC |
3862 | if (rc) |
3863 | goto init_cpu_err; | |
3864 | ||
b6016b76 | 3865 | /* Initialize the Completion Processor. */ |
57579f76 | 3866 | rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); |
fba9fe91 MC |
3867 | if (rc) |
3868 | goto init_cpu_err; | |
3869 | ||
d43584c8 | 3870 | /* Initialize the Command Processor. */ |
57579f76 | 3871 | rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); |
b6016b76 | 3872 | |
fba9fe91 | 3873 | init_cpu_err: |
fba9fe91 | 3874 | return rc; |
b6016b76 MC |
3875 | } |
3876 | ||
3877 | static int | |
829ca9a3 | 3878 | bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) |
b6016b76 MC |
3879 | { |
3880 | u16 pmcsr; | |
3881 | ||
3882 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
3883 | ||
3884 | switch (state) { | |
829ca9a3 | 3885 | case PCI_D0: { |
b6016b76 MC |
3886 | u32 val; |
3887 | ||
3888 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | |
3889 | (pmcsr & ~PCI_PM_CTRL_STATE_MASK) | | |
3890 | PCI_PM_CTRL_PME_STATUS); | |
3891 | ||
3892 | if (pmcsr & PCI_PM_CTRL_STATE_MASK) | |
3893 | /* delay required during transition out of D3hot */ | |
3894 | msleep(20); | |
3895 | ||
3896 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
3897 | val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; | |
3898 | val &= ~BNX2_EMAC_MODE_MPKT; | |
3899 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
3900 | ||
3901 | val = REG_RD(bp, BNX2_RPM_CONFIG); | |
3902 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | |
3903 | REG_WR(bp, BNX2_RPM_CONFIG, val); | |
3904 | break; | |
3905 | } | |
829ca9a3 | 3906 | case PCI_D3hot: { |
b6016b76 MC |
3907 | int i; |
3908 | u32 val, wol_msg; | |
3909 | ||
3910 | if (bp->wol) { | |
3911 | u32 advertising; | |
3912 | u8 autoneg; | |
3913 | ||
3914 | autoneg = bp->autoneg; | |
3915 | advertising = bp->advertising; | |
3916 | ||
239cd343 MC |
3917 | if (bp->phy_port == PORT_TP) { |
3918 | bp->autoneg = AUTONEG_SPEED; | |
3919 | bp->advertising = ADVERTISED_10baseT_Half | | |
3920 | ADVERTISED_10baseT_Full | | |
3921 | ADVERTISED_100baseT_Half | | |
3922 | ADVERTISED_100baseT_Full | | |
3923 | ADVERTISED_Autoneg; | |
3924 | } | |
b6016b76 | 3925 | |
239cd343 MC |
3926 | spin_lock_bh(&bp->phy_lock); |
3927 | bnx2_setup_phy(bp, bp->phy_port); | |
3928 | spin_unlock_bh(&bp->phy_lock); | |
b6016b76 MC |
3929 | |
3930 | bp->autoneg = autoneg; | |
3931 | bp->advertising = advertising; | |
3932 | ||
5fcaed01 | 3933 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 MC |
3934 | |
3935 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
3936 | ||
3937 | /* Enable port mode. */ | |
3938 | val &= ~BNX2_EMAC_MODE_PORT; | |
239cd343 | 3939 | val |= BNX2_EMAC_MODE_MPKT_RCVD | |
b6016b76 | 3940 | BNX2_EMAC_MODE_ACPI_RCVD | |
b6016b76 | 3941 | BNX2_EMAC_MODE_MPKT; |
239cd343 MC |
3942 | if (bp->phy_port == PORT_TP) |
3943 | val |= BNX2_EMAC_MODE_PORT_MII; | |
3944 | else { | |
3945 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
3946 | if (bp->line_speed == SPEED_2500) | |
3947 | val |= BNX2_EMAC_MODE_25G_MODE; | |
3948 | } | |
b6016b76 MC |
3949 | |
3950 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
3951 | ||
3952 | /* receive all multicast */ | |
3953 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
3954 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
3955 | 0xffffffff); | |
3956 | } | |
3957 | REG_WR(bp, BNX2_EMAC_RX_MODE, | |
3958 | BNX2_EMAC_RX_MODE_SORT_MODE); | |
3959 | ||
3960 | val = 1 | BNX2_RPM_SORT_USER0_BC_EN | | |
3961 | BNX2_RPM_SORT_USER0_MC_EN; | |
3962 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | |
3963 | REG_WR(bp, BNX2_RPM_SORT_USER0, val); | |
3964 | REG_WR(bp, BNX2_RPM_SORT_USER0, val | | |
3965 | BNX2_RPM_SORT_USER0_ENA); | |
3966 | ||
3967 | /* Need to enable EMAC and RPM for WOL. */ | |
3968 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
3969 | BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | | |
3970 | BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | | |
3971 | BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); | |
3972 | ||
3973 | val = REG_RD(bp, BNX2_RPM_CONFIG); | |
3974 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | |
3975 | REG_WR(bp, BNX2_RPM_CONFIG, val); | |
3976 | ||
3977 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
3978 | } | |
3979 | else { | |
3980 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
3981 | } | |
3982 | ||
f86e82fb | 3983 | if (!(bp->flags & BNX2_FLAG_NO_WOL)) |
a2f13890 MC |
3984 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, |
3985 | 1, 0); | |
b6016b76 MC |
3986 | |
3987 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
3988 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || | |
3989 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) { | |
3990 | ||
3991 | if (bp->wol) | |
3992 | pmcsr |= 3; | |
3993 | } | |
3994 | else { | |
3995 | pmcsr |= 3; | |
3996 | } | |
3997 | if (bp->wol) { | |
3998 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
3999 | } | |
4000 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | |
4001 | pmcsr); | |
4002 | ||
4003 | /* No more memory access after this point until | |
4004 | * device is brought back to D0. | |
4005 | */ | |
4006 | udelay(50); | |
4007 | break; | |
4008 | } | |
4009 | default: | |
4010 | return -EINVAL; | |
4011 | } | |
4012 | return 0; | |
4013 | } | |
4014 | ||
4015 | static int | |
4016 | bnx2_acquire_nvram_lock(struct bnx2 *bp) | |
4017 | { | |
4018 | u32 val; | |
4019 | int j; | |
4020 | ||
4021 | /* Request access to the flash interface. */ | |
4022 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); | |
4023 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4024 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | |
4025 | if (val & BNX2_NVM_SW_ARB_ARB_ARB2) | |
4026 | break; | |
4027 | ||
4028 | udelay(5); | |
4029 | } | |
4030 | ||
4031 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4032 | return -EBUSY; | |
4033 | ||
4034 | return 0; | |
4035 | } | |
4036 | ||
4037 | static int | |
4038 | bnx2_release_nvram_lock(struct bnx2 *bp) | |
4039 | { | |
4040 | int j; | |
4041 | u32 val; | |
4042 | ||
4043 | /* Relinquish nvram interface. */ | |
4044 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); | |
4045 | ||
4046 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4047 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | |
4048 | if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) | |
4049 | break; | |
4050 | ||
4051 | udelay(5); | |
4052 | } | |
4053 | ||
4054 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4055 | return -EBUSY; | |
4056 | ||
4057 | return 0; | |
4058 | } | |
4059 | ||
4060 | ||
4061 | static int | |
4062 | bnx2_enable_nvram_write(struct bnx2 *bp) | |
4063 | { | |
4064 | u32 val; | |
4065 | ||
4066 | val = REG_RD(bp, BNX2_MISC_CFG); | |
4067 | REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); | |
4068 | ||
e30372c9 | 4069 | if (bp->flash_info->flags & BNX2_NV_WREN) { |
b6016b76 MC |
4070 | int j; |
4071 | ||
4072 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
4073 | REG_WR(bp, BNX2_NVM_COMMAND, | |
4074 | BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); | |
4075 | ||
4076 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4077 | udelay(5); | |
4078 | ||
4079 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
4080 | if (val & BNX2_NVM_COMMAND_DONE) | |
4081 | break; | |
4082 | } | |
4083 | ||
4084 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4085 | return -EBUSY; | |
4086 | } | |
4087 | return 0; | |
4088 | } | |
4089 | ||
4090 | static void | |
4091 | bnx2_disable_nvram_write(struct bnx2 *bp) | |
4092 | { | |
4093 | u32 val; | |
4094 | ||
4095 | val = REG_RD(bp, BNX2_MISC_CFG); | |
4096 | REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); | |
4097 | } | |
4098 | ||
4099 | ||
4100 | static void | |
4101 | bnx2_enable_nvram_access(struct bnx2 *bp) | |
4102 | { | |
4103 | u32 val; | |
4104 | ||
4105 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | |
4106 | /* Enable both bits, even on read. */ | |
6aa20a22 | 4107 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
b6016b76 MC |
4108 | val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); |
4109 | } | |
4110 | ||
4111 | static void | |
4112 | bnx2_disable_nvram_access(struct bnx2 *bp) | |
4113 | { | |
4114 | u32 val; | |
4115 | ||
4116 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | |
4117 | /* Disable both bits, even after read. */ | |
6aa20a22 | 4118 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
b6016b76 MC |
4119 | val & ~(BNX2_NVM_ACCESS_ENABLE_EN | |
4120 | BNX2_NVM_ACCESS_ENABLE_WR_EN)); | |
4121 | } | |
4122 | ||
4123 | static int | |
4124 | bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) | |
4125 | { | |
4126 | u32 cmd; | |
4127 | int j; | |
4128 | ||
e30372c9 | 4129 | if (bp->flash_info->flags & BNX2_NV_BUFFERED) |
b6016b76 MC |
4130 | /* Buffered flash, no erase needed */ |
4131 | return 0; | |
4132 | ||
4133 | /* Build an erase command */ | |
4134 | cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | | |
4135 | BNX2_NVM_COMMAND_DOIT; | |
4136 | ||
4137 | /* Need to clear DONE bit separately. */ | |
4138 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
4139 | ||
4140 | /* Address of the NVRAM to read from. */ | |
4141 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
4142 | ||
4143 | /* Issue an erase command. */ | |
4144 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
4145 | ||
4146 | /* Wait for completion. */ | |
4147 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4148 | u32 val; | |
4149 | ||
4150 | udelay(5); | |
4151 | ||
4152 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
4153 | if (val & BNX2_NVM_COMMAND_DONE) | |
4154 | break; | |
4155 | } | |
4156 | ||
4157 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4158 | return -EBUSY; | |
4159 | ||
4160 | return 0; | |
4161 | } | |
4162 | ||
4163 | static int | |
4164 | bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) | |
4165 | { | |
4166 | u32 cmd; | |
4167 | int j; | |
4168 | ||
4169 | /* Build the command word. */ | |
4170 | cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; | |
4171 | ||
e30372c9 MC |
4172 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
4173 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
4174 | offset = ((offset / bp->flash_info->page_size) << |
4175 | bp->flash_info->page_bits) + | |
4176 | (offset % bp->flash_info->page_size); | |
4177 | } | |
4178 | ||
4179 | /* Need to clear DONE bit separately. */ | |
4180 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
4181 | ||
4182 | /* Address of the NVRAM to read from. */ | |
4183 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
4184 | ||
4185 | /* Issue a read command. */ | |
4186 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
4187 | ||
4188 | /* Wait for completion. */ | |
4189 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4190 | u32 val; | |
4191 | ||
4192 | udelay(5); | |
4193 | ||
4194 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
4195 | if (val & BNX2_NVM_COMMAND_DONE) { | |
b491edd5 AV |
4196 | __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ)); |
4197 | memcpy(ret_val, &v, 4); | |
b6016b76 MC |
4198 | break; |
4199 | } | |
4200 | } | |
4201 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4202 | return -EBUSY; | |
4203 | ||
4204 | return 0; | |
4205 | } | |
4206 | ||
4207 | ||
4208 | static int | |
4209 | bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) | |
4210 | { | |
b491edd5 AV |
4211 | u32 cmd; |
4212 | __be32 val32; | |
b6016b76 MC |
4213 | int j; |
4214 | ||
4215 | /* Build the command word. */ | |
4216 | cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; | |
4217 | ||
e30372c9 MC |
4218 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
4219 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
4220 | offset = ((offset / bp->flash_info->page_size) << |
4221 | bp->flash_info->page_bits) + | |
4222 | (offset % bp->flash_info->page_size); | |
4223 | } | |
4224 | ||
4225 | /* Need to clear DONE bit separately. */ | |
4226 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
4227 | ||
4228 | memcpy(&val32, val, 4); | |
b6016b76 MC |
4229 | |
4230 | /* Write the data. */ | |
b491edd5 | 4231 | REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); |
b6016b76 MC |
4232 | |
4233 | /* Address of the NVRAM to write to. */ | |
4234 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
4235 | ||
4236 | /* Issue the write command. */ | |
4237 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
4238 | ||
4239 | /* Wait for completion. */ | |
4240 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4241 | udelay(5); | |
4242 | ||
4243 | if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) | |
4244 | break; | |
4245 | } | |
4246 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4247 | return -EBUSY; | |
4248 | ||
4249 | return 0; | |
4250 | } | |
4251 | ||
4252 | static int | |
4253 | bnx2_init_nvram(struct bnx2 *bp) | |
4254 | { | |
4255 | u32 val; | |
e30372c9 | 4256 | int j, entry_count, rc = 0; |
0ced9d01 | 4257 | const struct flash_spec *flash; |
b6016b76 | 4258 | |
e30372c9 MC |
4259 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4260 | bp->flash_info = &flash_5709; | |
4261 | goto get_flash_size; | |
4262 | } | |
4263 | ||
b6016b76 MC |
4264 | /* Determine the selected interface. */ |
4265 | val = REG_RD(bp, BNX2_NVM_CFG1); | |
4266 | ||
ff8ac609 | 4267 | entry_count = ARRAY_SIZE(flash_table); |
b6016b76 | 4268 | |
b6016b76 MC |
4269 | if (val & 0x40000000) { |
4270 | ||
4271 | /* Flash interface has been reconfigured */ | |
4272 | for (j = 0, flash = &flash_table[0]; j < entry_count; | |
37137709 MC |
4273 | j++, flash++) { |
4274 | if ((val & FLASH_BACKUP_STRAP_MASK) == | |
4275 | (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { | |
b6016b76 MC |
4276 | bp->flash_info = flash; |
4277 | break; | |
4278 | } | |
4279 | } | |
4280 | } | |
4281 | else { | |
37137709 | 4282 | u32 mask; |
b6016b76 MC |
4283 | /* Not yet been reconfigured */ |
4284 | ||
37137709 MC |
4285 | if (val & (1 << 23)) |
4286 | mask = FLASH_BACKUP_STRAP_MASK; | |
4287 | else | |
4288 | mask = FLASH_STRAP_MASK; | |
4289 | ||
b6016b76 MC |
4290 | for (j = 0, flash = &flash_table[0]; j < entry_count; |
4291 | j++, flash++) { | |
4292 | ||
37137709 | 4293 | if ((val & mask) == (flash->strapping & mask)) { |
b6016b76 MC |
4294 | bp->flash_info = flash; |
4295 | ||
4296 | /* Request access to the flash interface. */ | |
4297 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4298 | return rc; | |
4299 | ||
4300 | /* Enable access to flash interface */ | |
4301 | bnx2_enable_nvram_access(bp); | |
4302 | ||
4303 | /* Reconfigure the flash interface */ | |
4304 | REG_WR(bp, BNX2_NVM_CFG1, flash->config1); | |
4305 | REG_WR(bp, BNX2_NVM_CFG2, flash->config2); | |
4306 | REG_WR(bp, BNX2_NVM_CFG3, flash->config3); | |
4307 | REG_WR(bp, BNX2_NVM_WRITE1, flash->write1); | |
4308 | ||
4309 | /* Disable access to flash interface */ | |
4310 | bnx2_disable_nvram_access(bp); | |
4311 | bnx2_release_nvram_lock(bp); | |
4312 | ||
4313 | break; | |
4314 | } | |
4315 | } | |
4316 | } /* if (val & 0x40000000) */ | |
4317 | ||
4318 | if (j == entry_count) { | |
4319 | bp->flash_info = NULL; | |
2f23c523 | 4320 | printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n"); |
1122db71 | 4321 | return -ENODEV; |
b6016b76 MC |
4322 | } |
4323 | ||
e30372c9 | 4324 | get_flash_size: |
2726d6e1 | 4325 | val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); |
1122db71 MC |
4326 | val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; |
4327 | if (val) | |
4328 | bp->flash_size = val; | |
4329 | else | |
4330 | bp->flash_size = bp->flash_info->total_size; | |
4331 | ||
b6016b76 MC |
4332 | return rc; |
4333 | } | |
4334 | ||
4335 | static int | |
4336 | bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, | |
4337 | int buf_size) | |
4338 | { | |
4339 | int rc = 0; | |
4340 | u32 cmd_flags, offset32, len32, extra; | |
4341 | ||
4342 | if (buf_size == 0) | |
4343 | return 0; | |
4344 | ||
4345 | /* Request access to the flash interface. */ | |
4346 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4347 | return rc; | |
4348 | ||
4349 | /* Enable access to flash interface */ | |
4350 | bnx2_enable_nvram_access(bp); | |
4351 | ||
4352 | len32 = buf_size; | |
4353 | offset32 = offset; | |
4354 | extra = 0; | |
4355 | ||
4356 | cmd_flags = 0; | |
4357 | ||
4358 | if (offset32 & 3) { | |
4359 | u8 buf[4]; | |
4360 | u32 pre_len; | |
4361 | ||
4362 | offset32 &= ~3; | |
4363 | pre_len = 4 - (offset & 3); | |
4364 | ||
4365 | if (pre_len >= len32) { | |
4366 | pre_len = len32; | |
4367 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
4368 | BNX2_NVM_COMMAND_LAST; | |
4369 | } | |
4370 | else { | |
4371 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
4372 | } | |
4373 | ||
4374 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4375 | ||
4376 | if (rc) | |
4377 | return rc; | |
4378 | ||
4379 | memcpy(ret_buf, buf + (offset & 3), pre_len); | |
4380 | ||
4381 | offset32 += 4; | |
4382 | ret_buf += pre_len; | |
4383 | len32 -= pre_len; | |
4384 | } | |
4385 | if (len32 & 3) { | |
4386 | extra = 4 - (len32 & 3); | |
4387 | len32 = (len32 + 4) & ~3; | |
4388 | } | |
4389 | ||
4390 | if (len32 == 4) { | |
4391 | u8 buf[4]; | |
4392 | ||
4393 | if (cmd_flags) | |
4394 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4395 | else | |
4396 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
4397 | BNX2_NVM_COMMAND_LAST; | |
4398 | ||
4399 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4400 | ||
4401 | memcpy(ret_buf, buf, 4 - extra); | |
4402 | } | |
4403 | else if (len32 > 0) { | |
4404 | u8 buf[4]; | |
4405 | ||
4406 | /* Read the first word. */ | |
4407 | if (cmd_flags) | |
4408 | cmd_flags = 0; | |
4409 | else | |
4410 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
4411 | ||
4412 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); | |
4413 | ||
4414 | /* Advance to the next dword. */ | |
4415 | offset32 += 4; | |
4416 | ret_buf += 4; | |
4417 | len32 -= 4; | |
4418 | ||
4419 | while (len32 > 4 && rc == 0) { | |
4420 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); | |
4421 | ||
4422 | /* Advance to the next dword. */ | |
4423 | offset32 += 4; | |
4424 | ret_buf += 4; | |
4425 | len32 -= 4; | |
4426 | } | |
4427 | ||
4428 | if (rc) | |
4429 | return rc; | |
4430 | ||
4431 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4432 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4433 | ||
4434 | memcpy(ret_buf, buf, 4 - extra); | |
4435 | } | |
4436 | ||
4437 | /* Disable access to flash interface */ | |
4438 | bnx2_disable_nvram_access(bp); | |
4439 | ||
4440 | bnx2_release_nvram_lock(bp); | |
4441 | ||
4442 | return rc; | |
4443 | } | |
4444 | ||
4445 | static int | |
4446 | bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | |
4447 | int buf_size) | |
4448 | { | |
4449 | u32 written, offset32, len32; | |
e6be763f | 4450 | u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; |
b6016b76 MC |
4451 | int rc = 0; |
4452 | int align_start, align_end; | |
4453 | ||
4454 | buf = data_buf; | |
4455 | offset32 = offset; | |
4456 | len32 = buf_size; | |
4457 | align_start = align_end = 0; | |
4458 | ||
4459 | if ((align_start = (offset32 & 3))) { | |
4460 | offset32 &= ~3; | |
c873879c MC |
4461 | len32 += align_start; |
4462 | if (len32 < 4) | |
4463 | len32 = 4; | |
b6016b76 MC |
4464 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) |
4465 | return rc; | |
4466 | } | |
4467 | ||
4468 | if (len32 & 3) { | |
c873879c MC |
4469 | align_end = 4 - (len32 & 3); |
4470 | len32 += align_end; | |
4471 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) | |
4472 | return rc; | |
b6016b76 MC |
4473 | } |
4474 | ||
4475 | if (align_start || align_end) { | |
e6be763f MC |
4476 | align_buf = kmalloc(len32, GFP_KERNEL); |
4477 | if (align_buf == NULL) | |
b6016b76 MC |
4478 | return -ENOMEM; |
4479 | if (align_start) { | |
e6be763f | 4480 | memcpy(align_buf, start, 4); |
b6016b76 MC |
4481 | } |
4482 | if (align_end) { | |
e6be763f | 4483 | memcpy(align_buf + len32 - 4, end, 4); |
b6016b76 | 4484 | } |
e6be763f MC |
4485 | memcpy(align_buf + align_start, data_buf, buf_size); |
4486 | buf = align_buf; | |
b6016b76 MC |
4487 | } |
4488 | ||
e30372c9 | 4489 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
ae181bc4 MC |
4490 | flash_buffer = kmalloc(264, GFP_KERNEL); |
4491 | if (flash_buffer == NULL) { | |
4492 | rc = -ENOMEM; | |
4493 | goto nvram_write_end; | |
4494 | } | |
4495 | } | |
4496 | ||
b6016b76 MC |
4497 | written = 0; |
4498 | while ((written < len32) && (rc == 0)) { | |
4499 | u32 page_start, page_end, data_start, data_end; | |
4500 | u32 addr, cmd_flags; | |
4501 | int i; | |
b6016b76 MC |
4502 | |
4503 | /* Find the page_start addr */ | |
4504 | page_start = offset32 + written; | |
4505 | page_start -= (page_start % bp->flash_info->page_size); | |
4506 | /* Find the page_end addr */ | |
4507 | page_end = page_start + bp->flash_info->page_size; | |
4508 | /* Find the data_start addr */ | |
4509 | data_start = (written == 0) ? offset32 : page_start; | |
4510 | /* Find the data_end addr */ | |
6aa20a22 | 4511 | data_end = (page_end > offset32 + len32) ? |
b6016b76 MC |
4512 | (offset32 + len32) : page_end; |
4513 | ||
4514 | /* Request access to the flash interface. */ | |
4515 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4516 | goto nvram_write_end; | |
4517 | ||
4518 | /* Enable access to flash interface */ | |
4519 | bnx2_enable_nvram_access(bp); | |
4520 | ||
4521 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
e30372c9 | 4522 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
4523 | int j; |
4524 | ||
4525 | /* Read the whole page into the buffer | |
4526 | * (non-buffer flash only) */ | |
4527 | for (j = 0; j < bp->flash_info->page_size; j += 4) { | |
4528 | if (j == (bp->flash_info->page_size - 4)) { | |
4529 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
4530 | } | |
4531 | rc = bnx2_nvram_read_dword(bp, | |
6aa20a22 JG |
4532 | page_start + j, |
4533 | &flash_buffer[j], | |
b6016b76 MC |
4534 | cmd_flags); |
4535 | ||
4536 | if (rc) | |
4537 | goto nvram_write_end; | |
4538 | ||
4539 | cmd_flags = 0; | |
4540 | } | |
4541 | } | |
4542 | ||
4543 | /* Enable writes to flash interface (unlock write-protect) */ | |
4544 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) | |
4545 | goto nvram_write_end; | |
4546 | ||
b6016b76 MC |
4547 | /* Loop to write back the buffer data from page_start to |
4548 | * data_start */ | |
4549 | i = 0; | |
e30372c9 | 4550 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
c873879c MC |
4551 | /* Erase the page */ |
4552 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | |
4553 | goto nvram_write_end; | |
4554 | ||
4555 | /* Re-enable the write again for the actual write */ | |
4556 | bnx2_enable_nvram_write(bp); | |
4557 | ||
b6016b76 MC |
4558 | for (addr = page_start; addr < data_start; |
4559 | addr += 4, i += 4) { | |
6aa20a22 | 4560 | |
b6016b76 MC |
4561 | rc = bnx2_nvram_write_dword(bp, addr, |
4562 | &flash_buffer[i], cmd_flags); | |
4563 | ||
4564 | if (rc != 0) | |
4565 | goto nvram_write_end; | |
4566 | ||
4567 | cmd_flags = 0; | |
4568 | } | |
4569 | } | |
4570 | ||
4571 | /* Loop to write the new data from data_start to data_end */ | |
bae25761 | 4572 | for (addr = data_start; addr < data_end; addr += 4, i += 4) { |
b6016b76 | 4573 | if ((addr == page_end - 4) || |
e30372c9 | 4574 | ((bp->flash_info->flags & BNX2_NV_BUFFERED) && |
b6016b76 MC |
4575 | (addr == data_end - 4))) { |
4576 | ||
4577 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
4578 | } | |
4579 | rc = bnx2_nvram_write_dword(bp, addr, buf, | |
4580 | cmd_flags); | |
4581 | ||
4582 | if (rc != 0) | |
4583 | goto nvram_write_end; | |
4584 | ||
4585 | cmd_flags = 0; | |
4586 | buf += 4; | |
4587 | } | |
4588 | ||
4589 | /* Loop to write back the buffer data from data_end | |
4590 | * to page_end */ | |
e30372c9 | 4591 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
4592 | for (addr = data_end; addr < page_end; |
4593 | addr += 4, i += 4) { | |
6aa20a22 | 4594 | |
b6016b76 MC |
4595 | if (addr == page_end-4) { |
4596 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4597 | } | |
4598 | rc = bnx2_nvram_write_dword(bp, addr, | |
4599 | &flash_buffer[i], cmd_flags); | |
4600 | ||
4601 | if (rc != 0) | |
4602 | goto nvram_write_end; | |
4603 | ||
4604 | cmd_flags = 0; | |
4605 | } | |
4606 | } | |
4607 | ||
4608 | /* Disable writes to flash interface (lock write-protect) */ | |
4609 | bnx2_disable_nvram_write(bp); | |
4610 | ||
4611 | /* Disable access to flash interface */ | |
4612 | bnx2_disable_nvram_access(bp); | |
4613 | bnx2_release_nvram_lock(bp); | |
4614 | ||
4615 | /* Increment written */ | |
4616 | written += data_end - data_start; | |
4617 | } | |
4618 | ||
4619 | nvram_write_end: | |
e6be763f MC |
4620 | kfree(flash_buffer); |
4621 | kfree(align_buf); | |
b6016b76 MC |
4622 | return rc; |
4623 | } | |
4624 | ||
0d8a6571 | 4625 | static void |
7c62e83b | 4626 | bnx2_init_fw_cap(struct bnx2 *bp) |
0d8a6571 | 4627 | { |
7c62e83b | 4628 | u32 val, sig = 0; |
0d8a6571 | 4629 | |
583c28e5 | 4630 | bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
7c62e83b MC |
4631 | bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; |
4632 | ||
4633 | if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) | |
4634 | bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; | |
0d8a6571 | 4635 | |
2726d6e1 | 4636 | val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); |
0d8a6571 MC |
4637 | if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) |
4638 | return; | |
4639 | ||
7c62e83b MC |
4640 | if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) { |
4641 | bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; | |
4642 | sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN; | |
4643 | } | |
4644 | ||
4645 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && | |
4646 | (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) { | |
4647 | u32 link; | |
4648 | ||
583c28e5 | 4649 | bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
0d8a6571 | 4650 | |
7c62e83b MC |
4651 | link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
4652 | if (link & BNX2_LINK_STATUS_SERDES_LINK) | |
0d8a6571 MC |
4653 | bp->phy_port = PORT_FIBRE; |
4654 | else | |
4655 | bp->phy_port = PORT_TP; | |
489310a4 | 4656 | |
7c62e83b MC |
4657 | sig |= BNX2_DRV_ACK_CAP_SIGNATURE | |
4658 | BNX2_FW_CAP_REMOTE_PHY_CAPABLE; | |
0d8a6571 | 4659 | } |
7c62e83b MC |
4660 | |
4661 | if (netif_running(bp->dev) && sig) | |
4662 | bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); | |
0d8a6571 MC |
4663 | } |
4664 | ||
b4b36042 MC |
4665 | static void |
4666 | bnx2_setup_msix_tbl(struct bnx2 *bp) | |
4667 | { | |
4668 | REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); | |
4669 | ||
4670 | REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); | |
4671 | REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); | |
4672 | } | |
4673 | ||
b6016b76 MC |
4674 | static int |
4675 | bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |
4676 | { | |
4677 | u32 val; | |
4678 | int i, rc = 0; | |
489310a4 | 4679 | u8 old_port; |
b6016b76 MC |
4680 | |
4681 | /* Wait for the current PCI transaction to complete before | |
4682 | * issuing a reset. */ | |
4683 | REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, | |
4684 | BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | | |
4685 | BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | | |
4686 | BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | | |
4687 | BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); | |
4688 | val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); | |
4689 | udelay(5); | |
4690 | ||
b090ae2b | 4691 | /* Wait for the firmware to tell us it is ok to issue a reset. */ |
a2f13890 | 4692 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1); |
b090ae2b | 4693 | |
b6016b76 MC |
4694 | /* Deposit a driver reset signature so the firmware knows that |
4695 | * this is a soft reset. */ | |
2726d6e1 MC |
4696 | bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, |
4697 | BNX2_DRV_RESET_SIGNATURE_MAGIC); | |
b6016b76 | 4698 | |
b6016b76 MC |
4699 | /* Do a dummy read to force the chip to complete all current transaction |
4700 | * before we issue a reset. */ | |
4701 | val = REG_RD(bp, BNX2_MISC_ID); | |
4702 | ||
234754d5 MC |
4703 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4704 | REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); | |
4705 | REG_RD(bp, BNX2_MISC_COMMAND); | |
4706 | udelay(5); | |
b6016b76 | 4707 | |
234754d5 MC |
4708 | val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | |
4709 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
b6016b76 | 4710 | |
234754d5 | 4711 | pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val); |
b6016b76 | 4712 | |
234754d5 MC |
4713 | } else { |
4714 | val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4715 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
4716 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
4717 | ||
4718 | /* Chip reset. */ | |
4719 | REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); | |
4720 | ||
594a9dfa MC |
4721 | /* Reading back any register after chip reset will hang the |
4722 | * bus on 5706 A0 and A1. The msleep below provides plenty | |
4723 | * of margin for write posting. | |
4724 | */ | |
234754d5 | 4725 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || |
8e545881 AV |
4726 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) |
4727 | msleep(20); | |
b6016b76 | 4728 | |
234754d5 MC |
4729 | /* Reset takes approximate 30 usec */ |
4730 | for (i = 0; i < 10; i++) { | |
4731 | val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); | |
4732 | if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4733 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) | |
4734 | break; | |
4735 | udelay(10); | |
4736 | } | |
4737 | ||
4738 | if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4739 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { | |
4740 | printk(KERN_ERR PFX "Chip reset did not complete\n"); | |
4741 | return -EBUSY; | |
4742 | } | |
b6016b76 MC |
4743 | } |
4744 | ||
4745 | /* Make sure byte swapping is properly configured. */ | |
4746 | val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); | |
4747 | if (val != 0x01020304) { | |
4748 | printk(KERN_ERR PFX "Chip not in correct endian mode\n"); | |
4749 | return -ENODEV; | |
4750 | } | |
4751 | ||
b6016b76 | 4752 | /* Wait for the firmware to finish its initialization. */ |
a2f13890 | 4753 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); |
b090ae2b MC |
4754 | if (rc) |
4755 | return rc; | |
b6016b76 | 4756 | |
0d8a6571 | 4757 | spin_lock_bh(&bp->phy_lock); |
489310a4 | 4758 | old_port = bp->phy_port; |
7c62e83b | 4759 | bnx2_init_fw_cap(bp); |
583c28e5 MC |
4760 | if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && |
4761 | old_port != bp->phy_port) | |
0d8a6571 MC |
4762 | bnx2_set_default_remote_link(bp); |
4763 | spin_unlock_bh(&bp->phy_lock); | |
4764 | ||
b6016b76 MC |
4765 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { |
4766 | /* Adjust the voltage regular to two steps lower. The default | |
4767 | * of this register is 0x0000000e. */ | |
4768 | REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); | |
4769 | ||
4770 | /* Remove bad rbuf memory from the free pool. */ | |
4771 | rc = bnx2_alloc_bad_rbuf(bp); | |
4772 | } | |
4773 | ||
f86e82fb | 4774 | if (bp->flags & BNX2_FLAG_USING_MSIX) |
b4b36042 MC |
4775 | bnx2_setup_msix_tbl(bp); |
4776 | ||
b6016b76 MC |
4777 | return rc; |
4778 | } | |
4779 | ||
4780 | static int | |
4781 | bnx2_init_chip(struct bnx2 *bp) | |
4782 | { | |
d8026d93 | 4783 | u32 val, mtu; |
b4b36042 | 4784 | int rc, i; |
b6016b76 MC |
4785 | |
4786 | /* Make sure the interrupt is not active. */ | |
4787 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
4788 | ||
4789 | val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | | |
4790 | BNX2_DMA_CONFIG_DATA_WORD_SWAP | | |
4791 | #ifdef __BIG_ENDIAN | |
6aa20a22 | 4792 | BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | |
b6016b76 | 4793 | #endif |
6aa20a22 | 4794 | BNX2_DMA_CONFIG_CNTL_WORD_SWAP | |
b6016b76 MC |
4795 | DMA_READ_CHANS << 12 | |
4796 | DMA_WRITE_CHANS << 16; | |
4797 | ||
4798 | val |= (0x2 << 20) | (1 << 11); | |
4799 | ||
f86e82fb | 4800 | if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) |
b6016b76 MC |
4801 | val |= (1 << 23); |
4802 | ||
4803 | if ((CHIP_NUM(bp) == CHIP_NUM_5706) && | |
f86e82fb | 4804 | (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX)) |
b6016b76 MC |
4805 | val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; |
4806 | ||
4807 | REG_WR(bp, BNX2_DMA_CONFIG, val); | |
4808 | ||
4809 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
4810 | val = REG_RD(bp, BNX2_TDMA_CONFIG); | |
4811 | val |= BNX2_TDMA_CONFIG_ONE_DMA; | |
4812 | REG_WR(bp, BNX2_TDMA_CONFIG, val); | |
4813 | } | |
4814 | ||
f86e82fb | 4815 | if (bp->flags & BNX2_FLAG_PCIX) { |
b6016b76 MC |
4816 | u16 val16; |
4817 | ||
4818 | pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4819 | &val16); | |
4820 | pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4821 | val16 & ~PCI_X_CMD_ERO); | |
4822 | } | |
4823 | ||
4824 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
4825 | BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | | |
4826 | BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | | |
4827 | BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); | |
4828 | ||
4829 | /* Initialize context mapping and zero out the quick contexts. The | |
4830 | * context block must have already been enabled. */ | |
641bdcd5 MC |
4831 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4832 | rc = bnx2_init_5709_context(bp); | |
4833 | if (rc) | |
4834 | return rc; | |
4835 | } else | |
59b47d8a | 4836 | bnx2_init_context(bp); |
b6016b76 | 4837 | |
fba9fe91 MC |
4838 | if ((rc = bnx2_init_cpus(bp)) != 0) |
4839 | return rc; | |
4840 | ||
b6016b76 MC |
4841 | bnx2_init_nvram(bp); |
4842 | ||
5fcaed01 | 4843 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 MC |
4844 | |
4845 | val = REG_RD(bp, BNX2_MQ_CONFIG); | |
4846 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; | |
4847 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; | |
4edd473f MC |
4848 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4849 | val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; | |
4850 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
4851 | val |= BNX2_MQ_CONFIG_HALT_DIS; | |
4852 | } | |
68c9f75a | 4853 | |
b6016b76 MC |
4854 | REG_WR(bp, BNX2_MQ_CONFIG, val); |
4855 | ||
4856 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); | |
4857 | REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); | |
4858 | REG_WR(bp, BNX2_MQ_KNL_WIND_END, val); | |
4859 | ||
4860 | val = (BCM_PAGE_BITS - 8) << 24; | |
4861 | REG_WR(bp, BNX2_RV2P_CONFIG, val); | |
4862 | ||
4863 | /* Configure page size. */ | |
4864 | val = REG_RD(bp, BNX2_TBDR_CONFIG); | |
4865 | val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; | |
4866 | val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; | |
4867 | REG_WR(bp, BNX2_TBDR_CONFIG, val); | |
4868 | ||
4869 | val = bp->mac_addr[0] + | |
4870 | (bp->mac_addr[1] << 8) + | |
4871 | (bp->mac_addr[2] << 16) + | |
4872 | bp->mac_addr[3] + | |
4873 | (bp->mac_addr[4] << 8) + | |
4874 | (bp->mac_addr[5] << 16); | |
4875 | REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); | |
4876 | ||
4877 | /* Program the MTU. Also include 4 bytes for CRC32. */ | |
d8026d93 MC |
4878 | mtu = bp->dev->mtu; |
4879 | val = mtu + ETH_HLEN + ETH_FCS_LEN; | |
b6016b76 MC |
4880 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) |
4881 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; | |
4882 | REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); | |
4883 | ||
d8026d93 MC |
4884 | if (mtu < 1500) |
4885 | mtu = 1500; | |
4886 | ||
4887 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); | |
4888 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); | |
4889 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); | |
4890 | ||
155d5561 | 4891 | memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); |
b4b36042 MC |
4892 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) |
4893 | bp->bnx2_napi[i].last_status_idx = 0; | |
4894 | ||
efba0180 MC |
4895 | bp->idle_chk_status_idx = 0xffff; |
4896 | ||
b6016b76 MC |
4897 | bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; |
4898 | ||
4899 | /* Set up how to generate a link change interrupt. */ | |
4900 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); | |
4901 | ||
4902 | REG_WR(bp, BNX2_HC_STATUS_ADDR_L, | |
4903 | (u64) bp->status_blk_mapping & 0xffffffff); | |
4904 | REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); | |
4905 | ||
4906 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L, | |
4907 | (u64) bp->stats_blk_mapping & 0xffffffff); | |
4908 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, | |
4909 | (u64) bp->stats_blk_mapping >> 32); | |
4910 | ||
6aa20a22 | 4911 | REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, |
b6016b76 MC |
4912 | (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); |
4913 | ||
4914 | REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, | |
4915 | (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); | |
4916 | ||
4917 | REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, | |
4918 | (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); | |
4919 | ||
4920 | REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); | |
4921 | ||
4922 | REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); | |
4923 | ||
4924 | REG_WR(bp, BNX2_HC_COM_TICKS, | |
4925 | (bp->com_ticks_int << 16) | bp->com_ticks); | |
4926 | ||
4927 | REG_WR(bp, BNX2_HC_CMD_TICKS, | |
4928 | (bp->cmd_ticks_int << 16) | bp->cmd_ticks); | |
4929 | ||
61d9e3fa | 4930 | if (bp->flags & BNX2_FLAG_BROKEN_STATS) |
02537b06 MC |
4931 | REG_WR(bp, BNX2_HC_STATS_TICKS, 0); |
4932 | else | |
7ea6920e | 4933 | REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); |
b6016b76 MC |
4934 | REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ |
4935 | ||
4936 | if (CHIP_ID(bp) == CHIP_ID_5706_A1) | |
8e6a72c4 | 4937 | val = BNX2_HC_CONFIG_COLLECT_STATS; |
b6016b76 | 4938 | else { |
8e6a72c4 MC |
4939 | val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | |
4940 | BNX2_HC_CONFIG_COLLECT_STATS; | |
b6016b76 MC |
4941 | } |
4942 | ||
efde73a3 | 4943 | if (bp->flags & BNX2_FLAG_USING_MSIX) { |
c76c0475 MC |
4944 | REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, |
4945 | BNX2_HC_MSIX_BIT_VECTOR_VAL); | |
4946 | ||
5e9ad9e1 MC |
4947 | val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; |
4948 | } | |
4949 | ||
4950 | if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) | |
cf7474a6 | 4951 | val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; |
5e9ad9e1 MC |
4952 | |
4953 | REG_WR(bp, BNX2_HC_CONFIG, val); | |
4954 | ||
4955 | for (i = 1; i < bp->irq_nvecs; i++) { | |
4956 | u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + | |
4957 | BNX2_HC_SB_CONFIG_1; | |
4958 | ||
6f743ca0 | 4959 | REG_WR(bp, base, |
c76c0475 | 4960 | BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | |
5e9ad9e1 | 4961 | BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | |
c76c0475 MC |
4962 | BNX2_HC_SB_CONFIG_1_ONE_SHOT); |
4963 | ||
6f743ca0 | 4964 | REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, |
c76c0475 MC |
4965 | (bp->tx_quick_cons_trip_int << 16) | |
4966 | bp->tx_quick_cons_trip); | |
4967 | ||
6f743ca0 | 4968 | REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF, |
c76c0475 MC |
4969 | (bp->tx_ticks_int << 16) | bp->tx_ticks); |
4970 | ||
5e9ad9e1 MC |
4971 | REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, |
4972 | (bp->rx_quick_cons_trip_int << 16) | | |
4973 | bp->rx_quick_cons_trip); | |
8e6a72c4 | 4974 | |
5e9ad9e1 MC |
4975 | REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF, |
4976 | (bp->rx_ticks_int << 16) | bp->rx_ticks); | |
4977 | } | |
8e6a72c4 | 4978 | |
b6016b76 MC |
4979 | /* Clear internal stats counters. */ |
4980 | REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); | |
4981 | ||
da3e4fbe | 4982 | REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); |
b6016b76 MC |
4983 | |
4984 | /* Initialize the receive filter. */ | |
4985 | bnx2_set_rx_mode(bp->dev); | |
4986 | ||
0aa38df7 MC |
4987 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4988 | val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); | |
4989 | val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; | |
4990 | REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); | |
4991 | } | |
b090ae2b | 4992 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, |
a2f13890 | 4993 | 1, 0); |
b6016b76 | 4994 | |
df149d70 | 4995 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); |
b6016b76 MC |
4996 | REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); |
4997 | ||
4998 | udelay(20); | |
4999 | ||
bf5295bb MC |
5000 | bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND); |
5001 | ||
b090ae2b | 5002 | return rc; |
b6016b76 MC |
5003 | } |
5004 | ||
c76c0475 MC |
5005 | static void |
5006 | bnx2_clear_ring_states(struct bnx2 *bp) | |
5007 | { | |
5008 | struct bnx2_napi *bnapi; | |
35e9010b | 5009 | struct bnx2_tx_ring_info *txr; |
bb4f98ab | 5010 | struct bnx2_rx_ring_info *rxr; |
c76c0475 MC |
5011 | int i; |
5012 | ||
5013 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { | |
5014 | bnapi = &bp->bnx2_napi[i]; | |
35e9010b | 5015 | txr = &bnapi->tx_ring; |
bb4f98ab | 5016 | rxr = &bnapi->rx_ring; |
c76c0475 | 5017 | |
35e9010b MC |
5018 | txr->tx_cons = 0; |
5019 | txr->hw_tx_cons = 0; | |
bb4f98ab MC |
5020 | rxr->rx_prod_bseq = 0; |
5021 | rxr->rx_prod = 0; | |
5022 | rxr->rx_cons = 0; | |
5023 | rxr->rx_pg_prod = 0; | |
5024 | rxr->rx_pg_cons = 0; | |
c76c0475 MC |
5025 | } |
5026 | } | |
5027 | ||
59b47d8a | 5028 | static void |
35e9010b | 5029 | bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) |
59b47d8a MC |
5030 | { |
5031 | u32 val, offset0, offset1, offset2, offset3; | |
62a8313c | 5032 | u32 cid_addr = GET_CID_ADDR(cid); |
59b47d8a MC |
5033 | |
5034 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
5035 | offset0 = BNX2_L2CTX_TYPE_XI; | |
5036 | offset1 = BNX2_L2CTX_CMD_TYPE_XI; | |
5037 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; | |
5038 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; | |
5039 | } else { | |
5040 | offset0 = BNX2_L2CTX_TYPE; | |
5041 | offset1 = BNX2_L2CTX_CMD_TYPE; | |
5042 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; | |
5043 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; | |
5044 | } | |
5045 | val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; | |
62a8313c | 5046 | bnx2_ctx_wr(bp, cid_addr, offset0, val); |
59b47d8a MC |
5047 | |
5048 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); | |
62a8313c | 5049 | bnx2_ctx_wr(bp, cid_addr, offset1, val); |
59b47d8a | 5050 | |
35e9010b | 5051 | val = (u64) txr->tx_desc_mapping >> 32; |
62a8313c | 5052 | bnx2_ctx_wr(bp, cid_addr, offset2, val); |
59b47d8a | 5053 | |
35e9010b | 5054 | val = (u64) txr->tx_desc_mapping & 0xffffffff; |
62a8313c | 5055 | bnx2_ctx_wr(bp, cid_addr, offset3, val); |
59b47d8a | 5056 | } |
b6016b76 MC |
5057 | |
5058 | static void | |
35e9010b | 5059 | bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) |
b6016b76 MC |
5060 | { |
5061 | struct tx_bd *txbd; | |
c76c0475 MC |
5062 | u32 cid = TX_CID; |
5063 | struct bnx2_napi *bnapi; | |
35e9010b | 5064 | struct bnx2_tx_ring_info *txr; |
c76c0475 | 5065 | |
35e9010b MC |
5066 | bnapi = &bp->bnx2_napi[ring_num]; |
5067 | txr = &bnapi->tx_ring; | |
5068 | ||
5069 | if (ring_num == 0) | |
5070 | cid = TX_CID; | |
5071 | else | |
5072 | cid = TX_TSS_CID + ring_num - 1; | |
b6016b76 | 5073 | |
2f8af120 MC |
5074 | bp->tx_wake_thresh = bp->tx_ring_size / 2; |
5075 | ||
35e9010b | 5076 | txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT]; |
6aa20a22 | 5077 | |
35e9010b MC |
5078 | txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; |
5079 | txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; | |
b6016b76 | 5080 | |
35e9010b MC |
5081 | txr->tx_prod = 0; |
5082 | txr->tx_prod_bseq = 0; | |
6aa20a22 | 5083 | |
35e9010b MC |
5084 | txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; |
5085 | txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; | |
b6016b76 | 5086 | |
35e9010b | 5087 | bnx2_init_tx_context(bp, cid, txr); |
b6016b76 MC |
5088 | } |
5089 | ||
5090 | static void | |
5d5d0015 MC |
5091 | bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size, |
5092 | int num_rings) | |
b6016b76 | 5093 | { |
b6016b76 | 5094 | int i; |
5d5d0015 | 5095 | struct rx_bd *rxbd; |
6aa20a22 | 5096 | |
5d5d0015 | 5097 | for (i = 0; i < num_rings; i++) { |
13daffa2 | 5098 | int j; |
b6016b76 | 5099 | |
5d5d0015 | 5100 | rxbd = &rx_ring[i][0]; |
13daffa2 | 5101 | for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) { |
5d5d0015 | 5102 | rxbd->rx_bd_len = buf_size; |
13daffa2 MC |
5103 | rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; |
5104 | } | |
5d5d0015 | 5105 | if (i == (num_rings - 1)) |
13daffa2 MC |
5106 | j = 0; |
5107 | else | |
5108 | j = i + 1; | |
5d5d0015 MC |
5109 | rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; |
5110 | rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; | |
13daffa2 | 5111 | } |
5d5d0015 MC |
5112 | } |
5113 | ||
5114 | static void | |
bb4f98ab | 5115 | bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) |
5d5d0015 MC |
5116 | { |
5117 | int i; | |
5118 | u16 prod, ring_prod; | |
bb4f98ab MC |
5119 | u32 cid, rx_cid_addr, val; |
5120 | struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; | |
5121 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
5122 | ||
5123 | if (ring_num == 0) | |
5124 | cid = RX_CID; | |
5125 | else | |
5126 | cid = RX_RSS_CID + ring_num - 1; | |
5127 | ||
5128 | rx_cid_addr = GET_CID_ADDR(cid); | |
5d5d0015 | 5129 | |
bb4f98ab | 5130 | bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, |
5d5d0015 MC |
5131 | bp->rx_buf_use_size, bp->rx_max_ring); |
5132 | ||
bb4f98ab | 5133 | bnx2_init_rx_context(bp, cid); |
83e3fc89 MC |
5134 | |
5135 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
5136 | val = REG_RD(bp, BNX2_MQ_MAP_L2_5); | |
5137 | REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); | |
5138 | } | |
5139 | ||
62a8313c | 5140 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); |
47bf4246 | 5141 | if (bp->rx_pg_ring_size) { |
bb4f98ab MC |
5142 | bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, |
5143 | rxr->rx_pg_desc_mapping, | |
47bf4246 MC |
5144 | PAGE_SIZE, bp->rx_max_pg_ring); |
5145 | val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; | |
62a8313c MC |
5146 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); |
5147 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, | |
5e9ad9e1 | 5148 | BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); |
47bf4246 | 5149 | |
bb4f98ab | 5150 | val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; |
62a8313c | 5151 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); |
47bf4246 | 5152 | |
bb4f98ab | 5153 | val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; |
62a8313c | 5154 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); |
47bf4246 MC |
5155 | |
5156 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
5157 | REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); | |
5158 | } | |
b6016b76 | 5159 | |
bb4f98ab | 5160 | val = (u64) rxr->rx_desc_mapping[0] >> 32; |
62a8313c | 5161 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); |
b6016b76 | 5162 | |
bb4f98ab | 5163 | val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; |
62a8313c | 5164 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); |
b6016b76 | 5165 | |
bb4f98ab | 5166 | ring_prod = prod = rxr->rx_pg_prod; |
47bf4246 | 5167 | for (i = 0; i < bp->rx_pg_ring_size; i++) { |
b929e53c MC |
5168 | if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) { |
5169 | printk(KERN_WARNING PFX "%s: init'ed rx page ring %d " | |
5170 | "with %d/%d pages only\n", | |
5171 | bp->dev->name, ring_num, i, bp->rx_pg_ring_size); | |
47bf4246 | 5172 | break; |
b929e53c | 5173 | } |
47bf4246 MC |
5174 | prod = NEXT_RX_BD(prod); |
5175 | ring_prod = RX_PG_RING_IDX(prod); | |
5176 | } | |
bb4f98ab | 5177 | rxr->rx_pg_prod = prod; |
47bf4246 | 5178 | |
bb4f98ab | 5179 | ring_prod = prod = rxr->rx_prod; |
236b6394 | 5180 | for (i = 0; i < bp->rx_ring_size; i++) { |
b929e53c MC |
5181 | if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) { |
5182 | printk(KERN_WARNING PFX "%s: init'ed rx ring %d with " | |
5183 | "%d/%d skbs only\n", | |
5184 | bp->dev->name, ring_num, i, bp->rx_ring_size); | |
b6016b76 | 5185 | break; |
b929e53c | 5186 | } |
b6016b76 MC |
5187 | prod = NEXT_RX_BD(prod); |
5188 | ring_prod = RX_RING_IDX(prod); | |
5189 | } | |
bb4f98ab | 5190 | rxr->rx_prod = prod; |
b6016b76 | 5191 | |
bb4f98ab MC |
5192 | rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; |
5193 | rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; | |
5194 | rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; | |
b6016b76 | 5195 | |
bb4f98ab MC |
5196 | REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); |
5197 | REG_WR16(bp, rxr->rx_bidx_addr, prod); | |
5198 | ||
5199 | REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); | |
b6016b76 MC |
5200 | } |
5201 | ||
35e9010b MC |
5202 | static void |
5203 | bnx2_init_all_rings(struct bnx2 *bp) | |
5204 | { | |
5205 | int i; | |
5e9ad9e1 | 5206 | u32 val; |
35e9010b MC |
5207 | |
5208 | bnx2_clear_ring_states(bp); | |
5209 | ||
5210 | REG_WR(bp, BNX2_TSCH_TSS_CFG, 0); | |
5211 | for (i = 0; i < bp->num_tx_rings; i++) | |
5212 | bnx2_init_tx_ring(bp, i); | |
5213 | ||
5214 | if (bp->num_tx_rings > 1) | |
5215 | REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | | |
5216 | (TX_TSS_CID << 7)); | |
5217 | ||
5e9ad9e1 MC |
5218 | REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); |
5219 | bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); | |
5220 | ||
bb4f98ab MC |
5221 | for (i = 0; i < bp->num_rx_rings; i++) |
5222 | bnx2_init_rx_ring(bp, i); | |
5e9ad9e1 MC |
5223 | |
5224 | if (bp->num_rx_rings > 1) { | |
5225 | u32 tbl_32; | |
5226 | u8 *tbl = (u8 *) &tbl_32; | |
5227 | ||
5228 | bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, | |
5229 | BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES); | |
5230 | ||
5231 | for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { | |
5232 | tbl[i % 4] = i % (bp->num_rx_rings - 1); | |
5233 | if ((i % 4) == 3) | |
5234 | bnx2_reg_wr_ind(bp, | |
5235 | BNX2_RXP_SCRATCH_RSS_TBL + i, | |
5236 | cpu_to_be32(tbl_32)); | |
5237 | } | |
5238 | ||
5239 | val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | | |
5240 | BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; | |
5241 | ||
5242 | REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val); | |
5243 | ||
5244 | } | |
35e9010b MC |
5245 | } |
5246 | ||
5d5d0015 | 5247 | static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) |
13daffa2 | 5248 | { |
5d5d0015 | 5249 | u32 max, num_rings = 1; |
13daffa2 | 5250 | |
5d5d0015 MC |
5251 | while (ring_size > MAX_RX_DESC_CNT) { |
5252 | ring_size -= MAX_RX_DESC_CNT; | |
13daffa2 MC |
5253 | num_rings++; |
5254 | } | |
5255 | /* round to next power of 2 */ | |
5d5d0015 | 5256 | max = max_size; |
13daffa2 MC |
5257 | while ((max & num_rings) == 0) |
5258 | max >>= 1; | |
5259 | ||
5260 | if (num_rings != max) | |
5261 | max <<= 1; | |
5262 | ||
5d5d0015 MC |
5263 | return max; |
5264 | } | |
5265 | ||
5266 | static void | |
5267 | bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) | |
5268 | { | |
84eaa187 | 5269 | u32 rx_size, rx_space, jumbo_size; |
5d5d0015 MC |
5270 | |
5271 | /* 8 for CRC and VLAN */ | |
d89cb6af | 5272 | rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; |
5d5d0015 | 5273 | |
84eaa187 MC |
5274 | rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + |
5275 | sizeof(struct skb_shared_info); | |
5276 | ||
601d3d18 | 5277 | bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; |
47bf4246 MC |
5278 | bp->rx_pg_ring_size = 0; |
5279 | bp->rx_max_pg_ring = 0; | |
5280 | bp->rx_max_pg_ring_idx = 0; | |
f86e82fb | 5281 | if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { |
84eaa187 MC |
5282 | int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; |
5283 | ||
5284 | jumbo_size = size * pages; | |
5285 | if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT) | |
5286 | jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT; | |
5287 | ||
5288 | bp->rx_pg_ring_size = jumbo_size; | |
5289 | bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, | |
5290 | MAX_RX_PG_RINGS); | |
5291 | bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1; | |
601d3d18 | 5292 | rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; |
84eaa187 MC |
5293 | bp->rx_copy_thresh = 0; |
5294 | } | |
5d5d0015 MC |
5295 | |
5296 | bp->rx_buf_use_size = rx_size; | |
5297 | /* hw alignment */ | |
5298 | bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN; | |
d89cb6af | 5299 | bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; |
5d5d0015 MC |
5300 | bp->rx_ring_size = size; |
5301 | bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS); | |
13daffa2 MC |
5302 | bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1; |
5303 | } | |
5304 | ||
b6016b76 MC |
5305 | static void |
5306 | bnx2_free_tx_skbs(struct bnx2 *bp) | |
5307 | { | |
5308 | int i; | |
5309 | ||
35e9010b MC |
5310 | for (i = 0; i < bp->num_tx_rings; i++) { |
5311 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
5312 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
5313 | int j; | |
b6016b76 | 5314 | |
35e9010b | 5315 | if (txr->tx_buf_ring == NULL) |
b6016b76 | 5316 | continue; |
b6016b76 | 5317 | |
35e9010b | 5318 | for (j = 0; j < TX_DESC_CNT; ) { |
3d16af86 | 5319 | struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; |
35e9010b | 5320 | struct sk_buff *skb = tx_buf->skb; |
e95524a7 | 5321 | int k, last; |
35e9010b MC |
5322 | |
5323 | if (skb == NULL) { | |
5324 | j++; | |
5325 | continue; | |
5326 | } | |
5327 | ||
e95524a7 AD |
5328 | pci_unmap_single(bp->pdev, |
5329 | pci_unmap_addr(tx_buf, mapping), | |
5330 | skb_headlen(skb), | |
5331 | PCI_DMA_TODEVICE); | |
b6016b76 | 5332 | |
35e9010b | 5333 | tx_buf->skb = NULL; |
b6016b76 | 5334 | |
e95524a7 AD |
5335 | last = tx_buf->nr_frags; |
5336 | j++; | |
5337 | for (k = 0; k < last; k++, j++) { | |
5338 | tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)]; | |
5339 | pci_unmap_page(bp->pdev, | |
5340 | pci_unmap_addr(tx_buf, mapping), | |
5341 | skb_shinfo(skb)->frags[k].size, | |
5342 | PCI_DMA_TODEVICE); | |
5343 | } | |
35e9010b | 5344 | dev_kfree_skb(skb); |
b6016b76 | 5345 | } |
b6016b76 | 5346 | } |
b6016b76 MC |
5347 | } |
5348 | ||
5349 | static void | |
5350 | bnx2_free_rx_skbs(struct bnx2 *bp) | |
5351 | { | |
5352 | int i; | |
5353 | ||
bb4f98ab MC |
5354 | for (i = 0; i < bp->num_rx_rings; i++) { |
5355 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
5356 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
5357 | int j; | |
b6016b76 | 5358 | |
bb4f98ab MC |
5359 | if (rxr->rx_buf_ring == NULL) |
5360 | return; | |
b6016b76 | 5361 | |
bb4f98ab MC |
5362 | for (j = 0; j < bp->rx_max_ring_idx; j++) { |
5363 | struct sw_bd *rx_buf = &rxr->rx_buf_ring[j]; | |
5364 | struct sk_buff *skb = rx_buf->skb; | |
b6016b76 | 5365 | |
bb4f98ab MC |
5366 | if (skb == NULL) |
5367 | continue; | |
b6016b76 | 5368 | |
bb4f98ab MC |
5369 | pci_unmap_single(bp->pdev, |
5370 | pci_unmap_addr(rx_buf, mapping), | |
5371 | bp->rx_buf_use_size, | |
5372 | PCI_DMA_FROMDEVICE); | |
b6016b76 | 5373 | |
bb4f98ab MC |
5374 | rx_buf->skb = NULL; |
5375 | ||
5376 | dev_kfree_skb(skb); | |
5377 | } | |
5378 | for (j = 0; j < bp->rx_max_pg_ring_idx; j++) | |
5379 | bnx2_free_rx_page(bp, rxr, j); | |
b6016b76 MC |
5380 | } |
5381 | } | |
5382 | ||
5383 | static void | |
5384 | bnx2_free_skbs(struct bnx2 *bp) | |
5385 | { | |
5386 | bnx2_free_tx_skbs(bp); | |
5387 | bnx2_free_rx_skbs(bp); | |
5388 | } | |
5389 | ||
5390 | static int | |
5391 | bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) | |
5392 | { | |
5393 | int rc; | |
5394 | ||
5395 | rc = bnx2_reset_chip(bp, reset_code); | |
5396 | bnx2_free_skbs(bp); | |
5397 | if (rc) | |
5398 | return rc; | |
5399 | ||
fba9fe91 MC |
5400 | if ((rc = bnx2_init_chip(bp)) != 0) |
5401 | return rc; | |
5402 | ||
35e9010b | 5403 | bnx2_init_all_rings(bp); |
b6016b76 MC |
5404 | return 0; |
5405 | } | |
5406 | ||
5407 | static int | |
9a120bc5 | 5408 | bnx2_init_nic(struct bnx2 *bp, int reset_phy) |
b6016b76 MC |
5409 | { |
5410 | int rc; | |
5411 | ||
5412 | if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) | |
5413 | return rc; | |
5414 | ||
80be4434 | 5415 | spin_lock_bh(&bp->phy_lock); |
9a120bc5 | 5416 | bnx2_init_phy(bp, reset_phy); |
b6016b76 | 5417 | bnx2_set_link(bp); |
543a827d MC |
5418 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
5419 | bnx2_remote_phy_event(bp); | |
0d8a6571 | 5420 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
5421 | return 0; |
5422 | } | |
5423 | ||
74bf4ba3 MC |
5424 | static int |
5425 | bnx2_shutdown_chip(struct bnx2 *bp) | |
5426 | { | |
5427 | u32 reset_code; | |
5428 | ||
5429 | if (bp->flags & BNX2_FLAG_NO_WOL) | |
5430 | reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; | |
5431 | else if (bp->wol) | |
5432 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
5433 | else | |
5434 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
5435 | ||
5436 | return bnx2_reset_chip(bp, reset_code); | |
5437 | } | |
5438 | ||
b6016b76 MC |
5439 | static int |
5440 | bnx2_test_registers(struct bnx2 *bp) | |
5441 | { | |
5442 | int ret; | |
5bae30c9 | 5443 | int i, is_5709; |
f71e1309 | 5444 | static const struct { |
b6016b76 MC |
5445 | u16 offset; |
5446 | u16 flags; | |
5bae30c9 | 5447 | #define BNX2_FL_NOT_5709 1 |
b6016b76 MC |
5448 | u32 rw_mask; |
5449 | u32 ro_mask; | |
5450 | } reg_tbl[] = { | |
5451 | { 0x006c, 0, 0x00000000, 0x0000003f }, | |
5452 | { 0x0090, 0, 0xffffffff, 0x00000000 }, | |
5453 | { 0x0094, 0, 0x00000000, 0x00000000 }, | |
5454 | ||
5bae30c9 MC |
5455 | { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, |
5456 | { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5457 | { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5458 | { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, | |
5459 | { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, | |
5460 | { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
5461 | { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, | |
5462 | { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5463 | { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5464 | ||
5465 | { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5466 | { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5467 | { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5468 | { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5469 | { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5470 | { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5471 | ||
5472 | { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
5473 | { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, | |
5474 | { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, | |
b6016b76 MC |
5475 | |
5476 | { 0x1000, 0, 0x00000000, 0x00000001 }, | |
15b169cc | 5477 | { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, |
b6016b76 MC |
5478 | |
5479 | { 0x1408, 0, 0x01c00800, 0x00000000 }, | |
5480 | { 0x149c, 0, 0x8000ffff, 0x00000000 }, | |
5481 | { 0x14a8, 0, 0x00000000, 0x000001ff }, | |
5b0c76ad | 5482 | { 0x14ac, 0, 0x0fffffff, 0x10000000 }, |
b6016b76 MC |
5483 | { 0x14b0, 0, 0x00000002, 0x00000001 }, |
5484 | { 0x14b8, 0, 0x00000000, 0x00000000 }, | |
5485 | { 0x14c0, 0, 0x00000000, 0x00000009 }, | |
5486 | { 0x14c4, 0, 0x00003fff, 0x00000000 }, | |
5487 | { 0x14cc, 0, 0x00000000, 0x00000001 }, | |
5488 | { 0x14d0, 0, 0xffffffff, 0x00000000 }, | |
b6016b76 MC |
5489 | |
5490 | { 0x1800, 0, 0x00000000, 0x00000001 }, | |
5491 | { 0x1804, 0, 0x00000000, 0x00000003 }, | |
b6016b76 MC |
5492 | |
5493 | { 0x2800, 0, 0x00000000, 0x00000001 }, | |
5494 | { 0x2804, 0, 0x00000000, 0x00003f01 }, | |
5495 | { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, | |
5496 | { 0x2810, 0, 0xffff0000, 0x00000000 }, | |
5497 | { 0x2814, 0, 0xffff0000, 0x00000000 }, | |
5498 | { 0x2818, 0, 0xffff0000, 0x00000000 }, | |
5499 | { 0x281c, 0, 0xffff0000, 0x00000000 }, | |
5500 | { 0x2834, 0, 0xffffffff, 0x00000000 }, | |
5501 | { 0x2840, 0, 0x00000000, 0xffffffff }, | |
5502 | { 0x2844, 0, 0x00000000, 0xffffffff }, | |
5503 | { 0x2848, 0, 0xffffffff, 0x00000000 }, | |
5504 | { 0x284c, 0, 0xf800f800, 0x07ff07ff }, | |
5505 | ||
5506 | { 0x2c00, 0, 0x00000000, 0x00000011 }, | |
5507 | { 0x2c04, 0, 0x00000000, 0x00030007 }, | |
5508 | ||
b6016b76 MC |
5509 | { 0x3c00, 0, 0x00000000, 0x00000001 }, |
5510 | { 0x3c04, 0, 0x00000000, 0x00070000 }, | |
5511 | { 0x3c08, 0, 0x00007f71, 0x07f00000 }, | |
5512 | { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, | |
5513 | { 0x3c10, 0, 0xffffffff, 0x00000000 }, | |
5514 | { 0x3c14, 0, 0x00000000, 0xffffffff }, | |
5515 | { 0x3c18, 0, 0x00000000, 0xffffffff }, | |
5516 | { 0x3c1c, 0, 0xfffff000, 0x00000000 }, | |
5517 | { 0x3c20, 0, 0xffffff00, 0x00000000 }, | |
b6016b76 MC |
5518 | |
5519 | { 0x5004, 0, 0x00000000, 0x0000007f }, | |
5520 | { 0x5008, 0, 0x0f0007ff, 0x00000000 }, | |
b6016b76 | 5521 | |
b6016b76 MC |
5522 | { 0x5c00, 0, 0x00000000, 0x00000001 }, |
5523 | { 0x5c04, 0, 0x00000000, 0x0003000f }, | |
5524 | { 0x5c08, 0, 0x00000003, 0x00000000 }, | |
5525 | { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, | |
5526 | { 0x5c10, 0, 0x00000000, 0xffffffff }, | |
5527 | { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, | |
5528 | { 0x5c84, 0, 0x00000000, 0x0000f333 }, | |
5529 | { 0x5c88, 0, 0x00000000, 0x00077373 }, | |
5530 | { 0x5c8c, 0, 0x00000000, 0x0007f737 }, | |
5531 | ||
5532 | { 0x6808, 0, 0x0000ff7f, 0x00000000 }, | |
5533 | { 0x680c, 0, 0xffffffff, 0x00000000 }, | |
5534 | { 0x6810, 0, 0xffffffff, 0x00000000 }, | |
5535 | { 0x6814, 0, 0xffffffff, 0x00000000 }, | |
5536 | { 0x6818, 0, 0xffffffff, 0x00000000 }, | |
5537 | { 0x681c, 0, 0xffffffff, 0x00000000 }, | |
5538 | { 0x6820, 0, 0x00ff00ff, 0x00000000 }, | |
5539 | { 0x6824, 0, 0x00ff00ff, 0x00000000 }, | |
5540 | { 0x6828, 0, 0x00ff00ff, 0x00000000 }, | |
5541 | { 0x682c, 0, 0x03ff03ff, 0x00000000 }, | |
5542 | { 0x6830, 0, 0x03ff03ff, 0x00000000 }, | |
5543 | { 0x6834, 0, 0x03ff03ff, 0x00000000 }, | |
5544 | { 0x6838, 0, 0x03ff03ff, 0x00000000 }, | |
5545 | { 0x683c, 0, 0x0000ffff, 0x00000000 }, | |
5546 | { 0x6840, 0, 0x00000ff0, 0x00000000 }, | |
5547 | { 0x6844, 0, 0x00ffff00, 0x00000000 }, | |
5548 | { 0x684c, 0, 0xffffffff, 0x00000000 }, | |
5549 | { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, | |
5550 | { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, | |
5551 | { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, | |
5552 | { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, | |
5553 | { 0x6908, 0, 0x00000000, 0x0001ff0f }, | |
5554 | { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, | |
5555 | ||
5556 | { 0xffff, 0, 0x00000000, 0x00000000 }, | |
5557 | }; | |
5558 | ||
5559 | ret = 0; | |
5bae30c9 MC |
5560 | is_5709 = 0; |
5561 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
5562 | is_5709 = 1; | |
5563 | ||
b6016b76 MC |
5564 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { |
5565 | u32 offset, rw_mask, ro_mask, save_val, val; | |
5bae30c9 MC |
5566 | u16 flags = reg_tbl[i].flags; |
5567 | ||
5568 | if (is_5709 && (flags & BNX2_FL_NOT_5709)) | |
5569 | continue; | |
b6016b76 MC |
5570 | |
5571 | offset = (u32) reg_tbl[i].offset; | |
5572 | rw_mask = reg_tbl[i].rw_mask; | |
5573 | ro_mask = reg_tbl[i].ro_mask; | |
5574 | ||
14ab9b86 | 5575 | save_val = readl(bp->regview + offset); |
b6016b76 | 5576 | |
14ab9b86 | 5577 | writel(0, bp->regview + offset); |
b6016b76 | 5578 | |
14ab9b86 | 5579 | val = readl(bp->regview + offset); |
b6016b76 MC |
5580 | if ((val & rw_mask) != 0) { |
5581 | goto reg_test_err; | |
5582 | } | |
5583 | ||
5584 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
5585 | goto reg_test_err; | |
5586 | } | |
5587 | ||
14ab9b86 | 5588 | writel(0xffffffff, bp->regview + offset); |
b6016b76 | 5589 | |
14ab9b86 | 5590 | val = readl(bp->regview + offset); |
b6016b76 MC |
5591 | if ((val & rw_mask) != rw_mask) { |
5592 | goto reg_test_err; | |
5593 | } | |
5594 | ||
5595 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
5596 | goto reg_test_err; | |
5597 | } | |
5598 | ||
14ab9b86 | 5599 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
5600 | continue; |
5601 | ||
5602 | reg_test_err: | |
14ab9b86 | 5603 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
5604 | ret = -ENODEV; |
5605 | break; | |
5606 | } | |
5607 | return ret; | |
5608 | } | |
5609 | ||
5610 | static int | |
5611 | bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) | |
5612 | { | |
f71e1309 | 5613 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, |
b6016b76 MC |
5614 | 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; |
5615 | int i; | |
5616 | ||
5617 | for (i = 0; i < sizeof(test_pattern) / 4; i++) { | |
5618 | u32 offset; | |
5619 | ||
5620 | for (offset = 0; offset < size; offset += 4) { | |
5621 | ||
2726d6e1 | 5622 | bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); |
b6016b76 | 5623 | |
2726d6e1 | 5624 | if (bnx2_reg_rd_ind(bp, start + offset) != |
b6016b76 MC |
5625 | test_pattern[i]) { |
5626 | return -ENODEV; | |
5627 | } | |
5628 | } | |
5629 | } | |
5630 | return 0; | |
5631 | } | |
5632 | ||
5633 | static int | |
5634 | bnx2_test_memory(struct bnx2 *bp) | |
5635 | { | |
5636 | int ret = 0; | |
5637 | int i; | |
5bae30c9 | 5638 | static struct mem_entry { |
b6016b76 MC |
5639 | u32 offset; |
5640 | u32 len; | |
5bae30c9 | 5641 | } mem_tbl_5706[] = { |
b6016b76 | 5642 | { 0x60000, 0x4000 }, |
5b0c76ad | 5643 | { 0xa0000, 0x3000 }, |
b6016b76 MC |
5644 | { 0xe0000, 0x4000 }, |
5645 | { 0x120000, 0x4000 }, | |
5646 | { 0x1a0000, 0x4000 }, | |
5647 | { 0x160000, 0x4000 }, | |
5648 | { 0xffffffff, 0 }, | |
5bae30c9 MC |
5649 | }, |
5650 | mem_tbl_5709[] = { | |
5651 | { 0x60000, 0x4000 }, | |
5652 | { 0xa0000, 0x3000 }, | |
5653 | { 0xe0000, 0x4000 }, | |
5654 | { 0x120000, 0x4000 }, | |
5655 | { 0x1a0000, 0x4000 }, | |
5656 | { 0xffffffff, 0 }, | |
b6016b76 | 5657 | }; |
5bae30c9 MC |
5658 | struct mem_entry *mem_tbl; |
5659 | ||
5660 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
5661 | mem_tbl = mem_tbl_5709; | |
5662 | else | |
5663 | mem_tbl = mem_tbl_5706; | |
b6016b76 MC |
5664 | |
5665 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
5666 | if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, | |
5667 | mem_tbl[i].len)) != 0) { | |
5668 | return ret; | |
5669 | } | |
5670 | } | |
6aa20a22 | 5671 | |
b6016b76 MC |
5672 | return ret; |
5673 | } | |
5674 | ||
bc5a0690 MC |
5675 | #define BNX2_MAC_LOOPBACK 0 |
5676 | #define BNX2_PHY_LOOPBACK 1 | |
5677 | ||
b6016b76 | 5678 | static int |
bc5a0690 | 5679 | bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) |
b6016b76 MC |
5680 | { |
5681 | unsigned int pkt_size, num_pkts, i; | |
5682 | struct sk_buff *skb, *rx_skb; | |
5683 | unsigned char *packet; | |
bc5a0690 | 5684 | u16 rx_start_idx, rx_idx; |
b6016b76 MC |
5685 | dma_addr_t map; |
5686 | struct tx_bd *txbd; | |
5687 | struct sw_bd *rx_buf; | |
5688 | struct l2_fhdr *rx_hdr; | |
5689 | int ret = -ENODEV; | |
c76c0475 | 5690 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; |
35e9010b | 5691 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
bb4f98ab | 5692 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
c76c0475 MC |
5693 | |
5694 | tx_napi = bnapi; | |
b6016b76 | 5695 | |
35e9010b | 5696 | txr = &tx_napi->tx_ring; |
bb4f98ab | 5697 | rxr = &bnapi->rx_ring; |
bc5a0690 MC |
5698 | if (loopback_mode == BNX2_MAC_LOOPBACK) { |
5699 | bp->loopback = MAC_LOOPBACK; | |
5700 | bnx2_set_mac_loopback(bp); | |
5701 | } | |
5702 | else if (loopback_mode == BNX2_PHY_LOOPBACK) { | |
583c28e5 | 5703 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
489310a4 MC |
5704 | return 0; |
5705 | ||
80be4434 | 5706 | bp->loopback = PHY_LOOPBACK; |
bc5a0690 MC |
5707 | bnx2_set_phy_loopback(bp); |
5708 | } | |
5709 | else | |
5710 | return -EINVAL; | |
b6016b76 | 5711 | |
84eaa187 | 5712 | pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); |
932f3772 | 5713 | skb = netdev_alloc_skb(bp->dev, pkt_size); |
b6cbc3b6 JL |
5714 | if (!skb) |
5715 | return -ENOMEM; | |
b6016b76 | 5716 | packet = skb_put(skb, pkt_size); |
6634292b | 5717 | memcpy(packet, bp->dev->dev_addr, 6); |
b6016b76 MC |
5718 | memset(packet + 6, 0x0, 8); |
5719 | for (i = 14; i < pkt_size; i++) | |
5720 | packet[i] = (unsigned char) (i & 0xff); | |
5721 | ||
e95524a7 AD |
5722 | map = pci_map_single(bp->pdev, skb->data, pkt_size, |
5723 | PCI_DMA_TODEVICE); | |
5724 | if (pci_dma_mapping_error(bp->pdev, map)) { | |
3d16af86 BL |
5725 | dev_kfree_skb(skb); |
5726 | return -EIO; | |
5727 | } | |
b6016b76 | 5728 | |
bf5295bb MC |
5729 | REG_WR(bp, BNX2_HC_COMMAND, |
5730 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
5731 | ||
b6016b76 MC |
5732 | REG_RD(bp, BNX2_HC_COMMAND); |
5733 | ||
5734 | udelay(5); | |
35efa7c1 | 5735 | rx_start_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 | 5736 | |
b6016b76 MC |
5737 | num_pkts = 0; |
5738 | ||
35e9010b | 5739 | txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)]; |
b6016b76 MC |
5740 | |
5741 | txbd->tx_bd_haddr_hi = (u64) map >> 32; | |
5742 | txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; | |
5743 | txbd->tx_bd_mss_nbytes = pkt_size; | |
5744 | txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; | |
5745 | ||
5746 | num_pkts++; | |
35e9010b MC |
5747 | txr->tx_prod = NEXT_TX_BD(txr->tx_prod); |
5748 | txr->tx_prod_bseq += pkt_size; | |
b6016b76 | 5749 | |
35e9010b MC |
5750 | REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); |
5751 | REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); | |
b6016b76 MC |
5752 | |
5753 | udelay(100); | |
5754 | ||
bf5295bb MC |
5755 | REG_WR(bp, BNX2_HC_COMMAND, |
5756 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
5757 | ||
b6016b76 MC |
5758 | REG_RD(bp, BNX2_HC_COMMAND); |
5759 | ||
5760 | udelay(5); | |
5761 | ||
e95524a7 | 5762 | pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); |
745720e5 | 5763 | dev_kfree_skb(skb); |
b6016b76 | 5764 | |
35e9010b | 5765 | if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) |
b6016b76 | 5766 | goto loopback_test_done; |
b6016b76 | 5767 | |
35efa7c1 | 5768 | rx_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 MC |
5769 | if (rx_idx != rx_start_idx + num_pkts) { |
5770 | goto loopback_test_done; | |
5771 | } | |
5772 | ||
bb4f98ab | 5773 | rx_buf = &rxr->rx_buf_ring[rx_start_idx]; |
b6016b76 MC |
5774 | rx_skb = rx_buf->skb; |
5775 | ||
5776 | rx_hdr = (struct l2_fhdr *) rx_skb->data; | |
d89cb6af | 5777 | skb_reserve(rx_skb, BNX2_RX_OFFSET); |
b6016b76 MC |
5778 | |
5779 | pci_dma_sync_single_for_cpu(bp->pdev, | |
5780 | pci_unmap_addr(rx_buf, mapping), | |
5781 | bp->rx_buf_size, PCI_DMA_FROMDEVICE); | |
5782 | ||
ade2bfe7 | 5783 | if (rx_hdr->l2_fhdr_status & |
b6016b76 MC |
5784 | (L2_FHDR_ERRORS_BAD_CRC | |
5785 | L2_FHDR_ERRORS_PHY_DECODE | | |
5786 | L2_FHDR_ERRORS_ALIGNMENT | | |
5787 | L2_FHDR_ERRORS_TOO_SHORT | | |
5788 | L2_FHDR_ERRORS_GIANT_FRAME)) { | |
5789 | ||
5790 | goto loopback_test_done; | |
5791 | } | |
5792 | ||
5793 | if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { | |
5794 | goto loopback_test_done; | |
5795 | } | |
5796 | ||
5797 | for (i = 14; i < pkt_size; i++) { | |
5798 | if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) { | |
5799 | goto loopback_test_done; | |
5800 | } | |
5801 | } | |
5802 | ||
5803 | ret = 0; | |
5804 | ||
5805 | loopback_test_done: | |
5806 | bp->loopback = 0; | |
5807 | return ret; | |
5808 | } | |
5809 | ||
bc5a0690 MC |
5810 | #define BNX2_MAC_LOOPBACK_FAILED 1 |
5811 | #define BNX2_PHY_LOOPBACK_FAILED 2 | |
5812 | #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \ | |
5813 | BNX2_PHY_LOOPBACK_FAILED) | |
5814 | ||
5815 | static int | |
5816 | bnx2_test_loopback(struct bnx2 *bp) | |
5817 | { | |
5818 | int rc = 0; | |
5819 | ||
5820 | if (!netif_running(bp->dev)) | |
5821 | return BNX2_LOOPBACK_FAILED; | |
5822 | ||
5823 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); | |
5824 | spin_lock_bh(&bp->phy_lock); | |
9a120bc5 | 5825 | bnx2_init_phy(bp, 1); |
bc5a0690 MC |
5826 | spin_unlock_bh(&bp->phy_lock); |
5827 | if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) | |
5828 | rc |= BNX2_MAC_LOOPBACK_FAILED; | |
5829 | if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK)) | |
5830 | rc |= BNX2_PHY_LOOPBACK_FAILED; | |
5831 | return rc; | |
5832 | } | |
5833 | ||
b6016b76 MC |
5834 | #define NVRAM_SIZE 0x200 |
5835 | #define CRC32_RESIDUAL 0xdebb20e3 | |
5836 | ||
5837 | static int | |
5838 | bnx2_test_nvram(struct bnx2 *bp) | |
5839 | { | |
b491edd5 | 5840 | __be32 buf[NVRAM_SIZE / 4]; |
b6016b76 MC |
5841 | u8 *data = (u8 *) buf; |
5842 | int rc = 0; | |
5843 | u32 magic, csum; | |
5844 | ||
5845 | if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) | |
5846 | goto test_nvram_done; | |
5847 | ||
5848 | magic = be32_to_cpu(buf[0]); | |
5849 | if (magic != 0x669955aa) { | |
5850 | rc = -ENODEV; | |
5851 | goto test_nvram_done; | |
5852 | } | |
5853 | ||
5854 | if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) | |
5855 | goto test_nvram_done; | |
5856 | ||
5857 | csum = ether_crc_le(0x100, data); | |
5858 | if (csum != CRC32_RESIDUAL) { | |
5859 | rc = -ENODEV; | |
5860 | goto test_nvram_done; | |
5861 | } | |
5862 | ||
5863 | csum = ether_crc_le(0x100, data + 0x100); | |
5864 | if (csum != CRC32_RESIDUAL) { | |
5865 | rc = -ENODEV; | |
5866 | } | |
5867 | ||
5868 | test_nvram_done: | |
5869 | return rc; | |
5870 | } | |
5871 | ||
5872 | static int | |
5873 | bnx2_test_link(struct bnx2 *bp) | |
5874 | { | |
5875 | u32 bmsr; | |
5876 | ||
9f52b564 MC |
5877 | if (!netif_running(bp->dev)) |
5878 | return -ENODEV; | |
5879 | ||
583c28e5 | 5880 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
489310a4 MC |
5881 | if (bp->link_up) |
5882 | return 0; | |
5883 | return -ENODEV; | |
5884 | } | |
c770a65c | 5885 | spin_lock_bh(&bp->phy_lock); |
27a005b8 MC |
5886 | bnx2_enable_bmsr1(bp); |
5887 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5888 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5889 | bnx2_disable_bmsr1(bp); | |
c770a65c | 5890 | spin_unlock_bh(&bp->phy_lock); |
6aa20a22 | 5891 | |
b6016b76 MC |
5892 | if (bmsr & BMSR_LSTATUS) { |
5893 | return 0; | |
5894 | } | |
5895 | return -ENODEV; | |
5896 | } | |
5897 | ||
5898 | static int | |
5899 | bnx2_test_intr(struct bnx2 *bp) | |
5900 | { | |
5901 | int i; | |
b6016b76 MC |
5902 | u16 status_idx; |
5903 | ||
5904 | if (!netif_running(bp->dev)) | |
5905 | return -ENODEV; | |
5906 | ||
5907 | status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; | |
5908 | ||
5909 | /* This register is not touched during run-time. */ | |
bf5295bb | 5910 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
b6016b76 MC |
5911 | REG_RD(bp, BNX2_HC_COMMAND); |
5912 | ||
5913 | for (i = 0; i < 10; i++) { | |
5914 | if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != | |
5915 | status_idx) { | |
5916 | ||
5917 | break; | |
5918 | } | |
5919 | ||
5920 | msleep_interruptible(10); | |
5921 | } | |
5922 | if (i < 10) | |
5923 | return 0; | |
5924 | ||
5925 | return -ENODEV; | |
5926 | } | |
5927 | ||
38ea3686 | 5928 | /* Determining link for parallel detection. */ |
b2fadeae MC |
5929 | static int |
5930 | bnx2_5706_serdes_has_link(struct bnx2 *bp) | |
5931 | { | |
5932 | u32 mode_ctl, an_dbg, exp; | |
5933 | ||
38ea3686 MC |
5934 | if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) |
5935 | return 0; | |
5936 | ||
b2fadeae MC |
5937 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); |
5938 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); | |
5939 | ||
5940 | if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET)) | |
5941 | return 0; | |
5942 | ||
5943 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
5944 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
5945 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
5946 | ||
f3014c0c | 5947 | if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID)) |
b2fadeae MC |
5948 | return 0; |
5949 | ||
5950 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); | |
5951 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); | |
5952 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); | |
5953 | ||
5954 | if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */ | |
5955 | return 0; | |
5956 | ||
5957 | return 1; | |
5958 | } | |
5959 | ||
b6016b76 | 5960 | static void |
48b01e2d | 5961 | bnx2_5706_serdes_timer(struct bnx2 *bp) |
b6016b76 | 5962 | { |
b2fadeae MC |
5963 | int check_link = 1; |
5964 | ||
48b01e2d | 5965 | spin_lock(&bp->phy_lock); |
b2fadeae | 5966 | if (bp->serdes_an_pending) { |
48b01e2d | 5967 | bp->serdes_an_pending--; |
b2fadeae MC |
5968 | check_link = 0; |
5969 | } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
48b01e2d | 5970 | u32 bmcr; |
b6016b76 | 5971 | |
ac392abc | 5972 | bp->current_interval = BNX2_TIMER_INTERVAL; |
cd339a0e | 5973 | |
ca58c3af | 5974 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 5975 | |
48b01e2d | 5976 | if (bmcr & BMCR_ANENABLE) { |
b2fadeae | 5977 | if (bnx2_5706_serdes_has_link(bp)) { |
48b01e2d MC |
5978 | bmcr &= ~BMCR_ANENABLE; |
5979 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
ca58c3af | 5980 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
583c28e5 | 5981 | bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; |
48b01e2d | 5982 | } |
b6016b76 | 5983 | } |
48b01e2d MC |
5984 | } |
5985 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && | |
583c28e5 | 5986 | (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { |
48b01e2d | 5987 | u32 phy2; |
b6016b76 | 5988 | |
48b01e2d MC |
5989 | bnx2_write_phy(bp, 0x17, 0x0f01); |
5990 | bnx2_read_phy(bp, 0x15, &phy2); | |
5991 | if (phy2 & 0x20) { | |
5992 | u32 bmcr; | |
cd339a0e | 5993 | |
ca58c3af | 5994 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
48b01e2d | 5995 | bmcr |= BMCR_ANENABLE; |
ca58c3af | 5996 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
b6016b76 | 5997 | |
583c28e5 | 5998 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
48b01e2d MC |
5999 | } |
6000 | } else | |
ac392abc | 6001 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6002 | |
a2724e25 | 6003 | if (check_link) { |
b2fadeae MC |
6004 | u32 val; |
6005 | ||
6006 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
6007 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | |
6008 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | |
6009 | ||
a2724e25 MC |
6010 | if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { |
6011 | if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { | |
6012 | bnx2_5706s_force_link_dn(bp, 1); | |
6013 | bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; | |
6014 | } else | |
6015 | bnx2_set_link(bp); | |
6016 | } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) | |
6017 | bnx2_set_link(bp); | |
b2fadeae | 6018 | } |
48b01e2d MC |
6019 | spin_unlock(&bp->phy_lock); |
6020 | } | |
b6016b76 | 6021 | |
f8dd064e MC |
6022 | static void |
6023 | bnx2_5708_serdes_timer(struct bnx2 *bp) | |
6024 | { | |
583c28e5 | 6025 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
6026 | return; |
6027 | ||
583c28e5 | 6028 | if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { |
f8dd064e MC |
6029 | bp->serdes_an_pending = 0; |
6030 | return; | |
6031 | } | |
b6016b76 | 6032 | |
f8dd064e MC |
6033 | spin_lock(&bp->phy_lock); |
6034 | if (bp->serdes_an_pending) | |
6035 | bp->serdes_an_pending--; | |
6036 | else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
6037 | u32 bmcr; | |
b6016b76 | 6038 | |
ca58c3af | 6039 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
f8dd064e | 6040 | if (bmcr & BMCR_ANENABLE) { |
605a9e20 | 6041 | bnx2_enable_forced_2g5(bp); |
40105c0b | 6042 | bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; |
f8dd064e | 6043 | } else { |
605a9e20 | 6044 | bnx2_disable_forced_2g5(bp); |
f8dd064e | 6045 | bp->serdes_an_pending = 2; |
ac392abc | 6046 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6047 | } |
b6016b76 | 6048 | |
f8dd064e | 6049 | } else |
ac392abc | 6050 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6051 | |
f8dd064e MC |
6052 | spin_unlock(&bp->phy_lock); |
6053 | } | |
6054 | ||
48b01e2d MC |
6055 | static void |
6056 | bnx2_timer(unsigned long data) | |
6057 | { | |
6058 | struct bnx2 *bp = (struct bnx2 *) data; | |
b6016b76 | 6059 | |
48b01e2d MC |
6060 | if (!netif_running(bp->dev)) |
6061 | return; | |
b6016b76 | 6062 | |
48b01e2d MC |
6063 | if (atomic_read(&bp->intr_sem) != 0) |
6064 | goto bnx2_restart_timer; | |
b6016b76 | 6065 | |
efba0180 MC |
6066 | if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == |
6067 | BNX2_FLAG_USING_MSI) | |
6068 | bnx2_chk_missed_msi(bp); | |
6069 | ||
df149d70 | 6070 | bnx2_send_heart_beat(bp); |
b6016b76 | 6071 | |
2726d6e1 MC |
6072 | bp->stats_blk->stat_FwRxDrop = |
6073 | bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); | |
b6016b76 | 6074 | |
02537b06 | 6075 | /* workaround occasional corrupted counters */ |
61d9e3fa | 6076 | if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) |
02537b06 MC |
6077 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | |
6078 | BNX2_HC_COMMAND_STATS_NOW); | |
6079 | ||
583c28e5 | 6080 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
f8dd064e MC |
6081 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
6082 | bnx2_5706_serdes_timer(bp); | |
27a005b8 | 6083 | else |
f8dd064e | 6084 | bnx2_5708_serdes_timer(bp); |
b6016b76 MC |
6085 | } |
6086 | ||
6087 | bnx2_restart_timer: | |
cd339a0e | 6088 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
6089 | } |
6090 | ||
8e6a72c4 MC |
6091 | static int |
6092 | bnx2_request_irq(struct bnx2 *bp) | |
6093 | { | |
6d866ffc | 6094 | unsigned long flags; |
b4b36042 MC |
6095 | struct bnx2_irq *irq; |
6096 | int rc = 0, i; | |
8e6a72c4 | 6097 | |
f86e82fb | 6098 | if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) |
6d866ffc MC |
6099 | flags = 0; |
6100 | else | |
6101 | flags = IRQF_SHARED; | |
b4b36042 MC |
6102 | |
6103 | for (i = 0; i < bp->irq_nvecs; i++) { | |
6104 | irq = &bp->irq_tbl[i]; | |
c76c0475 | 6105 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, |
f0ea2e63 | 6106 | &bp->bnx2_napi[i]); |
b4b36042 MC |
6107 | if (rc) |
6108 | break; | |
6109 | irq->requested = 1; | |
6110 | } | |
8e6a72c4 MC |
6111 | return rc; |
6112 | } | |
6113 | ||
6114 | static void | |
6115 | bnx2_free_irq(struct bnx2 *bp) | |
6116 | { | |
b4b36042 MC |
6117 | struct bnx2_irq *irq; |
6118 | int i; | |
8e6a72c4 | 6119 | |
b4b36042 MC |
6120 | for (i = 0; i < bp->irq_nvecs; i++) { |
6121 | irq = &bp->irq_tbl[i]; | |
6122 | if (irq->requested) | |
f0ea2e63 | 6123 | free_irq(irq->vector, &bp->bnx2_napi[i]); |
b4b36042 | 6124 | irq->requested = 0; |
6d866ffc | 6125 | } |
f86e82fb | 6126 | if (bp->flags & BNX2_FLAG_USING_MSI) |
b4b36042 | 6127 | pci_disable_msi(bp->pdev); |
f86e82fb | 6128 | else if (bp->flags & BNX2_FLAG_USING_MSIX) |
b4b36042 MC |
6129 | pci_disable_msix(bp->pdev); |
6130 | ||
f86e82fb | 6131 | bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); |
b4b36042 MC |
6132 | } |
6133 | ||
6134 | static void | |
5e9ad9e1 | 6135 | bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) |
b4b36042 | 6136 | { |
57851d84 MC |
6137 | int i, rc; |
6138 | struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; | |
4e1d0de9 MC |
6139 | struct net_device *dev = bp->dev; |
6140 | const int len = sizeof(bp->irq_tbl[0].name); | |
57851d84 | 6141 | |
b4b36042 MC |
6142 | bnx2_setup_msix_tbl(bp); |
6143 | REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); | |
6144 | REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); | |
6145 | REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); | |
57851d84 | 6146 | |
e2eb8e38 BL |
6147 | /* Need to flush the previous three writes to ensure MSI-X |
6148 | * is setup properly */ | |
6149 | REG_RD(bp, BNX2_PCI_MSIX_CONTROL); | |
6150 | ||
57851d84 MC |
6151 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
6152 | msix_ent[i].entry = i; | |
6153 | msix_ent[i].vector = 0; | |
6154 | } | |
6155 | ||
6156 | rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC); | |
6157 | if (rc != 0) | |
6158 | return; | |
6159 | ||
5e9ad9e1 | 6160 | bp->irq_nvecs = msix_vecs; |
f86e82fb | 6161 | bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; |
69010313 | 6162 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
57851d84 | 6163 | bp->irq_tbl[i].vector = msix_ent[i].vector; |
69010313 MC |
6164 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); |
6165 | bp->irq_tbl[i].handler = bnx2_msi_1shot; | |
6166 | } | |
6d866ffc MC |
6167 | } |
6168 | ||
6169 | static void | |
6170 | bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) | |
6171 | { | |
5e9ad9e1 | 6172 | int cpus = num_online_cpus(); |
706bf240 | 6173 | int msix_vecs = min(cpus + 1, RX_MAX_RINGS); |
5e9ad9e1 | 6174 | |
6d866ffc MC |
6175 | bp->irq_tbl[0].handler = bnx2_interrupt; |
6176 | strcpy(bp->irq_tbl[0].name, bp->dev->name); | |
b4b36042 MC |
6177 | bp->irq_nvecs = 1; |
6178 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
6179 | ||
5e9ad9e1 MC |
6180 | if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1) |
6181 | bnx2_enable_msix(bp, msix_vecs); | |
6d866ffc | 6182 | |
f86e82fb DM |
6183 | if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && |
6184 | !(bp->flags & BNX2_FLAG_USING_MSIX)) { | |
6d866ffc | 6185 | if (pci_enable_msi(bp->pdev) == 0) { |
f86e82fb | 6186 | bp->flags |= BNX2_FLAG_USING_MSI; |
6d866ffc | 6187 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
f86e82fb | 6188 | bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; |
6d866ffc MC |
6189 | bp->irq_tbl[0].handler = bnx2_msi_1shot; |
6190 | } else | |
6191 | bp->irq_tbl[0].handler = bnx2_msi; | |
b4b36042 MC |
6192 | |
6193 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
6d866ffc MC |
6194 | } |
6195 | } | |
706bf240 BL |
6196 | |
6197 | bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); | |
6198 | bp->dev->real_num_tx_queues = bp->num_tx_rings; | |
6199 | ||
5e9ad9e1 | 6200 | bp->num_rx_rings = bp->irq_nvecs; |
8e6a72c4 MC |
6201 | } |
6202 | ||
b6016b76 MC |
6203 | /* Called with rtnl_lock */ |
6204 | static int | |
6205 | bnx2_open(struct net_device *dev) | |
6206 | { | |
972ec0d4 | 6207 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6208 | int rc; |
6209 | ||
1b2f922f MC |
6210 | netif_carrier_off(dev); |
6211 | ||
829ca9a3 | 6212 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 MC |
6213 | bnx2_disable_int(bp); |
6214 | ||
35e9010b MC |
6215 | bnx2_setup_int_mode(bp, disable_msi); |
6216 | bnx2_napi_enable(bp); | |
b6016b76 | 6217 | rc = bnx2_alloc_mem(bp); |
2739a8bb MC |
6218 | if (rc) |
6219 | goto open_err; | |
b6016b76 | 6220 | |
8e6a72c4 | 6221 | rc = bnx2_request_irq(bp); |
2739a8bb MC |
6222 | if (rc) |
6223 | goto open_err; | |
b6016b76 | 6224 | |
9a120bc5 | 6225 | rc = bnx2_init_nic(bp, 1); |
2739a8bb MC |
6226 | if (rc) |
6227 | goto open_err; | |
6aa20a22 | 6228 | |
cd339a0e | 6229 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
6230 | |
6231 | atomic_set(&bp->intr_sem, 0); | |
6232 | ||
354fcd77 MC |
6233 | memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); |
6234 | ||
b6016b76 MC |
6235 | bnx2_enable_int(bp); |
6236 | ||
f86e82fb | 6237 | if (bp->flags & BNX2_FLAG_USING_MSI) { |
b6016b76 MC |
6238 | /* Test MSI to make sure it is working |
6239 | * If MSI test fails, go back to INTx mode | |
6240 | */ | |
6241 | if (bnx2_test_intr(bp) != 0) { | |
6242 | printk(KERN_WARNING PFX "%s: No interrupt was generated" | |
6243 | " using MSI, switching to INTx mode. Please" | |
6244 | " report this failure to the PCI maintainer" | |
6245 | " and include system chipset information.\n", | |
6246 | bp->dev->name); | |
6247 | ||
6248 | bnx2_disable_int(bp); | |
8e6a72c4 | 6249 | bnx2_free_irq(bp); |
b6016b76 | 6250 | |
6d866ffc MC |
6251 | bnx2_setup_int_mode(bp, 1); |
6252 | ||
9a120bc5 | 6253 | rc = bnx2_init_nic(bp, 0); |
b6016b76 | 6254 | |
8e6a72c4 MC |
6255 | if (!rc) |
6256 | rc = bnx2_request_irq(bp); | |
6257 | ||
b6016b76 | 6258 | if (rc) { |
b6016b76 | 6259 | del_timer_sync(&bp->timer); |
2739a8bb | 6260 | goto open_err; |
b6016b76 MC |
6261 | } |
6262 | bnx2_enable_int(bp); | |
6263 | } | |
6264 | } | |
f86e82fb | 6265 | if (bp->flags & BNX2_FLAG_USING_MSI) |
b6016b76 | 6266 | printk(KERN_INFO PFX "%s: using MSI\n", dev->name); |
f86e82fb | 6267 | else if (bp->flags & BNX2_FLAG_USING_MSIX) |
57851d84 | 6268 | printk(KERN_INFO PFX "%s: using MSIX\n", dev->name); |
b6016b76 | 6269 | |
706bf240 | 6270 | netif_tx_start_all_queues(dev); |
b6016b76 MC |
6271 | |
6272 | return 0; | |
2739a8bb MC |
6273 | |
6274 | open_err: | |
6275 | bnx2_napi_disable(bp); | |
6276 | bnx2_free_skbs(bp); | |
6277 | bnx2_free_irq(bp); | |
6278 | bnx2_free_mem(bp); | |
6279 | return rc; | |
b6016b76 MC |
6280 | } |
6281 | ||
6282 | static void | |
c4028958 | 6283 | bnx2_reset_task(struct work_struct *work) |
b6016b76 | 6284 | { |
c4028958 | 6285 | struct bnx2 *bp = container_of(work, struct bnx2, reset_task); |
b6016b76 | 6286 | |
51bf6bb4 MC |
6287 | rtnl_lock(); |
6288 | if (!netif_running(bp->dev)) { | |
6289 | rtnl_unlock(); | |
afdc08b9 | 6290 | return; |
51bf6bb4 | 6291 | } |
afdc08b9 | 6292 | |
b6016b76 MC |
6293 | bnx2_netif_stop(bp); |
6294 | ||
9a120bc5 | 6295 | bnx2_init_nic(bp, 1); |
b6016b76 MC |
6296 | |
6297 | atomic_set(&bp->intr_sem, 1); | |
6298 | bnx2_netif_start(bp); | |
51bf6bb4 | 6299 | rtnl_unlock(); |
b6016b76 MC |
6300 | } |
6301 | ||
20175c57 MC |
6302 | static void |
6303 | bnx2_dump_state(struct bnx2 *bp) | |
6304 | { | |
6305 | struct net_device *dev = bp->dev; | |
6306 | ||
6307 | printk(KERN_ERR PFX "%s DEBUG: intr_sem[%x]\n", dev->name, | |
6308 | atomic_read(&bp->intr_sem)); | |
6309 | printk(KERN_ERR PFX "%s DEBUG: EMAC_TX_STATUS[%08x] " | |
6310 | "RPM_MGMT_PKT_CTRL[%08x]\n", dev->name, | |
6311 | REG_RD(bp, BNX2_EMAC_TX_STATUS), | |
6312 | REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); | |
6313 | printk(KERN_ERR PFX "%s DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n", | |
6314 | dev->name, bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P0), | |
6315 | bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P1)); | |
6316 | printk(KERN_ERR PFX "%s DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", | |
6317 | dev->name, REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); | |
6318 | if (bp->flags & BNX2_FLAG_USING_MSIX) | |
6319 | printk(KERN_ERR PFX "%s DEBUG: PBA[%08x]\n", dev->name, | |
6320 | REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); | |
6321 | } | |
6322 | ||
b6016b76 MC |
6323 | static void |
6324 | bnx2_tx_timeout(struct net_device *dev) | |
6325 | { | |
972ec0d4 | 6326 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6327 | |
20175c57 MC |
6328 | bnx2_dump_state(bp); |
6329 | ||
b6016b76 MC |
6330 | /* This allows the netif to be shutdown gracefully before resetting */ |
6331 | schedule_work(&bp->reset_task); | |
6332 | } | |
6333 | ||
6334 | #ifdef BCM_VLAN | |
6335 | /* Called with rtnl_lock */ | |
6336 | static void | |
6337 | bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp) | |
6338 | { | |
972ec0d4 | 6339 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6340 | |
3767546c MC |
6341 | if (netif_running(dev)) |
6342 | bnx2_netif_stop(bp); | |
b6016b76 MC |
6343 | |
6344 | bp->vlgrp = vlgrp; | |
3767546c MC |
6345 | |
6346 | if (!netif_running(dev)) | |
6347 | return; | |
6348 | ||
b6016b76 | 6349 | bnx2_set_rx_mode(dev); |
7c62e83b MC |
6350 | if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN) |
6351 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); | |
b6016b76 MC |
6352 | |
6353 | bnx2_netif_start(bp); | |
6354 | } | |
b6016b76 MC |
6355 | #endif |
6356 | ||
932ff279 | 6357 | /* Called with netif_tx_lock. |
2f8af120 MC |
6358 | * bnx2_tx_int() runs without netif_tx_lock unless it needs to call |
6359 | * netif_wake_queue(). | |
b6016b76 | 6360 | */ |
61357325 | 6361 | static netdev_tx_t |
b6016b76 MC |
6362 | bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) |
6363 | { | |
972ec0d4 | 6364 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6365 | dma_addr_t mapping; |
6366 | struct tx_bd *txbd; | |
3d16af86 | 6367 | struct sw_tx_bd *tx_buf; |
b6016b76 MC |
6368 | u32 len, vlan_tag_flags, last_frag, mss; |
6369 | u16 prod, ring_prod; | |
6370 | int i; | |
706bf240 BL |
6371 | struct bnx2_napi *bnapi; |
6372 | struct bnx2_tx_ring_info *txr; | |
6373 | struct netdev_queue *txq; | |
6374 | ||
6375 | /* Determine which tx ring we will be placed on */ | |
6376 | i = skb_get_queue_mapping(skb); | |
6377 | bnapi = &bp->bnx2_napi[i]; | |
6378 | txr = &bnapi->tx_ring; | |
6379 | txq = netdev_get_tx_queue(dev, i); | |
b6016b76 | 6380 | |
35e9010b | 6381 | if (unlikely(bnx2_tx_avail(bp, txr) < |
a550c99b | 6382 | (skb_shinfo(skb)->nr_frags + 1))) { |
706bf240 | 6383 | netif_tx_stop_queue(txq); |
b6016b76 MC |
6384 | printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n", |
6385 | dev->name); | |
6386 | ||
6387 | return NETDEV_TX_BUSY; | |
6388 | } | |
6389 | len = skb_headlen(skb); | |
35e9010b | 6390 | prod = txr->tx_prod; |
b6016b76 MC |
6391 | ring_prod = TX_RING_IDX(prod); |
6392 | ||
6393 | vlan_tag_flags = 0; | |
84fa7933 | 6394 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
b6016b76 MC |
6395 | vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; |
6396 | } | |
6397 | ||
729b85cd | 6398 | #ifdef BCM_VLAN |
79ea13ce | 6399 | if (bp->vlgrp && vlan_tx_tag_present(skb)) { |
b6016b76 MC |
6400 | vlan_tag_flags |= |
6401 | (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); | |
6402 | } | |
729b85cd | 6403 | #endif |
fde82055 | 6404 | if ((mss = skb_shinfo(skb)->gso_size)) { |
a1efb4b6 | 6405 | u32 tcp_opt_len; |
eddc9ec5 | 6406 | struct iphdr *iph; |
b6016b76 | 6407 | |
b6016b76 MC |
6408 | vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; |
6409 | ||
4666f87a MC |
6410 | tcp_opt_len = tcp_optlen(skb); |
6411 | ||
6412 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { | |
6413 | u32 tcp_off = skb_transport_offset(skb) - | |
6414 | sizeof(struct ipv6hdr) - ETH_HLEN; | |
ab6a5bb6 | 6415 | |
4666f87a MC |
6416 | vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | |
6417 | TX_BD_FLAGS_SW_FLAGS; | |
6418 | if (likely(tcp_off == 0)) | |
6419 | vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; | |
6420 | else { | |
6421 | tcp_off >>= 3; | |
6422 | vlan_tag_flags |= ((tcp_off & 0x3) << | |
6423 | TX_BD_FLAGS_TCP6_OFF0_SHL) | | |
6424 | ((tcp_off & 0x10) << | |
6425 | TX_BD_FLAGS_TCP6_OFF4_SHL); | |
6426 | mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; | |
6427 | } | |
6428 | } else { | |
4666f87a | 6429 | iph = ip_hdr(skb); |
4666f87a MC |
6430 | if (tcp_opt_len || (iph->ihl > 5)) { |
6431 | vlan_tag_flags |= ((iph->ihl - 5) + | |
6432 | (tcp_opt_len >> 2)) << 8; | |
6433 | } | |
b6016b76 | 6434 | } |
4666f87a | 6435 | } else |
b6016b76 | 6436 | mss = 0; |
b6016b76 | 6437 | |
e95524a7 AD |
6438 | mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); |
6439 | if (pci_dma_mapping_error(bp->pdev, mapping)) { | |
3d16af86 BL |
6440 | dev_kfree_skb(skb); |
6441 | return NETDEV_TX_OK; | |
6442 | } | |
6443 | ||
35e9010b | 6444 | tx_buf = &txr->tx_buf_ring[ring_prod]; |
b6016b76 | 6445 | tx_buf->skb = skb; |
e95524a7 | 6446 | pci_unmap_addr_set(tx_buf, mapping, mapping); |
b6016b76 | 6447 | |
35e9010b | 6448 | txbd = &txr->tx_desc_ring[ring_prod]; |
b6016b76 MC |
6449 | |
6450 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
6451 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
6452 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
6453 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; | |
6454 | ||
6455 | last_frag = skb_shinfo(skb)->nr_frags; | |
d62fda08 ED |
6456 | tx_buf->nr_frags = last_frag; |
6457 | tx_buf->is_gso = skb_is_gso(skb); | |
b6016b76 MC |
6458 | |
6459 | for (i = 0; i < last_frag; i++) { | |
6460 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6461 | ||
6462 | prod = NEXT_TX_BD(prod); | |
6463 | ring_prod = TX_RING_IDX(prod); | |
35e9010b | 6464 | txbd = &txr->tx_desc_ring[ring_prod]; |
b6016b76 MC |
6465 | |
6466 | len = frag->size; | |
e95524a7 AD |
6467 | mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset, |
6468 | len, PCI_DMA_TODEVICE); | |
6469 | if (pci_dma_mapping_error(bp->pdev, mapping)) | |
6470 | goto dma_error; | |
6471 | pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, | |
6472 | mapping); | |
b6016b76 MC |
6473 | |
6474 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
6475 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
6476 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
6477 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; | |
6478 | ||
6479 | } | |
6480 | txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; | |
6481 | ||
6482 | prod = NEXT_TX_BD(prod); | |
35e9010b | 6483 | txr->tx_prod_bseq += skb->len; |
b6016b76 | 6484 | |
35e9010b MC |
6485 | REG_WR16(bp, txr->tx_bidx_addr, prod); |
6486 | REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); | |
b6016b76 MC |
6487 | |
6488 | mmiowb(); | |
6489 | ||
35e9010b | 6490 | txr->tx_prod = prod; |
b6016b76 | 6491 | |
35e9010b | 6492 | if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { |
706bf240 | 6493 | netif_tx_stop_queue(txq); |
35e9010b | 6494 | if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) |
706bf240 | 6495 | netif_tx_wake_queue(txq); |
b6016b76 MC |
6496 | } |
6497 | ||
e95524a7 AD |
6498 | return NETDEV_TX_OK; |
6499 | dma_error: | |
6500 | /* save value of frag that failed */ | |
6501 | last_frag = i; | |
6502 | ||
6503 | /* start back at beginning and unmap skb */ | |
6504 | prod = txr->tx_prod; | |
6505 | ring_prod = TX_RING_IDX(prod); | |
6506 | tx_buf = &txr->tx_buf_ring[ring_prod]; | |
6507 | tx_buf->skb = NULL; | |
6508 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), | |
6509 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
6510 | ||
6511 | /* unmap remaining mapped pages */ | |
6512 | for (i = 0; i < last_frag; i++) { | |
6513 | prod = NEXT_TX_BD(prod); | |
6514 | ring_prod = TX_RING_IDX(prod); | |
6515 | tx_buf = &txr->tx_buf_ring[ring_prod]; | |
6516 | pci_unmap_page(bp->pdev, pci_unmap_addr(tx_buf, mapping), | |
6517 | skb_shinfo(skb)->frags[i].size, | |
6518 | PCI_DMA_TODEVICE); | |
6519 | } | |
6520 | ||
6521 | dev_kfree_skb(skb); | |
b6016b76 MC |
6522 | return NETDEV_TX_OK; |
6523 | } | |
6524 | ||
6525 | /* Called with rtnl_lock */ | |
6526 | static int | |
6527 | bnx2_close(struct net_device *dev) | |
6528 | { | |
972ec0d4 | 6529 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6530 | |
4bb073c0 | 6531 | cancel_work_sync(&bp->reset_task); |
afdc08b9 | 6532 | |
bea3348e | 6533 | bnx2_disable_int_sync(bp); |
35efa7c1 | 6534 | bnx2_napi_disable(bp); |
b6016b76 | 6535 | del_timer_sync(&bp->timer); |
74bf4ba3 | 6536 | bnx2_shutdown_chip(bp); |
8e6a72c4 | 6537 | bnx2_free_irq(bp); |
b6016b76 MC |
6538 | bnx2_free_skbs(bp); |
6539 | bnx2_free_mem(bp); | |
6540 | bp->link_up = 0; | |
6541 | netif_carrier_off(bp->dev); | |
829ca9a3 | 6542 | bnx2_set_power_state(bp, PCI_D3hot); |
b6016b76 MC |
6543 | return 0; |
6544 | } | |
6545 | ||
354fcd77 MC |
6546 | static void |
6547 | bnx2_save_stats(struct bnx2 *bp) | |
6548 | { | |
6549 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
6550 | u32 *temp_stats = (u32 *) bp->temp_stats_blk; | |
6551 | int i; | |
6552 | ||
6553 | /* The 1st 10 counters are 64-bit counters */ | |
6554 | for (i = 0; i < 20; i += 2) { | |
6555 | u32 hi; | |
6556 | u64 lo; | |
6557 | ||
c9885fe5 PR |
6558 | hi = temp_stats[i] + hw_stats[i]; |
6559 | lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1]; | |
354fcd77 MC |
6560 | if (lo > 0xffffffff) |
6561 | hi++; | |
c9885fe5 PR |
6562 | temp_stats[i] = hi; |
6563 | temp_stats[i + 1] = lo & 0xffffffff; | |
354fcd77 MC |
6564 | } |
6565 | ||
6566 | for ( ; i < sizeof(struct statistics_block) / 4; i++) | |
c9885fe5 | 6567 | temp_stats[i] += hw_stats[i]; |
354fcd77 MC |
6568 | } |
6569 | ||
a4743058 | 6570 | #define GET_64BIT_NET_STATS64(ctr) \ |
b6016b76 MC |
6571 | (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \ |
6572 | (unsigned long) (ctr##_lo) | |
6573 | ||
a4743058 | 6574 | #define GET_64BIT_NET_STATS32(ctr) \ |
b6016b76 MC |
6575 | (ctr##_lo) |
6576 | ||
6577 | #if (BITS_PER_LONG == 64) | |
a4743058 | 6578 | #define GET_64BIT_NET_STATS(ctr) \ |
354fcd77 MC |
6579 | GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \ |
6580 | GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr) | |
b6016b76 | 6581 | #else |
a4743058 | 6582 | #define GET_64BIT_NET_STATS(ctr) \ |
354fcd77 MC |
6583 | GET_64BIT_NET_STATS32(bp->stats_blk->ctr) + \ |
6584 | GET_64BIT_NET_STATS32(bp->temp_stats_blk->ctr) | |
b6016b76 MC |
6585 | #endif |
6586 | ||
a4743058 | 6587 | #define GET_32BIT_NET_STATS(ctr) \ |
354fcd77 MC |
6588 | (unsigned long) (bp->stats_blk->ctr + \ |
6589 | bp->temp_stats_blk->ctr) | |
a4743058 | 6590 | |
b6016b76 MC |
6591 | static struct net_device_stats * |
6592 | bnx2_get_stats(struct net_device *dev) | |
6593 | { | |
972ec0d4 | 6594 | struct bnx2 *bp = netdev_priv(dev); |
d8e8034d | 6595 | struct net_device_stats *net_stats = &dev->stats; |
b6016b76 MC |
6596 | |
6597 | if (bp->stats_blk == NULL) { | |
6598 | return net_stats; | |
6599 | } | |
6600 | net_stats->rx_packets = | |
a4743058 MC |
6601 | GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) + |
6602 | GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) + | |
6603 | GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts); | |
b6016b76 MC |
6604 | |
6605 | net_stats->tx_packets = | |
a4743058 MC |
6606 | GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) + |
6607 | GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) + | |
6608 | GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts); | |
b6016b76 MC |
6609 | |
6610 | net_stats->rx_bytes = | |
a4743058 | 6611 | GET_64BIT_NET_STATS(stat_IfHCInOctets); |
b6016b76 MC |
6612 | |
6613 | net_stats->tx_bytes = | |
a4743058 | 6614 | GET_64BIT_NET_STATS(stat_IfHCOutOctets); |
b6016b76 | 6615 | |
6aa20a22 | 6616 | net_stats->multicast = |
a4743058 | 6617 | GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts); |
b6016b76 | 6618 | |
6aa20a22 | 6619 | net_stats->collisions = |
a4743058 | 6620 | GET_32BIT_NET_STATS(stat_EtherStatsCollisions); |
b6016b76 | 6621 | |
6aa20a22 | 6622 | net_stats->rx_length_errors = |
a4743058 MC |
6623 | GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) + |
6624 | GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts); | |
b6016b76 | 6625 | |
6aa20a22 | 6626 | net_stats->rx_over_errors = |
a4743058 MC |
6627 | GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + |
6628 | GET_32BIT_NET_STATS(stat_IfInMBUFDiscards); | |
b6016b76 | 6629 | |
6aa20a22 | 6630 | net_stats->rx_frame_errors = |
a4743058 | 6631 | GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors); |
b6016b76 | 6632 | |
6aa20a22 | 6633 | net_stats->rx_crc_errors = |
a4743058 | 6634 | GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors); |
b6016b76 MC |
6635 | |
6636 | net_stats->rx_errors = net_stats->rx_length_errors + | |
6637 | net_stats->rx_over_errors + net_stats->rx_frame_errors + | |
6638 | net_stats->rx_crc_errors; | |
6639 | ||
6640 | net_stats->tx_aborted_errors = | |
a4743058 MC |
6641 | GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) + |
6642 | GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions); | |
b6016b76 | 6643 | |
5b0c76ad MC |
6644 | if ((CHIP_NUM(bp) == CHIP_NUM_5706) || |
6645 | (CHIP_ID(bp) == CHIP_ID_5708_A0)) | |
b6016b76 MC |
6646 | net_stats->tx_carrier_errors = 0; |
6647 | else { | |
6648 | net_stats->tx_carrier_errors = | |
a4743058 | 6649 | GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors); |
b6016b76 MC |
6650 | } |
6651 | ||
6652 | net_stats->tx_errors = | |
a4743058 | 6653 | GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) + |
b6016b76 MC |
6654 | net_stats->tx_aborted_errors + |
6655 | net_stats->tx_carrier_errors; | |
6656 | ||
cea94db9 | 6657 | net_stats->rx_missed_errors = |
a4743058 MC |
6658 | GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + |
6659 | GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) + | |
6660 | GET_32BIT_NET_STATS(stat_FwRxDrop); | |
cea94db9 | 6661 | |
b6016b76 MC |
6662 | return net_stats; |
6663 | } | |
6664 | ||
6665 | /* All ethtool functions called with rtnl_lock */ | |
6666 | ||
6667 | static int | |
6668 | bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6669 | { | |
972ec0d4 | 6670 | struct bnx2 *bp = netdev_priv(dev); |
7b6b8347 | 6671 | int support_serdes = 0, support_copper = 0; |
b6016b76 MC |
6672 | |
6673 | cmd->supported = SUPPORTED_Autoneg; | |
583c28e5 | 6674 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
7b6b8347 MC |
6675 | support_serdes = 1; |
6676 | support_copper = 1; | |
6677 | } else if (bp->phy_port == PORT_FIBRE) | |
6678 | support_serdes = 1; | |
6679 | else | |
6680 | support_copper = 1; | |
6681 | ||
6682 | if (support_serdes) { | |
b6016b76 MC |
6683 | cmd->supported |= SUPPORTED_1000baseT_Full | |
6684 | SUPPORTED_FIBRE; | |
583c28e5 | 6685 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
605a9e20 | 6686 | cmd->supported |= SUPPORTED_2500baseX_Full; |
b6016b76 | 6687 | |
b6016b76 | 6688 | } |
7b6b8347 | 6689 | if (support_copper) { |
b6016b76 MC |
6690 | cmd->supported |= SUPPORTED_10baseT_Half | |
6691 | SUPPORTED_10baseT_Full | | |
6692 | SUPPORTED_100baseT_Half | | |
6693 | SUPPORTED_100baseT_Full | | |
6694 | SUPPORTED_1000baseT_Full | | |
6695 | SUPPORTED_TP; | |
6696 | ||
b6016b76 MC |
6697 | } |
6698 | ||
7b6b8347 MC |
6699 | spin_lock_bh(&bp->phy_lock); |
6700 | cmd->port = bp->phy_port; | |
b6016b76 MC |
6701 | cmd->advertising = bp->advertising; |
6702 | ||
6703 | if (bp->autoneg & AUTONEG_SPEED) { | |
6704 | cmd->autoneg = AUTONEG_ENABLE; | |
6705 | } | |
6706 | else { | |
6707 | cmd->autoneg = AUTONEG_DISABLE; | |
6708 | } | |
6709 | ||
6710 | if (netif_carrier_ok(dev)) { | |
6711 | cmd->speed = bp->line_speed; | |
6712 | cmd->duplex = bp->duplex; | |
6713 | } | |
6714 | else { | |
6715 | cmd->speed = -1; | |
6716 | cmd->duplex = -1; | |
6717 | } | |
7b6b8347 | 6718 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6719 | |
6720 | cmd->transceiver = XCVR_INTERNAL; | |
6721 | cmd->phy_address = bp->phy_addr; | |
6722 | ||
6723 | return 0; | |
6724 | } | |
6aa20a22 | 6725 | |
b6016b76 MC |
6726 | static int |
6727 | bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6728 | { | |
972ec0d4 | 6729 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6730 | u8 autoneg = bp->autoneg; |
6731 | u8 req_duplex = bp->req_duplex; | |
6732 | u16 req_line_speed = bp->req_line_speed; | |
6733 | u32 advertising = bp->advertising; | |
7b6b8347 MC |
6734 | int err = -EINVAL; |
6735 | ||
6736 | spin_lock_bh(&bp->phy_lock); | |
6737 | ||
6738 | if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) | |
6739 | goto err_out_unlock; | |
6740 | ||
583c28e5 MC |
6741 | if (cmd->port != bp->phy_port && |
6742 | !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) | |
7b6b8347 | 6743 | goto err_out_unlock; |
b6016b76 | 6744 | |
d6b14486 MC |
6745 | /* If device is down, we can store the settings only if the user |
6746 | * is setting the currently active port. | |
6747 | */ | |
6748 | if (!netif_running(dev) && cmd->port != bp->phy_port) | |
6749 | goto err_out_unlock; | |
6750 | ||
b6016b76 MC |
6751 | if (cmd->autoneg == AUTONEG_ENABLE) { |
6752 | autoneg |= AUTONEG_SPEED; | |
6753 | ||
beb499af MC |
6754 | advertising = cmd->advertising; |
6755 | if (cmd->port == PORT_TP) { | |
6756 | advertising &= ETHTOOL_ALL_COPPER_SPEED; | |
6757 | if (!advertising) | |
b6016b76 | 6758 | advertising = ETHTOOL_ALL_COPPER_SPEED; |
beb499af MC |
6759 | } else { |
6760 | advertising &= ETHTOOL_ALL_FIBRE_SPEED; | |
6761 | if (!advertising) | |
6762 | advertising = ETHTOOL_ALL_FIBRE_SPEED; | |
b6016b76 MC |
6763 | } |
6764 | advertising |= ADVERTISED_Autoneg; | |
6765 | } | |
6766 | else { | |
7b6b8347 | 6767 | if (cmd->port == PORT_FIBRE) { |
80be4434 MC |
6768 | if ((cmd->speed != SPEED_1000 && |
6769 | cmd->speed != SPEED_2500) || | |
6770 | (cmd->duplex != DUPLEX_FULL)) | |
7b6b8347 | 6771 | goto err_out_unlock; |
80be4434 MC |
6772 | |
6773 | if (cmd->speed == SPEED_2500 && | |
583c28e5 | 6774 | !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
7b6b8347 | 6775 | goto err_out_unlock; |
b6016b76 | 6776 | } |
7b6b8347 MC |
6777 | else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500) |
6778 | goto err_out_unlock; | |
6779 | ||
b6016b76 MC |
6780 | autoneg &= ~AUTONEG_SPEED; |
6781 | req_line_speed = cmd->speed; | |
6782 | req_duplex = cmd->duplex; | |
6783 | advertising = 0; | |
6784 | } | |
6785 | ||
6786 | bp->autoneg = autoneg; | |
6787 | bp->advertising = advertising; | |
6788 | bp->req_line_speed = req_line_speed; | |
6789 | bp->req_duplex = req_duplex; | |
6790 | ||
d6b14486 MC |
6791 | err = 0; |
6792 | /* If device is down, the new settings will be picked up when it is | |
6793 | * brought up. | |
6794 | */ | |
6795 | if (netif_running(dev)) | |
6796 | err = bnx2_setup_phy(bp, cmd->port); | |
b6016b76 | 6797 | |
7b6b8347 | 6798 | err_out_unlock: |
c770a65c | 6799 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 | 6800 | |
7b6b8347 | 6801 | return err; |
b6016b76 MC |
6802 | } |
6803 | ||
6804 | static void | |
6805 | bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
6806 | { | |
972ec0d4 | 6807 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6808 | |
6809 | strcpy(info->driver, DRV_MODULE_NAME); | |
6810 | strcpy(info->version, DRV_MODULE_VERSION); | |
6811 | strcpy(info->bus_info, pci_name(bp->pdev)); | |
58fc2ea4 | 6812 | strcpy(info->fw_version, bp->fw_version); |
b6016b76 MC |
6813 | } |
6814 | ||
244ac4f4 MC |
6815 | #define BNX2_REGDUMP_LEN (32 * 1024) |
6816 | ||
6817 | static int | |
6818 | bnx2_get_regs_len(struct net_device *dev) | |
6819 | { | |
6820 | return BNX2_REGDUMP_LEN; | |
6821 | } | |
6822 | ||
6823 | static void | |
6824 | bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) | |
6825 | { | |
6826 | u32 *p = _p, i, offset; | |
6827 | u8 *orig_p = _p; | |
6828 | struct bnx2 *bp = netdev_priv(dev); | |
6829 | u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c, | |
6830 | 0x0800, 0x0880, 0x0c00, 0x0c10, | |
6831 | 0x0c30, 0x0d08, 0x1000, 0x101c, | |
6832 | 0x1040, 0x1048, 0x1080, 0x10a4, | |
6833 | 0x1400, 0x1490, 0x1498, 0x14f0, | |
6834 | 0x1500, 0x155c, 0x1580, 0x15dc, | |
6835 | 0x1600, 0x1658, 0x1680, 0x16d8, | |
6836 | 0x1800, 0x1820, 0x1840, 0x1854, | |
6837 | 0x1880, 0x1894, 0x1900, 0x1984, | |
6838 | 0x1c00, 0x1c0c, 0x1c40, 0x1c54, | |
6839 | 0x1c80, 0x1c94, 0x1d00, 0x1d84, | |
6840 | 0x2000, 0x2030, 0x23c0, 0x2400, | |
6841 | 0x2800, 0x2820, 0x2830, 0x2850, | |
6842 | 0x2b40, 0x2c10, 0x2fc0, 0x3058, | |
6843 | 0x3c00, 0x3c94, 0x4000, 0x4010, | |
6844 | 0x4080, 0x4090, 0x43c0, 0x4458, | |
6845 | 0x4c00, 0x4c18, 0x4c40, 0x4c54, | |
6846 | 0x4fc0, 0x5010, 0x53c0, 0x5444, | |
6847 | 0x5c00, 0x5c18, 0x5c80, 0x5c90, | |
6848 | 0x5fc0, 0x6000, 0x6400, 0x6428, | |
6849 | 0x6800, 0x6848, 0x684c, 0x6860, | |
6850 | 0x6888, 0x6910, 0x8000 }; | |
6851 | ||
6852 | regs->version = 0; | |
6853 | ||
6854 | memset(p, 0, BNX2_REGDUMP_LEN); | |
6855 | ||
6856 | if (!netif_running(bp->dev)) | |
6857 | return; | |
6858 | ||
6859 | i = 0; | |
6860 | offset = reg_boundaries[0]; | |
6861 | p += offset; | |
6862 | while (offset < BNX2_REGDUMP_LEN) { | |
6863 | *p++ = REG_RD(bp, offset); | |
6864 | offset += 4; | |
6865 | if (offset == reg_boundaries[i + 1]) { | |
6866 | offset = reg_boundaries[i + 2]; | |
6867 | p = (u32 *) (orig_p + offset); | |
6868 | i += 2; | |
6869 | } | |
6870 | } | |
6871 | } | |
6872 | ||
b6016b76 MC |
6873 | static void |
6874 | bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
6875 | { | |
972ec0d4 | 6876 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6877 | |
f86e82fb | 6878 | if (bp->flags & BNX2_FLAG_NO_WOL) { |
b6016b76 MC |
6879 | wol->supported = 0; |
6880 | wol->wolopts = 0; | |
6881 | } | |
6882 | else { | |
6883 | wol->supported = WAKE_MAGIC; | |
6884 | if (bp->wol) | |
6885 | wol->wolopts = WAKE_MAGIC; | |
6886 | else | |
6887 | wol->wolopts = 0; | |
6888 | } | |
6889 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
6890 | } | |
6891 | ||
6892 | static int | |
6893 | bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
6894 | { | |
972ec0d4 | 6895 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6896 | |
6897 | if (wol->wolopts & ~WAKE_MAGIC) | |
6898 | return -EINVAL; | |
6899 | ||
6900 | if (wol->wolopts & WAKE_MAGIC) { | |
f86e82fb | 6901 | if (bp->flags & BNX2_FLAG_NO_WOL) |
b6016b76 MC |
6902 | return -EINVAL; |
6903 | ||
6904 | bp->wol = 1; | |
6905 | } | |
6906 | else { | |
6907 | bp->wol = 0; | |
6908 | } | |
6909 | return 0; | |
6910 | } | |
6911 | ||
6912 | static int | |
6913 | bnx2_nway_reset(struct net_device *dev) | |
6914 | { | |
972ec0d4 | 6915 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6916 | u32 bmcr; |
6917 | ||
9f52b564 MC |
6918 | if (!netif_running(dev)) |
6919 | return -EAGAIN; | |
6920 | ||
b6016b76 MC |
6921 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
6922 | return -EINVAL; | |
6923 | } | |
6924 | ||
c770a65c | 6925 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 6926 | |
583c28e5 | 6927 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
7b6b8347 MC |
6928 | int rc; |
6929 | ||
6930 | rc = bnx2_setup_remote_phy(bp, bp->phy_port); | |
6931 | spin_unlock_bh(&bp->phy_lock); | |
6932 | return rc; | |
6933 | } | |
6934 | ||
b6016b76 | 6935 | /* Force a link down visible on the other side */ |
583c28e5 | 6936 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
ca58c3af | 6937 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
c770a65c | 6938 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6939 | |
6940 | msleep(20); | |
6941 | ||
c770a65c | 6942 | spin_lock_bh(&bp->phy_lock); |
f8dd064e | 6943 | |
40105c0b | 6944 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
f8dd064e MC |
6945 | bp->serdes_an_pending = 1; |
6946 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
b6016b76 MC |
6947 | } |
6948 | ||
ca58c3af | 6949 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 6950 | bmcr &= ~BMCR_LOOPBACK; |
ca58c3af | 6951 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); |
b6016b76 | 6952 | |
c770a65c | 6953 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6954 | |
6955 | return 0; | |
6956 | } | |
6957 | ||
7959ea25 ON |
6958 | static u32 |
6959 | bnx2_get_link(struct net_device *dev) | |
6960 | { | |
6961 | struct bnx2 *bp = netdev_priv(dev); | |
6962 | ||
6963 | return bp->link_up; | |
6964 | } | |
6965 | ||
b6016b76 MC |
6966 | static int |
6967 | bnx2_get_eeprom_len(struct net_device *dev) | |
6968 | { | |
972ec0d4 | 6969 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6970 | |
1122db71 | 6971 | if (bp->flash_info == NULL) |
b6016b76 MC |
6972 | return 0; |
6973 | ||
1122db71 | 6974 | return (int) bp->flash_size; |
b6016b76 MC |
6975 | } |
6976 | ||
6977 | static int | |
6978 | bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
6979 | u8 *eebuf) | |
6980 | { | |
972ec0d4 | 6981 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6982 | int rc; |
6983 | ||
9f52b564 MC |
6984 | if (!netif_running(dev)) |
6985 | return -EAGAIN; | |
6986 | ||
1064e944 | 6987 | /* parameters already validated in ethtool_get_eeprom */ |
b6016b76 MC |
6988 | |
6989 | rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | |
6990 | ||
6991 | return rc; | |
6992 | } | |
6993 | ||
6994 | static int | |
6995 | bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
6996 | u8 *eebuf) | |
6997 | { | |
972ec0d4 | 6998 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6999 | int rc; |
7000 | ||
9f52b564 MC |
7001 | if (!netif_running(dev)) |
7002 | return -EAGAIN; | |
7003 | ||
1064e944 | 7004 | /* parameters already validated in ethtool_set_eeprom */ |
b6016b76 MC |
7005 | |
7006 | rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
7007 | ||
7008 | return rc; | |
7009 | } | |
7010 | ||
7011 | static int | |
7012 | bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
7013 | { | |
972ec0d4 | 7014 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7015 | |
7016 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
7017 | ||
7018 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
7019 | coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; | |
7020 | coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; | |
7021 | coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; | |
7022 | ||
7023 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
7024 | coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; | |
7025 | coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; | |
7026 | coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; | |
7027 | ||
7028 | coal->stats_block_coalesce_usecs = bp->stats_ticks; | |
7029 | ||
7030 | return 0; | |
7031 | } | |
7032 | ||
7033 | static int | |
7034 | bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
7035 | { | |
972ec0d4 | 7036 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7037 | |
7038 | bp->rx_ticks = (u16) coal->rx_coalesce_usecs; | |
7039 | if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; | |
7040 | ||
6aa20a22 | 7041 | bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; |
b6016b76 MC |
7042 | if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; |
7043 | ||
7044 | bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; | |
7045 | if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; | |
7046 | ||
7047 | bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; | |
7048 | if (bp->rx_quick_cons_trip_int > 0xff) | |
7049 | bp->rx_quick_cons_trip_int = 0xff; | |
7050 | ||
7051 | bp->tx_ticks = (u16) coal->tx_coalesce_usecs; | |
7052 | if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; | |
7053 | ||
7054 | bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; | |
7055 | if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; | |
7056 | ||
7057 | bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; | |
7058 | if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; | |
7059 | ||
7060 | bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; | |
7061 | if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = | |
7062 | 0xff; | |
7063 | ||
7064 | bp->stats_ticks = coal->stats_block_coalesce_usecs; | |
61d9e3fa | 7065 | if (bp->flags & BNX2_FLAG_BROKEN_STATS) { |
02537b06 MC |
7066 | if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) |
7067 | bp->stats_ticks = USEC_PER_SEC; | |
7068 | } | |
7ea6920e MC |
7069 | if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) |
7070 | bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
7071 | bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
b6016b76 MC |
7072 | |
7073 | if (netif_running(bp->dev)) { | |
7074 | bnx2_netif_stop(bp); | |
9a120bc5 | 7075 | bnx2_init_nic(bp, 0); |
b6016b76 MC |
7076 | bnx2_netif_start(bp); |
7077 | } | |
7078 | ||
7079 | return 0; | |
7080 | } | |
7081 | ||
7082 | static void | |
7083 | bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
7084 | { | |
972ec0d4 | 7085 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7086 | |
13daffa2 | 7087 | ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT; |
b6016b76 | 7088 | ering->rx_mini_max_pending = 0; |
47bf4246 | 7089 | ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT; |
b6016b76 MC |
7090 | |
7091 | ering->rx_pending = bp->rx_ring_size; | |
7092 | ering->rx_mini_pending = 0; | |
47bf4246 | 7093 | ering->rx_jumbo_pending = bp->rx_pg_ring_size; |
b6016b76 MC |
7094 | |
7095 | ering->tx_max_pending = MAX_TX_DESC_CNT; | |
7096 | ering->tx_pending = bp->tx_ring_size; | |
7097 | } | |
7098 | ||
7099 | static int | |
5d5d0015 | 7100 | bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx) |
b6016b76 | 7101 | { |
13daffa2 | 7102 | if (netif_running(bp->dev)) { |
354fcd77 MC |
7103 | /* Reset will erase chipset stats; save them */ |
7104 | bnx2_save_stats(bp); | |
7105 | ||
13daffa2 MC |
7106 | bnx2_netif_stop(bp); |
7107 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); | |
7108 | bnx2_free_skbs(bp); | |
7109 | bnx2_free_mem(bp); | |
7110 | } | |
7111 | ||
5d5d0015 MC |
7112 | bnx2_set_rx_ring_size(bp, rx); |
7113 | bp->tx_ring_size = tx; | |
b6016b76 MC |
7114 | |
7115 | if (netif_running(bp->dev)) { | |
13daffa2 MC |
7116 | int rc; |
7117 | ||
7118 | rc = bnx2_alloc_mem(bp); | |
6fefb65e MC |
7119 | if (!rc) |
7120 | rc = bnx2_init_nic(bp, 0); | |
7121 | ||
7122 | if (rc) { | |
7123 | bnx2_napi_enable(bp); | |
7124 | dev_close(bp->dev); | |
13daffa2 | 7125 | return rc; |
6fefb65e | 7126 | } |
e9f26c49 MC |
7127 | #ifdef BCM_CNIC |
7128 | mutex_lock(&bp->cnic_lock); | |
7129 | /* Let cnic know about the new status block. */ | |
7130 | if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) | |
7131 | bnx2_setup_cnic_irq_info(bp); | |
7132 | mutex_unlock(&bp->cnic_lock); | |
7133 | #endif | |
b6016b76 MC |
7134 | bnx2_netif_start(bp); |
7135 | } | |
b6016b76 MC |
7136 | return 0; |
7137 | } | |
7138 | ||
5d5d0015 MC |
7139 | static int |
7140 | bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
7141 | { | |
7142 | struct bnx2 *bp = netdev_priv(dev); | |
7143 | int rc; | |
7144 | ||
7145 | if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) || | |
7146 | (ering->tx_pending > MAX_TX_DESC_CNT) || | |
7147 | (ering->tx_pending <= MAX_SKB_FRAGS)) { | |
7148 | ||
7149 | return -EINVAL; | |
7150 | } | |
7151 | rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending); | |
7152 | return rc; | |
7153 | } | |
7154 | ||
b6016b76 MC |
7155 | static void |
7156 | bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
7157 | { | |
972ec0d4 | 7158 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7159 | |
7160 | epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); | |
7161 | epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); | |
7162 | epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); | |
7163 | } | |
7164 | ||
7165 | static int | |
7166 | bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
7167 | { | |
972ec0d4 | 7168 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7169 | |
7170 | bp->req_flow_ctrl = 0; | |
7171 | if (epause->rx_pause) | |
7172 | bp->req_flow_ctrl |= FLOW_CTRL_RX; | |
7173 | if (epause->tx_pause) | |
7174 | bp->req_flow_ctrl |= FLOW_CTRL_TX; | |
7175 | ||
7176 | if (epause->autoneg) { | |
7177 | bp->autoneg |= AUTONEG_FLOW_CTRL; | |
7178 | } | |
7179 | else { | |
7180 | bp->autoneg &= ~AUTONEG_FLOW_CTRL; | |
7181 | } | |
7182 | ||
9f52b564 MC |
7183 | if (netif_running(dev)) { |
7184 | spin_lock_bh(&bp->phy_lock); | |
7185 | bnx2_setup_phy(bp, bp->phy_port); | |
7186 | spin_unlock_bh(&bp->phy_lock); | |
7187 | } | |
b6016b76 MC |
7188 | |
7189 | return 0; | |
7190 | } | |
7191 | ||
7192 | static u32 | |
7193 | bnx2_get_rx_csum(struct net_device *dev) | |
7194 | { | |
972ec0d4 | 7195 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7196 | |
7197 | return bp->rx_csum; | |
7198 | } | |
7199 | ||
7200 | static int | |
7201 | bnx2_set_rx_csum(struct net_device *dev, u32 data) | |
7202 | { | |
972ec0d4 | 7203 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7204 | |
7205 | bp->rx_csum = data; | |
7206 | return 0; | |
7207 | } | |
7208 | ||
b11d6213 MC |
7209 | static int |
7210 | bnx2_set_tso(struct net_device *dev, u32 data) | |
7211 | { | |
4666f87a MC |
7212 | struct bnx2 *bp = netdev_priv(dev); |
7213 | ||
7214 | if (data) { | |
b11d6213 | 7215 | dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; |
4666f87a MC |
7216 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
7217 | dev->features |= NETIF_F_TSO6; | |
7218 | } else | |
7219 | dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 | | |
7220 | NETIF_F_TSO_ECN); | |
b11d6213 MC |
7221 | return 0; |
7222 | } | |
7223 | ||
14ab9b86 | 7224 | static struct { |
b6016b76 | 7225 | char string[ETH_GSTRING_LEN]; |
790dab2f | 7226 | } bnx2_stats_str_arr[] = { |
b6016b76 MC |
7227 | { "rx_bytes" }, |
7228 | { "rx_error_bytes" }, | |
7229 | { "tx_bytes" }, | |
7230 | { "tx_error_bytes" }, | |
7231 | { "rx_ucast_packets" }, | |
7232 | { "rx_mcast_packets" }, | |
7233 | { "rx_bcast_packets" }, | |
7234 | { "tx_ucast_packets" }, | |
7235 | { "tx_mcast_packets" }, | |
7236 | { "tx_bcast_packets" }, | |
7237 | { "tx_mac_errors" }, | |
7238 | { "tx_carrier_errors" }, | |
7239 | { "rx_crc_errors" }, | |
7240 | { "rx_align_errors" }, | |
7241 | { "tx_single_collisions" }, | |
7242 | { "tx_multi_collisions" }, | |
7243 | { "tx_deferred" }, | |
7244 | { "tx_excess_collisions" }, | |
7245 | { "tx_late_collisions" }, | |
7246 | { "tx_total_collisions" }, | |
7247 | { "rx_fragments" }, | |
7248 | { "rx_jabbers" }, | |
7249 | { "rx_undersize_packets" }, | |
7250 | { "rx_oversize_packets" }, | |
7251 | { "rx_64_byte_packets" }, | |
7252 | { "rx_65_to_127_byte_packets" }, | |
7253 | { "rx_128_to_255_byte_packets" }, | |
7254 | { "rx_256_to_511_byte_packets" }, | |
7255 | { "rx_512_to_1023_byte_packets" }, | |
7256 | { "rx_1024_to_1522_byte_packets" }, | |
7257 | { "rx_1523_to_9022_byte_packets" }, | |
7258 | { "tx_64_byte_packets" }, | |
7259 | { "tx_65_to_127_byte_packets" }, | |
7260 | { "tx_128_to_255_byte_packets" }, | |
7261 | { "tx_256_to_511_byte_packets" }, | |
7262 | { "tx_512_to_1023_byte_packets" }, | |
7263 | { "tx_1024_to_1522_byte_packets" }, | |
7264 | { "tx_1523_to_9022_byte_packets" }, | |
7265 | { "rx_xon_frames" }, | |
7266 | { "rx_xoff_frames" }, | |
7267 | { "tx_xon_frames" }, | |
7268 | { "tx_xoff_frames" }, | |
7269 | { "rx_mac_ctrl_frames" }, | |
7270 | { "rx_filtered_packets" }, | |
790dab2f | 7271 | { "rx_ftq_discards" }, |
b6016b76 | 7272 | { "rx_discards" }, |
cea94db9 | 7273 | { "rx_fw_discards" }, |
b6016b76 MC |
7274 | }; |
7275 | ||
790dab2f MC |
7276 | #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\ |
7277 | sizeof(bnx2_stats_str_arr[0])) | |
7278 | ||
b6016b76 MC |
7279 | #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) |
7280 | ||
f71e1309 | 7281 | static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
7282 | STATS_OFFSET32(stat_IfHCInOctets_hi), |
7283 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), | |
7284 | STATS_OFFSET32(stat_IfHCOutOctets_hi), | |
7285 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), | |
7286 | STATS_OFFSET32(stat_IfHCInUcastPkts_hi), | |
7287 | STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), | |
7288 | STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), | |
7289 | STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), | |
7290 | STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), | |
7291 | STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), | |
7292 | STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), | |
6aa20a22 JG |
7293 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), |
7294 | STATS_OFFSET32(stat_Dot3StatsFCSErrors), | |
7295 | STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), | |
7296 | STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), | |
7297 | STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), | |
7298 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), | |
7299 | STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), | |
7300 | STATS_OFFSET32(stat_Dot3StatsLateCollisions), | |
7301 | STATS_OFFSET32(stat_EtherStatsCollisions), | |
7302 | STATS_OFFSET32(stat_EtherStatsFragments), | |
7303 | STATS_OFFSET32(stat_EtherStatsJabbers), | |
7304 | STATS_OFFSET32(stat_EtherStatsUndersizePkts), | |
7305 | STATS_OFFSET32(stat_EtherStatsOverrsizePkts), | |
7306 | STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), | |
7307 | STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), | |
7308 | STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), | |
7309 | STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), | |
7310 | STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), | |
7311 | STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), | |
7312 | STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), | |
7313 | STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), | |
7314 | STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), | |
7315 | STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), | |
7316 | STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), | |
7317 | STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), | |
7318 | STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), | |
7319 | STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), | |
7320 | STATS_OFFSET32(stat_XonPauseFramesReceived), | |
7321 | STATS_OFFSET32(stat_XoffPauseFramesReceived), | |
7322 | STATS_OFFSET32(stat_OutXonSent), | |
7323 | STATS_OFFSET32(stat_OutXoffSent), | |
7324 | STATS_OFFSET32(stat_MacControlFramesReceived), | |
7325 | STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), | |
790dab2f | 7326 | STATS_OFFSET32(stat_IfInFTQDiscards), |
6aa20a22 | 7327 | STATS_OFFSET32(stat_IfInMBUFDiscards), |
cea94db9 | 7328 | STATS_OFFSET32(stat_FwRxDrop), |
b6016b76 MC |
7329 | }; |
7330 | ||
7331 | /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are | |
7332 | * skipped because of errata. | |
6aa20a22 | 7333 | */ |
14ab9b86 | 7334 | static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
7335 | 8,0,8,8,8,8,8,8,8,8, |
7336 | 4,0,4,4,4,4,4,4,4,4, | |
7337 | 4,4,4,4,4,4,4,4,4,4, | |
7338 | 4,4,4,4,4,4,4,4,4,4, | |
790dab2f | 7339 | 4,4,4,4,4,4,4, |
b6016b76 MC |
7340 | }; |
7341 | ||
5b0c76ad MC |
7342 | static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { |
7343 | 8,0,8,8,8,8,8,8,8,8, | |
7344 | 4,4,4,4,4,4,4,4,4,4, | |
7345 | 4,4,4,4,4,4,4,4,4,4, | |
7346 | 4,4,4,4,4,4,4,4,4,4, | |
790dab2f | 7347 | 4,4,4,4,4,4,4, |
5b0c76ad MC |
7348 | }; |
7349 | ||
b6016b76 MC |
7350 | #define BNX2_NUM_TESTS 6 |
7351 | ||
14ab9b86 | 7352 | static struct { |
b6016b76 MC |
7353 | char string[ETH_GSTRING_LEN]; |
7354 | } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { | |
7355 | { "register_test (offline)" }, | |
7356 | { "memory_test (offline)" }, | |
7357 | { "loopback_test (offline)" }, | |
7358 | { "nvram_test (online)" }, | |
7359 | { "interrupt_test (online)" }, | |
7360 | { "link_test (online)" }, | |
7361 | }; | |
7362 | ||
7363 | static int | |
b9f2c044 | 7364 | bnx2_get_sset_count(struct net_device *dev, int sset) |
b6016b76 | 7365 | { |
b9f2c044 JG |
7366 | switch (sset) { |
7367 | case ETH_SS_TEST: | |
7368 | return BNX2_NUM_TESTS; | |
7369 | case ETH_SS_STATS: | |
7370 | return BNX2_NUM_STATS; | |
7371 | default: | |
7372 | return -EOPNOTSUPP; | |
7373 | } | |
b6016b76 MC |
7374 | } |
7375 | ||
7376 | static void | |
7377 | bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) | |
7378 | { | |
972ec0d4 | 7379 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7380 | |
9f52b564 MC |
7381 | bnx2_set_power_state(bp, PCI_D0); |
7382 | ||
b6016b76 MC |
7383 | memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); |
7384 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
80be4434 MC |
7385 | int i; |
7386 | ||
b6016b76 MC |
7387 | bnx2_netif_stop(bp); |
7388 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); | |
7389 | bnx2_free_skbs(bp); | |
7390 | ||
7391 | if (bnx2_test_registers(bp) != 0) { | |
7392 | buf[0] = 1; | |
7393 | etest->flags |= ETH_TEST_FL_FAILED; | |
7394 | } | |
7395 | if (bnx2_test_memory(bp) != 0) { | |
7396 | buf[1] = 1; | |
7397 | etest->flags |= ETH_TEST_FL_FAILED; | |
7398 | } | |
bc5a0690 | 7399 | if ((buf[2] = bnx2_test_loopback(bp)) != 0) |
b6016b76 | 7400 | etest->flags |= ETH_TEST_FL_FAILED; |
b6016b76 | 7401 | |
9f52b564 MC |
7402 | if (!netif_running(bp->dev)) |
7403 | bnx2_shutdown_chip(bp); | |
b6016b76 | 7404 | else { |
9a120bc5 | 7405 | bnx2_init_nic(bp, 1); |
b6016b76 MC |
7406 | bnx2_netif_start(bp); |
7407 | } | |
7408 | ||
7409 | /* wait for link up */ | |
80be4434 MC |
7410 | for (i = 0; i < 7; i++) { |
7411 | if (bp->link_up) | |
7412 | break; | |
7413 | msleep_interruptible(1000); | |
7414 | } | |
b6016b76 MC |
7415 | } |
7416 | ||
7417 | if (bnx2_test_nvram(bp) != 0) { | |
7418 | buf[3] = 1; | |
7419 | etest->flags |= ETH_TEST_FL_FAILED; | |
7420 | } | |
7421 | if (bnx2_test_intr(bp) != 0) { | |
7422 | buf[4] = 1; | |
7423 | etest->flags |= ETH_TEST_FL_FAILED; | |
7424 | } | |
7425 | ||
7426 | if (bnx2_test_link(bp) != 0) { | |
7427 | buf[5] = 1; | |
7428 | etest->flags |= ETH_TEST_FL_FAILED; | |
7429 | ||
7430 | } | |
9f52b564 MC |
7431 | if (!netif_running(bp->dev)) |
7432 | bnx2_set_power_state(bp, PCI_D3hot); | |
b6016b76 MC |
7433 | } |
7434 | ||
7435 | static void | |
7436 | bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
7437 | { | |
7438 | switch (stringset) { | |
7439 | case ETH_SS_STATS: | |
7440 | memcpy(buf, bnx2_stats_str_arr, | |
7441 | sizeof(bnx2_stats_str_arr)); | |
7442 | break; | |
7443 | case ETH_SS_TEST: | |
7444 | memcpy(buf, bnx2_tests_str_arr, | |
7445 | sizeof(bnx2_tests_str_arr)); | |
7446 | break; | |
7447 | } | |
7448 | } | |
7449 | ||
b6016b76 MC |
7450 | static void |
7451 | bnx2_get_ethtool_stats(struct net_device *dev, | |
7452 | struct ethtool_stats *stats, u64 *buf) | |
7453 | { | |
972ec0d4 | 7454 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7455 | int i; |
7456 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
354fcd77 | 7457 | u32 *temp_stats = (u32 *) bp->temp_stats_blk; |
14ab9b86 | 7458 | u8 *stats_len_arr = NULL; |
b6016b76 MC |
7459 | |
7460 | if (hw_stats == NULL) { | |
7461 | memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); | |
7462 | return; | |
7463 | } | |
7464 | ||
5b0c76ad MC |
7465 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || |
7466 | (CHIP_ID(bp) == CHIP_ID_5706_A1) || | |
7467 | (CHIP_ID(bp) == CHIP_ID_5706_A2) || | |
7468 | (CHIP_ID(bp) == CHIP_ID_5708_A0)) | |
b6016b76 | 7469 | stats_len_arr = bnx2_5706_stats_len_arr; |
5b0c76ad MC |
7470 | else |
7471 | stats_len_arr = bnx2_5708_stats_len_arr; | |
b6016b76 MC |
7472 | |
7473 | for (i = 0; i < BNX2_NUM_STATS; i++) { | |
354fcd77 MC |
7474 | unsigned long offset; |
7475 | ||
b6016b76 MC |
7476 | if (stats_len_arr[i] == 0) { |
7477 | /* skip this counter */ | |
7478 | buf[i] = 0; | |
7479 | continue; | |
7480 | } | |
354fcd77 MC |
7481 | |
7482 | offset = bnx2_stats_offset_arr[i]; | |
b6016b76 MC |
7483 | if (stats_len_arr[i] == 4) { |
7484 | /* 4-byte counter */ | |
354fcd77 MC |
7485 | buf[i] = (u64) *(hw_stats + offset) + |
7486 | *(temp_stats + offset); | |
b6016b76 MC |
7487 | continue; |
7488 | } | |
7489 | /* 8-byte counter */ | |
354fcd77 MC |
7490 | buf[i] = (((u64) *(hw_stats + offset)) << 32) + |
7491 | *(hw_stats + offset + 1) + | |
7492 | (((u64) *(temp_stats + offset)) << 32) + | |
7493 | *(temp_stats + offset + 1); | |
b6016b76 MC |
7494 | } |
7495 | } | |
7496 | ||
7497 | static int | |
7498 | bnx2_phys_id(struct net_device *dev, u32 data) | |
7499 | { | |
972ec0d4 | 7500 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7501 | int i; |
7502 | u32 save; | |
7503 | ||
9f52b564 MC |
7504 | bnx2_set_power_state(bp, PCI_D0); |
7505 | ||
b6016b76 MC |
7506 | if (data == 0) |
7507 | data = 2; | |
7508 | ||
7509 | save = REG_RD(bp, BNX2_MISC_CFG); | |
7510 | REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); | |
7511 | ||
7512 | for (i = 0; i < (data * 2); i++) { | |
7513 | if ((i % 2) == 0) { | |
7514 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); | |
7515 | } | |
7516 | else { | |
7517 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | | |
7518 | BNX2_EMAC_LED_1000MB_OVERRIDE | | |
7519 | BNX2_EMAC_LED_100MB_OVERRIDE | | |
7520 | BNX2_EMAC_LED_10MB_OVERRIDE | | |
7521 | BNX2_EMAC_LED_TRAFFIC_OVERRIDE | | |
7522 | BNX2_EMAC_LED_TRAFFIC); | |
7523 | } | |
7524 | msleep_interruptible(500); | |
7525 | if (signal_pending(current)) | |
7526 | break; | |
7527 | } | |
7528 | REG_WR(bp, BNX2_EMAC_LED, 0); | |
7529 | REG_WR(bp, BNX2_MISC_CFG, save); | |
9f52b564 MC |
7530 | |
7531 | if (!netif_running(dev)) | |
7532 | bnx2_set_power_state(bp, PCI_D3hot); | |
7533 | ||
b6016b76 MC |
7534 | return 0; |
7535 | } | |
7536 | ||
4666f87a MC |
7537 | static int |
7538 | bnx2_set_tx_csum(struct net_device *dev, u32 data) | |
7539 | { | |
7540 | struct bnx2 *bp = netdev_priv(dev); | |
7541 | ||
7542 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
6460d948 | 7543 | return (ethtool_op_set_tx_ipv6_csum(dev, data)); |
4666f87a MC |
7544 | else |
7545 | return (ethtool_op_set_tx_csum(dev, data)); | |
7546 | } | |
7547 | ||
7282d491 | 7548 | static const struct ethtool_ops bnx2_ethtool_ops = { |
b6016b76 MC |
7549 | .get_settings = bnx2_get_settings, |
7550 | .set_settings = bnx2_set_settings, | |
7551 | .get_drvinfo = bnx2_get_drvinfo, | |
244ac4f4 MC |
7552 | .get_regs_len = bnx2_get_regs_len, |
7553 | .get_regs = bnx2_get_regs, | |
b6016b76 MC |
7554 | .get_wol = bnx2_get_wol, |
7555 | .set_wol = bnx2_set_wol, | |
7556 | .nway_reset = bnx2_nway_reset, | |
7959ea25 | 7557 | .get_link = bnx2_get_link, |
b6016b76 MC |
7558 | .get_eeprom_len = bnx2_get_eeprom_len, |
7559 | .get_eeprom = bnx2_get_eeprom, | |
7560 | .set_eeprom = bnx2_set_eeprom, | |
7561 | .get_coalesce = bnx2_get_coalesce, | |
7562 | .set_coalesce = bnx2_set_coalesce, | |
7563 | .get_ringparam = bnx2_get_ringparam, | |
7564 | .set_ringparam = bnx2_set_ringparam, | |
7565 | .get_pauseparam = bnx2_get_pauseparam, | |
7566 | .set_pauseparam = bnx2_set_pauseparam, | |
7567 | .get_rx_csum = bnx2_get_rx_csum, | |
7568 | .set_rx_csum = bnx2_set_rx_csum, | |
4666f87a | 7569 | .set_tx_csum = bnx2_set_tx_csum, |
b6016b76 | 7570 | .set_sg = ethtool_op_set_sg, |
b11d6213 | 7571 | .set_tso = bnx2_set_tso, |
b6016b76 MC |
7572 | .self_test = bnx2_self_test, |
7573 | .get_strings = bnx2_get_strings, | |
7574 | .phys_id = bnx2_phys_id, | |
b6016b76 | 7575 | .get_ethtool_stats = bnx2_get_ethtool_stats, |
b9f2c044 | 7576 | .get_sset_count = bnx2_get_sset_count, |
b6016b76 MC |
7577 | }; |
7578 | ||
7579 | /* Called with rtnl_lock */ | |
7580 | static int | |
7581 | bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
7582 | { | |
14ab9b86 | 7583 | struct mii_ioctl_data *data = if_mii(ifr); |
972ec0d4 | 7584 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7585 | int err; |
7586 | ||
7587 | switch(cmd) { | |
7588 | case SIOCGMIIPHY: | |
7589 | data->phy_id = bp->phy_addr; | |
7590 | ||
7591 | /* fallthru */ | |
7592 | case SIOCGMIIREG: { | |
7593 | u32 mii_regval; | |
7594 | ||
583c28e5 | 7595 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
7b6b8347 MC |
7596 | return -EOPNOTSUPP; |
7597 | ||
dad3e452 MC |
7598 | if (!netif_running(dev)) |
7599 | return -EAGAIN; | |
7600 | ||
c770a65c | 7601 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7602 | err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); |
c770a65c | 7603 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7604 | |
7605 | data->val_out = mii_regval; | |
7606 | ||
7607 | return err; | |
7608 | } | |
7609 | ||
7610 | case SIOCSMIIREG: | |
583c28e5 | 7611 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
7b6b8347 MC |
7612 | return -EOPNOTSUPP; |
7613 | ||
dad3e452 MC |
7614 | if (!netif_running(dev)) |
7615 | return -EAGAIN; | |
7616 | ||
c770a65c | 7617 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7618 | err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); |
c770a65c | 7619 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7620 | |
7621 | return err; | |
7622 | ||
7623 | default: | |
7624 | /* do nothing */ | |
7625 | break; | |
7626 | } | |
7627 | return -EOPNOTSUPP; | |
7628 | } | |
7629 | ||
7630 | /* Called with rtnl_lock */ | |
7631 | static int | |
7632 | bnx2_change_mac_addr(struct net_device *dev, void *p) | |
7633 | { | |
7634 | struct sockaddr *addr = p; | |
972ec0d4 | 7635 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7636 | |
73eef4cd MC |
7637 | if (!is_valid_ether_addr(addr->sa_data)) |
7638 | return -EINVAL; | |
7639 | ||
b6016b76 MC |
7640 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7641 | if (netif_running(dev)) | |
5fcaed01 | 7642 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 MC |
7643 | |
7644 | return 0; | |
7645 | } | |
7646 | ||
7647 | /* Called with rtnl_lock */ | |
7648 | static int | |
7649 | bnx2_change_mtu(struct net_device *dev, int new_mtu) | |
7650 | { | |
972ec0d4 | 7651 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7652 | |
7653 | if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || | |
7654 | ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) | |
7655 | return -EINVAL; | |
7656 | ||
7657 | dev->mtu = new_mtu; | |
5d5d0015 | 7658 | return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size)); |
b6016b76 MC |
7659 | } |
7660 | ||
257ddbda | 7661 | #ifdef CONFIG_NET_POLL_CONTROLLER |
b6016b76 MC |
7662 | static void |
7663 | poll_bnx2(struct net_device *dev) | |
7664 | { | |
972ec0d4 | 7665 | struct bnx2 *bp = netdev_priv(dev); |
b2af2c1d | 7666 | int i; |
b6016b76 | 7667 | |
b2af2c1d NH |
7668 | for (i = 0; i < bp->irq_nvecs; i++) { |
7669 | disable_irq(bp->irq_tbl[i].vector); | |
7670 | bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]); | |
7671 | enable_irq(bp->irq_tbl[i].vector); | |
7672 | } | |
b6016b76 MC |
7673 | } |
7674 | #endif | |
7675 | ||
253c8b75 MC |
7676 | static void __devinit |
7677 | bnx2_get_5709_media(struct bnx2 *bp) | |
7678 | { | |
7679 | u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); | |
7680 | u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; | |
7681 | u32 strap; | |
7682 | ||
7683 | if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) | |
7684 | return; | |
7685 | else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { | |
583c28e5 | 7686 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7687 | return; |
7688 | } | |
7689 | ||
7690 | if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) | |
7691 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; | |
7692 | else | |
7693 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; | |
7694 | ||
7695 | if (PCI_FUNC(bp->pdev->devfn) == 0) { | |
7696 | switch (strap) { | |
7697 | case 0x4: | |
7698 | case 0x5: | |
7699 | case 0x6: | |
583c28e5 | 7700 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7701 | return; |
7702 | } | |
7703 | } else { | |
7704 | switch (strap) { | |
7705 | case 0x1: | |
7706 | case 0x2: | |
7707 | case 0x4: | |
583c28e5 | 7708 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7709 | return; |
7710 | } | |
7711 | } | |
7712 | } | |
7713 | ||
883e5151 MC |
7714 | static void __devinit |
7715 | bnx2_get_pci_speed(struct bnx2 *bp) | |
7716 | { | |
7717 | u32 reg; | |
7718 | ||
7719 | reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); | |
7720 | if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { | |
7721 | u32 clkreg; | |
7722 | ||
f86e82fb | 7723 | bp->flags |= BNX2_FLAG_PCIX; |
883e5151 MC |
7724 | |
7725 | clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); | |
7726 | ||
7727 | clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; | |
7728 | switch (clkreg) { | |
7729 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: | |
7730 | bp->bus_speed_mhz = 133; | |
7731 | break; | |
7732 | ||
7733 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: | |
7734 | bp->bus_speed_mhz = 100; | |
7735 | break; | |
7736 | ||
7737 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: | |
7738 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: | |
7739 | bp->bus_speed_mhz = 66; | |
7740 | break; | |
7741 | ||
7742 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: | |
7743 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: | |
7744 | bp->bus_speed_mhz = 50; | |
7745 | break; | |
7746 | ||
7747 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: | |
7748 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: | |
7749 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: | |
7750 | bp->bus_speed_mhz = 33; | |
7751 | break; | |
7752 | } | |
7753 | } | |
7754 | else { | |
7755 | if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) | |
7756 | bp->bus_speed_mhz = 66; | |
7757 | else | |
7758 | bp->bus_speed_mhz = 33; | |
7759 | } | |
7760 | ||
7761 | if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) | |
f86e82fb | 7762 | bp->flags |= BNX2_FLAG_PCI_32BIT; |
883e5151 MC |
7763 | |
7764 | } | |
7765 | ||
76d99061 MC |
7766 | static void __devinit |
7767 | bnx2_read_vpd_fw_ver(struct bnx2 *bp) | |
7768 | { | |
7769 | int rc, i, v0_len = 0; | |
7770 | u8 *data; | |
7771 | u8 *v0_str = NULL; | |
7772 | bool mn_match = false; | |
7773 | ||
012093f6 MC |
7774 | #define BNX2_VPD_NVRAM_OFFSET 0x300 |
7775 | #define BNX2_VPD_LEN 128 | |
76d99061 MC |
7776 | #define BNX2_MAX_VER_SLEN 30 |
7777 | ||
7778 | data = kmalloc(256, GFP_KERNEL); | |
7779 | if (!data) | |
7780 | return; | |
7781 | ||
012093f6 MC |
7782 | rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN, |
7783 | BNX2_VPD_LEN); | |
76d99061 MC |
7784 | if (rc) |
7785 | goto vpd_done; | |
7786 | ||
012093f6 MC |
7787 | for (i = 0; i < BNX2_VPD_LEN; i += 4) { |
7788 | data[i] = data[i + BNX2_VPD_LEN + 3]; | |
7789 | data[i + 1] = data[i + BNX2_VPD_LEN + 2]; | |
7790 | data[i + 2] = data[i + BNX2_VPD_LEN + 1]; | |
7791 | data[i + 3] = data[i + BNX2_VPD_LEN]; | |
76d99061 MC |
7792 | } |
7793 | ||
012093f6 | 7794 | for (i = 0; i <= BNX2_VPD_LEN - 3; ) { |
76d99061 MC |
7795 | unsigned char val = data[i]; |
7796 | unsigned int block_end; | |
7797 | ||
7798 | if (val == 0x82 || val == 0x91) { | |
7799 | i = (i + 3 + (data[i + 1] + (data[i + 2] << 8))); | |
7800 | continue; | |
7801 | } | |
7802 | ||
7803 | if (val != 0x90) | |
7804 | goto vpd_done; | |
7805 | ||
7806 | block_end = (i + 3 + (data[i + 1] + (data[i + 2] << 8))); | |
7807 | i += 3; | |
7808 | ||
012093f6 | 7809 | if (block_end > BNX2_VPD_LEN) |
76d99061 MC |
7810 | goto vpd_done; |
7811 | ||
7812 | while (i < (block_end - 2)) { | |
012093f6 | 7813 | int len = data[i + 2]; |
76d99061 | 7814 | |
012093f6 MC |
7815 | if (i + 3 + len > block_end) |
7816 | goto vpd_done; | |
76d99061 | 7817 | |
012093f6 MC |
7818 | if (data[i] == 'M' && data[i + 1] == 'N') { |
7819 | if (len != 4 || | |
7820 | memcmp(&data[i + 3], "1028", 4)) | |
76d99061 MC |
7821 | goto vpd_done; |
7822 | mn_match = true; | |
76d99061 MC |
7823 | |
7824 | } else if (data[i] == 'V' && data[i + 1] == '0') { | |
012093f6 | 7825 | if (len > BNX2_MAX_VER_SLEN) |
76d99061 MC |
7826 | goto vpd_done; |
7827 | ||
012093f6 MC |
7828 | v0_len = len; |
7829 | v0_str = &data[i + 3]; | |
76d99061 | 7830 | } |
012093f6 | 7831 | i += 3 + len; |
76d99061 MC |
7832 | |
7833 | if (mn_match && v0_str) { | |
7834 | memcpy(bp->fw_version, v0_str, v0_len); | |
7835 | bp->fw_version[v0_len] = ' '; | |
7836 | goto vpd_done; | |
7837 | } | |
7838 | } | |
7839 | goto vpd_done; | |
7840 | } | |
7841 | ||
7842 | vpd_done: | |
7843 | kfree(data); | |
7844 | } | |
7845 | ||
b6016b76 MC |
7846 | static int __devinit |
7847 | bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |
7848 | { | |
7849 | struct bnx2 *bp; | |
7850 | unsigned long mem_len; | |
58fc2ea4 | 7851 | int rc, i, j; |
b6016b76 | 7852 | u32 reg; |
40453c83 | 7853 | u64 dma_mask, persist_dma_mask; |
b6016b76 | 7854 | |
b6016b76 | 7855 | SET_NETDEV_DEV(dev, &pdev->dev); |
972ec0d4 | 7856 | bp = netdev_priv(dev); |
b6016b76 MC |
7857 | |
7858 | bp->flags = 0; | |
7859 | bp->phy_flags = 0; | |
7860 | ||
354fcd77 MC |
7861 | bp->temp_stats_blk = |
7862 | kzalloc(sizeof(struct statistics_block), GFP_KERNEL); | |
7863 | ||
7864 | if (bp->temp_stats_blk == NULL) { | |
7865 | rc = -ENOMEM; | |
7866 | goto err_out; | |
7867 | } | |
7868 | ||
b6016b76 MC |
7869 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ |
7870 | rc = pci_enable_device(pdev); | |
7871 | if (rc) { | |
898eb71c | 7872 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n"); |
b6016b76 MC |
7873 | goto err_out; |
7874 | } | |
7875 | ||
7876 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
9b91cf9d | 7877 | dev_err(&pdev->dev, |
2e8a538d | 7878 | "Cannot find PCI device base address, aborting.\n"); |
b6016b76 MC |
7879 | rc = -ENODEV; |
7880 | goto err_out_disable; | |
7881 | } | |
7882 | ||
7883 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
7884 | if (rc) { | |
9b91cf9d | 7885 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n"); |
b6016b76 MC |
7886 | goto err_out_disable; |
7887 | } | |
7888 | ||
7889 | pci_set_master(pdev); | |
6ff2da49 | 7890 | pci_save_state(pdev); |
b6016b76 MC |
7891 | |
7892 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
7893 | if (bp->pm_cap == 0) { | |
9b91cf9d | 7894 | dev_err(&pdev->dev, |
2e8a538d | 7895 | "Cannot find power management capability, aborting.\n"); |
b6016b76 MC |
7896 | rc = -EIO; |
7897 | goto err_out_release; | |
7898 | } | |
7899 | ||
b6016b76 MC |
7900 | bp->dev = dev; |
7901 | bp->pdev = pdev; | |
7902 | ||
7903 | spin_lock_init(&bp->phy_lock); | |
1b8227c4 | 7904 | spin_lock_init(&bp->indirect_lock); |
c5a88950 MC |
7905 | #ifdef BCM_CNIC |
7906 | mutex_init(&bp->cnic_lock); | |
7907 | #endif | |
c4028958 | 7908 | INIT_WORK(&bp->reset_task, bnx2_reset_task); |
b6016b76 MC |
7909 | |
7910 | dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); | |
4edd473f | 7911 | mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1); |
b6016b76 MC |
7912 | dev->mem_end = dev->mem_start + mem_len; |
7913 | dev->irq = pdev->irq; | |
7914 | ||
7915 | bp->regview = ioremap_nocache(dev->base_addr, mem_len); | |
7916 | ||
7917 | if (!bp->regview) { | |
9b91cf9d | 7918 | dev_err(&pdev->dev, "Cannot map register space, aborting.\n"); |
b6016b76 MC |
7919 | rc = -ENOMEM; |
7920 | goto err_out_release; | |
7921 | } | |
7922 | ||
7923 | /* Configure byte swap and enable write to the reg_window registers. | |
7924 | * Rely on CPU to do target byte swapping on big endian systems | |
7925 | * The chip's target access swapping will not swap all accesses | |
7926 | */ | |
7927 | pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, | |
7928 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
7929 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); | |
7930 | ||
829ca9a3 | 7931 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 MC |
7932 | |
7933 | bp->chip_id = REG_RD(bp, BNX2_MISC_ID); | |
7934 | ||
883e5151 MC |
7935 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
7936 | if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) { | |
7937 | dev_err(&pdev->dev, | |
7938 | "Cannot find PCIE capability, aborting.\n"); | |
7939 | rc = -EIO; | |
7940 | goto err_out_unmap; | |
7941 | } | |
f86e82fb | 7942 | bp->flags |= BNX2_FLAG_PCIE; |
2dd201d7 | 7943 | if (CHIP_REV(bp) == CHIP_REV_Ax) |
f86e82fb | 7944 | bp->flags |= BNX2_FLAG_JUMBO_BROKEN; |
883e5151 | 7945 | } else { |
59b47d8a MC |
7946 | bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); |
7947 | if (bp->pcix_cap == 0) { | |
7948 | dev_err(&pdev->dev, | |
7949 | "Cannot find PCIX capability, aborting.\n"); | |
7950 | rc = -EIO; | |
7951 | goto err_out_unmap; | |
7952 | } | |
61d9e3fa | 7953 | bp->flags |= BNX2_FLAG_BROKEN_STATS; |
59b47d8a MC |
7954 | } |
7955 | ||
b4b36042 MC |
7956 | if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) { |
7957 | if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) | |
f86e82fb | 7958 | bp->flags |= BNX2_FLAG_MSIX_CAP; |
b4b36042 MC |
7959 | } |
7960 | ||
8e6a72c4 MC |
7961 | if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) { |
7962 | if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) | |
f86e82fb | 7963 | bp->flags |= BNX2_FLAG_MSI_CAP; |
8e6a72c4 MC |
7964 | } |
7965 | ||
40453c83 MC |
7966 | /* 5708 cannot support DMA addresses > 40-bit. */ |
7967 | if (CHIP_NUM(bp) == CHIP_NUM_5708) | |
50cf156a | 7968 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
40453c83 | 7969 | else |
6a35528a | 7970 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
40453c83 MC |
7971 | |
7972 | /* Configure DMA attributes. */ | |
7973 | if (pci_set_dma_mask(pdev, dma_mask) == 0) { | |
7974 | dev->features |= NETIF_F_HIGHDMA; | |
7975 | rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); | |
7976 | if (rc) { | |
7977 | dev_err(&pdev->dev, | |
7978 | "pci_set_consistent_dma_mask failed, aborting.\n"); | |
7979 | goto err_out_unmap; | |
7980 | } | |
284901a9 | 7981 | } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { |
40453c83 MC |
7982 | dev_err(&pdev->dev, "System does not support DMA, aborting.\n"); |
7983 | goto err_out_unmap; | |
7984 | } | |
7985 | ||
f86e82fb | 7986 | if (!(bp->flags & BNX2_FLAG_PCIE)) |
883e5151 | 7987 | bnx2_get_pci_speed(bp); |
b6016b76 MC |
7988 | |
7989 | /* 5706A0 may falsely detect SERR and PERR. */ | |
7990 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
7991 | reg = REG_RD(bp, PCI_COMMAND); | |
7992 | reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | |
7993 | REG_WR(bp, PCI_COMMAND, reg); | |
7994 | } | |
7995 | else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && | |
f86e82fb | 7996 | !(bp->flags & BNX2_FLAG_PCIX)) { |
b6016b76 | 7997 | |
9b91cf9d | 7998 | dev_err(&pdev->dev, |
2e8a538d | 7999 | "5706 A1 can only be used in a PCIX bus, aborting.\n"); |
b6016b76 MC |
8000 | goto err_out_unmap; |
8001 | } | |
8002 | ||
8003 | bnx2_init_nvram(bp); | |
8004 | ||
2726d6e1 | 8005 | reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); |
e3648b3d MC |
8006 | |
8007 | if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == | |
24cb230b MC |
8008 | BNX2_SHM_HDR_SIGNATURE_SIG) { |
8009 | u32 off = PCI_FUNC(pdev->devfn) << 2; | |
8010 | ||
2726d6e1 | 8011 | bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); |
24cb230b | 8012 | } else |
e3648b3d MC |
8013 | bp->shmem_base = HOST_VIEW_SHMEM_BASE; |
8014 | ||
b6016b76 MC |
8015 | /* Get the permanent MAC address. First we need to make sure the |
8016 | * firmware is actually running. | |
8017 | */ | |
2726d6e1 | 8018 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); |
b6016b76 MC |
8019 | |
8020 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != | |
8021 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { | |
9b91cf9d | 8022 | dev_err(&pdev->dev, "Firmware not running, aborting.\n"); |
b6016b76 MC |
8023 | rc = -ENODEV; |
8024 | goto err_out_unmap; | |
8025 | } | |
8026 | ||
76d99061 MC |
8027 | bnx2_read_vpd_fw_ver(bp); |
8028 | ||
8029 | j = strlen(bp->fw_version); | |
2726d6e1 | 8030 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); |
76d99061 | 8031 | for (i = 0; i < 3 && j < 24; i++) { |
58fc2ea4 MC |
8032 | u8 num, k, skip0; |
8033 | ||
76d99061 MC |
8034 | if (i == 0) { |
8035 | bp->fw_version[j++] = 'b'; | |
8036 | bp->fw_version[j++] = 'c'; | |
8037 | bp->fw_version[j++] = ' '; | |
8038 | } | |
58fc2ea4 MC |
8039 | num = (u8) (reg >> (24 - (i * 8))); |
8040 | for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { | |
8041 | if (num >= k || !skip0 || k == 1) { | |
8042 | bp->fw_version[j++] = (num / k) + '0'; | |
8043 | skip0 = 0; | |
8044 | } | |
8045 | } | |
8046 | if (i != 2) | |
8047 | bp->fw_version[j++] = '.'; | |
8048 | } | |
2726d6e1 | 8049 | reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); |
846f5c62 MC |
8050 | if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) |
8051 | bp->wol = 1; | |
8052 | ||
8053 | if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { | |
f86e82fb | 8054 | bp->flags |= BNX2_FLAG_ASF_ENABLE; |
c2d3db8c MC |
8055 | |
8056 | for (i = 0; i < 30; i++) { | |
2726d6e1 | 8057 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
c2d3db8c MC |
8058 | if (reg & BNX2_CONDITION_MFW_RUN_MASK) |
8059 | break; | |
8060 | msleep(10); | |
8061 | } | |
8062 | } | |
2726d6e1 | 8063 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
58fc2ea4 MC |
8064 | reg &= BNX2_CONDITION_MFW_RUN_MASK; |
8065 | if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && | |
8066 | reg != BNX2_CONDITION_MFW_RUN_NONE) { | |
2726d6e1 | 8067 | u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); |
58fc2ea4 | 8068 | |
76d99061 MC |
8069 | if (j < 32) |
8070 | bp->fw_version[j++] = ' '; | |
8071 | for (i = 0; i < 3 && j < 28; i++) { | |
2726d6e1 | 8072 | reg = bnx2_reg_rd_ind(bp, addr + i * 4); |
58fc2ea4 MC |
8073 | reg = swab32(reg); |
8074 | memcpy(&bp->fw_version[j], ®, 4); | |
8075 | j += 4; | |
8076 | } | |
8077 | } | |
b6016b76 | 8078 | |
2726d6e1 | 8079 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); |
b6016b76 MC |
8080 | bp->mac_addr[0] = (u8) (reg >> 8); |
8081 | bp->mac_addr[1] = (u8) reg; | |
8082 | ||
2726d6e1 | 8083 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); |
b6016b76 MC |
8084 | bp->mac_addr[2] = (u8) (reg >> 24); |
8085 | bp->mac_addr[3] = (u8) (reg >> 16); | |
8086 | bp->mac_addr[4] = (u8) (reg >> 8); | |
8087 | bp->mac_addr[5] = (u8) reg; | |
8088 | ||
8089 | bp->tx_ring_size = MAX_TX_DESC_CNT; | |
932f3772 | 8090 | bnx2_set_rx_ring_size(bp, 255); |
b6016b76 MC |
8091 | |
8092 | bp->rx_csum = 1; | |
8093 | ||
cf7474a6 | 8094 | bp->tx_quick_cons_trip_int = 2; |
b6016b76 | 8095 | bp->tx_quick_cons_trip = 20; |
cf7474a6 | 8096 | bp->tx_ticks_int = 18; |
b6016b76 | 8097 | bp->tx_ticks = 80; |
6aa20a22 | 8098 | |
cf7474a6 MC |
8099 | bp->rx_quick_cons_trip_int = 2; |
8100 | bp->rx_quick_cons_trip = 12; | |
b6016b76 MC |
8101 | bp->rx_ticks_int = 18; |
8102 | bp->rx_ticks = 18; | |
8103 | ||
7ea6920e | 8104 | bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; |
b6016b76 | 8105 | |
ac392abc | 8106 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 8107 | |
5b0c76ad MC |
8108 | bp->phy_addr = 1; |
8109 | ||
b6016b76 | 8110 | /* Disable WOL support if we are running on a SERDES chip. */ |
253c8b75 MC |
8111 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
8112 | bnx2_get_5709_media(bp); | |
8113 | else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) | |
583c28e5 | 8114 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
bac0dff6 | 8115 | |
0d8a6571 | 8116 | bp->phy_port = PORT_TP; |
583c28e5 | 8117 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
0d8a6571 | 8118 | bp->phy_port = PORT_FIBRE; |
2726d6e1 | 8119 | reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
846f5c62 | 8120 | if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { |
f86e82fb | 8121 | bp->flags |= BNX2_FLAG_NO_WOL; |
846f5c62 MC |
8122 | bp->wol = 0; |
8123 | } | |
38ea3686 MC |
8124 | if (CHIP_NUM(bp) == CHIP_NUM_5706) { |
8125 | /* Don't do parallel detect on this board because of | |
8126 | * some board problems. The link will not go down | |
8127 | * if we do parallel detect. | |
8128 | */ | |
8129 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && | |
8130 | pdev->subsystem_device == 0x310c) | |
8131 | bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; | |
8132 | } else { | |
5b0c76ad | 8133 | bp->phy_addr = 2; |
5b0c76ad | 8134 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) |
583c28e5 | 8135 | bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; |
5b0c76ad | 8136 | } |
261dd5ca MC |
8137 | } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || |
8138 | CHIP_NUM(bp) == CHIP_NUM_5708) | |
583c28e5 | 8139 | bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; |
fb0c18bd MC |
8140 | else if (CHIP_NUM(bp) == CHIP_NUM_5709 && |
8141 | (CHIP_REV(bp) == CHIP_REV_Ax || | |
8142 | CHIP_REV(bp) == CHIP_REV_Bx)) | |
583c28e5 | 8143 | bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; |
b6016b76 | 8144 | |
7c62e83b MC |
8145 | bnx2_init_fw_cap(bp); |
8146 | ||
16088272 MC |
8147 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || |
8148 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || | |
5ec6d7bf MC |
8149 | (CHIP_ID(bp) == CHIP_ID_5708_B1) || |
8150 | !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { | |
f86e82fb | 8151 | bp->flags |= BNX2_FLAG_NO_WOL; |
846f5c62 MC |
8152 | bp->wol = 0; |
8153 | } | |
dda1e390 | 8154 | |
b6016b76 MC |
8155 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { |
8156 | bp->tx_quick_cons_trip_int = | |
8157 | bp->tx_quick_cons_trip; | |
8158 | bp->tx_ticks_int = bp->tx_ticks; | |
8159 | bp->rx_quick_cons_trip_int = | |
8160 | bp->rx_quick_cons_trip; | |
8161 | bp->rx_ticks_int = bp->rx_ticks; | |
8162 | bp->comp_prod_trip_int = bp->comp_prod_trip; | |
8163 | bp->com_ticks_int = bp->com_ticks; | |
8164 | bp->cmd_ticks_int = bp->cmd_ticks; | |
8165 | } | |
8166 | ||
f9317a40 MC |
8167 | /* Disable MSI on 5706 if AMD 8132 bridge is found. |
8168 | * | |
8169 | * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes | |
8170 | * with byte enables disabled on the unused 32-bit word. This is legal | |
8171 | * but causes problems on the AMD 8132 which will eventually stop | |
8172 | * responding after a while. | |
8173 | * | |
8174 | * AMD believes this incompatibility is unique to the 5706, and | |
88187dfa | 8175 | * prefers to locally disable MSI rather than globally disabling it. |
f9317a40 MC |
8176 | */ |
8177 | if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) { | |
8178 | struct pci_dev *amd_8132 = NULL; | |
8179 | ||
8180 | while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, | |
8181 | PCI_DEVICE_ID_AMD_8132_BRIDGE, | |
8182 | amd_8132))) { | |
f9317a40 | 8183 | |
44c10138 AK |
8184 | if (amd_8132->revision >= 0x10 && |
8185 | amd_8132->revision <= 0x13) { | |
f9317a40 MC |
8186 | disable_msi = 1; |
8187 | pci_dev_put(amd_8132); | |
8188 | break; | |
8189 | } | |
8190 | } | |
8191 | } | |
8192 | ||
deaf391b | 8193 | bnx2_set_default_link(bp); |
b6016b76 MC |
8194 | bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; |
8195 | ||
cd339a0e | 8196 | init_timer(&bp->timer); |
ac392abc | 8197 | bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); |
cd339a0e MC |
8198 | bp->timer.data = (unsigned long) bp; |
8199 | bp->timer.function = bnx2_timer; | |
8200 | ||
b6016b76 MC |
8201 | return 0; |
8202 | ||
8203 | err_out_unmap: | |
8204 | if (bp->regview) { | |
8205 | iounmap(bp->regview); | |
73eef4cd | 8206 | bp->regview = NULL; |
b6016b76 MC |
8207 | } |
8208 | ||
8209 | err_out_release: | |
8210 | pci_release_regions(pdev); | |
8211 | ||
8212 | err_out_disable: | |
8213 | pci_disable_device(pdev); | |
8214 | pci_set_drvdata(pdev, NULL); | |
8215 | ||
8216 | err_out: | |
8217 | return rc; | |
8218 | } | |
8219 | ||
883e5151 MC |
8220 | static char * __devinit |
8221 | bnx2_bus_string(struct bnx2 *bp, char *str) | |
8222 | { | |
8223 | char *s = str; | |
8224 | ||
f86e82fb | 8225 | if (bp->flags & BNX2_FLAG_PCIE) { |
883e5151 MC |
8226 | s += sprintf(s, "PCI Express"); |
8227 | } else { | |
8228 | s += sprintf(s, "PCI"); | |
f86e82fb | 8229 | if (bp->flags & BNX2_FLAG_PCIX) |
883e5151 | 8230 | s += sprintf(s, "-X"); |
f86e82fb | 8231 | if (bp->flags & BNX2_FLAG_PCI_32BIT) |
883e5151 MC |
8232 | s += sprintf(s, " 32-bit"); |
8233 | else | |
8234 | s += sprintf(s, " 64-bit"); | |
8235 | s += sprintf(s, " %dMHz", bp->bus_speed_mhz); | |
8236 | } | |
8237 | return str; | |
8238 | } | |
8239 | ||
2ba582b7 | 8240 | static void __devinit |
35efa7c1 MC |
8241 | bnx2_init_napi(struct bnx2 *bp) |
8242 | { | |
b4b36042 | 8243 | int i; |
35efa7c1 | 8244 | |
b4b36042 | 8245 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
35e9010b MC |
8246 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; |
8247 | int (*poll)(struct napi_struct *, int); | |
8248 | ||
8249 | if (i == 0) | |
8250 | poll = bnx2_poll; | |
8251 | else | |
f0ea2e63 | 8252 | poll = bnx2_poll_msix; |
35e9010b MC |
8253 | |
8254 | netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64); | |
b4b36042 MC |
8255 | bnapi->bp = bp; |
8256 | } | |
35efa7c1 MC |
8257 | } |
8258 | ||
0421eae6 SH |
8259 | static const struct net_device_ops bnx2_netdev_ops = { |
8260 | .ndo_open = bnx2_open, | |
8261 | .ndo_start_xmit = bnx2_start_xmit, | |
8262 | .ndo_stop = bnx2_close, | |
8263 | .ndo_get_stats = bnx2_get_stats, | |
8264 | .ndo_set_rx_mode = bnx2_set_rx_mode, | |
8265 | .ndo_do_ioctl = bnx2_ioctl, | |
8266 | .ndo_validate_addr = eth_validate_addr, | |
8267 | .ndo_set_mac_address = bnx2_change_mac_addr, | |
8268 | .ndo_change_mtu = bnx2_change_mtu, | |
8269 | .ndo_tx_timeout = bnx2_tx_timeout, | |
8270 | #ifdef BCM_VLAN | |
8271 | .ndo_vlan_rx_register = bnx2_vlan_rx_register, | |
8272 | #endif | |
257ddbda | 8273 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0421eae6 SH |
8274 | .ndo_poll_controller = poll_bnx2, |
8275 | #endif | |
8276 | }; | |
8277 | ||
72dccb01 ED |
8278 | static void inline vlan_features_add(struct net_device *dev, unsigned long flags) |
8279 | { | |
8280 | #ifdef BCM_VLAN | |
8281 | dev->vlan_features |= flags; | |
8282 | #endif | |
8283 | } | |
8284 | ||
b6016b76 MC |
8285 | static int __devinit |
8286 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
8287 | { | |
8288 | static int version_printed = 0; | |
8289 | struct net_device *dev = NULL; | |
8290 | struct bnx2 *bp; | |
0795af57 | 8291 | int rc; |
883e5151 | 8292 | char str[40]; |
b6016b76 MC |
8293 | |
8294 | if (version_printed++ == 0) | |
8295 | printk(KERN_INFO "%s", version); | |
8296 | ||
8297 | /* dev zeroed in init_etherdev */ | |
706bf240 | 8298 | dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS); |
b6016b76 MC |
8299 | |
8300 | if (!dev) | |
8301 | return -ENOMEM; | |
8302 | ||
8303 | rc = bnx2_init_board(pdev, dev); | |
8304 | if (rc < 0) { | |
8305 | free_netdev(dev); | |
8306 | return rc; | |
8307 | } | |
8308 | ||
0421eae6 | 8309 | dev->netdev_ops = &bnx2_netdev_ops; |
b6016b76 | 8310 | dev->watchdog_timeo = TX_TIMEOUT; |
b6016b76 | 8311 | dev->ethtool_ops = &bnx2_ethtool_ops; |
b6016b76 | 8312 | |
972ec0d4 | 8313 | bp = netdev_priv(dev); |
35efa7c1 | 8314 | bnx2_init_napi(bp); |
b6016b76 | 8315 | |
1b2f922f MC |
8316 | pci_set_drvdata(pdev, dev); |
8317 | ||
57579f76 MC |
8318 | rc = bnx2_request_firmware(bp); |
8319 | if (rc) | |
8320 | goto error; | |
8321 | ||
1b2f922f MC |
8322 | memcpy(dev->dev_addr, bp->mac_addr, 6); |
8323 | memcpy(dev->perm_addr, bp->mac_addr, 6); | |
1b2f922f | 8324 | |
d212f87b | 8325 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
72dccb01 ED |
8326 | vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG); |
8327 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
d212f87b | 8328 | dev->features |= NETIF_F_IPV6_CSUM; |
72dccb01 ED |
8329 | vlan_features_add(dev, NETIF_F_IPV6_CSUM); |
8330 | } | |
1b2f922f MC |
8331 | #ifdef BCM_VLAN |
8332 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
8333 | #endif | |
8334 | dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; | |
72dccb01 ED |
8335 | vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN); |
8336 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
4666f87a | 8337 | dev->features |= NETIF_F_TSO6; |
72dccb01 ED |
8338 | vlan_features_add(dev, NETIF_F_TSO6); |
8339 | } | |
b6016b76 | 8340 | if ((rc = register_netdev(dev))) { |
9b91cf9d | 8341 | dev_err(&pdev->dev, "Cannot register net device\n"); |
57579f76 | 8342 | goto error; |
b6016b76 MC |
8343 | } |
8344 | ||
883e5151 | 8345 | printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " |
e174961c | 8346 | "IRQ %d, node addr %pM\n", |
b6016b76 | 8347 | dev->name, |
fbbf68b7 | 8348 | board_info[ent->driver_data].name, |
b6016b76 MC |
8349 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', |
8350 | ((CHIP_ID(bp) & 0x0ff0) >> 4), | |
883e5151 | 8351 | bnx2_bus_string(bp, str), |
b6016b76 | 8352 | dev->base_addr, |
e174961c | 8353 | bp->pdev->irq, dev->dev_addr); |
b6016b76 | 8354 | |
b6016b76 | 8355 | return 0; |
57579f76 MC |
8356 | |
8357 | error: | |
8358 | if (bp->mips_firmware) | |
8359 | release_firmware(bp->mips_firmware); | |
8360 | if (bp->rv2p_firmware) | |
8361 | release_firmware(bp->rv2p_firmware); | |
8362 | ||
8363 | if (bp->regview) | |
8364 | iounmap(bp->regview); | |
8365 | pci_release_regions(pdev); | |
8366 | pci_disable_device(pdev); | |
8367 | pci_set_drvdata(pdev, NULL); | |
8368 | free_netdev(dev); | |
8369 | return rc; | |
b6016b76 MC |
8370 | } |
8371 | ||
8372 | static void __devexit | |
8373 | bnx2_remove_one(struct pci_dev *pdev) | |
8374 | { | |
8375 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 8376 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 8377 | |
afdc08b9 MC |
8378 | flush_scheduled_work(); |
8379 | ||
b6016b76 MC |
8380 | unregister_netdev(dev); |
8381 | ||
57579f76 MC |
8382 | if (bp->mips_firmware) |
8383 | release_firmware(bp->mips_firmware); | |
8384 | if (bp->rv2p_firmware) | |
8385 | release_firmware(bp->rv2p_firmware); | |
8386 | ||
b6016b76 MC |
8387 | if (bp->regview) |
8388 | iounmap(bp->regview); | |
8389 | ||
354fcd77 MC |
8390 | kfree(bp->temp_stats_blk); |
8391 | ||
b6016b76 MC |
8392 | free_netdev(dev); |
8393 | pci_release_regions(pdev); | |
8394 | pci_disable_device(pdev); | |
8395 | pci_set_drvdata(pdev, NULL); | |
8396 | } | |
8397 | ||
8398 | static int | |
829ca9a3 | 8399 | bnx2_suspend(struct pci_dev *pdev, pm_message_t state) |
b6016b76 MC |
8400 | { |
8401 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 8402 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 8403 | |
6caebb02 MC |
8404 | /* PCI register 4 needs to be saved whether netif_running() or not. |
8405 | * MSI address and data need to be saved if using MSI and | |
8406 | * netif_running(). | |
8407 | */ | |
8408 | pci_save_state(pdev); | |
b6016b76 MC |
8409 | if (!netif_running(dev)) |
8410 | return 0; | |
8411 | ||
1d60290f | 8412 | flush_scheduled_work(); |
b6016b76 MC |
8413 | bnx2_netif_stop(bp); |
8414 | netif_device_detach(dev); | |
8415 | del_timer_sync(&bp->timer); | |
74bf4ba3 | 8416 | bnx2_shutdown_chip(bp); |
b6016b76 | 8417 | bnx2_free_skbs(bp); |
829ca9a3 | 8418 | bnx2_set_power_state(bp, pci_choose_state(pdev, state)); |
b6016b76 MC |
8419 | return 0; |
8420 | } | |
8421 | ||
8422 | static int | |
8423 | bnx2_resume(struct pci_dev *pdev) | |
8424 | { | |
8425 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 8426 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 8427 | |
6caebb02 | 8428 | pci_restore_state(pdev); |
b6016b76 MC |
8429 | if (!netif_running(dev)) |
8430 | return 0; | |
8431 | ||
829ca9a3 | 8432 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 | 8433 | netif_device_attach(dev); |
9a120bc5 | 8434 | bnx2_init_nic(bp, 1); |
b6016b76 MC |
8435 | bnx2_netif_start(bp); |
8436 | return 0; | |
8437 | } | |
8438 | ||
6ff2da49 WX |
8439 | /** |
8440 | * bnx2_io_error_detected - called when PCI error is detected | |
8441 | * @pdev: Pointer to PCI device | |
8442 | * @state: The current pci connection state | |
8443 | * | |
8444 | * This function is called after a PCI bus error affecting | |
8445 | * this device has been detected. | |
8446 | */ | |
8447 | static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev, | |
8448 | pci_channel_state_t state) | |
8449 | { | |
8450 | struct net_device *dev = pci_get_drvdata(pdev); | |
8451 | struct bnx2 *bp = netdev_priv(dev); | |
8452 | ||
8453 | rtnl_lock(); | |
8454 | netif_device_detach(dev); | |
8455 | ||
2ec3de26 DN |
8456 | if (state == pci_channel_io_perm_failure) { |
8457 | rtnl_unlock(); | |
8458 | return PCI_ERS_RESULT_DISCONNECT; | |
8459 | } | |
8460 | ||
6ff2da49 WX |
8461 | if (netif_running(dev)) { |
8462 | bnx2_netif_stop(bp); | |
8463 | del_timer_sync(&bp->timer); | |
8464 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); | |
8465 | } | |
8466 | ||
8467 | pci_disable_device(pdev); | |
8468 | rtnl_unlock(); | |
8469 | ||
8470 | /* Request a slot slot reset. */ | |
8471 | return PCI_ERS_RESULT_NEED_RESET; | |
8472 | } | |
8473 | ||
8474 | /** | |
8475 | * bnx2_io_slot_reset - called after the pci bus has been reset. | |
8476 | * @pdev: Pointer to PCI device | |
8477 | * | |
8478 | * Restart the card from scratch, as if from a cold-boot. | |
8479 | */ | |
8480 | static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev) | |
8481 | { | |
8482 | struct net_device *dev = pci_get_drvdata(pdev); | |
8483 | struct bnx2 *bp = netdev_priv(dev); | |
8484 | ||
8485 | rtnl_lock(); | |
8486 | if (pci_enable_device(pdev)) { | |
8487 | dev_err(&pdev->dev, | |
8488 | "Cannot re-enable PCI device after reset.\n"); | |
8489 | rtnl_unlock(); | |
8490 | return PCI_ERS_RESULT_DISCONNECT; | |
8491 | } | |
8492 | pci_set_master(pdev); | |
8493 | pci_restore_state(pdev); | |
529fab67 | 8494 | pci_save_state(pdev); |
6ff2da49 WX |
8495 | |
8496 | if (netif_running(dev)) { | |
8497 | bnx2_set_power_state(bp, PCI_D0); | |
8498 | bnx2_init_nic(bp, 1); | |
8499 | } | |
8500 | ||
8501 | rtnl_unlock(); | |
8502 | return PCI_ERS_RESULT_RECOVERED; | |
8503 | } | |
8504 | ||
8505 | /** | |
8506 | * bnx2_io_resume - called when traffic can start flowing again. | |
8507 | * @pdev: Pointer to PCI device | |
8508 | * | |
8509 | * This callback is called when the error recovery driver tells us that | |
8510 | * its OK to resume normal operation. | |
8511 | */ | |
8512 | static void bnx2_io_resume(struct pci_dev *pdev) | |
8513 | { | |
8514 | struct net_device *dev = pci_get_drvdata(pdev); | |
8515 | struct bnx2 *bp = netdev_priv(dev); | |
8516 | ||
8517 | rtnl_lock(); | |
8518 | if (netif_running(dev)) | |
8519 | bnx2_netif_start(bp); | |
8520 | ||
8521 | netif_device_attach(dev); | |
8522 | rtnl_unlock(); | |
8523 | } | |
8524 | ||
8525 | static struct pci_error_handlers bnx2_err_handler = { | |
8526 | .error_detected = bnx2_io_error_detected, | |
8527 | .slot_reset = bnx2_io_slot_reset, | |
8528 | .resume = bnx2_io_resume, | |
8529 | }; | |
8530 | ||
b6016b76 | 8531 | static struct pci_driver bnx2_pci_driver = { |
14ab9b86 PH |
8532 | .name = DRV_MODULE_NAME, |
8533 | .id_table = bnx2_pci_tbl, | |
8534 | .probe = bnx2_init_one, | |
8535 | .remove = __devexit_p(bnx2_remove_one), | |
8536 | .suspend = bnx2_suspend, | |
8537 | .resume = bnx2_resume, | |
6ff2da49 | 8538 | .err_handler = &bnx2_err_handler, |
b6016b76 MC |
8539 | }; |
8540 | ||
8541 | static int __init bnx2_init(void) | |
8542 | { | |
29917620 | 8543 | return pci_register_driver(&bnx2_pci_driver); |
b6016b76 MC |
8544 | } |
8545 | ||
8546 | static void __exit bnx2_cleanup(void) | |
8547 | { | |
8548 | pci_unregister_driver(&bnx2_pci_driver); | |
8549 | } | |
8550 | ||
8551 | module_init(bnx2_init); | |
8552 | module_exit(bnx2_cleanup); | |
8553 | ||
8554 | ||
8555 |