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[PATCH] bnx2: update nvram code for 5708
[mirror_ubuntu-jammy-kernel.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12#include "bnx2.h"
13#include "bnx2_fw.h"
14
15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": "
c921e4c4
MC		 17#define DRV_MODULE_VERSION "1.2.21"
18#define DRV_MODULE_RELDATE "September 7, 2005"
b6016b76
MC		 19
20#define RUN_AT(x) (jiffies + (x))
21
22/* Time in jiffies before concluding the transmitter is hung. */
23#define TX_TIMEOUT (5*HZ)
24
25static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30MODULE_LICENSE("GPL");
31MODULE_VERSION(DRV_MODULE_VERSION);
32
33static int disable_msi = 0;
34
35module_param(disable_msi, int, 0);
36MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
5b0c76ad
MC		 44 BCM5708,
45 BCM5708S,
b6016b76
MC		 46} board_t;
47
48/* indexed by board_t, above */
49static struct {
50 char *name;
51} board_info[] __devinitdata = {
52 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
53 { "HP NC370T Multifunction Gigabit Server Adapter" },
54 { "HP NC370i Multifunction Gigabit Server Adapter" },
55 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
56 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 57 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
b6016b76
MC		 59 };
60
61static struct pci_device_id bnx2_pci_tbl[] = {
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
65 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 68 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 70 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
71 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
72 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 74 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
b6016b76
MC		 76 { 0, }
77};
78
79static struct flash_spec flash_table[] =
80{
81 /* Slow EEPROM */
37137709 82 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
b6016b76
MC		 83 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
84 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
85 "EEPROM - slow"},
37137709
MC		 86 /* Expansion entry 0001 */
87 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76 88 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 89 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
90 "Entry 0001"},
b6016b76
MC		 91 /* Saifun SA25F010 (non-buffered flash) */
92 /* strap, cfg1, & write1 need updates */
37137709 93 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 94 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
95 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
96 "Non-buffered flash (128kB)"},
97 /* Saifun SA25F020 (non-buffered flash) */
98 /* strap, cfg1, & write1 need updates */
37137709 99 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 100 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
101 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
102 "Non-buffered flash (256kB)"},
37137709
MC		 103 /* Expansion entry 0100 */
104 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
105 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
107 "Entry 0100"},
108 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
109 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
110 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
111 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
112 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
113 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
114 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
115 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
116 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
117 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
118 /* Saifun SA25F005 (non-buffered flash) */
119 /* strap, cfg1, & write1 need updates */
120 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
121 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
122 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
123 "Non-buffered flash (64kB)"},
124 /* Fast EEPROM */
125 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
126 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
127 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128 "EEPROM - fast"},
129 /* Expansion entry 1001 */
130 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
131 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
132 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133 "Entry 1001"},
134 /* Expansion entry 1010 */
135 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138 "Entry 1010"},
139 /* ATMEL AT45DB011B (buffered flash) */
140 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
141 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
142 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
143 "Buffered flash (128kB)"},
144 /* Expansion entry 1100 */
145 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 "Entry 1100"},
149 /* Expansion entry 1101 */
150 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
151 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
153 "Entry 1101"},
154 /* Ateml Expansion entry 1110 */
155 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
156 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
157 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
158 "Entry 1110 (Atmel)"},
159 /* ATMEL AT45DB021B (buffered flash) */
160 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
161 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
162 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
163 "Buffered flash (256kB)"},
b6016b76
MC		 164};
165
166MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
167
e89bbf10
MC		 168static inline u32 bnx2_tx_avail(struct bnx2 *bp)
169{
170 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
171
172 if (diff > MAX_TX_DESC_CNT)
173 diff = (diff & MAX_TX_DESC_CNT) - 1;
174 return (bp->tx_ring_size - diff);
175}
176
b6016b76
MC		 177static u32
178bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
179{
180 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
181 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
182}
183
184static void
185bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
186{
187 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
188 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
189}
190
191static void
192bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
193{
194 offset += cid_addr;
195 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
196 REG_WR(bp, BNX2_CTX_DATA, val);
197}
198
199static int
200bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
201{
202 u32 val1;
203 int i, ret;
204
205 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
206 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
207 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
208
209 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
210 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
211
212 udelay(40);
213 }
214
215 val1 = (bp->phy_addr << 21) | (reg << 16) |
216 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
217 BNX2_EMAC_MDIO_COMM_START_BUSY;
218 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
219
220 for (i = 0; i < 50; i++) {
221 udelay(10);
222
223 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
224 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
225 udelay(5);
226
227 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
228 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
229
230 break;
231 }
232 }
233
234 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
235 *val = 0x0;
236 ret = -EBUSY;
237 }
238 else {
239 *val = val1;
240 ret = 0;
241 }
242
243 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
244 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
245 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
246
247 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
248 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249
250 udelay(40);
251 }
252
253 return ret;
254}
255
256static int
257bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
258{
259 u32 val1;
260 int i, ret;
261
262 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
263 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
264 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
265
266 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
267 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
268
269 udelay(40);
270 }
271
272 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
273 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
274 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
275 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
276
277 for (i = 0; i < 50; i++) {
278 udelay(10);
279
280 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
281 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
282 udelay(5);
283 break;
284 }
285 }
286
287 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
288 ret = -EBUSY;
289 else
290 ret = 0;
291
292 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
293 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
294 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
295
296 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
297 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
298
299 udelay(40);
300 }
301
302 return ret;
303}
304
305static void
306bnx2_disable_int(struct bnx2 *bp)
307{
308 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
309 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
310 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
311}
312
313static void
314bnx2_enable_int(struct bnx2 *bp)
315{
316 u32 val;
317
318 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
320
321 val = REG_RD(bp, BNX2_HC_COMMAND);
322 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
323}
324
325static void
326bnx2_disable_int_sync(struct bnx2 *bp)
327{
328 atomic_inc(&bp->intr_sem);
329 bnx2_disable_int(bp);
330 synchronize_irq(bp->pdev->irq);
331}
332
333static void
334bnx2_netif_stop(struct bnx2 *bp)
335{
336 bnx2_disable_int_sync(bp);
337 if (netif_running(bp->dev)) {
338 netif_poll_disable(bp->dev);
339 netif_tx_disable(bp->dev);
340 bp->dev->trans_start = jiffies; /* prevent tx timeout */
341 }
342}
343
344static void
345bnx2_netif_start(struct bnx2 *bp)
346{
347 if (atomic_dec_and_test(&bp->intr_sem)) {
348 if (netif_running(bp->dev)) {
349 netif_wake_queue(bp->dev);
350 netif_poll_enable(bp->dev);
351 bnx2_enable_int(bp);
352 }
353 }
354}
355
356static void
357bnx2_free_mem(struct bnx2 *bp)
358{
359 if (bp->stats_blk) {
360 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
361 bp->stats_blk, bp->stats_blk_mapping);
362 bp->stats_blk = NULL;
363 }
364 if (bp->status_blk) {
365 pci_free_consistent(bp->pdev, sizeof(struct status_block),
366 bp->status_blk, bp->status_blk_mapping);
367 bp->status_blk = NULL;
368 }
369 if (bp->tx_desc_ring) {
370 pci_free_consistent(bp->pdev,
371 sizeof(struct tx_bd) * TX_DESC_CNT,
372 bp->tx_desc_ring, bp->tx_desc_mapping);
373 bp->tx_desc_ring = NULL;
374 }
b4558ea9
JJ		 375 kfree(bp->tx_buf_ring);
376 bp->tx_buf_ring = NULL;
b6016b76
MC		 377 if (bp->rx_desc_ring) {
378 pci_free_consistent(bp->pdev,
379 sizeof(struct rx_bd) * RX_DESC_CNT,
380 bp->rx_desc_ring, bp->rx_desc_mapping);
381 bp->rx_desc_ring = NULL;
382 }
b4558ea9
JJ		 383 kfree(bp->rx_buf_ring);
384 bp->rx_buf_ring = NULL;
b6016b76
MC		 385}
386
387static int
388bnx2_alloc_mem(struct bnx2 *bp)
389{
390 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
391 GFP_KERNEL);
392 if (bp->tx_buf_ring == NULL)
393 return -ENOMEM;
394
395 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
396 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
397 sizeof(struct tx_bd) *
398 TX_DESC_CNT,
399 &bp->tx_desc_mapping);
400 if (bp->tx_desc_ring == NULL)
401 goto alloc_mem_err;
402
403 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
404 GFP_KERNEL);
405 if (bp->rx_buf_ring == NULL)
406 goto alloc_mem_err;
407
408 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
409 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
410 sizeof(struct rx_bd) *
411 RX_DESC_CNT,
412 &bp->rx_desc_mapping);
413 if (bp->rx_desc_ring == NULL)
414 goto alloc_mem_err;
415
416 bp->status_blk = pci_alloc_consistent(bp->pdev,
417 sizeof(struct status_block),
418 &bp->status_blk_mapping);
419 if (bp->status_blk == NULL)
420 goto alloc_mem_err;
421
422 memset(bp->status_blk, 0, sizeof(struct status_block));
423
424 bp->stats_blk = pci_alloc_consistent(bp->pdev,
425 sizeof(struct statistics_block),
426 &bp->stats_blk_mapping);
427 if (bp->stats_blk == NULL)
428 goto alloc_mem_err;
429
430 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
431
432 return 0;
433
434alloc_mem_err:
435 bnx2_free_mem(bp);
436 return -ENOMEM;
437}
438
439static void
440bnx2_report_link(struct bnx2 *bp)
441{
442 if (bp->link_up) {
443 netif_carrier_on(bp->dev);
444 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
445
446 printk("%d Mbps ", bp->line_speed);
447
448 if (bp->duplex == DUPLEX_FULL)
449 printk("full duplex");
450 else
451 printk("half duplex");
452
453 if (bp->flow_ctrl) {
454 if (bp->flow_ctrl & FLOW_CTRL_RX) {
455 printk(", receive ");
456 if (bp->flow_ctrl & FLOW_CTRL_TX)
457 printk("& transmit ");
458 }
459 else {
460 printk(", transmit ");
461 }
462 printk("flow control ON");
463 }
464 printk("\n");
465 }
466 else {
467 netif_carrier_off(bp->dev);
468 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
469 }
470}
471
472static void
473bnx2_resolve_flow_ctrl(struct bnx2 *bp)
474{
475 u32 local_adv, remote_adv;
476
477 bp->flow_ctrl = 0;
478 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
479 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
480
481 if (bp->duplex == DUPLEX_FULL) {
482 bp->flow_ctrl = bp->req_flow_ctrl;
483 }
484 return;
485 }
486
487 if (bp->duplex != DUPLEX_FULL) {
488 return;
489 }
490
5b0c76ad
MC		 491 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
492 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
493 u32 val;
494
495 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
496 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
497 bp->flow_ctrl |= FLOW_CTRL_TX;
498 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
499 bp->flow_ctrl |= FLOW_CTRL_RX;
500 return;
501 }
502
b6016b76
MC		 503 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
504 bnx2_read_phy(bp, MII_LPA, &remote_adv);
505
506 if (bp->phy_flags & PHY_SERDES_FLAG) {
507 u32 new_local_adv = 0;
508 u32 new_remote_adv = 0;
509
510 if (local_adv & ADVERTISE_1000XPAUSE)
511 new_local_adv |= ADVERTISE_PAUSE_CAP;
512 if (local_adv & ADVERTISE_1000XPSE_ASYM)
513 new_local_adv |= ADVERTISE_PAUSE_ASYM;
514 if (remote_adv & ADVERTISE_1000XPAUSE)
515 new_remote_adv |= ADVERTISE_PAUSE_CAP;
516 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
517 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
518
519 local_adv = new_local_adv;
520 remote_adv = new_remote_adv;
521 }
522
523 /* See Table 28B-3 of 802.3ab-1999 spec. */
524 if (local_adv & ADVERTISE_PAUSE_CAP) {
525 if(local_adv & ADVERTISE_PAUSE_ASYM) {
526 if (remote_adv & ADVERTISE_PAUSE_CAP) {
527 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
528 }
529 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
530 bp->flow_ctrl = FLOW_CTRL_RX;
531 }
532 }
533 else {
534 if (remote_adv & ADVERTISE_PAUSE_CAP) {
535 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
536 }
537 }
538 }
539 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
540 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
541 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
542
543 bp->flow_ctrl = FLOW_CTRL_TX;
544 }
545 }
546}
547
548static int
5b0c76ad
MC		 549bnx2_5708s_linkup(struct bnx2 *bp)
550{
551 u32 val;
552
553 bp->link_up = 1;
554 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
555 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
556 case BCM5708S_1000X_STAT1_SPEED_10:
557 bp->line_speed = SPEED_10;
558 break;
559 case BCM5708S_1000X_STAT1_SPEED_100:
560 bp->line_speed = SPEED_100;
561 break;
562 case BCM5708S_1000X_STAT1_SPEED_1G:
563 bp->line_speed = SPEED_1000;
564 break;
565 case BCM5708S_1000X_STAT1_SPEED_2G5:
566 bp->line_speed = SPEED_2500;
567 break;
568 }
569 if (val & BCM5708S_1000X_STAT1_FD)
570 bp->duplex = DUPLEX_FULL;
571 else
572 bp->duplex = DUPLEX_HALF;
573
574 return 0;
575}
576
577static int
578bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 579{
580 u32 bmcr, local_adv, remote_adv, common;
581
582 bp->link_up = 1;
583 bp->line_speed = SPEED_1000;
584
585 bnx2_read_phy(bp, MII_BMCR, &bmcr);
586 if (bmcr & BMCR_FULLDPLX) {
587 bp->duplex = DUPLEX_FULL;
588 }
589 else {
590 bp->duplex = DUPLEX_HALF;
591 }
592
593 if (!(bmcr & BMCR_ANENABLE)) {
594 return 0;
595 }
596
597 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
598 bnx2_read_phy(bp, MII_LPA, &remote_adv);
599
600 common = local_adv & remote_adv;
601 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
602
603 if (common & ADVERTISE_1000XFULL) {
604 bp->duplex = DUPLEX_FULL;
605 }
606 else {
607 bp->duplex = DUPLEX_HALF;
608 }
609 }
610
611 return 0;
612}
613
614static int
615bnx2_copper_linkup(struct bnx2 *bp)
616{
617 u32 bmcr;
618
619 bnx2_read_phy(bp, MII_BMCR, &bmcr);
620 if (bmcr & BMCR_ANENABLE) {
621 u32 local_adv, remote_adv, common;
622
623 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
624 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
625
626 common = local_adv & (remote_adv >> 2);
627 if (common & ADVERTISE_1000FULL) {
628 bp->line_speed = SPEED_1000;
629 bp->duplex = DUPLEX_FULL;
630 }
631 else if (common & ADVERTISE_1000HALF) {
632 bp->line_speed = SPEED_1000;
633 bp->duplex = DUPLEX_HALF;
634 }
635 else {
636 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
637 bnx2_read_phy(bp, MII_LPA, &remote_adv);
638
639 common = local_adv & remote_adv;
640 if (common & ADVERTISE_100FULL) {
641 bp->line_speed = SPEED_100;
642 bp->duplex = DUPLEX_FULL;
643 }
644 else if (common & ADVERTISE_100HALF) {
645 bp->line_speed = SPEED_100;
646 bp->duplex = DUPLEX_HALF;
647 }
648 else if (common & ADVERTISE_10FULL) {
649 bp->line_speed = SPEED_10;
650 bp->duplex = DUPLEX_FULL;
651 }
652 else if (common & ADVERTISE_10HALF) {
653 bp->line_speed = SPEED_10;
654 bp->duplex = DUPLEX_HALF;
655 }
656 else {
657 bp->line_speed = 0;
658 bp->link_up = 0;
659 }
660 }
661 }
662 else {
663 if (bmcr & BMCR_SPEED100) {
664 bp->line_speed = SPEED_100;
665 }
666 else {
667 bp->line_speed = SPEED_10;
668 }
669 if (bmcr & BMCR_FULLDPLX) {
670 bp->duplex = DUPLEX_FULL;
671 }
672 else {
673 bp->duplex = DUPLEX_HALF;
674 }
675 }
676
677 return 0;
678}
679
680static int
681bnx2_set_mac_link(struct bnx2 *bp)
682{
683 u32 val;
684
685 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
686 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
687 (bp->duplex == DUPLEX_HALF)) {
688 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
689 }
690
691 /* Configure the EMAC mode register. */
692 val = REG_RD(bp, BNX2_EMAC_MODE);
693
694 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad
MC		 695 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
696 BNX2_EMAC_MODE_25G);
b6016b76
MC		 697
698 if (bp->link_up) {
5b0c76ad
MC		 699 switch (bp->line_speed) {
700 case SPEED_10:
701 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
702 val |= BNX2_EMAC_MODE_PORT_MII_10;
703 break;
704 }
705 /* fall through */
706 case SPEED_100:
707 val |= BNX2_EMAC_MODE_PORT_MII;
708 break;
709 case SPEED_2500:
710 val |= BNX2_EMAC_MODE_25G;
711 /* fall through */
712 case SPEED_1000:
713 val |= BNX2_EMAC_MODE_PORT_GMII;
714 break;
715 }
b6016b76
MC		 716 }
717 else {
718 val |= BNX2_EMAC_MODE_PORT_GMII;
719 }
720
721 /* Set the MAC to operate in the appropriate duplex mode. */
722 if (bp->duplex == DUPLEX_HALF)
723 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
724 REG_WR(bp, BNX2_EMAC_MODE, val);
725
726 /* Enable/disable rx PAUSE. */
727 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
728
729 if (bp->flow_ctrl & FLOW_CTRL_RX)
730 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
731 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
732
733 /* Enable/disable tx PAUSE. */
734 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
735 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
736
737 if (bp->flow_ctrl & FLOW_CTRL_TX)
738 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
739 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
740
741 /* Acknowledge the interrupt. */
742 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
743
744 return 0;
745}
746
747static int
748bnx2_set_link(struct bnx2 *bp)
749{
750 u32 bmsr;
751 u8 link_up;
752
753 if (bp->loopback == MAC_LOOPBACK) {
754 bp->link_up = 1;
755 return 0;
756 }
757
758 link_up = bp->link_up;
759
760 bnx2_read_phy(bp, MII_BMSR, &bmsr);
761 bnx2_read_phy(bp, MII_BMSR, &bmsr);
762
763 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
764 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
765 u32 val;
766
767 val = REG_RD(bp, BNX2_EMAC_STATUS);
768 if (val & BNX2_EMAC_STATUS_LINK)
769 bmsr |= BMSR_LSTATUS;
770 else
771 bmsr &= ~BMSR_LSTATUS;
772 }
773
774 if (bmsr & BMSR_LSTATUS) {
775 bp->link_up = 1;
776
777 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 778 if (CHIP_NUM(bp) == CHIP_NUM_5706)
779 bnx2_5706s_linkup(bp);
780 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
781 bnx2_5708s_linkup(bp);
b6016b76
MC		 782 }
783 else {
784 bnx2_copper_linkup(bp);
785 }
786 bnx2_resolve_flow_ctrl(bp);
787 }
788 else {
789 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
790 (bp->autoneg & AUTONEG_SPEED)) {
791
792 u32 bmcr;
793
794 bnx2_read_phy(bp, MII_BMCR, &bmcr);
795 if (!(bmcr & BMCR_ANENABLE)) {
796 bnx2_write_phy(bp, MII_BMCR, bmcr |
797 BMCR_ANENABLE);
798 }
799 }
800 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
801 bp->link_up = 0;
802 }
803
804 if (bp->link_up != link_up) {
805 bnx2_report_link(bp);
806 }
807
808 bnx2_set_mac_link(bp);
809
810 return 0;
811}
812
813static int
814bnx2_reset_phy(struct bnx2 *bp)
815{
816 int i;
817 u32 reg;
818
819 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
820
821#define PHY_RESET_MAX_WAIT 100
822 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
823 udelay(10);
824
825 bnx2_read_phy(bp, MII_BMCR, &reg);
826 if (!(reg & BMCR_RESET)) {
827 udelay(20);
828 break;
829 }
830 }
831 if (i == PHY_RESET_MAX_WAIT) {
832 return -EBUSY;
833 }
834 return 0;
835}
836
837static u32
838bnx2_phy_get_pause_adv(struct bnx2 *bp)
839{
840 u32 adv = 0;
841
842 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
843 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
844
845 if (bp->phy_flags & PHY_SERDES_FLAG) {
846 adv = ADVERTISE_1000XPAUSE;
847 }
848 else {
849 adv = ADVERTISE_PAUSE_CAP;
850 }
851 }
852 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
853 if (bp->phy_flags & PHY_SERDES_FLAG) {
854 adv = ADVERTISE_1000XPSE_ASYM;
855 }
856 else {
857 adv = ADVERTISE_PAUSE_ASYM;
858 }
859 }
860 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
861 if (bp->phy_flags & PHY_SERDES_FLAG) {
862 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
863 }
864 else {
865 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
866 }
867 }
868 return adv;
869}
870
871static int
872bnx2_setup_serdes_phy(struct bnx2 *bp)
873{
5b0c76ad 874 u32 adv, bmcr, up1;
b6016b76
MC		 875 u32 new_adv = 0;
876
877 if (!(bp->autoneg & AUTONEG_SPEED)) {
878 u32 new_bmcr;
5b0c76ad
MC		 879 int force_link_down = 0;
880
881 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
882 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
883 if (up1 & BCM5708S_UP1_2G5) {
884 up1 &= ~BCM5708S_UP1_2G5;
885 bnx2_write_phy(bp, BCM5708S_UP1, up1);
886 force_link_down = 1;
887 }
888 }
889
890 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
891 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
b6016b76
MC		 892
893 bnx2_read_phy(bp, MII_BMCR, &bmcr);
894 new_bmcr = bmcr & ~BMCR_ANENABLE;
895 new_bmcr |= BMCR_SPEED1000;
896 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 897 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 898 new_bmcr |= BMCR_FULLDPLX;
899 }
900 else {
5b0c76ad 901 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 902 new_bmcr &= ~BMCR_FULLDPLX;
903 }
5b0c76ad 904 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 905 /* Force a link down visible on the other side */
906 if (bp->link_up) {
5b0c76ad
MC		 907 bnx2_write_phy(bp, MII_ADVERTISE, adv &
908 ~(ADVERTISE_1000XFULL |
909 ADVERTISE_1000XHALF));
b6016b76
MC		 910 bnx2_write_phy(bp, MII_BMCR, bmcr |
911 BMCR_ANRESTART | BMCR_ANENABLE);
912
913 bp->link_up = 0;
914 netif_carrier_off(bp->dev);
5b0c76ad 915 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
b6016b76 916 }
5b0c76ad 917 bnx2_write_phy(bp, MII_ADVERTISE, adv);
b6016b76
MC		 918 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
919 }
920 return 0;
921 }
922
5b0c76ad
MC		 923 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
924 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
925 up1 |= BCM5708S_UP1_2G5;
926 bnx2_write_phy(bp, BCM5708S_UP1, up1);
927 }
928
b6016b76
MC		 929 if (bp->advertising & ADVERTISED_1000baseT_Full)
930 new_adv |= ADVERTISE_1000XFULL;
931
932 new_adv |= bnx2_phy_get_pause_adv(bp);
933
934 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
935 bnx2_read_phy(bp, MII_BMCR, &bmcr);
936
937 bp->serdes_an_pending = 0;
938 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
939 /* Force a link down visible on the other side */
940 if (bp->link_up) {
941 int i;
942
943 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
944 for (i = 0; i < 110; i++) {
945 udelay(100);
946 }
947 }
948
949 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
950 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
951 BMCR_ANENABLE);
cd339a0e
MC		 952 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
953 /* Speed up link-up time when the link partner
954 * does not autonegotiate which is very common
955 * in blade servers. Some blade servers use
956 * IPMI for kerboard input and it's important
957 * to minimize link disruptions. Autoneg. involves
958 * exchanging base pages plus 3 next pages and
959 * normally completes in about 120 msec.
960 */
961 bp->current_interval = SERDES_AN_TIMEOUT;
962 bp->serdes_an_pending = 1;
963 mod_timer(&bp->timer, jiffies + bp->current_interval);
964 }
b6016b76
MC		 965 }
966
967 return 0;
968}
969
970#define ETHTOOL_ALL_FIBRE_SPEED \
971 (ADVERTISED_1000baseT_Full)
972
973#define ETHTOOL_ALL_COPPER_SPEED \
974 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
975 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
976 ADVERTISED_1000baseT_Full)
977
978#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
979 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
980
981#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
982
983static int
984bnx2_setup_copper_phy(struct bnx2 *bp)
985{
986 u32 bmcr;
987 u32 new_bmcr;
988
989 bnx2_read_phy(bp, MII_BMCR, &bmcr);
990
991 if (bp->autoneg & AUTONEG_SPEED) {
992 u32 adv_reg, adv1000_reg;
993 u32 new_adv_reg = 0;
994 u32 new_adv1000_reg = 0;
995
996 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
997 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
998 ADVERTISE_PAUSE_ASYM);
999
1000 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1001 adv1000_reg &= PHY_ALL_1000_SPEED;
1002
1003 if (bp->advertising & ADVERTISED_10baseT_Half)
1004 new_adv_reg |= ADVERTISE_10HALF;
1005 if (bp->advertising & ADVERTISED_10baseT_Full)
1006 new_adv_reg |= ADVERTISE_10FULL;
1007 if (bp->advertising & ADVERTISED_100baseT_Half)
1008 new_adv_reg |= ADVERTISE_100HALF;
1009 if (bp->advertising & ADVERTISED_100baseT_Full)
1010 new_adv_reg |= ADVERTISE_100FULL;
1011 if (bp->advertising & ADVERTISED_1000baseT_Full)
1012 new_adv1000_reg |= ADVERTISE_1000FULL;
1013
1014 new_adv_reg |= ADVERTISE_CSMA;
1015
1016 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1017
1018 if ((adv1000_reg != new_adv1000_reg) ||
1019 (adv_reg != new_adv_reg) ||
1020 ((bmcr & BMCR_ANENABLE) == 0)) {
1021
1022 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1023 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1024 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1025 BMCR_ANENABLE);
1026 }
1027 else if (bp->link_up) {
1028 /* Flow ctrl may have changed from auto to forced */
1029 /* or vice-versa. */
1030
1031 bnx2_resolve_flow_ctrl(bp);
1032 bnx2_set_mac_link(bp);
1033 }
1034 return 0;
1035 }
1036
1037 new_bmcr = 0;
1038 if (bp->req_line_speed == SPEED_100) {
1039 new_bmcr |= BMCR_SPEED100;
1040 }
1041 if (bp->req_duplex == DUPLEX_FULL) {
1042 new_bmcr |= BMCR_FULLDPLX;
1043 }
1044 if (new_bmcr != bmcr) {
1045 u32 bmsr;
1046 int i = 0;
1047
1048 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1049 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1050
1051 if (bmsr & BMSR_LSTATUS) {
1052 /* Force link down */
1053 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1054 do {
1055 udelay(100);
1056 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1057 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1058 i++;
1059 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1060 }
1061
1062 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1063
1064 /* Normally, the new speed is setup after the link has
1065 * gone down and up again. In some cases, link will not go
1066 * down so we need to set up the new speed here.
1067 */
1068 if (bmsr & BMSR_LSTATUS) {
1069 bp->line_speed = bp->req_line_speed;
1070 bp->duplex = bp->req_duplex;
1071 bnx2_resolve_flow_ctrl(bp);
1072 bnx2_set_mac_link(bp);
1073 }
1074 }
1075 return 0;
1076}
1077
1078static int
1079bnx2_setup_phy(struct bnx2 *bp)
1080{
1081 if (bp->loopback == MAC_LOOPBACK)
1082 return 0;
1083
1084 if (bp->phy_flags & PHY_SERDES_FLAG) {
1085 return (bnx2_setup_serdes_phy(bp));
1086 }
1087 else {
1088 return (bnx2_setup_copper_phy(bp));
1089 }
1090}
1091
1092static int
5b0c76ad
MC		 1093bnx2_init_5708s_phy(struct bnx2 *bp)
1094{
1095 u32 val;
1096
1097 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1098 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1099 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1100
1101 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1102 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1103 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1104
1105 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1106 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1107 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1108
1109 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1110 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1111 val |= BCM5708S_UP1_2G5;
1112 bnx2_write_phy(bp, BCM5708S_UP1, val);
1113 }
1114
1115 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1116 (CHIP_ID(bp) == CHIP_ID_5708_B0)) {
1117 /* increase tx signal amplitude */
1118 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1119 BCM5708S_BLK_ADDR_TX_MISC);
1120 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1121 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1122 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1123 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1124 }
1125
1126 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_CONFIG) &
1127 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1128
1129 if (val) {
1130 u32 is_backplane;
1131
1132 is_backplane = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
1133 BNX2_SHARED_HW_CFG_CONFIG);
1134 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1135 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1136 BCM5708S_BLK_ADDR_TX_MISC);
1137 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1138 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1139 BCM5708S_BLK_ADDR_DIG);
1140 }
1141 }
1142 return 0;
1143}
1144
1145static int
1146bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76
MC		 1147{
1148 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1149
1150 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1151 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1152 }
1153
1154 if (bp->dev->mtu > 1500) {
1155 u32 val;
1156
1157 /* Set extended packet length bit */
1158 bnx2_write_phy(bp, 0x18, 0x7);
1159 bnx2_read_phy(bp, 0x18, &val);
1160 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1161
1162 bnx2_write_phy(bp, 0x1c, 0x6c00);
1163 bnx2_read_phy(bp, 0x1c, &val);
1164 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1165 }
1166 else {
1167 u32 val;
1168
1169 bnx2_write_phy(bp, 0x18, 0x7);
1170 bnx2_read_phy(bp, 0x18, &val);
1171 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1172
1173 bnx2_write_phy(bp, 0x1c, 0x6c00);
1174 bnx2_read_phy(bp, 0x1c, &val);
1175 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1176 }
1177
1178 return 0;
1179}
1180
1181static int
1182bnx2_init_copper_phy(struct bnx2 *bp)
1183{
5b0c76ad
MC		 1184 u32 val;
1185
b6016b76
MC		 1186 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1187
1188 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1189 bnx2_write_phy(bp, 0x18, 0x0c00);
1190 bnx2_write_phy(bp, 0x17, 0x000a);
1191 bnx2_write_phy(bp, 0x15, 0x310b);
1192 bnx2_write_phy(bp, 0x17, 0x201f);
1193 bnx2_write_phy(bp, 0x15, 0x9506);
1194 bnx2_write_phy(bp, 0x17, 0x401f);
1195 bnx2_write_phy(bp, 0x15, 0x14e2);
1196 bnx2_write_phy(bp, 0x18, 0x0400);
1197 }
1198
1199 if (bp->dev->mtu > 1500) {
b6016b76
MC		 1200 /* Set extended packet length bit */
1201 bnx2_write_phy(bp, 0x18, 0x7);
1202 bnx2_read_phy(bp, 0x18, &val);
1203 bnx2_write_phy(bp, 0x18, val | 0x4000);
1204
1205 bnx2_read_phy(bp, 0x10, &val);
1206 bnx2_write_phy(bp, 0x10, val | 0x1);
1207 }
1208 else {
b6016b76
MC		 1209 bnx2_write_phy(bp, 0x18, 0x7);
1210 bnx2_read_phy(bp, 0x18, &val);
1211 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1212
1213 bnx2_read_phy(bp, 0x10, &val);
1214 bnx2_write_phy(bp, 0x10, val & ~0x1);
1215 }
1216
5b0c76ad
MC		 1217 /* ethernet@wirespeed */
1218 bnx2_write_phy(bp, 0x18, 0x7007);
1219 bnx2_read_phy(bp, 0x18, &val);
1220 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 1221 return 0;
1222}
1223
1224
1225static int
1226bnx2_init_phy(struct bnx2 *bp)
1227{
1228 u32 val;
1229 int rc = 0;
1230
1231 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1232 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1233
1234 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1235
1236 bnx2_reset_phy(bp);
1237
1238 bnx2_read_phy(bp, MII_PHYSID1, &val);
1239 bp->phy_id = val << 16;
1240 bnx2_read_phy(bp, MII_PHYSID2, &val);
1241 bp->phy_id |= val & 0xffff;
1242
1243 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 1244 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1245 rc = bnx2_init_5706s_phy(bp);
1246 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1247 rc = bnx2_init_5708s_phy(bp);
b6016b76
MC		 1248 }
1249 else {
1250 rc = bnx2_init_copper_phy(bp);
1251 }
1252
1253 bnx2_setup_phy(bp);
1254
1255 return rc;
1256}
1257
1258static int
1259bnx2_set_mac_loopback(struct bnx2 *bp)
1260{
1261 u32 mac_mode;
1262
1263 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1264 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1265 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1266 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1267 bp->link_up = 1;
1268 return 0;
1269}
1270
1271static int
1272bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1273{
1274 int i;
1275 u32 val;
1276
1277 if (bp->fw_timed_out)
1278 return -EBUSY;
1279
1280 bp->fw_wr_seq++;
1281 msg_data |= bp->fw_wr_seq;
1282
1283 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1284
1285 /* wait for an acknowledgement. */
1286 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1287 udelay(5);
1288
1289 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1290
1291 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1292 break;
1293 }
1294
1295 /* If we timed out, inform the firmware that this is the case. */
1296 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1297 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1298
1299 msg_data &= ~BNX2_DRV_MSG_CODE;
1300 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1301
1302 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1303
1304 bp->fw_timed_out = 1;
1305
1306 return -EBUSY;
1307 }
1308
1309 return 0;
1310}
1311
1312static void
1313bnx2_init_context(struct bnx2 *bp)
1314{
1315 u32 vcid;
1316
1317 vcid = 96;
1318 while (vcid) {
1319 u32 vcid_addr, pcid_addr, offset;
1320
1321 vcid--;
1322
1323 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1324 u32 new_vcid;
1325
1326 vcid_addr = GET_PCID_ADDR(vcid);
1327 if (vcid & 0x8) {
1328 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1329 }
1330 else {
1331 new_vcid = vcid;
1332 }
1333 pcid_addr = GET_PCID_ADDR(new_vcid);
1334 }
1335 else {
1336 vcid_addr = GET_CID_ADDR(vcid);
1337 pcid_addr = vcid_addr;
1338 }
1339
1340 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1341 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1342
1343 /* Zero out the context. */
1344 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1345 CTX_WR(bp, 0x00, offset, 0);
1346 }
1347
1348 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1349 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1350 }
1351}
1352
1353static int
1354bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1355{
1356 u16 *good_mbuf;
1357 u32 good_mbuf_cnt;
1358 u32 val;
1359
1360 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1361 if (good_mbuf == NULL) {
1362 printk(KERN_ERR PFX "Failed to allocate memory in "
1363 "bnx2_alloc_bad_rbuf\n");
1364 return -ENOMEM;
1365 }
1366
1367 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1368 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1369
1370 good_mbuf_cnt = 0;
1371
1372 /* Allocate a bunch of mbufs and save the good ones in an array. */
1373 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1374 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1375 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1376
1377 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1378
1379 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1380
1381 /* The addresses with Bit 9 set are bad memory blocks. */
1382 if (!(val & (1 << 9))) {
1383 good_mbuf[good_mbuf_cnt] = (u16) val;
1384 good_mbuf_cnt++;
1385 }
1386
1387 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1388 }
1389
1390 /* Free the good ones back to the mbuf pool thus discarding
1391 * all the bad ones. */
1392 while (good_mbuf_cnt) {
1393 good_mbuf_cnt--;
1394
1395 val = good_mbuf[good_mbuf_cnt];
1396 val = (val << 9) | val | 1;
1397
1398 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1399 }
1400 kfree(good_mbuf);
1401 return 0;
1402}
1403
1404static void
1405bnx2_set_mac_addr(struct bnx2 *bp)
1406{
1407 u32 val;
1408 u8 *mac_addr = bp->dev->dev_addr;
1409
1410 val = (mac_addr[0] << 8) | mac_addr[1];
1411
1412 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1413
1414 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1415 (mac_addr[4] << 8) | mac_addr[5];
1416
1417 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1418}
1419
1420static inline int
1421bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1422{
1423 struct sk_buff *skb;
1424 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1425 dma_addr_t mapping;
1426 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1427 unsigned long align;
1428
1429 skb = dev_alloc_skb(bp->rx_buf_size);
1430 if (skb == NULL) {
1431 return -ENOMEM;
1432 }
1433
1434 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1435 skb_reserve(skb, 8 - align);
1436 }
1437
1438 skb->dev = bp->dev;
1439 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1440 PCI_DMA_FROMDEVICE);
1441
1442 rx_buf->skb = skb;
1443 pci_unmap_addr_set(rx_buf, mapping, mapping);
1444
1445 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1446 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1447
1448 bp->rx_prod_bseq += bp->rx_buf_use_size;
1449
1450 return 0;
1451}
1452
1453static void
1454bnx2_phy_int(struct bnx2 *bp)
1455{
1456 u32 new_link_state, old_link_state;
1457
1458 new_link_state = bp->status_blk->status_attn_bits &
1459 STATUS_ATTN_BITS_LINK_STATE;
1460 old_link_state = bp->status_blk->status_attn_bits_ack &
1461 STATUS_ATTN_BITS_LINK_STATE;
1462 if (new_link_state != old_link_state) {
1463 if (new_link_state) {
1464 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1465 STATUS_ATTN_BITS_LINK_STATE);
1466 }
1467 else {
1468 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1469 STATUS_ATTN_BITS_LINK_STATE);
1470 }
1471 bnx2_set_link(bp);
1472 }
1473}
1474
1475static void
1476bnx2_tx_int(struct bnx2 *bp)
1477{
1478 u16 hw_cons, sw_cons, sw_ring_cons;
1479 int tx_free_bd = 0;
1480
1481 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1482 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1483 hw_cons++;
1484 }
1485 sw_cons = bp->tx_cons;
1486
1487 while (sw_cons != hw_cons) {
1488 struct sw_bd *tx_buf;
1489 struct sk_buff *skb;
1490 int i, last;
1491
1492 sw_ring_cons = TX_RING_IDX(sw_cons);
1493
1494 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1495 skb = tx_buf->skb;
1496#ifdef BCM_TSO
1497 /* partial BD completions possible with TSO packets */
1498 if (skb_shinfo(skb)->tso_size) {
1499 u16 last_idx, last_ring_idx;
1500
1501 last_idx = sw_cons +
1502 skb_shinfo(skb)->nr_frags + 1;
1503 last_ring_idx = sw_ring_cons +
1504 skb_shinfo(skb)->nr_frags + 1;
1505 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1506 last_idx++;
1507 }
1508 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1509 break;
1510 }
1511 }
1512#endif
1513 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1514 skb_headlen(skb), PCI_DMA_TODEVICE);
1515
1516 tx_buf->skb = NULL;
1517 last = skb_shinfo(skb)->nr_frags;
1518
1519 for (i = 0; i < last; i++) {
1520 sw_cons = NEXT_TX_BD(sw_cons);
1521
1522 pci_unmap_page(bp->pdev,
1523 pci_unmap_addr(
1524 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1525 mapping),
1526 skb_shinfo(skb)->frags[i].size,
1527 PCI_DMA_TODEVICE);
1528 }
1529
1530 sw_cons = NEXT_TX_BD(sw_cons);
1531
1532 tx_free_bd += last + 1;
1533
1534 dev_kfree_skb_irq(skb);
1535
1536 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1537 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1538 hw_cons++;
1539 }
1540 }
1541
e89bbf10 1542 bp->tx_cons = sw_cons;
b6016b76
MC		 1543
1544 if (unlikely(netif_queue_stopped(bp->dev))) {
c770a65c 1545 spin_lock(&bp->tx_lock);
b6016b76 1546 if ((netif_queue_stopped(bp->dev)) &&
e89bbf10 1547 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
b6016b76
MC		 1548
1549 netif_wake_queue(bp->dev);
1550 }
c770a65c 1551 spin_unlock(&bp->tx_lock);
b6016b76 1552 }
b6016b76
MC		 1553}
1554
1555static inline void
1556bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1557 u16 cons, u16 prod)
1558{
1559 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1560 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1561 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1562 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1563
1564 pci_dma_sync_single_for_device(bp->pdev,
1565 pci_unmap_addr(cons_rx_buf, mapping),
1566 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1567
1568 prod_rx_buf->skb = cons_rx_buf->skb;
1569 pci_unmap_addr_set(prod_rx_buf, mapping,
1570 pci_unmap_addr(cons_rx_buf, mapping));
1571
1572 memcpy(prod_bd, cons_bd, 8);
1573
1574 bp->rx_prod_bseq += bp->rx_buf_use_size;
1575
1576}
1577
1578static int
1579bnx2_rx_int(struct bnx2 *bp, int budget)
1580{
1581 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1582 struct l2_fhdr *rx_hdr;
1583 int rx_pkt = 0;
1584
1585 hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1586 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1587 hw_cons++;
1588 }
1589 sw_cons = bp->rx_cons;
1590 sw_prod = bp->rx_prod;
1591
1592 /* Memory barrier necessary as speculative reads of the rx
1593 * buffer can be ahead of the index in the status block
1594 */
1595 rmb();
1596 while (sw_cons != hw_cons) {
1597 unsigned int len;
1598 u16 status;
1599 struct sw_bd *rx_buf;
1600 struct sk_buff *skb;
1601
1602 sw_ring_cons = RX_RING_IDX(sw_cons);
1603 sw_ring_prod = RX_RING_IDX(sw_prod);
1604
1605 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1606 skb = rx_buf->skb;
1607 pci_dma_sync_single_for_cpu(bp->pdev,
1608 pci_unmap_addr(rx_buf, mapping),
1609 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1610
1611 rx_hdr = (struct l2_fhdr *) skb->data;
1612 len = rx_hdr->l2_fhdr_pkt_len - 4;
1613
1614 if (rx_hdr->l2_fhdr_errors &
1615 (L2_FHDR_ERRORS_BAD_CRC |
1616 L2_FHDR_ERRORS_PHY_DECODE |
1617 L2_FHDR_ERRORS_ALIGNMENT |
1618 L2_FHDR_ERRORS_TOO_SHORT |
1619 L2_FHDR_ERRORS_GIANT_FRAME)) {
1620
1621 goto reuse_rx;
1622 }
1623
1624 /* Since we don't have a jumbo ring, copy small packets
1625 * if mtu > 1500
1626 */
1627 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1628 struct sk_buff *new_skb;
1629
1630 new_skb = dev_alloc_skb(len + 2);
1631 if (new_skb == NULL)
1632 goto reuse_rx;
1633
1634 /* aligned copy */
1635 memcpy(new_skb->data,
1636 skb->data + bp->rx_offset - 2,
1637 len + 2);
1638
1639 skb_reserve(new_skb, 2);
1640 skb_put(new_skb, len);
1641 new_skb->dev = bp->dev;
1642
1643 bnx2_reuse_rx_skb(bp, skb,
1644 sw_ring_cons, sw_ring_prod);
1645
1646 skb = new_skb;
1647 }
1648 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1649 pci_unmap_single(bp->pdev,
1650 pci_unmap_addr(rx_buf, mapping),
1651 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1652
1653 skb_reserve(skb, bp->rx_offset);
1654 skb_put(skb, len);
1655 }
1656 else {
1657reuse_rx:
1658 bnx2_reuse_rx_skb(bp, skb,
1659 sw_ring_cons, sw_ring_prod);
1660 goto next_rx;
1661 }
1662
1663 skb->protocol = eth_type_trans(skb, bp->dev);
1664
1665 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1666 (htons(skb->protocol) != 0x8100)) {
1667
1668 dev_kfree_skb_irq(skb);
1669 goto next_rx;
1670
1671 }
1672
1673 status = rx_hdr->l2_fhdr_status;
1674 skb->ip_summed = CHECKSUM_NONE;
1675 if (bp->rx_csum &&
1676 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1677 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1678
1679 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1680
1681 if (cksum == 0xffff)
1682 skb->ip_summed = CHECKSUM_UNNECESSARY;
1683 }
1684
1685#ifdef BCM_VLAN
1686 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1687 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1688 rx_hdr->l2_fhdr_vlan_tag);
1689 }
1690 else
1691#endif
1692 netif_receive_skb(skb);
1693
1694 bp->dev->last_rx = jiffies;
1695 rx_pkt++;
1696
1697next_rx:
1698 rx_buf->skb = NULL;
1699
1700 sw_cons = NEXT_RX_BD(sw_cons);
1701 sw_prod = NEXT_RX_BD(sw_prod);
1702
1703 if ((rx_pkt == budget))
1704 break;
1705 }
1706 bp->rx_cons = sw_cons;
1707 bp->rx_prod = sw_prod;
1708
1709 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1710
1711 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1712
1713 mmiowb();
1714
1715 return rx_pkt;
1716
1717}
1718
1719/* MSI ISR - The only difference between this and the INTx ISR
1720 * is that the MSI interrupt is always serviced.
1721 */
1722static irqreturn_t
1723bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1724{
1725 struct net_device *dev = dev_instance;
1726 struct bnx2 *bp = dev->priv;
1727
c921e4c4 1728 prefetch(bp->status_blk);
b6016b76
MC		 1729 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1730 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1731 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1732
1733 /* Return here if interrupt is disabled. */
73eef4cd
MC		 1734 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1735 return IRQ_HANDLED;
b6016b76 1736
73eef4cd 1737 netif_rx_schedule(dev);
b6016b76 1738
73eef4cd 1739 return IRQ_HANDLED;
b6016b76
MC		 1740}
1741
1742static irqreturn_t
1743bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1744{
1745 struct net_device *dev = dev_instance;
1746 struct bnx2 *bp = dev->priv;
1747
1748 /* When using INTx, it is possible for the interrupt to arrive
1749 * at the CPU before the status block posted prior to the
1750 * interrupt. Reading a register will flush the status block.
1751 * When using MSI, the MSI message will always complete after
1752 * the status block write.
1753 */
c921e4c4 1754 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
b6016b76
MC		 1755 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1756 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 1757 return IRQ_NONE;
b6016b76
MC		 1758
1759 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1760 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1761 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1762
1763 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 1764 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1765 return IRQ_HANDLED;
b6016b76 1766
73eef4cd 1767 netif_rx_schedule(dev);
b6016b76 1768
73eef4cd 1769 return IRQ_HANDLED;
b6016b76
MC		 1770}
1771
1772static int
1773bnx2_poll(struct net_device *dev, int *budget)
1774{
1775 struct bnx2 *bp = dev->priv;
1776 int rx_done = 1;
1777
1778 bp->last_status_idx = bp->status_blk->status_idx;
1779
1780 rmb();
1781 if ((bp->status_blk->status_attn_bits &
1782 STATUS_ATTN_BITS_LINK_STATE) !=
1783 (bp->status_blk->status_attn_bits_ack &
1784 STATUS_ATTN_BITS_LINK_STATE)) {
1785
c770a65c 1786 spin_lock(&bp->phy_lock);
b6016b76 1787 bnx2_phy_int(bp);
c770a65c 1788 spin_unlock(&bp->phy_lock);
b6016b76
MC		 1789 }
1790
1791 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1792 bnx2_tx_int(bp);
1793 }
1794
1795 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1796 int orig_budget = *budget;
1797 int work_done;
1798
1799 if (orig_budget > dev->quota)
1800 orig_budget = dev->quota;
1801
1802 work_done = bnx2_rx_int(bp, orig_budget);
1803 *budget -= work_done;
1804 dev->quota -= work_done;
1805
1806 if (work_done >= orig_budget) {
1807 rx_done = 0;
1808 }
1809 }
1810
1811 if (rx_done) {
1812 netif_rx_complete(dev);
1813 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1814 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1815 bp->last_status_idx);
1816 return 0;
1817 }
1818
1819 return 1;
1820}
1821
1822/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1823 * from set_multicast.
1824 */
1825static void
1826bnx2_set_rx_mode(struct net_device *dev)
1827{
1828 struct bnx2 *bp = dev->priv;
1829 u32 rx_mode, sort_mode;
1830 int i;
b6016b76 1831
c770a65c 1832 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1833
1834 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1835 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1836 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1837#ifdef BCM_VLAN
1838 if (!bp->vlgrp) {
1839 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1840 }
1841#else
1842 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1843#endif
1844 if (dev->flags & IFF_PROMISC) {
1845 /* Promiscuous mode. */
1846 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1847 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1848 }
1849 else if (dev->flags & IFF_ALLMULTI) {
1850 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1851 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1852 0xffffffff);
1853 }
1854 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1855 }
1856 else {
1857 /* Accept one or more multicast(s). */
1858 struct dev_mc_list *mclist;
1859 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1860 u32 regidx;
1861 u32 bit;
1862 u32 crc;
1863
1864 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1865
1866 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1867 i++, mclist = mclist->next) {
1868
1869 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1870 bit = crc & 0xff;
1871 regidx = (bit & 0xe0) >> 5;
1872 bit &= 0x1f;
1873 mc_filter[regidx] |= (1 << bit);
1874 }
1875
1876 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1877 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1878 mc_filter[i]);
1879 }
1880
1881 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1882 }
1883
1884 if (rx_mode != bp->rx_mode) {
1885 bp->rx_mode = rx_mode;
1886 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1887 }
1888
1889 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1890 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1891 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1892
c770a65c 1893 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 1894}
1895
1896static void
1897load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1898 u32 rv2p_proc)
1899{
1900 int i;
1901 u32 val;
1902
1903
1904 for (i = 0; i < rv2p_code_len; i += 8) {
1905 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1906 rv2p_code++;
1907 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1908 rv2p_code++;
1909
1910 if (rv2p_proc == RV2P_PROC1) {
1911 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1912 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1913 }
1914 else {
1915 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1916 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1917 }
1918 }
1919
1920 /* Reset the processor, un-stall is done later. */
1921 if (rv2p_proc == RV2P_PROC1) {
1922 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1923 }
1924 else {
1925 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1926 }
1927}
1928
1929static void
1930load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1931{
1932 u32 offset;
1933 u32 val;
1934
1935 /* Halt the CPU. */
1936 val = REG_RD_IND(bp, cpu_reg->mode);
1937 val |= cpu_reg->mode_value_halt;
1938 REG_WR_IND(bp, cpu_reg->mode, val);
1939 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1940
1941 /* Load the Text area. */
1942 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1943 if (fw->text) {
1944 int j;
1945
1946 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1947 REG_WR_IND(bp, offset, fw->text[j]);
1948 }
1949 }
1950
1951 /* Load the Data area. */
1952 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1953 if (fw->data) {
1954 int j;
1955
1956 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1957 REG_WR_IND(bp, offset, fw->data[j]);
1958 }
1959 }
1960
1961 /* Load the SBSS area. */
1962 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1963 if (fw->sbss) {
1964 int j;
1965
1966 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1967 REG_WR_IND(bp, offset, fw->sbss[j]);
1968 }
1969 }
1970
1971 /* Load the BSS area. */
1972 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1973 if (fw->bss) {
1974 int j;
1975
1976 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1977 REG_WR_IND(bp, offset, fw->bss[j]);
1978 }
1979 }
1980
1981 /* Load the Read-Only area. */
1982 offset = cpu_reg->spad_base +
1983 (fw->rodata_addr - cpu_reg->mips_view_base);
1984 if (fw->rodata) {
1985 int j;
1986
1987 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1988 REG_WR_IND(bp, offset, fw->rodata[j]);
1989 }
1990 }
1991
1992 /* Clear the pre-fetch instruction. */
1993 REG_WR_IND(bp, cpu_reg->inst, 0);
1994 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1995
1996 /* Start the CPU. */
1997 val = REG_RD_IND(bp, cpu_reg->mode);
1998 val &= ~cpu_reg->mode_value_halt;
1999 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2000 REG_WR_IND(bp, cpu_reg->mode, val);
2001}
2002
2003static void
2004bnx2_init_cpus(struct bnx2 *bp)
2005{
2006 struct cpu_reg cpu_reg;
2007 struct fw_info fw;
2008
2009 /* Initialize the RV2P processor. */
2010 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2011 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2012
2013 /* Initialize the RX Processor. */
2014 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2015 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2016 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2017 cpu_reg.state = BNX2_RXP_CPU_STATE;
2018 cpu_reg.state_value_clear = 0xffffff;
2019 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2020 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2021 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2022 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2023 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2024 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2025 cpu_reg.mips_view_base = 0x8000000;
2026
2027 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2028 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2029 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2030 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2031
2032 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2033 fw.text_len = bnx2_RXP_b06FwTextLen;
2034 fw.text_index = 0;
2035 fw.text = bnx2_RXP_b06FwText;
2036
2037 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2038 fw.data_len = bnx2_RXP_b06FwDataLen;
2039 fw.data_index = 0;
2040 fw.data = bnx2_RXP_b06FwData;
2041
2042 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2043 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2044 fw.sbss_index = 0;
2045 fw.sbss = bnx2_RXP_b06FwSbss;
2046
2047 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2048 fw.bss_len = bnx2_RXP_b06FwBssLen;
2049 fw.bss_index = 0;
2050 fw.bss = bnx2_RXP_b06FwBss;
2051
2052 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2053 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2054 fw.rodata_index = 0;
2055 fw.rodata = bnx2_RXP_b06FwRodata;
2056
2057 load_cpu_fw(bp, &cpu_reg, &fw);
2058
2059 /* Initialize the TX Processor. */
2060 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2061 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2062 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2063 cpu_reg.state = BNX2_TXP_CPU_STATE;
2064 cpu_reg.state_value_clear = 0xffffff;
2065 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2066 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2067 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2068 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2069 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2070 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2071 cpu_reg.mips_view_base = 0x8000000;
2072
2073 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2074 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2075 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2076 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2077
2078 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2079 fw.text_len = bnx2_TXP_b06FwTextLen;
2080 fw.text_index = 0;
2081 fw.text = bnx2_TXP_b06FwText;
2082
2083 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2084 fw.data_len = bnx2_TXP_b06FwDataLen;
2085 fw.data_index = 0;
2086 fw.data = bnx2_TXP_b06FwData;
2087
2088 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2089 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2090 fw.sbss_index = 0;
2091 fw.sbss = bnx2_TXP_b06FwSbss;
2092
2093 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2094 fw.bss_len = bnx2_TXP_b06FwBssLen;
2095 fw.bss_index = 0;
2096 fw.bss = bnx2_TXP_b06FwBss;
2097
2098 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2099 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2100 fw.rodata_index = 0;
2101 fw.rodata = bnx2_TXP_b06FwRodata;
2102
2103 load_cpu_fw(bp, &cpu_reg, &fw);
2104
2105 /* Initialize the TX Patch-up Processor. */
2106 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2107 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2108 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2109 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2110 cpu_reg.state_value_clear = 0xffffff;
2111 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2112 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2113 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2114 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2115 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2116 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2117 cpu_reg.mips_view_base = 0x8000000;
2118
2119 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2120 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2121 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2122 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2123
2124 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2125 fw.text_len = bnx2_TPAT_b06FwTextLen;
2126 fw.text_index = 0;
2127 fw.text = bnx2_TPAT_b06FwText;
2128
2129 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2130 fw.data_len = bnx2_TPAT_b06FwDataLen;
2131 fw.data_index = 0;
2132 fw.data = bnx2_TPAT_b06FwData;
2133
2134 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2135 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2136 fw.sbss_index = 0;
2137 fw.sbss = bnx2_TPAT_b06FwSbss;
2138
2139 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2140 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2141 fw.bss_index = 0;
2142 fw.bss = bnx2_TPAT_b06FwBss;
2143
2144 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2145 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2146 fw.rodata_index = 0;
2147 fw.rodata = bnx2_TPAT_b06FwRodata;
2148
2149 load_cpu_fw(bp, &cpu_reg, &fw);
2150
2151 /* Initialize the Completion Processor. */
2152 cpu_reg.mode = BNX2_COM_CPU_MODE;
2153 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2154 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2155 cpu_reg.state = BNX2_COM_CPU_STATE;
2156 cpu_reg.state_value_clear = 0xffffff;
2157 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2158 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2159 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2160 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2161 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2162 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2163 cpu_reg.mips_view_base = 0x8000000;
2164
2165 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2166 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2167 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2168 fw.start_addr = bnx2_COM_b06FwStartAddr;
2169
2170 fw.text_addr = bnx2_COM_b06FwTextAddr;
2171 fw.text_len = bnx2_COM_b06FwTextLen;
2172 fw.text_index = 0;
2173 fw.text = bnx2_COM_b06FwText;
2174
2175 fw.data_addr = bnx2_COM_b06FwDataAddr;
2176 fw.data_len = bnx2_COM_b06FwDataLen;
2177 fw.data_index = 0;
2178 fw.data = bnx2_COM_b06FwData;
2179
2180 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2181 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2182 fw.sbss_index = 0;
2183 fw.sbss = bnx2_COM_b06FwSbss;
2184
2185 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2186 fw.bss_len = bnx2_COM_b06FwBssLen;
2187 fw.bss_index = 0;
2188 fw.bss = bnx2_COM_b06FwBss;
2189
2190 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2191 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2192 fw.rodata_index = 0;
2193 fw.rodata = bnx2_COM_b06FwRodata;
2194
2195 load_cpu_fw(bp, &cpu_reg, &fw);
2196
2197}
2198
2199static int
829ca9a3 2200bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 2201{
2202 u16 pmcsr;
2203
2204 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2205
2206 switch (state) {
829ca9a3 2207 case PCI_D0: {
b6016b76
MC		 2208 u32 val;
2209
2210 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2211 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2212 PCI_PM_CTRL_PME_STATUS);
2213
2214 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2215 /* delay required during transition out of D3hot */
2216 msleep(20);
2217
2218 val = REG_RD(bp, BNX2_EMAC_MODE);
2219 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2220 val &= ~BNX2_EMAC_MODE_MPKT;
2221 REG_WR(bp, BNX2_EMAC_MODE, val);
2222
2223 val = REG_RD(bp, BNX2_RPM_CONFIG);
2224 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2225 REG_WR(bp, BNX2_RPM_CONFIG, val);
2226 break;
2227 }
829ca9a3 2228 case PCI_D3hot: {
b6016b76
MC		 2229 int i;
2230 u32 val, wol_msg;
2231
2232 if (bp->wol) {
2233 u32 advertising;
2234 u8 autoneg;
2235
2236 autoneg = bp->autoneg;
2237 advertising = bp->advertising;
2238
2239 bp->autoneg = AUTONEG_SPEED;
2240 bp->advertising = ADVERTISED_10baseT_Half |
2241 ADVERTISED_10baseT_Full |
2242 ADVERTISED_100baseT_Half |
2243 ADVERTISED_100baseT_Full |
2244 ADVERTISED_Autoneg;
2245
2246 bnx2_setup_copper_phy(bp);
2247
2248 bp->autoneg = autoneg;
2249 bp->advertising = advertising;
2250
2251 bnx2_set_mac_addr(bp);
2252
2253 val = REG_RD(bp, BNX2_EMAC_MODE);
2254
2255 /* Enable port mode. */
2256 val &= ~BNX2_EMAC_MODE_PORT;
2257 val |= BNX2_EMAC_MODE_PORT_MII |
2258 BNX2_EMAC_MODE_MPKT_RCVD |
2259 BNX2_EMAC_MODE_ACPI_RCVD |
2260 BNX2_EMAC_MODE_FORCE_LINK |
2261 BNX2_EMAC_MODE_MPKT;
2262
2263 REG_WR(bp, BNX2_EMAC_MODE, val);
2264
2265 /* receive all multicast */
2266 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2267 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2268 0xffffffff);
2269 }
2270 REG_WR(bp, BNX2_EMAC_RX_MODE,
2271 BNX2_EMAC_RX_MODE_SORT_MODE);
2272
2273 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2274 BNX2_RPM_SORT_USER0_MC_EN;
2275 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2276 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2277 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2278 BNX2_RPM_SORT_USER0_ENA);
2279
2280 /* Need to enable EMAC and RPM for WOL. */
2281 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2282 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2283 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2284 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2285
2286 val = REG_RD(bp, BNX2_RPM_CONFIG);
2287 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2288 REG_WR(bp, BNX2_RPM_CONFIG, val);
2289
2290 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2291 }
2292 else {
2293 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2294 }
2295
2296 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2297
2298 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2299 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2300 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2301
2302 if (bp->wol)
2303 pmcsr |= 3;
2304 }
2305 else {
2306 pmcsr |= 3;
2307 }
2308 if (bp->wol) {
2309 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2310 }
2311 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2312 pmcsr);
2313
2314 /* No more memory access after this point until
2315 * device is brought back to D0.
2316 */
2317 udelay(50);
2318 break;
2319 }
2320 default:
2321 return -EINVAL;
2322 }
2323 return 0;
2324}
2325
2326static int
2327bnx2_acquire_nvram_lock(struct bnx2 *bp)
2328{
2329 u32 val;
2330 int j;
2331
2332 /* Request access to the flash interface. */
2333 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2334 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2335 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2336 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2337 break;
2338
2339 udelay(5);
2340 }
2341
2342 if (j >= NVRAM_TIMEOUT_COUNT)
2343 return -EBUSY;
2344
2345 return 0;
2346}
2347
2348static int
2349bnx2_release_nvram_lock(struct bnx2 *bp)
2350{
2351 int j;
2352 u32 val;
2353
2354 /* Relinquish nvram interface. */
2355 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2356
2357 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2358 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2359 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2360 break;
2361
2362 udelay(5);
2363 }
2364
2365 if (j >= NVRAM_TIMEOUT_COUNT)
2366 return -EBUSY;
2367
2368 return 0;
2369}
2370
2371
2372static int
2373bnx2_enable_nvram_write(struct bnx2 *bp)
2374{
2375 u32 val;
2376
2377 val = REG_RD(bp, BNX2_MISC_CFG);
2378 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2379
2380 if (!bp->flash_info->buffered) {
2381 int j;
2382
2383 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2384 REG_WR(bp, BNX2_NVM_COMMAND,
2385 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2386
2387 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2388 udelay(5);
2389
2390 val = REG_RD(bp, BNX2_NVM_COMMAND);
2391 if (val & BNX2_NVM_COMMAND_DONE)
2392 break;
2393 }
2394
2395 if (j >= NVRAM_TIMEOUT_COUNT)
2396 return -EBUSY;
2397 }
2398 return 0;
2399}
2400
2401static void
2402bnx2_disable_nvram_write(struct bnx2 *bp)
2403{
2404 u32 val;
2405
2406 val = REG_RD(bp, BNX2_MISC_CFG);
2407 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2408}
2409
2410
2411static void
2412bnx2_enable_nvram_access(struct bnx2 *bp)
2413{
2414 u32 val;
2415
2416 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2417 /* Enable both bits, even on read. */
2418 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2419 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2420}
2421
2422static void
2423bnx2_disable_nvram_access(struct bnx2 *bp)
2424{
2425 u32 val;
2426
2427 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2428 /* Disable both bits, even after read. */
2429 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2430 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2431 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2432}
2433
2434static int
2435bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2436{
2437 u32 cmd;
2438 int j;
2439
2440 if (bp->flash_info->buffered)
2441 /* Buffered flash, no erase needed */
2442 return 0;
2443
2444 /* Build an erase command */
2445 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2446 BNX2_NVM_COMMAND_DOIT;
2447
2448 /* Need to clear DONE bit separately. */
2449 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2450
2451 /* Address of the NVRAM to read from. */
2452 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2453
2454 /* Issue an erase command. */
2455 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2456
2457 /* Wait for completion. */
2458 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2459 u32 val;
2460
2461 udelay(5);
2462
2463 val = REG_RD(bp, BNX2_NVM_COMMAND);
2464 if (val & BNX2_NVM_COMMAND_DONE)
2465 break;
2466 }
2467
2468 if (j >= NVRAM_TIMEOUT_COUNT)
2469 return -EBUSY;
2470
2471 return 0;
2472}
2473
2474static int
2475bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2476{
2477 u32 cmd;
2478 int j;
2479
2480 /* Build the command word. */
2481 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2482
2483 /* Calculate an offset of a buffered flash. */
2484 if (bp->flash_info->buffered) {
2485 offset = ((offset / bp->flash_info->page_size) <<
2486 bp->flash_info->page_bits) +
2487 (offset % bp->flash_info->page_size);
2488 }
2489
2490 /* Need to clear DONE bit separately. */
2491 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2492
2493 /* Address of the NVRAM to read from. */
2494 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2495
2496 /* Issue a read command. */
2497 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2498
2499 /* Wait for completion. */
2500 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2501 u32 val;
2502
2503 udelay(5);
2504
2505 val = REG_RD(bp, BNX2_NVM_COMMAND);
2506 if (val & BNX2_NVM_COMMAND_DONE) {
2507 val = REG_RD(bp, BNX2_NVM_READ);
2508
2509 val = be32_to_cpu(val);
2510 memcpy(ret_val, &val, 4);
2511 break;
2512 }
2513 }
2514 if (j >= NVRAM_TIMEOUT_COUNT)
2515 return -EBUSY;
2516
2517 return 0;
2518}
2519
2520
2521static int
2522bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2523{
2524 u32 cmd, val32;
2525 int j;
2526
2527 /* Build the command word. */
2528 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2529
2530 /* Calculate an offset of a buffered flash. */
2531 if (bp->flash_info->buffered) {
2532 offset = ((offset / bp->flash_info->page_size) <<
2533 bp->flash_info->page_bits) +
2534 (offset % bp->flash_info->page_size);
2535 }
2536
2537 /* Need to clear DONE bit separately. */
2538 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2539
2540 memcpy(&val32, val, 4);
2541 val32 = cpu_to_be32(val32);
2542
2543 /* Write the data. */
2544 REG_WR(bp, BNX2_NVM_WRITE, val32);
2545
2546 /* Address of the NVRAM to write to. */
2547 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2548
2549 /* Issue the write command. */
2550 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2551
2552 /* Wait for completion. */
2553 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2554 udelay(5);
2555
2556 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2557 break;
2558 }
2559 if (j >= NVRAM_TIMEOUT_COUNT)
2560 return -EBUSY;
2561
2562 return 0;
2563}
2564
2565static int
2566bnx2_init_nvram(struct bnx2 *bp)
2567{
2568 u32 val;
2569 int j, entry_count, rc;
2570 struct flash_spec *flash;
2571
2572 /* Determine the selected interface. */
2573 val = REG_RD(bp, BNX2_NVM_CFG1);
2574
2575 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2576
2577 rc = 0;
2578 if (val & 0x40000000) {
2579
2580 /* Flash interface has been reconfigured */
2581 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 2582 j++, flash++) {
2583 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2584 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 2585 bp->flash_info = flash;
2586 break;
2587 }
2588 }
2589 }
2590 else {
37137709 2591 u32 mask;
b6016b76
MC		 2592 /* Not yet been reconfigured */
2593
37137709
MC		 2594 if (val & (1 << 23))
2595 mask = FLASH_BACKUP_STRAP_MASK;
2596 else
2597 mask = FLASH_STRAP_MASK;
2598
b6016b76
MC		 2599 for (j = 0, flash = &flash_table[0]; j < entry_count;
2600 j++, flash++) {
2601
37137709 2602 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 2603 bp->flash_info = flash;
2604
2605 /* Request access to the flash interface. */
2606 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2607 return rc;
2608
2609 /* Enable access to flash interface */
2610 bnx2_enable_nvram_access(bp);
2611
2612 /* Reconfigure the flash interface */
2613 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2614 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2615 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2616 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2617
2618 /* Disable access to flash interface */
2619 bnx2_disable_nvram_access(bp);
2620 bnx2_release_nvram_lock(bp);
2621
2622 break;
2623 }
2624 }
2625 } /* if (val & 0x40000000) */
2626
2627 if (j == entry_count) {
2628 bp->flash_info = NULL;
2629 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2630 rc = -ENODEV;
2631 }
2632
2633 return rc;
2634}
2635
2636static int
2637bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2638 int buf_size)
2639{
2640 int rc = 0;
2641 u32 cmd_flags, offset32, len32, extra;
2642
2643 if (buf_size == 0)
2644 return 0;
2645
2646 /* Request access to the flash interface. */
2647 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2648 return rc;
2649
2650 /* Enable access to flash interface */
2651 bnx2_enable_nvram_access(bp);
2652
2653 len32 = buf_size;
2654 offset32 = offset;
2655 extra = 0;
2656
2657 cmd_flags = 0;
2658
2659 if (offset32 & 3) {
2660 u8 buf[4];
2661 u32 pre_len;
2662
2663 offset32 &= ~3;
2664 pre_len = 4 - (offset & 3);
2665
2666 if (pre_len >= len32) {
2667 pre_len = len32;
2668 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2669 BNX2_NVM_COMMAND_LAST;
2670 }
2671 else {
2672 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2673 }
2674
2675 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2676
2677 if (rc)
2678 return rc;
2679
2680 memcpy(ret_buf, buf + (offset & 3), pre_len);
2681
2682 offset32 += 4;
2683 ret_buf += pre_len;
2684 len32 -= pre_len;
2685 }
2686 if (len32 & 3) {
2687 extra = 4 - (len32 & 3);
2688 len32 = (len32 + 4) & ~3;
2689 }
2690
2691 if (len32 == 4) {
2692 u8 buf[4];
2693
2694 if (cmd_flags)
2695 cmd_flags = BNX2_NVM_COMMAND_LAST;
2696 else
2697 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2698 BNX2_NVM_COMMAND_LAST;
2699
2700 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2701
2702 memcpy(ret_buf, buf, 4 - extra);
2703 }
2704 else if (len32 > 0) {
2705 u8 buf[4];
2706
2707 /* Read the first word. */
2708 if (cmd_flags)
2709 cmd_flags = 0;
2710 else
2711 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2712
2713 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2714
2715 /* Advance to the next dword. */
2716 offset32 += 4;
2717 ret_buf += 4;
2718 len32 -= 4;
2719
2720 while (len32 > 4 && rc == 0) {
2721 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2722
2723 /* Advance to the next dword. */
2724 offset32 += 4;
2725 ret_buf += 4;
2726 len32 -= 4;
2727 }
2728
2729 if (rc)
2730 return rc;
2731
2732 cmd_flags = BNX2_NVM_COMMAND_LAST;
2733 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2734
2735 memcpy(ret_buf, buf, 4 - extra);
2736 }
2737
2738 /* Disable access to flash interface */
2739 bnx2_disable_nvram_access(bp);
2740
2741 bnx2_release_nvram_lock(bp);
2742
2743 return rc;
2744}
2745
2746static int
2747bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2748 int buf_size)
2749{
2750 u32 written, offset32, len32;
2751 u8 *buf, start[4], end[4];
2752 int rc = 0;
2753 int align_start, align_end;
2754
2755 buf = data_buf;
2756 offset32 = offset;
2757 len32 = buf_size;
2758 align_start = align_end = 0;
2759
2760 if ((align_start = (offset32 & 3))) {
2761 offset32 &= ~3;
2762 len32 += align_start;
2763 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2764 return rc;
2765 }
2766
2767 if (len32 & 3) {
2768 if ((len32 > 4) || !align_start) {
2769 align_end = 4 - (len32 & 3);
2770 len32 += align_end;
2771 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2772 end, 4))) {
2773 return rc;
2774 }
2775 }
2776 }
2777
2778 if (align_start || align_end) {
2779 buf = kmalloc(len32, GFP_KERNEL);
2780 if (buf == 0)
2781 return -ENOMEM;
2782 if (align_start) {
2783 memcpy(buf, start, 4);
2784 }
2785 if (align_end) {
2786 memcpy(buf + len32 - 4, end, 4);
2787 }
2788 memcpy(buf + align_start, data_buf, buf_size);
2789 }
2790
2791 written = 0;
2792 while ((written < len32) && (rc == 0)) {
2793 u32 page_start, page_end, data_start, data_end;
2794 u32 addr, cmd_flags;
2795 int i;
2796 u8 flash_buffer[264];
2797
2798 /* Find the page_start addr */
2799 page_start = offset32 + written;
2800 page_start -= (page_start % bp->flash_info->page_size);
2801 /* Find the page_end addr */
2802 page_end = page_start + bp->flash_info->page_size;
2803 /* Find the data_start addr */
2804 data_start = (written == 0) ? offset32 : page_start;
2805 /* Find the data_end addr */
2806 data_end = (page_end > offset32 + len32) ?
2807 (offset32 + len32) : page_end;
2808
2809 /* Request access to the flash interface. */
2810 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2811 goto nvram_write_end;
2812
2813 /* Enable access to flash interface */
2814 bnx2_enable_nvram_access(bp);
2815
2816 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2817 if (bp->flash_info->buffered == 0) {
2818 int j;
2819
2820 /* Read the whole page into the buffer
2821 * (non-buffer flash only) */
2822 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2823 if (j == (bp->flash_info->page_size - 4)) {
2824 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2825 }
2826 rc = bnx2_nvram_read_dword(bp,
2827 page_start + j,
2828 &flash_buffer[j],
2829 cmd_flags);
2830
2831 if (rc)
2832 goto nvram_write_end;
2833
2834 cmd_flags = 0;
2835 }
2836 }
2837
2838 /* Enable writes to flash interface (unlock write-protect) */
2839 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2840 goto nvram_write_end;
2841
2842 /* Erase the page */
2843 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2844 goto nvram_write_end;
2845
2846 /* Re-enable the write again for the actual write */
2847 bnx2_enable_nvram_write(bp);
2848
2849 /* Loop to write back the buffer data from page_start to
2850 * data_start */
2851 i = 0;
2852 if (bp->flash_info->buffered == 0) {
2853 for (addr = page_start; addr < data_start;
2854 addr += 4, i += 4) {
2855
2856 rc = bnx2_nvram_write_dword(bp, addr,
2857 &flash_buffer[i], cmd_flags);
2858
2859 if (rc != 0)
2860 goto nvram_write_end;
2861
2862 cmd_flags = 0;
2863 }
2864 }
2865
2866 /* Loop to write the new data from data_start to data_end */
2867 for (addr = data_start; addr < data_end; addr += 4, i++) {
2868 if ((addr == page_end - 4) ||
2869 ((bp->flash_info->buffered) &&
2870 (addr == data_end - 4))) {
2871
2872 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2873 }
2874 rc = bnx2_nvram_write_dword(bp, addr, buf,
2875 cmd_flags);
2876
2877 if (rc != 0)
2878 goto nvram_write_end;
2879
2880 cmd_flags = 0;
2881 buf += 4;
2882 }
2883
2884 /* Loop to write back the buffer data from data_end
2885 * to page_end */
2886 if (bp->flash_info->buffered == 0) {
2887 for (addr = data_end; addr < page_end;
2888 addr += 4, i += 4) {
2889
2890 if (addr == page_end-4) {
2891 cmd_flags = BNX2_NVM_COMMAND_LAST;
2892 }
2893 rc = bnx2_nvram_write_dword(bp, addr,
2894 &flash_buffer[i], cmd_flags);
2895
2896 if (rc != 0)
2897 goto nvram_write_end;
2898
2899 cmd_flags = 0;
2900 }
2901 }
2902
2903 /* Disable writes to flash interface (lock write-protect) */
2904 bnx2_disable_nvram_write(bp);
2905
2906 /* Disable access to flash interface */
2907 bnx2_disable_nvram_access(bp);
2908 bnx2_release_nvram_lock(bp);
2909
2910 /* Increment written */
2911 written += data_end - data_start;
2912 }
2913
2914nvram_write_end:
2915 if (align_start || align_end)
2916 kfree(buf);
2917 return rc;
2918}
2919
2920static int
2921bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2922{
2923 u32 val;
2924 int i, rc = 0;
2925
2926 /* Wait for the current PCI transaction to complete before
2927 * issuing a reset. */
2928 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2929 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2930 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2931 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2932 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2933 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2934 udelay(5);
2935
2936 /* Deposit a driver reset signature so the firmware knows that
2937 * this is a soft reset. */
2938 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2939 BNX2_DRV_RESET_SIGNATURE_MAGIC);
2940
2941 bp->fw_timed_out = 0;
2942
2943 /* Wait for the firmware to tell us it is ok to issue a reset. */
2944 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2945
2946 /* Do a dummy read to force the chip to complete all current transaction
2947 * before we issue a reset. */
2948 val = REG_RD(bp, BNX2_MISC_ID);
2949
2950 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2951 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2952 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2953
2954 /* Chip reset. */
2955 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2956
2957 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2958 (CHIP_ID(bp) == CHIP_ID_5706_A1))
2959 msleep(15);
2960
2961 /* Reset takes approximate 30 usec */
2962 for (i = 0; i < 10; i++) {
2963 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2964 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2965 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2966 break;
2967 }
2968 udelay(10);
2969 }
2970
2971 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2972 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2973 printk(KERN_ERR PFX "Chip reset did not complete\n");
2974 return -EBUSY;
2975 }
2976
2977 /* Make sure byte swapping is properly configured. */
2978 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2979 if (val != 0x01020304) {
2980 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2981 return -ENODEV;
2982 }
2983
2984 bp->fw_timed_out = 0;
2985
2986 /* Wait for the firmware to finish its initialization. */
2987 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2988
2989 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2990 /* Adjust the voltage regular to two steps lower. The default
2991 * of this register is 0x0000000e. */
2992 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2993
2994 /* Remove bad rbuf memory from the free pool. */
2995 rc = bnx2_alloc_bad_rbuf(bp);
2996 }
2997
2998 return rc;
2999}
3000
3001static int
3002bnx2_init_chip(struct bnx2 *bp)
3003{
3004 u32 val;
3005
3006 /* Make sure the interrupt is not active. */
3007 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3008
3009 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3010 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3011#ifdef __BIG_ENDIAN
3012 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3013#endif
3014 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3015 DMA_READ_CHANS << 12 |
3016 DMA_WRITE_CHANS << 16;
3017
3018 val |= (0x2 << 20) | (1 << 11);
3019
3020 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
3021 val |= (1 << 23);
3022
3023 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3024 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3025 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3026
3027 REG_WR(bp, BNX2_DMA_CONFIG, val);
3028
3029 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3030 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3031 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3032 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3033 }
3034
3035 if (bp->flags & PCIX_FLAG) {
3036 u16 val16;
3037
3038 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3039 &val16);
3040 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3041 val16 & ~PCI_X_CMD_ERO);
3042 }
3043
3044 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3045 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3046 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3047 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3048
3049 /* Initialize context mapping and zero out the quick contexts. The
3050 * context block must have already been enabled. */
3051 bnx2_init_context(bp);
3052
3053 bnx2_init_cpus(bp);
3054 bnx2_init_nvram(bp);
3055
3056 bnx2_set_mac_addr(bp);
3057
3058 val = REG_RD(bp, BNX2_MQ_CONFIG);
3059 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3060 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3061 REG_WR(bp, BNX2_MQ_CONFIG, val);
3062
3063 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3064 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3065 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3066
3067 val = (BCM_PAGE_BITS - 8) << 24;
3068 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3069
3070 /* Configure page size. */
3071 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3072 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3073 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3074 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3075
3076 val = bp->mac_addr[0] +
3077 (bp->mac_addr[1] << 8) +
3078 (bp->mac_addr[2] << 16) +
3079 bp->mac_addr[3] +
3080 (bp->mac_addr[4] << 8) +
3081 (bp->mac_addr[5] << 16);
3082 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3083
3084 /* Program the MTU. Also include 4 bytes for CRC32. */
3085 val = bp->dev->mtu + ETH_HLEN + 4;
3086 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3087 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3088 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3089
3090 bp->last_status_idx = 0;
3091 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3092
3093 /* Set up how to generate a link change interrupt. */
3094 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3095
3096 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3097 (u64) bp->status_blk_mapping & 0xffffffff);
3098 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3099
3100 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3101 (u64) bp->stats_blk_mapping & 0xffffffff);
3102 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3103 (u64) bp->stats_blk_mapping >> 32);
3104
3105 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3106 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3107
3108 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3109 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3110
3111 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3112 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3113
3114 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3115
3116 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3117
3118 REG_WR(bp, BNX2_HC_COM_TICKS,
3119 (bp->com_ticks_int << 16) | bp->com_ticks);
3120
3121 REG_WR(bp, BNX2_HC_CMD_TICKS,
3122 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3123
3124 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3125 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3126
3127 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3128 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3129 else {
3130 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3131 BNX2_HC_CONFIG_TX_TMR_MODE |
3132 BNX2_HC_CONFIG_COLLECT_STATS);
3133 }
3134
3135 /* Clear internal stats counters. */
3136 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3137
3138 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3139
3140 /* Initialize the receive filter. */
3141 bnx2_set_rx_mode(bp->dev);
3142
3143 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
3144
3145 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3146 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3147
3148 udelay(20);
3149
3150 return 0;
3151}
3152
3153
3154static void
3155bnx2_init_tx_ring(struct bnx2 *bp)
3156{
3157 struct tx_bd *txbd;
3158 u32 val;
3159
3160 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3161
3162 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3163 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3164
3165 bp->tx_prod = 0;
3166 bp->tx_cons = 0;
3167 bp->tx_prod_bseq = 0;
b6016b76
MC		 3168
3169 val = BNX2_L2CTX_TYPE_TYPE_L2;
3170 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3171 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3172
3173 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3174 val |= 8 << 16;
3175 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3176
3177 val = (u64) bp->tx_desc_mapping >> 32;
3178 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3179
3180 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3181 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3182}
3183
3184static void
3185bnx2_init_rx_ring(struct bnx2 *bp)
3186{
3187 struct rx_bd *rxbd;
3188 int i;
3189 u16 prod, ring_prod;
3190 u32 val;
3191
3192 /* 8 for CRC and VLAN */
3193 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3194 /* 8 for alignment */
3195 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3196
3197 ring_prod = prod = bp->rx_prod = 0;
3198 bp->rx_cons = 0;
3199 bp->rx_prod_bseq = 0;
3200
3201 rxbd = &bp->rx_desc_ring[0];
3202 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3203 rxbd->rx_bd_len = bp->rx_buf_use_size;
3204 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3205 }
3206
3207 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3208 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3209
3210 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3211 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3212 val |= 0x02 << 8;
3213 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3214
3215 val = (u64) bp->rx_desc_mapping >> 32;
3216 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3217
3218 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3219 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3220
3221 for ( ;ring_prod < bp->rx_ring_size; ) {
3222 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3223 break;
3224 }
3225 prod = NEXT_RX_BD(prod);
3226 ring_prod = RX_RING_IDX(prod);
3227 }
3228 bp->rx_prod = prod;
3229
3230 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3231
3232 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3233}
3234
3235static void
3236bnx2_free_tx_skbs(struct bnx2 *bp)
3237{
3238 int i;
3239
3240 if (bp->tx_buf_ring == NULL)
3241 return;
3242
3243 for (i = 0; i < TX_DESC_CNT; ) {
3244 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3245 struct sk_buff *skb = tx_buf->skb;
3246 int j, last;
3247
3248 if (skb == NULL) {
3249 i++;
3250 continue;
3251 }
3252
3253 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3254 skb_headlen(skb), PCI_DMA_TODEVICE);
3255
3256 tx_buf->skb = NULL;
3257
3258 last = skb_shinfo(skb)->nr_frags;
3259 for (j = 0; j < last; j++) {
3260 tx_buf = &bp->tx_buf_ring[i + j + 1];
3261 pci_unmap_page(bp->pdev,
3262 pci_unmap_addr(tx_buf, mapping),
3263 skb_shinfo(skb)->frags[j].size,
3264 PCI_DMA_TODEVICE);
3265 }
3266 dev_kfree_skb_any(skb);
3267 i += j + 1;
3268 }
3269
3270}
3271
3272static void
3273bnx2_free_rx_skbs(struct bnx2 *bp)
3274{
3275 int i;
3276
3277 if (bp->rx_buf_ring == NULL)
3278 return;
3279
3280 for (i = 0; i < RX_DESC_CNT; i++) {
3281 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3282 struct sk_buff *skb = rx_buf->skb;
3283
3284 if (skb == 0)
3285 continue;
3286
3287 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3288 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3289
3290 rx_buf->skb = NULL;
3291
3292 dev_kfree_skb_any(skb);
3293 }
3294}
3295
3296static void
3297bnx2_free_skbs(struct bnx2 *bp)
3298{
3299 bnx2_free_tx_skbs(bp);
3300 bnx2_free_rx_skbs(bp);
3301}
3302
3303static int
3304bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3305{
3306 int rc;
3307
3308 rc = bnx2_reset_chip(bp, reset_code);
3309 bnx2_free_skbs(bp);
3310 if (rc)
3311 return rc;
3312
3313 bnx2_init_chip(bp);
3314 bnx2_init_tx_ring(bp);
3315 bnx2_init_rx_ring(bp);
3316 return 0;
3317}
3318
3319static int
3320bnx2_init_nic(struct bnx2 *bp)
3321{
3322 int rc;
3323
3324 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3325 return rc;
3326
3327 bnx2_init_phy(bp);
3328 bnx2_set_link(bp);
3329 return 0;
3330}
3331
3332static int
3333bnx2_test_registers(struct bnx2 *bp)
3334{
3335 int ret;
3336 int i;
3337 static struct {
3338 u16 offset;
3339 u16 flags;
3340 u32 rw_mask;
3341 u32 ro_mask;
3342 } reg_tbl[] = {
3343 { 0x006c, 0, 0x00000000, 0x0000003f },
3344 { 0x0090, 0, 0xffffffff, 0x00000000 },
3345 { 0x0094, 0, 0x00000000, 0x00000000 },
3346
3347 { 0x0404, 0, 0x00003f00, 0x00000000 },
3348 { 0x0418, 0, 0x00000000, 0xffffffff },
3349 { 0x041c, 0, 0x00000000, 0xffffffff },
3350 { 0x0420, 0, 0x00000000, 0x80ffffff },
3351 { 0x0424, 0, 0x00000000, 0x00000000 },
3352 { 0x0428, 0, 0x00000000, 0x00000001 },
3353 { 0x0450, 0, 0x00000000, 0x0000ffff },
3354 { 0x0454, 0, 0x00000000, 0xffffffff },
3355 { 0x0458, 0, 0x00000000, 0xffffffff },
3356
3357 { 0x0808, 0, 0x00000000, 0xffffffff },
3358 { 0x0854, 0, 0x00000000, 0xffffffff },
3359 { 0x0868, 0, 0x00000000, 0x77777777 },
3360 { 0x086c, 0, 0x00000000, 0x77777777 },
3361 { 0x0870, 0, 0x00000000, 0x77777777 },
3362 { 0x0874, 0, 0x00000000, 0x77777777 },
3363
3364 { 0x0c00, 0, 0x00000000, 0x00000001 },
3365 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3366 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3367 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3368 { 0x0c30, 0, 0x00000000, 0xffffffff },
3369 { 0x0c34, 0, 0x00000000, 0xffffffff },
3370 { 0x0c38, 0, 0x00000000, 0xffffffff },
3371 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3372 { 0x0c40, 0, 0x00000000, 0xffffffff },
3373 { 0x0c44, 0, 0x00000000, 0xffffffff },
3374 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3375 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3376 { 0x0c50, 0, 0x00000000, 0xffffffff },
3377 { 0x0c54, 0, 0x00000000, 0xffffffff },
3378 { 0x0c58, 0, 0x00000000, 0xffffffff },
3379 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3380 { 0x0c60, 0, 0x00000000, 0xffffffff },
3381 { 0x0c64, 0, 0x00000000, 0xffffffff },
3382 { 0x0c68, 0, 0x00000000, 0xffffffff },
3383 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3384 { 0x0c70, 0, 0x00000000, 0xffffffff },
3385 { 0x0c74, 0, 0x00000000, 0xffffffff },
3386 { 0x0c78, 0, 0x00000000, 0xffffffff },
3387 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3388 { 0x0c80, 0, 0x00000000, 0xffffffff },
3389 { 0x0c84, 0, 0x00000000, 0xffffffff },
3390 { 0x0c88, 0, 0x00000000, 0xffffffff },
3391 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3392 { 0x0c90, 0, 0x00000000, 0xffffffff },
3393 { 0x0c94, 0, 0x00000000, 0xffffffff },
3394 { 0x0c98, 0, 0x00000000, 0xffffffff },
3395 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3396 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3397 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3398 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3399 { 0x0cac, 0, 0x00000000, 0xffffffff },
3400 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3401 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3402 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3403 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3404 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3405 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3406 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3407 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3408 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3409 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3410 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3411 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3412 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3413 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3414 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3415 { 0x0cec, 0, 0x00000000, 0xffffffff },
3416 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3417 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3418 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3419 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3420 { 0x0d00, 0, 0x00000000, 0xffffffff },
3421 { 0x0d04, 0, 0x00000000, 0xffffffff },
3422
3423 { 0x1000, 0, 0x00000000, 0x00000001 },
3424 { 0x1004, 0, 0x00000000, 0x000f0001 },
3425 { 0x1044, 0, 0x00000000, 0xffc003ff },
3426 { 0x1080, 0, 0x00000000, 0x0001ffff },
3427 { 0x1084, 0, 0x00000000, 0xffffffff },
3428 { 0x1088, 0, 0x00000000, 0xffffffff },
3429 { 0x108c, 0, 0x00000000, 0xffffffff },
3430 { 0x1090, 0, 0x00000000, 0xffffffff },
3431 { 0x1094, 0, 0x00000000, 0xffffffff },
3432 { 0x1098, 0, 0x00000000, 0xffffffff },
3433 { 0x109c, 0, 0x00000000, 0xffffffff },
3434 { 0x10a0, 0, 0x00000000, 0xffffffff },
3435
3436 { 0x1408, 0, 0x01c00800, 0x00000000 },
3437 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3438 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 3439 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 3440 { 0x14b0, 0, 0x00000002, 0x00000001 },
3441 { 0x14b8, 0, 0x00000000, 0x00000000 },
3442 { 0x14c0, 0, 0x00000000, 0x00000009 },
3443 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3444 { 0x14cc, 0, 0x00000000, 0x00000001 },
3445 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3446 { 0x1500, 0, 0x00000000, 0xffffffff },
3447 { 0x1504, 0, 0x00000000, 0xffffffff },
3448 { 0x1508, 0, 0x00000000, 0xffffffff },
3449 { 0x150c, 0, 0x00000000, 0xffffffff },
3450 { 0x1510, 0, 0x00000000, 0xffffffff },
3451 { 0x1514, 0, 0x00000000, 0xffffffff },
3452 { 0x1518, 0, 0x00000000, 0xffffffff },
3453 { 0x151c, 0, 0x00000000, 0xffffffff },
3454 { 0x1520, 0, 0x00000000, 0xffffffff },
3455 { 0x1524, 0, 0x00000000, 0xffffffff },
3456 { 0x1528, 0, 0x00000000, 0xffffffff },
3457 { 0x152c, 0, 0x00000000, 0xffffffff },
3458 { 0x1530, 0, 0x00000000, 0xffffffff },
3459 { 0x1534, 0, 0x00000000, 0xffffffff },
3460 { 0x1538, 0, 0x00000000, 0xffffffff },
3461 { 0x153c, 0, 0x00000000, 0xffffffff },
3462 { 0x1540, 0, 0x00000000, 0xffffffff },
3463 { 0x1544, 0, 0x00000000, 0xffffffff },
3464 { 0x1548, 0, 0x00000000, 0xffffffff },
3465 { 0x154c, 0, 0x00000000, 0xffffffff },
3466 { 0x1550, 0, 0x00000000, 0xffffffff },
3467 { 0x1554, 0, 0x00000000, 0xffffffff },
3468 { 0x1558, 0, 0x00000000, 0xffffffff },
3469 { 0x1600, 0, 0x00000000, 0xffffffff },
3470 { 0x1604, 0, 0x00000000, 0xffffffff },
3471 { 0x1608, 0, 0x00000000, 0xffffffff },
3472 { 0x160c, 0, 0x00000000, 0xffffffff },
3473 { 0x1610, 0, 0x00000000, 0xffffffff },
3474 { 0x1614, 0, 0x00000000, 0xffffffff },
3475 { 0x1618, 0, 0x00000000, 0xffffffff },
3476 { 0x161c, 0, 0x00000000, 0xffffffff },
3477 { 0x1620, 0, 0x00000000, 0xffffffff },
3478 { 0x1624, 0, 0x00000000, 0xffffffff },
3479 { 0x1628, 0, 0x00000000, 0xffffffff },
3480 { 0x162c, 0, 0x00000000, 0xffffffff },
3481 { 0x1630, 0, 0x00000000, 0xffffffff },
3482 { 0x1634, 0, 0x00000000, 0xffffffff },
3483 { 0x1638, 0, 0x00000000, 0xffffffff },
3484 { 0x163c, 0, 0x00000000, 0xffffffff },
3485 { 0x1640, 0, 0x00000000, 0xffffffff },
3486 { 0x1644, 0, 0x00000000, 0xffffffff },
3487 { 0x1648, 0, 0x00000000, 0xffffffff },
3488 { 0x164c, 0, 0x00000000, 0xffffffff },
3489 { 0x1650, 0, 0x00000000, 0xffffffff },
3490 { 0x1654, 0, 0x00000000, 0xffffffff },
3491
3492 { 0x1800, 0, 0x00000000, 0x00000001 },
3493 { 0x1804, 0, 0x00000000, 0x00000003 },
3494 { 0x1840, 0, 0x00000000, 0xffffffff },
3495 { 0x1844, 0, 0x00000000, 0xffffffff },
3496 { 0x1848, 0, 0x00000000, 0xffffffff },
3497 { 0x184c, 0, 0x00000000, 0xffffffff },
3498 { 0x1850, 0, 0x00000000, 0xffffffff },
3499 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3500 { 0x1904, 0, 0xffffffff, 0x00000000 },
3501 { 0x190c, 0, 0xffffffff, 0x00000000 },
3502 { 0x1914, 0, 0xffffffff, 0x00000000 },
3503 { 0x191c, 0, 0xffffffff, 0x00000000 },
3504 { 0x1924, 0, 0xffffffff, 0x00000000 },
3505 { 0x192c, 0, 0xffffffff, 0x00000000 },
3506 { 0x1934, 0, 0xffffffff, 0x00000000 },
3507 { 0x193c, 0, 0xffffffff, 0x00000000 },
3508 { 0x1944, 0, 0xffffffff, 0x00000000 },
3509 { 0x194c, 0, 0xffffffff, 0x00000000 },
3510 { 0x1954, 0, 0xffffffff, 0x00000000 },
3511 { 0x195c, 0, 0xffffffff, 0x00000000 },
3512 { 0x1964, 0, 0xffffffff, 0x00000000 },
3513 { 0x196c, 0, 0xffffffff, 0x00000000 },
3514 { 0x1974, 0, 0xffffffff, 0x00000000 },
3515 { 0x197c, 0, 0xffffffff, 0x00000000 },
3516 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3517
3518 { 0x1c00, 0, 0x00000000, 0x00000001 },
3519 { 0x1c04, 0, 0x00000000, 0x00000003 },
3520 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3521 { 0x1c40, 0, 0x00000000, 0xffffffff },
3522 { 0x1c44, 0, 0x00000000, 0xffffffff },
3523 { 0x1c48, 0, 0x00000000, 0xffffffff },
3524 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3525 { 0x1c50, 0, 0x00000000, 0xffffffff },
3526 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3527 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3528 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3529 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3530 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3531 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3532 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3533 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3534 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3535 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3536 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3537 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3538 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3539 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3540 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3541 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3542 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3543 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3544
3545 { 0x2004, 0, 0x00000000, 0x0337000f },
3546 { 0x2008, 0, 0xffffffff, 0x00000000 },
3547 { 0x200c, 0, 0xffffffff, 0x00000000 },
3548 { 0x2010, 0, 0xffffffff, 0x00000000 },
3549 { 0x2014, 0, 0x801fff80, 0x00000000 },
3550 { 0x2018, 0, 0x000003ff, 0x00000000 },
3551
3552 { 0x2800, 0, 0x00000000, 0x00000001 },
3553 { 0x2804, 0, 0x00000000, 0x00003f01 },
3554 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3555 { 0x2810, 0, 0xffff0000, 0x00000000 },
3556 { 0x2814, 0, 0xffff0000, 0x00000000 },
3557 { 0x2818, 0, 0xffff0000, 0x00000000 },
3558 { 0x281c, 0, 0xffff0000, 0x00000000 },
3559 { 0x2834, 0, 0xffffffff, 0x00000000 },
3560 { 0x2840, 0, 0x00000000, 0xffffffff },
3561 { 0x2844, 0, 0x00000000, 0xffffffff },
3562 { 0x2848, 0, 0xffffffff, 0x00000000 },
3563 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3564
3565 { 0x2c00, 0, 0x00000000, 0x00000011 },
3566 { 0x2c04, 0, 0x00000000, 0x00030007 },
3567
3568 { 0x3000, 0, 0x00000000, 0x00000001 },
3569 { 0x3004, 0, 0x00000000, 0x007007ff },
3570 { 0x3008, 0, 0x00000003, 0x00000000 },
3571 { 0x300c, 0, 0xffffffff, 0x00000000 },
3572 { 0x3010, 0, 0xffffffff, 0x00000000 },
3573 { 0x3014, 0, 0xffffffff, 0x00000000 },
3574 { 0x3034, 0, 0xffffffff, 0x00000000 },
3575 { 0x3038, 0, 0xffffffff, 0x00000000 },
3576 { 0x3050, 0, 0x00000001, 0x00000000 },
3577
3578 { 0x3c00, 0, 0x00000000, 0x00000001 },
3579 { 0x3c04, 0, 0x00000000, 0x00070000 },
3580 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3581 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3582 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3583 { 0x3c14, 0, 0x00000000, 0xffffffff },
3584 { 0x3c18, 0, 0x00000000, 0xffffffff },
3585 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3586 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3587 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3588 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3589 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3590 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3591 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3592 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3593 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3594 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3595 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3596 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3597 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3598 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3599 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3600 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3601 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3602 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3603 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3604 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3605 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3606 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3607 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3608 { 0x3c78, 0, 0x00000000, 0x00000000 },
3609 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3610 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3611 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3612 { 0x3c88, 0, 0x00000000, 0xffffffff },
3613 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3614
3615 { 0x4000, 0, 0x00000000, 0x00000001 },
3616 { 0x4004, 0, 0x00000000, 0x00030000 },
3617 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3618 { 0x400c, 0, 0xffffffff, 0x00000000 },
3619 { 0x4088, 0, 0x00000000, 0x00070303 },
3620
3621 { 0x4400, 0, 0x00000000, 0x00000001 },
3622 { 0x4404, 0, 0x00000000, 0x00003f01 },
3623 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3624 { 0x440c, 0, 0xffffffff, 0x00000000 },
3625 { 0x4410, 0, 0xffff, 0x0000 },
3626 { 0x4414, 0, 0xffff, 0x0000 },
3627 { 0x4418, 0, 0xffff, 0x0000 },
3628 { 0x441c, 0, 0xffff, 0x0000 },
3629 { 0x4428, 0, 0xffffffff, 0x00000000 },
3630 { 0x442c, 0, 0xffffffff, 0x00000000 },
3631 { 0x4430, 0, 0xffffffff, 0x00000000 },
3632 { 0x4434, 0, 0xffffffff, 0x00000000 },
3633 { 0x4438, 0, 0xffffffff, 0x00000000 },
3634 { 0x443c, 0, 0xffffffff, 0x00000000 },
3635 { 0x4440, 0, 0xffffffff, 0x00000000 },
3636 { 0x4444, 0, 0xffffffff, 0x00000000 },
3637
3638 { 0x4c00, 0, 0x00000000, 0x00000001 },
3639 { 0x4c04, 0, 0x00000000, 0x0000003f },
3640 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3641 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3642 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3643 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3644 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3645 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3646 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3647 { 0x4c50, 0, 0x00000000, 0xffffffff },
3648
3649 { 0x5004, 0, 0x00000000, 0x0000007f },
3650 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3651 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3652
3653 { 0x5400, 0, 0x00000008, 0x00000001 },
3654 { 0x5404, 0, 0x00000000, 0x0000003f },
3655 { 0x5408, 0, 0x0000001f, 0x00000000 },
3656 { 0x540c, 0, 0xffffffff, 0x00000000 },
3657 { 0x5410, 0, 0xffffffff, 0x00000000 },
3658 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3659 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3660 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3661 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3662 { 0x5428, 0, 0x000000ff, 0x00000000 },
3663 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3664 { 0x5430, 0, 0x001fff80, 0x00000000 },
3665 { 0x5438, 0, 0xffffffff, 0x00000000 },
3666 { 0x543c, 0, 0xffffffff, 0x00000000 },
3667 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3668
3669 { 0x5c00, 0, 0x00000000, 0x00000001 },
3670 { 0x5c04, 0, 0x00000000, 0x0003000f },
3671 { 0x5c08, 0, 0x00000003, 0x00000000 },
3672 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3673 { 0x5c10, 0, 0x00000000, 0xffffffff },
3674 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3675 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3676 { 0x5c88, 0, 0x00000000, 0x00077373 },
3677 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3678
3679 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3680 { 0x680c, 0, 0xffffffff, 0x00000000 },
3681 { 0x6810, 0, 0xffffffff, 0x00000000 },
3682 { 0x6814, 0, 0xffffffff, 0x00000000 },
3683 { 0x6818, 0, 0xffffffff, 0x00000000 },
3684 { 0x681c, 0, 0xffffffff, 0x00000000 },
3685 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3686 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3687 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3688 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3689 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3690 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3691 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3692 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3693 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3694 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3695 { 0x684c, 0, 0xffffffff, 0x00000000 },
3696 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3697 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3698 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3699 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3700 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3701 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3702
3703 { 0xffff, 0, 0x00000000, 0x00000000 },
3704 };
3705
3706 ret = 0;
3707 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3708 u32 offset, rw_mask, ro_mask, save_val, val;
3709
3710 offset = (u32) reg_tbl[i].offset;
3711 rw_mask = reg_tbl[i].rw_mask;
3712 ro_mask = reg_tbl[i].ro_mask;
3713
14ab9b86 3714 save_val = readl(bp->regview + offset);
b6016b76 3715
14ab9b86 3716 writel(0, bp->regview + offset);
b6016b76 3717
14ab9b86 3718 val = readl(bp->regview + offset);
b6016b76
MC		 3719 if ((val & rw_mask) != 0) {
3720 goto reg_test_err;
3721 }
3722
3723 if ((val & ro_mask) != (save_val & ro_mask)) {
3724 goto reg_test_err;
3725 }
3726
14ab9b86 3727 writel(0xffffffff, bp->regview + offset);
b6016b76 3728
14ab9b86 3729 val = readl(bp->regview + offset);
b6016b76
MC		 3730 if ((val & rw_mask) != rw_mask) {
3731 goto reg_test_err;
3732 }
3733
3734 if ((val & ro_mask) != (save_val & ro_mask)) {
3735 goto reg_test_err;
3736 }
3737
14ab9b86 3738 writel(save_val, bp->regview + offset);
b6016b76
MC		 3739 continue;
3740
3741reg_test_err:
14ab9b86 3742 writel(save_val, bp->regview + offset);
b6016b76
MC		 3743 ret = -ENODEV;
3744 break;
3745 }
3746 return ret;
3747}
3748
3749static int
3750bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3751{
3752 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3753 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3754 int i;
3755
3756 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3757 u32 offset;
3758
3759 for (offset = 0; offset < size; offset += 4) {
3760
3761 REG_WR_IND(bp, start + offset, test_pattern[i]);
3762
3763 if (REG_RD_IND(bp, start + offset) !=
3764 test_pattern[i]) {
3765 return -ENODEV;
3766 }
3767 }
3768 }
3769 return 0;
3770}
3771
3772static int
3773bnx2_test_memory(struct bnx2 *bp)
3774{
3775 int ret = 0;
3776 int i;
3777 static struct {
3778 u32 offset;
3779 u32 len;
3780 } mem_tbl[] = {
3781 { 0x60000, 0x4000 },
5b0c76ad 3782 { 0xa0000, 0x3000 },
b6016b76
MC		 3783 { 0xe0000, 0x4000 },
3784 { 0x120000, 0x4000 },
3785 { 0x1a0000, 0x4000 },
3786 { 0x160000, 0x4000 },
3787 { 0xffffffff, 0 },
3788 };
3789
3790 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3791 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3792 mem_tbl[i].len)) != 0) {
3793 return ret;
3794 }
3795 }
3796
3797 return ret;
3798}
3799
3800static int
3801bnx2_test_loopback(struct bnx2 *bp)
3802{
3803 unsigned int pkt_size, num_pkts, i;
3804 struct sk_buff *skb, *rx_skb;
3805 unsigned char *packet;
3806 u16 rx_start_idx, rx_idx, send_idx;
3807 u32 send_bseq, val;
3808 dma_addr_t map;
3809 struct tx_bd *txbd;
3810 struct sw_bd *rx_buf;
3811 struct l2_fhdr *rx_hdr;
3812 int ret = -ENODEV;
3813
3814 if (!netif_running(bp->dev))
3815 return -ENODEV;
3816
3817 bp->loopback = MAC_LOOPBACK;
3818 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3819 bnx2_set_mac_loopback(bp);
3820
3821 pkt_size = 1514;
3822 skb = dev_alloc_skb(pkt_size);
3823 packet = skb_put(skb, pkt_size);
3824 memcpy(packet, bp->mac_addr, 6);
3825 memset(packet + 6, 0x0, 8);
3826 for (i = 14; i < pkt_size; i++)
3827 packet[i] = (unsigned char) (i & 0xff);
3828
3829 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3830 PCI_DMA_TODEVICE);
3831
3832 val = REG_RD(bp, BNX2_HC_COMMAND);
3833 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3834 REG_RD(bp, BNX2_HC_COMMAND);
3835
3836 udelay(5);
3837 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3838
3839 send_idx = 0;
3840 send_bseq = 0;
3841 num_pkts = 0;
3842
3843 txbd = &bp->tx_desc_ring[send_idx];
3844
3845 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3846 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3847 txbd->tx_bd_mss_nbytes = pkt_size;
3848 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3849
3850 num_pkts++;
3851 send_idx = NEXT_TX_BD(send_idx);
3852
3853 send_bseq += pkt_size;
3854
3855 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3856 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3857
3858
3859 udelay(100);
3860
3861 val = REG_RD(bp, BNX2_HC_COMMAND);
3862 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3863 REG_RD(bp, BNX2_HC_COMMAND);
3864
3865 udelay(5);
3866
3867 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3868 dev_kfree_skb_irq(skb);
3869
3870 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3871 goto loopback_test_done;
3872 }
3873
3874 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3875 if (rx_idx != rx_start_idx + num_pkts) {
3876 goto loopback_test_done;
3877 }
3878
3879 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3880 rx_skb = rx_buf->skb;
3881
3882 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3883 skb_reserve(rx_skb, bp->rx_offset);
3884
3885 pci_dma_sync_single_for_cpu(bp->pdev,
3886 pci_unmap_addr(rx_buf, mapping),
3887 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3888
3889 if (rx_hdr->l2_fhdr_errors &
3890 (L2_FHDR_ERRORS_BAD_CRC |
3891 L2_FHDR_ERRORS_PHY_DECODE |
3892 L2_FHDR_ERRORS_ALIGNMENT |
3893 L2_FHDR_ERRORS_TOO_SHORT |
3894 L2_FHDR_ERRORS_GIANT_FRAME)) {
3895
3896 goto loopback_test_done;
3897 }
3898
3899 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3900 goto loopback_test_done;
3901 }
3902
3903 for (i = 14; i < pkt_size; i++) {
3904 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3905 goto loopback_test_done;
3906 }
3907 }
3908
3909 ret = 0;
3910
3911loopback_test_done:
3912 bp->loopback = 0;
3913 return ret;
3914}
3915
3916#define NVRAM_SIZE 0x200
3917#define CRC32_RESIDUAL 0xdebb20e3
3918
3919static int
3920bnx2_test_nvram(struct bnx2 *bp)
3921{
3922 u32 buf[NVRAM_SIZE / 4];
3923 u8 *data = (u8 *) buf;
3924 int rc = 0;
3925 u32 magic, csum;
3926
3927 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3928 goto test_nvram_done;
3929
3930 magic = be32_to_cpu(buf[0]);
3931 if (magic != 0x669955aa) {
3932 rc = -ENODEV;
3933 goto test_nvram_done;
3934 }
3935
3936 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3937 goto test_nvram_done;
3938
3939 csum = ether_crc_le(0x100, data);
3940 if (csum != CRC32_RESIDUAL) {
3941 rc = -ENODEV;
3942 goto test_nvram_done;
3943 }
3944
3945 csum = ether_crc_le(0x100, data + 0x100);
3946 if (csum != CRC32_RESIDUAL) {
3947 rc = -ENODEV;
3948 }
3949
3950test_nvram_done:
3951 return rc;
3952}
3953
3954static int
3955bnx2_test_link(struct bnx2 *bp)
3956{
3957 u32 bmsr;
3958
c770a65c 3959 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3960 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3961 bnx2_read_phy(bp, MII_BMSR, &bmsr);
c770a65c 3962 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3963
3964 if (bmsr & BMSR_LSTATUS) {
3965 return 0;
3966 }
3967 return -ENODEV;
3968}
3969
3970static int
3971bnx2_test_intr(struct bnx2 *bp)
3972{
3973 int i;
3974 u32 val;
3975 u16 status_idx;
3976
3977 if (!netif_running(bp->dev))
3978 return -ENODEV;
3979
3980 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3981
3982 /* This register is not touched during run-time. */
3983 val = REG_RD(bp, BNX2_HC_COMMAND);
3984 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3985 REG_RD(bp, BNX2_HC_COMMAND);
3986
3987 for (i = 0; i < 10; i++) {
3988 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3989 status_idx) {
3990
3991 break;
3992 }
3993
3994 msleep_interruptible(10);
3995 }
3996 if (i < 10)
3997 return 0;
3998
3999 return -ENODEV;
4000}
4001
4002static void
4003bnx2_timer(unsigned long data)
4004{
4005 struct bnx2 *bp = (struct bnx2 *) data;
4006 u32 msg;
4007
cd339a0e
MC		 4008 if (!netif_running(bp->dev))
4009 return;
4010
b6016b76
MC		 4011 if (atomic_read(&bp->intr_sem) != 0)
4012 goto bnx2_restart_timer;
4013
4014 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4015 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
4016
4017 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4018 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
b6016b76 4019
c770a65c 4020 spin_lock(&bp->phy_lock);
b6016b76
MC		 4021 if (bp->serdes_an_pending) {
4022 bp->serdes_an_pending--;
4023 }
4024 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4025 u32 bmcr;
4026
cd339a0e
MC		 4027 bp->current_interval = bp->timer_interval;
4028
b6016b76
MC		 4029 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4030
4031 if (bmcr & BMCR_ANENABLE) {
4032 u32 phy1, phy2;
4033
4034 bnx2_write_phy(bp, 0x1c, 0x7c00);
4035 bnx2_read_phy(bp, 0x1c, &phy1);
4036
4037 bnx2_write_phy(bp, 0x17, 0x0f01);
4038 bnx2_read_phy(bp, 0x15, &phy2);
4039 bnx2_write_phy(bp, 0x17, 0x0f01);
4040 bnx2_read_phy(bp, 0x15, &phy2);
4041
4042 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4043 !(phy2 & 0x20)) { /* no CONFIG */
4044
4045 bmcr &= ~BMCR_ANENABLE;
4046 bmcr |= BMCR_SPEED1000 |
4047 BMCR_FULLDPLX;
4048 bnx2_write_phy(bp, MII_BMCR, bmcr);
4049 bp->phy_flags |=
4050 PHY_PARALLEL_DETECT_FLAG;
4051 }
4052 }
4053 }
4054 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4055 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4056 u32 phy2;
4057
4058 bnx2_write_phy(bp, 0x17, 0x0f01);
4059 bnx2_read_phy(bp, 0x15, &phy2);
4060 if (phy2 & 0x20) {
4061 u32 bmcr;
4062
4063 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4064 bmcr |= BMCR_ANENABLE;
4065 bnx2_write_phy(bp, MII_BMCR, bmcr);
4066
4067 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4068
4069 }
4070 }
cd339a0e
MC		 4071 else
4072 bp->current_interval = bp->timer_interval;
b6016b76 4073
c770a65c 4074 spin_unlock(&bp->phy_lock);
b6016b76
MC		 4075 }
4076
4077bnx2_restart_timer:
cd339a0e 4078 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4079}
4080
4081/* Called with rtnl_lock */
4082static int
4083bnx2_open(struct net_device *dev)
4084{
4085 struct bnx2 *bp = dev->priv;
4086 int rc;
4087
829ca9a3 4088 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 4089 bnx2_disable_int(bp);
4090
4091 rc = bnx2_alloc_mem(bp);
4092 if (rc)
4093 return rc;
4094
4095 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4096 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4097 !disable_msi) {
4098
4099 if (pci_enable_msi(bp->pdev) == 0) {
4100 bp->flags |= USING_MSI_FLAG;
4101 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4102 dev);
4103 }
4104 else {
4105 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4106 SA_SHIRQ, dev->name, dev);
4107 }
4108 }
4109 else {
4110 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4111 dev->name, dev);
4112 }
4113 if (rc) {
4114 bnx2_free_mem(bp);
4115 return rc;
4116 }
4117
4118 rc = bnx2_init_nic(bp);
4119
4120 if (rc) {
4121 free_irq(bp->pdev->irq, dev);
4122 if (bp->flags & USING_MSI_FLAG) {
4123 pci_disable_msi(bp->pdev);
4124 bp->flags &= ~USING_MSI_FLAG;
4125 }
4126 bnx2_free_skbs(bp);
4127 bnx2_free_mem(bp);
4128 return rc;
4129 }
4130
cd339a0e 4131 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4132
4133 atomic_set(&bp->intr_sem, 0);
4134
4135 bnx2_enable_int(bp);
4136
4137 if (bp->flags & USING_MSI_FLAG) {
4138 /* Test MSI to make sure it is working
4139 * If MSI test fails, go back to INTx mode
4140 */
4141 if (bnx2_test_intr(bp) != 0) {
4142 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4143 " using MSI, switching to INTx mode. Please"
4144 " report this failure to the PCI maintainer"
4145 " and include system chipset information.\n",
4146 bp->dev->name);
4147
4148 bnx2_disable_int(bp);
4149 free_irq(bp->pdev->irq, dev);
4150 pci_disable_msi(bp->pdev);
4151 bp->flags &= ~USING_MSI_FLAG;
4152
4153 rc = bnx2_init_nic(bp);
4154
4155 if (!rc) {
4156 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4157 SA_SHIRQ, dev->name, dev);
4158 }
4159 if (rc) {
4160 bnx2_free_skbs(bp);
4161 bnx2_free_mem(bp);
4162 del_timer_sync(&bp->timer);
4163 return rc;
4164 }
4165 bnx2_enable_int(bp);
4166 }
4167 }
4168 if (bp->flags & USING_MSI_FLAG) {
4169 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4170 }
4171
4172 netif_start_queue(dev);
4173
4174 return 0;
4175}
4176
4177static void
4178bnx2_reset_task(void *data)
4179{
4180 struct bnx2 *bp = data;
4181
afdc08b9
MC		 4182 if (!netif_running(bp->dev))
4183 return;
4184
4185 bp->in_reset_task = 1;
b6016b76
MC		 4186 bnx2_netif_stop(bp);
4187
4188 bnx2_init_nic(bp);
4189
4190 atomic_set(&bp->intr_sem, 1);
4191 bnx2_netif_start(bp);
afdc08b9 4192 bp->in_reset_task = 0;
b6016b76
MC		 4193}
4194
4195static void
4196bnx2_tx_timeout(struct net_device *dev)
4197{
4198 struct bnx2 *bp = dev->priv;
4199
4200 /* This allows the netif to be shutdown gracefully before resetting */
4201 schedule_work(&bp->reset_task);
4202}
4203
4204#ifdef BCM_VLAN
4205/* Called with rtnl_lock */
4206static void
4207bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4208{
4209 struct bnx2 *bp = dev->priv;
4210
4211 bnx2_netif_stop(bp);
4212
4213 bp->vlgrp = vlgrp;
4214 bnx2_set_rx_mode(dev);
4215
4216 bnx2_netif_start(bp);
4217}
4218
4219/* Called with rtnl_lock */
4220static void
4221bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4222{
4223 struct bnx2 *bp = dev->priv;
4224
4225 bnx2_netif_stop(bp);
4226
4227 if (bp->vlgrp)
4228 bp->vlgrp->vlan_devices[vid] = NULL;
4229 bnx2_set_rx_mode(dev);
4230
4231 bnx2_netif_start(bp);
4232}
4233#endif
4234
4235/* Called with dev->xmit_lock.
4236 * hard_start_xmit is pseudo-lockless - a lock is only required when
4237 * the tx queue is full. This way, we get the benefit of lockless
4238 * operations most of the time without the complexities to handle
4239 * netif_stop_queue/wake_queue race conditions.
4240 */
4241static int
4242bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4243{
4244 struct bnx2 *bp = dev->priv;
4245 dma_addr_t mapping;
4246 struct tx_bd *txbd;
4247 struct sw_bd *tx_buf;
4248 u32 len, vlan_tag_flags, last_frag, mss;
4249 u16 prod, ring_prod;
4250 int i;
4251
e89bbf10 4252 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 4253 netif_stop_queue(dev);
4254 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4255 dev->name);
4256
4257 return NETDEV_TX_BUSY;
4258 }
4259 len = skb_headlen(skb);
4260 prod = bp->tx_prod;
4261 ring_prod = TX_RING_IDX(prod);
4262
4263 vlan_tag_flags = 0;
4264 if (skb->ip_summed == CHECKSUM_HW) {
4265 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4266 }
4267
4268 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4269 vlan_tag_flags |=
4270 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4271 }
4272#ifdef BCM_TSO
4273 if ((mss = skb_shinfo(skb)->tso_size) &&
4274 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4275 u32 tcp_opt_len, ip_tcp_len;
4276
4277 if (skb_header_cloned(skb) &&
4278 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4279 dev_kfree_skb(skb);
4280 return NETDEV_TX_OK;
4281 }
4282
4283 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4284 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4285
4286 tcp_opt_len = 0;
4287 if (skb->h.th->doff > 5) {
4288 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4289 }
4290 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4291
4292 skb->nh.iph->check = 0;
4293 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4294 skb->h.th->check =
4295 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4296 skb->nh.iph->daddr,
4297 0, IPPROTO_TCP, 0);
4298
4299 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4300 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4301 (tcp_opt_len >> 2)) << 8;
4302 }
4303 }
4304 else
4305#endif
4306 {
4307 mss = 0;
4308 }
4309
4310 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4311
4312 tx_buf = &bp->tx_buf_ring[ring_prod];
4313 tx_buf->skb = skb;
4314 pci_unmap_addr_set(tx_buf, mapping, mapping);
4315
4316 txbd = &bp->tx_desc_ring[ring_prod];
4317
4318 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4319 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4320 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4321 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4322
4323 last_frag = skb_shinfo(skb)->nr_frags;
4324
4325 for (i = 0; i < last_frag; i++) {
4326 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4327
4328 prod = NEXT_TX_BD(prod);
4329 ring_prod = TX_RING_IDX(prod);
4330 txbd = &bp->tx_desc_ring[ring_prod];
4331
4332 len = frag->size;
4333 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4334 len, PCI_DMA_TODEVICE);
4335 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4336 mapping, mapping);
4337
4338 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4339 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4340 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4341 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4342
4343 }
4344 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4345
4346 prod = NEXT_TX_BD(prod);
4347 bp->tx_prod_bseq += skb->len;
4348
b6016b76
MC		 4349 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4350 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4351
4352 mmiowb();
4353
4354 bp->tx_prod = prod;
4355 dev->trans_start = jiffies;
4356
e89bbf10 4357 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
c770a65c 4358 spin_lock(&bp->tx_lock);
e89bbf10
MC		 4359 netif_stop_queue(dev);
4360
4361 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4362 netif_wake_queue(dev);
c770a65c 4363 spin_unlock(&bp->tx_lock);
b6016b76
MC		 4364 }
4365
4366 return NETDEV_TX_OK;
4367}
4368
4369/* Called with rtnl_lock */
4370static int
4371bnx2_close(struct net_device *dev)
4372{
4373 struct bnx2 *bp = dev->priv;
4374 u32 reset_code;
4375
afdc08b9
MC		 4376 /* Calling flush_scheduled_work() may deadlock because
4377 * linkwatch_event() may be on the workqueue and it will try to get
4378 * the rtnl_lock which we are holding.
4379 */
4380 while (bp->in_reset_task)
4381 msleep(1);
4382
b6016b76
MC		 4383 bnx2_netif_stop(bp);
4384 del_timer_sync(&bp->timer);
4385 if (bp->wol)
4386 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4387 else
4388 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4389 bnx2_reset_chip(bp, reset_code);
4390 free_irq(bp->pdev->irq, dev);
4391 if (bp->flags & USING_MSI_FLAG) {
4392 pci_disable_msi(bp->pdev);
4393 bp->flags &= ~USING_MSI_FLAG;
4394 }
4395 bnx2_free_skbs(bp);
4396 bnx2_free_mem(bp);
4397 bp->link_up = 0;
4398 netif_carrier_off(bp->dev);
829ca9a3 4399 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 4400 return 0;
4401}
4402
4403#define GET_NET_STATS64(ctr) \
4404 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4405 (unsigned long) (ctr##_lo)
4406
4407#define GET_NET_STATS32(ctr) \
4408 (ctr##_lo)
4409
4410#if (BITS_PER_LONG == 64)
4411#define GET_NET_STATS GET_NET_STATS64
4412#else
4413#define GET_NET_STATS GET_NET_STATS32
4414#endif
4415
4416static struct net_device_stats *
4417bnx2_get_stats(struct net_device *dev)
4418{
4419 struct bnx2 *bp = dev->priv;
4420 struct statistics_block *stats_blk = bp->stats_blk;
4421 struct net_device_stats *net_stats = &bp->net_stats;
4422
4423 if (bp->stats_blk == NULL) {
4424 return net_stats;
4425 }
4426 net_stats->rx_packets =
4427 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4428 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4429 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4430
4431 net_stats->tx_packets =
4432 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4433 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4434 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4435
4436 net_stats->rx_bytes =
4437 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4438
4439 net_stats->tx_bytes =
4440 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4441
4442 net_stats->multicast =
4443 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4444
4445 net_stats->collisions =
4446 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4447
4448 net_stats->rx_length_errors =
4449 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4450 stats_blk->stat_EtherStatsOverrsizePkts);
4451
4452 net_stats->rx_over_errors =
4453 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4454
4455 net_stats->rx_frame_errors =
4456 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4457
4458 net_stats->rx_crc_errors =
4459 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4460
4461 net_stats->rx_errors = net_stats->rx_length_errors +
4462 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4463 net_stats->rx_crc_errors;
4464
4465 net_stats->tx_aborted_errors =
4466 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4467 stats_blk->stat_Dot3StatsLateCollisions);
4468
5b0c76ad
MC		 4469 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4470 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 4471 net_stats->tx_carrier_errors = 0;
4472 else {
4473 net_stats->tx_carrier_errors =
4474 (unsigned long)
4475 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4476 }
4477
4478 net_stats->tx_errors =
4479 (unsigned long)
4480 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4481 +
4482 net_stats->tx_aborted_errors +
4483 net_stats->tx_carrier_errors;
4484
4485 return net_stats;
4486}
4487
4488/* All ethtool functions called with rtnl_lock */
4489
4490static int
4491bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4492{
4493 struct bnx2 *bp = dev->priv;
4494
4495 cmd->supported = SUPPORTED_Autoneg;
4496 if (bp->phy_flags & PHY_SERDES_FLAG) {
4497 cmd->supported |= SUPPORTED_1000baseT_Full |
4498 SUPPORTED_FIBRE;
4499
4500 cmd->port = PORT_FIBRE;
4501 }
4502 else {
4503 cmd->supported |= SUPPORTED_10baseT_Half |
4504 SUPPORTED_10baseT_Full |
4505 SUPPORTED_100baseT_Half |
4506 SUPPORTED_100baseT_Full |
4507 SUPPORTED_1000baseT_Full |
4508 SUPPORTED_TP;
4509
4510 cmd->port = PORT_TP;
4511 }
4512
4513 cmd->advertising = bp->advertising;
4514
4515 if (bp->autoneg & AUTONEG_SPEED) {
4516 cmd->autoneg = AUTONEG_ENABLE;
4517 }
4518 else {
4519 cmd->autoneg = AUTONEG_DISABLE;
4520 }
4521
4522 if (netif_carrier_ok(dev)) {
4523 cmd->speed = bp->line_speed;
4524 cmd->duplex = bp->duplex;
4525 }
4526 else {
4527 cmd->speed = -1;
4528 cmd->duplex = -1;
4529 }
4530
4531 cmd->transceiver = XCVR_INTERNAL;
4532 cmd->phy_address = bp->phy_addr;
4533
4534 return 0;
4535}
4536
4537static int
4538bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4539{
4540 struct bnx2 *bp = dev->priv;
4541 u8 autoneg = bp->autoneg;
4542 u8 req_duplex = bp->req_duplex;
4543 u16 req_line_speed = bp->req_line_speed;
4544 u32 advertising = bp->advertising;
4545
4546 if (cmd->autoneg == AUTONEG_ENABLE) {
4547 autoneg |= AUTONEG_SPEED;
4548
4549 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4550
4551 /* allow advertising 1 speed */
4552 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4553 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4554 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4555 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4556
4557 if (bp->phy_flags & PHY_SERDES_FLAG)
4558 return -EINVAL;
4559
4560 advertising = cmd->advertising;
4561
4562 }
4563 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4564 advertising = cmd->advertising;
4565 }
4566 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4567 return -EINVAL;
4568 }
4569 else {
4570 if (bp->phy_flags & PHY_SERDES_FLAG) {
4571 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4572 }
4573 else {
4574 advertising = ETHTOOL_ALL_COPPER_SPEED;
4575 }
4576 }
4577 advertising |= ADVERTISED_Autoneg;
4578 }
4579 else {
4580 if (bp->phy_flags & PHY_SERDES_FLAG) {
4581 if ((cmd->speed != SPEED_1000) ||
4582 (cmd->duplex != DUPLEX_FULL)) {
4583 return -EINVAL;
4584 }
4585 }
4586 else if (cmd->speed == SPEED_1000) {
4587 return -EINVAL;
4588 }
4589 autoneg &= ~AUTONEG_SPEED;
4590 req_line_speed = cmd->speed;
4591 req_duplex = cmd->duplex;
4592 advertising = 0;
4593 }
4594
4595 bp->autoneg = autoneg;
4596 bp->advertising = advertising;
4597 bp->req_line_speed = req_line_speed;
4598 bp->req_duplex = req_duplex;
4599
c770a65c 4600 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4601
4602 bnx2_setup_phy(bp);
4603
c770a65c 4604 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4605
4606 return 0;
4607}
4608
4609static void
4610bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4611{
4612 struct bnx2 *bp = dev->priv;
4613
4614 strcpy(info->driver, DRV_MODULE_NAME);
4615 strcpy(info->version, DRV_MODULE_VERSION);
4616 strcpy(info->bus_info, pci_name(bp->pdev));
4617 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4618 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4619 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4620 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4621 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4622 info->fw_version[7] = 0;
4623}
4624
4625static void
4626bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4627{
4628 struct bnx2 *bp = dev->priv;
4629
4630 if (bp->flags & NO_WOL_FLAG) {
4631 wol->supported = 0;
4632 wol->wolopts = 0;
4633 }
4634 else {
4635 wol->supported = WAKE_MAGIC;
4636 if (bp->wol)
4637 wol->wolopts = WAKE_MAGIC;
4638 else
4639 wol->wolopts = 0;
4640 }
4641 memset(&wol->sopass, 0, sizeof(wol->sopass));
4642}
4643
4644static int
4645bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4646{
4647 struct bnx2 *bp = dev->priv;
4648
4649 if (wol->wolopts & ~WAKE_MAGIC)
4650 return -EINVAL;
4651
4652 if (wol->wolopts & WAKE_MAGIC) {
4653 if (bp->flags & NO_WOL_FLAG)
4654 return -EINVAL;
4655
4656 bp->wol = 1;
4657 }
4658 else {
4659 bp->wol = 0;
4660 }
4661 return 0;
4662}
4663
4664static int
4665bnx2_nway_reset(struct net_device *dev)
4666{
4667 struct bnx2 *bp = dev->priv;
4668 u32 bmcr;
4669
4670 if (!(bp->autoneg & AUTONEG_SPEED)) {
4671 return -EINVAL;
4672 }
4673
c770a65c 4674 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4675
4676 /* Force a link down visible on the other side */
4677 if (bp->phy_flags & PHY_SERDES_FLAG) {
4678 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
c770a65c 4679 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4680
4681 msleep(20);
4682
c770a65c 4683 spin_lock_bh(&bp->phy_lock);
b6016b76 4684 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
cd339a0e
MC		 4685 bp->current_interval = SERDES_AN_TIMEOUT;
4686 bp->serdes_an_pending = 1;
4687 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4688 }
4689 }
4690
4691 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4692 bmcr &= ~BMCR_LOOPBACK;
4693 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4694
c770a65c 4695 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4696
4697 return 0;
4698}
4699
4700static int
4701bnx2_get_eeprom_len(struct net_device *dev)
4702{
4703 struct bnx2 *bp = dev->priv;
4704
4705 if (bp->flash_info == 0)
4706 return 0;
4707
4708 return (int) bp->flash_info->total_size;
4709}
4710
4711static int
4712bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4713 u8 *eebuf)
4714{
4715 struct bnx2 *bp = dev->priv;
4716 int rc;
4717
4718 if (eeprom->offset > bp->flash_info->total_size)
4719 return -EINVAL;
4720
4721 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4722 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4723
4724 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4725
4726 return rc;
4727}
4728
4729static int
4730bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4731 u8 *eebuf)
4732{
4733 struct bnx2 *bp = dev->priv;
4734 int rc;
4735
4736 if (eeprom->offset > bp->flash_info->total_size)
4737 return -EINVAL;
4738
4739 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4740 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4741
4742 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4743
4744 return rc;
4745}
4746
4747static int
4748bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4749{
4750 struct bnx2 *bp = dev->priv;
4751
4752 memset(coal, 0, sizeof(struct ethtool_coalesce));
4753
4754 coal->rx_coalesce_usecs = bp->rx_ticks;
4755 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4756 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4757 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4758
4759 coal->tx_coalesce_usecs = bp->tx_ticks;
4760 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4761 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4762 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4763
4764 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4765
4766 return 0;
4767}
4768
4769static int
4770bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4771{
4772 struct bnx2 *bp = dev->priv;
4773
4774 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4775 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4776
4777 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4778 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4779
4780 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4781 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4782
4783 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4784 if (bp->rx_quick_cons_trip_int > 0xff)
4785 bp->rx_quick_cons_trip_int = 0xff;
4786
4787 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4788 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4789
4790 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4791 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4792
4793 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4794 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4795
4796 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4797 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4798 0xff;
4799
4800 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4801 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4802 bp->stats_ticks &= 0xffff00;
4803
4804 if (netif_running(bp->dev)) {
4805 bnx2_netif_stop(bp);
4806 bnx2_init_nic(bp);
4807 bnx2_netif_start(bp);
4808 }
4809
4810 return 0;
4811}
4812
4813static void
4814bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4815{
4816 struct bnx2 *bp = dev->priv;
4817
4818 ering->rx_max_pending = MAX_RX_DESC_CNT;
4819 ering->rx_mini_max_pending = 0;
4820 ering->rx_jumbo_max_pending = 0;
4821
4822 ering->rx_pending = bp->rx_ring_size;
4823 ering->rx_mini_pending = 0;
4824 ering->rx_jumbo_pending = 0;
4825
4826 ering->tx_max_pending = MAX_TX_DESC_CNT;
4827 ering->tx_pending = bp->tx_ring_size;
4828}
4829
4830static int
4831bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4832{
4833 struct bnx2 *bp = dev->priv;
4834
4835 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4836 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4837 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4838
4839 return -EINVAL;
4840 }
4841 bp->rx_ring_size = ering->rx_pending;
4842 bp->tx_ring_size = ering->tx_pending;
4843
4844 if (netif_running(bp->dev)) {
4845 bnx2_netif_stop(bp);
4846 bnx2_init_nic(bp);
4847 bnx2_netif_start(bp);
4848 }
4849
4850 return 0;
4851}
4852
4853static void
4854bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4855{
4856 struct bnx2 *bp = dev->priv;
4857
4858 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4859 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4860 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4861}
4862
4863static int
4864bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4865{
4866 struct bnx2 *bp = dev->priv;
4867
4868 bp->req_flow_ctrl = 0;
4869 if (epause->rx_pause)
4870 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4871 if (epause->tx_pause)
4872 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4873
4874 if (epause->autoneg) {
4875 bp->autoneg |= AUTONEG_FLOW_CTRL;
4876 }
4877 else {
4878 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4879 }
4880
c770a65c 4881 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4882
4883 bnx2_setup_phy(bp);
4884
c770a65c 4885 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4886
4887 return 0;
4888}
4889
4890static u32
4891bnx2_get_rx_csum(struct net_device *dev)
4892{
4893 struct bnx2 *bp = dev->priv;
4894
4895 return bp->rx_csum;
4896}
4897
4898static int
4899bnx2_set_rx_csum(struct net_device *dev, u32 data)
4900{
4901 struct bnx2 *bp = dev->priv;
4902
4903 bp->rx_csum = data;
4904 return 0;
4905}
4906
4907#define BNX2_NUM_STATS 45
4908
14ab9b86 4909static struct {
b6016b76
MC		 4910 char string[ETH_GSTRING_LEN];
4911} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4912 { "rx_bytes" },
4913 { "rx_error_bytes" },
4914 { "tx_bytes" },
4915 { "tx_error_bytes" },
4916 { "rx_ucast_packets" },
4917 { "rx_mcast_packets" },
4918 { "rx_bcast_packets" },
4919 { "tx_ucast_packets" },
4920 { "tx_mcast_packets" },
4921 { "tx_bcast_packets" },
4922 { "tx_mac_errors" },
4923 { "tx_carrier_errors" },
4924 { "rx_crc_errors" },
4925 { "rx_align_errors" },
4926 { "tx_single_collisions" },
4927 { "tx_multi_collisions" },
4928 { "tx_deferred" },
4929 { "tx_excess_collisions" },
4930 { "tx_late_collisions" },
4931 { "tx_total_collisions" },
4932 { "rx_fragments" },
4933 { "rx_jabbers" },
4934 { "rx_undersize_packets" },
4935 { "rx_oversize_packets" },
4936 { "rx_64_byte_packets" },
4937 { "rx_65_to_127_byte_packets" },
4938 { "rx_128_to_255_byte_packets" },
4939 { "rx_256_to_511_byte_packets" },
4940 { "rx_512_to_1023_byte_packets" },
4941 { "rx_1024_to_1522_byte_packets" },
4942 { "rx_1523_to_9022_byte_packets" },
4943 { "tx_64_byte_packets" },
4944 { "tx_65_to_127_byte_packets" },
4945 { "tx_128_to_255_byte_packets" },
4946 { "tx_256_to_511_byte_packets" },
4947 { "tx_512_to_1023_byte_packets" },
4948 { "tx_1024_to_1522_byte_packets" },
4949 { "tx_1523_to_9022_byte_packets" },
4950 { "rx_xon_frames" },
4951 { "rx_xoff_frames" },
4952 { "tx_xon_frames" },
4953 { "tx_xoff_frames" },
4954 { "rx_mac_ctrl_frames" },
4955 { "rx_filtered_packets" },
4956 { "rx_discards" },
4957};
4958
4959#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4960
14ab9b86 4961static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 4962 STATS_OFFSET32(stat_IfHCInOctets_hi),
4963 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4964 STATS_OFFSET32(stat_IfHCOutOctets_hi),
4965 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4966 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4967 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4968 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4969 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4970 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4971 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4972 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4973 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4974 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4975 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4976 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4977 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4978 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4979 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4980 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4981 STATS_OFFSET32(stat_EtherStatsCollisions),
4982 STATS_OFFSET32(stat_EtherStatsFragments),
4983 STATS_OFFSET32(stat_EtherStatsJabbers),
4984 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4985 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4986 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4987 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4988 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4989 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4990 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4991 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4992 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4993 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4994 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4995 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4996 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4997 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4998 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4999 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5000 STATS_OFFSET32(stat_XonPauseFramesReceived),
5001 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5002 STATS_OFFSET32(stat_OutXonSent),
5003 STATS_OFFSET32(stat_OutXoffSent),
5004 STATS_OFFSET32(stat_MacControlFramesReceived),
5005 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5006 STATS_OFFSET32(stat_IfInMBUFDiscards),
5007};
5008
5009/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5010 * skipped because of errata.
5011 */
14ab9b86 5012static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 5013 8,0,8,8,8,8,8,8,8,8,
5014 4,0,4,4,4,4,4,4,4,4,
5015 4,4,4,4,4,4,4,4,4,4,
5016 4,4,4,4,4,4,4,4,4,4,
5017 4,4,4,4,4,
5018};
5019
5b0c76ad
MC		 5020static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5021 8,0,8,8,8,8,8,8,8,8,
5022 4,4,4,4,4,4,4,4,4,4,
5023 4,4,4,4,4,4,4,4,4,4,
5024 4,4,4,4,4,4,4,4,4,4,
5025 4,4,4,4,4,
5026};
5027
b6016b76
MC		 5028#define BNX2_NUM_TESTS 6
5029
14ab9b86 5030static struct {
b6016b76
MC		 5031 char string[ETH_GSTRING_LEN];
5032} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5033 { "register_test (offline)" },
5034 { "memory_test (offline)" },
5035 { "loopback_test (offline)" },
5036 { "nvram_test (online)" },
5037 { "interrupt_test (online)" },
5038 { "link_test (online)" },
5039};
5040
5041static int
5042bnx2_self_test_count(struct net_device *dev)
5043{
5044 return BNX2_NUM_TESTS;
5045}
5046
5047static void
5048bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5049{
5050 struct bnx2 *bp = dev->priv;
5051
5052 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5053 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5054 bnx2_netif_stop(bp);
5055 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5056 bnx2_free_skbs(bp);
5057
5058 if (bnx2_test_registers(bp) != 0) {
5059 buf[0] = 1;
5060 etest->flags |= ETH_TEST_FL_FAILED;
5061 }
5062 if (bnx2_test_memory(bp) != 0) {
5063 buf[1] = 1;
5064 etest->flags |= ETH_TEST_FL_FAILED;
5065 }
5066 if (bnx2_test_loopback(bp) != 0) {
5067 buf[2] = 1;
5068 etest->flags |= ETH_TEST_FL_FAILED;
5069 }
5070
5071 if (!netif_running(bp->dev)) {
5072 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5073 }
5074 else {
5075 bnx2_init_nic(bp);
5076 bnx2_netif_start(bp);
5077 }
5078
5079 /* wait for link up */
5080 msleep_interruptible(3000);
5081 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5082 msleep_interruptible(4000);
5083 }
5084
5085 if (bnx2_test_nvram(bp) != 0) {
5086 buf[3] = 1;
5087 etest->flags |= ETH_TEST_FL_FAILED;
5088 }
5089 if (bnx2_test_intr(bp) != 0) {
5090 buf[4] = 1;
5091 etest->flags |= ETH_TEST_FL_FAILED;
5092 }
5093
5094 if (bnx2_test_link(bp) != 0) {
5095 buf[5] = 1;
5096 etest->flags |= ETH_TEST_FL_FAILED;
5097
5098 }
5099}
5100
5101static void
5102bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5103{
5104 switch (stringset) {
5105 case ETH_SS_STATS:
5106 memcpy(buf, bnx2_stats_str_arr,
5107 sizeof(bnx2_stats_str_arr));
5108 break;
5109 case ETH_SS_TEST:
5110 memcpy(buf, bnx2_tests_str_arr,
5111 sizeof(bnx2_tests_str_arr));
5112 break;
5113 }
5114}
5115
5116static int
5117bnx2_get_stats_count(struct net_device *dev)
5118{
5119 return BNX2_NUM_STATS;
5120}
5121
5122static void
5123bnx2_get_ethtool_stats(struct net_device *dev,
5124 struct ethtool_stats *stats, u64 *buf)
5125{
5126 struct bnx2 *bp = dev->priv;
5127 int i;
5128 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 5129 u8 *stats_len_arr = NULL;
b6016b76
MC		 5130
5131 if (hw_stats == NULL) {
5132 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5133 return;
5134 }
5135
5b0c76ad
MC		 5136 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5137 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5138 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5139 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 5140 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 5141 else
5142 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 5143
5144 for (i = 0; i < BNX2_NUM_STATS; i++) {
5145 if (stats_len_arr[i] == 0) {
5146 /* skip this counter */
5147 buf[i] = 0;
5148 continue;
5149 }
5150 if (stats_len_arr[i] == 4) {
5151 /* 4-byte counter */
5152 buf[i] = (u64)
5153 *(hw_stats + bnx2_stats_offset_arr[i]);
5154 continue;
5155 }
5156 /* 8-byte counter */
5157 buf[i] = (((u64) *(hw_stats +
5158 bnx2_stats_offset_arr[i])) << 32) +
5159 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5160 }
5161}
5162
5163static int
5164bnx2_phys_id(struct net_device *dev, u32 data)
5165{
5166 struct bnx2 *bp = dev->priv;
5167 int i;
5168 u32 save;
5169
5170 if (data == 0)
5171 data = 2;
5172
5173 save = REG_RD(bp, BNX2_MISC_CFG);
5174 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5175
5176 for (i = 0; i < (data * 2); i++) {
5177 if ((i % 2) == 0) {
5178 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5179 }
5180 else {
5181 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5182 BNX2_EMAC_LED_1000MB_OVERRIDE |
5183 BNX2_EMAC_LED_100MB_OVERRIDE |
5184 BNX2_EMAC_LED_10MB_OVERRIDE |
5185 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5186 BNX2_EMAC_LED_TRAFFIC);
5187 }
5188 msleep_interruptible(500);
5189 if (signal_pending(current))
5190 break;
5191 }
5192 REG_WR(bp, BNX2_EMAC_LED, 0);
5193 REG_WR(bp, BNX2_MISC_CFG, save);
5194 return 0;
5195}
5196
5197static struct ethtool_ops bnx2_ethtool_ops = {
5198 .get_settings = bnx2_get_settings,
5199 .set_settings = bnx2_set_settings,
5200 .get_drvinfo = bnx2_get_drvinfo,
5201 .get_wol = bnx2_get_wol,
5202 .set_wol = bnx2_set_wol,
5203 .nway_reset = bnx2_nway_reset,
5204 .get_link = ethtool_op_get_link,
5205 .get_eeprom_len = bnx2_get_eeprom_len,
5206 .get_eeprom = bnx2_get_eeprom,
5207 .set_eeprom = bnx2_set_eeprom,
5208 .get_coalesce = bnx2_get_coalesce,
5209 .set_coalesce = bnx2_set_coalesce,
5210 .get_ringparam = bnx2_get_ringparam,
5211 .set_ringparam = bnx2_set_ringparam,
5212 .get_pauseparam = bnx2_get_pauseparam,
5213 .set_pauseparam = bnx2_set_pauseparam,
5214 .get_rx_csum = bnx2_get_rx_csum,
5215 .set_rx_csum = bnx2_set_rx_csum,
5216 .get_tx_csum = ethtool_op_get_tx_csum,
5217 .set_tx_csum = ethtool_op_set_tx_csum,
5218 .get_sg = ethtool_op_get_sg,
5219 .set_sg = ethtool_op_set_sg,
5220#ifdef BCM_TSO
5221 .get_tso = ethtool_op_get_tso,
5222 .set_tso = ethtool_op_set_tso,
5223#endif
5224 .self_test_count = bnx2_self_test_count,
5225 .self_test = bnx2_self_test,
5226 .get_strings = bnx2_get_strings,
5227 .phys_id = bnx2_phys_id,
5228 .get_stats_count = bnx2_get_stats_count,
5229 .get_ethtool_stats = bnx2_get_ethtool_stats,
24b8e05d 5230 .get_perm_addr = ethtool_op_get_perm_addr,
b6016b76
MC		 5231};
5232
5233/* Called with rtnl_lock */
5234static int
5235bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5236{
14ab9b86 5237 struct mii_ioctl_data *data = if_mii(ifr);
b6016b76
MC		 5238 struct bnx2 *bp = dev->priv;
5239 int err;
5240
5241 switch(cmd) {
5242 case SIOCGMIIPHY:
5243 data->phy_id = bp->phy_addr;
5244
5245 /* fallthru */
5246 case SIOCGMIIREG: {
5247 u32 mii_regval;
5248
c770a65c 5249 spin_lock_bh(&bp->phy_lock);
b6016b76 5250 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 5251 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5252
5253 data->val_out = mii_regval;
5254
5255 return err;
5256 }
5257
5258 case SIOCSMIIREG:
5259 if (!capable(CAP_NET_ADMIN))
5260 return -EPERM;
5261
c770a65c 5262 spin_lock_bh(&bp->phy_lock);
b6016b76 5263 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 5264 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5265
5266 return err;
5267
5268 default:
5269 /* do nothing */
5270 break;
5271 }
5272 return -EOPNOTSUPP;
5273}
5274
5275/* Called with rtnl_lock */
5276static int
5277bnx2_change_mac_addr(struct net_device *dev, void *p)
5278{
5279 struct sockaddr *addr = p;
5280 struct bnx2 *bp = dev->priv;
5281
73eef4cd
MC		 5282 if (!is_valid_ether_addr(addr->sa_data))
5283 return -EINVAL;
5284
b6016b76
MC		 5285 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5286 if (netif_running(dev))
5287 bnx2_set_mac_addr(bp);
5288
5289 return 0;
5290}
5291
5292/* Called with rtnl_lock */
5293static int
5294bnx2_change_mtu(struct net_device *dev, int new_mtu)
5295{
5296 struct bnx2 *bp = dev->priv;
5297
5298 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5299 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5300 return -EINVAL;
5301
5302 dev->mtu = new_mtu;
5303 if (netif_running(dev)) {
5304 bnx2_netif_stop(bp);
5305
5306 bnx2_init_nic(bp);
5307
5308 bnx2_netif_start(bp);
5309 }
5310 return 0;
5311}
5312
5313#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5314static void
5315poll_bnx2(struct net_device *dev)
5316{
5317 struct bnx2 *bp = dev->priv;
5318
5319 disable_irq(bp->pdev->irq);
5320 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5321 enable_irq(bp->pdev->irq);
5322}
5323#endif
5324
5325static int __devinit
5326bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5327{
5328 struct bnx2 *bp;
5329 unsigned long mem_len;
5330 int rc;
5331 u32 reg;
5332
5333 SET_MODULE_OWNER(dev);
5334 SET_NETDEV_DEV(dev, &pdev->dev);
5335 bp = dev->priv;
5336
5337 bp->flags = 0;
5338 bp->phy_flags = 0;
5339
5340 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5341 rc = pci_enable_device(pdev);
5342 if (rc) {
5343 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5344 goto err_out;
5345 }
5346
5347 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5348 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5349 "aborting.\n");
5350 rc = -ENODEV;
5351 goto err_out_disable;
5352 }
5353
5354 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5355 if (rc) {
5356 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5357 goto err_out_disable;
5358 }
5359
5360 pci_set_master(pdev);
5361
5362 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5363 if (bp->pm_cap == 0) {
5364 printk(KERN_ERR PFX "Cannot find power management capability, "
5365 "aborting.\n");
5366 rc = -EIO;
5367 goto err_out_release;
5368 }
5369
5370 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5371 if (bp->pcix_cap == 0) {
5372 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5373 rc = -EIO;
5374 goto err_out_release;
5375 }
5376
5377 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5378 bp->flags |= USING_DAC_FLAG;
5379 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5380 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5381 "failed, aborting.\n");
5382 rc = -EIO;
5383 goto err_out_release;
5384 }
5385 }
5386 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5387 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5388 rc = -EIO;
5389 goto err_out_release;
5390 }
5391
5392 bp->dev = dev;
5393 bp->pdev = pdev;
5394
5395 spin_lock_init(&bp->phy_lock);
5396 spin_lock_init(&bp->tx_lock);
5397 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5398
5399 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5400 mem_len = MB_GET_CID_ADDR(17);
5401 dev->mem_end = dev->mem_start + mem_len;
5402 dev->irq = pdev->irq;
5403
5404 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5405
5406 if (!bp->regview) {
5407 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5408 rc = -ENOMEM;
5409 goto err_out_release;
5410 }
5411
5412 /* Configure byte swap and enable write to the reg_window registers.
5413 * Rely on CPU to do target byte swapping on big endian systems
5414 * The chip's target access swapping will not swap all accesses
5415 */
5416 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5417 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5418 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5419
829ca9a3 5420 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5421
5422 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5423
b6016b76
MC		 5424 /* Get bus information. */
5425 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5426 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5427 u32 clkreg;
5428
5429 bp->flags |= PCIX_FLAG;
5430
5431 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5432
5433 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5434 switch (clkreg) {
5435 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5436 bp->bus_speed_mhz = 133;
5437 break;
5438
5439 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5440 bp->bus_speed_mhz = 100;
5441 break;
5442
5443 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5444 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5445 bp->bus_speed_mhz = 66;
5446 break;
5447
5448 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5449 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5450 bp->bus_speed_mhz = 50;
5451 break;
5452
5453 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5454 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5455 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5456 bp->bus_speed_mhz = 33;
5457 break;
5458 }
5459 }
5460 else {
5461 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5462 bp->bus_speed_mhz = 66;
5463 else
5464 bp->bus_speed_mhz = 33;
5465 }
5466
5467 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5468 bp->flags |= PCI_32BIT_FLAG;
5469
5470 /* 5706A0 may falsely detect SERR and PERR. */
5471 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5472 reg = REG_RD(bp, PCI_COMMAND);
5473 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5474 REG_WR(bp, PCI_COMMAND, reg);
5475 }
5476 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5477 !(bp->flags & PCIX_FLAG)) {
5478
5479 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5480 "aborting.\n");
5481 goto err_out_unmap;
5482 }
5483
5484 bnx2_init_nvram(bp);
5485
5486 /* Get the permanent MAC address. First we need to make sure the
5487 * firmware is actually running.
5488 */
5489 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5490
5491 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5492 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5493 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5494 rc = -ENODEV;
5495 goto err_out_unmap;
5496 }
5497
5498 bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5499 BNX2_DEV_INFO_BC_REV);
5500
5501 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5502 bp->mac_addr[0] = (u8) (reg >> 8);
5503 bp->mac_addr[1] = (u8) reg;
5504
5505 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5506 bp->mac_addr[2] = (u8) (reg >> 24);
5507 bp->mac_addr[3] = (u8) (reg >> 16);
5508 bp->mac_addr[4] = (u8) (reg >> 8);
5509 bp->mac_addr[5] = (u8) reg;
5510
5511 bp->tx_ring_size = MAX_TX_DESC_CNT;
5512 bp->rx_ring_size = 100;
5513
5514 bp->rx_csum = 1;
5515
5516 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5517
5518 bp->tx_quick_cons_trip_int = 20;
5519 bp->tx_quick_cons_trip = 20;
5520 bp->tx_ticks_int = 80;
5521 bp->tx_ticks = 80;
5522
5523 bp->rx_quick_cons_trip_int = 6;
5524 bp->rx_quick_cons_trip = 6;
5525 bp->rx_ticks_int = 18;
5526 bp->rx_ticks = 18;
5527
5528 bp->stats_ticks = 1000000 & 0xffff00;
5529
5530 bp->timer_interval = HZ;
cd339a0e 5531 bp->current_interval = HZ;
b6016b76 5532
5b0c76ad
MC		 5533 bp->phy_addr = 1;
5534
b6016b76
MC		 5535 /* Disable WOL support if we are running on a SERDES chip. */
5536 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5537 bp->phy_flags |= PHY_SERDES_FLAG;
5538 bp->flags |= NO_WOL_FLAG;
5b0c76ad
MC		 5539 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5540 bp->phy_addr = 2;
5541 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5542 BNX2_SHARED_HW_CFG_CONFIG);
5543 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5544 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5545 }
b6016b76
MC		 5546 }
5547
5548 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5549 bp->tx_quick_cons_trip_int =
5550 bp->tx_quick_cons_trip;
5551 bp->tx_ticks_int = bp->tx_ticks;
5552 bp->rx_quick_cons_trip_int =
5553 bp->rx_quick_cons_trip;
5554 bp->rx_ticks_int = bp->rx_ticks;
5555 bp->comp_prod_trip_int = bp->comp_prod_trip;
5556 bp->com_ticks_int = bp->com_ticks;
5557 bp->cmd_ticks_int = bp->cmd_ticks;
5558 }
5559
5560 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5561 bp->req_line_speed = 0;
5562 if (bp->phy_flags & PHY_SERDES_FLAG) {
5563 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
cd339a0e
MC		 5564
5565 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5566 BNX2_PORT_HW_CFG_CONFIG);
5567 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5568 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5569 bp->autoneg = 0;
5570 bp->req_line_speed = bp->line_speed = SPEED_1000;
5571 bp->req_duplex = DUPLEX_FULL;
5572 }
b6016b76
MC		 5573 }
5574 else {
5575 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5576 }
5577
5578 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5579
cd339a0e
MC		 5580 init_timer(&bp->timer);
5581 bp->timer.expires = RUN_AT(bp->timer_interval);
5582 bp->timer.data = (unsigned long) bp;
5583 bp->timer.function = bnx2_timer;
5584
b6016b76
MC		 5585 return 0;
5586
5587err_out_unmap:
5588 if (bp->regview) {
5589 iounmap(bp->regview);
73eef4cd 5590 bp->regview = NULL;
b6016b76
MC		 5591 }
5592
5593err_out_release:
5594 pci_release_regions(pdev);
5595
5596err_out_disable:
5597 pci_disable_device(pdev);
5598 pci_set_drvdata(pdev, NULL);
5599
5600err_out:
5601 return rc;
5602}
5603
5604static int __devinit
5605bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5606{
5607 static int version_printed = 0;
5608 struct net_device *dev = NULL;
5609 struct bnx2 *bp;
5610 int rc, i;
5611
5612 if (version_printed++ == 0)
5613 printk(KERN_INFO "%s", version);
5614
5615 /* dev zeroed in init_etherdev */
5616 dev = alloc_etherdev(sizeof(*bp));
5617
5618 if (!dev)
5619 return -ENOMEM;
5620
5621 rc = bnx2_init_board(pdev, dev);
5622 if (rc < 0) {
5623 free_netdev(dev);
5624 return rc;
5625 }
5626
5627 dev->open = bnx2_open;
5628 dev->hard_start_xmit = bnx2_start_xmit;
5629 dev->stop = bnx2_close;
5630 dev->get_stats = bnx2_get_stats;
5631 dev->set_multicast_list = bnx2_set_rx_mode;
5632 dev->do_ioctl = bnx2_ioctl;
5633 dev->set_mac_address = bnx2_change_mac_addr;
5634 dev->change_mtu = bnx2_change_mtu;
5635 dev->tx_timeout = bnx2_tx_timeout;
5636 dev->watchdog_timeo = TX_TIMEOUT;
5637#ifdef BCM_VLAN
5638 dev->vlan_rx_register = bnx2_vlan_rx_register;
5639 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5640#endif
5641 dev->poll = bnx2_poll;
5642 dev->ethtool_ops = &bnx2_ethtool_ops;
5643 dev->weight = 64;
5644
5645 bp = dev->priv;
5646
5647#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5648 dev->poll_controller = poll_bnx2;
5649#endif
5650
5651 if ((rc = register_netdev(dev))) {
5652 printk(KERN_ERR PFX "Cannot register net device\n");
5653 if (bp->regview)
5654 iounmap(bp->regview);
5655 pci_release_regions(pdev);
5656 pci_disable_device(pdev);
5657 pci_set_drvdata(pdev, NULL);
5658 free_netdev(dev);
5659 return rc;
5660 }
5661
5662 pci_set_drvdata(pdev, dev);
5663
5664 memcpy(dev->dev_addr, bp->mac_addr, 6);
24b8e05d 5665 memcpy(dev->perm_addr, bp->mac_addr, 6);
b6016b76
MC		 5666 bp->name = board_info[ent->driver_data].name,
5667 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5668 "IRQ %d, ",
5669 dev->name,
5670 bp->name,
5671 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5672 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5673 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5674 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5675 bp->bus_speed_mhz,
5676 dev->base_addr,
5677 bp->pdev->irq);
5678
5679 printk("node addr ");
5680 for (i = 0; i < 6; i++)
5681 printk("%2.2x", dev->dev_addr[i]);
5682 printk("\n");
5683
5684 dev->features |= NETIF_F_SG;
5685 if (bp->flags & USING_DAC_FLAG)
5686 dev->features |= NETIF_F_HIGHDMA;
5687 dev->features |= NETIF_F_IP_CSUM;
5688#ifdef BCM_VLAN
5689 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5690#endif
5691#ifdef BCM_TSO
5692 dev->features |= NETIF_F_TSO;
5693#endif
5694
5695 netif_carrier_off(bp->dev);
5696
5697 return 0;
5698}
5699
5700static void __devexit
5701bnx2_remove_one(struct pci_dev *pdev)
5702{
5703 struct net_device *dev = pci_get_drvdata(pdev);
5704 struct bnx2 *bp = dev->priv;
5705
afdc08b9
MC		 5706 flush_scheduled_work();
5707
b6016b76
MC		 5708 unregister_netdev(dev);
5709
5710 if (bp->regview)
5711 iounmap(bp->regview);
5712
5713 free_netdev(dev);
5714 pci_release_regions(pdev);
5715 pci_disable_device(pdev);
5716 pci_set_drvdata(pdev, NULL);
5717}
5718
5719static int
829ca9a3 5720bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 5721{
5722 struct net_device *dev = pci_get_drvdata(pdev);
5723 struct bnx2 *bp = dev->priv;
5724 u32 reset_code;
5725
5726 if (!netif_running(dev))
5727 return 0;
5728
5729 bnx2_netif_stop(bp);
5730 netif_device_detach(dev);
5731 del_timer_sync(&bp->timer);
5732 if (bp->wol)
5733 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5734 else
5735 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5736 bnx2_reset_chip(bp, reset_code);
5737 bnx2_free_skbs(bp);
829ca9a3 5738 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 5739 return 0;
5740}
5741
5742static int
5743bnx2_resume(struct pci_dev *pdev)
5744{
5745 struct net_device *dev = pci_get_drvdata(pdev);
5746 struct bnx2 *bp = dev->priv;
5747
5748 if (!netif_running(dev))
5749 return 0;
5750
829ca9a3 5751 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5752 netif_device_attach(dev);
5753 bnx2_init_nic(bp);
5754 bnx2_netif_start(bp);
5755 return 0;
5756}
5757
5758static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 5759 .name = DRV_MODULE_NAME,
5760 .id_table = bnx2_pci_tbl,
5761 .probe = bnx2_init_one,
5762 .remove = __devexit_p(bnx2_remove_one),
5763 .suspend = bnx2_suspend,
5764 .resume = bnx2_resume,
b6016b76
MC		 5765};
5766
5767static int __init bnx2_init(void)
5768{
5769 return pci_module_init(&bnx2_pci_driver);
5770}
5771
5772static void __exit bnx2_cleanup(void)
5773{
5774 pci_unregister_driver(&bnx2_pci_driver);
5775}
5776
5777module_init(bnx2_init);
5778module_exit(bnx2_cleanup);
5779
5780
5781
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