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bnx2: Call pci_enable_msix() with actual number of vectors.
[mirror_ubuntu-jammy-kernel.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
bec92044 3 * Copyright (c) 2004-2010 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
17#include <linux/kernel.h>
18#include <linux/timer.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/slab.h>
22#include <linux/vmalloc.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/dma-mapping.h>
1977f032 30#include <linux/bitops.h>
f2a4f052
MC		 31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/delay.h>
34#include <asm/byteorder.h>
c86a31f4 35#include <asm/page.h>
f2a4f052
MC		 36#include <linux/time.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
f2a4f052 39#include <linux/if_vlan.h>
08013fa3 40#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
f2a4f052
MC		 41#define BCM_VLAN 1
42#endif
f2a4f052 43#include <net/ip.h>
de081fa5 44#include <net/tcp.h>
f2a4f052 45#include <net/checksum.h>
f2a4f052
MC		 46#include <linux/workqueue.h>
47#include <linux/crc32.h>
48#include <linux/prefetch.h>
29b12174 49#include <linux/cache.h>
57579f76 50#include <linux/firmware.h>
706bf240 51#include <linux/log2.h>
f2a4f052 52
4edd473f
MC		 53#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54#define BCM_CNIC 1
55#include "cnic_if.h"
56#endif
b6016b76
MC		 57#include "bnx2.h"
58#include "bnx2_fw.h"
b3448b0b 59
b6016b76 60#define DRV_MODULE_NAME "bnx2"
e5a0c1fd
MC		 61#define DRV_MODULE_VERSION "2.0.16"
62#define DRV_MODULE_RELDATE "July 2, 2010"
bec92044 63#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
078b0735 64#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
a931d294 65#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
bec92044
MC		 66#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
67#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
b6016b76
MC		 68
69#define RUN_AT(x) (jiffies + (x))
70
71/* Time in jiffies before concluding the transmitter is hung. */
72#define TX_TIMEOUT (5*HZ)
73
fefa8645 74static char version[] __devinitdata =
b6016b76
MC		 75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 78MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 79MODULE_LICENSE("GPL");
80MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 81MODULE_FIRMWARE(FW_MIPS_FILE_06);
82MODULE_FIRMWARE(FW_RV2P_FILE_06);
83MODULE_FIRMWARE(FW_MIPS_FILE_09);
84MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 85MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 86
87static int disable_msi = 0;
88
89module_param(disable_msi, int, 0);
90MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
5b0c76ad
MC		 98 BCM5708,
99 BCM5708S,
bac0dff6 100 BCM5709,
27a005b8 101 BCM5709S,
7bb0a04f 102 BCM5716,
1caacecb 103 BCM5716S,
b6016b76
MC		 104} board_t;
105
106/* indexed by board_t, above */
fefa8645 107static struct {
b6016b76
MC		 108 char *name;
109} board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 121 };
122
7bb0a04f 123static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 146 { 0, }
147};
148
0ced9d01 149static const struct flash_spec flash_table[] =
b6016b76 150{
e30372c9
MC		 151#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 153 /* Slow EEPROM */
37137709 154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
37137709
MC		 158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
b6016b76
MC		 163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
37137709 165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
37137709 171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
37137709
MC		 175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
b6016b76
MC		 236};
237
0ced9d01 238static const struct flash_spec flash_5709 = {
e30372c9
MC		 239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245};
246
b6016b76
MC		 247MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
4327ba43 249static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 250static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 251
35e9010b 252static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 253{
2f8af120 254 u32 diff;
e89bbf10 255
2f8af120 256 smp_mb();
faac9c4b
MC		 257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
35e9010b 261 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
e89bbf10
MC		 267 return (bp->tx_ring_size - diff);
268}
269
b6016b76
MC		 270static u32
271bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272{
1b8227c4
MC		 273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
b6016b76 276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
b6016b76
MC		 280}
281
282static void
283bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284{
1b8227c4 285 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 288 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 289}
290
2726d6e1
MC		 291static void
292bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293{
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295}
296
297static u32
298bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299{
300 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
301}
302
b6016b76
MC		 303static void
304bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305{
306 offset += cid_addr;
1b8227c4 307 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
59b47d8a
MC		 315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
1b8227c4 324 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 325}
326
4edd473f
MC		 327#ifdef BCM_CNIC
328static int
329bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330{
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348}
349
350static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351{
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375}
376
377static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379{
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
389 bp->cnic_data = data;
390 rcu_assign_pointer(bp->cnic_ops, ops);
391
392 cp->num_irq = 0;
393 cp->drv_state = CNIC_DRV_STATE_REGD;
394
395 bnx2_setup_cnic_irq_info(bp);
396
397 return 0;
398}
399
400static int bnx2_unregister_cnic(struct net_device *dev)
401{
402 struct bnx2 *bp = netdev_priv(dev);
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
405
c5a88950 406 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 407 cp->drv_state = 0;
408 bnapi->cnic_present = 0;
409 rcu_assign_pointer(bp->cnic_ops, NULL);
c5a88950 410 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 411 synchronize_rcu();
412 return 0;
413}
414
415struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
416{
417 struct bnx2 *bp = netdev_priv(dev);
418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
419
420 cp->drv_owner = THIS_MODULE;
421 cp->chip_id = bp->chip_id;
422 cp->pdev = bp->pdev;
423 cp->io_base = bp->regview;
424 cp->drv_ctl = bnx2_drv_ctl;
425 cp->drv_register_cnic = bnx2_register_cnic;
426 cp->drv_unregister_cnic = bnx2_unregister_cnic;
427
428 return cp;
429}
430EXPORT_SYMBOL(bnx2_cnic_probe);
431
432static void
433bnx2_cnic_stop(struct bnx2 *bp)
434{
435 struct cnic_ops *c_ops;
436 struct cnic_ctl_info info;
437
c5a88950
MC		 438 mutex_lock(&bp->cnic_lock);
439 c_ops = bp->cnic_ops;
4edd473f
MC		 440 if (c_ops) {
441 info.cmd = CNIC_CTL_STOP_CMD;
442 c_ops->cnic_ctl(bp->cnic_data, &info);
443 }
c5a88950 444 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 445}
446
447static void
448bnx2_cnic_start(struct bnx2 *bp)
449{
450 struct cnic_ops *c_ops;
451 struct cnic_ctl_info info;
452
c5a88950
MC		 453 mutex_lock(&bp->cnic_lock);
454 c_ops = bp->cnic_ops;
4edd473f
MC		 455 if (c_ops) {
456 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
457 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
458
459 bnapi->cnic_tag = bnapi->last_status_idx;
460 }
461 info.cmd = CNIC_CTL_START_CMD;
462 c_ops->cnic_ctl(bp->cnic_data, &info);
463 }
c5a88950 464 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 465}
466
467#else
468
469static void
470bnx2_cnic_stop(struct bnx2 *bp)
471{
472}
473
474static void
475bnx2_cnic_start(struct bnx2 *bp)
476{
477}
478
479#endif
480
b6016b76
MC		 481static int
482bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
483{
484 u32 val1;
485 int i, ret;
486
583c28e5 487 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 488 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
489 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
490
491 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
492 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
493
494 udelay(40);
495 }
496
497 val1 = (bp->phy_addr << 21) | (reg << 16) |
498 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
499 BNX2_EMAC_MDIO_COMM_START_BUSY;
500 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
501
502 for (i = 0; i < 50; i++) {
503 udelay(10);
504
505 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
506 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
507 udelay(5);
508
509 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
510 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
511
512 break;
513 }
514 }
515
516 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
517 *val = 0x0;
518 ret = -EBUSY;
519 }
520 else {
521 *val = val1;
522 ret = 0;
523 }
524
583c28e5 525 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 526 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
527 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
528
529 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
530 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
531
532 udelay(40);
533 }
534
535 return ret;
536}
537
538static int
539bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
540{
541 u32 val1;
542 int i, ret;
543
583c28e5 544 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 545 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
546 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
547
548 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
549 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
550
551 udelay(40);
552 }
553
554 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
555 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
556 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
557 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 558
b6016b76
MC		 559 for (i = 0; i < 50; i++) {
560 udelay(10);
561
562 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
563 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
564 udelay(5);
565 break;
566 }
567 }
568
569 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
570 ret = -EBUSY;
571 else
572 ret = 0;
573
583c28e5 574 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 575 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
576 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
577
578 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
579 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
580
581 udelay(40);
582 }
583
584 return ret;
585}
586
587static void
588bnx2_disable_int(struct bnx2 *bp)
589{
b4b36042
MC		 590 int i;
591 struct bnx2_napi *bnapi;
592
593 for (i = 0; i < bp->irq_nvecs; i++) {
594 bnapi = &bp->bnx2_napi[i];
595 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
596 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
597 }
b6016b76
MC		 598 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
599}
600
601static void
602bnx2_enable_int(struct bnx2 *bp)
603{
b4b36042
MC		 604 int i;
605 struct bnx2_napi *bnapi;
35efa7c1 606
b4b36042
MC		 607 for (i = 0; i < bp->irq_nvecs; i++) {
608 bnapi = &bp->bnx2_napi[i];
1269a8a6 609
b4b36042
MC		 610 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
611 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
612 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
613 bnapi->last_status_idx);
b6016b76 614
b4b36042
MC		 615 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
617 bnapi->last_status_idx);
618 }
bf5295bb 619 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 620}
621
622static void
623bnx2_disable_int_sync(struct bnx2 *bp)
624{
b4b36042
MC		 625 int i;
626
b6016b76 627 atomic_inc(&bp->intr_sem);
3767546c
MC		 628 if (!netif_running(bp->dev))
629 return;
630
b6016b76 631 bnx2_disable_int(bp);
b4b36042
MC		 632 for (i = 0; i < bp->irq_nvecs; i++)
633 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 634}
635
35efa7c1
MC		 636static void
637bnx2_napi_disable(struct bnx2 *bp)
638{
b4b36042
MC		 639 int i;
640
641 for (i = 0; i < bp->irq_nvecs; i++)
642 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 643}
644
645static void
646bnx2_napi_enable(struct bnx2 *bp)
647{
b4b36042
MC		 648 int i;
649
650 for (i = 0; i < bp->irq_nvecs; i++)
651 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 652}
653
b6016b76 654static void
212f9934 655bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 656{
212f9934
MC		 657 if (stop_cnic)
658 bnx2_cnic_stop(bp);
b6016b76 659 if (netif_running(bp->dev)) {
35efa7c1 660 bnx2_napi_disable(bp);
b6016b76 661 netif_tx_disable(bp->dev);
b6016b76 662 }
b7466560 663 bnx2_disable_int_sync(bp);
a0ba6760 664 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 665}
666
667static void
212f9934 668bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 669{
670 if (atomic_dec_and_test(&bp->intr_sem)) {
671 if (netif_running(bp->dev)) {
706bf240 672 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 673 spin_lock_bh(&bp->phy_lock);
674 if (bp->link_up)
675 netif_carrier_on(bp->dev);
676 spin_unlock_bh(&bp->phy_lock);
35efa7c1 677 bnx2_napi_enable(bp);
b6016b76 678 bnx2_enable_int(bp);
212f9934
MC		 679 if (start_cnic)
680 bnx2_cnic_start(bp);
b6016b76
MC		 681 }
682 }
683}
684
35e9010b
MC		 685static void
686bnx2_free_tx_mem(struct bnx2 *bp)
687{
688 int i;
689
690 for (i = 0; i < bp->num_tx_rings; i++) {
691 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
692 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
693
694 if (txr->tx_desc_ring) {
36227e88
SG		 695 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
696 txr->tx_desc_ring,
697 txr->tx_desc_mapping);
35e9010b
MC		 698 txr->tx_desc_ring = NULL;
699 }
700 kfree(txr->tx_buf_ring);
701 txr->tx_buf_ring = NULL;
702 }
703}
704
bb4f98ab
MC		 705static void
706bnx2_free_rx_mem(struct bnx2 *bp)
707{
708 int i;
709
710 for (i = 0; i < bp->num_rx_rings; i++) {
711 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
712 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
713 int j;
714
715 for (j = 0; j < bp->rx_max_ring; j++) {
716 if (rxr->rx_desc_ring[j])
36227e88
SG		 717 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
718 rxr->rx_desc_ring[j],
719 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 720 rxr->rx_desc_ring[j] = NULL;
721 }
25b0b999 722 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 723 rxr->rx_buf_ring = NULL;
724
725 for (j = 0; j < bp->rx_max_pg_ring; j++) {
726 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 727 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
728 rxr->rx_pg_desc_ring[j],
729 rxr->rx_pg_desc_mapping[j]);
3298a738 730 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 731 }
25b0b999 732 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 733 rxr->rx_pg_ring = NULL;
734 }
735}
736
35e9010b
MC		 737static int
738bnx2_alloc_tx_mem(struct bnx2 *bp)
739{
740 int i;
741
742 for (i = 0; i < bp->num_tx_rings; i++) {
743 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
744 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
745
746 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
747 if (txr->tx_buf_ring == NULL)
748 return -ENOMEM;
749
750 txr->tx_desc_ring =
36227e88
SG		 751 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
752 &txr->tx_desc_mapping, GFP_KERNEL);
35e9010b
MC		 753 if (txr->tx_desc_ring == NULL)
754 return -ENOMEM;
755 }
756 return 0;
757}
758
bb4f98ab
MC		 759static int
760bnx2_alloc_rx_mem(struct bnx2 *bp)
761{
762 int i;
763
764 for (i = 0; i < bp->num_rx_rings; i++) {
765 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
766 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
767 int j;
768
769 rxr->rx_buf_ring =
770 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
771 if (rxr->rx_buf_ring == NULL)
772 return -ENOMEM;
773
774 memset(rxr->rx_buf_ring, 0,
775 SW_RXBD_RING_SIZE * bp->rx_max_ring);
776
777 for (j = 0; j < bp->rx_max_ring; j++) {
778 rxr->rx_desc_ring[j] =
36227e88
SG		 779 dma_alloc_coherent(&bp->pdev->dev,
780 RXBD_RING_SIZE,
781 &rxr->rx_desc_mapping[j],
782 GFP_KERNEL);
bb4f98ab
MC		 783 if (rxr->rx_desc_ring[j] == NULL)
784 return -ENOMEM;
785
786 }
787
788 if (bp->rx_pg_ring_size) {
789 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
790 bp->rx_max_pg_ring);
791 if (rxr->rx_pg_ring == NULL)
792 return -ENOMEM;
793
794 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
795 bp->rx_max_pg_ring);
796 }
797
798 for (j = 0; j < bp->rx_max_pg_ring; j++) {
799 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 800 dma_alloc_coherent(&bp->pdev->dev,
801 RXBD_RING_SIZE,
802 &rxr->rx_pg_desc_mapping[j],
803 GFP_KERNEL);
bb4f98ab
MC		 804 if (rxr->rx_pg_desc_ring[j] == NULL)
805 return -ENOMEM;
806
807 }
808 }
809 return 0;
810}
811
b6016b76
MC		 812static void
813bnx2_free_mem(struct bnx2 *bp)
814{
13daffa2 815 int i;
43e80b89 816 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 817
35e9010b 818 bnx2_free_tx_mem(bp);
bb4f98ab 819 bnx2_free_rx_mem(bp);
35e9010b 820
59b47d8a
MC		 821 for (i = 0; i < bp->ctx_pages; i++) {
822 if (bp->ctx_blk[i]) {
36227e88
SG		 823 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
824 bp->ctx_blk[i],
825 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 826 bp->ctx_blk[i] = NULL;
827 }
828 }
43e80b89 829 if (bnapi->status_blk.msi) {
36227e88
SG		 830 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
831 bnapi->status_blk.msi,
832 bp->status_blk_mapping);
43e80b89 833 bnapi->status_blk.msi = NULL;
0f31f994 834 bp->stats_blk = NULL;
b6016b76 835 }
b6016b76
MC		 836}
837
838static int
839bnx2_alloc_mem(struct bnx2 *bp)
840{
35e9010b 841 int i, status_blk_size, err;
43e80b89
MC		 842 struct bnx2_napi *bnapi;
843 void *status_blk;
b6016b76 844
0f31f994
MC		 845 /* Combine status and statistics blocks into one allocation. */
846 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 847 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 848 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
849 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 850 bp->status_stats_size = status_blk_size +
851 sizeof(struct statistics_block);
852
36227e88
SG		 853 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
854 &bp->status_blk_mapping, GFP_KERNEL);
43e80b89 855 if (status_blk == NULL)
b6016b76
MC		 856 goto alloc_mem_err;
857
43e80b89 858 memset(status_blk, 0, bp->status_stats_size);
b6016b76 859
43e80b89
MC		 860 bnapi = &bp->bnx2_napi[0];
861 bnapi->status_blk.msi = status_blk;
862 bnapi->hw_tx_cons_ptr =
863 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
864 bnapi->hw_rx_cons_ptr =
865 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 866 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 867 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 868 struct status_block_msix *sblk;
869
870 bnapi = &bp->bnx2_napi[i];
b4b36042 871
43e80b89
MC		 872 sblk = (void *) (status_blk +
873 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
874 bnapi->status_blk.msix = sblk;
875 bnapi->hw_tx_cons_ptr =
876 &sblk->status_tx_quick_consumer_index;
877 bnapi->hw_rx_cons_ptr =
878 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 879 bnapi->int_num = i << 24;
880 }
881 }
35efa7c1 882
43e80b89 883 bp->stats_blk = status_blk + status_blk_size;
b6016b76 884
0f31f994 885 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 886
59b47d8a
MC		 887 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
888 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
889 if (bp->ctx_pages == 0)
890 bp->ctx_pages = 1;
891 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 892 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
59b47d8a 893 BCM_PAGE_SIZE,
36227e88
SG		 894 &bp->ctx_blk_mapping[i],
895 GFP_KERNEL);
59b47d8a
MC		 896 if (bp->ctx_blk[i] == NULL)
897 goto alloc_mem_err;
898 }
899 }
35e9010b 900
bb4f98ab
MC		 901 err = bnx2_alloc_rx_mem(bp);
902 if (err)
903 goto alloc_mem_err;
904
35e9010b
MC		 905 err = bnx2_alloc_tx_mem(bp);
906 if (err)
907 goto alloc_mem_err;
908
b6016b76
MC		 909 return 0;
910
911alloc_mem_err:
912 bnx2_free_mem(bp);
913 return -ENOMEM;
914}
915
e3648b3d
MC		 916static void
917bnx2_report_fw_link(struct bnx2 *bp)
918{
919 u32 fw_link_status = 0;
920
583c28e5 921 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 922 return;
923
e3648b3d
MC		 924 if (bp->link_up) {
925 u32 bmsr;
926
927 switch (bp->line_speed) {
928 case SPEED_10:
929 if (bp->duplex == DUPLEX_HALF)
930 fw_link_status = BNX2_LINK_STATUS_10HALF;
931 else
932 fw_link_status = BNX2_LINK_STATUS_10FULL;
933 break;
934 case SPEED_100:
935 if (bp->duplex == DUPLEX_HALF)
936 fw_link_status = BNX2_LINK_STATUS_100HALF;
937 else
938 fw_link_status = BNX2_LINK_STATUS_100FULL;
939 break;
940 case SPEED_1000:
941 if (bp->duplex == DUPLEX_HALF)
942 fw_link_status = BNX2_LINK_STATUS_1000HALF;
943 else
944 fw_link_status = BNX2_LINK_STATUS_1000FULL;
945 break;
946 case SPEED_2500:
947 if (bp->duplex == DUPLEX_HALF)
948 fw_link_status = BNX2_LINK_STATUS_2500HALF;
949 else
950 fw_link_status = BNX2_LINK_STATUS_2500FULL;
951 break;
952 }
953
954 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
955
956 if (bp->autoneg) {
957 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
958
ca58c3af
MC		 959 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
960 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 961
962 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 963 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 964 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
965 else
966 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
967 }
968 }
969 else
970 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
971
2726d6e1 972 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 973}
974
9b1084b8
MC		 975static char *
976bnx2_xceiver_str(struct bnx2 *bp)
977{
978 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 979 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 980 "Copper"));
981}
982
b6016b76
MC		 983static void
984bnx2_report_link(struct bnx2 *bp)
985{
986 if (bp->link_up) {
987 netif_carrier_on(bp->dev);
3a9c6a49
JP		 988 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
989 bnx2_xceiver_str(bp),
990 bp->line_speed,
991 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 992
993 if (bp->flow_ctrl) {
994 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 995 pr_cont(", receive ");
b6016b76 996 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 997 pr_cont("& transmit ");
b6016b76
MC		 998 }
999 else {
3a9c6a49 1000 pr_cont(", transmit ");
b6016b76 1001 }
3a9c6a49 1002 pr_cont("flow control ON");
b6016b76 1003 }
3a9c6a49
JP		 1004 pr_cont("\n");
1005 } else {
b6016b76 1006 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1007 netdev_err(bp->dev, "NIC %s Link is Down\n",
1008 bnx2_xceiver_str(bp));
b6016b76 1009 }
e3648b3d
MC		 1010
1011 bnx2_report_fw_link(bp);
b6016b76
MC		 1012}
1013
1014static void
1015bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1016{
1017 u32 local_adv, remote_adv;
1018
1019 bp->flow_ctrl = 0;
6aa20a22 1020 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1021 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1022
1023 if (bp->duplex == DUPLEX_FULL) {
1024 bp->flow_ctrl = bp->req_flow_ctrl;
1025 }
1026 return;
1027 }
1028
1029 if (bp->duplex != DUPLEX_FULL) {
1030 return;
1031 }
1032
583c28e5 1033 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 1034 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1035 u32 val;
1036
1037 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1038 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1039 bp->flow_ctrl |= FLOW_CTRL_TX;
1040 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1041 bp->flow_ctrl |= FLOW_CTRL_RX;
1042 return;
1043 }
1044
ca58c3af
MC		 1045 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1046 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1047
583c28e5 1048 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1049 u32 new_local_adv = 0;
1050 u32 new_remote_adv = 0;
1051
1052 if (local_adv & ADVERTISE_1000XPAUSE)
1053 new_local_adv |= ADVERTISE_PAUSE_CAP;
1054 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1055 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1056 if (remote_adv & ADVERTISE_1000XPAUSE)
1057 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1058 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1059 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1060
1061 local_adv = new_local_adv;
1062 remote_adv = new_remote_adv;
1063 }
1064
1065 /* See Table 28B-3 of 802.3ab-1999 spec. */
1066 if (local_adv & ADVERTISE_PAUSE_CAP) {
1067 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1068 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1069 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1070 }
1071 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1072 bp->flow_ctrl = FLOW_CTRL_RX;
1073 }
1074 }
1075 else {
1076 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1077 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1078 }
1079 }
1080 }
1081 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1082 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1083 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1084
1085 bp->flow_ctrl = FLOW_CTRL_TX;
1086 }
1087 }
1088}
1089
27a005b8
MC		 1090static int
1091bnx2_5709s_linkup(struct bnx2 *bp)
1092{
1093 u32 val, speed;
1094
1095 bp->link_up = 1;
1096
1097 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1098 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1099 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1100
1101 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1102 bp->line_speed = bp->req_line_speed;
1103 bp->duplex = bp->req_duplex;
1104 return 0;
1105 }
1106 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1107 switch (speed) {
1108 case MII_BNX2_GP_TOP_AN_SPEED_10:
1109 bp->line_speed = SPEED_10;
1110 break;
1111 case MII_BNX2_GP_TOP_AN_SPEED_100:
1112 bp->line_speed = SPEED_100;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1115 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1116 bp->line_speed = SPEED_1000;
1117 break;
1118 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1119 bp->line_speed = SPEED_2500;
1120 break;
1121 }
1122 if (val & MII_BNX2_GP_TOP_AN_FD)
1123 bp->duplex = DUPLEX_FULL;
1124 else
1125 bp->duplex = DUPLEX_HALF;
1126 return 0;
1127}
1128
b6016b76 1129static int
5b0c76ad
MC		 1130bnx2_5708s_linkup(struct bnx2 *bp)
1131{
1132 u32 val;
1133
1134 bp->link_up = 1;
1135 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1136 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1137 case BCM5708S_1000X_STAT1_SPEED_10:
1138 bp->line_speed = SPEED_10;
1139 break;
1140 case BCM5708S_1000X_STAT1_SPEED_100:
1141 bp->line_speed = SPEED_100;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_1G:
1144 bp->line_speed = SPEED_1000;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_2G5:
1147 bp->line_speed = SPEED_2500;
1148 break;
1149 }
1150 if (val & BCM5708S_1000X_STAT1_FD)
1151 bp->duplex = DUPLEX_FULL;
1152 else
1153 bp->duplex = DUPLEX_HALF;
1154
1155 return 0;
1156}
1157
1158static int
1159bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1160{
1161 u32 bmcr, local_adv, remote_adv, common;
1162
1163 bp->link_up = 1;
1164 bp->line_speed = SPEED_1000;
1165
ca58c3af 1166 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1167 if (bmcr & BMCR_FULLDPLX) {
1168 bp->duplex = DUPLEX_FULL;
1169 }
1170 else {
1171 bp->duplex = DUPLEX_HALF;
1172 }
1173
1174 if (!(bmcr & BMCR_ANENABLE)) {
1175 return 0;
1176 }
1177
ca58c3af
MC		 1178 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1179 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1180
1181 common = local_adv & remote_adv;
1182 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1183
1184 if (common & ADVERTISE_1000XFULL) {
1185 bp->duplex = DUPLEX_FULL;
1186 }
1187 else {
1188 bp->duplex = DUPLEX_HALF;
1189 }
1190 }
1191
1192 return 0;
1193}
1194
1195static int
1196bnx2_copper_linkup(struct bnx2 *bp)
1197{
1198 u32 bmcr;
1199
ca58c3af 1200 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1201 if (bmcr & BMCR_ANENABLE) {
1202 u32 local_adv, remote_adv, common;
1203
1204 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1205 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1206
1207 common = local_adv & (remote_adv >> 2);
1208 if (common & ADVERTISE_1000FULL) {
1209 bp->line_speed = SPEED_1000;
1210 bp->duplex = DUPLEX_FULL;
1211 }
1212 else if (common & ADVERTISE_1000HALF) {
1213 bp->line_speed = SPEED_1000;
1214 bp->duplex = DUPLEX_HALF;
1215 }
1216 else {
ca58c3af
MC		 1217 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1218 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1219
1220 common = local_adv & remote_adv;
1221 if (common & ADVERTISE_100FULL) {
1222 bp->line_speed = SPEED_100;
1223 bp->duplex = DUPLEX_FULL;
1224 }
1225 else if (common & ADVERTISE_100HALF) {
1226 bp->line_speed = SPEED_100;
1227 bp->duplex = DUPLEX_HALF;
1228 }
1229 else if (common & ADVERTISE_10FULL) {
1230 bp->line_speed = SPEED_10;
1231 bp->duplex = DUPLEX_FULL;
1232 }
1233 else if (common & ADVERTISE_10HALF) {
1234 bp->line_speed = SPEED_10;
1235 bp->duplex = DUPLEX_HALF;
1236 }
1237 else {
1238 bp->line_speed = 0;
1239 bp->link_up = 0;
1240 }
1241 }
1242 }
1243 else {
1244 if (bmcr & BMCR_SPEED100) {
1245 bp->line_speed = SPEED_100;
1246 }
1247 else {
1248 bp->line_speed = SPEED_10;
1249 }
1250 if (bmcr & BMCR_FULLDPLX) {
1251 bp->duplex = DUPLEX_FULL;
1252 }
1253 else {
1254 bp->duplex = DUPLEX_HALF;
1255 }
1256 }
1257
1258 return 0;
1259}
1260
83e3fc89 1261static void
bb4f98ab 1262bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1263{
bb4f98ab 1264 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1265
1266 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1267 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1268 val |= 0x02 << 8;
1269
1270 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1271 u32 lo_water, hi_water;
1272
1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1275 else
1276 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1277 if (lo_water >= bp->rx_ring_size)
1278 lo_water = 0;
1279
5726026b 1280 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
83e3fc89
MC		 1281
1282 if (hi_water <= lo_water)
1283 lo_water = 0;
1284
1285 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1286 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1287
1288 if (hi_water > 0xf)
1289 hi_water = 0xf;
1290 else if (hi_water == 0)
1291 lo_water = 0;
1292 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1293 }
1294 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1295}
1296
bb4f98ab
MC		 1297static void
1298bnx2_init_all_rx_contexts(struct bnx2 *bp)
1299{
1300 int i;
1301 u32 cid;
1302
1303 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1304 if (i == 1)
1305 cid = RX_RSS_CID;
1306 bnx2_init_rx_context(bp, cid);
1307 }
1308}
1309
344478db 1310static void
b6016b76
MC		 1311bnx2_set_mac_link(struct bnx2 *bp)
1312{
1313 u32 val;
1314
1315 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1316 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1317 (bp->duplex == DUPLEX_HALF)) {
1318 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1319 }
1320
1321 /* Configure the EMAC mode register. */
1322 val = REG_RD(bp, BNX2_EMAC_MODE);
1323
1324 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1325 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1326 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1327
1328 if (bp->link_up) {
5b0c76ad
MC		 1329 switch (bp->line_speed) {
1330 case SPEED_10:
59b47d8a
MC		 1331 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1332 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1333 break;
1334 }
1335 /* fall through */
1336 case SPEED_100:
1337 val |= BNX2_EMAC_MODE_PORT_MII;
1338 break;
1339 case SPEED_2500:
59b47d8a 1340 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1341 /* fall through */
1342 case SPEED_1000:
1343 val |= BNX2_EMAC_MODE_PORT_GMII;
1344 break;
1345 }
b6016b76
MC		 1346 }
1347 else {
1348 val |= BNX2_EMAC_MODE_PORT_GMII;
1349 }
1350
1351 /* Set the MAC to operate in the appropriate duplex mode. */
1352 if (bp->duplex == DUPLEX_HALF)
1353 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1354 REG_WR(bp, BNX2_EMAC_MODE, val);
1355
1356 /* Enable/disable rx PAUSE. */
1357 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1358
1359 if (bp->flow_ctrl & FLOW_CTRL_RX)
1360 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1361 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1362
1363 /* Enable/disable tx PAUSE. */
1364 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1365 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1366
1367 if (bp->flow_ctrl & FLOW_CTRL_TX)
1368 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1369 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1370
1371 /* Acknowledge the interrupt. */
1372 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1373
83e3fc89 1374 if (CHIP_NUM(bp) == CHIP_NUM_5709)
bb4f98ab 1375 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1376}
1377
27a005b8
MC		 1378static void
1379bnx2_enable_bmsr1(struct bnx2 *bp)
1380{
583c28e5 1381 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1382 (CHIP_NUM(bp) == CHIP_NUM_5709))
1383 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1384 MII_BNX2_BLK_ADDR_GP_STATUS);
1385}
1386
1387static void
1388bnx2_disable_bmsr1(struct bnx2 *bp)
1389{
583c28e5 1390 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1391 (CHIP_NUM(bp) == CHIP_NUM_5709))
1392 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1393 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1394}
1395
605a9e20
MC		 1396static int
1397bnx2_test_and_enable_2g5(struct bnx2 *bp)
1398{
1399 u32 up1;
1400 int ret = 1;
1401
583c28e5 1402 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1403 return 0;
1404
1405 if (bp->autoneg & AUTONEG_SPEED)
1406 bp->advertising |= ADVERTISED_2500baseX_Full;
1407
27a005b8
MC		 1408 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1409 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1410
605a9e20
MC		 1411 bnx2_read_phy(bp, bp->mii_up1, &up1);
1412 if (!(up1 & BCM5708S_UP1_2G5)) {
1413 up1 |= BCM5708S_UP1_2G5;
1414 bnx2_write_phy(bp, bp->mii_up1, up1);
1415 ret = 0;
1416 }
1417
27a005b8
MC		 1418 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1419 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1420 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1421
605a9e20
MC		 1422 return ret;
1423}
1424
1425static int
1426bnx2_test_and_disable_2g5(struct bnx2 *bp)
1427{
1428 u32 up1;
1429 int ret = 0;
1430
583c28e5 1431 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1432 return 0;
1433
27a005b8
MC		 1434 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1435 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1436
605a9e20
MC		 1437 bnx2_read_phy(bp, bp->mii_up1, &up1);
1438 if (up1 & BCM5708S_UP1_2G5) {
1439 up1 &= ~BCM5708S_UP1_2G5;
1440 bnx2_write_phy(bp, bp->mii_up1, up1);
1441 ret = 1;
1442 }
1443
27a005b8
MC		 1444 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1445 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1446 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1447
605a9e20
MC		 1448 return ret;
1449}
1450
1451static void
1452bnx2_enable_forced_2g5(struct bnx2 *bp)
1453{
cbd6890c
MC		 1454 u32 uninitialized_var(bmcr);
1455 int err;
605a9e20 1456
583c28e5 1457 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1458 return;
1459
27a005b8
MC		 1460 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1461 u32 val;
1462
1463 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1464 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1465 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1466 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1467 val |= MII_BNX2_SD_MISC1_FORCE |
1468 MII_BNX2_SD_MISC1_FORCE_2_5G;
1469 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1470 }
27a005b8
MC		 1471
1472 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1473 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1474 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1475
1476 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1477 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1478 if (!err)
1479 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1480 } else {
1481 return;
605a9e20
MC		 1482 }
1483
cbd6890c
MC		 1484 if (err)
1485 return;
1486
605a9e20
MC		 1487 if (bp->autoneg & AUTONEG_SPEED) {
1488 bmcr &= ~BMCR_ANENABLE;
1489 if (bp->req_duplex == DUPLEX_FULL)
1490 bmcr |= BMCR_FULLDPLX;
1491 }
1492 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1493}
1494
1495static void
1496bnx2_disable_forced_2g5(struct bnx2 *bp)
1497{
cbd6890c
MC		 1498 u32 uninitialized_var(bmcr);
1499 int err;
605a9e20 1500
583c28e5 1501 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1502 return;
1503
27a005b8
MC		 1504 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1505 u32 val;
1506
1507 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1508 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1509 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1510 val &= ~MII_BNX2_SD_MISC1_FORCE;
1511 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1512 }
27a005b8
MC		 1513
1514 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1515 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1516 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1517
1518 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1519 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1520 if (!err)
1521 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1522 } else {
1523 return;
605a9e20
MC		 1524 }
1525
cbd6890c
MC		 1526 if (err)
1527 return;
1528
605a9e20
MC		 1529 if (bp->autoneg & AUTONEG_SPEED)
1530 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1531 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1532}
1533
b2fadeae
MC		 1534static void
1535bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1536{
1537 u32 val;
1538
1539 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1540 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1541 if (start)
1542 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1543 else
1544 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1545}
1546
b6016b76
MC		 1547static int
1548bnx2_set_link(struct bnx2 *bp)
1549{
1550 u32 bmsr;
1551 u8 link_up;
1552
80be4434 1553 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1554 bp->link_up = 1;
1555 return 0;
1556 }
1557
583c28e5 1558 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1559 return 0;
1560
b6016b76
MC		 1561 link_up = bp->link_up;
1562
27a005b8
MC		 1563 bnx2_enable_bmsr1(bp);
1564 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1565 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1566 bnx2_disable_bmsr1(bp);
b6016b76 1567
583c28e5 1568 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1569 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1570 u32 val, an_dbg;
b6016b76 1571
583c28e5 1572 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1573 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1574 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1575 }
b6016b76 1576 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1577
1578 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1579 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1580 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1581
1582 if ((val & BNX2_EMAC_STATUS_LINK) &&
1583 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1584 bmsr |= BMSR_LSTATUS;
1585 else
1586 bmsr &= ~BMSR_LSTATUS;
1587 }
1588
1589 if (bmsr & BMSR_LSTATUS) {
1590 bp->link_up = 1;
1591
583c28e5 1592 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1593 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1594 bnx2_5706s_linkup(bp);
1595 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1596 bnx2_5708s_linkup(bp);
27a005b8
MC		 1597 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1598 bnx2_5709s_linkup(bp);
b6016b76
MC		 1599 }
1600 else {
1601 bnx2_copper_linkup(bp);
1602 }
1603 bnx2_resolve_flow_ctrl(bp);
1604 }
1605 else {
583c28e5 1606 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1607 (bp->autoneg & AUTONEG_SPEED))
1608 bnx2_disable_forced_2g5(bp);
b6016b76 1609
583c28e5 1610 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1611 u32 bmcr;
1612
1613 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1614 bmcr |= BMCR_ANENABLE;
1615 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1616
583c28e5 1617 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1618 }
b6016b76
MC		 1619 bp->link_up = 0;
1620 }
1621
1622 if (bp->link_up != link_up) {
1623 bnx2_report_link(bp);
1624 }
1625
1626 bnx2_set_mac_link(bp);
1627
1628 return 0;
1629}
1630
1631static int
1632bnx2_reset_phy(struct bnx2 *bp)
1633{
1634 int i;
1635 u32 reg;
1636
ca58c3af 1637 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1638
1639#define PHY_RESET_MAX_WAIT 100
1640 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1641 udelay(10);
1642
ca58c3af 1643 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1644 if (!(reg & BMCR_RESET)) {
1645 udelay(20);
1646 break;
1647 }
1648 }
1649 if (i == PHY_RESET_MAX_WAIT) {
1650 return -EBUSY;
1651 }
1652 return 0;
1653}
1654
1655static u32
1656bnx2_phy_get_pause_adv(struct bnx2 *bp)
1657{
1658 u32 adv = 0;
1659
1660 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1661 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1662
583c28e5 1663 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1664 adv = ADVERTISE_1000XPAUSE;
1665 }
1666 else {
1667 adv = ADVERTISE_PAUSE_CAP;
1668 }
1669 }
1670 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1671 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1672 adv = ADVERTISE_1000XPSE_ASYM;
1673 }
1674 else {
1675 adv = ADVERTISE_PAUSE_ASYM;
1676 }
1677 }
1678 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1679 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1680 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1681 }
1682 else {
1683 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1684 }
1685 }
1686 return adv;
1687}
1688
a2f13890 1689static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1690
b6016b76 1691static int
0d8a6571 1692bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1693__releases(&bp->phy_lock)
1694__acquires(&bp->phy_lock)
0d8a6571
MC		 1695{
1696 u32 speed_arg = 0, pause_adv;
1697
1698 pause_adv = bnx2_phy_get_pause_adv(bp);
1699
1700 if (bp->autoneg & AUTONEG_SPEED) {
1701 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1702 if (bp->advertising & ADVERTISED_10baseT_Half)
1703 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1704 if (bp->advertising & ADVERTISED_10baseT_Full)
1705 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1706 if (bp->advertising & ADVERTISED_100baseT_Half)
1707 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1708 if (bp->advertising & ADVERTISED_100baseT_Full)
1709 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1710 if (bp->advertising & ADVERTISED_1000baseT_Full)
1711 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1712 if (bp->advertising & ADVERTISED_2500baseX_Full)
1713 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1714 } else {
1715 if (bp->req_line_speed == SPEED_2500)
1716 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1717 else if (bp->req_line_speed == SPEED_1000)
1718 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1719 else if (bp->req_line_speed == SPEED_100) {
1720 if (bp->req_duplex == DUPLEX_FULL)
1721 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1722 else
1723 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1724 } else if (bp->req_line_speed == SPEED_10) {
1725 if (bp->req_duplex == DUPLEX_FULL)
1726 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1727 else
1728 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1729 }
1730 }
1731
1732 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1733 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1734 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1735 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1736
1737 if (port == PORT_TP)
1738 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1739 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1740
2726d6e1 1741 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1742
1743 spin_unlock_bh(&bp->phy_lock);
a2f13890 1744 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1745 spin_lock_bh(&bp->phy_lock);
1746
1747 return 0;
1748}
1749
1750static int
1751bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1752__releases(&bp->phy_lock)
1753__acquires(&bp->phy_lock)
b6016b76 1754{
605a9e20 1755 u32 adv, bmcr;
b6016b76
MC		 1756 u32 new_adv = 0;
1757
583c28e5 1758 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1759 return (bnx2_setup_remote_phy(bp, port));
1760
b6016b76
MC		 1761 if (!(bp->autoneg & AUTONEG_SPEED)) {
1762 u32 new_bmcr;
5b0c76ad
MC		 1763 int force_link_down = 0;
1764
605a9e20
MC		 1765 if (bp->req_line_speed == SPEED_2500) {
1766 if (!bnx2_test_and_enable_2g5(bp))
1767 force_link_down = 1;
1768 } else if (bp->req_line_speed == SPEED_1000) {
1769 if (bnx2_test_and_disable_2g5(bp))
1770 force_link_down = 1;
1771 }
ca58c3af 1772 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1773 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1774
ca58c3af 1775 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1776 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1777 new_bmcr |= BMCR_SPEED1000;
605a9e20 1778
27a005b8
MC		 1779 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1780 if (bp->req_line_speed == SPEED_2500)
1781 bnx2_enable_forced_2g5(bp);
1782 else if (bp->req_line_speed == SPEED_1000) {
1783 bnx2_disable_forced_2g5(bp);
1784 new_bmcr &= ~0x2000;
1785 }
1786
1787 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1788 if (bp->req_line_speed == SPEED_2500)
1789 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1790 else
1791 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1792 }
1793
b6016b76 1794 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1795 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1796 new_bmcr |= BMCR_FULLDPLX;
1797 }
1798 else {
5b0c76ad 1799 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1800 new_bmcr &= ~BMCR_FULLDPLX;
1801 }
5b0c76ad 1802 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1803 /* Force a link down visible on the other side */
1804 if (bp->link_up) {
ca58c3af 1805 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1806 ~(ADVERTISE_1000XFULL |
1807 ADVERTISE_1000XHALF));
ca58c3af 1808 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1809 BMCR_ANRESTART | BMCR_ANENABLE);
1810
1811 bp->link_up = 0;
1812 netif_carrier_off(bp->dev);
ca58c3af 1813 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1814 bnx2_report_link(bp);
b6016b76 1815 }
ca58c3af
MC		 1816 bnx2_write_phy(bp, bp->mii_adv, adv);
1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1818 } else {
1819 bnx2_resolve_flow_ctrl(bp);
1820 bnx2_set_mac_link(bp);
b6016b76
MC		 1821 }
1822 return 0;
1823 }
1824
605a9e20 1825 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1826
b6016b76
MC		 1827 if (bp->advertising & ADVERTISED_1000baseT_Full)
1828 new_adv |= ADVERTISE_1000XFULL;
1829
1830 new_adv |= bnx2_phy_get_pause_adv(bp);
1831
ca58c3af
MC		 1832 bnx2_read_phy(bp, bp->mii_adv, &adv);
1833 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1834
1835 bp->serdes_an_pending = 0;
1836 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1837 /* Force a link down visible on the other side */
1838 if (bp->link_up) {
ca58c3af 1839 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1840 spin_unlock_bh(&bp->phy_lock);
1841 msleep(20);
1842 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1843 }
1844
ca58c3af
MC		 1845 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1846 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1847 BMCR_ANENABLE);
f8dd064e
MC		 1848 /* Speed up link-up time when the link partner
1849 * does not autonegotiate which is very common
1850 * in blade servers. Some blade servers use
1851 * IPMI for kerboard input and it's important
1852 * to minimize link disruptions. Autoneg. involves
1853 * exchanging base pages plus 3 next pages and
1854 * normally completes in about 120 msec.
1855 */
40105c0b 1856 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1857 bp->serdes_an_pending = 1;
1858 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1859 } else {
1860 bnx2_resolve_flow_ctrl(bp);
1861 bnx2_set_mac_link(bp);
b6016b76
MC		 1862 }
1863
1864 return 0;
1865}
1866
1867#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1868 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1869 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1870 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1871
1872#define ETHTOOL_ALL_COPPER_SPEED \
1873 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1874 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1875 ADVERTISED_1000baseT_Full)
1876
1877#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1878 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1879
b6016b76
MC		 1880#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1881
0d8a6571
MC		 1882static void
1883bnx2_set_default_remote_link(struct bnx2 *bp)
1884{
1885 u32 link;
1886
1887 if (bp->phy_port == PORT_TP)
2726d6e1 1888 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1889 else
2726d6e1 1890 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1891
1892 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1893 bp->req_line_speed = 0;
1894 bp->autoneg |= AUTONEG_SPEED;
1895 bp->advertising = ADVERTISED_Autoneg;
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1897 bp->advertising |= ADVERTISED_10baseT_Half;
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1899 bp->advertising |= ADVERTISED_10baseT_Full;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->advertising |= ADVERTISED_100baseT_Half;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1903 bp->advertising |= ADVERTISED_100baseT_Full;
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1905 bp->advertising |= ADVERTISED_1000baseT_Full;
1906 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1907 bp->advertising |= ADVERTISED_2500baseX_Full;
1908 } else {
1909 bp->autoneg = 0;
1910 bp->advertising = 0;
1911 bp->req_duplex = DUPLEX_FULL;
1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1913 bp->req_line_speed = SPEED_10;
1914 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1915 bp->req_duplex = DUPLEX_HALF;
1916 }
1917 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1918 bp->req_line_speed = SPEED_100;
1919 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1920 bp->req_duplex = DUPLEX_HALF;
1921 }
1922 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1923 bp->req_line_speed = SPEED_1000;
1924 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1925 bp->req_line_speed = SPEED_2500;
1926 }
1927}
1928
deaf391b
MC		 1929static void
1930bnx2_set_default_link(struct bnx2 *bp)
1931{
ab59859d
HH		 1932 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1933 bnx2_set_default_remote_link(bp);
1934 return;
1935 }
0d8a6571 1936
deaf391b
MC		 1937 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1938 bp->req_line_speed = 0;
583c28e5 1939 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1940 u32 reg;
1941
1942 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1943
2726d6e1 1944 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1945 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1946 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1947 bp->autoneg = 0;
1948 bp->req_line_speed = bp->line_speed = SPEED_1000;
1949 bp->req_duplex = DUPLEX_FULL;
1950 }
1951 } else
1952 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1953}
1954
df149d70
MC		 1955static void
1956bnx2_send_heart_beat(struct bnx2 *bp)
1957{
1958 u32 msg;
1959 u32 addr;
1960
1961 spin_lock(&bp->indirect_lock);
1962 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1963 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1964 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1965 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1966 spin_unlock(&bp->indirect_lock);
1967}
1968
0d8a6571
MC		 1969static void
1970bnx2_remote_phy_event(struct bnx2 *bp)
1971{
1972 u32 msg;
1973 u8 link_up = bp->link_up;
1974 u8 old_port;
1975
2726d6e1 1976 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1977
df149d70
MC		 1978 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1979 bnx2_send_heart_beat(bp);
1980
1981 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1982
0d8a6571
MC		 1983 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1984 bp->link_up = 0;
1985 else {
1986 u32 speed;
1987
1988 bp->link_up = 1;
1989 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1990 bp->duplex = DUPLEX_FULL;
1991 switch (speed) {
1992 case BNX2_LINK_STATUS_10HALF:
1993 bp->duplex = DUPLEX_HALF;
1994 case BNX2_LINK_STATUS_10FULL:
1995 bp->line_speed = SPEED_10;
1996 break;
1997 case BNX2_LINK_STATUS_100HALF:
1998 bp->duplex = DUPLEX_HALF;
1999 case BNX2_LINK_STATUS_100BASE_T4:
2000 case BNX2_LINK_STATUS_100FULL:
2001 bp->line_speed = SPEED_100;
2002 break;
2003 case BNX2_LINK_STATUS_1000HALF:
2004 bp->duplex = DUPLEX_HALF;
2005 case BNX2_LINK_STATUS_1000FULL:
2006 bp->line_speed = SPEED_1000;
2007 break;
2008 case BNX2_LINK_STATUS_2500HALF:
2009 bp->duplex = DUPLEX_HALF;
2010 case BNX2_LINK_STATUS_2500FULL:
2011 bp->line_speed = SPEED_2500;
2012 break;
2013 default:
2014 bp->line_speed = 0;
2015 break;
2016 }
2017
0d8a6571
MC		 2018 bp->flow_ctrl = 0;
2019 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2020 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2021 if (bp->duplex == DUPLEX_FULL)
2022 bp->flow_ctrl = bp->req_flow_ctrl;
2023 } else {
2024 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2025 bp->flow_ctrl |= FLOW_CTRL_TX;
2026 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2027 bp->flow_ctrl |= FLOW_CTRL_RX;
2028 }
2029
2030 old_port = bp->phy_port;
2031 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2032 bp->phy_port = PORT_FIBRE;
2033 else
2034 bp->phy_port = PORT_TP;
2035
2036 if (old_port != bp->phy_port)
2037 bnx2_set_default_link(bp);
2038
0d8a6571
MC		 2039 }
2040 if (bp->link_up != link_up)
2041 bnx2_report_link(bp);
2042
2043 bnx2_set_mac_link(bp);
2044}
2045
2046static int
2047bnx2_set_remote_link(struct bnx2 *bp)
2048{
2049 u32 evt_code;
2050
2726d6e1 2051 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2052 switch (evt_code) {
2053 case BNX2_FW_EVT_CODE_LINK_EVENT:
2054 bnx2_remote_phy_event(bp);
2055 break;
2056 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2057 default:
df149d70 2058 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2059 break;
2060 }
2061 return 0;
2062}
2063
b6016b76
MC		 2064static int
2065bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2066__releases(&bp->phy_lock)
2067__acquires(&bp->phy_lock)
b6016b76
MC		 2068{
2069 u32 bmcr;
2070 u32 new_bmcr;
2071
ca58c3af 2072 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2073
2074 if (bp->autoneg & AUTONEG_SPEED) {
2075 u32 adv_reg, adv1000_reg;
2076 u32 new_adv_reg = 0;
2077 u32 new_adv1000_reg = 0;
2078
ca58c3af 2079 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2080 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2081 ADVERTISE_PAUSE_ASYM);
2082
2083 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2084 adv1000_reg &= PHY_ALL_1000_SPEED;
2085
2086 if (bp->advertising & ADVERTISED_10baseT_Half)
2087 new_adv_reg |= ADVERTISE_10HALF;
2088 if (bp->advertising & ADVERTISED_10baseT_Full)
2089 new_adv_reg |= ADVERTISE_10FULL;
2090 if (bp->advertising & ADVERTISED_100baseT_Half)
2091 new_adv_reg |= ADVERTISE_100HALF;
2092 if (bp->advertising & ADVERTISED_100baseT_Full)
2093 new_adv_reg |= ADVERTISE_100FULL;
2094 if (bp->advertising & ADVERTISED_1000baseT_Full)
2095 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 2096
b6016b76
MC		 2097 new_adv_reg |= ADVERTISE_CSMA;
2098
2099 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2100
2101 if ((adv1000_reg != new_adv1000_reg) ||
2102 (adv_reg != new_adv_reg) ||
2103 ((bmcr & BMCR_ANENABLE) == 0)) {
2104
ca58c3af 2105 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 2106 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 2107 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2108 BMCR_ANENABLE);
2109 }
2110 else if (bp->link_up) {
2111 /* Flow ctrl may have changed from auto to forced */
2112 /* or vice-versa. */
2113
2114 bnx2_resolve_flow_ctrl(bp);
2115 bnx2_set_mac_link(bp);
2116 }
2117 return 0;
2118 }
2119
2120 new_bmcr = 0;
2121 if (bp->req_line_speed == SPEED_100) {
2122 new_bmcr |= BMCR_SPEED100;
2123 }
2124 if (bp->req_duplex == DUPLEX_FULL) {
2125 new_bmcr |= BMCR_FULLDPLX;
2126 }
2127 if (new_bmcr != bmcr) {
2128 u32 bmsr;
b6016b76 2129
ca58c3af
MC		 2130 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2131 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2132
b6016b76
MC		 2133 if (bmsr & BMSR_LSTATUS) {
2134 /* Force link down */
ca58c3af 2135 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2136 spin_unlock_bh(&bp->phy_lock);
2137 msleep(50);
2138 spin_lock_bh(&bp->phy_lock);
2139
ca58c3af
MC		 2140 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2141 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2142 }
2143
ca58c3af 2144 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2145
2146 /* Normally, the new speed is setup after the link has
2147 * gone down and up again. In some cases, link will not go
2148 * down so we need to set up the new speed here.
2149 */
2150 if (bmsr & BMSR_LSTATUS) {
2151 bp->line_speed = bp->req_line_speed;
2152 bp->duplex = bp->req_duplex;
2153 bnx2_resolve_flow_ctrl(bp);
2154 bnx2_set_mac_link(bp);
2155 }
27a005b8
MC		 2156 } else {
2157 bnx2_resolve_flow_ctrl(bp);
2158 bnx2_set_mac_link(bp);
b6016b76
MC		 2159 }
2160 return 0;
2161}
2162
2163static int
0d8a6571 2164bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2165__releases(&bp->phy_lock)
2166__acquires(&bp->phy_lock)
b6016b76
MC		 2167{
2168 if (bp->loopback == MAC_LOOPBACK)
2169 return 0;
2170
583c28e5 2171 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 2172 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 2173 }
2174 else {
2175 return (bnx2_setup_copper_phy(bp));
2176 }
2177}
2178
27a005b8 2179static int
9a120bc5 2180bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2181{
2182 u32 val;
2183
2184 bp->mii_bmcr = MII_BMCR + 0x10;
2185 bp->mii_bmsr = MII_BMSR + 0x10;
2186 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2187 bp->mii_adv = MII_ADVERTISE + 0x10;
2188 bp->mii_lpa = MII_LPA + 0x10;
2189 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2190
2191 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2192 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2193
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2195 if (reset_phy)
2196 bnx2_reset_phy(bp);
27a005b8
MC		 2197
2198 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2199
2200 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2201 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2202 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2203 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2204
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2206 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2207 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2208 val |= BCM5708S_UP1_2G5;
2209 else
2210 val &= ~BCM5708S_UP1_2G5;
2211 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2212
2213 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2214 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2215 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2216 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2217
2218 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2219
2220 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2221 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2222 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2223
2224 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2225
2226 return 0;
2227}
2228
b6016b76 2229static int
9a120bc5 2230bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2231{
2232 u32 val;
2233
9a120bc5
MC		 2234 if (reset_phy)
2235 bnx2_reset_phy(bp);
27a005b8
MC		 2236
2237 bp->mii_up1 = BCM5708S_UP1;
2238
5b0c76ad
MC		 2239 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2240 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2241 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2242
2243 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2244 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2245 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2246
2247 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2248 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2249 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2250
583c28e5 2251 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2252 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2253 val |= BCM5708S_UP1_2G5;
2254 bnx2_write_phy(bp, BCM5708S_UP1, val);
2255 }
2256
2257 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2258 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2259 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2260 /* increase tx signal amplitude */
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2262 BCM5708S_BLK_ADDR_TX_MISC);
2263 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2264 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2265 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2266 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2267 }
2268
2726d6e1 2269 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2270 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2271
2272 if (val) {
2273 u32 is_backplane;
2274
2726d6e1 2275 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2276 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2277 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2278 BCM5708S_BLK_ADDR_TX_MISC);
2279 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2280 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2281 BCM5708S_BLK_ADDR_DIG);
2282 }
2283 }
2284 return 0;
2285}
2286
2287static int
9a120bc5 2288bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2289{
9a120bc5
MC		 2290 if (reset_phy)
2291 bnx2_reset_phy(bp);
27a005b8 2292
583c28e5 2293 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2294
59b47d8a
MC		 2295 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2296 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2297
2298 if (bp->dev->mtu > 1500) {
2299 u32 val;
2300
2301 /* Set extended packet length bit */
2302 bnx2_write_phy(bp, 0x18, 0x7);
2303 bnx2_read_phy(bp, 0x18, &val);
2304 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2305
2306 bnx2_write_phy(bp, 0x1c, 0x6c00);
2307 bnx2_read_phy(bp, 0x1c, &val);
2308 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2309 }
2310 else {
2311 u32 val;
2312
2313 bnx2_write_phy(bp, 0x18, 0x7);
2314 bnx2_read_phy(bp, 0x18, &val);
2315 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2316
2317 bnx2_write_phy(bp, 0x1c, 0x6c00);
2318 bnx2_read_phy(bp, 0x1c, &val);
2319 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2320 }
2321
2322 return 0;
2323}
2324
2325static int
9a120bc5 2326bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2327{
5b0c76ad
MC		 2328 u32 val;
2329
9a120bc5
MC		 2330 if (reset_phy)
2331 bnx2_reset_phy(bp);
27a005b8 2332
583c28e5 2333 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2334 bnx2_write_phy(bp, 0x18, 0x0c00);
2335 bnx2_write_phy(bp, 0x17, 0x000a);
2336 bnx2_write_phy(bp, 0x15, 0x310b);
2337 bnx2_write_phy(bp, 0x17, 0x201f);
2338 bnx2_write_phy(bp, 0x15, 0x9506);
2339 bnx2_write_phy(bp, 0x17, 0x401f);
2340 bnx2_write_phy(bp, 0x15, 0x14e2);
2341 bnx2_write_phy(bp, 0x18, 0x0400);
2342 }
2343
583c28e5 2344 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2345 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2346 MII_BNX2_DSP_EXPAND_REG | 0x8);
2347 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2348 val &= ~(1 << 8);
2349 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2350 }
2351
b6016b76 2352 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2353 /* Set extended packet length bit */
2354 bnx2_write_phy(bp, 0x18, 0x7);
2355 bnx2_read_phy(bp, 0x18, &val);
2356 bnx2_write_phy(bp, 0x18, val | 0x4000);
2357
2358 bnx2_read_phy(bp, 0x10, &val);
2359 bnx2_write_phy(bp, 0x10, val | 0x1);
2360 }
2361 else {
b6016b76
MC		 2362 bnx2_write_phy(bp, 0x18, 0x7);
2363 bnx2_read_phy(bp, 0x18, &val);
2364 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2365
2366 bnx2_read_phy(bp, 0x10, &val);
2367 bnx2_write_phy(bp, 0x10, val & ~0x1);
2368 }
2369
5b0c76ad
MC		 2370 /* ethernet@wirespeed */
2371 bnx2_write_phy(bp, 0x18, 0x7007);
2372 bnx2_read_phy(bp, 0x18, &val);
2373 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2374 return 0;
2375}
2376
2377
2378static int
9a120bc5 2379bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2380__releases(&bp->phy_lock)
2381__acquires(&bp->phy_lock)
b6016b76
MC		 2382{
2383 u32 val;
2384 int rc = 0;
2385
583c28e5
MC		 2386 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2387 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2388
ca58c3af
MC		 2389 bp->mii_bmcr = MII_BMCR;
2390 bp->mii_bmsr = MII_BMSR;
27a005b8 2391 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2392 bp->mii_adv = MII_ADVERTISE;
2393 bp->mii_lpa = MII_LPA;
2394
b6016b76
MC		 2395 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2396
583c28e5 2397 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2398 goto setup_phy;
2399
b6016b76
MC		 2400 bnx2_read_phy(bp, MII_PHYSID1, &val);
2401 bp->phy_id = val << 16;
2402 bnx2_read_phy(bp, MII_PHYSID2, &val);
2403 bp->phy_id |= val & 0xffff;
2404
583c28e5 2405 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2406 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2407 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2408 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2409 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2410 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2411 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2412 }
2413 else {
9a120bc5 2414 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2415 }
2416
0d8a6571
MC		 2417setup_phy:
2418 if (!rc)
2419 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2420
2421 return rc;
2422}
2423
2424static int
2425bnx2_set_mac_loopback(struct bnx2 *bp)
2426{
2427 u32 mac_mode;
2428
2429 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2430 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2431 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2432 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2433 bp->link_up = 1;
2434 return 0;
2435}
2436
bc5a0690
MC		 2437static int bnx2_test_link(struct bnx2 *);
2438
2439static int
2440bnx2_set_phy_loopback(struct bnx2 *bp)
2441{
2442 u32 mac_mode;
2443 int rc, i;
2444
2445 spin_lock_bh(&bp->phy_lock);
ca58c3af 2446 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2447 BMCR_SPEED1000);
2448 spin_unlock_bh(&bp->phy_lock);
2449 if (rc)
2450 return rc;
2451
2452 for (i = 0; i < 10; i++) {
2453 if (bnx2_test_link(bp) == 0)
2454 break;
80be4434 2455 msleep(100);
bc5a0690
MC		 2456 }
2457
2458 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2459 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2460 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2461 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2462
2463 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2464 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2465 bp->link_up = 1;
2466 return 0;
2467}
2468
b6016b76 2469static int
a2f13890 2470bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2471{
2472 int i;
2473 u32 val;
2474
b6016b76
MC		 2475 bp->fw_wr_seq++;
2476 msg_data |= bp->fw_wr_seq;
2477
2726d6e1 2478 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2479
a2f13890
MC		 2480 if (!ack)
2481 return 0;
2482
b6016b76 2483 /* wait for an acknowledgement. */
40105c0b 2484 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2485 msleep(10);
b6016b76 2486
2726d6e1 2487 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2488
2489 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2490 break;
2491 }
b090ae2b
MC		 2492 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2493 return 0;
b6016b76
MC		 2494
2495 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2496 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2497 if (!silent)
3a9c6a49 2498 pr_err("fw sync timeout, reset code = %x\n", msg_data);
b6016b76
MC		 2499
2500 msg_data &= ~BNX2_DRV_MSG_CODE;
2501 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2502
2726d6e1 2503 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2504
b6016b76
MC		 2505 return -EBUSY;
2506 }
2507
b090ae2b
MC		 2508 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2509 return -EIO;
2510
b6016b76
MC		 2511 return 0;
2512}
2513
59b47d8a
MC		 2514static int
2515bnx2_init_5709_context(struct bnx2 *bp)
2516{
2517 int i, ret = 0;
2518 u32 val;
2519
2520 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2521 val |= (BCM_PAGE_BITS - 8) << 16;
2522 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2523 for (i = 0; i < 10; i++) {
2524 val = REG_RD(bp, BNX2_CTX_COMMAND);
2525 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2526 break;
2527 udelay(2);
2528 }
2529 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2530 return -EBUSY;
2531
59b47d8a
MC		 2532 for (i = 0; i < bp->ctx_pages; i++) {
2533 int j;
2534
352f7687
MC		 2535 if (bp->ctx_blk[i])
2536 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2537 else
2538 return -ENOMEM;
2539
59b47d8a
MC		 2540 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2541 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2542 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2543 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2544 (u64) bp->ctx_blk_mapping[i] >> 32);
2545 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2546 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2547 for (j = 0; j < 10; j++) {
2548
2549 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2550 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2551 break;
2552 udelay(5);
2553 }
2554 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2555 ret = -EBUSY;
2556 break;
2557 }
2558 }
2559 return ret;
2560}
2561
b6016b76
MC		 2562static void
2563bnx2_init_context(struct bnx2 *bp)
2564{
2565 u32 vcid;
2566
2567 vcid = 96;
2568 while (vcid) {
2569 u32 vcid_addr, pcid_addr, offset;
7947b20e 2570 int i;
b6016b76
MC		 2571
2572 vcid--;
2573
2574 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2575 u32 new_vcid;
2576
2577 vcid_addr = GET_PCID_ADDR(vcid);
2578 if (vcid & 0x8) {
2579 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2580 }
2581 else {
2582 new_vcid = vcid;
2583 }
2584 pcid_addr = GET_PCID_ADDR(new_vcid);
2585 }
2586 else {
2587 vcid_addr = GET_CID_ADDR(vcid);
2588 pcid_addr = vcid_addr;
2589 }
2590
7947b20e
MC		 2591 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2592 vcid_addr += (i << PHY_CTX_SHIFT);
2593 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2594
5d5d0015 2595 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2596 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2597
7947b20e
MC		 2598 /* Zero out the context. */
2599 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2600 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2601 }
b6016b76
MC		 2602 }
2603}
2604
2605static int
2606bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2607{
2608 u16 *good_mbuf;
2609 u32 good_mbuf_cnt;
2610 u32 val;
2611
2612 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2613 if (good_mbuf == NULL) {
3a9c6a49 2614 pr_err("Failed to allocate memory in %s\n", __func__);
b6016b76
MC		 2615 return -ENOMEM;
2616 }
2617
2618 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2619 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2620
2621 good_mbuf_cnt = 0;
2622
2623 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2624 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2625 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2626 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2627 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2628
2726d6e1 2629 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2630
2631 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2632
2633 /* The addresses with Bit 9 set are bad memory blocks. */
2634 if (!(val & (1 << 9))) {
2635 good_mbuf[good_mbuf_cnt] = (u16) val;
2636 good_mbuf_cnt++;
2637 }
2638
2726d6e1 2639 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2640 }
2641
2642 /* Free the good ones back to the mbuf pool thus discarding
2643 * all the bad ones. */
2644 while (good_mbuf_cnt) {
2645 good_mbuf_cnt--;
2646
2647 val = good_mbuf[good_mbuf_cnt];
2648 val = (val << 9) | val | 1;
2649
2726d6e1 2650 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2651 }
2652 kfree(good_mbuf);
2653 return 0;
2654}
2655
2656static void
5fcaed01 2657bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2658{
2659 u32 val;
b6016b76
MC		 2660
2661 val = (mac_addr[0] << 8) | mac_addr[1];
2662
5fcaed01 2663 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2664
6aa20a22 2665 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2666 (mac_addr[4] << 8) | mac_addr[5];
2667
5fcaed01 2668 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2669}
2670
47bf4246 2671static inline int
a2df00aa 2672bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2673{
2674 dma_addr_t mapping;
bb4f98ab 2675 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2676 struct rx_bd *rxbd =
bb4f98ab 2677 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
a2df00aa 2678 struct page *page = alloc_page(gfp);
47bf4246
MC		 2679
2680 if (!page)
2681 return -ENOMEM;
36227e88 2682 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2683 PCI_DMA_FROMDEVICE);
36227e88 2684 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2685 __free_page(page);
2686 return -EIO;
2687 }
2688
47bf4246 2689 rx_pg->page = page;
1a4ccc2d 2690 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2691 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2692 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2693 return 0;
2694}
2695
2696static void
bb4f98ab 2697bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2698{
bb4f98ab 2699 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2700 struct page *page = rx_pg->page;
2701
2702 if (!page)
2703 return;
2704
36227e88
SG		 2705 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2706 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2707
2708 __free_page(page);
2709 rx_pg->page = NULL;
2710}
2711
b6016b76 2712static inline int
a2df00aa 2713bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76
MC		 2714{
2715 struct sk_buff *skb;
bb4f98ab 2716 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2717 dma_addr_t mapping;
bb4f98ab 2718 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2719 unsigned long align;
2720
a2df00aa 2721 skb = __netdev_alloc_skb(bp->dev, bp->rx_buf_size, gfp);
b6016b76
MC		 2722 if (skb == NULL) {
2723 return -ENOMEM;
2724 }
2725
59b47d8a
MC		 2726 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2727 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2728
36227e88
SG		 2729 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_use_size,
2730 PCI_DMA_FROMDEVICE);
2731 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2732 dev_kfree_skb(skb);
2733 return -EIO;
2734 }
b6016b76
MC		 2735
2736 rx_buf->skb = skb;
a33fa66b 2737 rx_buf->desc = (struct l2_fhdr *) skb->data;
1a4ccc2d 2738 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2739
2740 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2741 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2742
bb4f98ab 2743 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2744
2745 return 0;
2746}
2747
da3e4fbe 2748static int
35efa7c1 2749bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2750{
43e80b89 2751 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2752 u32 new_link_state, old_link_state;
da3e4fbe 2753 int is_set = 1;
b6016b76 2754
da3e4fbe
MC		 2755 new_link_state = sblk->status_attn_bits & event;
2756 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2757 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2758 if (new_link_state)
2759 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2760 else
2761 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2762 } else
2763 is_set = 0;
2764
2765 return is_set;
2766}
2767
2768static void
35efa7c1 2769bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2770{
74ecc62d
MC		 2771 spin_lock(&bp->phy_lock);
2772
2773 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2774 bnx2_set_link(bp);
35efa7c1 2775 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2776 bnx2_set_remote_link(bp);
2777
74ecc62d
MC		 2778 spin_unlock(&bp->phy_lock);
2779
b6016b76
MC		 2780}
2781
ead7270b 2782static inline u16
35efa7c1 2783bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2784{
2785 u16 cons;
2786
43e80b89
MC		 2787 /* Tell compiler that status block fields can change. */
2788 barrier();
2789 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2790 barrier();
ead7270b
MC		 2791 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2792 cons++;
2793 return cons;
2794}
2795
57851d84
MC		 2796static int
2797bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2798{
35e9010b 2799 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2800 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2801 int tx_pkt = 0, index;
2802 struct netdev_queue *txq;
2803
2804 index = (bnapi - bp->bnx2_napi);
2805 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2806
35efa7c1 2807 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2808 sw_cons = txr->tx_cons;
b6016b76
MC		 2809
2810 while (sw_cons != hw_cons) {
3d16af86 2811 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2812 struct sk_buff *skb;
2813 int i, last;
2814
2815 sw_ring_cons = TX_RING_IDX(sw_cons);
2816
35e9010b 2817 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2818 skb = tx_buf->skb;
1d39ed56 2819
d62fda08
ED		 2820 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2821 prefetch(&skb->end);
2822
b6016b76 2823 /* partial BD completions possible with TSO packets */
d62fda08 2824 if (tx_buf->is_gso) {
b6016b76
MC		 2825 u16 last_idx, last_ring_idx;
2826
d62fda08
ED		 2827 last_idx = sw_cons + tx_buf->nr_frags + 1;
2828 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
b6016b76
MC		 2829 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2830 last_idx++;
2831 }
2832 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2833 break;
2834 }
2835 }
1d39ed56 2836
36227e88 2837 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2838 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2839
2840 tx_buf->skb = NULL;
d62fda08 2841 last = tx_buf->nr_frags;
b6016b76
MC		 2842
2843 for (i = 0; i < last; i++) {
2844 sw_cons = NEXT_TX_BD(sw_cons);
e95524a7 2845
36227e88 2846 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 2847 dma_unmap_addr(
e95524a7
AD		 2848 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2849 mapping),
2850 skb_shinfo(skb)->frags[i].size,
2851 PCI_DMA_TODEVICE);
b6016b76
MC		 2852 }
2853
2854 sw_cons = NEXT_TX_BD(sw_cons);
2855
745720e5 2856 dev_kfree_skb(skb);
57851d84
MC		 2857 tx_pkt++;
2858 if (tx_pkt == budget)
2859 break;
b6016b76 2860
d62fda08
ED		 2861 if (hw_cons == sw_cons)
2862 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2863 }
2864
35e9010b
MC		 2865 txr->hw_tx_cons = hw_cons;
2866 txr->tx_cons = sw_cons;
706bf240 2867
2f8af120 2868 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2869 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2870 * memory barrier, there is a small possibility that bnx2_start_xmit()
2871 * will miss it and cause the queue to be stopped forever.
2872 */
2873 smp_mb();
b6016b76 2874
706bf240 2875 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2876 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2877 __netif_tx_lock(txq, smp_processor_id());
2878 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2879 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2880 netif_tx_wake_queue(txq);
2881 __netif_tx_unlock(txq);
b6016b76 2882 }
706bf240 2883
57851d84 2884 return tx_pkt;
b6016b76
MC		 2885}
2886
1db82f2a 2887static void
bb4f98ab 2888bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2889 struct sk_buff *skb, int count)
1db82f2a
MC		 2890{
2891 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2892 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2893 int i;
3d16af86 2894 u16 hw_prod, prod;
bb4f98ab 2895 u16 cons = rxr->rx_pg_cons;
1db82f2a 2896
3d16af86
BL		 2897 cons_rx_pg = &rxr->rx_pg_ring[cons];
2898
2899 /* The caller was unable to allocate a new page to replace the
2900 * last one in the frags array, so we need to recycle that page
2901 * and then free the skb.
2902 */
2903 if (skb) {
2904 struct page *page;
2905 struct skb_shared_info *shinfo;
2906
2907 shinfo = skb_shinfo(skb);
2908 shinfo->nr_frags--;
2909 page = shinfo->frags[shinfo->nr_frags].page;
2910 shinfo->frags[shinfo->nr_frags].page = NULL;
2911
2912 cons_rx_pg->page = page;
2913 dev_kfree_skb(skb);
2914 }
2915
2916 hw_prod = rxr->rx_pg_prod;
2917
1db82f2a
MC		 2918 for (i = 0; i < count; i++) {
2919 prod = RX_PG_RING_IDX(hw_prod);
2920
bb4f98ab
MC		 2921 prod_rx_pg = &rxr->rx_pg_ring[prod];
2922 cons_rx_pg = &rxr->rx_pg_ring[cons];
2923 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2924 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2925
1db82f2a
MC		 2926 if (prod != cons) {
2927 prod_rx_pg->page = cons_rx_pg->page;
2928 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2929 dma_unmap_addr_set(prod_rx_pg, mapping,
2930 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2931
2932 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2933 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2934
2935 }
2936 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2937 hw_prod = NEXT_RX_BD(hw_prod);
2938 }
bb4f98ab
MC		 2939 rxr->rx_pg_prod = hw_prod;
2940 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2941}
2942
b6016b76 2943static inline void
bb4f98ab
MC		 2944bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2945 struct sk_buff *skb, u16 cons, u16 prod)
b6016b76 2946{
236b6394
MC		 2947 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2948 struct rx_bd *cons_bd, *prod_bd;
2949
bb4f98ab
MC		 2950 cons_rx_buf = &rxr->rx_buf_ring[cons];
2951 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 2952
36227e88 2953 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 2954 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2955 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2956
bb4f98ab 2957 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2958
236b6394 2959 prod_rx_buf->skb = skb;
a33fa66b 2960 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
b6016b76 2961
236b6394
MC		 2962 if (cons == prod)
2963 return;
b6016b76 2964
1a4ccc2d
FT		 2965 dma_unmap_addr_set(prod_rx_buf, mapping,
2966 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2967
bb4f98ab
MC		 2968 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2969 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2970 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2971 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2972}
2973
85833c62 2974static int
bb4f98ab 2975bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
a1f60190
MC		 2976 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2977 u32 ring_idx)
85833c62
MC		 2978{
2979 int err;
2980 u16 prod = ring_idx & 0xffff;
2981
a2df00aa 2982 err = bnx2_alloc_rx_skb(bp, rxr, prod, GFP_ATOMIC);
85833c62 2983 if (unlikely(err)) {
bb4f98ab 2984 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2985 if (hdr_len) {
2986 unsigned int raw_len = len + 4;
2987 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2988
bb4f98ab 2989 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 2990 }
85833c62
MC		 2991 return err;
2992 }
2993
d89cb6af 2994 skb_reserve(skb, BNX2_RX_OFFSET);
36227e88 2995 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62
MC		 2996 PCI_DMA_FROMDEVICE);
2997
1db82f2a
MC		 2998 if (hdr_len == 0) {
2999 skb_put(skb, len);
3000 return 0;
3001 } else {
3002 unsigned int i, frag_len, frag_size, pages;
3003 struct sw_pg *rx_pg;
bb4f98ab
MC		 3004 u16 pg_cons = rxr->rx_pg_cons;
3005 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3006
3007 frag_size = len + 4 - hdr_len;
3008 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3009 skb_put(skb, hdr_len);
3010
3011 for (i = 0; i < pages; i++) {
3d16af86
BL		 3012 dma_addr_t mapping_old;
3013
1db82f2a
MC		 3014 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3015 if (unlikely(frag_len <= 4)) {
3016 unsigned int tail = 4 - frag_len;
3017
bb4f98ab
MC		 3018 rxr->rx_pg_cons = pg_cons;
3019 rxr->rx_pg_prod = pg_prod;
3020 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3021 pages - i);
1db82f2a
MC		 3022 skb->len -= tail;
3023 if (i == 0) {
3024 skb->tail -= tail;
3025 } else {
3026 skb_frag_t *frag =
3027 &skb_shinfo(skb)->frags[i - 1];
3028 frag->size -= tail;
3029 skb->data_len -= tail;
3030 skb->truesize -= tail;
3031 }
3032 return 0;
3033 }
bb4f98ab 3034 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3035
3d16af86
BL		 3036 /* Don't unmap yet. If we're unable to allocate a new
3037 * page, we need to recycle the page and the DMA addr.
3038 */
1a4ccc2d 3039 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3040 if (i == pages - 1)
3041 frag_len -= 4;
3042
3043 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3044 rx_pg->page = NULL;
3045
bb4f98ab 3046 err = bnx2_alloc_rx_page(bp, rxr,
a2df00aa
SG		 3047 RX_PG_RING_IDX(pg_prod),
3048 GFP_ATOMIC);
1db82f2a 3049 if (unlikely(err)) {
bb4f98ab
MC		 3050 rxr->rx_pg_cons = pg_cons;
3051 rxr->rx_pg_prod = pg_prod;
3052 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3053 pages - i);
1db82f2a
MC		 3054 return err;
3055 }
3056
36227e88 3057 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3058 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3059
1db82f2a
MC		 3060 frag_size -= frag_len;
3061 skb->data_len += frag_len;
3062 skb->truesize += frag_len;
3063 skb->len += frag_len;
3064
3065 pg_prod = NEXT_RX_BD(pg_prod);
3066 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3067 }
bb4f98ab
MC		 3068 rxr->rx_pg_prod = pg_prod;
3069 rxr->rx_pg_cons = pg_cons;
1db82f2a 3070 }
85833c62
MC		 3071 return 0;
3072}
3073
c09c2627 3074static inline u16
35efa7c1 3075bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3076{
bb4f98ab
MC		 3077 u16 cons;
3078
43e80b89
MC		 3079 /* Tell compiler that status block fields can change. */
3080 barrier();
3081 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3082 barrier();
c09c2627
MC		 3083 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3084 cons++;
3085 return cons;
3086}
3087
b6016b76 3088static int
35efa7c1 3089bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3090{
bb4f98ab 3091 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3092 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3093 struct l2_fhdr *rx_hdr;
1db82f2a 3094 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3095
35efa7c1 3096 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3097 sw_cons = rxr->rx_cons;
3098 sw_prod = rxr->rx_prod;
b6016b76
MC		 3099
3100 /* Memory barrier necessary as speculative reads of the rx
3101 * buffer can be ahead of the index in the status block
3102 */
3103 rmb();
3104 while (sw_cons != hw_cons) {
1db82f2a 3105 unsigned int len, hdr_len;
ade2bfe7 3106 u32 status;
a33fa66b 3107 struct sw_bd *rx_buf, *next_rx_buf;
b6016b76 3108 struct sk_buff *skb;
236b6394 3109 dma_addr_t dma_addr;
f22828e8
MC		 3110 u16 vtag = 0;
3111 int hw_vlan __maybe_unused = 0;
b6016b76
MC		 3112
3113 sw_ring_cons = RX_RING_IDX(sw_cons);
3114 sw_ring_prod = RX_RING_IDX(sw_prod);
3115
bb4f98ab 3116 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
b6016b76 3117 skb = rx_buf->skb;
a33fa66b 3118 prefetchw(skb);
236b6394 3119
aabef8b2
FT		 3120 next_rx_buf =
3121 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3122 prefetch(next_rx_buf->desc);
3123
236b6394
MC		 3124 rx_buf->skb = NULL;
3125
1a4ccc2d 3126 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3127
36227e88 3128 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3129 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3130 PCI_DMA_FROMDEVICE);
b6016b76 3131
a33fa66b 3132 rx_hdr = rx_buf->desc;
1db82f2a 3133 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3134 status = rx_hdr->l2_fhdr_status;
b6016b76 3135
1db82f2a
MC		 3136 hdr_len = 0;
3137 if (status & L2_FHDR_STATUS_SPLIT) {
3138 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3139 pg_ring_used = 1;
3140 } else if (len > bp->rx_jumbo_thresh) {
3141 hdr_len = bp->rx_jumbo_thresh;
3142 pg_ring_used = 1;
3143 }
3144
990ec380
MC		 3145 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3146 L2_FHDR_ERRORS_PHY_DECODE |
3147 L2_FHDR_ERRORS_ALIGNMENT |
3148 L2_FHDR_ERRORS_TOO_SHORT |
3149 L2_FHDR_ERRORS_GIANT_FRAME))) {
3150
3151 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3152 sw_ring_prod);
3153 if (pg_ring_used) {
3154 int pages;
3155
3156 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3157
3158 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3159 }
3160 goto next_rx;
3161 }
3162
1db82f2a 3163 len -= 4;
b6016b76 3164
5d5d0015 3165 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 3166 struct sk_buff *new_skb;
3167
f22828e8 3168 new_skb = netdev_alloc_skb(bp->dev, len + 6);
85833c62 3169 if (new_skb == NULL) {
bb4f98ab 3170 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
85833c62
MC		 3171 sw_ring_prod);
3172 goto next_rx;
3173 }
b6016b76
MC		 3174
3175 /* aligned copy */
d89cb6af 3176 skb_copy_from_linear_data_offset(skb,
f22828e8
MC		 3177 BNX2_RX_OFFSET - 6,
3178 new_skb->data, len + 6);
3179 skb_reserve(new_skb, 6);
b6016b76 3180 skb_put(new_skb, len);
b6016b76 3181
bb4f98ab 3182 bnx2_reuse_rx_skb(bp, rxr, skb,
b6016b76
MC		 3183 sw_ring_cons, sw_ring_prod);
3184
3185 skb = new_skb;
bb4f98ab 3186 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
a1f60190 3187 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 3188 goto next_rx;
b6016b76 3189
f22828e8
MC		 3190 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3191 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3192 vtag = rx_hdr->l2_fhdr_vlan_tag;
3193#ifdef BCM_VLAN
3194 if (bp->vlgrp)
3195 hw_vlan = 1;
3196 else
3197#endif
3198 {
3199 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3200 __skb_push(skb, 4);
3201
3202 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3203 ve->h_vlan_proto = htons(ETH_P_8021Q);
3204 ve->h_vlan_TCI = htons(vtag);
3205 len += 4;
3206 }
3207 }
3208
b6016b76
MC		 3209 skb->protocol = eth_type_trans(skb, bp->dev);
3210
3211 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3212 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3213
745720e5 3214 dev_kfree_skb(skb);
b6016b76
MC		 3215 goto next_rx;
3216
3217 }
3218
b6016b76
MC		 3219 skb->ip_summed = CHECKSUM_NONE;
3220 if (bp->rx_csum &&
3221 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3222 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3223
ade2bfe7
MC		 3224 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3225 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3226 skb->ip_summed = CHECKSUM_UNNECESSARY;
3227 }
fdc8541d
MC		 3228 if ((bp->dev->features & NETIF_F_RXHASH) &&
3229 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3230 L2_FHDR_STATUS_USE_RXHASH))
3231 skb->rxhash = rx_hdr->l2_fhdr_hash;
b6016b76 3232
0c8dfc83
DM		 3233 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3234
b6016b76 3235#ifdef BCM_VLAN
f22828e8 3236 if (hw_vlan)
c67938a9 3237 vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
b6016b76
MC		 3238 else
3239#endif
c67938a9 3240 napi_gro_receive(&bnapi->napi, skb);
b6016b76 3241
b6016b76
MC		 3242 rx_pkt++;
3243
3244next_rx:
b6016b76
MC		 3245 sw_cons = NEXT_RX_BD(sw_cons);
3246 sw_prod = NEXT_RX_BD(sw_prod);
3247
3248 if ((rx_pkt == budget))
3249 break;
f4e418f7
MC		 3250
3251 /* Refresh hw_cons to see if there is new work */
3252 if (sw_cons == hw_cons) {
35efa7c1 3253 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3254 rmb();
3255 }
b6016b76 3256 }
bb4f98ab
MC		 3257 rxr->rx_cons = sw_cons;
3258 rxr->rx_prod = sw_prod;
b6016b76 3259
1db82f2a 3260 if (pg_ring_used)
bb4f98ab 3261 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3262
bb4f98ab 3263 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3264
bb4f98ab 3265 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3266
3267 mmiowb();
3268
3269 return rx_pkt;
3270
3271}
3272
3273/* MSI ISR - The only difference between this and the INTx ISR
3274 * is that the MSI interrupt is always serviced.
3275 */
3276static irqreturn_t
7d12e780 3277bnx2_msi(int irq, void *dev_instance)
b6016b76 3278{
f0ea2e63
MC		 3279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
b6016b76 3281
43e80b89 3282 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3283 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3284 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3285 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3286
3287 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3288 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3289 return IRQ_HANDLED;
b6016b76 3290
288379f0 3291 napi_schedule(&bnapi->napi);
b6016b76 3292
73eef4cd 3293 return IRQ_HANDLED;
b6016b76
MC		 3294}
3295
8e6a72c4
MC		 3296static irqreturn_t
3297bnx2_msi_1shot(int irq, void *dev_instance)
3298{
f0ea2e63
MC		 3299 struct bnx2_napi *bnapi = dev_instance;
3300 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3301
43e80b89 3302 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3303
3304 /* Return here if interrupt is disabled. */
3305 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3306 return IRQ_HANDLED;
3307
288379f0 3308 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3309
3310 return IRQ_HANDLED;
3311}
3312
b6016b76 3313static irqreturn_t
7d12e780 3314bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3315{
f0ea2e63
MC		 3316 struct bnx2_napi *bnapi = dev_instance;
3317 struct bnx2 *bp = bnapi->bp;
43e80b89 3318 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3319
3320 /* When using INTx, it is possible for the interrupt to arrive
3321 * at the CPU before the status block posted prior to the
3322 * interrupt. Reading a register will flush the status block.
3323 * When using MSI, the MSI message will always complete after
3324 * the status block write.
3325 */
35efa7c1 3326 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3327 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3328 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3329 return IRQ_NONE;
b6016b76
MC		 3330
3331 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3332 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3333 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3334
b8a7ce7b
MC		 3335 /* Read back to deassert IRQ immediately to avoid too many
3336 * spurious interrupts.
3337 */
3338 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3339
b6016b76 3340 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3341 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3342 return IRQ_HANDLED;
b6016b76 3343
288379f0 3344 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3345 bnapi->last_status_idx = sblk->status_idx;
288379f0 3346 __napi_schedule(&bnapi->napi);
b8a7ce7b 3347 }
b6016b76 3348
73eef4cd 3349 return IRQ_HANDLED;
b6016b76
MC		 3350}
3351
f4e418f7 3352static inline int
43e80b89 3353bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3354{
35e9010b 3355 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3356 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3357
bb4f98ab 3358 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3359 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3360 return 1;
43e80b89
MC		 3361 return 0;
3362}
3363
3364#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3365 STATUS_ATTN_BITS_TIMER_ABORT)
3366
3367static inline int
3368bnx2_has_work(struct bnx2_napi *bnapi)
3369{
3370 struct status_block *sblk = bnapi->status_blk.msi;
3371
3372 if (bnx2_has_fast_work(bnapi))
3373 return 1;
f4e418f7 3374
4edd473f
MC		 3375#ifdef BCM_CNIC
3376 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3377 return 1;
3378#endif
3379
da3e4fbe
MC		 3380 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3381 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3382 return 1;
3383
3384 return 0;
3385}
3386
efba0180
MC		 3387static void
3388bnx2_chk_missed_msi(struct bnx2 *bp)
3389{
3390 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3391 u32 msi_ctrl;
3392
3393 if (bnx2_has_work(bnapi)) {
3394 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3395 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3396 return;
3397
3398 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3399 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3400 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3401 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3402 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3403 }
3404 }
3405
3406 bp->idle_chk_status_idx = bnapi->last_status_idx;
3407}
3408
4edd473f
MC		 3409#ifdef BCM_CNIC
3410static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3411{
3412 struct cnic_ops *c_ops;
3413
3414 if (!bnapi->cnic_present)
3415 return;
3416
3417 rcu_read_lock();
3418 c_ops = rcu_dereference(bp->cnic_ops);
3419 if (c_ops)
3420 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3421 bnapi->status_blk.msi);
3422 rcu_read_unlock();
3423}
3424#endif
3425
43e80b89 3426static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3427{
43e80b89 3428 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3429 u32 status_attn_bits = sblk->status_attn_bits;
3430 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3431
da3e4fbe
MC		 3432 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3433 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3434
35efa7c1 3435 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3436
3437 /* This is needed to take care of transient status
3438 * during link changes.
3439 */
3440 REG_WR(bp, BNX2_HC_COMMAND,
3441 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3442 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3443 }
43e80b89
MC		 3444}
3445
3446static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3447 int work_done, int budget)
3448{
3449 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3450 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3451
35e9010b 3452 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3453 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3454
bb4f98ab 3455 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3456 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3457
6f535763
DM		 3458 return work_done;
3459}
3460
f0ea2e63
MC		 3461static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3462{
3463 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3464 struct bnx2 *bp = bnapi->bp;
3465 int work_done = 0;
3466 struct status_block_msix *sblk = bnapi->status_blk.msix;
3467
3468 while (1) {
3469 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3470 if (unlikely(work_done >= budget))
3471 break;
3472
3473 bnapi->last_status_idx = sblk->status_idx;
3474 /* status idx must be read before checking for more work. */
3475 rmb();
3476 if (likely(!bnx2_has_fast_work(bnapi))) {
3477
288379f0 3478 napi_complete(napi);
f0ea2e63
MC		 3479 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3480 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3481 bnapi->last_status_idx);
3482 break;
3483 }
3484 }
3485 return work_done;
3486}
3487
6f535763
DM		 3488static int bnx2_poll(struct napi_struct *napi, int budget)
3489{
35efa7c1
MC		 3490 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3491 struct bnx2 *bp = bnapi->bp;
6f535763 3492 int work_done = 0;
43e80b89 3493 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3494
3495 while (1) {
43e80b89
MC		 3496 bnx2_poll_link(bp, bnapi);
3497
35efa7c1 3498 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3499
4edd473f
MC		 3500#ifdef BCM_CNIC
3501 bnx2_poll_cnic(bp, bnapi);
3502#endif
3503
35efa7c1 3504 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3505 * much work has been processed, so we must read it before
3506 * checking for more work.
3507 */
35efa7c1 3508 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3509
3510 if (unlikely(work_done >= budget))
3511 break;
3512
6dee6421 3513 rmb();
35efa7c1 3514 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3515 napi_complete(napi);
f86e82fb 3516 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3517 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3518 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3519 bnapi->last_status_idx);
6dee6421 3520 break;
6f535763 3521 }
1269a8a6
MC		 3522 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3523 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3524 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3525 bnapi->last_status_idx);
1269a8a6 3526
6f535763
DM		 3527 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3528 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3529 bnapi->last_status_idx);
6f535763
DM		 3530 break;
3531 }
b6016b76
MC		 3532 }
3533
bea3348e 3534 return work_done;
b6016b76
MC		 3535}
3536
932ff279 3537/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3538 * from set_multicast.
3539 */
3540static void
3541bnx2_set_rx_mode(struct net_device *dev)
3542{
972ec0d4 3543 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3544 u32 rx_mode, sort_mode;
ccffad25 3545 struct netdev_hw_addr *ha;
b6016b76 3546 int i;
b6016b76 3547
9f52b564
MC		 3548 if (!netif_running(dev))
3549 return;
3550
c770a65c 3551 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3552
3553 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3554 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3555 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3556#ifdef BCM_VLAN
7c6337a1 3557 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3558 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3559#else
7c6337a1 3560 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
e29054f9 3561 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3562#endif
3563 if (dev->flags & IFF_PROMISC) {
3564 /* Promiscuous mode. */
3565 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3566 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3567 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3568 }
3569 else if (dev->flags & IFF_ALLMULTI) {
3570 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3571 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3572 0xffffffff);
3573 }
3574 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3575 }
3576 else {
3577 /* Accept one or more multicast(s). */
b6016b76
MC		 3578 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3579 u32 regidx;
3580 u32 bit;
3581 u32 crc;
3582
3583 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3584
22bedad3
JP		 3585 netdev_for_each_mc_addr(ha, dev) {
3586 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3587 bit = crc & 0xff;
3588 regidx = (bit & 0xe0) >> 5;
3589 bit &= 0x1f;
3590 mc_filter[regidx] |= (1 << bit);
3591 }
3592
3593 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3594 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3595 mc_filter[i]);
3596 }
3597
3598 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3599 }
3600
32e7bfc4 3601 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3602 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3603 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3604 BNX2_RPM_SORT_USER0_PROM_VLAN;
3605 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3606 /* Add all entries into to the match filter list */
ccffad25 3607 i = 0;
32e7bfc4 3608 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3609 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3610 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3611 sort_mode |= (1 <<
3612 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3613 i++;
5fcaed01
BL		 3614 }
3615
3616 }
3617
b6016b76
MC		 3618 if (rx_mode != bp->rx_mode) {
3619 bp->rx_mode = rx_mode;
3620 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3621 }
3622
3623 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3624 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3625 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3626
c770a65c 3627 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3628}
3629
57579f76
MC		 3630static int __devinit
3631check_fw_section(const struct firmware *fw,
3632 const struct bnx2_fw_file_section *section,
3633 u32 alignment, bool non_empty)
3634{
3635 u32 offset = be32_to_cpu(section->offset);
3636 u32 len = be32_to_cpu(section->len);
3637
3638 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3639 return -EINVAL;
3640 if ((non_empty && len == 0) || len > fw->size - offset ||
3641 len & (alignment - 1))
3642 return -EINVAL;
3643 return 0;
3644}
3645
3646static int __devinit
3647check_mips_fw_entry(const struct firmware *fw,
3648 const struct bnx2_mips_fw_file_entry *entry)
3649{
3650 if (check_fw_section(fw, &entry->text, 4, true) ||
3651 check_fw_section(fw, &entry->data, 4, false) ||
3652 check_fw_section(fw, &entry->rodata, 4, false))
3653 return -EINVAL;
3654 return 0;
3655}
3656
3657static int __devinit
3658bnx2_request_firmware(struct bnx2 *bp)
b6016b76 3659{
57579f76 3660 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3661 const struct bnx2_mips_fw_file *mips_fw;
3662 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3663 int rc;
3664
3665 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3666 mips_fw_file = FW_MIPS_FILE_09;
078b0735
MC		 3667 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3668 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3669 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3670 else
3671 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3672 } else {
3673 mips_fw_file = FW_MIPS_FILE_06;
3674 rv2p_fw_file = FW_RV2P_FILE_06;
3675 }
3676
3677 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3678 if (rc) {
3a9c6a49 3679 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
57579f76
MC		 3680 return rc;
3681 }
3682
3683 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3684 if (rc) {
3a9c6a49 3685 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
57579f76
MC		 3686 return rc;
3687 }
5ee1c326
BB		 3688 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3689 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3690 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3691 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3692 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3693 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3694 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3695 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3696 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
57579f76
MC		 3697 return -EINVAL;
3698 }
5ee1c326
BB		 3699 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3700 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3701 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3702 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
57579f76
MC		 3703 return -EINVAL;
3704 }
3705
3706 return 0;
3707}
3708
3709static u32
3710rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3711{
3712 switch (idx) {
3713 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3714 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3715 rv2p_code |= RV2P_BD_PAGE_SIZE;
3716 break;
3717 }
3718 return rv2p_code;
3719}
3720
3721static int
3722load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3723 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3724{
3725 u32 rv2p_code_len, file_offset;
3726 __be32 *rv2p_code;
b6016b76 3727 int i;
57579f76
MC		 3728 u32 val, cmd, addr;
3729
3730 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3731 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3732
3733 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3734
57579f76
MC		 3735 if (rv2p_proc == RV2P_PROC1) {
3736 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3737 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3738 } else {
3739 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3740 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3741 }
b6016b76
MC		 3742
3743 for (i = 0; i < rv2p_code_len; i += 8) {
57579f76 3744 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3745 rv2p_code++;
57579f76 3746 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3747 rv2p_code++;
3748
57579f76
MC		 3749 val = (i / 8) | cmd;
3750 REG_WR(bp, addr, val);
3751 }
3752
3753 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3754 for (i = 0; i < 8; i++) {
3755 u32 loc, code;
3756
3757 loc = be32_to_cpu(fw_entry->fixup[i]);
3758 if (loc && ((loc * 4) < rv2p_code_len)) {
3759 code = be32_to_cpu(*(rv2p_code + loc - 1));
3760 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3761 code = be32_to_cpu(*(rv2p_code + loc));
3762 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3763 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3764
3765 val = (loc / 2) | cmd;
3766 REG_WR(bp, addr, val);
b6016b76
MC		 3767 }
3768 }
3769
3770 /* Reset the processor, un-stall is done later. */
3771 if (rv2p_proc == RV2P_PROC1) {
3772 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3773 }
3774 else {
3775 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3776 }
57579f76
MC		 3777
3778 return 0;
b6016b76
MC		 3779}
3780
af3ee519 3781static int
57579f76
MC		 3782load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3783 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3784{
57579f76
MC		 3785 u32 addr, len, file_offset;
3786 __be32 *data;
b6016b76
MC		 3787 u32 offset;
3788 u32 val;
3789
3790 /* Halt the CPU. */
2726d6e1 3791 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3792 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3793 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3794 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3795
3796 /* Load the Text area. */
57579f76
MC		 3797 addr = be32_to_cpu(fw_entry->text.addr);
3798 len = be32_to_cpu(fw_entry->text.len);
3799 file_offset = be32_to_cpu(fw_entry->text.offset);
3800 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3801
57579f76
MC		 3802 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3803 if (len) {
b6016b76
MC		 3804 int j;
3805
57579f76
MC		 3806 for (j = 0; j < (len / 4); j++, offset += 4)
3807 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3808 }
3809
57579f76
MC		 3810 /* Load the Data area. */
3811 addr = be32_to_cpu(fw_entry->data.addr);
3812 len = be32_to_cpu(fw_entry->data.len);
3813 file_offset = be32_to_cpu(fw_entry->data.offset);
3814 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3815
57579f76
MC		 3816 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3817 if (len) {
b6016b76
MC		 3818 int j;
3819
57579f76
MC		 3820 for (j = 0; j < (len / 4); j++, offset += 4)
3821 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3822 }
3823
3824 /* Load the Read-Only area. */
57579f76
MC		 3825 addr = be32_to_cpu(fw_entry->rodata.addr);
3826 len = be32_to_cpu(fw_entry->rodata.len);
3827 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3828 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3829
3830 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3831 if (len) {
b6016b76
MC		 3832 int j;
3833
57579f76
MC		 3834 for (j = 0; j < (len / 4); j++, offset += 4)
3835 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3836 }
3837
3838 /* Clear the pre-fetch instruction. */
2726d6e1 3839 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3840
3841 val = be32_to_cpu(fw_entry->start_addr);
3842 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3843
3844 /* Start the CPU. */
2726d6e1 3845 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3846 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3847 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3848 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3849
3850 return 0;
b6016b76
MC		 3851}
3852
fba9fe91 3853static int
b6016b76
MC		 3854bnx2_init_cpus(struct bnx2 *bp)
3855{
57579f76
MC		 3856 const struct bnx2_mips_fw_file *mips_fw =
3857 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3858 const struct bnx2_rv2p_fw_file *rv2p_fw =
3859 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3860 int rc;
b6016b76
MC		 3861
3862 /* Initialize the RV2P processor. */
57579f76
MC		 3863 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3864 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3865
3866 /* Initialize the RX Processor. */
57579f76 3867 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3868 if (rc)
3869 goto init_cpu_err;
3870
b6016b76 3871 /* Initialize the TX Processor. */
57579f76 3872 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3873 if (rc)
3874 goto init_cpu_err;
3875
b6016b76 3876 /* Initialize the TX Patch-up Processor. */
57579f76 3877 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3878 if (rc)
3879 goto init_cpu_err;
3880
b6016b76 3881 /* Initialize the Completion Processor. */
57579f76 3882 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3883 if (rc)
3884 goto init_cpu_err;
3885
d43584c8 3886 /* Initialize the Command Processor. */
57579f76 3887 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3888
fba9fe91 3889init_cpu_err:
fba9fe91 3890 return rc;
b6016b76
MC		 3891}
3892
3893static int
829ca9a3 3894bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3895{
3896 u16 pmcsr;
3897
3898 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3899
3900 switch (state) {
829ca9a3 3901 case PCI_D0: {
b6016b76
MC		 3902 u32 val;
3903
3904 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3905 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3906 PCI_PM_CTRL_PME_STATUS);
3907
3908 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3909 /* delay required during transition out of D3hot */
3910 msleep(20);
3911
3912 val = REG_RD(bp, BNX2_EMAC_MODE);
3913 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3914 val &= ~BNX2_EMAC_MODE_MPKT;
3915 REG_WR(bp, BNX2_EMAC_MODE, val);
3916
3917 val = REG_RD(bp, BNX2_RPM_CONFIG);
3918 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3919 REG_WR(bp, BNX2_RPM_CONFIG, val);
3920 break;
3921 }
829ca9a3 3922 case PCI_D3hot: {
b6016b76
MC		 3923 int i;
3924 u32 val, wol_msg;
3925
3926 if (bp->wol) {
3927 u32 advertising;
3928 u8 autoneg;
3929
3930 autoneg = bp->autoneg;
3931 advertising = bp->advertising;
3932
239cd343
MC		 3933 if (bp->phy_port == PORT_TP) {
3934 bp->autoneg = AUTONEG_SPEED;
3935 bp->advertising = ADVERTISED_10baseT_Half |
3936 ADVERTISED_10baseT_Full |
3937 ADVERTISED_100baseT_Half |
3938 ADVERTISED_100baseT_Full |
3939 ADVERTISED_Autoneg;
3940 }
b6016b76 3941
239cd343
MC		 3942 spin_lock_bh(&bp->phy_lock);
3943 bnx2_setup_phy(bp, bp->phy_port);
3944 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3945
3946 bp->autoneg = autoneg;
3947 bp->advertising = advertising;
3948
5fcaed01 3949 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3950
3951 val = REG_RD(bp, BNX2_EMAC_MODE);
3952
3953 /* Enable port mode. */
3954 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3955 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3956 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3957 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3958 if (bp->phy_port == PORT_TP)
3959 val |= BNX2_EMAC_MODE_PORT_MII;
3960 else {
3961 val |= BNX2_EMAC_MODE_PORT_GMII;
3962 if (bp->line_speed == SPEED_2500)
3963 val |= BNX2_EMAC_MODE_25G_MODE;
3964 }
b6016b76
MC		 3965
3966 REG_WR(bp, BNX2_EMAC_MODE, val);
3967
3968 /* receive all multicast */
3969 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3970 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3971 0xffffffff);
3972 }
3973 REG_WR(bp, BNX2_EMAC_RX_MODE,
3974 BNX2_EMAC_RX_MODE_SORT_MODE);
3975
3976 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3977 BNX2_RPM_SORT_USER0_MC_EN;
3978 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3979 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3980 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3981 BNX2_RPM_SORT_USER0_ENA);
3982
3983 /* Need to enable EMAC and RPM for WOL. */
3984 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3985 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3986 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3987 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3988
3989 val = REG_RD(bp, BNX2_RPM_CONFIG);
3990 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3991 REG_WR(bp, BNX2_RPM_CONFIG, val);
3992
3993 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3994 }
3995 else {
3996 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3997 }
3998
f86e82fb 3999 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 4000 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
4001 1, 0);
b6016b76
MC		 4002
4003 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4004 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4005 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4006
4007 if (bp->wol)
4008 pmcsr |= 3;
4009 }
4010 else {
4011 pmcsr |= 3;
4012 }
4013 if (bp->wol) {
4014 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4015 }
4016 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4017 pmcsr);
4018
4019 /* No more memory access after this point until
4020 * device is brought back to D0.
4021 */
4022 udelay(50);
4023 break;
4024 }
4025 default:
4026 return -EINVAL;
4027 }
4028 return 0;
4029}
4030
4031static int
4032bnx2_acquire_nvram_lock(struct bnx2 *bp)
4033{
4034 u32 val;
4035 int j;
4036
4037 /* Request access to the flash interface. */
4038 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4039 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4040 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4041 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4042 break;
4043
4044 udelay(5);
4045 }
4046
4047 if (j >= NVRAM_TIMEOUT_COUNT)
4048 return -EBUSY;
4049
4050 return 0;
4051}
4052
4053static int
4054bnx2_release_nvram_lock(struct bnx2 *bp)
4055{
4056 int j;
4057 u32 val;
4058
4059 /* Relinquish nvram interface. */
4060 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4061
4062 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4063 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4064 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4065 break;
4066
4067 udelay(5);
4068 }
4069
4070 if (j >= NVRAM_TIMEOUT_COUNT)
4071 return -EBUSY;
4072
4073 return 0;
4074}
4075
4076
4077static int
4078bnx2_enable_nvram_write(struct bnx2 *bp)
4079{
4080 u32 val;
4081
4082 val = REG_RD(bp, BNX2_MISC_CFG);
4083 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4084
e30372c9 4085 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4086 int j;
4087
4088 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4089 REG_WR(bp, BNX2_NVM_COMMAND,
4090 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4091
4092 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4093 udelay(5);
4094
4095 val = REG_RD(bp, BNX2_NVM_COMMAND);
4096 if (val & BNX2_NVM_COMMAND_DONE)
4097 break;
4098 }
4099
4100 if (j >= NVRAM_TIMEOUT_COUNT)
4101 return -EBUSY;
4102 }
4103 return 0;
4104}
4105
4106static void
4107bnx2_disable_nvram_write(struct bnx2 *bp)
4108{
4109 u32 val;
4110
4111 val = REG_RD(bp, BNX2_MISC_CFG);
4112 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4113}
4114
4115
4116static void
4117bnx2_enable_nvram_access(struct bnx2 *bp)
4118{
4119 u32 val;
4120
4121 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4122 /* Enable both bits, even on read. */
6aa20a22 4123 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4124 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4125}
4126
4127static void
4128bnx2_disable_nvram_access(struct bnx2 *bp)
4129{
4130 u32 val;
4131
4132 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4133 /* Disable both bits, even after read. */
6aa20a22 4134 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4135 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4136 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4137}
4138
4139static int
4140bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4141{
4142 u32 cmd;
4143 int j;
4144
e30372c9 4145 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4146 /* Buffered flash, no erase needed */
4147 return 0;
4148
4149 /* Build an erase command */
4150 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4151 BNX2_NVM_COMMAND_DOIT;
4152
4153 /* Need to clear DONE bit separately. */
4154 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4155
4156 /* Address of the NVRAM to read from. */
4157 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4158
4159 /* Issue an erase command. */
4160 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4161
4162 /* Wait for completion. */
4163 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4164 u32 val;
4165
4166 udelay(5);
4167
4168 val = REG_RD(bp, BNX2_NVM_COMMAND);
4169 if (val & BNX2_NVM_COMMAND_DONE)
4170 break;
4171 }
4172
4173 if (j >= NVRAM_TIMEOUT_COUNT)
4174 return -EBUSY;
4175
4176 return 0;
4177}
4178
4179static int
4180bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4181{
4182 u32 cmd;
4183 int j;
4184
4185 /* Build the command word. */
4186 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4187
e30372c9
MC		 4188 /* Calculate an offset of a buffered flash, not needed for 5709. */
4189 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4190 offset = ((offset / bp->flash_info->page_size) <<
4191 bp->flash_info->page_bits) +
4192 (offset % bp->flash_info->page_size);
4193 }
4194
4195 /* Need to clear DONE bit separately. */
4196 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4197
4198 /* Address of the NVRAM to read from. */
4199 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4200
4201 /* Issue a read command. */
4202 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4203
4204 /* Wait for completion. */
4205 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4206 u32 val;
4207
4208 udelay(5);
4209
4210 val = REG_RD(bp, BNX2_NVM_COMMAND);
4211 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 4212 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4213 memcpy(ret_val, &v, 4);
b6016b76
MC		 4214 break;
4215 }
4216 }
4217 if (j >= NVRAM_TIMEOUT_COUNT)
4218 return -EBUSY;
4219
4220 return 0;
4221}
4222
4223
4224static int
4225bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4226{
b491edd5
AV		 4227 u32 cmd;
4228 __be32 val32;
b6016b76
MC		 4229 int j;
4230
4231 /* Build the command word. */
4232 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4233
e30372c9
MC		 4234 /* Calculate an offset of a buffered flash, not needed for 5709. */
4235 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4236 offset = ((offset / bp->flash_info->page_size) <<
4237 bp->flash_info->page_bits) +
4238 (offset % bp->flash_info->page_size);
4239 }
4240
4241 /* Need to clear DONE bit separately. */
4242 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4243
4244 memcpy(&val32, val, 4);
b6016b76
MC		 4245
4246 /* Write the data. */
b491edd5 4247 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4248
4249 /* Address of the NVRAM to write to. */
4250 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4251
4252 /* Issue the write command. */
4253 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4254
4255 /* Wait for completion. */
4256 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4257 udelay(5);
4258
4259 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4260 break;
4261 }
4262 if (j >= NVRAM_TIMEOUT_COUNT)
4263 return -EBUSY;
4264
4265 return 0;
4266}
4267
4268static int
4269bnx2_init_nvram(struct bnx2 *bp)
4270{
4271 u32 val;
e30372c9 4272 int j, entry_count, rc = 0;
0ced9d01 4273 const struct flash_spec *flash;
b6016b76 4274
e30372c9
MC		 4275 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4276 bp->flash_info = &flash_5709;
4277 goto get_flash_size;
4278 }
4279
b6016b76
MC		 4280 /* Determine the selected interface. */
4281 val = REG_RD(bp, BNX2_NVM_CFG1);
4282
ff8ac609 4283 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4284
b6016b76
MC		 4285 if (val & 0x40000000) {
4286
4287 /* Flash interface has been reconfigured */
4288 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4289 j++, flash++) {
4290 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4291 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4292 bp->flash_info = flash;
4293 break;
4294 }
4295 }
4296 }
4297 else {
37137709 4298 u32 mask;
b6016b76
MC		 4299 /* Not yet been reconfigured */
4300
37137709
MC		 4301 if (val & (1 << 23))
4302 mask = FLASH_BACKUP_STRAP_MASK;
4303 else
4304 mask = FLASH_STRAP_MASK;
4305
b6016b76
MC		 4306 for (j = 0, flash = &flash_table[0]; j < entry_count;
4307 j++, flash++) {
4308
37137709 4309 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4310 bp->flash_info = flash;
4311
4312 /* Request access to the flash interface. */
4313 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4314 return rc;
4315
4316 /* Enable access to flash interface */
4317 bnx2_enable_nvram_access(bp);
4318
4319 /* Reconfigure the flash interface */
4320 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4321 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4322 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4323 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4324
4325 /* Disable access to flash interface */
4326 bnx2_disable_nvram_access(bp);
4327 bnx2_release_nvram_lock(bp);
4328
4329 break;
4330 }
4331 }
4332 } /* if (val & 0x40000000) */
4333
4334 if (j == entry_count) {
4335 bp->flash_info = NULL;
3a9c6a49 4336 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4337 return -ENODEV;
b6016b76
MC		 4338 }
4339
e30372c9 4340get_flash_size:
2726d6e1 4341 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4342 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4343 if (val)
4344 bp->flash_size = val;
4345 else
4346 bp->flash_size = bp->flash_info->total_size;
4347
b6016b76
MC		 4348 return rc;
4349}
4350
4351static int
4352bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4353 int buf_size)
4354{
4355 int rc = 0;
4356 u32 cmd_flags, offset32, len32, extra;
4357
4358 if (buf_size == 0)
4359 return 0;
4360
4361 /* Request access to the flash interface. */
4362 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4363 return rc;
4364
4365 /* Enable access to flash interface */
4366 bnx2_enable_nvram_access(bp);
4367
4368 len32 = buf_size;
4369 offset32 = offset;
4370 extra = 0;
4371
4372 cmd_flags = 0;
4373
4374 if (offset32 & 3) {
4375 u8 buf[4];
4376 u32 pre_len;
4377
4378 offset32 &= ~3;
4379 pre_len = 4 - (offset & 3);
4380
4381 if (pre_len >= len32) {
4382 pre_len = len32;
4383 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4384 BNX2_NVM_COMMAND_LAST;
4385 }
4386 else {
4387 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4388 }
4389
4390 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4391
4392 if (rc)
4393 return rc;
4394
4395 memcpy(ret_buf, buf + (offset & 3), pre_len);
4396
4397 offset32 += 4;
4398 ret_buf += pre_len;
4399 len32 -= pre_len;
4400 }
4401 if (len32 & 3) {
4402 extra = 4 - (len32 & 3);
4403 len32 = (len32 + 4) & ~3;
4404 }
4405
4406 if (len32 == 4) {
4407 u8 buf[4];
4408
4409 if (cmd_flags)
4410 cmd_flags = BNX2_NVM_COMMAND_LAST;
4411 else
4412 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4413 BNX2_NVM_COMMAND_LAST;
4414
4415 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4416
4417 memcpy(ret_buf, buf, 4 - extra);
4418 }
4419 else if (len32 > 0) {
4420 u8 buf[4];
4421
4422 /* Read the first word. */
4423 if (cmd_flags)
4424 cmd_flags = 0;
4425 else
4426 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4427
4428 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4429
4430 /* Advance to the next dword. */
4431 offset32 += 4;
4432 ret_buf += 4;
4433 len32 -= 4;
4434
4435 while (len32 > 4 && rc == 0) {
4436 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4437
4438 /* Advance to the next dword. */
4439 offset32 += 4;
4440 ret_buf += 4;
4441 len32 -= 4;
4442 }
4443
4444 if (rc)
4445 return rc;
4446
4447 cmd_flags = BNX2_NVM_COMMAND_LAST;
4448 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4449
4450 memcpy(ret_buf, buf, 4 - extra);
4451 }
4452
4453 /* Disable access to flash interface */
4454 bnx2_disable_nvram_access(bp);
4455
4456 bnx2_release_nvram_lock(bp);
4457
4458 return rc;
4459}
4460
4461static int
4462bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4463 int buf_size)
4464{
4465 u32 written, offset32, len32;
e6be763f 4466 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4467 int rc = 0;
4468 int align_start, align_end;
4469
4470 buf = data_buf;
4471 offset32 = offset;
4472 len32 = buf_size;
4473 align_start = align_end = 0;
4474
4475 if ((align_start = (offset32 & 3))) {
4476 offset32 &= ~3;
c873879c
MC		 4477 len32 += align_start;
4478 if (len32 < 4)
4479 len32 = 4;
b6016b76
MC		 4480 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4481 return rc;
4482 }
4483
4484 if (len32 & 3) {
c873879c
MC		 4485 align_end = 4 - (len32 & 3);
4486 len32 += align_end;
4487 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4488 return rc;
b6016b76
MC		 4489 }
4490
4491 if (align_start || align_end) {
e6be763f
MC		 4492 align_buf = kmalloc(len32, GFP_KERNEL);
4493 if (align_buf == NULL)
b6016b76
MC		 4494 return -ENOMEM;
4495 if (align_start) {
e6be763f 4496 memcpy(align_buf, start, 4);
b6016b76
MC		 4497 }
4498 if (align_end) {
e6be763f 4499 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4500 }
e6be763f
MC		 4501 memcpy(align_buf + align_start, data_buf, buf_size);
4502 buf = align_buf;
b6016b76
MC		 4503 }
4504
e30372c9 4505 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4506 flash_buffer = kmalloc(264, GFP_KERNEL);
4507 if (flash_buffer == NULL) {
4508 rc = -ENOMEM;
4509 goto nvram_write_end;
4510 }
4511 }
4512
b6016b76
MC		 4513 written = 0;
4514 while ((written < len32) && (rc == 0)) {
4515 u32 page_start, page_end, data_start, data_end;
4516 u32 addr, cmd_flags;
4517 int i;
b6016b76
MC		 4518
4519 /* Find the page_start addr */
4520 page_start = offset32 + written;
4521 page_start -= (page_start % bp->flash_info->page_size);
4522 /* Find the page_end addr */
4523 page_end = page_start + bp->flash_info->page_size;
4524 /* Find the data_start addr */
4525 data_start = (written == 0) ? offset32 : page_start;
4526 /* Find the data_end addr */
6aa20a22 4527 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4528 (offset32 + len32) : page_end;
4529
4530 /* Request access to the flash interface. */
4531 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4532 goto nvram_write_end;
4533
4534 /* Enable access to flash interface */
4535 bnx2_enable_nvram_access(bp);
4536
4537 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4538 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4539 int j;
4540
4541 /* Read the whole page into the buffer
4542 * (non-buffer flash only) */
4543 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4544 if (j == (bp->flash_info->page_size - 4)) {
4545 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4546 }
4547 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4548 page_start + j,
4549 &flash_buffer[j],
b6016b76
MC		 4550 cmd_flags);
4551
4552 if (rc)
4553 goto nvram_write_end;
4554
4555 cmd_flags = 0;
4556 }
4557 }
4558
4559 /* Enable writes to flash interface (unlock write-protect) */
4560 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4561 goto nvram_write_end;
4562
b6016b76
MC		 4563 /* Loop to write back the buffer data from page_start to
4564 * data_start */
4565 i = 0;
e30372c9 4566 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4567 /* Erase the page */
4568 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4569 goto nvram_write_end;
4570
4571 /* Re-enable the write again for the actual write */
4572 bnx2_enable_nvram_write(bp);
4573
b6016b76
MC		 4574 for (addr = page_start; addr < data_start;
4575 addr += 4, i += 4) {
6aa20a22 4576
b6016b76
MC		 4577 rc = bnx2_nvram_write_dword(bp, addr,
4578 &flash_buffer[i], cmd_flags);
4579
4580 if (rc != 0)
4581 goto nvram_write_end;
4582
4583 cmd_flags = 0;
4584 }
4585 }
4586
4587 /* Loop to write the new data from data_start to data_end */
bae25761 4588 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4589 if ((addr == page_end - 4) ||
e30372c9 4590 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4591 (addr == data_end - 4))) {
4592
4593 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4594 }
4595 rc = bnx2_nvram_write_dword(bp, addr, buf,
4596 cmd_flags);
4597
4598 if (rc != 0)
4599 goto nvram_write_end;
4600
4601 cmd_flags = 0;
4602 buf += 4;
4603 }
4604
4605 /* Loop to write back the buffer data from data_end
4606 * to page_end */
e30372c9 4607 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4608 for (addr = data_end; addr < page_end;
4609 addr += 4, i += 4) {
6aa20a22 4610
b6016b76
MC		 4611 if (addr == page_end-4) {
4612 cmd_flags = BNX2_NVM_COMMAND_LAST;
4613 }
4614 rc = bnx2_nvram_write_dword(bp, addr,
4615 &flash_buffer[i], cmd_flags);
4616
4617 if (rc != 0)
4618 goto nvram_write_end;
4619
4620 cmd_flags = 0;
4621 }
4622 }
4623
4624 /* Disable writes to flash interface (lock write-protect) */
4625 bnx2_disable_nvram_write(bp);
4626
4627 /* Disable access to flash interface */
4628 bnx2_disable_nvram_access(bp);
4629 bnx2_release_nvram_lock(bp);
4630
4631 /* Increment written */
4632 written += data_end - data_start;
4633 }
4634
4635nvram_write_end:
e6be763f
MC		 4636 kfree(flash_buffer);
4637 kfree(align_buf);
b6016b76
MC		 4638 return rc;
4639}
4640
0d8a6571 4641static void
7c62e83b 4642bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4643{
7c62e83b 4644 u32 val, sig = 0;
0d8a6571 4645
583c28e5 4646 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4647 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4648
4649 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4650 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4651
2726d6e1 4652 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4653 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4654 return;
4655
7c62e83b
MC		 4656 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4657 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4658 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4659 }
4660
4661 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4662 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4663 u32 link;
4664
583c28e5 4665 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4666
7c62e83b
MC		 4667 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4668 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4669 bp->phy_port = PORT_FIBRE;
4670 else
4671 bp->phy_port = PORT_TP;
489310a4 4672
7c62e83b
MC		 4673 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4674 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4675 }
7c62e83b
MC		 4676
4677 if (netif_running(bp->dev) && sig)
4678 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4679}
4680
b4b36042
MC		 4681static void
4682bnx2_setup_msix_tbl(struct bnx2 *bp)
4683{
4684 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4685
4686 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4687 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4688}
4689
b6016b76
MC		 4690static int
4691bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4692{
4693 u32 val;
4694 int i, rc = 0;
489310a4 4695 u8 old_port;
b6016b76
MC		 4696
4697 /* Wait for the current PCI transaction to complete before
4698 * issuing a reset. */
4699 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4700 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4701 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4702 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4703 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4704 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4705 udelay(5);
4706
b090ae2b 4707 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4708 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4709
b6016b76
MC		 4710 /* Deposit a driver reset signature so the firmware knows that
4711 * this is a soft reset. */
2726d6e1
MC		 4712 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4713 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4714
b6016b76
MC		 4715 /* Do a dummy read to force the chip to complete all current transaction
4716 * before we issue a reset. */
4717 val = REG_RD(bp, BNX2_MISC_ID);
4718
234754d5
MC		 4719 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4720 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4721 REG_RD(bp, BNX2_MISC_COMMAND);
4722 udelay(5);
b6016b76 4723
234754d5
MC		 4724 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4725 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4726
234754d5 4727 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4728
234754d5
MC		 4729 } else {
4730 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4731 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4732 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4733
4734 /* Chip reset. */
4735 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4736
594a9dfa
MC		 4737 /* Reading back any register after chip reset will hang the
4738 * bus on 5706 A0 and A1. The msleep below provides plenty
4739 * of margin for write posting.
4740 */
234754d5 4741 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4742 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4743 msleep(20);
b6016b76 4744
234754d5
MC		 4745 /* Reset takes approximate 30 usec */
4746 for (i = 0; i < 10; i++) {
4747 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4748 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4749 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4750 break;
4751 udelay(10);
4752 }
4753
4754 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4755 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4756 pr_err("Chip reset did not complete\n");
234754d5
MC		 4757 return -EBUSY;
4758 }
b6016b76
MC		 4759 }
4760
4761 /* Make sure byte swapping is properly configured. */
4762 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4763 if (val != 0x01020304) {
3a9c6a49 4764 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4765 return -ENODEV;
4766 }
4767
b6016b76 4768 /* Wait for the firmware to finish its initialization. */
a2f13890 4769 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4770 if (rc)
4771 return rc;
b6016b76 4772
0d8a6571 4773 spin_lock_bh(&bp->phy_lock);
489310a4 4774 old_port = bp->phy_port;
7c62e83b 4775 bnx2_init_fw_cap(bp);
583c28e5
MC		 4776 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4777 old_port != bp->phy_port)
0d8a6571
MC		 4778 bnx2_set_default_remote_link(bp);
4779 spin_unlock_bh(&bp->phy_lock);
4780
b6016b76
MC		 4781 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4782 /* Adjust the voltage regular to two steps lower. The default
4783 * of this register is 0x0000000e. */
4784 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4785
4786 /* Remove bad rbuf memory from the free pool. */
4787 rc = bnx2_alloc_bad_rbuf(bp);
4788 }
4789
c441b8d2 4790 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4791 bnx2_setup_msix_tbl(bp);
c441b8d2
MC		 4792 /* Prevent MSIX table reads and write from timing out */
4793 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4794 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4795 }
b4b36042 4796
b6016b76
MC		 4797 return rc;
4798}
4799
4800static int
4801bnx2_init_chip(struct bnx2 *bp)
4802{
d8026d93 4803 u32 val, mtu;
b4b36042 4804 int rc, i;
b6016b76
MC		 4805
4806 /* Make sure the interrupt is not active. */
4807 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4808
4809 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4810 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4811#ifdef __BIG_ENDIAN
6aa20a22 4812 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4813#endif
6aa20a22 4814 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4815 DMA_READ_CHANS << 12 |
4816 DMA_WRITE_CHANS << 16;
4817
4818 val |= (0x2 << 20) | (1 << 11);
4819
f86e82fb 4820 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4821 val |= (1 << 23);
4822
4823 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4824 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4825 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4826
4827 REG_WR(bp, BNX2_DMA_CONFIG, val);
4828
4829 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4830 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4831 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4832 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4833 }
4834
f86e82fb 4835 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4836 u16 val16;
4837
4838 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4839 &val16);
4840 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4841 val16 & ~PCI_X_CMD_ERO);
4842 }
4843
4844 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4845 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4846 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4847 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4848
4849 /* Initialize context mapping and zero out the quick contexts. The
4850 * context block must have already been enabled. */
641bdcd5
MC		 4851 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4852 rc = bnx2_init_5709_context(bp);
4853 if (rc)
4854 return rc;
4855 } else
59b47d8a 4856 bnx2_init_context(bp);
b6016b76 4857
fba9fe91
MC		 4858 if ((rc = bnx2_init_cpus(bp)) != 0)
4859 return rc;
4860
b6016b76
MC		 4861 bnx2_init_nvram(bp);
4862
5fcaed01 4863 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4864
4865 val = REG_RD(bp, BNX2_MQ_CONFIG);
4866 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4867 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4edd473f
MC		 4868 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4869 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4870 if (CHIP_REV(bp) == CHIP_REV_Ax)
4871 val |= BNX2_MQ_CONFIG_HALT_DIS;
4872 }
68c9f75a 4873
b6016b76
MC		 4874 REG_WR(bp, BNX2_MQ_CONFIG, val);
4875
4876 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4877 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4878 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4879
4880 val = (BCM_PAGE_BITS - 8) << 24;
4881 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4882
4883 /* Configure page size. */
4884 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4885 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4886 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4887 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4888
4889 val = bp->mac_addr[0] +
4890 (bp->mac_addr[1] << 8) +
4891 (bp->mac_addr[2] << 16) +
4892 bp->mac_addr[3] +
4893 (bp->mac_addr[4] << 8) +
4894 (bp->mac_addr[5] << 16);
4895 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4896
4897 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4898 mtu = bp->dev->mtu;
4899 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4900 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4901 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4902 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4903
d8026d93
MC		 4904 if (mtu < 1500)
4905 mtu = 1500;
4906
4907 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4908 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4909 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4910
155d5561 4911 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4912 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4913 bp->bnx2_napi[i].last_status_idx = 0;
4914
efba0180
MC		 4915 bp->idle_chk_status_idx = 0xffff;
4916
b6016b76
MC		 4917 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4918
4919 /* Set up how to generate a link change interrupt. */
4920 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4921
4922 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4923 (u64) bp->status_blk_mapping & 0xffffffff);
4924 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4925
4926 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4927 (u64) bp->stats_blk_mapping & 0xffffffff);
4928 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4929 (u64) bp->stats_blk_mapping >> 32);
4930
6aa20a22 4931 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4932 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4933
4934 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4935 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4936
4937 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4938 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4939
4940 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4941
4942 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4943
4944 REG_WR(bp, BNX2_HC_COM_TICKS,
4945 (bp->com_ticks_int << 16) | bp->com_ticks);
4946
4947 REG_WR(bp, BNX2_HC_CMD_TICKS,
4948 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4949
61d9e3fa 4950 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
02537b06
MC		 4951 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4952 else
7ea6920e 4953 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4954 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4955
4956 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4957 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4958 else {
8e6a72c4
MC		 4959 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4960 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4961 }
4962
efde73a3 4963 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4964 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4965 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4966
5e9ad9e1
MC		 4967 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4968 }
4969
4970 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 4971 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1
MC		 4972
4973 REG_WR(bp, BNX2_HC_CONFIG, val);
4974
4975 for (i = 1; i < bp->irq_nvecs; i++) {
4976 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4977 BNX2_HC_SB_CONFIG_1;
4978
6f743ca0 4979 REG_WR(bp, base,
c76c0475 4980 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 4981 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 4982 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4983
6f743ca0 4984 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4985 (bp->tx_quick_cons_trip_int << 16) |
4986 bp->tx_quick_cons_trip);
4987
6f743ca0 4988 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4989 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4990
5e9ad9e1
MC		 4991 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4992 (bp->rx_quick_cons_trip_int << 16) |
4993 bp->rx_quick_cons_trip);
8e6a72c4 4994
5e9ad9e1
MC		 4995 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4996 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4997 }
8e6a72c4 4998
b6016b76
MC		 4999 /* Clear internal stats counters. */
5000 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5001
da3e4fbe 5002 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 5003
5004 /* Initialize the receive filter. */
5005 bnx2_set_rx_mode(bp->dev);
5006
0aa38df7
MC		 5007 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5008 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5009 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5010 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5011 }
b090ae2b 5012 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5013 1, 0);
b6016b76 5014
df149d70 5015 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 5016 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5017
5018 udelay(20);
5019
bf5295bb
MC		 5020 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5021
b090ae2b 5022 return rc;
b6016b76
MC		 5023}
5024
c76c0475
MC		 5025static void
5026bnx2_clear_ring_states(struct bnx2 *bp)
5027{
5028 struct bnx2_napi *bnapi;
35e9010b 5029 struct bnx2_tx_ring_info *txr;
bb4f98ab 5030 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5031 int i;
5032
5033 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5034 bnapi = &bp->bnx2_napi[i];
35e9010b 5035 txr = &bnapi->tx_ring;
bb4f98ab 5036 rxr = &bnapi->rx_ring;
c76c0475 5037
35e9010b
MC		 5038 txr->tx_cons = 0;
5039 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5040 rxr->rx_prod_bseq = 0;
5041 rxr->rx_prod = 0;
5042 rxr->rx_cons = 0;
5043 rxr->rx_pg_prod = 0;
5044 rxr->rx_pg_cons = 0;
c76c0475
MC		 5045 }
5046}
5047
59b47d8a 5048static void
35e9010b 5049bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5050{
5051 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5052 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 5053
5054 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5055 offset0 = BNX2_L2CTX_TYPE_XI;
5056 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5057 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5058 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5059 } else {
5060 offset0 = BNX2_L2CTX_TYPE;
5061 offset1 = BNX2_L2CTX_CMD_TYPE;
5062 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5063 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5064 }
5065 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5066 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5067
5068 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5069 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5070
35e9010b 5071 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5072 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5073
35e9010b 5074 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5075 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5076}
b6016b76
MC		 5077
5078static void
35e9010b 5079bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 5080{
5081 struct tx_bd *txbd;
c76c0475
MC		 5082 u32 cid = TX_CID;
5083 struct bnx2_napi *bnapi;
35e9010b 5084 struct bnx2_tx_ring_info *txr;
c76c0475 5085
35e9010b
MC		 5086 bnapi = &bp->bnx2_napi[ring_num];
5087 txr = &bnapi->tx_ring;
5088
5089 if (ring_num == 0)
5090 cid = TX_CID;
5091 else
5092 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5093
2f8af120
MC		 5094 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5095
35e9010b 5096 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 5097
35e9010b
MC		 5098 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5099 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5100
35e9010b
MC		 5101 txr->tx_prod = 0;
5102 txr->tx_prod_bseq = 0;
6aa20a22 5103
35e9010b
MC		 5104 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5105 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5106
35e9010b 5107 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5108}
5109
5110static void
5d5d0015
MC		 5111bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5112 int num_rings)
b6016b76 5113{
b6016b76 5114 int i;
5d5d0015 5115 struct rx_bd *rxbd;
6aa20a22 5116
5d5d0015 5117 for (i = 0; i < num_rings; i++) {
13daffa2 5118 int j;
b6016b76 5119
5d5d0015 5120 rxbd = &rx_ring[i][0];
13daffa2 5121 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5122 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5123 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5124 }
5d5d0015 5125 if (i == (num_rings - 1))
13daffa2
MC		 5126 j = 0;
5127 else
5128 j = i + 1;
5d5d0015
MC		 5129 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5130 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5131 }
5d5d0015
MC		 5132}
5133
5134static void
bb4f98ab 5135bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5136{
5137 int i;
5138 u16 prod, ring_prod;
bb4f98ab
MC		 5139 u32 cid, rx_cid_addr, val;
5140 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5141 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5142
5143 if (ring_num == 0)
5144 cid = RX_CID;
5145 else
5146 cid = RX_RSS_CID + ring_num - 1;
5147
5148 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5149
bb4f98ab 5150 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5151 bp->rx_buf_use_size, bp->rx_max_ring);
5152
bb4f98ab 5153 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 5154
5155 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5156 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5157 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5158 }
5159
62a8313c 5160 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5161 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5162 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5163 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5164 PAGE_SIZE, bp->rx_max_pg_ring);
5165 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5166 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5167 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5168 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5169
bb4f98ab 5170 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5171 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5172
bb4f98ab 5173 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5174 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 5175
5176 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5177 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5178 }
b6016b76 5179
bb4f98ab 5180 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5181 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5182
bb4f98ab 5183 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5184 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5185
bb4f98ab 5186 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5187 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5188 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5189 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5190 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5191 break;
b929e53c 5192 }
47bf4246
MC		 5193 prod = NEXT_RX_BD(prod);
5194 ring_prod = RX_PG_RING_IDX(prod);
5195 }
bb4f98ab 5196 rxr->rx_pg_prod = prod;
47bf4246 5197
bb4f98ab 5198 ring_prod = prod = rxr->rx_prod;
236b6394 5199 for (i = 0; i < bp->rx_ring_size; i++) {
a2df00aa 5200 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5201 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5202 ring_num, i, bp->rx_ring_size);
b6016b76 5203 break;
b929e53c 5204 }
b6016b76
MC		 5205 prod = NEXT_RX_BD(prod);
5206 ring_prod = RX_RING_IDX(prod);
5207 }
bb4f98ab 5208 rxr->rx_prod = prod;
b6016b76 5209
bb4f98ab
MC		 5210 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5211 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5212 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5213
bb4f98ab
MC		 5214 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5215 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5216
5217 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5218}
5219
35e9010b
MC		 5220static void
5221bnx2_init_all_rings(struct bnx2 *bp)
5222{
5223 int i;
5e9ad9e1 5224 u32 val;
35e9010b
MC		 5225
5226 bnx2_clear_ring_states(bp);
5227
5228 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5229 for (i = 0; i < bp->num_tx_rings; i++)
5230 bnx2_init_tx_ring(bp, i);
5231
5232 if (bp->num_tx_rings > 1)
5233 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5234 (TX_TSS_CID << 7));
5235
5e9ad9e1
MC		 5236 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5237 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5238
bb4f98ab
MC		 5239 for (i = 0; i < bp->num_rx_rings; i++)
5240 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5241
5242 if (bp->num_rx_rings > 1) {
5243 u32 tbl_32;
5244 u8 *tbl = (u8 *) &tbl_32;
5245
5246 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5247 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5248
5249 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5250 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5251 if ((i % 4) == 3)
5252 bnx2_reg_wr_ind(bp,
5253 BNX2_RXP_SCRATCH_RSS_TBL + i,
5254 cpu_to_be32(tbl_32));
5255 }
5256
5257 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5258 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5259
5260 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5261
5262 }
35e9010b
MC		 5263}
5264
5d5d0015 5265static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5266{
5d5d0015 5267 u32 max, num_rings = 1;
13daffa2 5268
5d5d0015
MC		 5269 while (ring_size > MAX_RX_DESC_CNT) {
5270 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 5271 num_rings++;
5272 }
5273 /* round to next power of 2 */
5d5d0015 5274 max = max_size;
13daffa2
MC		 5275 while ((max & num_rings) == 0)
5276 max >>= 1;
5277
5278 if (num_rings != max)
5279 max <<= 1;
5280
5d5d0015
MC		 5281 return max;
5282}
5283
5284static void
5285bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5286{
84eaa187 5287 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5288
5289 /* 8 for CRC and VLAN */
d89cb6af 5290 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5291
84eaa187
MC		 5292 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5293 sizeof(struct skb_shared_info);
5294
601d3d18 5295 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5296 bp->rx_pg_ring_size = 0;
5297 bp->rx_max_pg_ring = 0;
5298 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5299 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5300 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5301
5302 jumbo_size = size * pages;
5303 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5304 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5305
5306 bp->rx_pg_ring_size = jumbo_size;
5307 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5308 MAX_RX_PG_RINGS);
5309 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 5310 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5311 bp->rx_copy_thresh = 0;
5312 }
5d5d0015
MC		 5313
5314 bp->rx_buf_use_size = rx_size;
5315 /* hw alignment */
5316 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 5317 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 5318 bp->rx_ring_size = size;
5319 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 5320 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5321}
5322
b6016b76
MC		 5323static void
5324bnx2_free_tx_skbs(struct bnx2 *bp)
5325{
5326 int i;
5327
35e9010b
MC		 5328 for (i = 0; i < bp->num_tx_rings; i++) {
5329 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5330 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5331 int j;
b6016b76 5332
35e9010b 5333 if (txr->tx_buf_ring == NULL)
b6016b76 5334 continue;
b6016b76 5335
35e9010b 5336 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5337 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5338 struct sk_buff *skb = tx_buf->skb;
e95524a7 5339 int k, last;
35e9010b
MC		 5340
5341 if (skb == NULL) {
5342 j++;
5343 continue;
5344 }
5345
36227e88 5346 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5347 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5348 skb_headlen(skb),
5349 PCI_DMA_TODEVICE);
b6016b76 5350
35e9010b 5351 tx_buf->skb = NULL;
b6016b76 5352
e95524a7
AD		 5353 last = tx_buf->nr_frags;
5354 j++;
5355 for (k = 0; k < last; k++, j++) {
5356 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
36227e88 5357 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5358 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5359 skb_shinfo(skb)->frags[k].size,
5360 PCI_DMA_TODEVICE);
5361 }
35e9010b 5362 dev_kfree_skb(skb);
b6016b76 5363 }
b6016b76 5364 }
b6016b76
MC		 5365}
5366
5367static void
5368bnx2_free_rx_skbs(struct bnx2 *bp)
5369{
5370 int i;
5371
bb4f98ab
MC		 5372 for (i = 0; i < bp->num_rx_rings; i++) {
5373 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5374 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5375 int j;
b6016b76 5376
bb4f98ab
MC		 5377 if (rxr->rx_buf_ring == NULL)
5378 return;
b6016b76 5379
bb4f98ab
MC		 5380 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5381 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5382 struct sk_buff *skb = rx_buf->skb;
b6016b76 5383
bb4f98ab
MC		 5384 if (skb == NULL)
5385 continue;
b6016b76 5386
36227e88 5387 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5388 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5389 bp->rx_buf_use_size,
5390 PCI_DMA_FROMDEVICE);
b6016b76 5391
bb4f98ab
MC		 5392 rx_buf->skb = NULL;
5393
5394 dev_kfree_skb(skb);
5395 }
5396 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5397 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5398 }
5399}
5400
5401static void
5402bnx2_free_skbs(struct bnx2 *bp)
5403{
5404 bnx2_free_tx_skbs(bp);
5405 bnx2_free_rx_skbs(bp);
5406}
5407
5408static int
5409bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5410{
5411 int rc;
5412
5413 rc = bnx2_reset_chip(bp, reset_code);
5414 bnx2_free_skbs(bp);
5415 if (rc)
5416 return rc;
5417
fba9fe91
MC		 5418 if ((rc = bnx2_init_chip(bp)) != 0)
5419 return rc;
5420
35e9010b 5421 bnx2_init_all_rings(bp);
b6016b76
MC		 5422 return 0;
5423}
5424
5425static int
9a120bc5 5426bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5427{
5428 int rc;
5429
5430 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5431 return rc;
5432
80be4434 5433 spin_lock_bh(&bp->phy_lock);
9a120bc5 5434 bnx2_init_phy(bp, reset_phy);
b6016b76 5435 bnx2_set_link(bp);
543a827d
MC		 5436 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5437 bnx2_remote_phy_event(bp);
0d8a6571 5438 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5439 return 0;
5440}
5441
74bf4ba3
MC		 5442static int
5443bnx2_shutdown_chip(struct bnx2 *bp)
5444{
5445 u32 reset_code;
5446
5447 if (bp->flags & BNX2_FLAG_NO_WOL)
5448 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5449 else if (bp->wol)
5450 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5451 else
5452 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5453
5454 return bnx2_reset_chip(bp, reset_code);
5455}
5456
b6016b76
MC		 5457static int
5458bnx2_test_registers(struct bnx2 *bp)
5459{
5460 int ret;
5bae30c9 5461 int i, is_5709;
f71e1309 5462 static const struct {
b6016b76
MC		 5463 u16 offset;
5464 u16 flags;
5bae30c9 5465#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5466 u32 rw_mask;
5467 u32 ro_mask;
5468 } reg_tbl[] = {
5469 { 0x006c, 0, 0x00000000, 0x0000003f },
5470 { 0x0090, 0, 0xffffffff, 0x00000000 },
5471 { 0x0094, 0, 0x00000000, 0x00000000 },
5472
5bae30c9
MC		 5473 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5474 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5475 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5476 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5477 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5478 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5479 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5480 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5481 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5482
5483 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5484 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5485 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5486 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5487 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5488 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5489
5490 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5491 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5492 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5493
5494 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5495 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5496
5497 { 0x1408, 0, 0x01c00800, 0x00000000 },
5498 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5499 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5500 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5501 { 0x14b0, 0, 0x00000002, 0x00000001 },
5502 { 0x14b8, 0, 0x00000000, 0x00000000 },
5503 { 0x14c0, 0, 0x00000000, 0x00000009 },
5504 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5505 { 0x14cc, 0, 0x00000000, 0x00000001 },
5506 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5507
5508 { 0x1800, 0, 0x00000000, 0x00000001 },
5509 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5510
5511 { 0x2800, 0, 0x00000000, 0x00000001 },
5512 { 0x2804, 0, 0x00000000, 0x00003f01 },
5513 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5514 { 0x2810, 0, 0xffff0000, 0x00000000 },
5515 { 0x2814, 0, 0xffff0000, 0x00000000 },
5516 { 0x2818, 0, 0xffff0000, 0x00000000 },
5517 { 0x281c, 0, 0xffff0000, 0x00000000 },
5518 { 0x2834, 0, 0xffffffff, 0x00000000 },
5519 { 0x2840, 0, 0x00000000, 0xffffffff },
5520 { 0x2844, 0, 0x00000000, 0xffffffff },
5521 { 0x2848, 0, 0xffffffff, 0x00000000 },
5522 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5523
5524 { 0x2c00, 0, 0x00000000, 0x00000011 },
5525 { 0x2c04, 0, 0x00000000, 0x00030007 },
5526
b6016b76
MC		 5527 { 0x3c00, 0, 0x00000000, 0x00000001 },
5528 { 0x3c04, 0, 0x00000000, 0x00070000 },
5529 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5530 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5531 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5532 { 0x3c14, 0, 0x00000000, 0xffffffff },
5533 { 0x3c18, 0, 0x00000000, 0xffffffff },
5534 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5535 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5536
5537 { 0x5004, 0, 0x00000000, 0x0000007f },
5538 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5539
b6016b76
MC		 5540 { 0x5c00, 0, 0x00000000, 0x00000001 },
5541 { 0x5c04, 0, 0x00000000, 0x0003000f },
5542 { 0x5c08, 0, 0x00000003, 0x00000000 },
5543 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5544 { 0x5c10, 0, 0x00000000, 0xffffffff },
5545 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5546 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5547 { 0x5c88, 0, 0x00000000, 0x00077373 },
5548 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5549
5550 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5551 { 0x680c, 0, 0xffffffff, 0x00000000 },
5552 { 0x6810, 0, 0xffffffff, 0x00000000 },
5553 { 0x6814, 0, 0xffffffff, 0x00000000 },
5554 { 0x6818, 0, 0xffffffff, 0x00000000 },
5555 { 0x681c, 0, 0xffffffff, 0x00000000 },
5556 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5557 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5558 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5559 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5560 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5561 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5562 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5563 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5564 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5565 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5566 { 0x684c, 0, 0xffffffff, 0x00000000 },
5567 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5568 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5569 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5570 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5571 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5572 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5573
5574 { 0xffff, 0, 0x00000000, 0x00000000 },
5575 };
5576
5577 ret = 0;
5bae30c9
MC		 5578 is_5709 = 0;
5579 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5580 is_5709 = 1;
5581
b6016b76
MC		 5582 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5583 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5584 u16 flags = reg_tbl[i].flags;
5585
5586 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5587 continue;
b6016b76
MC		 5588
5589 offset = (u32) reg_tbl[i].offset;
5590 rw_mask = reg_tbl[i].rw_mask;
5591 ro_mask = reg_tbl[i].ro_mask;
5592
14ab9b86 5593 save_val = readl(bp->regview + offset);
b6016b76 5594
14ab9b86 5595 writel(0, bp->regview + offset);
b6016b76 5596
14ab9b86 5597 val = readl(bp->regview + offset);
b6016b76
MC		 5598 if ((val & rw_mask) != 0) {
5599 goto reg_test_err;
5600 }
5601
5602 if ((val & ro_mask) != (save_val & ro_mask)) {
5603 goto reg_test_err;
5604 }
5605
14ab9b86 5606 writel(0xffffffff, bp->regview + offset);
b6016b76 5607
14ab9b86 5608 val = readl(bp->regview + offset);
b6016b76
MC		 5609 if ((val & rw_mask) != rw_mask) {
5610 goto reg_test_err;
5611 }
5612
5613 if ((val & ro_mask) != (save_val & ro_mask)) {
5614 goto reg_test_err;
5615 }
5616
14ab9b86 5617 writel(save_val, bp->regview + offset);
b6016b76
MC		 5618 continue;
5619
5620reg_test_err:
14ab9b86 5621 writel(save_val, bp->regview + offset);
b6016b76
MC		 5622 ret = -ENODEV;
5623 break;
5624 }
5625 return ret;
5626}
5627
5628static int
5629bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5630{
f71e1309 5631 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5632 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5633 int i;
5634
5635 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5636 u32 offset;
5637
5638 for (offset = 0; offset < size; offset += 4) {
5639
2726d6e1 5640 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5641
2726d6e1 5642 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5643 test_pattern[i]) {
5644 return -ENODEV;
5645 }
5646 }
5647 }
5648 return 0;
5649}
5650
5651static int
5652bnx2_test_memory(struct bnx2 *bp)
5653{
5654 int ret = 0;
5655 int i;
5bae30c9 5656 static struct mem_entry {
b6016b76
MC		 5657 u32 offset;
5658 u32 len;
5bae30c9 5659 } mem_tbl_5706[] = {
b6016b76 5660 { 0x60000, 0x4000 },
5b0c76ad 5661 { 0xa0000, 0x3000 },
b6016b76
MC		 5662 { 0xe0000, 0x4000 },
5663 { 0x120000, 0x4000 },
5664 { 0x1a0000, 0x4000 },
5665 { 0x160000, 0x4000 },
5666 { 0xffffffff, 0 },
5bae30c9
MC		 5667 },
5668 mem_tbl_5709[] = {
5669 { 0x60000, 0x4000 },
5670 { 0xa0000, 0x3000 },
5671 { 0xe0000, 0x4000 },
5672 { 0x120000, 0x4000 },
5673 { 0x1a0000, 0x4000 },
5674 { 0xffffffff, 0 },
b6016b76 5675 };
5bae30c9
MC		 5676 struct mem_entry *mem_tbl;
5677
5678 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5679 mem_tbl = mem_tbl_5709;
5680 else
5681 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5682
5683 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5684 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5685 mem_tbl[i].len)) != 0) {
5686 return ret;
5687 }
5688 }
6aa20a22 5689
b6016b76
MC		 5690 return ret;
5691}
5692
bc5a0690
MC		 5693#define BNX2_MAC_LOOPBACK 0
5694#define BNX2_PHY_LOOPBACK 1
5695
b6016b76 5696static int
bc5a0690 5697bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5698{
5699 unsigned int pkt_size, num_pkts, i;
5700 struct sk_buff *skb, *rx_skb;
5701 unsigned char *packet;
bc5a0690 5702 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5703 dma_addr_t map;
5704 struct tx_bd *txbd;
5705 struct sw_bd *rx_buf;
5706 struct l2_fhdr *rx_hdr;
5707 int ret = -ENODEV;
c76c0475 5708 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5709 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5710 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5711
5712 tx_napi = bnapi;
b6016b76 5713
35e9010b 5714 txr = &tx_napi->tx_ring;
bb4f98ab 5715 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5716 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5717 bp->loopback = MAC_LOOPBACK;
5718 bnx2_set_mac_loopback(bp);
5719 }
5720 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5721 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5722 return 0;
5723
80be4434 5724 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5725 bnx2_set_phy_loopback(bp);
5726 }
5727 else
5728 return -EINVAL;
b6016b76 5729
84eaa187 5730 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5731 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5732 if (!skb)
5733 return -ENOMEM;
b6016b76 5734 packet = skb_put(skb, pkt_size);
6634292b 5735 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5736 memset(packet + 6, 0x0, 8);
5737 for (i = 14; i < pkt_size; i++)
5738 packet[i] = (unsigned char) (i & 0xff);
5739
36227e88
SG		 5740 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5741 PCI_DMA_TODEVICE);
5742 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5743 dev_kfree_skb(skb);
5744 return -EIO;
5745 }
b6016b76 5746
bf5295bb
MC		 5747 REG_WR(bp, BNX2_HC_COMMAND,
5748 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5749
b6016b76
MC		 5750 REG_RD(bp, BNX2_HC_COMMAND);
5751
5752 udelay(5);
35efa7c1 5753 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5754
b6016b76
MC		 5755 num_pkts = 0;
5756
35e9010b 5757 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5758
5759 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5760 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5761 txbd->tx_bd_mss_nbytes = pkt_size;
5762 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5763
5764 num_pkts++;
35e9010b
MC		 5765 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5766 txr->tx_prod_bseq += pkt_size;
b6016b76 5767
35e9010b
MC		 5768 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5769 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5770
5771 udelay(100);
5772
bf5295bb
MC		 5773 REG_WR(bp, BNX2_HC_COMMAND,
5774 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5775
b6016b76
MC		 5776 REG_RD(bp, BNX2_HC_COMMAND);
5777
5778 udelay(5);
5779
36227e88 5780 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5781 dev_kfree_skb(skb);
b6016b76 5782
35e9010b 5783 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5784 goto loopback_test_done;
b6016b76 5785
35efa7c1 5786 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5787 if (rx_idx != rx_start_idx + num_pkts) {
5788 goto loopback_test_done;
5789 }
5790
bb4f98ab 5791 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
b6016b76
MC		 5792 rx_skb = rx_buf->skb;
5793
a33fa66b 5794 rx_hdr = rx_buf->desc;
d89cb6af 5795 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76 5796
36227e88 5797 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5798 dma_unmap_addr(rx_buf, mapping),
b6016b76
MC		 5799 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5800
ade2bfe7 5801 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5802 (L2_FHDR_ERRORS_BAD_CRC |
5803 L2_FHDR_ERRORS_PHY_DECODE |
5804 L2_FHDR_ERRORS_ALIGNMENT |
5805 L2_FHDR_ERRORS_TOO_SHORT |
5806 L2_FHDR_ERRORS_GIANT_FRAME)) {
5807
5808 goto loopback_test_done;
5809 }
5810
5811 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5812 goto loopback_test_done;
5813 }
5814
5815 for (i = 14; i < pkt_size; i++) {
5816 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5817 goto loopback_test_done;
5818 }
5819 }
5820
5821 ret = 0;
5822
5823loopback_test_done:
5824 bp->loopback = 0;
5825 return ret;
5826}
5827
bc5a0690
MC		 5828#define BNX2_MAC_LOOPBACK_FAILED 1
5829#define BNX2_PHY_LOOPBACK_FAILED 2
5830#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5831 BNX2_PHY_LOOPBACK_FAILED)
5832
5833static int
5834bnx2_test_loopback(struct bnx2 *bp)
5835{
5836 int rc = 0;
5837
5838 if (!netif_running(bp->dev))
5839 return BNX2_LOOPBACK_FAILED;
5840
5841 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5842 spin_lock_bh(&bp->phy_lock);
9a120bc5 5843 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5844 spin_unlock_bh(&bp->phy_lock);
5845 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5846 rc |= BNX2_MAC_LOOPBACK_FAILED;
5847 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5848 rc |= BNX2_PHY_LOOPBACK_FAILED;
5849 return rc;
5850}
5851
b6016b76
MC		 5852#define NVRAM_SIZE 0x200
5853#define CRC32_RESIDUAL 0xdebb20e3
5854
5855static int
5856bnx2_test_nvram(struct bnx2 *bp)
5857{
b491edd5 5858 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5859 u8 *data = (u8 *) buf;
5860 int rc = 0;
5861 u32 magic, csum;
5862
5863 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5864 goto test_nvram_done;
5865
5866 magic = be32_to_cpu(buf[0]);
5867 if (magic != 0x669955aa) {
5868 rc = -ENODEV;
5869 goto test_nvram_done;
5870 }
5871
5872 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5873 goto test_nvram_done;
5874
5875 csum = ether_crc_le(0x100, data);
5876 if (csum != CRC32_RESIDUAL) {
5877 rc = -ENODEV;
5878 goto test_nvram_done;
5879 }
5880
5881 csum = ether_crc_le(0x100, data + 0x100);
5882 if (csum != CRC32_RESIDUAL) {
5883 rc = -ENODEV;
5884 }
5885
5886test_nvram_done:
5887 return rc;
5888}
5889
5890static int
5891bnx2_test_link(struct bnx2 *bp)
5892{
5893 u32 bmsr;
5894
9f52b564
MC		 5895 if (!netif_running(bp->dev))
5896 return -ENODEV;
5897
583c28e5 5898 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5899 if (bp->link_up)
5900 return 0;
5901 return -ENODEV;
5902 }
c770a65c 5903 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5904 bnx2_enable_bmsr1(bp);
5905 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5906 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5907 bnx2_disable_bmsr1(bp);
c770a65c 5908 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5909
b6016b76
MC		 5910 if (bmsr & BMSR_LSTATUS) {
5911 return 0;
5912 }
5913 return -ENODEV;
5914}
5915
5916static int
5917bnx2_test_intr(struct bnx2 *bp)
5918{
5919 int i;
b6016b76
MC		 5920 u16 status_idx;
5921
5922 if (!netif_running(bp->dev))
5923 return -ENODEV;
5924
5925 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5926
5927 /* This register is not touched during run-time. */
bf5295bb 5928 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5929 REG_RD(bp, BNX2_HC_COMMAND);
5930
5931 for (i = 0; i < 10; i++) {
5932 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5933 status_idx) {
5934
5935 break;
5936 }
5937
5938 msleep_interruptible(10);
5939 }
5940 if (i < 10)
5941 return 0;
5942
5943 return -ENODEV;
5944}
5945
38ea3686 5946/* Determining link for parallel detection. */
b2fadeae
MC		 5947static int
5948bnx2_5706_serdes_has_link(struct bnx2 *bp)
5949{
5950 u32 mode_ctl, an_dbg, exp;
5951
38ea3686
MC		 5952 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5953 return 0;
5954
b2fadeae
MC		 5955 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5956 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5957
5958 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5959 return 0;
5960
5961 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5962 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5963 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5964
f3014c0c 5965 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5966 return 0;
5967
5968 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5969 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5970 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5971
5972 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5973 return 0;
5974
5975 return 1;
5976}
5977
b6016b76 5978static void
48b01e2d 5979bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5980{
b2fadeae
MC		 5981 int check_link = 1;
5982
48b01e2d 5983 spin_lock(&bp->phy_lock);
b2fadeae 5984 if (bp->serdes_an_pending) {
48b01e2d 5985 bp->serdes_an_pending--;
b2fadeae
MC		 5986 check_link = 0;
5987 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5988 u32 bmcr;
b6016b76 5989
ac392abc 5990 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 5991
ca58c3af 5992 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5993
48b01e2d 5994 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5995 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5996 bmcr &= ~BMCR_ANENABLE;
5997 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5998 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5999 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 6000 }
b6016b76 6001 }
48b01e2d
MC		 6002 }
6003 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 6004 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 6005 u32 phy2;
b6016b76 6006
48b01e2d
MC		 6007 bnx2_write_phy(bp, 0x17, 0x0f01);
6008 bnx2_read_phy(bp, 0x15, &phy2);
6009 if (phy2 & 0x20) {
6010 u32 bmcr;
cd339a0e 6011
ca58c3af 6012 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6013 bmcr |= BMCR_ANENABLE;
ca58c3af 6014 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6015
583c28e5 6016 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6017 }
6018 } else
ac392abc 6019 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6020
a2724e25 6021 if (check_link) {
b2fadeae
MC		 6022 u32 val;
6023
6024 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6025 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6026 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6027
a2724e25
MC		 6028 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6029 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6030 bnx2_5706s_force_link_dn(bp, 1);
6031 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6032 } else
6033 bnx2_set_link(bp);
6034 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6035 bnx2_set_link(bp);
b2fadeae 6036 }
48b01e2d
MC		 6037 spin_unlock(&bp->phy_lock);
6038}
b6016b76 6039
f8dd064e
MC		 6040static void
6041bnx2_5708_serdes_timer(struct bnx2 *bp)
6042{
583c28e5 6043 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6044 return;
6045
583c28e5 6046 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6047 bp->serdes_an_pending = 0;
6048 return;
6049 }
b6016b76 6050
f8dd064e
MC		 6051 spin_lock(&bp->phy_lock);
6052 if (bp->serdes_an_pending)
6053 bp->serdes_an_pending--;
6054 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6055 u32 bmcr;
b6016b76 6056
ca58c3af 6057 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6058 if (bmcr & BMCR_ANENABLE) {
605a9e20 6059 bnx2_enable_forced_2g5(bp);
40105c0b 6060 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6061 } else {
605a9e20 6062 bnx2_disable_forced_2g5(bp);
f8dd064e 6063 bp->serdes_an_pending = 2;
ac392abc 6064 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6065 }
b6016b76 6066
f8dd064e 6067 } else
ac392abc 6068 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6069
f8dd064e
MC		 6070 spin_unlock(&bp->phy_lock);
6071}
6072
48b01e2d
MC		 6073static void
6074bnx2_timer(unsigned long data)
6075{
6076 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6077
48b01e2d
MC		 6078 if (!netif_running(bp->dev))
6079 return;
b6016b76 6080
48b01e2d
MC		 6081 if (atomic_read(&bp->intr_sem) != 0)
6082 goto bnx2_restart_timer;
b6016b76 6083
efba0180
MC		 6084 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6085 BNX2_FLAG_USING_MSI)
6086 bnx2_chk_missed_msi(bp);
6087
df149d70 6088 bnx2_send_heart_beat(bp);
b6016b76 6089
2726d6e1
MC		 6090 bp->stats_blk->stat_FwRxDrop =
6091 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6092
02537b06 6093 /* workaround occasional corrupted counters */
61d9e3fa 6094 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
02537b06
MC		 6095 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6096 BNX2_HC_COMMAND_STATS_NOW);
6097
583c28e5 6098 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 6099 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6100 bnx2_5706_serdes_timer(bp);
27a005b8 6101 else
f8dd064e 6102 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6103 }
6104
6105bnx2_restart_timer:
cd339a0e 6106 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6107}
6108
8e6a72c4
MC		 6109static int
6110bnx2_request_irq(struct bnx2 *bp)
6111{
6d866ffc 6112 unsigned long flags;
b4b36042
MC		 6113 struct bnx2_irq *irq;
6114 int rc = 0, i;
8e6a72c4 6115
f86e82fb 6116 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6117 flags = 0;
6118 else
6119 flags = IRQF_SHARED;
b4b36042
MC		 6120
6121 for (i = 0; i < bp->irq_nvecs; i++) {
6122 irq = &bp->irq_tbl[i];
c76c0475 6123 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6124 &bp->bnx2_napi[i]);
b4b36042
MC		 6125 if (rc)
6126 break;
6127 irq->requested = 1;
6128 }
8e6a72c4
MC		 6129 return rc;
6130}
6131
6132static void
6133bnx2_free_irq(struct bnx2 *bp)
6134{
b4b36042
MC		 6135 struct bnx2_irq *irq;
6136 int i;
8e6a72c4 6137
b4b36042
MC		 6138 for (i = 0; i < bp->irq_nvecs; i++) {
6139 irq = &bp->irq_tbl[i];
6140 if (irq->requested)
f0ea2e63 6141 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6142 irq->requested = 0;
6d866ffc 6143 }
f86e82fb 6144 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6145 pci_disable_msi(bp->pdev);
f86e82fb 6146 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6147 pci_disable_msix(bp->pdev);
6148
f86e82fb 6149 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6150}
6151
6152static void
5e9ad9e1 6153bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6154{
379b39a2 6155 int i, total_vecs, rc;
57851d84 6156 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6157 struct net_device *dev = bp->dev;
6158 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6159
b4b36042
MC		 6160 bnx2_setup_msix_tbl(bp);
6161 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6162 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6163 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6164
e2eb8e38
BL		 6165 /* Need to flush the previous three writes to ensure MSI-X
6166 * is setup properly */
6167 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6168
57851d84
MC		 6169 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6170 msix_ent[i].entry = i;
6171 msix_ent[i].vector = 0;
6172 }
6173
379b39a2
MC		 6174 total_vecs = msix_vecs;
6175#ifdef BCM_CNIC
6176 total_vecs++;
6177#endif
6178 rc = -ENOSPC;
6179 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6180 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6181 if (rc <= 0)
6182 break;
6183 if (rc > 0)
6184 total_vecs = rc;
6185 }
6186
57851d84
MC		 6187 if (rc != 0)
6188 return;
6189
379b39a2
MC		 6190 msix_vecs = total_vecs;
6191#ifdef BCM_CNIC
6192 msix_vecs--;
6193#endif
5e9ad9e1 6194 bp->irq_nvecs = msix_vecs;
f86e82fb 6195 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6196 for (i = 0; i < total_vecs; i++) {
57851d84 6197 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6198 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6199 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6200 }
6d866ffc
MC		 6201}
6202
6203static void
6204bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6205{
5e9ad9e1 6206 int cpus = num_online_cpus();
706bf240 6207 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 6208
6d866ffc
MC		 6209 bp->irq_tbl[0].handler = bnx2_interrupt;
6210 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6211 bp->irq_nvecs = 1;
6212 bp->irq_tbl[0].vector = bp->pdev->irq;
6213
3d5f3a7b 6214 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6215 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6216
f86e82fb
DM		 6217 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6218 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6219 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6220 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 6221 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 6222 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6223 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6224 } else
6225 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6226
6227 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6228 }
6229 }
706bf240
BL		 6230
6231 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6232 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6233
5e9ad9e1 6234 bp->num_rx_rings = bp->irq_nvecs;
8e6a72c4
MC		 6235}
6236
b6016b76
MC		 6237/* Called with rtnl_lock */
6238static int
6239bnx2_open(struct net_device *dev)
6240{
972ec0d4 6241 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6242 int rc;
6243
1b2f922f
MC		 6244 netif_carrier_off(dev);
6245
829ca9a3 6246 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 6247 bnx2_disable_int(bp);
6248
35e9010b 6249 bnx2_setup_int_mode(bp, disable_msi);
4327ba43 6250 bnx2_init_napi(bp);
35e9010b 6251 bnx2_napi_enable(bp);
b6016b76 6252 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6253 if (rc)
6254 goto open_err;
b6016b76 6255
8e6a72c4 6256 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6257 if (rc)
6258 goto open_err;
b6016b76 6259
9a120bc5 6260 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6261 if (rc)
6262 goto open_err;
6aa20a22 6263
cd339a0e 6264 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6265
6266 atomic_set(&bp->intr_sem, 0);
6267
354fcd77
MC		 6268 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6269
b6016b76
MC		 6270 bnx2_enable_int(bp);
6271
f86e82fb 6272 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6273 /* Test MSI to make sure it is working
6274 * If MSI test fails, go back to INTx mode
6275 */
6276 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6277 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6278
6279 bnx2_disable_int(bp);
8e6a72c4 6280 bnx2_free_irq(bp);
b6016b76 6281
6d866ffc
MC		 6282 bnx2_setup_int_mode(bp, 1);
6283
9a120bc5 6284 rc = bnx2_init_nic(bp, 0);
b6016b76 6285
8e6a72c4
MC		 6286 if (!rc)
6287 rc = bnx2_request_irq(bp);
6288
b6016b76 6289 if (rc) {
b6016b76 6290 del_timer_sync(&bp->timer);
2739a8bb 6291 goto open_err;
b6016b76
MC		 6292 }
6293 bnx2_enable_int(bp);
6294 }
6295 }
f86e82fb 6296 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6297 netdev_info(dev, "using MSI\n");
f86e82fb 6298 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6299 netdev_info(dev, "using MSIX\n");
b6016b76 6300
706bf240 6301 netif_tx_start_all_queues(dev);
b6016b76
MC		 6302
6303 return 0;
2739a8bb
MC		 6304
6305open_err:
6306 bnx2_napi_disable(bp);
6307 bnx2_free_skbs(bp);
6308 bnx2_free_irq(bp);
6309 bnx2_free_mem(bp);
f048fa9c 6310 bnx2_del_napi(bp);
2739a8bb 6311 return rc;
b6016b76
MC		 6312}
6313
6314static void
c4028958 6315bnx2_reset_task(struct work_struct *work)
b6016b76 6316{
c4028958 6317 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 6318
51bf6bb4
MC		 6319 rtnl_lock();
6320 if (!netif_running(bp->dev)) {
6321 rtnl_unlock();
afdc08b9 6322 return;
51bf6bb4 6323 }
afdc08b9 6324
212f9934 6325 bnx2_netif_stop(bp, true);
b6016b76 6326
9a120bc5 6327 bnx2_init_nic(bp, 1);
b6016b76
MC		 6328
6329 atomic_set(&bp->intr_sem, 1);
212f9934 6330 bnx2_netif_start(bp, true);
51bf6bb4 6331 rtnl_unlock();
b6016b76
MC		 6332}
6333
20175c57
MC		 6334static void
6335bnx2_dump_state(struct bnx2 *bp)
6336{
6337 struct net_device *dev = bp->dev;
5804a8fb
MC		 6338 u32 mcp_p0, mcp_p1, val1, val2;
6339
6340 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6341 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6342 atomic_read(&bp->intr_sem), val1);
6343 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6344 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6345 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6346 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
3a9c6a49 6347 REG_RD(bp, BNX2_EMAC_TX_STATUS),
b98eba52
EW		 6348 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6349 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
3a9c6a49 6350 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
b98eba52
EW		 6351 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6352 mcp_p0 = BNX2_MCP_STATE_P0;
6353 mcp_p1 = BNX2_MCP_STATE_P1;
6354 } else {
6355 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6356 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6357 }
3a9c6a49 6358 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
b98eba52 6359 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
3a9c6a49
JP		 6360 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6361 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6362 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49
JP		 6363 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6364 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6365}
6366
b6016b76
MC		 6367static void
6368bnx2_tx_timeout(struct net_device *dev)
6369{
972ec0d4 6370 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6371
20175c57
MC		 6372 bnx2_dump_state(bp);
6373
b6016b76
MC		 6374 /* This allows the netif to be shutdown gracefully before resetting */
6375 schedule_work(&bp->reset_task);
6376}
6377
6378#ifdef BCM_VLAN
6379/* Called with rtnl_lock */
6380static void
6381bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6382{
972ec0d4 6383 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6384
3767546c 6385 if (netif_running(dev))
212f9934 6386 bnx2_netif_stop(bp, false);
b6016b76
MC		 6387
6388 bp->vlgrp = vlgrp;
3767546c
MC		 6389
6390 if (!netif_running(dev))
6391 return;
6392
b6016b76 6393 bnx2_set_rx_mode(dev);
7c62e83b
MC		 6394 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6395 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
b6016b76 6396
212f9934 6397 bnx2_netif_start(bp, false);
b6016b76 6398}
b6016b76
MC		 6399#endif
6400
932ff279 6401/* Called with netif_tx_lock.
2f8af120
MC		 6402 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6403 * netif_wake_queue().
b6016b76 6404 */
61357325 6405static netdev_tx_t
b6016b76
MC		 6406bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6407{
972ec0d4 6408 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6409 dma_addr_t mapping;
6410 struct tx_bd *txbd;
3d16af86 6411 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6412 u32 len, vlan_tag_flags, last_frag, mss;
6413 u16 prod, ring_prod;
6414 int i;
706bf240
BL		 6415 struct bnx2_napi *bnapi;
6416 struct bnx2_tx_ring_info *txr;
6417 struct netdev_queue *txq;
6418
6419 /* Determine which tx ring we will be placed on */
6420 i = skb_get_queue_mapping(skb);
6421 bnapi = &bp->bnx2_napi[i];
6422 txr = &bnapi->tx_ring;
6423 txq = netdev_get_tx_queue(dev, i);
b6016b76 6424
35e9010b 6425 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6426 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6427 netif_tx_stop_queue(txq);
3a9c6a49 6428 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6429
6430 return NETDEV_TX_BUSY;
6431 }
6432 len = skb_headlen(skb);
35e9010b 6433 prod = txr->tx_prod;
b6016b76
MC		 6434 ring_prod = TX_RING_IDX(prod);
6435
6436 vlan_tag_flags = 0;
84fa7933 6437 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6438 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6439 }
6440
729b85cd 6441#ifdef BCM_VLAN
79ea13ce 6442 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 6443 vlan_tag_flags |=
6444 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6445 }
729b85cd 6446#endif
fde82055 6447 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6448 u32 tcp_opt_len;
eddc9ec5 6449 struct iphdr *iph;
b6016b76 6450
b6016b76
MC		 6451 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6452
4666f87a
MC		 6453 tcp_opt_len = tcp_optlen(skb);
6454
6455 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6456 u32 tcp_off = skb_transport_offset(skb) -
6457 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6458
4666f87a
MC		 6459 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6460 TX_BD_FLAGS_SW_FLAGS;
6461 if (likely(tcp_off == 0))
6462 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6463 else {
6464 tcp_off >>= 3;
6465 vlan_tag_flags |= ((tcp_off & 0x3) <<
6466 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6467 ((tcp_off & 0x10) <<
6468 TX_BD_FLAGS_TCP6_OFF4_SHL);
6469 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6470 }
6471 } else {
4666f87a 6472 iph = ip_hdr(skb);
4666f87a
MC		 6473 if (tcp_opt_len || (iph->ihl > 5)) {
6474 vlan_tag_flags |= ((iph->ihl - 5) +
6475 (tcp_opt_len >> 2)) << 8;
6476 }
b6016b76 6477 }
4666f87a 6478 } else
b6016b76 6479 mss = 0;
b6016b76 6480
36227e88
SG		 6481 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6482 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 6483 dev_kfree_skb(skb);
6484 return NETDEV_TX_OK;
6485 }
6486
35e9010b 6487 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6488 tx_buf->skb = skb;
1a4ccc2d 6489 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6490
35e9010b 6491 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6492
6493 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6494 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6495 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6496 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6497
6498 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6499 tx_buf->nr_frags = last_frag;
6500 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6501
6502 for (i = 0; i < last_frag; i++) {
6503 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6504
6505 prod = NEXT_TX_BD(prod);
6506 ring_prod = TX_RING_IDX(prod);
35e9010b 6507 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6508
6509 len = frag->size;
36227e88
SG		 6510 mapping = dma_map_page(&bp->pdev->dev, frag->page, frag->page_offset,
6511 len, PCI_DMA_TODEVICE);
6512 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6513 goto dma_error;
1a4ccc2d 6514 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6515 mapping);
b6016b76
MC		 6516
6517 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6518 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6519 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6520 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6521
6522 }
6523 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6524
6525 prod = NEXT_TX_BD(prod);
35e9010b 6526 txr->tx_prod_bseq += skb->len;
b6016b76 6527
35e9010b
MC		 6528 REG_WR16(bp, txr->tx_bidx_addr, prod);
6529 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6530
6531 mmiowb();
6532
35e9010b 6533 txr->tx_prod = prod;
b6016b76 6534
35e9010b 6535 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6536 netif_tx_stop_queue(txq);
35e9010b 6537 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6538 netif_tx_wake_queue(txq);
b6016b76
MC		 6539 }
6540
e95524a7
AD		 6541 return NETDEV_TX_OK;
6542dma_error:
6543 /* save value of frag that failed */
6544 last_frag = i;
6545
6546 /* start back at beginning and unmap skb */
6547 prod = txr->tx_prod;
6548 ring_prod = TX_RING_IDX(prod);
6549 tx_buf = &txr->tx_buf_ring[ring_prod];
6550 tx_buf->skb = NULL;
36227e88 6551 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6552 skb_headlen(skb), PCI_DMA_TODEVICE);
6553
6554 /* unmap remaining mapped pages */
6555 for (i = 0; i < last_frag; i++) {
6556 prod = NEXT_TX_BD(prod);
6557 ring_prod = TX_RING_IDX(prod);
6558 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6559 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6560 skb_shinfo(skb)->frags[i].size,
6561 PCI_DMA_TODEVICE);
6562 }
6563
6564 dev_kfree_skb(skb);
b6016b76
MC		 6565 return NETDEV_TX_OK;
6566}
6567
6568/* Called with rtnl_lock */
6569static int
6570bnx2_close(struct net_device *dev)
6571{
972ec0d4 6572 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6573
4bb073c0 6574 cancel_work_sync(&bp->reset_task);
afdc08b9 6575
bea3348e 6576 bnx2_disable_int_sync(bp);
35efa7c1 6577 bnx2_napi_disable(bp);
b6016b76 6578 del_timer_sync(&bp->timer);
74bf4ba3 6579 bnx2_shutdown_chip(bp);
8e6a72c4 6580 bnx2_free_irq(bp);
b6016b76
MC		 6581 bnx2_free_skbs(bp);
6582 bnx2_free_mem(bp);
f048fa9c 6583 bnx2_del_napi(bp);
b6016b76
MC		 6584 bp->link_up = 0;
6585 netif_carrier_off(bp->dev);
829ca9a3 6586 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6587 return 0;
6588}
6589
354fcd77
MC		 6590static void
6591bnx2_save_stats(struct bnx2 *bp)
6592{
6593 u32 *hw_stats = (u32 *) bp->stats_blk;
6594 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6595 int i;
6596
6597 /* The 1st 10 counters are 64-bit counters */
6598 for (i = 0; i < 20; i += 2) {
6599 u32 hi;
6600 u64 lo;
6601
c9885fe5
PR		 6602 hi = temp_stats[i] + hw_stats[i];
6603 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6604 if (lo > 0xffffffff)
6605 hi++;
c9885fe5
PR		 6606 temp_stats[i] = hi;
6607 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6608 }
6609
6610 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6611 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6612}
6613
5d07bf26
ED		 6614#define GET_64BIT_NET_STATS64(ctr) \
6615 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6616
a4743058 6617#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6618 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6619 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6620
a4743058 6621#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6622 (unsigned long) (bp->stats_blk->ctr + \
6623 bp->temp_stats_blk->ctr)
a4743058 6624
5d07bf26
ED		 6625static struct rtnl_link_stats64 *
6626bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6627{
972ec0d4 6628 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6629
5d07bf26 6630 if (bp->stats_blk == NULL)
b6016b76 6631 return net_stats;
5d07bf26 6632
b6016b76 6633 net_stats->rx_packets =
a4743058
MC		 6634 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6635 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6636 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6637
6638 net_stats->tx_packets =
a4743058
MC		 6639 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6640 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6641 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6642
6643 net_stats->rx_bytes =
a4743058 6644 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6645
6646 net_stats->tx_bytes =
a4743058 6647 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6648
6aa20a22 6649 net_stats->multicast =
6fdae995 6650 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6651
6aa20a22 6652 net_stats->collisions =
a4743058 6653 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6654
6aa20a22 6655 net_stats->rx_length_errors =
a4743058
MC		 6656 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6657 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6658
6aa20a22 6659 net_stats->rx_over_errors =
a4743058
MC		 6660 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6661 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6662
6aa20a22 6663 net_stats->rx_frame_errors =
a4743058 6664 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6665
6aa20a22 6666 net_stats->rx_crc_errors =
a4743058 6667 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6668
6669 net_stats->rx_errors = net_stats->rx_length_errors +
6670 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6671 net_stats->rx_crc_errors;
6672
6673 net_stats->tx_aborted_errors =
a4743058
MC		 6674 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6675 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6676
5b0c76ad
MC		 6677 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6678 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6679 net_stats->tx_carrier_errors = 0;
6680 else {
6681 net_stats->tx_carrier_errors =
a4743058 6682 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6683 }
6684
6685 net_stats->tx_errors =
a4743058 6686 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6687 net_stats->tx_aborted_errors +
6688 net_stats->tx_carrier_errors;
6689
cea94db9 6690 net_stats->rx_missed_errors =
a4743058
MC		 6691 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6692 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6693 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6694
b6016b76
MC		 6695 return net_stats;
6696}
6697
6698/* All ethtool functions called with rtnl_lock */
6699
6700static int
6701bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6702{
972ec0d4 6703 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6704 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6705
6706 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6707 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6708 support_serdes = 1;
6709 support_copper = 1;
6710 } else if (bp->phy_port == PORT_FIBRE)
6711 support_serdes = 1;
6712 else
6713 support_copper = 1;
6714
6715 if (support_serdes) {
b6016b76
MC		 6716 cmd->supported |= SUPPORTED_1000baseT_Full |
6717 SUPPORTED_FIBRE;
583c28e5 6718 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6719 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6720
b6016b76 6721 }
7b6b8347 6722 if (support_copper) {
b6016b76
MC		 6723 cmd->supported |= SUPPORTED_10baseT_Half |
6724 SUPPORTED_10baseT_Full |
6725 SUPPORTED_100baseT_Half |
6726 SUPPORTED_100baseT_Full |
6727 SUPPORTED_1000baseT_Full |
6728 SUPPORTED_TP;
6729
b6016b76
MC		 6730 }
6731
7b6b8347
MC		 6732 spin_lock_bh(&bp->phy_lock);
6733 cmd->port = bp->phy_port;
b6016b76
MC		 6734 cmd->advertising = bp->advertising;
6735
6736 if (bp->autoneg & AUTONEG_SPEED) {
6737 cmd->autoneg = AUTONEG_ENABLE;
6738 }
6739 else {
6740 cmd->autoneg = AUTONEG_DISABLE;
6741 }
6742
6743 if (netif_carrier_ok(dev)) {
6744 cmd->speed = bp->line_speed;
6745 cmd->duplex = bp->duplex;
6746 }
6747 else {
6748 cmd->speed = -1;
6749 cmd->duplex = -1;
6750 }
7b6b8347 6751 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6752
6753 cmd->transceiver = XCVR_INTERNAL;
6754 cmd->phy_address = bp->phy_addr;
6755
6756 return 0;
6757}
6aa20a22 6758
b6016b76
MC		 6759static int
6760bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6761{
972ec0d4 6762 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6763 u8 autoneg = bp->autoneg;
6764 u8 req_duplex = bp->req_duplex;
6765 u16 req_line_speed = bp->req_line_speed;
6766 u32 advertising = bp->advertising;
7b6b8347
MC		 6767 int err = -EINVAL;
6768
6769 spin_lock_bh(&bp->phy_lock);
6770
6771 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6772 goto err_out_unlock;
6773
583c28e5
MC		 6774 if (cmd->port != bp->phy_port &&
6775 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6776 goto err_out_unlock;
b6016b76 6777
d6b14486
MC		 6778 /* If device is down, we can store the settings only if the user
6779 * is setting the currently active port.
6780 */
6781 if (!netif_running(dev) && cmd->port != bp->phy_port)
6782 goto err_out_unlock;
6783
b6016b76
MC		 6784 if (cmd->autoneg == AUTONEG_ENABLE) {
6785 autoneg |= AUTONEG_SPEED;
6786
beb499af
MC		 6787 advertising = cmd->advertising;
6788 if (cmd->port == PORT_TP) {
6789 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6790 if (!advertising)
b6016b76 6791 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6792 } else {
6793 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6794 if (!advertising)
6795 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6796 }
6797 advertising |= ADVERTISED_Autoneg;
6798 }
6799 else {
7b6b8347 6800 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6801 if ((cmd->speed != SPEED_1000 &&
6802 cmd->speed != SPEED_2500) ||
6803 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6804 goto err_out_unlock;
80be4434
MC		 6805
6806 if (cmd->speed == SPEED_2500 &&
583c28e5 6807 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6808 goto err_out_unlock;
b6016b76 6809 }
7b6b8347
MC		 6810 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6811 goto err_out_unlock;
6812
b6016b76
MC		 6813 autoneg &= ~AUTONEG_SPEED;
6814 req_line_speed = cmd->speed;
6815 req_duplex = cmd->duplex;
6816 advertising = 0;
6817 }
6818
6819 bp->autoneg = autoneg;
6820 bp->advertising = advertising;
6821 bp->req_line_speed = req_line_speed;
6822 bp->req_duplex = req_duplex;
6823
d6b14486
MC		 6824 err = 0;
6825 /* If device is down, the new settings will be picked up when it is
6826 * brought up.
6827 */
6828 if (netif_running(dev))
6829 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6830
7b6b8347 6831err_out_unlock:
c770a65c 6832 spin_unlock_bh(&bp->phy_lock);
b6016b76 6833
7b6b8347 6834 return err;
b6016b76
MC		 6835}
6836
6837static void
6838bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6839{
972ec0d4 6840 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6841
6842 strcpy(info->driver, DRV_MODULE_NAME);
6843 strcpy(info->version, DRV_MODULE_VERSION);
6844 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6845 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6846}
6847
244ac4f4
MC		 6848#define BNX2_REGDUMP_LEN (32 * 1024)
6849
6850static int
6851bnx2_get_regs_len(struct net_device *dev)
6852{
6853 return BNX2_REGDUMP_LEN;
6854}
6855
6856static void
6857bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6858{
6859 u32 *p = _p, i, offset;
6860 u8 *orig_p = _p;
6861 struct bnx2 *bp = netdev_priv(dev);
6862 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6863 0x0800, 0x0880, 0x0c00, 0x0c10,
6864 0x0c30, 0x0d08, 0x1000, 0x101c,
6865 0x1040, 0x1048, 0x1080, 0x10a4,
6866 0x1400, 0x1490, 0x1498, 0x14f0,
6867 0x1500, 0x155c, 0x1580, 0x15dc,
6868 0x1600, 0x1658, 0x1680, 0x16d8,
6869 0x1800, 0x1820, 0x1840, 0x1854,
6870 0x1880, 0x1894, 0x1900, 0x1984,
6871 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6872 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6873 0x2000, 0x2030, 0x23c0, 0x2400,
6874 0x2800, 0x2820, 0x2830, 0x2850,
6875 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6876 0x3c00, 0x3c94, 0x4000, 0x4010,
6877 0x4080, 0x4090, 0x43c0, 0x4458,
6878 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6879 0x4fc0, 0x5010, 0x53c0, 0x5444,
6880 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6881 0x5fc0, 0x6000, 0x6400, 0x6428,
6882 0x6800, 0x6848, 0x684c, 0x6860,
6883 0x6888, 0x6910, 0x8000 };
6884
6885 regs->version = 0;
6886
6887 memset(p, 0, BNX2_REGDUMP_LEN);
6888
6889 if (!netif_running(bp->dev))
6890 return;
6891
6892 i = 0;
6893 offset = reg_boundaries[0];
6894 p += offset;
6895 while (offset < BNX2_REGDUMP_LEN) {
6896 *p++ = REG_RD(bp, offset);
6897 offset += 4;
6898 if (offset == reg_boundaries[i + 1]) {
6899 offset = reg_boundaries[i + 2];
6900 p = (u32 *) (orig_p + offset);
6901 i += 2;
6902 }
6903 }
6904}
6905
b6016b76
MC		 6906static void
6907bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6908{
972ec0d4 6909 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6910
f86e82fb 6911 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6912 wol->supported = 0;
6913 wol->wolopts = 0;
6914 }
6915 else {
6916 wol->supported = WAKE_MAGIC;
6917 if (bp->wol)
6918 wol->wolopts = WAKE_MAGIC;
6919 else
6920 wol->wolopts = 0;
6921 }
6922 memset(&wol->sopass, 0, sizeof(wol->sopass));
6923}
6924
6925static int
6926bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6927{
972ec0d4 6928 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6929
6930 if (wol->wolopts & ~WAKE_MAGIC)
6931 return -EINVAL;
6932
6933 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6934 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6935 return -EINVAL;
6936
6937 bp->wol = 1;
6938 }
6939 else {
6940 bp->wol = 0;
6941 }
6942 return 0;
6943}
6944
6945static int
6946bnx2_nway_reset(struct net_device *dev)
6947{
972ec0d4 6948 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6949 u32 bmcr;
6950
9f52b564
MC		 6951 if (!netif_running(dev))
6952 return -EAGAIN;
6953
b6016b76
MC		 6954 if (!(bp->autoneg & AUTONEG_SPEED)) {
6955 return -EINVAL;
6956 }
6957
c770a65c 6958 spin_lock_bh(&bp->phy_lock);
b6016b76 6959
583c28e5 6960 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6961 int rc;
6962
6963 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6964 spin_unlock_bh(&bp->phy_lock);
6965 return rc;
6966 }
6967
b6016b76 6968 /* Force a link down visible on the other side */
583c28e5 6969 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6970 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6971 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6972
6973 msleep(20);
6974
c770a65c 6975 spin_lock_bh(&bp->phy_lock);
f8dd064e 6976
40105c0b 6977 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 6978 bp->serdes_an_pending = 1;
6979 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6980 }
6981
ca58c3af 6982 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6983 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6984 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6985
c770a65c 6986 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6987
6988 return 0;
6989}
6990
7959ea25
ON		 6991static u32
6992bnx2_get_link(struct net_device *dev)
6993{
6994 struct bnx2 *bp = netdev_priv(dev);
6995
6996 return bp->link_up;
6997}
6998
b6016b76
MC		 6999static int
7000bnx2_get_eeprom_len(struct net_device *dev)
7001{
972ec0d4 7002 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7003
1122db71 7004 if (bp->flash_info == NULL)
b6016b76
MC		 7005 return 0;
7006
1122db71 7007 return (int) bp->flash_size;
b6016b76
MC		 7008}
7009
7010static int
7011bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7012 u8 *eebuf)
7013{
972ec0d4 7014 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7015 int rc;
7016
9f52b564
MC		 7017 if (!netif_running(dev))
7018 return -EAGAIN;
7019
1064e944 7020 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 7021
7022 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7023
7024 return rc;
7025}
7026
7027static int
7028bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7029 u8 *eebuf)
7030{
972ec0d4 7031 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7032 int rc;
7033
9f52b564
MC		 7034 if (!netif_running(dev))
7035 return -EAGAIN;
7036
1064e944 7037 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7038
7039 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7040
7041 return rc;
7042}
7043
7044static int
7045bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7046{
972ec0d4 7047 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7048
7049 memset(coal, 0, sizeof(struct ethtool_coalesce));
7050
7051 coal->rx_coalesce_usecs = bp->rx_ticks;
7052 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7053 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7054 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7055
7056 coal->tx_coalesce_usecs = bp->tx_ticks;
7057 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7058 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7059 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7060
7061 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7062
7063 return 0;
7064}
7065
7066static int
7067bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7068{
972ec0d4 7069 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7070
7071 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7072 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7073
6aa20a22 7074 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7075 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7076
7077 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7078 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7079
7080 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7081 if (bp->rx_quick_cons_trip_int > 0xff)
7082 bp->rx_quick_cons_trip_int = 0xff;
7083
7084 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7085 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7086
7087 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7088 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7089
7090 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7091 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7092
7093 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7094 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7095 0xff;
7096
7097 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7098 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7099 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7100 bp->stats_ticks = USEC_PER_SEC;
7101 }
7ea6920e
MC		 7102 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7103 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7104 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7105
7106 if (netif_running(bp->dev)) {
212f9934 7107 bnx2_netif_stop(bp, true);
9a120bc5 7108 bnx2_init_nic(bp, 0);
212f9934 7109 bnx2_netif_start(bp, true);
b6016b76
MC		 7110 }
7111
7112 return 0;
7113}
7114
7115static void
7116bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7117{
972ec0d4 7118 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7119
13daffa2 7120 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 7121 ering->rx_mini_max_pending = 0;
47bf4246 7122 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7123
7124 ering->rx_pending = bp->rx_ring_size;
7125 ering->rx_mini_pending = 0;
47bf4246 7126 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 7127
7128 ering->tx_max_pending = MAX_TX_DESC_CNT;
7129 ering->tx_pending = bp->tx_ring_size;
7130}
7131
7132static int
5d5d0015 7133bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 7134{
13daffa2 7135 if (netif_running(bp->dev)) {
354fcd77
MC		 7136 /* Reset will erase chipset stats; save them */
7137 bnx2_save_stats(bp);
7138
212f9934 7139 bnx2_netif_stop(bp, true);
13daffa2
MC		 7140 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7141 bnx2_free_skbs(bp);
7142 bnx2_free_mem(bp);
7143 }
7144
5d5d0015
MC		 7145 bnx2_set_rx_ring_size(bp, rx);
7146 bp->tx_ring_size = tx;
b6016b76
MC		 7147
7148 if (netif_running(bp->dev)) {
13daffa2
MC		 7149 int rc;
7150
7151 rc = bnx2_alloc_mem(bp);
6fefb65e
MC		 7152 if (!rc)
7153 rc = bnx2_init_nic(bp, 0);
7154
7155 if (rc) {
7156 bnx2_napi_enable(bp);
7157 dev_close(bp->dev);
13daffa2 7158 return rc;
6fefb65e 7159 }
e9f26c49
MC		 7160#ifdef BCM_CNIC
7161 mutex_lock(&bp->cnic_lock);
7162 /* Let cnic know about the new status block. */
7163 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7164 bnx2_setup_cnic_irq_info(bp);
7165 mutex_unlock(&bp->cnic_lock);
7166#endif
212f9934 7167 bnx2_netif_start(bp, true);
b6016b76 7168 }
b6016b76
MC		 7169 return 0;
7170}
7171
5d5d0015
MC		 7172static int
7173bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7174{
7175 struct bnx2 *bp = netdev_priv(dev);
7176 int rc;
7177
7178 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7179 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7180 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7181
7182 return -EINVAL;
7183 }
7184 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7185 return rc;
7186}
7187
b6016b76
MC		 7188static void
7189bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7190{
972ec0d4 7191 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7192
7193 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7194 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7195 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7196}
7197
7198static int
7199bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7200{
972ec0d4 7201 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7202
7203 bp->req_flow_ctrl = 0;
7204 if (epause->rx_pause)
7205 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7206 if (epause->tx_pause)
7207 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7208
7209 if (epause->autoneg) {
7210 bp->autoneg |= AUTONEG_FLOW_CTRL;
7211 }
7212 else {
7213 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7214 }
7215
9f52b564
MC		 7216 if (netif_running(dev)) {
7217 spin_lock_bh(&bp->phy_lock);
7218 bnx2_setup_phy(bp, bp->phy_port);
7219 spin_unlock_bh(&bp->phy_lock);
7220 }
b6016b76
MC		 7221
7222 return 0;
7223}
7224
7225static u32
7226bnx2_get_rx_csum(struct net_device *dev)
7227{
972ec0d4 7228 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7229
7230 return bp->rx_csum;
7231}
7232
7233static int
7234bnx2_set_rx_csum(struct net_device *dev, u32 data)
7235{
972ec0d4 7236 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7237
7238 bp->rx_csum = data;
7239 return 0;
7240}
7241
b11d6213
MC		 7242static int
7243bnx2_set_tso(struct net_device *dev, u32 data)
7244{
4666f87a
MC		 7245 struct bnx2 *bp = netdev_priv(dev);
7246
7247 if (data) {
b11d6213 7248 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7249 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7250 dev->features |= NETIF_F_TSO6;
7251 } else
7252 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7253 NETIF_F_TSO_ECN);
b11d6213
MC		 7254 return 0;
7255}
7256
14ab9b86 7257static struct {
b6016b76 7258 char string[ETH_GSTRING_LEN];
790dab2f 7259} bnx2_stats_str_arr[] = {
b6016b76
MC		 7260 { "rx_bytes" },
7261 { "rx_error_bytes" },
7262 { "tx_bytes" },
7263 { "tx_error_bytes" },
7264 { "rx_ucast_packets" },
7265 { "rx_mcast_packets" },
7266 { "rx_bcast_packets" },
7267 { "tx_ucast_packets" },
7268 { "tx_mcast_packets" },
7269 { "tx_bcast_packets" },
7270 { "tx_mac_errors" },
7271 { "tx_carrier_errors" },
7272 { "rx_crc_errors" },
7273 { "rx_align_errors" },
7274 { "tx_single_collisions" },
7275 { "tx_multi_collisions" },
7276 { "tx_deferred" },
7277 { "tx_excess_collisions" },
7278 { "tx_late_collisions" },
7279 { "tx_total_collisions" },
7280 { "rx_fragments" },
7281 { "rx_jabbers" },
7282 { "rx_undersize_packets" },
7283 { "rx_oversize_packets" },
7284 { "rx_64_byte_packets" },
7285 { "rx_65_to_127_byte_packets" },
7286 { "rx_128_to_255_byte_packets" },
7287 { "rx_256_to_511_byte_packets" },
7288 { "rx_512_to_1023_byte_packets" },
7289 { "rx_1024_to_1522_byte_packets" },
7290 { "rx_1523_to_9022_byte_packets" },
7291 { "tx_64_byte_packets" },
7292 { "tx_65_to_127_byte_packets" },
7293 { "tx_128_to_255_byte_packets" },
7294 { "tx_256_to_511_byte_packets" },
7295 { "tx_512_to_1023_byte_packets" },
7296 { "tx_1024_to_1522_byte_packets" },
7297 { "tx_1523_to_9022_byte_packets" },
7298 { "rx_xon_frames" },
7299 { "rx_xoff_frames" },
7300 { "tx_xon_frames" },
7301 { "tx_xoff_frames" },
7302 { "rx_mac_ctrl_frames" },
7303 { "rx_filtered_packets" },
790dab2f 7304 { "rx_ftq_discards" },
b6016b76 7305 { "rx_discards" },
cea94db9 7306 { "rx_fw_discards" },
b6016b76
MC		 7307};
7308
790dab2f
MC		 7309#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7310 sizeof(bnx2_stats_str_arr[0]))
7311
b6016b76
MC		 7312#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7313
f71e1309 7314static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7315 STATS_OFFSET32(stat_IfHCInOctets_hi),
7316 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7317 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7318 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7319 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7320 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7321 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7322 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7323 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7324 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7325 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7326 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7327 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7328 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7329 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7330 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7331 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7332 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7333 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7334 STATS_OFFSET32(stat_EtherStatsCollisions),
7335 STATS_OFFSET32(stat_EtherStatsFragments),
7336 STATS_OFFSET32(stat_EtherStatsJabbers),
7337 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7338 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7339 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7340 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7341 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7342 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7343 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7344 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7345 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7346 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7347 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7348 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7349 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7350 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7351 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7352 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7353 STATS_OFFSET32(stat_XonPauseFramesReceived),
7354 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7355 STATS_OFFSET32(stat_OutXonSent),
7356 STATS_OFFSET32(stat_OutXoffSent),
7357 STATS_OFFSET32(stat_MacControlFramesReceived),
7358 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7359 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7360 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7361 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7362};
7363
7364/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7365 * skipped because of errata.
6aa20a22 7366 */
14ab9b86 7367static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7368 8,0,8,8,8,8,8,8,8,8,
7369 4,0,4,4,4,4,4,4,4,4,
7370 4,4,4,4,4,4,4,4,4,4,
7371 4,4,4,4,4,4,4,4,4,4,
790dab2f 7372 4,4,4,4,4,4,4,
b6016b76
MC		 7373};
7374
5b0c76ad
MC		 7375static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7376 8,0,8,8,8,8,8,8,8,8,
7377 4,4,4,4,4,4,4,4,4,4,
7378 4,4,4,4,4,4,4,4,4,4,
7379 4,4,4,4,4,4,4,4,4,4,
790dab2f 7380 4,4,4,4,4,4,4,
5b0c76ad
MC		 7381};
7382
b6016b76
MC		 7383#define BNX2_NUM_TESTS 6
7384
14ab9b86 7385static struct {
b6016b76
MC		 7386 char string[ETH_GSTRING_LEN];
7387} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7388 { "register_test (offline)" },
7389 { "memory_test (offline)" },
7390 { "loopback_test (offline)" },
7391 { "nvram_test (online)" },
7392 { "interrupt_test (online)" },
7393 { "link_test (online)" },
7394};
7395
7396static int
b9f2c044 7397bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7398{
b9f2c044
JG		 7399 switch (sset) {
7400 case ETH_SS_TEST:
7401 return BNX2_NUM_TESTS;
7402 case ETH_SS_STATS:
7403 return BNX2_NUM_STATS;
7404 default:
7405 return -EOPNOTSUPP;
7406 }
b6016b76
MC		 7407}
7408
7409static void
7410bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7411{
972ec0d4 7412 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7413
9f52b564
MC		 7414 bnx2_set_power_state(bp, PCI_D0);
7415
b6016b76
MC		 7416 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7417 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7418 int i;
7419
212f9934 7420 bnx2_netif_stop(bp, true);
b6016b76
MC		 7421 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7422 bnx2_free_skbs(bp);
7423
7424 if (bnx2_test_registers(bp) != 0) {
7425 buf[0] = 1;
7426 etest->flags |= ETH_TEST_FL_FAILED;
7427 }
7428 if (bnx2_test_memory(bp) != 0) {
7429 buf[1] = 1;
7430 etest->flags |= ETH_TEST_FL_FAILED;
7431 }
bc5a0690 7432 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7433 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7434
9f52b564
MC		 7435 if (!netif_running(bp->dev))
7436 bnx2_shutdown_chip(bp);
b6016b76 7437 else {
9a120bc5 7438 bnx2_init_nic(bp, 1);
212f9934 7439 bnx2_netif_start(bp, true);
b6016b76
MC		 7440 }
7441
7442 /* wait for link up */
80be4434
MC		 7443 for (i = 0; i < 7; i++) {
7444 if (bp->link_up)
7445 break;
7446 msleep_interruptible(1000);
7447 }
b6016b76
MC		 7448 }
7449
7450 if (bnx2_test_nvram(bp) != 0) {
7451 buf[3] = 1;
7452 etest->flags |= ETH_TEST_FL_FAILED;
7453 }
7454 if (bnx2_test_intr(bp) != 0) {
7455 buf[4] = 1;
7456 etest->flags |= ETH_TEST_FL_FAILED;
7457 }
7458
7459 if (bnx2_test_link(bp) != 0) {
7460 buf[5] = 1;
7461 etest->flags |= ETH_TEST_FL_FAILED;
7462
7463 }
9f52b564
MC		 7464 if (!netif_running(bp->dev))
7465 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7466}
7467
7468static void
7469bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7470{
7471 switch (stringset) {
7472 case ETH_SS_STATS:
7473 memcpy(buf, bnx2_stats_str_arr,
7474 sizeof(bnx2_stats_str_arr));
7475 break;
7476 case ETH_SS_TEST:
7477 memcpy(buf, bnx2_tests_str_arr,
7478 sizeof(bnx2_tests_str_arr));
7479 break;
7480 }
7481}
7482
b6016b76
MC		 7483static void
7484bnx2_get_ethtool_stats(struct net_device *dev,
7485 struct ethtool_stats *stats, u64 *buf)
7486{
972ec0d4 7487 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7488 int i;
7489 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7490 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7491 u8 *stats_len_arr = NULL;
b6016b76
MC		 7492
7493 if (hw_stats == NULL) {
7494 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7495 return;
7496 }
7497
5b0c76ad
MC		 7498 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7499 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7500 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7501 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7502 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7503 else
7504 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7505
7506 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7507 unsigned long offset;
7508
b6016b76
MC		 7509 if (stats_len_arr[i] == 0) {
7510 /* skip this counter */
7511 buf[i] = 0;
7512 continue;
7513 }
354fcd77
MC		 7514
7515 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7516 if (stats_len_arr[i] == 4) {
7517 /* 4-byte counter */
354fcd77
MC		 7518 buf[i] = (u64) *(hw_stats + offset) +
7519 *(temp_stats + offset);
b6016b76
MC		 7520 continue;
7521 }
7522 /* 8-byte counter */
354fcd77
MC		 7523 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7524 *(hw_stats + offset + 1) +
7525 (((u64) *(temp_stats + offset)) << 32) +
7526 *(temp_stats + offset + 1);
b6016b76
MC		 7527 }
7528}
7529
7530static int
7531bnx2_phys_id(struct net_device *dev, u32 data)
7532{
972ec0d4 7533 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7534 int i;
7535 u32 save;
7536
9f52b564
MC		 7537 bnx2_set_power_state(bp, PCI_D0);
7538
b6016b76
MC		 7539 if (data == 0)
7540 data = 2;
7541
7542 save = REG_RD(bp, BNX2_MISC_CFG);
7543 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7544
7545 for (i = 0; i < (data * 2); i++) {
7546 if ((i % 2) == 0) {
7547 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7548 }
7549 else {
7550 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7551 BNX2_EMAC_LED_1000MB_OVERRIDE |
7552 BNX2_EMAC_LED_100MB_OVERRIDE |
7553 BNX2_EMAC_LED_10MB_OVERRIDE |
7554 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7555 BNX2_EMAC_LED_TRAFFIC);
7556 }
7557 msleep_interruptible(500);
7558 if (signal_pending(current))
7559 break;
7560 }
7561 REG_WR(bp, BNX2_EMAC_LED, 0);
7562 REG_WR(bp, BNX2_MISC_CFG, save);
9f52b564
MC		 7563
7564 if (!netif_running(dev))
7565 bnx2_set_power_state(bp, PCI_D3hot);
7566
b6016b76
MC		 7567 return 0;
7568}
7569
4666f87a
MC		 7570static int
7571bnx2_set_tx_csum(struct net_device *dev, u32 data)
7572{
7573 struct bnx2 *bp = netdev_priv(dev);
7574
7575 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 7576 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 7577 else
7578 return (ethtool_op_set_tx_csum(dev, data));
7579}
7580
fdc8541d
MC		 7581static int
7582bnx2_set_flags(struct net_device *dev, u32 data)
7583{
7584 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
7585}
7586
7282d491 7587static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7588 .get_settings = bnx2_get_settings,
7589 .set_settings = bnx2_set_settings,
7590 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7591 .get_regs_len = bnx2_get_regs_len,
7592 .get_regs = bnx2_get_regs,
b6016b76
MC		 7593 .get_wol = bnx2_get_wol,
7594 .set_wol = bnx2_set_wol,
7595 .nway_reset = bnx2_nway_reset,
7959ea25 7596 .get_link = bnx2_get_link,
b6016b76
MC		 7597 .get_eeprom_len = bnx2_get_eeprom_len,
7598 .get_eeprom = bnx2_get_eeprom,
7599 .set_eeprom = bnx2_set_eeprom,
7600 .get_coalesce = bnx2_get_coalesce,
7601 .set_coalesce = bnx2_set_coalesce,
7602 .get_ringparam = bnx2_get_ringparam,
7603 .set_ringparam = bnx2_set_ringparam,
7604 .get_pauseparam = bnx2_get_pauseparam,
7605 .set_pauseparam = bnx2_set_pauseparam,
7606 .get_rx_csum = bnx2_get_rx_csum,
7607 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 7608 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 7609 .set_sg = ethtool_op_set_sg,
b11d6213 7610 .set_tso = bnx2_set_tso,
b6016b76
MC		 7611 .self_test = bnx2_self_test,
7612 .get_strings = bnx2_get_strings,
7613 .phys_id = bnx2_phys_id,
b6016b76 7614 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7615 .get_sset_count = bnx2_get_sset_count,
fdc8541d
MC		 7616 .set_flags = bnx2_set_flags,
7617 .get_flags = ethtool_op_get_flags,
b6016b76
MC		 7618};
7619
7620/* Called with rtnl_lock */
7621static int
7622bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7623{
14ab9b86 7624 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7625 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7626 int err;
7627
7628 switch(cmd) {
7629 case SIOCGMIIPHY:
7630 data->phy_id = bp->phy_addr;
7631
7632 /* fallthru */
7633 case SIOCGMIIREG: {
7634 u32 mii_regval;
7635
583c28e5 7636 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7637 return -EOPNOTSUPP;
7638
dad3e452
MC		 7639 if (!netif_running(dev))
7640 return -EAGAIN;
7641
c770a65c 7642 spin_lock_bh(&bp->phy_lock);
b6016b76 7643 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7644 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7645
7646 data->val_out = mii_regval;
7647
7648 return err;
7649 }
7650
7651 case SIOCSMIIREG:
583c28e5 7652 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7653 return -EOPNOTSUPP;
7654
dad3e452
MC		 7655 if (!netif_running(dev))
7656 return -EAGAIN;
7657
c770a65c 7658 spin_lock_bh(&bp->phy_lock);
b6016b76 7659 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7660 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7661
7662 return err;
7663
7664 default:
7665 /* do nothing */
7666 break;
7667 }
7668 return -EOPNOTSUPP;
7669}
7670
7671/* Called with rtnl_lock */
7672static int
7673bnx2_change_mac_addr(struct net_device *dev, void *p)
7674{
7675 struct sockaddr *addr = p;
972ec0d4 7676 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7677
73eef4cd
MC		 7678 if (!is_valid_ether_addr(addr->sa_data))
7679 return -EINVAL;
7680
b6016b76
MC		 7681 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7682 if (netif_running(dev))
5fcaed01 7683 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7684
7685 return 0;
7686}
7687
7688/* Called with rtnl_lock */
7689static int
7690bnx2_change_mtu(struct net_device *dev, int new_mtu)
7691{
972ec0d4 7692 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7693
7694 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7695 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7696 return -EINVAL;
7697
7698 dev->mtu = new_mtu;
5d5d0015 7699 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 7700}
7701
257ddbda 7702#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7703static void
7704poll_bnx2(struct net_device *dev)
7705{
972ec0d4 7706 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7707 int i;
b6016b76 7708
b2af2c1d 7709 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7710 struct bnx2_irq *irq = &bp->irq_tbl[i];
7711
7712 disable_irq(irq->vector);
7713 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7714 enable_irq(irq->vector);
b2af2c1d 7715 }
b6016b76
MC		 7716}
7717#endif
7718
253c8b75
MC		 7719static void __devinit
7720bnx2_get_5709_media(struct bnx2 *bp)
7721{
7722 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7723 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7724 u32 strap;
7725
7726 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7727 return;
7728 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7729 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7730 return;
7731 }
7732
7733 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7734 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7735 else
7736 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7737
7738 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7739 switch (strap) {
7740 case 0x4:
7741 case 0x5:
7742 case 0x6:
583c28e5 7743 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7744 return;
7745 }
7746 } else {
7747 switch (strap) {
7748 case 0x1:
7749 case 0x2:
7750 case 0x4:
583c28e5 7751 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7752 return;
7753 }
7754 }
7755}
7756
883e5151
MC		 7757static void __devinit
7758bnx2_get_pci_speed(struct bnx2 *bp)
7759{
7760 u32 reg;
7761
7762 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7763 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7764 u32 clkreg;
7765
f86e82fb 7766 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7767
7768 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7769
7770 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7771 switch (clkreg) {
7772 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7773 bp->bus_speed_mhz = 133;
7774 break;
7775
7776 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7777 bp->bus_speed_mhz = 100;
7778 break;
7779
7780 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7781 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7782 bp->bus_speed_mhz = 66;
7783 break;
7784
7785 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7786 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7787 bp->bus_speed_mhz = 50;
7788 break;
7789
7790 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7791 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7792 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7793 bp->bus_speed_mhz = 33;
7794 break;
7795 }
7796 }
7797 else {
7798 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7799 bp->bus_speed_mhz = 66;
7800 else
7801 bp->bus_speed_mhz = 33;
7802 }
7803
7804 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7805 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7806
7807}
7808
76d99061
MC		 7809static void __devinit
7810bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7811{
df25bc38 7812 int rc, i, j;
76d99061 7813 u8 *data;
df25bc38 7814 unsigned int block_end, rosize, len;
76d99061 7815
012093f6
MC		 7816#define BNX2_VPD_NVRAM_OFFSET 0x300
7817#define BNX2_VPD_LEN 128
76d99061
MC		 7818#define BNX2_MAX_VER_SLEN 30
7819
7820 data = kmalloc(256, GFP_KERNEL);
7821 if (!data)
7822 return;
7823
012093f6
MC		 7824 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7825 BNX2_VPD_LEN);
76d99061
MC		 7826 if (rc)
7827 goto vpd_done;
7828
012093f6
MC		 7829 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7830 data[i] = data[i + BNX2_VPD_LEN + 3];
7831 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7832 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7833 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 7834 }
7835
df25bc38
MC		 7836 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7837 if (i < 0)
7838 goto vpd_done;
76d99061 7839
df25bc38
MC		 7840 rosize = pci_vpd_lrdt_size(&data[i]);
7841 i += PCI_VPD_LRDT_TAG_SIZE;
7842 block_end = i + rosize;
76d99061 7843
df25bc38
MC		 7844 if (block_end > BNX2_VPD_LEN)
7845 goto vpd_done;
76d99061 7846
df25bc38
MC		 7847 j = pci_vpd_find_info_keyword(data, i, rosize,
7848 PCI_VPD_RO_KEYWORD_MFR_ID);
7849 if (j < 0)
7850 goto vpd_done;
76d99061 7851
df25bc38 7852 len = pci_vpd_info_field_size(&data[j]);
76d99061 7853
df25bc38
MC		 7854 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7855 if (j + len > block_end || len != 4 ||
7856 memcmp(&data[j], "1028", 4))
7857 goto vpd_done;
4067a854 7858
df25bc38
MC		 7859 j = pci_vpd_find_info_keyword(data, i, rosize,
7860 PCI_VPD_RO_KEYWORD_VENDOR0);
7861 if (j < 0)
7862 goto vpd_done;
4067a854 7863
df25bc38 7864 len = pci_vpd_info_field_size(&data[j]);
4067a854 7865
df25bc38
MC		 7866 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7867 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 7868 goto vpd_done;
df25bc38
MC		 7869
7870 memcpy(bp->fw_version, &data[j], len);
7871 bp->fw_version[len] = ' ';
76d99061
MC		 7872
7873vpd_done:
7874 kfree(data);
7875}
7876
b6016b76
MC		 7877static int __devinit
7878bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7879{
7880 struct bnx2 *bp;
7881 unsigned long mem_len;
58fc2ea4 7882 int rc, i, j;
b6016b76 7883 u32 reg;
40453c83 7884 u64 dma_mask, persist_dma_mask;
b6016b76 7885
b6016b76 7886 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7887 bp = netdev_priv(dev);
b6016b76
MC		 7888
7889 bp->flags = 0;
7890 bp->phy_flags = 0;
7891
354fcd77
MC		 7892 bp->temp_stats_blk =
7893 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7894
7895 if (bp->temp_stats_blk == NULL) {
7896 rc = -ENOMEM;
7897 goto err_out;
7898 }
7899
b6016b76
MC		 7900 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7901 rc = pci_enable_device(pdev);
7902 if (rc) {
3a9c6a49 7903 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 7904 goto err_out;
7905 }
7906
7907 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7908 dev_err(&pdev->dev,
3a9c6a49 7909 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 7910 rc = -ENODEV;
7911 goto err_out_disable;
7912 }
7913
7914 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7915 if (rc) {
3a9c6a49 7916 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 7917 goto err_out_disable;
7918 }
7919
7920 pci_set_master(pdev);
6ff2da49 7921 pci_save_state(pdev);
b6016b76
MC		 7922
7923 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7924 if (bp->pm_cap == 0) {
9b91cf9d 7925 dev_err(&pdev->dev,
3a9c6a49 7926 "Cannot find power management capability, aborting\n");
b6016b76
MC		 7927 rc = -EIO;
7928 goto err_out_release;
7929 }
7930
b6016b76
MC		 7931 bp->dev = dev;
7932 bp->pdev = pdev;
7933
7934 spin_lock_init(&bp->phy_lock);
1b8227c4 7935 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 7936#ifdef BCM_CNIC
7937 mutex_init(&bp->cnic_lock);
7938#endif
c4028958 7939 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7940
7941 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
4edd473f 7942 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
b6016b76
MC		 7943 dev->mem_end = dev->mem_start + mem_len;
7944 dev->irq = pdev->irq;
7945
7946 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7947
7948 if (!bp->regview) {
3a9c6a49 7949 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 7950 rc = -ENOMEM;
7951 goto err_out_release;
7952 }
7953
7954 /* Configure byte swap and enable write to the reg_window registers.
7955 * Rely on CPU to do target byte swapping on big endian systems
7956 * The chip's target access swapping will not swap all accesses
7957 */
7958 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7959 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7960 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7961
829ca9a3 7962 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7963
7964 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7965
883e5151
MC		 7966 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7967 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7968 dev_err(&pdev->dev,
3a9c6a49 7969 "Cannot find PCIE capability, aborting\n");
883e5151
MC		 7970 rc = -EIO;
7971 goto err_out_unmap;
7972 }
f86e82fb 7973 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7974 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7975 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7976 } else {
59b47d8a
MC		 7977 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7978 if (bp->pcix_cap == 0) {
7979 dev_err(&pdev->dev,
3a9c6a49 7980 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 7981 rc = -EIO;
7982 goto err_out_unmap;
7983 }
61d9e3fa 7984 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 7985 }
7986
b4b36042
MC		 7987 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7988 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7989 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7990 }
7991
8e6a72c4
MC		 7992 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7993 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7994 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7995 }
7996
40453c83
MC		 7997 /* 5708 cannot support DMA addresses > 40-bit. */
7998 if (CHIP_NUM(bp) == CHIP_NUM_5708)
50cf156a 7999 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 8000 else
6a35528a 8001 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 8002
8003 /* Configure DMA attributes. */
8004 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8005 dev->features |= NETIF_F_HIGHDMA;
8006 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8007 if (rc) {
8008 dev_err(&pdev->dev,
3a9c6a49 8009 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 8010 goto err_out_unmap;
8011 }
284901a9 8012 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 8013 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 8014 goto err_out_unmap;
8015 }
8016
f86e82fb 8017 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8018 bnx2_get_pci_speed(bp);
b6016b76
MC		 8019
8020 /* 5706A0 may falsely detect SERR and PERR. */
8021 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8022 reg = REG_RD(bp, PCI_COMMAND);
8023 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8024 REG_WR(bp, PCI_COMMAND, reg);
8025 }
8026 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 8027 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8028
9b91cf9d 8029 dev_err(&pdev->dev,
3a9c6a49 8030 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8031 goto err_out_unmap;
8032 }
8033
8034 bnx2_init_nvram(bp);
8035
2726d6e1 8036 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 8037
8038 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 8039 BNX2_SHM_HDR_SIGNATURE_SIG) {
8040 u32 off = PCI_FUNC(pdev->devfn) << 2;
8041
2726d6e1 8042 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8043 } else
e3648b3d
MC		 8044 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8045
b6016b76
MC		 8046 /* Get the permanent MAC address. First we need to make sure the
8047 * firmware is actually running.
8048 */
2726d6e1 8049 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8050
8051 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8052 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8053 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8054 rc = -ENODEV;
8055 goto err_out_unmap;
8056 }
8057
76d99061
MC		 8058 bnx2_read_vpd_fw_ver(bp);
8059
8060 j = strlen(bp->fw_version);
2726d6e1 8061 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8062 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8063 u8 num, k, skip0;
8064
76d99061
MC		 8065 if (i == 0) {
8066 bp->fw_version[j++] = 'b';
8067 bp->fw_version[j++] = 'c';
8068 bp->fw_version[j++] = ' ';
8069 }
58fc2ea4
MC		 8070 num = (u8) (reg >> (24 - (i * 8)));
8071 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8072 if (num >= k || !skip0 || k == 1) {
8073 bp->fw_version[j++] = (num / k) + '0';
8074 skip0 = 0;
8075 }
8076 }
8077 if (i != 2)
8078 bp->fw_version[j++] = '.';
8079 }
2726d6e1 8080 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8081 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8082 bp->wol = 1;
8083
8084 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8085 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8086
8087 for (i = 0; i < 30; i++) {
2726d6e1 8088 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8089 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8090 break;
8091 msleep(10);
8092 }
8093 }
2726d6e1 8094 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8095 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8096 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8097 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8098 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8099
76d99061
MC		 8100 if (j < 32)
8101 bp->fw_version[j++] = ' ';
8102 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8103 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 8104 reg = swab32(reg);
8105 memcpy(&bp->fw_version[j], &reg, 4);
8106 j += 4;
8107 }
8108 }
b6016b76 8109
2726d6e1 8110 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8111 bp->mac_addr[0] = (u8) (reg >> 8);
8112 bp->mac_addr[1] = (u8) reg;
8113
2726d6e1 8114 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8115 bp->mac_addr[2] = (u8) (reg >> 24);
8116 bp->mac_addr[3] = (u8) (reg >> 16);
8117 bp->mac_addr[4] = (u8) (reg >> 8);
8118 bp->mac_addr[5] = (u8) reg;
8119
8120 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 8121 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 8122
8123 bp->rx_csum = 1;
8124
cf7474a6 8125 bp->tx_quick_cons_trip_int = 2;
b6016b76 8126 bp->tx_quick_cons_trip = 20;
cf7474a6 8127 bp->tx_ticks_int = 18;
b6016b76 8128 bp->tx_ticks = 80;
6aa20a22 8129
cf7474a6
MC		 8130 bp->rx_quick_cons_trip_int = 2;
8131 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8132 bp->rx_ticks_int = 18;
8133 bp->rx_ticks = 18;
8134
7ea6920e 8135 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8136
ac392abc 8137 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8138
5b0c76ad
MC		 8139 bp->phy_addr = 1;
8140
b6016b76 8141 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 8142 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8143 bnx2_get_5709_media(bp);
8144 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 8145 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8146
0d8a6571 8147 bp->phy_port = PORT_TP;
583c28e5 8148 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8149 bp->phy_port = PORT_FIBRE;
2726d6e1 8150 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8151 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8152 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8153 bp->wol = 0;
8154 }
38ea3686
MC		 8155 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8156 /* Don't do parallel detect on this board because of
8157 * some board problems. The link will not go down
8158 * if we do parallel detect.
8159 */
8160 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8161 pdev->subsystem_device == 0x310c)
8162 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8163 } else {
5b0c76ad 8164 bp->phy_addr = 2;
5b0c76ad 8165 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8166 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8167 }
261dd5ca
MC		 8168 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8169 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 8170 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 8171 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8172 (CHIP_REV(bp) == CHIP_REV_Ax ||
8173 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 8174 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8175
7c62e83b
MC		 8176 bnx2_init_fw_cap(bp);
8177
16088272
MC		 8178 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8179 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5ec6d7bf
MC		 8180 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8181 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8182 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8183 bp->wol = 0;
8184 }
dda1e390 8185
b6016b76
MC		 8186 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8187 bp->tx_quick_cons_trip_int =
8188 bp->tx_quick_cons_trip;
8189 bp->tx_ticks_int = bp->tx_ticks;
8190 bp->rx_quick_cons_trip_int =
8191 bp->rx_quick_cons_trip;
8192 bp->rx_ticks_int = bp->rx_ticks;
8193 bp->comp_prod_trip_int = bp->comp_prod_trip;
8194 bp->com_ticks_int = bp->com_ticks;
8195 bp->cmd_ticks_int = bp->cmd_ticks;
8196 }
8197
f9317a40
MC		 8198 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8199 *
8200 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8201 * with byte enables disabled on the unused 32-bit word. This is legal
8202 * but causes problems on the AMD 8132 which will eventually stop
8203 * responding after a while.
8204 *
8205 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8206 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 8207 */
8208 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8209 struct pci_dev *amd_8132 = NULL;
8210
8211 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8212 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8213 amd_8132))) {
f9317a40 8214
44c10138
AK		 8215 if (amd_8132->revision >= 0x10 &&
8216 amd_8132->revision <= 0x13) {
f9317a40
MC		 8217 disable_msi = 1;
8218 pci_dev_put(amd_8132);
8219 break;
8220 }
8221 }
8222 }
8223
deaf391b 8224 bnx2_set_default_link(bp);
b6016b76
MC		 8225 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8226
cd339a0e 8227 init_timer(&bp->timer);
ac392abc 8228 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8229 bp->timer.data = (unsigned long) bp;
8230 bp->timer.function = bnx2_timer;
8231
b6016b76
MC		 8232 return 0;
8233
8234err_out_unmap:
8235 if (bp->regview) {
8236 iounmap(bp->regview);
73eef4cd 8237 bp->regview = NULL;
b6016b76
MC		 8238 }
8239
8240err_out_release:
8241 pci_release_regions(pdev);
8242
8243err_out_disable:
8244 pci_disable_device(pdev);
8245 pci_set_drvdata(pdev, NULL);
8246
8247err_out:
8248 return rc;
8249}
8250
883e5151
MC		 8251static char * __devinit
8252bnx2_bus_string(struct bnx2 *bp, char *str)
8253{
8254 char *s = str;
8255
f86e82fb 8256 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8257 s += sprintf(s, "PCI Express");
8258 } else {
8259 s += sprintf(s, "PCI");
f86e82fb 8260 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8261 s += sprintf(s, "-X");
f86e82fb 8262 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8263 s += sprintf(s, " 32-bit");
8264 else
8265 s += sprintf(s, " 64-bit");
8266 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8267 }
8268 return str;
8269}
8270
f048fa9c
MC		 8271static void
8272bnx2_del_napi(struct bnx2 *bp)
8273{
8274 int i;
8275
8276 for (i = 0; i < bp->irq_nvecs; i++)
8277 netif_napi_del(&bp->bnx2_napi[i].napi);
8278}
8279
8280static void
35efa7c1
MC		 8281bnx2_init_napi(struct bnx2 *bp)
8282{
b4b36042 8283 int i;
35efa7c1 8284
4327ba43 8285 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8286 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8287 int (*poll)(struct napi_struct *, int);
8288
8289 if (i == 0)
8290 poll = bnx2_poll;
8291 else
f0ea2e63 8292 poll = bnx2_poll_msix;
35e9010b
MC		 8293
8294 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8295 bnapi->bp = bp;
8296 }
35efa7c1
MC		 8297}
8298
0421eae6
SH		 8299static const struct net_device_ops bnx2_netdev_ops = {
8300 .ndo_open = bnx2_open,
8301 .ndo_start_xmit = bnx2_start_xmit,
8302 .ndo_stop = bnx2_close,
5d07bf26 8303 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8304 .ndo_set_rx_mode = bnx2_set_rx_mode,
8305 .ndo_do_ioctl = bnx2_ioctl,
8306 .ndo_validate_addr = eth_validate_addr,
8307 .ndo_set_mac_address = bnx2_change_mac_addr,
8308 .ndo_change_mtu = bnx2_change_mtu,
8309 .ndo_tx_timeout = bnx2_tx_timeout,
8310#ifdef BCM_VLAN
8311 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8312#endif
257ddbda 8313#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8314 .ndo_poll_controller = poll_bnx2,
8315#endif
8316};
8317
72dccb01
ED		 8318static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8319{
8320#ifdef BCM_VLAN
8321 dev->vlan_features |= flags;
8322#endif
8323}
8324
b6016b76
MC		 8325static int __devinit
8326bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8327{
8328 static int version_printed = 0;
8329 struct net_device *dev = NULL;
8330 struct bnx2 *bp;
0795af57 8331 int rc;
883e5151 8332 char str[40];
b6016b76
MC		 8333
8334 if (version_printed++ == 0)
3a9c6a49 8335 pr_info("%s", version);
b6016b76
MC		 8336
8337 /* dev zeroed in init_etherdev */
706bf240 8338 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8339
8340 if (!dev)
8341 return -ENOMEM;
8342
8343 rc = bnx2_init_board(pdev, dev);
8344 if (rc < 0) {
8345 free_netdev(dev);
8346 return rc;
8347 }
8348
0421eae6 8349 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8350 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8351 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8352
972ec0d4 8353 bp = netdev_priv(dev);
b6016b76 8354
1b2f922f
MC		 8355 pci_set_drvdata(pdev, dev);
8356
57579f76
MC		 8357 rc = bnx2_request_firmware(bp);
8358 if (rc)
8359 goto error;
8360
1b2f922f
MC		 8361 memcpy(dev->dev_addr, bp->mac_addr, 6);
8362 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 8363
fdc8541d
MC		 8364 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO |
8365 NETIF_F_RXHASH;
72dccb01
ED		 8366 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8367 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
d212f87b 8368 dev->features |= NETIF_F_IPV6_CSUM;
72dccb01
ED		 8369 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8370 }
1b2f922f
MC		 8371#ifdef BCM_VLAN
8372 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8373#endif
8374 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
72dccb01
ED		 8375 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8376 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4666f87a 8377 dev->features |= NETIF_F_TSO6;
72dccb01
ED		 8378 vlan_features_add(dev, NETIF_F_TSO6);
8379 }
b6016b76 8380 if ((rc = register_netdev(dev))) {
9b91cf9d 8381 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8382 goto error;
b6016b76
MC		 8383 }
8384
3a9c6a49
JP		 8385 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8386 board_info[ent->driver_data].name,
8387 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8388 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8389 bnx2_bus_string(bp, str),
8390 dev->base_addr,
8391 bp->pdev->irq, dev->dev_addr);
b6016b76 8392
b6016b76 8393 return 0;
57579f76
MC		 8394
8395error:
8396 if (bp->mips_firmware)
8397 release_firmware(bp->mips_firmware);
8398 if (bp->rv2p_firmware)
8399 release_firmware(bp->rv2p_firmware);
8400
8401 if (bp->regview)
8402 iounmap(bp->regview);
8403 pci_release_regions(pdev);
8404 pci_disable_device(pdev);
8405 pci_set_drvdata(pdev, NULL);
8406 free_netdev(dev);
8407 return rc;
b6016b76
MC		 8408}
8409
8410static void __devexit
8411bnx2_remove_one(struct pci_dev *pdev)
8412{
8413 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8414 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8415
afdc08b9
MC		 8416 flush_scheduled_work();
8417
b6016b76
MC		 8418 unregister_netdev(dev);
8419
57579f76
MC		 8420 if (bp->mips_firmware)
8421 release_firmware(bp->mips_firmware);
8422 if (bp->rv2p_firmware)
8423 release_firmware(bp->rv2p_firmware);
8424
b6016b76
MC		 8425 if (bp->regview)
8426 iounmap(bp->regview);
8427
354fcd77
MC		 8428 kfree(bp->temp_stats_blk);
8429
b6016b76
MC		 8430 free_netdev(dev);
8431 pci_release_regions(pdev);
8432 pci_disable_device(pdev);
8433 pci_set_drvdata(pdev, NULL);
8434}
8435
8436static int
829ca9a3 8437bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 8438{
8439 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8440 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8441
6caebb02
MC		 8442 /* PCI register 4 needs to be saved whether netif_running() or not.
8443 * MSI address and data need to be saved if using MSI and
8444 * netif_running().
8445 */
8446 pci_save_state(pdev);
b6016b76
MC		 8447 if (!netif_running(dev))
8448 return 0;
8449
1d60290f 8450 flush_scheduled_work();
212f9934 8451 bnx2_netif_stop(bp, true);
b6016b76
MC		 8452 netif_device_detach(dev);
8453 del_timer_sync(&bp->timer);
74bf4ba3 8454 bnx2_shutdown_chip(bp);
b6016b76 8455 bnx2_free_skbs(bp);
829ca9a3 8456 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 8457 return 0;
8458}
8459
8460static int
8461bnx2_resume(struct pci_dev *pdev)
8462{
8463 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8464 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8465
6caebb02 8466 pci_restore_state(pdev);
b6016b76
MC		 8467 if (!netif_running(dev))
8468 return 0;
8469
829ca9a3 8470 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8471 netif_device_attach(dev);
9a120bc5 8472 bnx2_init_nic(bp, 1);
212f9934 8473 bnx2_netif_start(bp, true);
b6016b76
MC		 8474 return 0;
8475}
8476
6ff2da49
WX		 8477/**
8478 * bnx2_io_error_detected - called when PCI error is detected
8479 * @pdev: Pointer to PCI device
8480 * @state: The current pci connection state
8481 *
8482 * This function is called after a PCI bus error affecting
8483 * this device has been detected.
8484 */
8485static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8486 pci_channel_state_t state)
8487{
8488 struct net_device *dev = pci_get_drvdata(pdev);
8489 struct bnx2 *bp = netdev_priv(dev);
8490
8491 rtnl_lock();
8492 netif_device_detach(dev);
8493
2ec3de26
DN		 8494 if (state == pci_channel_io_perm_failure) {
8495 rtnl_unlock();
8496 return PCI_ERS_RESULT_DISCONNECT;
8497 }
8498
6ff2da49 8499 if (netif_running(dev)) {
212f9934 8500 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8501 del_timer_sync(&bp->timer);
8502 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8503 }
8504
8505 pci_disable_device(pdev);
8506 rtnl_unlock();
8507
8508 /* Request a slot slot reset. */
8509 return PCI_ERS_RESULT_NEED_RESET;
8510}
8511
8512/**
8513 * bnx2_io_slot_reset - called after the pci bus has been reset.
8514 * @pdev: Pointer to PCI device
8515 *
8516 * Restart the card from scratch, as if from a cold-boot.
8517 */
8518static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8519{
8520 struct net_device *dev = pci_get_drvdata(pdev);
8521 struct bnx2 *bp = netdev_priv(dev);
8522
8523 rtnl_lock();
8524 if (pci_enable_device(pdev)) {
8525 dev_err(&pdev->dev,
3a9c6a49 8526 "Cannot re-enable PCI device after reset\n");
6ff2da49
WX		 8527 rtnl_unlock();
8528 return PCI_ERS_RESULT_DISCONNECT;
8529 }
8530 pci_set_master(pdev);
8531 pci_restore_state(pdev);
529fab67 8532 pci_save_state(pdev);
6ff2da49
WX		 8533
8534 if (netif_running(dev)) {
8535 bnx2_set_power_state(bp, PCI_D0);
8536 bnx2_init_nic(bp, 1);
8537 }
8538
8539 rtnl_unlock();
8540 return PCI_ERS_RESULT_RECOVERED;
8541}
8542
8543/**
8544 * bnx2_io_resume - called when traffic can start flowing again.
8545 * @pdev: Pointer to PCI device
8546 *
8547 * This callback is called when the error recovery driver tells us that
8548 * its OK to resume normal operation.
8549 */
8550static void bnx2_io_resume(struct pci_dev *pdev)
8551{
8552 struct net_device *dev = pci_get_drvdata(pdev);
8553 struct bnx2 *bp = netdev_priv(dev);
8554
8555 rtnl_lock();
8556 if (netif_running(dev))
212f9934 8557 bnx2_netif_start(bp, true);
6ff2da49
WX		 8558
8559 netif_device_attach(dev);
8560 rtnl_unlock();
8561}
8562
8563static struct pci_error_handlers bnx2_err_handler = {
8564 .error_detected = bnx2_io_error_detected,
8565 .slot_reset = bnx2_io_slot_reset,
8566 .resume = bnx2_io_resume,
8567};
8568
b6016b76 8569static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8570 .name = DRV_MODULE_NAME,
8571 .id_table = bnx2_pci_tbl,
8572 .probe = bnx2_init_one,
8573 .remove = __devexit_p(bnx2_remove_one),
8574 .suspend = bnx2_suspend,
8575 .resume = bnx2_resume,
6ff2da49 8576 .err_handler = &bnx2_err_handler,
b6016b76
MC		 8577};
8578
8579static int __init bnx2_init(void)
8580{
29917620 8581 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 8582}
8583
8584static void __exit bnx2_cleanup(void)
8585{
8586 pci_unregister_driver(&bnx2_pci_driver);
8587}
8588
8589module_init(bnx2_init);
8590module_exit(bnx2_cleanup);
8591
8592
8593
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