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bnx2: Rename RX_COPY_THRESH to BNX2_RX_COPY_THRESH.
[mirror_ubuntu-bionic-kernel.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
feebb331 3 * Copyright (c) 2004-2008 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
1977f032 29#include <linux/bitops.h>
f2a4f052
MC		 30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
c86a31f4 34#include <asm/page.h>
f2a4f052
MC		 35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h>
40#define BCM_VLAN 1
41#endif
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
fba9fe91 49#include <linux/zlib.h>
f2a4f052 50
b6016b76
MC		 51#include "bnx2.h"
52#include "bnx2_fw.h"
d43584c8 53#include "bnx2_fw2.h"
b6016b76 54
110d0ef9 55#define FW_BUF_SIZE 0x10000
b3448b0b 56
b6016b76
MC		 57#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": "
705d2091
MC		 59#define DRV_MODULE_VERSION "1.7.5"
60#define DRV_MODULE_RELDATE "April 29, 2008"
b6016b76
MC		 61
62#define RUN_AT(x) (jiffies + (x))
63
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (5*HZ)
66
fefa8645 67static char version[] __devinitdata =
b6016b76
MC		 68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 71MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 72MODULE_LICENSE("GPL");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75static int disable_msi = 0;
76
77module_param(disable_msi, int, 0);
78MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
5b0c76ad
MC		 86 BCM5708,
87 BCM5708S,
bac0dff6 88 BCM5709,
27a005b8 89 BCM5709S,
b6016b76
MC		 90} board_t;
91
92/* indexed by board_t, above */
fefa8645 93static struct {
b6016b76
MC		 94 char *name;
95} board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
b6016b76
MC		 105 };
106
107static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
b6016b76
MC		 126 { 0, }
127};
128
129static struct flash_spec flash_table[] =
130{
e30372c9
MC		 131#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 133 /* Slow EEPROM */
37137709 134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
37137709
MC		 138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
b6016b76
MC		 143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
37137709 145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
37137709 151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
37137709
MC		 155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
b6016b76
MC		 216};
217
e30372c9
MC		 218static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225};
226
b6016b76
MC		 227MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
a550c99b 229static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
e89bbf10 230{
2f8af120 231 u32 diff;
e89bbf10 232
2f8af120 233 smp_mb();
faac9c4b
MC		 234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
a550c99b 238 diff = bp->tx_prod - bnapi->tx_cons;
faac9c4b
MC		 239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
e89bbf10
MC		 244 return (bp->tx_ring_size - diff);
245}
246
b6016b76
MC		 247static u32
248bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249{
1b8227c4
MC		 250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
b6016b76 253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
b6016b76
MC		 257}
258
259static void
260bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261{
1b8227c4 262 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 265 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 266}
267
2726d6e1
MC		 268static void
269bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
270{
271 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
272}
273
274static u32
275bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
276{
277 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
278}
279
b6016b76
MC		 280static void
281bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
282{
283 offset += cid_addr;
1b8227c4 284 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
286 int i;
287
288 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
289 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) {
292 u32 val;
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
295 break;
296 udelay(5);
297 }
298 } else {
299 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
300 REG_WR(bp, BNX2_CTX_DATA, val);
301 }
1b8227c4 302 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 303}
304
305static int
306bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
307{
308 u32 val1;
309 int i, ret;
310
583c28e5 311 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 312 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
313 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
314
315 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
316 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317
318 udelay(40);
319 }
320
321 val1 = (bp->phy_addr << 21) | (reg << 16) |
322 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
323 BNX2_EMAC_MDIO_COMM_START_BUSY;
324 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
325
326 for (i = 0; i < 50; i++) {
327 udelay(10);
328
329 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
330 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
331 udelay(5);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
335
336 break;
337 }
338 }
339
340 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
341 *val = 0x0;
342 ret = -EBUSY;
343 }
344 else {
345 *val = val1;
346 ret = 0;
347 }
348
583c28e5 349 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 350 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
352
353 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
354 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355
356 udelay(40);
357 }
358
359 return ret;
360}
361
362static int
363bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
364{
365 u32 val1;
366 int i, ret;
367
583c28e5 368 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 369 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
370 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
371
372 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
373 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374
375 udelay(40);
376 }
377
378 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
379 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
380 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
381 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 382
b6016b76
MC		 383 for (i = 0; i < 50; i++) {
384 udelay(10);
385
386 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
387 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
388 udelay(5);
389 break;
390 }
391 }
392
393 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
394 ret = -EBUSY;
395 else
396 ret = 0;
397
583c28e5 398 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
401
402 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
403 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404
405 udelay(40);
406 }
407
408 return ret;
409}
410
411static void
412bnx2_disable_int(struct bnx2 *bp)
413{
b4b36042
MC		 414 int i;
415 struct bnx2_napi *bnapi;
416
417 for (i = 0; i < bp->irq_nvecs; i++) {
418 bnapi = &bp->bnx2_napi[i];
419 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
420 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
421 }
b6016b76
MC		 422 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
423}
424
425static void
426bnx2_enable_int(struct bnx2 *bp)
427{
b4b36042
MC		 428 int i;
429 struct bnx2_napi *bnapi;
35efa7c1 430
b4b36042
MC		 431 for (i = 0; i < bp->irq_nvecs; i++) {
432 bnapi = &bp->bnx2_napi[i];
1269a8a6 433
b4b36042
MC		 434 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
435 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
436 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
437 bnapi->last_status_idx);
b6016b76 438
b4b36042
MC		 439 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
440 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
441 bnapi->last_status_idx);
442 }
bf5295bb 443 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 444}
445
446static void
447bnx2_disable_int_sync(struct bnx2 *bp)
448{
b4b36042
MC		 449 int i;
450
b6016b76
MC		 451 atomic_inc(&bp->intr_sem);
452 bnx2_disable_int(bp);
b4b36042
MC		 453 for (i = 0; i < bp->irq_nvecs; i++)
454 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 455}
456
35efa7c1
MC		 457static void
458bnx2_napi_disable(struct bnx2 *bp)
459{
b4b36042
MC		 460 int i;
461
462 for (i = 0; i < bp->irq_nvecs; i++)
463 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 464}
465
466static void
467bnx2_napi_enable(struct bnx2 *bp)
468{
b4b36042
MC		 469 int i;
470
471 for (i = 0; i < bp->irq_nvecs; i++)
472 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 473}
474
b6016b76
MC		 475static void
476bnx2_netif_stop(struct bnx2 *bp)
477{
478 bnx2_disable_int_sync(bp);
479 if (netif_running(bp->dev)) {
35efa7c1 480 bnx2_napi_disable(bp);
b6016b76
MC		 481 netif_tx_disable(bp->dev);
482 bp->dev->trans_start = jiffies; /* prevent tx timeout */
483 }
484}
485
486static void
487bnx2_netif_start(struct bnx2 *bp)
488{
489 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev);
35efa7c1 492 bnx2_napi_enable(bp);
b6016b76
MC		 493 bnx2_enable_int(bp);
494 }
495 }
496}
497
498static void
499bnx2_free_mem(struct bnx2 *bp)
500{
13daffa2
MC		 501 int i;
502
59b47d8a
MC		 503 for (i = 0; i < bp->ctx_pages; i++) {
504 if (bp->ctx_blk[i]) {
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
506 bp->ctx_blk[i],
507 bp->ctx_blk_mapping[i]);
508 bp->ctx_blk[i] = NULL;
509 }
510 }
b6016b76 511 if (bp->status_blk) {
0f31f994 512 pci_free_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 513 bp->status_blk, bp->status_blk_mapping);
514 bp->status_blk = NULL;
0f31f994 515 bp->stats_blk = NULL;
b6016b76
MC		 516 }
517 if (bp->tx_desc_ring) {
e343d55c 518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
521 }
b4558ea9
JJ		 522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
13daffa2
MC		 524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
e343d55c 526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 527 bp->rx_desc_ring[i],
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
530 }
531 vfree(bp->rx_buf_ring);
b4558ea9 532 bp->rx_buf_ring = NULL;
47bf4246
MC		 533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
539 }
540 if (bp->rx_pg_ring)
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
b6016b76
MC		 543}
544
545static int
546bnx2_alloc_mem(struct bnx2 *bp)
547{
0f31f994 548 int i, status_blk_size;
13daffa2 549
e343d55c 550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
b6016b76
MC		 551 if (bp->tx_buf_ring == NULL)
552 return -ENOMEM;
553
e343d55c 554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 555 &bp->tx_desc_mapping);
556 if (bp->tx_desc_ring == NULL)
557 goto alloc_mem_err;
558
e343d55c 559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
b6016b76
MC		 560 if (bp->rx_buf_ring == NULL)
561 goto alloc_mem_err;
562
e343d55c 563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
13daffa2
MC		 564
565 for (i = 0; i < bp->rx_max_ring; i++) {
566 bp->rx_desc_ring[i] =
e343d55c 567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
570 goto alloc_mem_err;
571
572 }
b6016b76 573
47bf4246
MC		 574 if (bp->rx_pg_ring_size) {
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
576 bp->rx_max_pg_ring);
577 if (bp->rx_pg_ring == NULL)
578 goto alloc_mem_err;
579
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
581 bp->rx_max_pg_ring);
582 }
583
584 for (i = 0; i < bp->rx_max_pg_ring; i++) {
585 bp->rx_pg_desc_ring[i] =
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
587 &bp->rx_pg_desc_mapping[i]);
588 if (bp->rx_pg_desc_ring[i] == NULL)
589 goto alloc_mem_err;
590
591 }
592
0f31f994
MC		 593 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 595 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 596 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
597 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 598 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block);
600
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 602 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL)
604 goto alloc_mem_err;
605
0f31f994 606 memset(bp->status_blk, 0, bp->status_stats_size);
b6016b76 607
b4b36042 608 bp->bnx2_napi[0].status_blk = bp->status_blk;
f86e82fb 609 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042
MC		 610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
612
57851d84 613 bnapi->status_blk_msix = (void *)
b4b36042
MC		 614 ((unsigned long) bp->status_blk +
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
616 bnapi->int_num = i << 24;
617 }
618 }
35efa7c1 619
0f31f994
MC		 620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
621 status_blk_size);
b6016b76 622
0f31f994 623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 624
59b47d8a
MC		 625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
626 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
627 if (bp->ctx_pages == 0)
628 bp->ctx_pages = 1;
629 for (i = 0; i < bp->ctx_pages; i++) {
630 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
631 BCM_PAGE_SIZE,
632 &bp->ctx_blk_mapping[i]);
633 if (bp->ctx_blk[i] == NULL)
634 goto alloc_mem_err;
635 }
636 }
b6016b76
MC		 637 return 0;
638
639alloc_mem_err:
640 bnx2_free_mem(bp);
641 return -ENOMEM;
642}
643
e3648b3d
MC		 644static void
645bnx2_report_fw_link(struct bnx2 *bp)
646{
647 u32 fw_link_status = 0;
648
583c28e5 649 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 650 return;
651
e3648b3d
MC		 652 if (bp->link_up) {
653 u32 bmsr;
654
655 switch (bp->line_speed) {
656 case SPEED_10:
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_10HALF;
659 else
660 fw_link_status = BNX2_LINK_STATUS_10FULL;
661 break;
662 case SPEED_100:
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_100HALF;
665 else
666 fw_link_status = BNX2_LINK_STATUS_100FULL;
667 break;
668 case SPEED_1000:
669 if (bp->duplex == DUPLEX_HALF)
670 fw_link_status = BNX2_LINK_STATUS_1000HALF;
671 else
672 fw_link_status = BNX2_LINK_STATUS_1000FULL;
673 break;
674 case SPEED_2500:
675 if (bp->duplex == DUPLEX_HALF)
676 fw_link_status = BNX2_LINK_STATUS_2500HALF;
677 else
678 fw_link_status = BNX2_LINK_STATUS_2500FULL;
679 break;
680 }
681
682 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
683
684 if (bp->autoneg) {
685 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
686
ca58c3af
MC		 687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 689
690 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 691 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 692 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
693 else
694 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
695 }
696 }
697 else
698 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
699
2726d6e1 700 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 701}
702
9b1084b8
MC		 703static char *
704bnx2_xceiver_str(struct bnx2 *bp)
705{
706 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 707 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 708 "Copper"));
709}
710
b6016b76
MC		 711static void
712bnx2_report_link(struct bnx2 *bp)
713{
714 if (bp->link_up) {
715 netif_carrier_on(bp->dev);
9b1084b8
MC		 716 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
717 bnx2_xceiver_str(bp));
b6016b76
MC		 718
719 printk("%d Mbps ", bp->line_speed);
720
721 if (bp->duplex == DUPLEX_FULL)
722 printk("full duplex");
723 else
724 printk("half duplex");
725
726 if (bp->flow_ctrl) {
727 if (bp->flow_ctrl & FLOW_CTRL_RX) {
728 printk(", receive ");
729 if (bp->flow_ctrl & FLOW_CTRL_TX)
730 printk("& transmit ");
731 }
732 else {
733 printk(", transmit ");
734 }
735 printk("flow control ON");
736 }
737 printk("\n");
738 }
739 else {
740 netif_carrier_off(bp->dev);
9b1084b8
MC		 741 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
742 bnx2_xceiver_str(bp));
b6016b76 743 }
e3648b3d
MC		 744
745 bnx2_report_fw_link(bp);
b6016b76
MC		 746}
747
748static void
749bnx2_resolve_flow_ctrl(struct bnx2 *bp)
750{
751 u32 local_adv, remote_adv;
752
753 bp->flow_ctrl = 0;
6aa20a22 754 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 755 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
756
757 if (bp->duplex == DUPLEX_FULL) {
758 bp->flow_ctrl = bp->req_flow_ctrl;
759 }
760 return;
761 }
762
763 if (bp->duplex != DUPLEX_FULL) {
764 return;
765 }
766
583c28e5 767 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 768 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
769 u32 val;
770
771 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
772 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
773 bp->flow_ctrl |= FLOW_CTRL_TX;
774 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
775 bp->flow_ctrl |= FLOW_CTRL_RX;
776 return;
777 }
778
ca58c3af
MC		 779 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
780 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 781
583c28e5 782 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 783 u32 new_local_adv = 0;
784 u32 new_remote_adv = 0;
785
786 if (local_adv & ADVERTISE_1000XPAUSE)
787 new_local_adv |= ADVERTISE_PAUSE_CAP;
788 if (local_adv & ADVERTISE_1000XPSE_ASYM)
789 new_local_adv |= ADVERTISE_PAUSE_ASYM;
790 if (remote_adv & ADVERTISE_1000XPAUSE)
791 new_remote_adv |= ADVERTISE_PAUSE_CAP;
792 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
793 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
794
795 local_adv = new_local_adv;
796 remote_adv = new_remote_adv;
797 }
798
799 /* See Table 28B-3 of 802.3ab-1999 spec. */
800 if (local_adv & ADVERTISE_PAUSE_CAP) {
801 if(local_adv & ADVERTISE_PAUSE_ASYM) {
802 if (remote_adv & ADVERTISE_PAUSE_CAP) {
803 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
804 }
805 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
806 bp->flow_ctrl = FLOW_CTRL_RX;
807 }
808 }
809 else {
810 if (remote_adv & ADVERTISE_PAUSE_CAP) {
811 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
812 }
813 }
814 }
815 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
816 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
817 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
818
819 bp->flow_ctrl = FLOW_CTRL_TX;
820 }
821 }
822}
823
27a005b8
MC		 824static int
825bnx2_5709s_linkup(struct bnx2 *bp)
826{
827 u32 val, speed;
828
829 bp->link_up = 1;
830
831 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
832 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
833 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
834
835 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
836 bp->line_speed = bp->req_line_speed;
837 bp->duplex = bp->req_duplex;
838 return 0;
839 }
840 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
841 switch (speed) {
842 case MII_BNX2_GP_TOP_AN_SPEED_10:
843 bp->line_speed = SPEED_10;
844 break;
845 case MII_BNX2_GP_TOP_AN_SPEED_100:
846 bp->line_speed = SPEED_100;
847 break;
848 case MII_BNX2_GP_TOP_AN_SPEED_1G:
849 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
850 bp->line_speed = SPEED_1000;
851 break;
852 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
853 bp->line_speed = SPEED_2500;
854 break;
855 }
856 if (val & MII_BNX2_GP_TOP_AN_FD)
857 bp->duplex = DUPLEX_FULL;
858 else
859 bp->duplex = DUPLEX_HALF;
860 return 0;
861}
862
b6016b76 863static int
5b0c76ad
MC		 864bnx2_5708s_linkup(struct bnx2 *bp)
865{
866 u32 val;
867
868 bp->link_up = 1;
869 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
870 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
871 case BCM5708S_1000X_STAT1_SPEED_10:
872 bp->line_speed = SPEED_10;
873 break;
874 case BCM5708S_1000X_STAT1_SPEED_100:
875 bp->line_speed = SPEED_100;
876 break;
877 case BCM5708S_1000X_STAT1_SPEED_1G:
878 bp->line_speed = SPEED_1000;
879 break;
880 case BCM5708S_1000X_STAT1_SPEED_2G5:
881 bp->line_speed = SPEED_2500;
882 break;
883 }
884 if (val & BCM5708S_1000X_STAT1_FD)
885 bp->duplex = DUPLEX_FULL;
886 else
887 bp->duplex = DUPLEX_HALF;
888
889 return 0;
890}
891
892static int
893bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 894{
895 u32 bmcr, local_adv, remote_adv, common;
896
897 bp->link_up = 1;
898 bp->line_speed = SPEED_1000;
899
ca58c3af 900 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
903 }
904 else {
905 bp->duplex = DUPLEX_HALF;
906 }
907
908 if (!(bmcr & BMCR_ANENABLE)) {
909 return 0;
910 }
911
ca58c3af
MC		 912 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
913 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 914
915 common = local_adv & remote_adv;
916 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
917
918 if (common & ADVERTISE_1000XFULL) {
919 bp->duplex = DUPLEX_FULL;
920 }
921 else {
922 bp->duplex = DUPLEX_HALF;
923 }
924 }
925
926 return 0;
927}
928
929static int
930bnx2_copper_linkup(struct bnx2 *bp)
931{
932 u32 bmcr;
933
ca58c3af 934 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 935 if (bmcr & BMCR_ANENABLE) {
936 u32 local_adv, remote_adv, common;
937
938 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
939 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
940
941 common = local_adv & (remote_adv >> 2);
942 if (common & ADVERTISE_1000FULL) {
943 bp->line_speed = SPEED_1000;
944 bp->duplex = DUPLEX_FULL;
945 }
946 else if (common & ADVERTISE_1000HALF) {
947 bp->line_speed = SPEED_1000;
948 bp->duplex = DUPLEX_HALF;
949 }
950 else {
ca58c3af
MC		 951 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
952 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 953
954 common = local_adv & remote_adv;
955 if (common & ADVERTISE_100FULL) {
956 bp->line_speed = SPEED_100;
957 bp->duplex = DUPLEX_FULL;
958 }
959 else if (common & ADVERTISE_100HALF) {
960 bp->line_speed = SPEED_100;
961 bp->duplex = DUPLEX_HALF;
962 }
963 else if (common & ADVERTISE_10FULL) {
964 bp->line_speed = SPEED_10;
965 bp->duplex = DUPLEX_FULL;
966 }
967 else if (common & ADVERTISE_10HALF) {
968 bp->line_speed = SPEED_10;
969 bp->duplex = DUPLEX_HALF;
970 }
971 else {
972 bp->line_speed = 0;
973 bp->link_up = 0;
974 }
975 }
976 }
977 else {
978 if (bmcr & BMCR_SPEED100) {
979 bp->line_speed = SPEED_100;
980 }
981 else {
982 bp->line_speed = SPEED_10;
983 }
984 if (bmcr & BMCR_FULLDPLX) {
985 bp->duplex = DUPLEX_FULL;
986 }
987 else {
988 bp->duplex = DUPLEX_HALF;
989 }
990 }
991
992 return 0;
993}
994
83e3fc89
MC		 995static void
996bnx2_init_rx_context0(struct bnx2 *bp)
997{
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
999
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002 val |= 0x02 << 8;
1003
1004 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005 u32 lo_water, hi_water;
1006
1007 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009 else
1010 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011 if (lo_water >= bp->rx_ring_size)
1012 lo_water = 0;
1013
1014 hi_water = bp->rx_ring_size / 4;
1015
1016 if (hi_water <= lo_water)
1017 lo_water = 0;
1018
1019 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022 if (hi_water > 0xf)
1023 hi_water = 0xf;
1024 else if (hi_water == 0)
1025 lo_water = 0;
1026 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027 }
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029}
1030
b6016b76
MC		 1031static int
1032bnx2_set_mac_link(struct bnx2 *bp)
1033{
1034 u32 val;
1035
1036 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038 (bp->duplex == DUPLEX_HALF)) {
1039 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040 }
1041
1042 /* Configure the EMAC mode register. */
1043 val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1046 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1047 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1048
1049 if (bp->link_up) {
5b0c76ad
MC		 1050 switch (bp->line_speed) {
1051 case SPEED_10:
59b47d8a
MC		 1052 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1054 break;
1055 }
1056 /* fall through */
1057 case SPEED_100:
1058 val |= BNX2_EMAC_MODE_PORT_MII;
1059 break;
1060 case SPEED_2500:
59b47d8a 1061 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1062 /* fall through */
1063 case SPEED_1000:
1064 val |= BNX2_EMAC_MODE_PORT_GMII;
1065 break;
1066 }
b6016b76
MC		 1067 }
1068 else {
1069 val |= BNX2_EMAC_MODE_PORT_GMII;
1070 }
1071
1072 /* Set the MAC to operate in the appropriate duplex mode. */
1073 if (bp->duplex == DUPLEX_HALF)
1074 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075 REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077 /* Enable/disable rx PAUSE. */
1078 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080 if (bp->flow_ctrl & FLOW_CTRL_RX)
1081 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084 /* Enable/disable tx PAUSE. */
1085 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088 if (bp->flow_ctrl & FLOW_CTRL_TX)
1089 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092 /* Acknowledge the interrupt. */
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
83e3fc89
MC		 1095 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp);
1097
b6016b76
MC		 1098 return 0;
1099}
1100
27a005b8
MC		 1101static void
1102bnx2_enable_bmsr1(struct bnx2 *bp)
1103{
583c28e5 1104 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1105 (CHIP_NUM(bp) == CHIP_NUM_5709))
1106 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107 MII_BNX2_BLK_ADDR_GP_STATUS);
1108}
1109
1110static void
1111bnx2_disable_bmsr1(struct bnx2 *bp)
1112{
583c28e5 1113 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1114 (CHIP_NUM(bp) == CHIP_NUM_5709))
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117}
1118
605a9e20
MC		 1119static int
1120bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121{
1122 u32 up1;
1123 int ret = 1;
1124
583c28e5 1125 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1126 return 0;
1127
1128 if (bp->autoneg & AUTONEG_SPEED)
1129 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
27a005b8
MC		 1131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
605a9e20
MC		 1134 bnx2_read_phy(bp, bp->mii_up1, &up1);
1135 if (!(up1 & BCM5708S_UP1_2G5)) {
1136 up1 |= BCM5708S_UP1_2G5;
1137 bnx2_write_phy(bp, bp->mii_up1, up1);
1138 ret = 0;
1139 }
1140
27a005b8
MC		 1141 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
605a9e20
MC		 1145 return ret;
1146}
1147
1148static int
1149bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150{
1151 u32 up1;
1152 int ret = 0;
1153
583c28e5 1154 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1155 return 0;
1156
27a005b8
MC		 1157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
605a9e20
MC		 1160 bnx2_read_phy(bp, bp->mii_up1, &up1);
1161 if (up1 & BCM5708S_UP1_2G5) {
1162 up1 &= ~BCM5708S_UP1_2G5;
1163 bnx2_write_phy(bp, bp->mii_up1, up1);
1164 ret = 1;
1165 }
1166
27a005b8
MC		 1167 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
605a9e20
MC		 1171 return ret;
1172}
1173
1174static void
1175bnx2_enable_forced_2g5(struct bnx2 *bp)
1176{
1177 u32 bmcr;
1178
583c28e5 1179 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1180 return;
1181
27a005b8
MC		 1182 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183 u32 val;
1184
1185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186 MII_BNX2_BLK_ADDR_SERDES_DIG);
1187 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1197 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199 }
1200
1201 if (bp->autoneg & AUTONEG_SPEED) {
1202 bmcr &= ~BMCR_ANENABLE;
1203 if (bp->req_duplex == DUPLEX_FULL)
1204 bmcr |= BMCR_FULLDPLX;
1205 }
1206 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207}
1208
1209static void
1210bnx2_disable_forced_2g5(struct bnx2 *bp)
1211{
1212 u32 bmcr;
1213
583c28e5 1214 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1215 return;
1216
27a005b8
MC		 1217 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218 u32 val;
1219
1220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221 MII_BNX2_BLK_ADDR_SERDES_DIG);
1222 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1231 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233 }
1234
1235 if (bp->autoneg & AUTONEG_SPEED)
1236 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238}
1239
b2fadeae
MC		 1240static void
1241bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242{
1243 u32 val;
1244
1245 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247 if (start)
1248 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249 else
1250 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251}
1252
b6016b76
MC		 1253static int
1254bnx2_set_link(struct bnx2 *bp)
1255{
1256 u32 bmsr;
1257 u8 link_up;
1258
80be4434 1259 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1260 bp->link_up = 1;
1261 return 0;
1262 }
1263
583c28e5 1264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1265 return 0;
1266
b6016b76
MC		 1267 link_up = bp->link_up;
1268
27a005b8
MC		 1269 bnx2_enable_bmsr1(bp);
1270 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272 bnx2_disable_bmsr1(bp);
b6016b76 1273
583c28e5 1274 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1275 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1276 u32 val, an_dbg;
b6016b76 1277
583c28e5 1278 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1279 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1280 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1281 }
b6016b76 1282 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1283
1284 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
1288 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1290 bmsr |= BMSR_LSTATUS;
1291 else
1292 bmsr &= ~BMSR_LSTATUS;
1293 }
1294
1295 if (bmsr & BMSR_LSTATUS) {
1296 bp->link_up = 1;
1297
583c28e5 1298 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1299 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300 bnx2_5706s_linkup(bp);
1301 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302 bnx2_5708s_linkup(bp);
27a005b8
MC		 1303 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304 bnx2_5709s_linkup(bp);
b6016b76
MC		 1305 }
1306 else {
1307 bnx2_copper_linkup(bp);
1308 }
1309 bnx2_resolve_flow_ctrl(bp);
1310 }
1311 else {
583c28e5 1312 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1313 (bp->autoneg & AUTONEG_SPEED))
1314 bnx2_disable_forced_2g5(bp);
b6016b76 1315
583c28e5 1316 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1317 u32 bmcr;
1318
1319 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320 bmcr |= BMCR_ANENABLE;
1321 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1322
583c28e5 1323 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1324 }
b6016b76
MC		 1325 bp->link_up = 0;
1326 }
1327
1328 if (bp->link_up != link_up) {
1329 bnx2_report_link(bp);
1330 }
1331
1332 bnx2_set_mac_link(bp);
1333
1334 return 0;
1335}
1336
1337static int
1338bnx2_reset_phy(struct bnx2 *bp)
1339{
1340 int i;
1341 u32 reg;
1342
ca58c3af 1343 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1344
1345#define PHY_RESET_MAX_WAIT 100
1346 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1347 udelay(10);
1348
ca58c3af 1349 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1350 if (!(reg & BMCR_RESET)) {
1351 udelay(20);
1352 break;
1353 }
1354 }
1355 if (i == PHY_RESET_MAX_WAIT) {
1356 return -EBUSY;
1357 }
1358 return 0;
1359}
1360
1361static u32
1362bnx2_phy_get_pause_adv(struct bnx2 *bp)
1363{
1364 u32 adv = 0;
1365
1366 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1368
583c28e5 1369 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1370 adv = ADVERTISE_1000XPAUSE;
1371 }
1372 else {
1373 adv = ADVERTISE_PAUSE_CAP;
1374 }
1375 }
1376 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1378 adv = ADVERTISE_1000XPSE_ASYM;
1379 }
1380 else {
1381 adv = ADVERTISE_PAUSE_ASYM;
1382 }
1383 }
1384 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1386 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1387 }
1388 else {
1389 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1390 }
1391 }
1392 return adv;
1393}
1394
0d8a6571
MC		 1395static int bnx2_fw_sync(struct bnx2 *, u32, int);
1396
b6016b76 1397static int
0d8a6571
MC		 1398bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1399{
1400 u32 speed_arg = 0, pause_adv;
1401
1402 pause_adv = bnx2_phy_get_pause_adv(bp);
1403
1404 if (bp->autoneg & AUTONEG_SPEED) {
1405 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406 if (bp->advertising & ADVERTISED_10baseT_Half)
1407 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408 if (bp->advertising & ADVERTISED_10baseT_Full)
1409 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410 if (bp->advertising & ADVERTISED_100baseT_Half)
1411 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412 if (bp->advertising & ADVERTISED_100baseT_Full)
1413 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1418 } else {
1419 if (bp->req_line_speed == SPEED_2500)
1420 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421 else if (bp->req_line_speed == SPEED_1000)
1422 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423 else if (bp->req_line_speed == SPEED_100) {
1424 if (bp->req_duplex == DUPLEX_FULL)
1425 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1426 else
1427 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428 } else if (bp->req_line_speed == SPEED_10) {
1429 if (bp->req_duplex == DUPLEX_FULL)
1430 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1431 else
1432 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1433 }
1434 }
1435
1436 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1438 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1439 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1440
1441 if (port == PORT_TP)
1442 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1444
2726d6e1 1445 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1446
1447 spin_unlock_bh(&bp->phy_lock);
1448 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449 spin_lock_bh(&bp->phy_lock);
1450
1451 return 0;
1452}
1453
1454static int
1455bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
b6016b76 1456{
605a9e20 1457 u32 adv, bmcr;
b6016b76
MC		 1458 u32 new_adv = 0;
1459
583c28e5 1460 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1461 return (bnx2_setup_remote_phy(bp, port));
1462
b6016b76
MC		 1463 if (!(bp->autoneg & AUTONEG_SPEED)) {
1464 u32 new_bmcr;
5b0c76ad
MC		 1465 int force_link_down = 0;
1466
605a9e20
MC		 1467 if (bp->req_line_speed == SPEED_2500) {
1468 if (!bnx2_test_and_enable_2g5(bp))
1469 force_link_down = 1;
1470 } else if (bp->req_line_speed == SPEED_1000) {
1471 if (bnx2_test_and_disable_2g5(bp))
1472 force_link_down = 1;
1473 }
ca58c3af 1474 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1475 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1476
ca58c3af 1477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1478 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1479 new_bmcr |= BMCR_SPEED1000;
605a9e20 1480
27a005b8
MC		 1481 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482 if (bp->req_line_speed == SPEED_2500)
1483 bnx2_enable_forced_2g5(bp);
1484 else if (bp->req_line_speed == SPEED_1000) {
1485 bnx2_disable_forced_2g5(bp);
1486 new_bmcr &= ~0x2000;
1487 }
1488
1489 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1490 if (bp->req_line_speed == SPEED_2500)
1491 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1492 else
1493 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1494 }
1495
b6016b76 1496 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1497 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1498 new_bmcr |= BMCR_FULLDPLX;
1499 }
1500 else {
5b0c76ad 1501 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1502 new_bmcr &= ~BMCR_FULLDPLX;
1503 }
5b0c76ad 1504 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1505 /* Force a link down visible on the other side */
1506 if (bp->link_up) {
ca58c3af 1507 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1508 ~(ADVERTISE_1000XFULL |
1509 ADVERTISE_1000XHALF));
ca58c3af 1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1511 BMCR_ANRESTART | BMCR_ANENABLE);
1512
1513 bp->link_up = 0;
1514 netif_carrier_off(bp->dev);
ca58c3af 1515 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1516 bnx2_report_link(bp);
b6016b76 1517 }
ca58c3af
MC		 1518 bnx2_write_phy(bp, bp->mii_adv, adv);
1519 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1520 } else {
1521 bnx2_resolve_flow_ctrl(bp);
1522 bnx2_set_mac_link(bp);
b6016b76
MC		 1523 }
1524 return 0;
1525 }
1526
605a9e20 1527 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1528
b6016b76
MC		 1529 if (bp->advertising & ADVERTISED_1000baseT_Full)
1530 new_adv |= ADVERTISE_1000XFULL;
1531
1532 new_adv |= bnx2_phy_get_pause_adv(bp);
1533
ca58c3af
MC		 1534 bnx2_read_phy(bp, bp->mii_adv, &adv);
1535 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1536
1537 bp->serdes_an_pending = 0;
1538 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539 /* Force a link down visible on the other side */
1540 if (bp->link_up) {
ca58c3af 1541 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1542 spin_unlock_bh(&bp->phy_lock);
1543 msleep(20);
1544 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1545 }
1546
ca58c3af
MC		 1547 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1549 BMCR_ANENABLE);
f8dd064e
MC		 1550 /* Speed up link-up time when the link partner
1551 * does not autonegotiate which is very common
1552 * in blade servers. Some blade servers use
1553 * IPMI for kerboard input and it's important
1554 * to minimize link disruptions. Autoneg. involves
1555 * exchanging base pages plus 3 next pages and
1556 * normally completes in about 120 msec.
1557 */
1558 bp->current_interval = SERDES_AN_TIMEOUT;
1559 bp->serdes_an_pending = 1;
1560 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1561 } else {
1562 bnx2_resolve_flow_ctrl(bp);
1563 bnx2_set_mac_link(bp);
b6016b76
MC		 1564 }
1565
1566 return 0;
1567}
1568
1569#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1570 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1571 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1573
1574#define ETHTOOL_ALL_COPPER_SPEED \
1575 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1576 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1577 ADVERTISED_1000baseT_Full)
1578
1579#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1581
b6016b76
MC		 1582#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1583
0d8a6571
MC		 1584static void
1585bnx2_set_default_remote_link(struct bnx2 *bp)
1586{
1587 u32 link;
1588
1589 if (bp->phy_port == PORT_TP)
2726d6e1 1590 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1591 else
2726d6e1 1592 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1593
1594 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595 bp->req_line_speed = 0;
1596 bp->autoneg |= AUTONEG_SPEED;
1597 bp->advertising = ADVERTISED_Autoneg;
1598 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599 bp->advertising |= ADVERTISED_10baseT_Half;
1600 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601 bp->advertising |= ADVERTISED_10baseT_Full;
1602 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603 bp->advertising |= ADVERTISED_100baseT_Half;
1604 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605 bp->advertising |= ADVERTISED_100baseT_Full;
1606 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607 bp->advertising |= ADVERTISED_1000baseT_Full;
1608 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609 bp->advertising |= ADVERTISED_2500baseX_Full;
1610 } else {
1611 bp->autoneg = 0;
1612 bp->advertising = 0;
1613 bp->req_duplex = DUPLEX_FULL;
1614 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615 bp->req_line_speed = SPEED_10;
1616 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617 bp->req_duplex = DUPLEX_HALF;
1618 }
1619 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620 bp->req_line_speed = SPEED_100;
1621 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622 bp->req_duplex = DUPLEX_HALF;
1623 }
1624 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625 bp->req_line_speed = SPEED_1000;
1626 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627 bp->req_line_speed = SPEED_2500;
1628 }
1629}
1630
deaf391b
MC		 1631static void
1632bnx2_set_default_link(struct bnx2 *bp)
1633{
ab59859d
HH		 1634 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1635 bnx2_set_default_remote_link(bp);
1636 return;
1637 }
0d8a6571 1638
deaf391b
MC		 1639 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1640 bp->req_line_speed = 0;
583c28e5 1641 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1642 u32 reg;
1643
1644 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1645
2726d6e1 1646 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1647 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1648 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1649 bp->autoneg = 0;
1650 bp->req_line_speed = bp->line_speed = SPEED_1000;
1651 bp->req_duplex = DUPLEX_FULL;
1652 }
1653 } else
1654 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1655}
1656
df149d70
MC		 1657static void
1658bnx2_send_heart_beat(struct bnx2 *bp)
1659{
1660 u32 msg;
1661 u32 addr;
1662
1663 spin_lock(&bp->indirect_lock);
1664 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1665 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1666 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1667 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1668 spin_unlock(&bp->indirect_lock);
1669}
1670
0d8a6571
MC		 1671static void
1672bnx2_remote_phy_event(struct bnx2 *bp)
1673{
1674 u32 msg;
1675 u8 link_up = bp->link_up;
1676 u8 old_port;
1677
2726d6e1 1678 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1679
df149d70
MC		 1680 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1681 bnx2_send_heart_beat(bp);
1682
1683 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1684
0d8a6571
MC		 1685 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1686 bp->link_up = 0;
1687 else {
1688 u32 speed;
1689
1690 bp->link_up = 1;
1691 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1692 bp->duplex = DUPLEX_FULL;
1693 switch (speed) {
1694 case BNX2_LINK_STATUS_10HALF:
1695 bp->duplex = DUPLEX_HALF;
1696 case BNX2_LINK_STATUS_10FULL:
1697 bp->line_speed = SPEED_10;
1698 break;
1699 case BNX2_LINK_STATUS_100HALF:
1700 bp->duplex = DUPLEX_HALF;
1701 case BNX2_LINK_STATUS_100BASE_T4:
1702 case BNX2_LINK_STATUS_100FULL:
1703 bp->line_speed = SPEED_100;
1704 break;
1705 case BNX2_LINK_STATUS_1000HALF:
1706 bp->duplex = DUPLEX_HALF;
1707 case BNX2_LINK_STATUS_1000FULL:
1708 bp->line_speed = SPEED_1000;
1709 break;
1710 case BNX2_LINK_STATUS_2500HALF:
1711 bp->duplex = DUPLEX_HALF;
1712 case BNX2_LINK_STATUS_2500FULL:
1713 bp->line_speed = SPEED_2500;
1714 break;
1715 default:
1716 bp->line_speed = 0;
1717 break;
1718 }
1719
0d8a6571
MC		 1720 bp->flow_ctrl = 0;
1721 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1722 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1723 if (bp->duplex == DUPLEX_FULL)
1724 bp->flow_ctrl = bp->req_flow_ctrl;
1725 } else {
1726 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1727 bp->flow_ctrl |= FLOW_CTRL_TX;
1728 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1729 bp->flow_ctrl |= FLOW_CTRL_RX;
1730 }
1731
1732 old_port = bp->phy_port;
1733 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1734 bp->phy_port = PORT_FIBRE;
1735 else
1736 bp->phy_port = PORT_TP;
1737
1738 if (old_port != bp->phy_port)
1739 bnx2_set_default_link(bp);
1740
0d8a6571
MC		 1741 }
1742 if (bp->link_up != link_up)
1743 bnx2_report_link(bp);
1744
1745 bnx2_set_mac_link(bp);
1746}
1747
1748static int
1749bnx2_set_remote_link(struct bnx2 *bp)
1750{
1751 u32 evt_code;
1752
2726d6e1 1753 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 1754 switch (evt_code) {
1755 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756 bnx2_remote_phy_event(bp);
1757 break;
1758 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1759 default:
df149d70 1760 bnx2_send_heart_beat(bp);
0d8a6571
MC		 1761 break;
1762 }
1763 return 0;
1764}
1765
b6016b76
MC		 1766static int
1767bnx2_setup_copper_phy(struct bnx2 *bp)
1768{
1769 u32 bmcr;
1770 u32 new_bmcr;
1771
ca58c3af 1772 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1773
1774 if (bp->autoneg & AUTONEG_SPEED) {
1775 u32 adv_reg, adv1000_reg;
1776 u32 new_adv_reg = 0;
1777 u32 new_adv1000_reg = 0;
1778
ca58c3af 1779 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 1780 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781 ADVERTISE_PAUSE_ASYM);
1782
1783 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784 adv1000_reg &= PHY_ALL_1000_SPEED;
1785
1786 if (bp->advertising & ADVERTISED_10baseT_Half)
1787 new_adv_reg |= ADVERTISE_10HALF;
1788 if (bp->advertising & ADVERTISED_10baseT_Full)
1789 new_adv_reg |= ADVERTISE_10FULL;
1790 if (bp->advertising & ADVERTISED_100baseT_Half)
1791 new_adv_reg |= ADVERTISE_100HALF;
1792 if (bp->advertising & ADVERTISED_100baseT_Full)
1793 new_adv_reg |= ADVERTISE_100FULL;
1794 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 1796
b6016b76
MC		 1797 new_adv_reg |= ADVERTISE_CSMA;
1798
1799 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1800
1801 if ((adv1000_reg != new_adv1000_reg) ||
1802 (adv_reg != new_adv_reg) ||
1803 ((bmcr & BMCR_ANENABLE) == 0)) {
1804
ca58c3af 1805 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 1806 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 1807 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 1808 BMCR_ANENABLE);
1809 }
1810 else if (bp->link_up) {
1811 /* Flow ctrl may have changed from auto to forced */
1812 /* or vice-versa. */
1813
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
1816 }
1817 return 0;
1818 }
1819
1820 new_bmcr = 0;
1821 if (bp->req_line_speed == SPEED_100) {
1822 new_bmcr |= BMCR_SPEED100;
1823 }
1824 if (bp->req_duplex == DUPLEX_FULL) {
1825 new_bmcr |= BMCR_FULLDPLX;
1826 }
1827 if (new_bmcr != bmcr) {
1828 u32 bmsr;
b6016b76 1829
ca58c3af
MC		 1830 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 1832
b6016b76
MC		 1833 if (bmsr & BMSR_LSTATUS) {
1834 /* Force link down */
ca58c3af 1835 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 1836 spin_unlock_bh(&bp->phy_lock);
1837 msleep(50);
1838 spin_lock_bh(&bp->phy_lock);
1839
ca58c3af
MC		 1840 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 1842 }
1843
ca58c3af 1844 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 1845
1846 /* Normally, the new speed is setup after the link has
1847 * gone down and up again. In some cases, link will not go
1848 * down so we need to set up the new speed here.
1849 */
1850 if (bmsr & BMSR_LSTATUS) {
1851 bp->line_speed = bp->req_line_speed;
1852 bp->duplex = bp->req_duplex;
1853 bnx2_resolve_flow_ctrl(bp);
1854 bnx2_set_mac_link(bp);
1855 }
27a005b8
MC		 1856 } else {
1857 bnx2_resolve_flow_ctrl(bp);
1858 bnx2_set_mac_link(bp);
b6016b76
MC		 1859 }
1860 return 0;
1861}
1862
1863static int
0d8a6571 1864bnx2_setup_phy(struct bnx2 *bp, u8 port)
b6016b76
MC		 1865{
1866 if (bp->loopback == MAC_LOOPBACK)
1867 return 0;
1868
583c28e5 1869 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 1870 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 1871 }
1872 else {
1873 return (bnx2_setup_copper_phy(bp));
1874 }
1875}
1876
27a005b8 1877static int
9a120bc5 1878bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 1879{
1880 u32 val;
1881
1882 bp->mii_bmcr = MII_BMCR + 0x10;
1883 bp->mii_bmsr = MII_BMSR + 0x10;
1884 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885 bp->mii_adv = MII_ADVERTISE + 0x10;
1886 bp->mii_lpa = MII_LPA + 0x10;
1887 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1888
1889 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 1893 if (reset_phy)
1894 bnx2_reset_phy(bp);
27a005b8
MC		 1895
1896 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1897
1898 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1899 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1900 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1901 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1902
1903 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1904 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 1905 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 1906 val |= BCM5708S_UP1_2G5;
1907 else
1908 val &= ~BCM5708S_UP1_2G5;
1909 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1910
1911 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1912 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1913 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1914 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1915
1916 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1917
1918 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1919 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1920 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1921
1922 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1923
1924 return 0;
1925}
1926
b6016b76 1927static int
9a120bc5 1928bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 1929{
1930 u32 val;
1931
9a120bc5
MC		 1932 if (reset_phy)
1933 bnx2_reset_phy(bp);
27a005b8
MC		 1934
1935 bp->mii_up1 = BCM5708S_UP1;
1936
5b0c76ad
MC		 1937 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1938 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1939 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1940
1941 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1942 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1943 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1944
1945 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1946 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1947 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1948
583c28e5 1949 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 1950 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1951 val |= BCM5708S_UP1_2G5;
1952 bnx2_write_phy(bp, BCM5708S_UP1, val);
1953 }
1954
1955 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1956 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1957 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1958 /* increase tx signal amplitude */
1959 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1960 BCM5708S_BLK_ADDR_TX_MISC);
1961 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1962 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1963 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1964 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1965 }
1966
2726d6e1 1967 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1968 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1969
1970 if (val) {
1971 u32 is_backplane;
1972
2726d6e1 1973 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 1974 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1975 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1976 BCM5708S_BLK_ADDR_TX_MISC);
1977 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1978 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1979 BCM5708S_BLK_ADDR_DIG);
1980 }
1981 }
1982 return 0;
1983}
1984
1985static int
9a120bc5 1986bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 1987{
9a120bc5
MC		 1988 if (reset_phy)
1989 bnx2_reset_phy(bp);
27a005b8 1990
583c28e5 1991 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 1992
59b47d8a
MC		 1993 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1994 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 1995
1996 if (bp->dev->mtu > 1500) {
1997 u32 val;
1998
1999 /* Set extended packet length bit */
2000 bnx2_write_phy(bp, 0x18, 0x7);
2001 bnx2_read_phy(bp, 0x18, &val);
2002 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2003
2004 bnx2_write_phy(bp, 0x1c, 0x6c00);
2005 bnx2_read_phy(bp, 0x1c, &val);
2006 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2007 }
2008 else {
2009 u32 val;
2010
2011 bnx2_write_phy(bp, 0x18, 0x7);
2012 bnx2_read_phy(bp, 0x18, &val);
2013 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2014
2015 bnx2_write_phy(bp, 0x1c, 0x6c00);
2016 bnx2_read_phy(bp, 0x1c, &val);
2017 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2018 }
2019
2020 return 0;
2021}
2022
2023static int
9a120bc5 2024bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2025{
5b0c76ad
MC		 2026 u32 val;
2027
9a120bc5
MC		 2028 if (reset_phy)
2029 bnx2_reset_phy(bp);
27a005b8 2030
583c28e5 2031 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2032 bnx2_write_phy(bp, 0x18, 0x0c00);
2033 bnx2_write_phy(bp, 0x17, 0x000a);
2034 bnx2_write_phy(bp, 0x15, 0x310b);
2035 bnx2_write_phy(bp, 0x17, 0x201f);
2036 bnx2_write_phy(bp, 0x15, 0x9506);
2037 bnx2_write_phy(bp, 0x17, 0x401f);
2038 bnx2_write_phy(bp, 0x15, 0x14e2);
2039 bnx2_write_phy(bp, 0x18, 0x0400);
2040 }
2041
583c28e5 2042 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2043 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2044 MII_BNX2_DSP_EXPAND_REG | 0x8);
2045 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2046 val &= ~(1 << 8);
2047 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2048 }
2049
b6016b76 2050 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2051 /* Set extended packet length bit */
2052 bnx2_write_phy(bp, 0x18, 0x7);
2053 bnx2_read_phy(bp, 0x18, &val);
2054 bnx2_write_phy(bp, 0x18, val | 0x4000);
2055
2056 bnx2_read_phy(bp, 0x10, &val);
2057 bnx2_write_phy(bp, 0x10, val | 0x1);
2058 }
2059 else {
b6016b76
MC		 2060 bnx2_write_phy(bp, 0x18, 0x7);
2061 bnx2_read_phy(bp, 0x18, &val);
2062 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2063
2064 bnx2_read_phy(bp, 0x10, &val);
2065 bnx2_write_phy(bp, 0x10, val & ~0x1);
2066 }
2067
5b0c76ad
MC		 2068 /* ethernet@wirespeed */
2069 bnx2_write_phy(bp, 0x18, 0x7007);
2070 bnx2_read_phy(bp, 0x18, &val);
2071 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2072 return 0;
2073}
2074
2075
2076static int
9a120bc5 2077bnx2_init_phy(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 2078{
2079 u32 val;
2080 int rc = 0;
2081
583c28e5
MC		 2082 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2083 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2084
ca58c3af
MC		 2085 bp->mii_bmcr = MII_BMCR;
2086 bp->mii_bmsr = MII_BMSR;
27a005b8 2087 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2088 bp->mii_adv = MII_ADVERTISE;
2089 bp->mii_lpa = MII_LPA;
2090
b6016b76
MC		 2091 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2092
583c28e5 2093 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2094 goto setup_phy;
2095
b6016b76
MC		 2096 bnx2_read_phy(bp, MII_PHYSID1, &val);
2097 bp->phy_id = val << 16;
2098 bnx2_read_phy(bp, MII_PHYSID2, &val);
2099 bp->phy_id |= val & 0xffff;
2100
583c28e5 2101 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2102 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2103 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2104 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2105 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2106 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2107 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2108 }
2109 else {
9a120bc5 2110 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2111 }
2112
0d8a6571
MC		 2113setup_phy:
2114 if (!rc)
2115 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2116
2117 return rc;
2118}
2119
2120static int
2121bnx2_set_mac_loopback(struct bnx2 *bp)
2122{
2123 u32 mac_mode;
2124
2125 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2126 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2127 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2128 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2129 bp->link_up = 1;
2130 return 0;
2131}
2132
bc5a0690
MC		 2133static int bnx2_test_link(struct bnx2 *);
2134
2135static int
2136bnx2_set_phy_loopback(struct bnx2 *bp)
2137{
2138 u32 mac_mode;
2139 int rc, i;
2140
2141 spin_lock_bh(&bp->phy_lock);
ca58c3af 2142 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2143 BMCR_SPEED1000);
2144 spin_unlock_bh(&bp->phy_lock);
2145 if (rc)
2146 return rc;
2147
2148 for (i = 0; i < 10; i++) {
2149 if (bnx2_test_link(bp) == 0)
2150 break;
80be4434 2151 msleep(100);
bc5a0690
MC		 2152 }
2153
2154 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2155 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2156 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2157 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2158
2159 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2160 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2161 bp->link_up = 1;
2162 return 0;
2163}
2164
b6016b76 2165static int
b090ae2b 2166bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 2167{
2168 int i;
2169 u32 val;
2170
b6016b76
MC		 2171 bp->fw_wr_seq++;
2172 msg_data |= bp->fw_wr_seq;
2173
2726d6e1 2174 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76
MC		 2175
2176 /* wait for an acknowledgement. */
b090ae2b
MC		 2177 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2178 msleep(10);
b6016b76 2179
2726d6e1 2180 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2181
2182 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2183 break;
2184 }
b090ae2b
MC		 2185 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2186 return 0;
b6016b76
MC		 2187
2188 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2189 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2190 if (!silent)
2191 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2192 "%x\n", msg_data);
b6016b76
MC		 2193
2194 msg_data &= ~BNX2_DRV_MSG_CODE;
2195 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2196
2726d6e1 2197 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2198
b6016b76
MC		 2199 return -EBUSY;
2200 }
2201
b090ae2b
MC		 2202 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2203 return -EIO;
2204
b6016b76
MC		 2205 return 0;
2206}
2207
59b47d8a
MC		 2208static int
2209bnx2_init_5709_context(struct bnx2 *bp)
2210{
2211 int i, ret = 0;
2212 u32 val;
2213
2214 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2215 val |= (BCM_PAGE_BITS - 8) << 16;
2216 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2217 for (i = 0; i < 10; i++) {
2218 val = REG_RD(bp, BNX2_CTX_COMMAND);
2219 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2220 break;
2221 udelay(2);
2222 }
2223 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2224 return -EBUSY;
2225
59b47d8a
MC		 2226 for (i = 0; i < bp->ctx_pages; i++) {
2227 int j;
2228
352f7687
MC		 2229 if (bp->ctx_blk[i])
2230 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2231 else
2232 return -ENOMEM;
2233
59b47d8a
MC		 2234 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2235 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2236 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2237 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2238 (u64) bp->ctx_blk_mapping[i] >> 32);
2239 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2240 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2241 for (j = 0; j < 10; j++) {
2242
2243 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2244 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2245 break;
2246 udelay(5);
2247 }
2248 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2249 ret = -EBUSY;
2250 break;
2251 }
2252 }
2253 return ret;
2254}
2255
b6016b76
MC		 2256static void
2257bnx2_init_context(struct bnx2 *bp)
2258{
2259 u32 vcid;
2260
2261 vcid = 96;
2262 while (vcid) {
2263 u32 vcid_addr, pcid_addr, offset;
7947b20e 2264 int i;
b6016b76
MC		 2265
2266 vcid--;
2267
2268 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2269 u32 new_vcid;
2270
2271 vcid_addr = GET_PCID_ADDR(vcid);
2272 if (vcid & 0x8) {
2273 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2274 }
2275 else {
2276 new_vcid = vcid;
2277 }
2278 pcid_addr = GET_PCID_ADDR(new_vcid);
2279 }
2280 else {
2281 vcid_addr = GET_CID_ADDR(vcid);
2282 pcid_addr = vcid_addr;
2283 }
2284
7947b20e
MC		 2285 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2286 vcid_addr += (i << PHY_CTX_SHIFT);
2287 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2288
5d5d0015 2289 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2290 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2291
7947b20e
MC		 2292 /* Zero out the context. */
2293 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2294 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2295 }
b6016b76
MC		 2296 }
2297}
2298
2299static int
2300bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2301{
2302 u16 *good_mbuf;
2303 u32 good_mbuf_cnt;
2304 u32 val;
2305
2306 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2307 if (good_mbuf == NULL) {
2308 printk(KERN_ERR PFX "Failed to allocate memory in "
2309 "bnx2_alloc_bad_rbuf\n");
2310 return -ENOMEM;
2311 }
2312
2313 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2314 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2315
2316 good_mbuf_cnt = 0;
2317
2318 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2319 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2320 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2321 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2322 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2323
2726d6e1 2324 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2325
2326 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2327
2328 /* The addresses with Bit 9 set are bad memory blocks. */
2329 if (!(val & (1 << 9))) {
2330 good_mbuf[good_mbuf_cnt] = (u16) val;
2331 good_mbuf_cnt++;
2332 }
2333
2726d6e1 2334 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2335 }
2336
2337 /* Free the good ones back to the mbuf pool thus discarding
2338 * all the bad ones. */
2339 while (good_mbuf_cnt) {
2340 good_mbuf_cnt--;
2341
2342 val = good_mbuf[good_mbuf_cnt];
2343 val = (val << 9) | val | 1;
2344
2726d6e1 2345 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2346 }
2347 kfree(good_mbuf);
2348 return 0;
2349}
2350
2351static void
6aa20a22 2352bnx2_set_mac_addr(struct bnx2 *bp)
b6016b76
MC		 2353{
2354 u32 val;
2355 u8 *mac_addr = bp->dev->dev_addr;
2356
2357 val = (mac_addr[0] << 8) | mac_addr[1];
2358
2359 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2360
6aa20a22 2361 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2362 (mac_addr[4] << 8) | mac_addr[5];
2363
2364 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2365}
2366
47bf4246
MC		 2367static inline int
2368bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2369{
2370 dma_addr_t mapping;
2371 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2372 struct rx_bd *rxbd =
2373 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2374 struct page *page = alloc_page(GFP_ATOMIC);
2375
2376 if (!page)
2377 return -ENOMEM;
2378 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2379 PCI_DMA_FROMDEVICE);
2380 rx_pg->page = page;
2381 pci_unmap_addr_set(rx_pg, mapping, mapping);
2382 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2383 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2384 return 0;
2385}
2386
2387static void
2388bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2389{
2390 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2391 struct page *page = rx_pg->page;
2392
2393 if (!page)
2394 return;
2395
2396 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2397 PCI_DMA_FROMDEVICE);
2398
2399 __free_page(page);
2400 rx_pg->page = NULL;
2401}
2402
b6016b76 2403static inline int
a1f60190 2404bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
b6016b76
MC		 2405{
2406 struct sk_buff *skb;
2407 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2408 dma_addr_t mapping;
13daffa2 2409 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2410 unsigned long align;
2411
932f3772 2412 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2413 if (skb == NULL) {
2414 return -ENOMEM;
2415 }
2416
59b47d8a
MC		 2417 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2418 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2419
b6016b76
MC		 2420 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2421 PCI_DMA_FROMDEVICE);
2422
2423 rx_buf->skb = skb;
2424 pci_unmap_addr_set(rx_buf, mapping, mapping);
2425
2426 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2427 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2428
a1f60190 2429 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2430
2431 return 0;
2432}
2433
da3e4fbe 2434static int
35efa7c1 2435bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2436{
35efa7c1 2437 struct status_block *sblk = bnapi->status_blk;
b6016b76 2438 u32 new_link_state, old_link_state;
da3e4fbe 2439 int is_set = 1;
b6016b76 2440
da3e4fbe
MC		 2441 new_link_state = sblk->status_attn_bits & event;
2442 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2443 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2444 if (new_link_state)
2445 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2446 else
2447 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2448 } else
2449 is_set = 0;
2450
2451 return is_set;
2452}
2453
2454static void
35efa7c1 2455bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2456{
74ecc62d
MC		 2457 spin_lock(&bp->phy_lock);
2458
2459 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2460 bnx2_set_link(bp);
35efa7c1 2461 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2462 bnx2_set_remote_link(bp);
2463
74ecc62d
MC		 2464 spin_unlock(&bp->phy_lock);
2465
b6016b76
MC		 2466}
2467
ead7270b 2468static inline u16
35efa7c1 2469bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2470{
2471 u16 cons;
2472
c76c0475
MC		 2473 if (bnapi->int_num == 0)
2474 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2475 else
2476 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
ead7270b
MC		 2477
2478 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2479 cons++;
2480 return cons;
2481}
2482
57851d84
MC		 2483static int
2484bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2485{
2486 u16 hw_cons, sw_cons, sw_ring_cons;
57851d84 2487 int tx_pkt = 0;
b6016b76 2488
35efa7c1 2489 hw_cons = bnx2_get_hw_tx_cons(bnapi);
a550c99b 2490 sw_cons = bnapi->tx_cons;
b6016b76
MC		 2491
2492 while (sw_cons != hw_cons) {
2493 struct sw_bd *tx_buf;
2494 struct sk_buff *skb;
2495 int i, last;
2496
2497 sw_ring_cons = TX_RING_IDX(sw_cons);
2498
2499 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2500 skb = tx_buf->skb;
1d39ed56 2501
b6016b76 2502 /* partial BD completions possible with TSO packets */
89114afd 2503 if (skb_is_gso(skb)) {
b6016b76
MC		 2504 u16 last_idx, last_ring_idx;
2505
2506 last_idx = sw_cons +
2507 skb_shinfo(skb)->nr_frags + 1;
2508 last_ring_idx = sw_ring_cons +
2509 skb_shinfo(skb)->nr_frags + 1;
2510 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2511 last_idx++;
2512 }
2513 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2514 break;
2515 }
2516 }
1d39ed56 2517
b6016b76
MC		 2518 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2519 skb_headlen(skb), PCI_DMA_TODEVICE);
2520
2521 tx_buf->skb = NULL;
2522 last = skb_shinfo(skb)->nr_frags;
2523
2524 for (i = 0; i < last; i++) {
2525 sw_cons = NEXT_TX_BD(sw_cons);
2526
2527 pci_unmap_page(bp->pdev,
2528 pci_unmap_addr(
2529 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2530 mapping),
2531 skb_shinfo(skb)->frags[i].size,
2532 PCI_DMA_TODEVICE);
2533 }
2534
2535 sw_cons = NEXT_TX_BD(sw_cons);
2536
745720e5 2537 dev_kfree_skb(skb);
57851d84
MC		 2538 tx_pkt++;
2539 if (tx_pkt == budget)
2540 break;
b6016b76 2541
35efa7c1 2542 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2543 }
2544
a550c99b
MC		 2545 bnapi->hw_tx_cons = hw_cons;
2546 bnapi->tx_cons = sw_cons;
2f8af120
MC		 2547 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2548 * before checking for netif_queue_stopped(). Without the
2549 * memory barrier, there is a small possibility that bnx2_start_xmit()
2550 * will miss it and cause the queue to be stopped forever.
2551 */
2552 smp_mb();
b6016b76 2553
2f8af120 2554 if (unlikely(netif_queue_stopped(bp->dev)) &&
a550c99b 2555 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2f8af120 2556 netif_tx_lock(bp->dev);
b6016b76 2557 if ((netif_queue_stopped(bp->dev)) &&
a550c99b 2558 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
b6016b76 2559 netif_wake_queue(bp->dev);
2f8af120 2560 netif_tx_unlock(bp->dev);
b6016b76 2561 }
57851d84 2562 return tx_pkt;
b6016b76
MC		 2563}
2564
1db82f2a 2565static void
a1f60190
MC		 2566bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2567 struct sk_buff *skb, int count)
1db82f2a
MC		 2568{
2569 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2570 struct rx_bd *cons_bd, *prod_bd;
2571 dma_addr_t mapping;
2572 int i;
a1f60190
MC		 2573 u16 hw_prod = bnapi->rx_pg_prod, prod;
2574 u16 cons = bnapi->rx_pg_cons;
1db82f2a
MC		 2575
2576 for (i = 0; i < count; i++) {
2577 prod = RX_PG_RING_IDX(hw_prod);
2578
2579 prod_rx_pg = &bp->rx_pg_ring[prod];
2580 cons_rx_pg = &bp->rx_pg_ring[cons];
2581 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2582 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2583
2584 if (i == 0 && skb) {
2585 struct page *page;
2586 struct skb_shared_info *shinfo;
2587
2588 shinfo = skb_shinfo(skb);
2589 shinfo->nr_frags--;
2590 page = shinfo->frags[shinfo->nr_frags].page;
2591 shinfo->frags[shinfo->nr_frags].page = NULL;
2592 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2593 PCI_DMA_FROMDEVICE);
2594 cons_rx_pg->page = page;
2595 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2596 dev_kfree_skb(skb);
2597 }
2598 if (prod != cons) {
2599 prod_rx_pg->page = cons_rx_pg->page;
2600 cons_rx_pg->page = NULL;
2601 pci_unmap_addr_set(prod_rx_pg, mapping,
2602 pci_unmap_addr(cons_rx_pg, mapping));
2603
2604 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2605 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2606
2607 }
2608 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2609 hw_prod = NEXT_RX_BD(hw_prod);
2610 }
a1f60190
MC		 2611 bnapi->rx_pg_prod = hw_prod;
2612 bnapi->rx_pg_cons = cons;
1db82f2a
MC		 2613}
2614
b6016b76 2615static inline void
a1f60190 2616bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
b6016b76
MC		 2617 u16 cons, u16 prod)
2618{
236b6394
MC		 2619 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2620 struct rx_bd *cons_bd, *prod_bd;
2621
2622 cons_rx_buf = &bp->rx_buf_ring[cons];
2623 prod_rx_buf = &bp->rx_buf_ring[prod];
b6016b76
MC		 2624
2625 pci_dma_sync_single_for_device(bp->pdev,
2626 pci_unmap_addr(cons_rx_buf, mapping),
601d3d18 2627 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2628
a1f60190 2629 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2630
236b6394 2631 prod_rx_buf->skb = skb;
b6016b76 2632
236b6394
MC		 2633 if (cons == prod)
2634 return;
b6016b76 2635
236b6394
MC		 2636 pci_unmap_addr_set(prod_rx_buf, mapping,
2637 pci_unmap_addr(cons_rx_buf, mapping));
2638
3fdfcc2c
MC		 2639 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2640 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2641 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2642 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2643}
2644
85833c62 2645static int
a1f60190
MC		 2646bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2647 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2648 u32 ring_idx)
85833c62
MC		 2649{
2650 int err;
2651 u16 prod = ring_idx & 0xffff;
2652
a1f60190 2653 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
85833c62 2654 if (unlikely(err)) {
a1f60190 2655 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2656 if (hdr_len) {
2657 unsigned int raw_len = len + 4;
2658 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2659
a1f60190 2660 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
1db82f2a 2661 }
85833c62
MC		 2662 return err;
2663 }
2664
d89cb6af 2665 skb_reserve(skb, BNX2_RX_OFFSET);
85833c62
MC		 2666 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2667 PCI_DMA_FROMDEVICE);
2668
1db82f2a
MC		 2669 if (hdr_len == 0) {
2670 skb_put(skb, len);
2671 return 0;
2672 } else {
2673 unsigned int i, frag_len, frag_size, pages;
2674 struct sw_pg *rx_pg;
a1f60190
MC		 2675 u16 pg_cons = bnapi->rx_pg_cons;
2676 u16 pg_prod = bnapi->rx_pg_prod;
1db82f2a
MC		 2677
2678 frag_size = len + 4 - hdr_len;
2679 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2680 skb_put(skb, hdr_len);
2681
2682 for (i = 0; i < pages; i++) {
2683 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2684 if (unlikely(frag_len <= 4)) {
2685 unsigned int tail = 4 - frag_len;
2686
a1f60190
MC		 2687 bnapi->rx_pg_cons = pg_cons;
2688 bnapi->rx_pg_prod = pg_prod;
2689 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2690 pages - i);
1db82f2a
MC		 2691 skb->len -= tail;
2692 if (i == 0) {
2693 skb->tail -= tail;
2694 } else {
2695 skb_frag_t *frag =
2696 &skb_shinfo(skb)->frags[i - 1];
2697 frag->size -= tail;
2698 skb->data_len -= tail;
2699 skb->truesize -= tail;
2700 }
2701 return 0;
2702 }
2703 rx_pg = &bp->rx_pg_ring[pg_cons];
2704
2705 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2706 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2707
2708 if (i == pages - 1)
2709 frag_len -= 4;
2710
2711 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2712 rx_pg->page = NULL;
2713
2714 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2715 if (unlikely(err)) {
a1f60190
MC		 2716 bnapi->rx_pg_cons = pg_cons;
2717 bnapi->rx_pg_prod = pg_prod;
2718 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2719 pages - i);
1db82f2a
MC		 2720 return err;
2721 }
2722
2723 frag_size -= frag_len;
2724 skb->data_len += frag_len;
2725 skb->truesize += frag_len;
2726 skb->len += frag_len;
2727
2728 pg_prod = NEXT_RX_BD(pg_prod);
2729 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2730 }
a1f60190
MC		 2731 bnapi->rx_pg_prod = pg_prod;
2732 bnapi->rx_pg_cons = pg_cons;
1db82f2a 2733 }
85833c62
MC		 2734 return 0;
2735}
2736
c09c2627 2737static inline u16
35efa7c1 2738bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 2739{
35efa7c1 2740 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
c09c2627
MC		 2741
2742 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2743 cons++;
2744 return cons;
2745}
2746
b6016b76 2747static int
35efa7c1 2748bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2749{
2750 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2751 struct l2_fhdr *rx_hdr;
1db82f2a 2752 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 2753
35efa7c1 2754 hw_cons = bnx2_get_hw_rx_cons(bnapi);
a1f60190
MC		 2755 sw_cons = bnapi->rx_cons;
2756 sw_prod = bnapi->rx_prod;
b6016b76
MC		 2757
2758 /* Memory barrier necessary as speculative reads of the rx
2759 * buffer can be ahead of the index in the status block
2760 */
2761 rmb();
2762 while (sw_cons != hw_cons) {
1db82f2a 2763 unsigned int len, hdr_len;
ade2bfe7 2764 u32 status;
b6016b76
MC		 2765 struct sw_bd *rx_buf;
2766 struct sk_buff *skb;
236b6394 2767 dma_addr_t dma_addr;
b6016b76
MC		 2768
2769 sw_ring_cons = RX_RING_IDX(sw_cons);
2770 sw_ring_prod = RX_RING_IDX(sw_prod);
2771
2772 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2773 skb = rx_buf->skb;
236b6394
MC		 2774
2775 rx_buf->skb = NULL;
2776
2777 dma_addr = pci_unmap_addr(rx_buf, mapping);
2778
2779 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
601d3d18
BL		 2780 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2781 PCI_DMA_FROMDEVICE);
b6016b76
MC		 2782
2783 rx_hdr = (struct l2_fhdr *) skb->data;
1db82f2a 2784 len = rx_hdr->l2_fhdr_pkt_len;
b6016b76 2785
ade2bfe7 2786 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 2787 (L2_FHDR_ERRORS_BAD_CRC |
2788 L2_FHDR_ERRORS_PHY_DECODE |
2789 L2_FHDR_ERRORS_ALIGNMENT |
2790 L2_FHDR_ERRORS_TOO_SHORT |
2791 L2_FHDR_ERRORS_GIANT_FRAME)) {
2792
a1f60190
MC		 2793 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2794 sw_ring_prod);
85833c62 2795 goto next_rx;
b6016b76 2796 }
1db82f2a
MC		 2797 hdr_len = 0;
2798 if (status & L2_FHDR_STATUS_SPLIT) {
2799 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2800 pg_ring_used = 1;
2801 } else if (len > bp->rx_jumbo_thresh) {
2802 hdr_len = bp->rx_jumbo_thresh;
2803 pg_ring_used = 1;
2804 }
2805
2806 len -= 4;
b6016b76 2807
5d5d0015 2808 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 2809 struct sk_buff *new_skb;
2810
932f3772 2811 new_skb = netdev_alloc_skb(bp->dev, len + 2);
85833c62 2812 if (new_skb == NULL) {
a1f60190 2813 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
85833c62
MC		 2814 sw_ring_prod);
2815 goto next_rx;
2816 }
b6016b76
MC		 2817
2818 /* aligned copy */
d89cb6af
BL		 2819 skb_copy_from_linear_data_offset(skb,
2820 BNX2_RX_OFFSET - 2,
d626f62b 2821 new_skb->data, len + 2);
b6016b76
MC		 2822 skb_reserve(new_skb, 2);
2823 skb_put(new_skb, len);
b6016b76 2824
a1f60190 2825 bnx2_reuse_rx_skb(bp, bnapi, skb,
b6016b76
MC		 2826 sw_ring_cons, sw_ring_prod);
2827
2828 skb = new_skb;
a1f60190
MC		 2829 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2830 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 2831 goto next_rx;
b6016b76
MC		 2832
2833 skb->protocol = eth_type_trans(skb, bp->dev);
2834
2835 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 2836 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 2837
745720e5 2838 dev_kfree_skb(skb);
b6016b76
MC		 2839 goto next_rx;
2840
2841 }
2842
b6016b76
MC		 2843 skb->ip_summed = CHECKSUM_NONE;
2844 if (bp->rx_csum &&
2845 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2846 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2847
ade2bfe7
MC		 2848 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2849 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 2850 skb->ip_summed = CHECKSUM_UNNECESSARY;
2851 }
2852
2853#ifdef BCM_VLAN
79ea13ce 2854 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
b6016b76
MC		 2855 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2856 rx_hdr->l2_fhdr_vlan_tag);
2857 }
2858 else
2859#endif
2860 netif_receive_skb(skb);
2861
2862 bp->dev->last_rx = jiffies;
2863 rx_pkt++;
2864
2865next_rx:
b6016b76
MC		 2866 sw_cons = NEXT_RX_BD(sw_cons);
2867 sw_prod = NEXT_RX_BD(sw_prod);
2868
2869 if ((rx_pkt == budget))
2870 break;
f4e418f7
MC		 2871
2872 /* Refresh hw_cons to see if there is new work */
2873 if (sw_cons == hw_cons) {
35efa7c1 2874 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 2875 rmb();
2876 }
b6016b76 2877 }
a1f60190
MC		 2878 bnapi->rx_cons = sw_cons;
2879 bnapi->rx_prod = sw_prod;
b6016b76 2880
1db82f2a
MC		 2881 if (pg_ring_used)
2882 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
a1f60190 2883 bnapi->rx_pg_prod);
1db82f2a 2884
b6016b76
MC		 2885 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2886
a1f60190 2887 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 2888
2889 mmiowb();
2890
2891 return rx_pkt;
2892
2893}
2894
2895/* MSI ISR - The only difference between this and the INTx ISR
2896 * is that the MSI interrupt is always serviced.
2897 */
2898static irqreturn_t
7d12e780 2899bnx2_msi(int irq, void *dev_instance)
b6016b76
MC		 2900{
2901 struct net_device *dev = dev_instance;
972ec0d4 2902 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2903 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
b6016b76 2904
35efa7c1 2905 prefetch(bnapi->status_blk);
b6016b76
MC		 2906 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2907 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2908 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2909
2910 /* Return here if interrupt is disabled. */
73eef4cd
MC		 2911 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2912 return IRQ_HANDLED;
b6016b76 2913
35efa7c1 2914 netif_rx_schedule(dev, &bnapi->napi);
b6016b76 2915
73eef4cd 2916 return IRQ_HANDLED;
b6016b76
MC		 2917}
2918
8e6a72c4
MC		 2919static irqreturn_t
2920bnx2_msi_1shot(int irq, void *dev_instance)
2921{
2922 struct net_device *dev = dev_instance;
2923 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2924 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
8e6a72c4 2925
35efa7c1 2926 prefetch(bnapi->status_blk);
8e6a72c4
MC		 2927
2928 /* Return here if interrupt is disabled. */
2929 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2930 return IRQ_HANDLED;
2931
35efa7c1 2932 netif_rx_schedule(dev, &bnapi->napi);
8e6a72c4
MC		 2933
2934 return IRQ_HANDLED;
2935}
2936
b6016b76 2937static irqreturn_t
7d12e780 2938bnx2_interrupt(int irq, void *dev_instance)
b6016b76
MC		 2939{
2940 struct net_device *dev = dev_instance;
972ec0d4 2941 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2942 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
35efa7c1 2943 struct status_block *sblk = bnapi->status_blk;
b6016b76
MC		 2944
2945 /* When using INTx, it is possible for the interrupt to arrive
2946 * at the CPU before the status block posted prior to the
2947 * interrupt. Reading a register will flush the status block.
2948 * When using MSI, the MSI message will always complete after
2949 * the status block write.
2950 */
35efa7c1 2951 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 2952 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2953 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 2954 return IRQ_NONE;
b6016b76
MC		 2955
2956 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2957 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2958 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2959
b8a7ce7b
MC		 2960 /* Read back to deassert IRQ immediately to avoid too many
2961 * spurious interrupts.
2962 */
2963 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2964
b6016b76 2965 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 2966 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2967 return IRQ_HANDLED;
b6016b76 2968
35efa7c1
MC		 2969 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2970 bnapi->last_status_idx = sblk->status_idx;
2971 __netif_rx_schedule(dev, &bnapi->napi);
b8a7ce7b 2972 }
b6016b76 2973
73eef4cd 2974 return IRQ_HANDLED;
b6016b76
MC		 2975}
2976
57851d84
MC		 2977static irqreturn_t
2978bnx2_tx_msix(int irq, void *dev_instance)
2979{
2980 struct net_device *dev = dev_instance;
2981 struct bnx2 *bp = netdev_priv(dev);
2982 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2983
2984 prefetch(bnapi->status_blk_msix);
2985
2986 /* Return here if interrupt is disabled. */
2987 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2988 return IRQ_HANDLED;
2989
2990 netif_rx_schedule(dev, &bnapi->napi);
2991 return IRQ_HANDLED;
2992}
2993
0d8a6571
MC		 2994#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2995 STATUS_ATTN_BITS_TIMER_ABORT)
da3e4fbe 2996
f4e418f7 2997static inline int
35efa7c1 2998bnx2_has_work(struct bnx2_napi *bnapi)
f4e418f7 2999{
1097f5e9 3000 struct status_block *sblk = bnapi->status_blk;
f4e418f7 3001
a1f60190 3002 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
a550c99b 3003 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
f4e418f7
MC		 3004 return 1;
3005
da3e4fbe
MC		 3006 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3007 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3008 return 1;
3009
3010 return 0;
3011}
3012
57851d84
MC		 3013static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3014{
3015 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3016 struct bnx2 *bp = bnapi->bp;
3017 int work_done = 0;
3018 struct status_block_msix *sblk = bnapi->status_blk_msix;
3019
3020 do {
3021 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3022 if (unlikely(work_done >= budget))
3023 return work_done;
3024
3025 bnapi->last_status_idx = sblk->status_idx;
3026 rmb();
3027 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3028
3029 netif_rx_complete(bp->dev, napi);
3030 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3031 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3032 bnapi->last_status_idx);
3033 return work_done;
3034}
3035
35efa7c1
MC		 3036static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3037 int work_done, int budget)
b6016b76 3038{
35efa7c1 3039 struct status_block *sblk = bnapi->status_blk;
da3e4fbe
MC		 3040 u32 status_attn_bits = sblk->status_attn_bits;
3041 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3042
da3e4fbe
MC		 3043 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3044 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3045
35efa7c1 3046 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3047
3048 /* This is needed to take care of transient status
3049 * during link changes.
3050 */
3051 REG_WR(bp, BNX2_HC_COMMAND,
3052 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3053 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 3054 }
3055
a550c99b 3056 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
57851d84 3057 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3058
a1f60190 3059 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
35efa7c1 3060 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3061
6f535763
DM		 3062 return work_done;
3063}
3064
3065static int bnx2_poll(struct napi_struct *napi, int budget)
3066{
35efa7c1
MC		 3067 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3068 struct bnx2 *bp = bnapi->bp;
6f535763 3069 int work_done = 0;
35efa7c1 3070 struct status_block *sblk = bnapi->status_blk;
6f535763
DM		 3071
3072 while (1) {
35efa7c1 3073 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3074
6f535763
DM		 3075 if (unlikely(work_done >= budget))
3076 break;
3077
35efa7c1 3078 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3079 * much work has been processed, so we must read it before
3080 * checking for more work.
3081 */
35efa7c1 3082 bnapi->last_status_idx = sblk->status_idx;
6dee6421 3083 rmb();
35efa7c1 3084 if (likely(!bnx2_has_work(bnapi))) {
6f535763 3085 netif_rx_complete(bp->dev, napi);
f86e82fb 3086 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3087 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3088 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3089 bnapi->last_status_idx);
6dee6421 3090 break;
6f535763 3091 }
1269a8a6
MC		 3092 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3093 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3094 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3095 bnapi->last_status_idx);
1269a8a6 3096
6f535763
DM		 3097 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3098 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3099 bnapi->last_status_idx);
6f535763
DM		 3100 break;
3101 }
b6016b76
MC		 3102 }
3103
bea3348e 3104 return work_done;
b6016b76
MC		 3105}
3106
932ff279 3107/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3108 * from set_multicast.
3109 */
3110static void
3111bnx2_set_rx_mode(struct net_device *dev)
3112{
972ec0d4 3113 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 3114 u32 rx_mode, sort_mode;
3115 int i;
b6016b76 3116
c770a65c 3117 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3118
3119 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3120 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3121 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3122#ifdef BCM_VLAN
f86e82fb 3123 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
b6016b76 3124 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3125#else
f86e82fb 3126 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
e29054f9 3127 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3128#endif
3129 if (dev->flags & IFF_PROMISC) {
3130 /* Promiscuous mode. */
3131 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3132 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3133 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3134 }
3135 else if (dev->flags & IFF_ALLMULTI) {
3136 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3137 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3138 0xffffffff);
3139 }
3140 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3141 }
3142 else {
3143 /* Accept one or more multicast(s). */
3144 struct dev_mc_list *mclist;
3145 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3146 u32 regidx;
3147 u32 bit;
3148 u32 crc;
3149
3150 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3151
3152 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3153 i++, mclist = mclist->next) {
3154
3155 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3156 bit = crc & 0xff;
3157 regidx = (bit & 0xe0) >> 5;
3158 bit &= 0x1f;
3159 mc_filter[regidx] |= (1 << bit);
3160 }
3161
3162 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3163 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3164 mc_filter[i]);
3165 }
3166
3167 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3168 }
3169
3170 if (rx_mode != bp->rx_mode) {
3171 bp->rx_mode = rx_mode;
3172 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3173 }
3174
3175 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3176 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3177 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3178
c770a65c 3179 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3180}
3181
3182static void
b491edd5 3183load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
b6016b76
MC		 3184 u32 rv2p_proc)
3185{
3186 int i;
3187 u32 val;
3188
d25be1d3
MC		 3189 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3190 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3191 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3192 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3193 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3194 }
b6016b76
MC		 3195
3196 for (i = 0; i < rv2p_code_len; i += 8) {
b491edd5 3197 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
b6016b76 3198 rv2p_code++;
b491edd5 3199 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
b6016b76
MC		 3200 rv2p_code++;
3201
3202 if (rv2p_proc == RV2P_PROC1) {
3203 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3204 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3205 }
3206 else {
3207 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3208 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3209 }
3210 }
3211
3212 /* Reset the processor, un-stall is done later. */
3213 if (rv2p_proc == RV2P_PROC1) {
3214 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3215 }
3216 else {
3217 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3218 }
3219}
3220
af3ee519 3221static int
b6016b76
MC		 3222load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3223{
3224 u32 offset;
3225 u32 val;
af3ee519 3226 int rc;
b6016b76
MC		 3227
3228 /* Halt the CPU. */
2726d6e1 3229 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3230 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3231 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3232 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3233
3234 /* Load the Text area. */
3235 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
af3ee519 3236 if (fw->gz_text) {
b6016b76
MC		 3237 int j;
3238
ea1f8d5c
MC		 3239 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3240 fw->gz_text_len);
3241 if (rc < 0)
b3448b0b 3242 return rc;
ea1f8d5c 3243
b6016b76 3244 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2726d6e1 3245 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
b6016b76
MC		 3246 }
3247 }
3248
3249 /* Load the Data area. */
3250 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3251 if (fw->data) {
3252 int j;
3253
3254 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2726d6e1 3255 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
b6016b76
MC		 3256 }
3257 }
3258
3259 /* Load the SBSS area. */
3260 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3261 if (fw->sbss_len) {
b6016b76
MC		 3262 int j;
3263
3264 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2726d6e1 3265 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3266 }
3267 }
3268
3269 /* Load the BSS area. */
3270 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3271 if (fw->bss_len) {
b6016b76
MC		 3272 int j;
3273
3274 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2726d6e1 3275 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3276 }
3277 }
3278
3279 /* Load the Read-Only area. */
3280 offset = cpu_reg->spad_base +
3281 (fw->rodata_addr - cpu_reg->mips_view_base);
3282 if (fw->rodata) {
3283 int j;
3284
3285 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2726d6e1 3286 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
b6016b76
MC		 3287 }
3288 }
3289
3290 /* Clear the pre-fetch instruction. */
2726d6e1
MC		 3291 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3292 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
b6016b76
MC		 3293
3294 /* Start the CPU. */
2726d6e1 3295 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3296 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3297 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3298 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3299
3300 return 0;
b6016b76
MC		 3301}
3302
fba9fe91 3303static int
b6016b76
MC		 3304bnx2_init_cpus(struct bnx2 *bp)
3305{
3306 struct cpu_reg cpu_reg;
af3ee519 3307 struct fw_info *fw;
110d0ef9
MC		 3308 int rc, rv2p_len;
3309 void *text, *rv2p;
b6016b76
MC		 3310
3311 /* Initialize the RV2P processor. */
b3448b0b
DV		 3312 text = vmalloc(FW_BUF_SIZE);
3313 if (!text)
3314 return -ENOMEM;
110d0ef9
MC		 3315 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3316 rv2p = bnx2_xi_rv2p_proc1;
3317 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3318 } else {
3319 rv2p = bnx2_rv2p_proc1;
3320 rv2p_len = sizeof(bnx2_rv2p_proc1);
3321 }
3322 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3323 if (rc < 0)
fba9fe91 3324 goto init_cpu_err;
ea1f8d5c 3325
b3448b0b 3326 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
fba9fe91 3327
110d0ef9
MC		 3328 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3329 rv2p = bnx2_xi_rv2p_proc2;
3330 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3331 } else {
3332 rv2p = bnx2_rv2p_proc2;
3333 rv2p_len = sizeof(bnx2_rv2p_proc2);
3334 }
3335 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3336 if (rc < 0)
fba9fe91 3337 goto init_cpu_err;
ea1f8d5c 3338
b3448b0b 3339 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
b6016b76
MC		 3340
3341 /* Initialize the RX Processor. */
3342 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3343 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3344 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3345 cpu_reg.state = BNX2_RXP_CPU_STATE;
3346 cpu_reg.state_value_clear = 0xffffff;
3347 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3348 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3349 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3350 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3351 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3352 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3353 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3354
d43584c8
MC		 3355 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3356 fw = &bnx2_rxp_fw_09;
3357 else
3358 fw = &bnx2_rxp_fw_06;
fba9fe91 3359
ea1f8d5c 3360 fw->text = text;
af3ee519 3361 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3362 if (rc)
3363 goto init_cpu_err;
3364
b6016b76
MC		 3365 /* Initialize the TX Processor. */
3366 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3367 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3368 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3369 cpu_reg.state = BNX2_TXP_CPU_STATE;
3370 cpu_reg.state_value_clear = 0xffffff;
3371 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3372 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3373 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3374 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3375 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3376 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3377 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3378
d43584c8
MC		 3379 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3380 fw = &bnx2_txp_fw_09;
3381 else
3382 fw = &bnx2_txp_fw_06;
fba9fe91 3383
ea1f8d5c 3384 fw->text = text;
af3ee519 3385 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3386 if (rc)
3387 goto init_cpu_err;
3388
b6016b76
MC		 3389 /* Initialize the TX Patch-up Processor. */
3390 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3391 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3392 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3393 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3394 cpu_reg.state_value_clear = 0xffffff;
3395 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3396 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3397 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3398 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3399 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3400 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3401 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3402
d43584c8
MC		 3403 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3404 fw = &bnx2_tpat_fw_09;
3405 else
3406 fw = &bnx2_tpat_fw_06;
fba9fe91 3407
ea1f8d5c 3408 fw->text = text;
af3ee519 3409 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3410 if (rc)
3411 goto init_cpu_err;
3412
b6016b76
MC		 3413 /* Initialize the Completion Processor. */
3414 cpu_reg.mode = BNX2_COM_CPU_MODE;
3415 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3416 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3417 cpu_reg.state = BNX2_COM_CPU_STATE;
3418 cpu_reg.state_value_clear = 0xffffff;
3419 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3420 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3421 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3422 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3423 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3424 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3425 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3426
d43584c8
MC		 3427 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3428 fw = &bnx2_com_fw_09;
3429 else
3430 fw = &bnx2_com_fw_06;
fba9fe91 3431
ea1f8d5c 3432 fw->text = text;
af3ee519 3433 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3434 if (rc)
3435 goto init_cpu_err;
3436
d43584c8
MC		 3437 /* Initialize the Command Processor. */
3438 cpu_reg.mode = BNX2_CP_CPU_MODE;
3439 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3440 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3441 cpu_reg.state = BNX2_CP_CPU_STATE;
3442 cpu_reg.state_value_clear = 0xffffff;
3443 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3444 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3445 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3446 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3447 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3448 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3449 cpu_reg.mips_view_base = 0x8000000;
b6016b76 3450
110d0ef9 3451 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d43584c8 3452 fw = &bnx2_cp_fw_09;
110d0ef9
MC		 3453 else
3454 fw = &bnx2_cp_fw_06;
3455
3456 fw->text = text;
3457 rc = load_cpu_fw(bp, &cpu_reg, fw);
b6016b76 3458
fba9fe91 3459init_cpu_err:
ea1f8d5c 3460 vfree(text);
fba9fe91 3461 return rc;
b6016b76
MC		 3462}
3463
3464static int
829ca9a3 3465bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3466{
3467 u16 pmcsr;
3468
3469 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3470
3471 switch (state) {
829ca9a3 3472 case PCI_D0: {
b6016b76
MC		 3473 u32 val;
3474
3475 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3476 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3477 PCI_PM_CTRL_PME_STATUS);
3478
3479 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3480 /* delay required during transition out of D3hot */
3481 msleep(20);
3482
3483 val = REG_RD(bp, BNX2_EMAC_MODE);
3484 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3485 val &= ~BNX2_EMAC_MODE_MPKT;
3486 REG_WR(bp, BNX2_EMAC_MODE, val);
3487
3488 val = REG_RD(bp, BNX2_RPM_CONFIG);
3489 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3490 REG_WR(bp, BNX2_RPM_CONFIG, val);
3491 break;
3492 }
829ca9a3 3493 case PCI_D3hot: {
b6016b76
MC		 3494 int i;
3495 u32 val, wol_msg;
3496
3497 if (bp->wol) {
3498 u32 advertising;
3499 u8 autoneg;
3500
3501 autoneg = bp->autoneg;
3502 advertising = bp->advertising;
3503
239cd343
MC		 3504 if (bp->phy_port == PORT_TP) {
3505 bp->autoneg = AUTONEG_SPEED;
3506 bp->advertising = ADVERTISED_10baseT_Half |
3507 ADVERTISED_10baseT_Full |
3508 ADVERTISED_100baseT_Half |
3509 ADVERTISED_100baseT_Full |
3510 ADVERTISED_Autoneg;
3511 }
b6016b76 3512
239cd343
MC		 3513 spin_lock_bh(&bp->phy_lock);
3514 bnx2_setup_phy(bp, bp->phy_port);
3515 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3516
3517 bp->autoneg = autoneg;
3518 bp->advertising = advertising;
3519
3520 bnx2_set_mac_addr(bp);
3521
3522 val = REG_RD(bp, BNX2_EMAC_MODE);
3523
3524 /* Enable port mode. */
3525 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3526 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3527 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3528 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3529 if (bp->phy_port == PORT_TP)
3530 val |= BNX2_EMAC_MODE_PORT_MII;
3531 else {
3532 val |= BNX2_EMAC_MODE_PORT_GMII;
3533 if (bp->line_speed == SPEED_2500)
3534 val |= BNX2_EMAC_MODE_25G_MODE;
3535 }
b6016b76
MC		 3536
3537 REG_WR(bp, BNX2_EMAC_MODE, val);
3538
3539 /* receive all multicast */
3540 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3541 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3542 0xffffffff);
3543 }
3544 REG_WR(bp, BNX2_EMAC_RX_MODE,
3545 BNX2_EMAC_RX_MODE_SORT_MODE);
3546
3547 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3548 BNX2_RPM_SORT_USER0_MC_EN;
3549 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3550 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3551 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3552 BNX2_RPM_SORT_USER0_ENA);
3553
3554 /* Need to enable EMAC and RPM for WOL. */
3555 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3556 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3557 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3558 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3559
3560 val = REG_RD(bp, BNX2_RPM_CONFIG);
3561 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3562 REG_WR(bp, BNX2_RPM_CONFIG, val);
3563
3564 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3565 }
3566 else {
3567 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3568 }
3569
f86e82fb 3570 if (!(bp->flags & BNX2_FLAG_NO_WOL))
dda1e390 3571 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 3572
3573 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3574 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3575 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3576
3577 if (bp->wol)
3578 pmcsr |= 3;
3579 }
3580 else {
3581 pmcsr |= 3;
3582 }
3583 if (bp->wol) {
3584 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3585 }
3586 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3587 pmcsr);
3588
3589 /* No more memory access after this point until
3590 * device is brought back to D0.
3591 */
3592 udelay(50);
3593 break;
3594 }
3595 default:
3596 return -EINVAL;
3597 }
3598 return 0;
3599}
3600
3601static int
3602bnx2_acquire_nvram_lock(struct bnx2 *bp)
3603{
3604 u32 val;
3605 int j;
3606
3607 /* Request access to the flash interface. */
3608 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3609 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3610 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3611 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3612 break;
3613
3614 udelay(5);
3615 }
3616
3617 if (j >= NVRAM_TIMEOUT_COUNT)
3618 return -EBUSY;
3619
3620 return 0;
3621}
3622
3623static int
3624bnx2_release_nvram_lock(struct bnx2 *bp)
3625{
3626 int j;
3627 u32 val;
3628
3629 /* Relinquish nvram interface. */
3630 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3631
3632 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3633 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3634 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3635 break;
3636
3637 udelay(5);
3638 }
3639
3640 if (j >= NVRAM_TIMEOUT_COUNT)
3641 return -EBUSY;
3642
3643 return 0;
3644}
3645
3646
3647static int
3648bnx2_enable_nvram_write(struct bnx2 *bp)
3649{
3650 u32 val;
3651
3652 val = REG_RD(bp, BNX2_MISC_CFG);
3653 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3654
e30372c9 3655 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 3656 int j;
3657
3658 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3659 REG_WR(bp, BNX2_NVM_COMMAND,
3660 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3661
3662 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3663 udelay(5);
3664
3665 val = REG_RD(bp, BNX2_NVM_COMMAND);
3666 if (val & BNX2_NVM_COMMAND_DONE)
3667 break;
3668 }
3669
3670 if (j >= NVRAM_TIMEOUT_COUNT)
3671 return -EBUSY;
3672 }
3673 return 0;
3674}
3675
3676static void
3677bnx2_disable_nvram_write(struct bnx2 *bp)
3678{
3679 u32 val;
3680
3681 val = REG_RD(bp, BNX2_MISC_CFG);
3682 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3683}
3684
3685
3686static void
3687bnx2_enable_nvram_access(struct bnx2 *bp)
3688{
3689 u32 val;
3690
3691 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3692 /* Enable both bits, even on read. */
6aa20a22 3693 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3694 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3695}
3696
3697static void
3698bnx2_disable_nvram_access(struct bnx2 *bp)
3699{
3700 u32 val;
3701
3702 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3703 /* Disable both bits, even after read. */
6aa20a22 3704 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3705 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3706 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3707}
3708
3709static int
3710bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3711{
3712 u32 cmd;
3713 int j;
3714
e30372c9 3715 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 3716 /* Buffered flash, no erase needed */
3717 return 0;
3718
3719 /* Build an erase command */
3720 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3721 BNX2_NVM_COMMAND_DOIT;
3722
3723 /* Need to clear DONE bit separately. */
3724 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3725
3726 /* Address of the NVRAM to read from. */
3727 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3728
3729 /* Issue an erase command. */
3730 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3731
3732 /* Wait for completion. */
3733 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3734 u32 val;
3735
3736 udelay(5);
3737
3738 val = REG_RD(bp, BNX2_NVM_COMMAND);
3739 if (val & BNX2_NVM_COMMAND_DONE)
3740 break;
3741 }
3742
3743 if (j >= NVRAM_TIMEOUT_COUNT)
3744 return -EBUSY;
3745
3746 return 0;
3747}
3748
3749static int
3750bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3751{
3752 u32 cmd;
3753 int j;
3754
3755 /* Build the command word. */
3756 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3757
e30372c9
MC		 3758 /* Calculate an offset of a buffered flash, not needed for 5709. */
3759 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3760 offset = ((offset / bp->flash_info->page_size) <<
3761 bp->flash_info->page_bits) +
3762 (offset % bp->flash_info->page_size);
3763 }
3764
3765 /* Need to clear DONE bit separately. */
3766 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3767
3768 /* Address of the NVRAM to read from. */
3769 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3770
3771 /* Issue a read command. */
3772 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3773
3774 /* Wait for completion. */
3775 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3776 u32 val;
3777
3778 udelay(5);
3779
3780 val = REG_RD(bp, BNX2_NVM_COMMAND);
3781 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 3782 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3783 memcpy(ret_val, &v, 4);
b6016b76
MC		 3784 break;
3785 }
3786 }
3787 if (j >= NVRAM_TIMEOUT_COUNT)
3788 return -EBUSY;
3789
3790 return 0;
3791}
3792
3793
3794static int
3795bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3796{
b491edd5
AV		 3797 u32 cmd;
3798 __be32 val32;
b6016b76
MC		 3799 int j;
3800
3801 /* Build the command word. */
3802 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3803
e30372c9
MC		 3804 /* Calculate an offset of a buffered flash, not needed for 5709. */
3805 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3806 offset = ((offset / bp->flash_info->page_size) <<
3807 bp->flash_info->page_bits) +
3808 (offset % bp->flash_info->page_size);
3809 }
3810
3811 /* Need to clear DONE bit separately. */
3812 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3813
3814 memcpy(&val32, val, 4);
b6016b76
MC		 3815
3816 /* Write the data. */
b491edd5 3817 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 3818
3819 /* Address of the NVRAM to write to. */
3820 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3821
3822 /* Issue the write command. */
3823 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3824
3825 /* Wait for completion. */
3826 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3827 udelay(5);
3828
3829 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3830 break;
3831 }
3832 if (j >= NVRAM_TIMEOUT_COUNT)
3833 return -EBUSY;
3834
3835 return 0;
3836}
3837
3838static int
3839bnx2_init_nvram(struct bnx2 *bp)
3840{
3841 u32 val;
e30372c9 3842 int j, entry_count, rc = 0;
b6016b76
MC		 3843 struct flash_spec *flash;
3844
e30372c9
MC		 3845 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3846 bp->flash_info = &flash_5709;
3847 goto get_flash_size;
3848 }
3849
b6016b76
MC		 3850 /* Determine the selected interface. */
3851 val = REG_RD(bp, BNX2_NVM_CFG1);
3852
ff8ac609 3853 entry_count = ARRAY_SIZE(flash_table);
b6016b76 3854
b6016b76
MC		 3855 if (val & 0x40000000) {
3856
3857 /* Flash interface has been reconfigured */
3858 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 3859 j++, flash++) {
3860 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3861 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 3862 bp->flash_info = flash;
3863 break;
3864 }
3865 }
3866 }
3867 else {
37137709 3868 u32 mask;
b6016b76
MC		 3869 /* Not yet been reconfigured */
3870
37137709
MC		 3871 if (val & (1 << 23))
3872 mask = FLASH_BACKUP_STRAP_MASK;
3873 else
3874 mask = FLASH_STRAP_MASK;
3875
b6016b76
MC		 3876 for (j = 0, flash = &flash_table[0]; j < entry_count;
3877 j++, flash++) {
3878
37137709 3879 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 3880 bp->flash_info = flash;
3881
3882 /* Request access to the flash interface. */
3883 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3884 return rc;
3885
3886 /* Enable access to flash interface */
3887 bnx2_enable_nvram_access(bp);
3888
3889 /* Reconfigure the flash interface */
3890 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3891 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3892 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3893 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3894
3895 /* Disable access to flash interface */
3896 bnx2_disable_nvram_access(bp);
3897 bnx2_release_nvram_lock(bp);
3898
3899 break;
3900 }
3901 }
3902 } /* if (val & 0x40000000) */
3903
3904 if (j == entry_count) {
3905 bp->flash_info = NULL;
2f23c523 3906 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 3907 return -ENODEV;
b6016b76
MC		 3908 }
3909
e30372c9 3910get_flash_size:
2726d6e1 3911 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 3912 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3913 if (val)
3914 bp->flash_size = val;
3915 else
3916 bp->flash_size = bp->flash_info->total_size;
3917
b6016b76
MC		 3918 return rc;
3919}
3920
3921static int
3922bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3923 int buf_size)
3924{
3925 int rc = 0;
3926 u32 cmd_flags, offset32, len32, extra;
3927
3928 if (buf_size == 0)
3929 return 0;
3930
3931 /* Request access to the flash interface. */
3932 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3933 return rc;
3934
3935 /* Enable access to flash interface */
3936 bnx2_enable_nvram_access(bp);
3937
3938 len32 = buf_size;
3939 offset32 = offset;
3940 extra = 0;
3941
3942 cmd_flags = 0;
3943
3944 if (offset32 & 3) {
3945 u8 buf[4];
3946 u32 pre_len;
3947
3948 offset32 &= ~3;
3949 pre_len = 4 - (offset & 3);
3950
3951 if (pre_len >= len32) {
3952 pre_len = len32;
3953 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3954 BNX2_NVM_COMMAND_LAST;
3955 }
3956 else {
3957 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3958 }
3959
3960 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3961
3962 if (rc)
3963 return rc;
3964
3965 memcpy(ret_buf, buf + (offset & 3), pre_len);
3966
3967 offset32 += 4;
3968 ret_buf += pre_len;
3969 len32 -= pre_len;
3970 }
3971 if (len32 & 3) {
3972 extra = 4 - (len32 & 3);
3973 len32 = (len32 + 4) & ~3;
3974 }
3975
3976 if (len32 == 4) {
3977 u8 buf[4];
3978
3979 if (cmd_flags)
3980 cmd_flags = BNX2_NVM_COMMAND_LAST;
3981 else
3982 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3983 BNX2_NVM_COMMAND_LAST;
3984
3985 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3986
3987 memcpy(ret_buf, buf, 4 - extra);
3988 }
3989 else if (len32 > 0) {
3990 u8 buf[4];
3991
3992 /* Read the first word. */
3993 if (cmd_flags)
3994 cmd_flags = 0;
3995 else
3996 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3997
3998 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3999
4000 /* Advance to the next dword. */
4001 offset32 += 4;
4002 ret_buf += 4;
4003 len32 -= 4;
4004
4005 while (len32 > 4 && rc == 0) {
4006 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4007
4008 /* Advance to the next dword. */
4009 offset32 += 4;
4010 ret_buf += 4;
4011 len32 -= 4;
4012 }
4013
4014 if (rc)
4015 return rc;
4016
4017 cmd_flags = BNX2_NVM_COMMAND_LAST;
4018 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4019
4020 memcpy(ret_buf, buf, 4 - extra);
4021 }
4022
4023 /* Disable access to flash interface */
4024 bnx2_disable_nvram_access(bp);
4025
4026 bnx2_release_nvram_lock(bp);
4027
4028 return rc;
4029}
4030
4031static int
4032bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4033 int buf_size)
4034{
4035 u32 written, offset32, len32;
e6be763f 4036 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4037 int rc = 0;
4038 int align_start, align_end;
4039
4040 buf = data_buf;
4041 offset32 = offset;
4042 len32 = buf_size;
4043 align_start = align_end = 0;
4044
4045 if ((align_start = (offset32 & 3))) {
4046 offset32 &= ~3;
c873879c
MC		 4047 len32 += align_start;
4048 if (len32 < 4)
4049 len32 = 4;
b6016b76
MC		 4050 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4051 return rc;
4052 }
4053
4054 if (len32 & 3) {
c873879c
MC		 4055 align_end = 4 - (len32 & 3);
4056 len32 += align_end;
4057 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4058 return rc;
b6016b76
MC		 4059 }
4060
4061 if (align_start || align_end) {
e6be763f
MC		 4062 align_buf = kmalloc(len32, GFP_KERNEL);
4063 if (align_buf == NULL)
b6016b76
MC		 4064 return -ENOMEM;
4065 if (align_start) {
e6be763f 4066 memcpy(align_buf, start, 4);
b6016b76
MC		 4067 }
4068 if (align_end) {
e6be763f 4069 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4070 }
e6be763f
MC		 4071 memcpy(align_buf + align_start, data_buf, buf_size);
4072 buf = align_buf;
b6016b76
MC		 4073 }
4074
e30372c9 4075 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4076 flash_buffer = kmalloc(264, GFP_KERNEL);
4077 if (flash_buffer == NULL) {
4078 rc = -ENOMEM;
4079 goto nvram_write_end;
4080 }
4081 }
4082
b6016b76
MC		 4083 written = 0;
4084 while ((written < len32) && (rc == 0)) {
4085 u32 page_start, page_end, data_start, data_end;
4086 u32 addr, cmd_flags;
4087 int i;
b6016b76
MC		 4088
4089 /* Find the page_start addr */
4090 page_start = offset32 + written;
4091 page_start -= (page_start % bp->flash_info->page_size);
4092 /* Find the page_end addr */
4093 page_end = page_start + bp->flash_info->page_size;
4094 /* Find the data_start addr */
4095 data_start = (written == 0) ? offset32 : page_start;
4096 /* Find the data_end addr */
6aa20a22 4097 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4098 (offset32 + len32) : page_end;
4099
4100 /* Request access to the flash interface. */
4101 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4102 goto nvram_write_end;
4103
4104 /* Enable access to flash interface */
4105 bnx2_enable_nvram_access(bp);
4106
4107 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4108 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4109 int j;
4110
4111 /* Read the whole page into the buffer
4112 * (non-buffer flash only) */
4113 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4114 if (j == (bp->flash_info->page_size - 4)) {
4115 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4116 }
4117 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4118 page_start + j,
4119 &flash_buffer[j],
b6016b76
MC		 4120 cmd_flags);
4121
4122 if (rc)
4123 goto nvram_write_end;
4124
4125 cmd_flags = 0;
4126 }
4127 }
4128
4129 /* Enable writes to flash interface (unlock write-protect) */
4130 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4131 goto nvram_write_end;
4132
b6016b76
MC		 4133 /* Loop to write back the buffer data from page_start to
4134 * data_start */
4135 i = 0;
e30372c9 4136 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4137 /* Erase the page */
4138 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4139 goto nvram_write_end;
4140
4141 /* Re-enable the write again for the actual write */
4142 bnx2_enable_nvram_write(bp);
4143
b6016b76
MC		 4144 for (addr = page_start; addr < data_start;
4145 addr += 4, i += 4) {
6aa20a22 4146
b6016b76
MC		 4147 rc = bnx2_nvram_write_dword(bp, addr,
4148 &flash_buffer[i], cmd_flags);
4149
4150 if (rc != 0)
4151 goto nvram_write_end;
4152
4153 cmd_flags = 0;
4154 }
4155 }
4156
4157 /* Loop to write the new data from data_start to data_end */
bae25761 4158 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4159 if ((addr == page_end - 4) ||
e30372c9 4160 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4161 (addr == data_end - 4))) {
4162
4163 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4164 }
4165 rc = bnx2_nvram_write_dword(bp, addr, buf,
4166 cmd_flags);
4167
4168 if (rc != 0)
4169 goto nvram_write_end;
4170
4171 cmd_flags = 0;
4172 buf += 4;
4173 }
4174
4175 /* Loop to write back the buffer data from data_end
4176 * to page_end */
e30372c9 4177 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4178 for (addr = data_end; addr < page_end;
4179 addr += 4, i += 4) {
6aa20a22 4180
b6016b76
MC		 4181 if (addr == page_end-4) {
4182 cmd_flags = BNX2_NVM_COMMAND_LAST;
4183 }
4184 rc = bnx2_nvram_write_dword(bp, addr,
4185 &flash_buffer[i], cmd_flags);
4186
4187 if (rc != 0)
4188 goto nvram_write_end;
4189
4190 cmd_flags = 0;
4191 }
4192 }
4193
4194 /* Disable writes to flash interface (lock write-protect) */
4195 bnx2_disable_nvram_write(bp);
4196
4197 /* Disable access to flash interface */
4198 bnx2_disable_nvram_access(bp);
4199 bnx2_release_nvram_lock(bp);
4200
4201 /* Increment written */
4202 written += data_end - data_start;
4203 }
4204
4205nvram_write_end:
e6be763f
MC		 4206 kfree(flash_buffer);
4207 kfree(align_buf);
b6016b76
MC		 4208 return rc;
4209}
4210
0d8a6571
MC		 4211static void
4212bnx2_init_remote_phy(struct bnx2 *bp)
4213{
4214 u32 val;
4215
583c28e5
MC		 4216 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4217 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
0d8a6571
MC		 4218 return;
4219
2726d6e1 4220 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4221 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4222 return;
4223
4224 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
583c28e5 4225 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4226
2726d6e1 4227 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571
MC		 4228 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4229 bp->phy_port = PORT_FIBRE;
4230 else
4231 bp->phy_port = PORT_TP;
489310a4
MC		 4232
4233 if (netif_running(bp->dev)) {
4234 u32 sig;
4235
489310a4
MC		 4236 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4237 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
2726d6e1 4238 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
489310a4 4239 }
0d8a6571
MC		 4240 }
4241}
4242
b4b36042
MC		 4243static void
4244bnx2_setup_msix_tbl(struct bnx2 *bp)
4245{
4246 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4247
4248 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4249 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4250}
4251
b6016b76
MC		 4252static int
4253bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4254{
4255 u32 val;
4256 int i, rc = 0;
489310a4 4257 u8 old_port;
b6016b76
MC		 4258
4259 /* Wait for the current PCI transaction to complete before
4260 * issuing a reset. */
4261 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4262 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4263 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4264 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4265 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4266 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4267 udelay(5);
4268
b090ae2b
MC		 4269 /* Wait for the firmware to tell us it is ok to issue a reset. */
4270 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4271
b6016b76
MC		 4272 /* Deposit a driver reset signature so the firmware knows that
4273 * this is a soft reset. */
2726d6e1
MC		 4274 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4275 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4276
b6016b76
MC		 4277 /* Do a dummy read to force the chip to complete all current transaction
4278 * before we issue a reset. */
4279 val = REG_RD(bp, BNX2_MISC_ID);
4280
234754d5
MC		 4281 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4282 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4283 REG_RD(bp, BNX2_MISC_COMMAND);
4284 udelay(5);
b6016b76 4285
234754d5
MC		 4286 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4287 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4288
234754d5 4289 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4290
234754d5
MC		 4291 } else {
4292 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4293 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4294 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4295
4296 /* Chip reset. */
4297 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4298
594a9dfa
MC		 4299 /* Reading back any register after chip reset will hang the
4300 * bus on 5706 A0 and A1. The msleep below provides plenty
4301 * of margin for write posting.
4302 */
234754d5 4303 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4304 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4305 msleep(20);
b6016b76 4306
234754d5
MC		 4307 /* Reset takes approximate 30 usec */
4308 for (i = 0; i < 10; i++) {
4309 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4310 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4311 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4312 break;
4313 udelay(10);
4314 }
4315
4316 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4317 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4318 printk(KERN_ERR PFX "Chip reset did not complete\n");
4319 return -EBUSY;
4320 }
b6016b76
MC		 4321 }
4322
4323 /* Make sure byte swapping is properly configured. */
4324 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4325 if (val != 0x01020304) {
4326 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4327 return -ENODEV;
4328 }
4329
b6016b76 4330 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 4331 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4332 if (rc)
4333 return rc;
b6016b76 4334
0d8a6571 4335 spin_lock_bh(&bp->phy_lock);
489310a4 4336 old_port = bp->phy_port;
0d8a6571 4337 bnx2_init_remote_phy(bp);
583c28e5
MC		 4338 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4339 old_port != bp->phy_port)
0d8a6571
MC		 4340 bnx2_set_default_remote_link(bp);
4341 spin_unlock_bh(&bp->phy_lock);
4342
b6016b76
MC		 4343 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4344 /* Adjust the voltage regular to two steps lower. The default
4345 * of this register is 0x0000000e. */
4346 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4347
4348 /* Remove bad rbuf memory from the free pool. */
4349 rc = bnx2_alloc_bad_rbuf(bp);
4350 }
4351
f86e82fb 4352 if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 4353 bnx2_setup_msix_tbl(bp);
4354
b6016b76
MC		 4355 return rc;
4356}
4357
4358static int
4359bnx2_init_chip(struct bnx2 *bp)
4360{
4361 u32 val;
b4b36042 4362 int rc, i;
b6016b76
MC		 4363
4364 /* Make sure the interrupt is not active. */
4365 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4366
4367 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4368 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4369#ifdef __BIG_ENDIAN
6aa20a22 4370 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4371#endif
6aa20a22 4372 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4373 DMA_READ_CHANS << 12 |
4374 DMA_WRITE_CHANS << 16;
4375
4376 val |= (0x2 << 20) | (1 << 11);
4377
f86e82fb 4378 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4379 val |= (1 << 23);
4380
4381 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4382 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4383 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4384
4385 REG_WR(bp, BNX2_DMA_CONFIG, val);
4386
4387 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4388 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4389 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4390 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4391 }
4392
f86e82fb 4393 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4394 u16 val16;
4395
4396 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4397 &val16);
4398 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4399 val16 & ~PCI_X_CMD_ERO);
4400 }
4401
4402 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4403 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4404 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4405 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4406
4407 /* Initialize context mapping and zero out the quick contexts. The
4408 * context block must have already been enabled. */
641bdcd5
MC		 4409 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4410 rc = bnx2_init_5709_context(bp);
4411 if (rc)
4412 return rc;
4413 } else
59b47d8a 4414 bnx2_init_context(bp);
b6016b76 4415
fba9fe91
MC		 4416 if ((rc = bnx2_init_cpus(bp)) != 0)
4417 return rc;
4418
b6016b76
MC		 4419 bnx2_init_nvram(bp);
4420
4421 bnx2_set_mac_addr(bp);
4422
4423 val = REG_RD(bp, BNX2_MQ_CONFIG);
4424 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4425 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
68c9f75a
MC		 4426 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4427 val |= BNX2_MQ_CONFIG_HALT_DIS;
4428
b6016b76
MC		 4429 REG_WR(bp, BNX2_MQ_CONFIG, val);
4430
4431 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4432 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4433 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4434
4435 val = (BCM_PAGE_BITS - 8) << 24;
4436 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4437
4438 /* Configure page size. */
4439 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4440 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4441 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4442 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4443
4444 val = bp->mac_addr[0] +
4445 (bp->mac_addr[1] << 8) +
4446 (bp->mac_addr[2] << 16) +
4447 bp->mac_addr[3] +
4448 (bp->mac_addr[4] << 8) +
4449 (bp->mac_addr[5] << 16);
4450 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4451
4452 /* Program the MTU. Also include 4 bytes for CRC32. */
4453 val = bp->dev->mtu + ETH_HLEN + 4;
4454 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4455 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4456 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4457
b4b36042
MC		 4458 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4459 bp->bnx2_napi[i].last_status_idx = 0;
4460
b6016b76
MC		 4461 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4462
4463 /* Set up how to generate a link change interrupt. */
4464 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4465
4466 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4467 (u64) bp->status_blk_mapping & 0xffffffff);
4468 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4469
4470 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4471 (u64) bp->stats_blk_mapping & 0xffffffff);
4472 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4473 (u64) bp->stats_blk_mapping >> 32);
4474
6aa20a22 4475 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4476 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4477
4478 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4479 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4480
4481 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4482 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4483
4484 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4485
4486 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4487
4488 REG_WR(bp, BNX2_HC_COM_TICKS,
4489 (bp->com_ticks_int << 16) | bp->com_ticks);
4490
4491 REG_WR(bp, BNX2_HC_CMD_TICKS,
4492 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4493
02537b06
MC		 4494 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4495 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4496 else
7ea6920e 4497 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4498 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4499
4500 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4501 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4502 else {
8e6a72c4
MC		 4503 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4504 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4505 }
4506
f86e82fb 4507 if (bp->flags & BNX2_FLAG_USING_MSIX) {
6f743ca0
MC		 4508 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4509 BNX2_HC_SB_CONFIG_1;
4510
c76c0475
MC		 4511 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4512 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4513
6f743ca0 4514 REG_WR(bp, base,
c76c0475
MC		 4515 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4516 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4517
6f743ca0 4518 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4519 (bp->tx_quick_cons_trip_int << 16) |
4520 bp->tx_quick_cons_trip);
4521
6f743ca0 4522 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4523 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4524
4525 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4526 }
4527
f86e82fb 4528 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
8e6a72c4
MC		 4529 val |= BNX2_HC_CONFIG_ONE_SHOT;
4530
4531 REG_WR(bp, BNX2_HC_CONFIG, val);
4532
b6016b76
MC		 4533 /* Clear internal stats counters. */
4534 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4535
da3e4fbe 4536 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4537
4538 /* Initialize the receive filter. */
4539 bnx2_set_rx_mode(bp->dev);
4540
0aa38df7
MC		 4541 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4542 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4543 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4544 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4545 }
b090ae2b
MC		 4546 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4547 0);
b6016b76 4548
df149d70 4549 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4550 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4551
4552 udelay(20);
4553
bf5295bb
MC		 4554 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4555
b090ae2b 4556 return rc;
b6016b76
MC		 4557}
4558
c76c0475
MC		 4559static void
4560bnx2_clear_ring_states(struct bnx2 *bp)
4561{
4562 struct bnx2_napi *bnapi;
4563 int i;
4564
4565 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4566 bnapi = &bp->bnx2_napi[i];
4567
4568 bnapi->tx_cons = 0;
4569 bnapi->hw_tx_cons = 0;
4570 bnapi->rx_prod_bseq = 0;
4571 bnapi->rx_prod = 0;
4572 bnapi->rx_cons = 0;
4573 bnapi->rx_pg_prod = 0;
4574 bnapi->rx_pg_cons = 0;
4575 }
4576}
4577
59b47d8a
MC		 4578static void
4579bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4580{
4581 u32 val, offset0, offset1, offset2, offset3;
62a8313c 4582 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 4583
4584 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4585 offset0 = BNX2_L2CTX_TYPE_XI;
4586 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4587 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4588 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4589 } else {
4590 offset0 = BNX2_L2CTX_TYPE;
4591 offset1 = BNX2_L2CTX_CMD_TYPE;
4592 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4593 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4594 }
4595 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 4596 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 4597
4598 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 4599 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a
MC		 4600
4601 val = (u64) bp->tx_desc_mapping >> 32;
62a8313c 4602 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a
MC		 4603
4604 val = (u64) bp->tx_desc_mapping & 0xffffffff;
62a8313c 4605 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 4606}
b6016b76
MC		 4607
4608static void
4609bnx2_init_tx_ring(struct bnx2 *bp)
4610{
4611 struct tx_bd *txbd;
c76c0475
MC		 4612 u32 cid = TX_CID;
4613 struct bnx2_napi *bnapi;
4614
4615 bp->tx_vec = 0;
f86e82fb 4616 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4617 cid = TX_TSS_CID;
4618 bp->tx_vec = BNX2_TX_VEC;
4619 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4620 (TX_TSS_CID << 7));
4621 }
4622 bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 4623
2f8af120
MC		 4624 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4625
b6016b76 4626 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 4627
b6016b76
MC		 4628 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4629 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4630
4631 bp->tx_prod = 0;
b6016b76 4632 bp->tx_prod_bseq = 0;
6aa20a22 4633
59b47d8a
MC		 4634 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4635 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 4636
59b47d8a 4637 bnx2_init_tx_context(bp, cid);
b6016b76
MC		 4638}
4639
4640static void
5d5d0015
MC		 4641bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4642 int num_rings)
b6016b76 4643{
b6016b76 4644 int i;
5d5d0015 4645 struct rx_bd *rxbd;
6aa20a22 4646
5d5d0015 4647 for (i = 0; i < num_rings; i++) {
13daffa2 4648 int j;
b6016b76 4649
5d5d0015 4650 rxbd = &rx_ring[i][0];
13daffa2 4651 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 4652 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 4653 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4654 }
5d5d0015 4655 if (i == (num_rings - 1))
13daffa2
MC		 4656 j = 0;
4657 else
4658 j = i + 1;
5d5d0015
MC		 4659 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4660 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 4661 }
5d5d0015
MC		 4662}
4663
4664static void
4665bnx2_init_rx_ring(struct bnx2 *bp)
4666{
4667 int i;
4668 u16 prod, ring_prod;
4669 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
b4b36042 4670 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
5d5d0015 4671
5d5d0015
MC		 4672 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4673 bp->rx_buf_use_size, bp->rx_max_ring);
4674
83e3fc89
MC		 4675 bnx2_init_rx_context0(bp);
4676
4677 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4678 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4679 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4680 }
4681
62a8313c 4682 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246
MC		 4683 if (bp->rx_pg_ring_size) {
4684 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4685 bp->rx_pg_desc_mapping,
4686 PAGE_SIZE, bp->rx_max_pg_ring);
4687 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 4688 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4689 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
47bf4246
MC		 4690 BNX2_L2CTX_RBDC_JUMBO_KEY);
4691
4692 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
62a8313c 4693 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246
MC		 4694
4695 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 4696 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 4697
4698 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4699 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4700 }
b6016b76 4701
13daffa2 4702 val = (u64) bp->rx_desc_mapping[0] >> 32;
62a8313c 4703 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 4704
13daffa2 4705 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
62a8313c 4706 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 4707
a1f60190 4708 ring_prod = prod = bnapi->rx_pg_prod;
47bf4246
MC		 4709 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4710 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4711 break;
4712 prod = NEXT_RX_BD(prod);
4713 ring_prod = RX_PG_RING_IDX(prod);
4714 }
a1f60190 4715 bnapi->rx_pg_prod = prod;
47bf4246 4716
a1f60190 4717 ring_prod = prod = bnapi->rx_prod;
236b6394 4718 for (i = 0; i < bp->rx_ring_size; i++) {
a1f60190 4719 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
b6016b76
MC		 4720 break;
4721 }
4722 prod = NEXT_RX_BD(prod);
4723 ring_prod = RX_RING_IDX(prod);
4724 }
a1f60190 4725 bnapi->rx_prod = prod;
b6016b76 4726
a1f60190
MC		 4727 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4728 bnapi->rx_pg_prod);
b6016b76
MC		 4729 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4730
a1f60190 4731 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 4732}
4733
5d5d0015 4734static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 4735{
5d5d0015 4736 u32 max, num_rings = 1;
13daffa2 4737
5d5d0015
MC		 4738 while (ring_size > MAX_RX_DESC_CNT) {
4739 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 4740 num_rings++;
4741 }
4742 /* round to next power of 2 */
5d5d0015 4743 max = max_size;
13daffa2
MC		 4744 while ((max & num_rings) == 0)
4745 max >>= 1;
4746
4747 if (num_rings != max)
4748 max <<= 1;
4749
5d5d0015
MC		 4750 return max;
4751}
4752
4753static void
4754bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4755{
84eaa187 4756 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 4757
4758 /* 8 for CRC and VLAN */
d89cb6af 4759 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 4760
84eaa187
MC		 4761 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4762 sizeof(struct skb_shared_info);
4763
601d3d18 4764 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 4765 bp->rx_pg_ring_size = 0;
4766 bp->rx_max_pg_ring = 0;
4767 bp->rx_max_pg_ring_idx = 0;
f86e82fb 4768 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 4769 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4770
4771 jumbo_size = size * pages;
4772 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4773 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4774
4775 bp->rx_pg_ring_size = jumbo_size;
4776 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4777 MAX_RX_PG_RINGS);
4778 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 4779 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 4780 bp->rx_copy_thresh = 0;
4781 }
5d5d0015
MC		 4782
4783 bp->rx_buf_use_size = rx_size;
4784 /* hw alignment */
4785 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 4786 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 4787 bp->rx_ring_size = size;
4788 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 4789 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4790}
4791
b6016b76
MC		 4792static void
4793bnx2_free_tx_skbs(struct bnx2 *bp)
4794{
4795 int i;
4796
4797 if (bp->tx_buf_ring == NULL)
4798 return;
4799
4800 for (i = 0; i < TX_DESC_CNT; ) {
4801 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4802 struct sk_buff *skb = tx_buf->skb;
4803 int j, last;
4804
4805 if (skb == NULL) {
4806 i++;
4807 continue;
4808 }
4809
4810 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4811 skb_headlen(skb), PCI_DMA_TODEVICE);
4812
4813 tx_buf->skb = NULL;
4814
4815 last = skb_shinfo(skb)->nr_frags;
4816 for (j = 0; j < last; j++) {
4817 tx_buf = &bp->tx_buf_ring[i + j + 1];
4818 pci_unmap_page(bp->pdev,
4819 pci_unmap_addr(tx_buf, mapping),
4820 skb_shinfo(skb)->frags[j].size,
4821 PCI_DMA_TODEVICE);
4822 }
745720e5 4823 dev_kfree_skb(skb);
b6016b76
MC		 4824 i += j + 1;
4825 }
4826
4827}
4828
4829static void
4830bnx2_free_rx_skbs(struct bnx2 *bp)
4831{
4832 int i;
4833
4834 if (bp->rx_buf_ring == NULL)
4835 return;
4836
13daffa2 4837 for (i = 0; i < bp->rx_max_ring_idx; i++) {
b6016b76
MC		 4838 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4839 struct sk_buff *skb = rx_buf->skb;
4840
05d0f1cf 4841 if (skb == NULL)
b6016b76
MC		 4842 continue;
4843
4844 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4845 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4846
4847 rx_buf->skb = NULL;
4848
745720e5 4849 dev_kfree_skb(skb);
b6016b76 4850 }
47bf4246
MC		 4851 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4852 bnx2_free_rx_page(bp, i);
b6016b76
MC		 4853}
4854
4855static void
4856bnx2_free_skbs(struct bnx2 *bp)
4857{
4858 bnx2_free_tx_skbs(bp);
4859 bnx2_free_rx_skbs(bp);
4860}
4861
4862static int
4863bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4864{
4865 int rc;
4866
4867 rc = bnx2_reset_chip(bp, reset_code);
4868 bnx2_free_skbs(bp);
4869 if (rc)
4870 return rc;
4871
fba9fe91
MC		 4872 if ((rc = bnx2_init_chip(bp)) != 0)
4873 return rc;
4874
c76c0475 4875 bnx2_clear_ring_states(bp);
b6016b76
MC		 4876 bnx2_init_tx_ring(bp);
4877 bnx2_init_rx_ring(bp);
4878 return 0;
4879}
4880
4881static int
9a120bc5 4882bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 4883{
4884 int rc;
4885
4886 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4887 return rc;
4888
80be4434 4889 spin_lock_bh(&bp->phy_lock);
9a120bc5 4890 bnx2_init_phy(bp, reset_phy);
b6016b76 4891 bnx2_set_link(bp);
543a827d
MC		 4892 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4893 bnx2_remote_phy_event(bp);
0d8a6571 4894 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4895 return 0;
4896}
4897
4898static int
4899bnx2_test_registers(struct bnx2 *bp)
4900{
4901 int ret;
5bae30c9 4902 int i, is_5709;
f71e1309 4903 static const struct {
b6016b76
MC		 4904 u16 offset;
4905 u16 flags;
5bae30c9 4906#define BNX2_FL_NOT_5709 1
b6016b76
MC		 4907 u32 rw_mask;
4908 u32 ro_mask;
4909 } reg_tbl[] = {
4910 { 0x006c, 0, 0x00000000, 0x0000003f },
4911 { 0x0090, 0, 0xffffffff, 0x00000000 },
4912 { 0x0094, 0, 0x00000000, 0x00000000 },
4913
5bae30c9
MC		 4914 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4915 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4916 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4917 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4918 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4919 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4920 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4921 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4922 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4923
4924 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4925 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4926 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4927 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4928 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4929 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4930
4931 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4932 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4933 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 4934
4935 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 4936 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 4937
4938 { 0x1408, 0, 0x01c00800, 0x00000000 },
4939 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4940 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 4941 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 4942 { 0x14b0, 0, 0x00000002, 0x00000001 },
4943 { 0x14b8, 0, 0x00000000, 0x00000000 },
4944 { 0x14c0, 0, 0x00000000, 0x00000009 },
4945 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4946 { 0x14cc, 0, 0x00000000, 0x00000001 },
4947 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 4948
4949 { 0x1800, 0, 0x00000000, 0x00000001 },
4950 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 4951
4952 { 0x2800, 0, 0x00000000, 0x00000001 },
4953 { 0x2804, 0, 0x00000000, 0x00003f01 },
4954 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4955 { 0x2810, 0, 0xffff0000, 0x00000000 },
4956 { 0x2814, 0, 0xffff0000, 0x00000000 },
4957 { 0x2818, 0, 0xffff0000, 0x00000000 },
4958 { 0x281c, 0, 0xffff0000, 0x00000000 },
4959 { 0x2834, 0, 0xffffffff, 0x00000000 },
4960 { 0x2840, 0, 0x00000000, 0xffffffff },
4961 { 0x2844, 0, 0x00000000, 0xffffffff },
4962 { 0x2848, 0, 0xffffffff, 0x00000000 },
4963 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4964
4965 { 0x2c00, 0, 0x00000000, 0x00000011 },
4966 { 0x2c04, 0, 0x00000000, 0x00030007 },
4967
b6016b76
MC		 4968 { 0x3c00, 0, 0x00000000, 0x00000001 },
4969 { 0x3c04, 0, 0x00000000, 0x00070000 },
4970 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4971 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4972 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4973 { 0x3c14, 0, 0x00000000, 0xffffffff },
4974 { 0x3c18, 0, 0x00000000, 0xffffffff },
4975 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4976 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 4977
4978 { 0x5004, 0, 0x00000000, 0x0000007f },
4979 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 4980
b6016b76
MC		 4981 { 0x5c00, 0, 0x00000000, 0x00000001 },
4982 { 0x5c04, 0, 0x00000000, 0x0003000f },
4983 { 0x5c08, 0, 0x00000003, 0x00000000 },
4984 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4985 { 0x5c10, 0, 0x00000000, 0xffffffff },
4986 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4987 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4988 { 0x5c88, 0, 0x00000000, 0x00077373 },
4989 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4990
4991 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4992 { 0x680c, 0, 0xffffffff, 0x00000000 },
4993 { 0x6810, 0, 0xffffffff, 0x00000000 },
4994 { 0x6814, 0, 0xffffffff, 0x00000000 },
4995 { 0x6818, 0, 0xffffffff, 0x00000000 },
4996 { 0x681c, 0, 0xffffffff, 0x00000000 },
4997 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4998 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4999 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5000 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5001 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5002 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5003 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5004 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5005 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5006 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5007 { 0x684c, 0, 0xffffffff, 0x00000000 },
5008 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5009 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5010 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5011 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5012 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5013 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5014
5015 { 0xffff, 0, 0x00000000, 0x00000000 },
5016 };
5017
5018 ret = 0;
5bae30c9
MC		 5019 is_5709 = 0;
5020 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5021 is_5709 = 1;
5022
b6016b76
MC		 5023 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5024 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5025 u16 flags = reg_tbl[i].flags;
5026
5027 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5028 continue;
b6016b76
MC		 5029
5030 offset = (u32) reg_tbl[i].offset;
5031 rw_mask = reg_tbl[i].rw_mask;
5032 ro_mask = reg_tbl[i].ro_mask;
5033
14ab9b86 5034 save_val = readl(bp->regview + offset);
b6016b76 5035
14ab9b86 5036 writel(0, bp->regview + offset);
b6016b76 5037
14ab9b86 5038 val = readl(bp->regview + offset);
b6016b76
MC		 5039 if ((val & rw_mask) != 0) {
5040 goto reg_test_err;
5041 }
5042
5043 if ((val & ro_mask) != (save_val & ro_mask)) {
5044 goto reg_test_err;
5045 }
5046
14ab9b86 5047 writel(0xffffffff, bp->regview + offset);
b6016b76 5048
14ab9b86 5049 val = readl(bp->regview + offset);
b6016b76
MC		 5050 if ((val & rw_mask) != rw_mask) {
5051 goto reg_test_err;
5052 }
5053
5054 if ((val & ro_mask) != (save_val & ro_mask)) {
5055 goto reg_test_err;
5056 }
5057
14ab9b86 5058 writel(save_val, bp->regview + offset);
b6016b76
MC		 5059 continue;
5060
5061reg_test_err:
14ab9b86 5062 writel(save_val, bp->regview + offset);
b6016b76
MC		 5063 ret = -ENODEV;
5064 break;
5065 }
5066 return ret;
5067}
5068
5069static int
5070bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5071{
f71e1309 5072 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5073 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5074 int i;
5075
5076 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5077 u32 offset;
5078
5079 for (offset = 0; offset < size; offset += 4) {
5080
2726d6e1 5081 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5082
2726d6e1 5083 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5084 test_pattern[i]) {
5085 return -ENODEV;
5086 }
5087 }
5088 }
5089 return 0;
5090}
5091
5092static int
5093bnx2_test_memory(struct bnx2 *bp)
5094{
5095 int ret = 0;
5096 int i;
5bae30c9 5097 static struct mem_entry {
b6016b76
MC		 5098 u32 offset;
5099 u32 len;
5bae30c9 5100 } mem_tbl_5706[] = {
b6016b76 5101 { 0x60000, 0x4000 },
5b0c76ad 5102 { 0xa0000, 0x3000 },
b6016b76
MC		 5103 { 0xe0000, 0x4000 },
5104 { 0x120000, 0x4000 },
5105 { 0x1a0000, 0x4000 },
5106 { 0x160000, 0x4000 },
5107 { 0xffffffff, 0 },
5bae30c9
MC		 5108 },
5109 mem_tbl_5709[] = {
5110 { 0x60000, 0x4000 },
5111 { 0xa0000, 0x3000 },
5112 { 0xe0000, 0x4000 },
5113 { 0x120000, 0x4000 },
5114 { 0x1a0000, 0x4000 },
5115 { 0xffffffff, 0 },
b6016b76 5116 };
5bae30c9
MC		 5117 struct mem_entry *mem_tbl;
5118
5119 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5120 mem_tbl = mem_tbl_5709;
5121 else
5122 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5123
5124 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5125 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5126 mem_tbl[i].len)) != 0) {
5127 return ret;
5128 }
5129 }
6aa20a22 5130
b6016b76
MC		 5131 return ret;
5132}
5133
bc5a0690
MC		 5134#define BNX2_MAC_LOOPBACK 0
5135#define BNX2_PHY_LOOPBACK 1
5136
b6016b76 5137static int
bc5a0690 5138bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5139{
5140 unsigned int pkt_size, num_pkts, i;
5141 struct sk_buff *skb, *rx_skb;
5142 unsigned char *packet;
bc5a0690 5143 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5144 dma_addr_t map;
5145 struct tx_bd *txbd;
5146 struct sw_bd *rx_buf;
5147 struct l2_fhdr *rx_hdr;
5148 int ret = -ENODEV;
c76c0475
MC		 5149 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5150
5151 tx_napi = bnapi;
f86e82fb 5152 if (bp->flags & BNX2_FLAG_USING_MSIX)
c76c0475 5153 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
b6016b76 5154
bc5a0690
MC		 5155 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5156 bp->loopback = MAC_LOOPBACK;
5157 bnx2_set_mac_loopback(bp);
5158 }
5159 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5160 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5161 return 0;
5162
80be4434 5163 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5164 bnx2_set_phy_loopback(bp);
5165 }
5166 else
5167 return -EINVAL;
b6016b76 5168
84eaa187 5169 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5170 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5171 if (!skb)
5172 return -ENOMEM;
b6016b76 5173 packet = skb_put(skb, pkt_size);
6634292b 5174 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5175 memset(packet + 6, 0x0, 8);
5176 for (i = 14; i < pkt_size; i++)
5177 packet[i] = (unsigned char) (i & 0xff);
5178
5179 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5180 PCI_DMA_TODEVICE);
5181
bf5295bb
MC		 5182 REG_WR(bp, BNX2_HC_COMMAND,
5183 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5184
b6016b76
MC		 5185 REG_RD(bp, BNX2_HC_COMMAND);
5186
5187 udelay(5);
35efa7c1 5188 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5189
b6016b76
MC		 5190 num_pkts = 0;
5191
bc5a0690 5192 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
b6016b76
MC		 5193
5194 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5195 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5196 txbd->tx_bd_mss_nbytes = pkt_size;
5197 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5198
5199 num_pkts++;
bc5a0690
MC		 5200 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5201 bp->tx_prod_bseq += pkt_size;
b6016b76 5202
234754d5
MC		 5203 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5204 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5205
5206 udelay(100);
5207
bf5295bb
MC		 5208 REG_WR(bp, BNX2_HC_COMMAND,
5209 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5210
b6016b76
MC		 5211 REG_RD(bp, BNX2_HC_COMMAND);
5212
5213 udelay(5);
5214
5215 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5216 dev_kfree_skb(skb);
b6016b76 5217
c76c0475 5218 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
b6016b76 5219 goto loopback_test_done;
b6016b76 5220
35efa7c1 5221 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5222 if (rx_idx != rx_start_idx + num_pkts) {
5223 goto loopback_test_done;
5224 }
5225
5226 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5227 rx_skb = rx_buf->skb;
5228
5229 rx_hdr = (struct l2_fhdr *) rx_skb->data;
d89cb6af 5230 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76
MC		 5231
5232 pci_dma_sync_single_for_cpu(bp->pdev,
5233 pci_unmap_addr(rx_buf, mapping),
5234 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5235
ade2bfe7 5236 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5237 (L2_FHDR_ERRORS_BAD_CRC |
5238 L2_FHDR_ERRORS_PHY_DECODE |
5239 L2_FHDR_ERRORS_ALIGNMENT |
5240 L2_FHDR_ERRORS_TOO_SHORT |
5241 L2_FHDR_ERRORS_GIANT_FRAME)) {
5242
5243 goto loopback_test_done;
5244 }
5245
5246 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5247 goto loopback_test_done;
5248 }
5249
5250 for (i = 14; i < pkt_size; i++) {
5251 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5252 goto loopback_test_done;
5253 }
5254 }
5255
5256 ret = 0;
5257
5258loopback_test_done:
5259 bp->loopback = 0;
5260 return ret;
5261}
5262
bc5a0690
MC		 5263#define BNX2_MAC_LOOPBACK_FAILED 1
5264#define BNX2_PHY_LOOPBACK_FAILED 2
5265#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5266 BNX2_PHY_LOOPBACK_FAILED)
5267
5268static int
5269bnx2_test_loopback(struct bnx2 *bp)
5270{
5271 int rc = 0;
5272
5273 if (!netif_running(bp->dev))
5274 return BNX2_LOOPBACK_FAILED;
5275
5276 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5277 spin_lock_bh(&bp->phy_lock);
9a120bc5 5278 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5279 spin_unlock_bh(&bp->phy_lock);
5280 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5281 rc |= BNX2_MAC_LOOPBACK_FAILED;
5282 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5283 rc |= BNX2_PHY_LOOPBACK_FAILED;
5284 return rc;
5285}
5286
b6016b76
MC		 5287#define NVRAM_SIZE 0x200
5288#define CRC32_RESIDUAL 0xdebb20e3
5289
5290static int
5291bnx2_test_nvram(struct bnx2 *bp)
5292{
b491edd5 5293 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5294 u8 *data = (u8 *) buf;
5295 int rc = 0;
5296 u32 magic, csum;
5297
5298 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5299 goto test_nvram_done;
5300
5301 magic = be32_to_cpu(buf[0]);
5302 if (magic != 0x669955aa) {
5303 rc = -ENODEV;
5304 goto test_nvram_done;
5305 }
5306
5307 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5308 goto test_nvram_done;
5309
5310 csum = ether_crc_le(0x100, data);
5311 if (csum != CRC32_RESIDUAL) {
5312 rc = -ENODEV;
5313 goto test_nvram_done;
5314 }
5315
5316 csum = ether_crc_le(0x100, data + 0x100);
5317 if (csum != CRC32_RESIDUAL) {
5318 rc = -ENODEV;
5319 }
5320
5321test_nvram_done:
5322 return rc;
5323}
5324
5325static int
5326bnx2_test_link(struct bnx2 *bp)
5327{
5328 u32 bmsr;
5329
583c28e5 5330 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5331 if (bp->link_up)
5332 return 0;
5333 return -ENODEV;
5334 }
c770a65c 5335 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5336 bnx2_enable_bmsr1(bp);
5337 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5338 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5339 bnx2_disable_bmsr1(bp);
c770a65c 5340 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5341
b6016b76
MC		 5342 if (bmsr & BMSR_LSTATUS) {
5343 return 0;
5344 }
5345 return -ENODEV;
5346}
5347
5348static int
5349bnx2_test_intr(struct bnx2 *bp)
5350{
5351 int i;
b6016b76
MC		 5352 u16 status_idx;
5353
5354 if (!netif_running(bp->dev))
5355 return -ENODEV;
5356
5357 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5358
5359 /* This register is not touched during run-time. */
bf5295bb 5360 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5361 REG_RD(bp, BNX2_HC_COMMAND);
5362
5363 for (i = 0; i < 10; i++) {
5364 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5365 status_idx) {
5366
5367 break;
5368 }
5369
5370 msleep_interruptible(10);
5371 }
5372 if (i < 10)
5373 return 0;
5374
5375 return -ENODEV;
5376}
5377
38ea3686 5378/* Determining link for parallel detection. */
b2fadeae
MC		 5379static int
5380bnx2_5706_serdes_has_link(struct bnx2 *bp)
5381{
5382 u32 mode_ctl, an_dbg, exp;
5383
38ea3686
MC		 5384 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5385 return 0;
5386
b2fadeae
MC		 5387 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5388 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5389
5390 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5391 return 0;
5392
5393 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5394 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5395 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5396
f3014c0c 5397 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5398 return 0;
5399
5400 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5401 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5402 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5403
5404 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5405 return 0;
5406
5407 return 1;
5408}
5409
b6016b76 5410static void
48b01e2d 5411bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5412{
b2fadeae
MC		 5413 int check_link = 1;
5414
48b01e2d 5415 spin_lock(&bp->phy_lock);
b2fadeae 5416 if (bp->serdes_an_pending) {
48b01e2d 5417 bp->serdes_an_pending--;
b2fadeae
MC		 5418 check_link = 0;
5419 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5420 u32 bmcr;
b6016b76 5421
48b01e2d 5422 bp->current_interval = bp->timer_interval;
cd339a0e 5423
ca58c3af 5424 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5425
48b01e2d 5426 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5427 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5428 bmcr &= ~BMCR_ANENABLE;
5429 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5430 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5431 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5432 }
b6016b76 5433 }
48b01e2d
MC		 5434 }
5435 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5436 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5437 u32 phy2;
b6016b76 5438
48b01e2d
MC		 5439 bnx2_write_phy(bp, 0x17, 0x0f01);
5440 bnx2_read_phy(bp, 0x15, &phy2);
5441 if (phy2 & 0x20) {
5442 u32 bmcr;
cd339a0e 5443
ca58c3af 5444 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5445 bmcr |= BMCR_ANENABLE;
ca58c3af 5446 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5447
583c28e5 5448 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5449 }
5450 } else
5451 bp->current_interval = bp->timer_interval;
b6016b76 5452
a2724e25 5453 if (check_link) {
b2fadeae
MC		 5454 u32 val;
5455
5456 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5457 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5458 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5459
a2724e25
MC		 5460 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5461 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5462 bnx2_5706s_force_link_dn(bp, 1);
5463 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5464 } else
5465 bnx2_set_link(bp);
5466 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5467 bnx2_set_link(bp);
b2fadeae 5468 }
48b01e2d
MC		 5469 spin_unlock(&bp->phy_lock);
5470}
b6016b76 5471
f8dd064e
MC		 5472static void
5473bnx2_5708_serdes_timer(struct bnx2 *bp)
5474{
583c28e5 5475 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 5476 return;
5477
583c28e5 5478 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 5479 bp->serdes_an_pending = 0;
5480 return;
5481 }
b6016b76 5482
f8dd064e
MC		 5483 spin_lock(&bp->phy_lock);
5484 if (bp->serdes_an_pending)
5485 bp->serdes_an_pending--;
5486 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5487 u32 bmcr;
b6016b76 5488
ca58c3af 5489 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 5490 if (bmcr & BMCR_ANENABLE) {
605a9e20 5491 bnx2_enable_forced_2g5(bp);
f8dd064e
MC		 5492 bp->current_interval = SERDES_FORCED_TIMEOUT;
5493 } else {
605a9e20 5494 bnx2_disable_forced_2g5(bp);
f8dd064e
MC		 5495 bp->serdes_an_pending = 2;
5496 bp->current_interval = bp->timer_interval;
b6016b76 5497 }
b6016b76 5498
f8dd064e
MC		 5499 } else
5500 bp->current_interval = bp->timer_interval;
b6016b76 5501
f8dd064e
MC		 5502 spin_unlock(&bp->phy_lock);
5503}
5504
48b01e2d
MC		 5505static void
5506bnx2_timer(unsigned long data)
5507{
5508 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 5509
48b01e2d
MC		 5510 if (!netif_running(bp->dev))
5511 return;
b6016b76 5512
48b01e2d
MC		 5513 if (atomic_read(&bp->intr_sem) != 0)
5514 goto bnx2_restart_timer;
b6016b76 5515
df149d70 5516 bnx2_send_heart_beat(bp);
b6016b76 5517
2726d6e1
MC		 5518 bp->stats_blk->stat_FwRxDrop =
5519 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 5520
02537b06
MC		 5521 /* workaround occasional corrupted counters */
5522 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5523 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5524 BNX2_HC_COMMAND_STATS_NOW);
5525
583c28e5 5526 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 5527 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5528 bnx2_5706_serdes_timer(bp);
27a005b8 5529 else
f8dd064e 5530 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 5531 }
5532
5533bnx2_restart_timer:
cd339a0e 5534 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5535}
5536
8e6a72c4
MC		 5537static int
5538bnx2_request_irq(struct bnx2 *bp)
5539{
5540 struct net_device *dev = bp->dev;
6d866ffc 5541 unsigned long flags;
b4b36042
MC		 5542 struct bnx2_irq *irq;
5543 int rc = 0, i;
8e6a72c4 5544
f86e82fb 5545 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 5546 flags = 0;
5547 else
5548 flags = IRQF_SHARED;
b4b36042
MC		 5549
5550 for (i = 0; i < bp->irq_nvecs; i++) {
5551 irq = &bp->irq_tbl[i];
c76c0475 5552 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
b4b36042
MC		 5553 dev);
5554 if (rc)
5555 break;
5556 irq->requested = 1;
5557 }
8e6a72c4
MC		 5558 return rc;
5559}
5560
5561static void
5562bnx2_free_irq(struct bnx2 *bp)
5563{
5564 struct net_device *dev = bp->dev;
b4b36042
MC		 5565 struct bnx2_irq *irq;
5566 int i;
8e6a72c4 5567
b4b36042
MC		 5568 for (i = 0; i < bp->irq_nvecs; i++) {
5569 irq = &bp->irq_tbl[i];
5570 if (irq->requested)
5571 free_irq(irq->vector, dev);
5572 irq->requested = 0;
6d866ffc 5573 }
f86e82fb 5574 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 5575 pci_disable_msi(bp->pdev);
f86e82fb 5576 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 5577 pci_disable_msix(bp->pdev);
5578
f86e82fb 5579 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 5580}
5581
5582static void
5583bnx2_enable_msix(struct bnx2 *bp)
5584{
57851d84
MC		 5585 int i, rc;
5586 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5587
b4b36042
MC		 5588 bnx2_setup_msix_tbl(bp);
5589 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5590 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5591 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84
MC		 5592
5593 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5594 msix_ent[i].entry = i;
5595 msix_ent[i].vector = 0;
5596 }
5597
5598 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5599 if (rc != 0)
5600 return;
5601
5602 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5603 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5604
5605 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5606 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5607 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5608 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5609
5610 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
f86e82fb 5611 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
57851d84
MC		 5612 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5613 bp->irq_tbl[i].vector = msix_ent[i].vector;
6d866ffc
MC		 5614}
5615
5616static void
5617bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5618{
5619 bp->irq_tbl[0].handler = bnx2_interrupt;
5620 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 5621 bp->irq_nvecs = 1;
5622 bp->irq_tbl[0].vector = bp->pdev->irq;
5623
f86e82fb 5624 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
b4b36042 5625 bnx2_enable_msix(bp);
6d866ffc 5626
f86e82fb
DM		 5627 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5628 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 5629 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 5630 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 5631 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 5632 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 5633 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5634 } else
5635 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 5636
5637 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 5638 }
5639 }
8e6a72c4
MC		 5640}
5641
b6016b76
MC		 5642/* Called with rtnl_lock */
5643static int
5644bnx2_open(struct net_device *dev)
5645{
972ec0d4 5646 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5647 int rc;
5648
1b2f922f
MC		 5649 netif_carrier_off(dev);
5650
829ca9a3 5651 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5652 bnx2_disable_int(bp);
5653
5654 rc = bnx2_alloc_mem(bp);
5655 if (rc)
5656 return rc;
5657
6d866ffc 5658 bnx2_setup_int_mode(bp, disable_msi);
35efa7c1 5659 bnx2_napi_enable(bp);
8e6a72c4
MC		 5660 rc = bnx2_request_irq(bp);
5661
b6016b76 5662 if (rc) {
35efa7c1 5663 bnx2_napi_disable(bp);
b6016b76
MC		 5664 bnx2_free_mem(bp);
5665 return rc;
5666 }
5667
9a120bc5 5668 rc = bnx2_init_nic(bp, 1);
b6016b76
MC		 5669
5670 if (rc) {
35efa7c1 5671 bnx2_napi_disable(bp);
8e6a72c4 5672 bnx2_free_irq(bp);
b6016b76
MC		 5673 bnx2_free_skbs(bp);
5674 bnx2_free_mem(bp);
5675 return rc;
5676 }
6aa20a22 5677
cd339a0e 5678 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5679
5680 atomic_set(&bp->intr_sem, 0);
5681
5682 bnx2_enable_int(bp);
5683
f86e82fb 5684 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 5685 /* Test MSI to make sure it is working
5686 * If MSI test fails, go back to INTx mode
5687 */
5688 if (bnx2_test_intr(bp) != 0) {
5689 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5690 " using MSI, switching to INTx mode. Please"
5691 " report this failure to the PCI maintainer"
5692 " and include system chipset information.\n",
5693 bp->dev->name);
5694
5695 bnx2_disable_int(bp);
8e6a72c4 5696 bnx2_free_irq(bp);
b6016b76 5697
6d866ffc
MC		 5698 bnx2_setup_int_mode(bp, 1);
5699
9a120bc5 5700 rc = bnx2_init_nic(bp, 0);
b6016b76 5701
8e6a72c4
MC		 5702 if (!rc)
5703 rc = bnx2_request_irq(bp);
5704
b6016b76 5705 if (rc) {
35efa7c1 5706 bnx2_napi_disable(bp);
b6016b76
MC		 5707 bnx2_free_skbs(bp);
5708 bnx2_free_mem(bp);
5709 del_timer_sync(&bp->timer);
5710 return rc;
5711 }
5712 bnx2_enable_int(bp);
5713 }
5714 }
f86e82fb 5715 if (bp->flags & BNX2_FLAG_USING_MSI)
b6016b76 5716 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
f86e82fb 5717 else if (bp->flags & BNX2_FLAG_USING_MSIX)
57851d84 5718 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
b6016b76
MC		 5719
5720 netif_start_queue(dev);
5721
5722 return 0;
5723}
5724
5725static void
c4028958 5726bnx2_reset_task(struct work_struct *work)
b6016b76 5727{
c4028958 5728 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 5729
afdc08b9
MC		 5730 if (!netif_running(bp->dev))
5731 return;
5732
5733 bp->in_reset_task = 1;
b6016b76
MC		 5734 bnx2_netif_stop(bp);
5735
9a120bc5 5736 bnx2_init_nic(bp, 1);
b6016b76
MC		 5737
5738 atomic_set(&bp->intr_sem, 1);
5739 bnx2_netif_start(bp);
afdc08b9 5740 bp->in_reset_task = 0;
b6016b76
MC		 5741}
5742
5743static void
5744bnx2_tx_timeout(struct net_device *dev)
5745{
972ec0d4 5746 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5747
5748 /* This allows the netif to be shutdown gracefully before resetting */
5749 schedule_work(&bp->reset_task);
5750}
5751
5752#ifdef BCM_VLAN
5753/* Called with rtnl_lock */
5754static void
5755bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5756{
972ec0d4 5757 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5758
5759 bnx2_netif_stop(bp);
5760
5761 bp->vlgrp = vlgrp;
5762 bnx2_set_rx_mode(dev);
5763
5764 bnx2_netif_start(bp);
5765}
b6016b76
MC		 5766#endif
5767
932ff279 5768/* Called with netif_tx_lock.
2f8af120
MC		 5769 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5770 * netif_wake_queue().
b6016b76
MC		 5771 */
5772static int
5773bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5774{
972ec0d4 5775 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5776 dma_addr_t mapping;
5777 struct tx_bd *txbd;
5778 struct sw_bd *tx_buf;
5779 u32 len, vlan_tag_flags, last_frag, mss;
5780 u16 prod, ring_prod;
5781 int i;
57851d84 5782 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 5783
a550c99b
MC		 5784 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5785 (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 5786 netif_stop_queue(dev);
5787 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5788 dev->name);
5789
5790 return NETDEV_TX_BUSY;
5791 }
5792 len = skb_headlen(skb);
5793 prod = bp->tx_prod;
5794 ring_prod = TX_RING_IDX(prod);
5795
5796 vlan_tag_flags = 0;
84fa7933 5797 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 5798 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5799 }
5800
79ea13ce 5801 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 5802 vlan_tag_flags |=
5803 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5804 }
fde82055 5805 if ((mss = skb_shinfo(skb)->gso_size)) {
b6016b76 5806 u32 tcp_opt_len, ip_tcp_len;
eddc9ec5 5807 struct iphdr *iph;
b6016b76 5808
b6016b76
MC		 5809 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5810
4666f87a
MC		 5811 tcp_opt_len = tcp_optlen(skb);
5812
5813 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5814 u32 tcp_off = skb_transport_offset(skb) -
5815 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 5816
4666f87a
MC		 5817 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5818 TX_BD_FLAGS_SW_FLAGS;
5819 if (likely(tcp_off == 0))
5820 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5821 else {
5822 tcp_off >>= 3;
5823 vlan_tag_flags |= ((tcp_off & 0x3) <<
5824 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5825 ((tcp_off & 0x10) <<
5826 TX_BD_FLAGS_TCP6_OFF4_SHL);
5827 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5828 }
5829 } else {
5830 if (skb_header_cloned(skb) &&
5831 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5832 dev_kfree_skb(skb);
5833 return NETDEV_TX_OK;
5834 }
b6016b76 5835
4666f87a
MC		 5836 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5837
5838 iph = ip_hdr(skb);
5839 iph->check = 0;
5840 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5841 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5842 iph->daddr, 0,
5843 IPPROTO_TCP,
5844 0);
5845 if (tcp_opt_len || (iph->ihl > 5)) {
5846 vlan_tag_flags |= ((iph->ihl - 5) +
5847 (tcp_opt_len >> 2)) << 8;
5848 }
b6016b76 5849 }
4666f87a 5850 } else
b6016b76 5851 mss = 0;
b6016b76
MC		 5852
5853 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6aa20a22 5854
b6016b76
MC		 5855 tx_buf = &bp->tx_buf_ring[ring_prod];
5856 tx_buf->skb = skb;
5857 pci_unmap_addr_set(tx_buf, mapping, mapping);
5858
5859 txbd = &bp->tx_desc_ring[ring_prod];
5860
5861 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5862 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5863 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5864 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5865
5866 last_frag = skb_shinfo(skb)->nr_frags;
5867
5868 for (i = 0; i < last_frag; i++) {
5869 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5870
5871 prod = NEXT_TX_BD(prod);
5872 ring_prod = TX_RING_IDX(prod);
5873 txbd = &bp->tx_desc_ring[ring_prod];
5874
5875 len = frag->size;
5876 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5877 len, PCI_DMA_TODEVICE);
5878 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5879 mapping, mapping);
5880
5881 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5882 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5883 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5884 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5885
5886 }
5887 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5888
5889 prod = NEXT_TX_BD(prod);
5890 bp->tx_prod_bseq += skb->len;
5891
234754d5
MC		 5892 REG_WR16(bp, bp->tx_bidx_addr, prod);
5893 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5894
5895 mmiowb();
5896
5897 bp->tx_prod = prod;
5898 dev->trans_start = jiffies;
5899
a550c99b 5900 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
e89bbf10 5901 netif_stop_queue(dev);
a550c99b 5902 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
e89bbf10 5903 netif_wake_queue(dev);
b6016b76
MC		 5904 }
5905
5906 return NETDEV_TX_OK;
5907}
5908
5909/* Called with rtnl_lock */
5910static int
5911bnx2_close(struct net_device *dev)
5912{
972ec0d4 5913 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5914 u32 reset_code;
5915
afdc08b9
MC		 5916 /* Calling flush_scheduled_work() may deadlock because
5917 * linkwatch_event() may be on the workqueue and it will try to get
5918 * the rtnl_lock which we are holding.
5919 */
5920 while (bp->in_reset_task)
5921 msleep(1);
5922
bea3348e 5923 bnx2_disable_int_sync(bp);
35efa7c1 5924 bnx2_napi_disable(bp);
b6016b76 5925 del_timer_sync(&bp->timer);
f86e82fb 5926 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 5927 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 5928 else if (bp->wol)
b6016b76
MC		 5929 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5930 else
5931 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5932 bnx2_reset_chip(bp, reset_code);
8e6a72c4 5933 bnx2_free_irq(bp);
b6016b76
MC		 5934 bnx2_free_skbs(bp);
5935 bnx2_free_mem(bp);
5936 bp->link_up = 0;
5937 netif_carrier_off(bp->dev);
829ca9a3 5938 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 5939 return 0;
5940}
5941
5942#define GET_NET_STATS64(ctr) \
5943 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5944 (unsigned long) (ctr##_lo)
5945
5946#define GET_NET_STATS32(ctr) \
5947 (ctr##_lo)
5948
5949#if (BITS_PER_LONG == 64)
5950#define GET_NET_STATS GET_NET_STATS64
5951#else
5952#define GET_NET_STATS GET_NET_STATS32
5953#endif
5954
5955static struct net_device_stats *
5956bnx2_get_stats(struct net_device *dev)
5957{
972ec0d4 5958 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5959 struct statistics_block *stats_blk = bp->stats_blk;
5960 struct net_device_stats *net_stats = &bp->net_stats;
5961
5962 if (bp->stats_blk == NULL) {
5963 return net_stats;
5964 }
5965 net_stats->rx_packets =
5966 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5967 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5968 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5969
5970 net_stats->tx_packets =
5971 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5972 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5973 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5974
5975 net_stats->rx_bytes =
5976 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5977
5978 net_stats->tx_bytes =
5979 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5980
6aa20a22 5981 net_stats->multicast =
b6016b76
MC		 5982 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5983
6aa20a22 5984 net_stats->collisions =
b6016b76
MC		 5985 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5986
6aa20a22 5987 net_stats->rx_length_errors =
b6016b76
MC		 5988 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5989 stats_blk->stat_EtherStatsOverrsizePkts);
5990
6aa20a22 5991 net_stats->rx_over_errors =
b6016b76
MC		 5992 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5993
6aa20a22 5994 net_stats->rx_frame_errors =
b6016b76
MC		 5995 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5996
6aa20a22 5997 net_stats->rx_crc_errors =
b6016b76
MC		 5998 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5999
6000 net_stats->rx_errors = net_stats->rx_length_errors +
6001 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6002 net_stats->rx_crc_errors;
6003
6004 net_stats->tx_aborted_errors =
6005 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6006 stats_blk->stat_Dot3StatsLateCollisions);
6007
5b0c76ad
MC		 6008 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6009 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6010 net_stats->tx_carrier_errors = 0;
6011 else {
6012 net_stats->tx_carrier_errors =
6013 (unsigned long)
6014 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6015 }
6016
6017 net_stats->tx_errors =
6aa20a22 6018 (unsigned long)
b6016b76
MC		 6019 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6020 +
6021 net_stats->tx_aborted_errors +
6022 net_stats->tx_carrier_errors;
6023
cea94db9
MC		 6024 net_stats->rx_missed_errors =
6025 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6026 stats_blk->stat_FwRxDrop);
6027
b6016b76
MC		 6028 return net_stats;
6029}
6030
6031/* All ethtool functions called with rtnl_lock */
6032
6033static int
6034bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6035{
972ec0d4 6036 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6037 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6038
6039 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6040 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6041 support_serdes = 1;
6042 support_copper = 1;
6043 } else if (bp->phy_port == PORT_FIBRE)
6044 support_serdes = 1;
6045 else
6046 support_copper = 1;
6047
6048 if (support_serdes) {
b6016b76
MC		 6049 cmd->supported |= SUPPORTED_1000baseT_Full |
6050 SUPPORTED_FIBRE;
583c28e5 6051 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6052 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6053
b6016b76 6054 }
7b6b8347 6055 if (support_copper) {
b6016b76
MC		 6056 cmd->supported |= SUPPORTED_10baseT_Half |
6057 SUPPORTED_10baseT_Full |
6058 SUPPORTED_100baseT_Half |
6059 SUPPORTED_100baseT_Full |
6060 SUPPORTED_1000baseT_Full |
6061 SUPPORTED_TP;
6062
b6016b76
MC		 6063 }
6064
7b6b8347
MC		 6065 spin_lock_bh(&bp->phy_lock);
6066 cmd->port = bp->phy_port;
b6016b76
MC		 6067 cmd->advertising = bp->advertising;
6068
6069 if (bp->autoneg & AUTONEG_SPEED) {
6070 cmd->autoneg = AUTONEG_ENABLE;
6071 }
6072 else {
6073 cmd->autoneg = AUTONEG_DISABLE;
6074 }
6075
6076 if (netif_carrier_ok(dev)) {
6077 cmd->speed = bp->line_speed;
6078 cmd->duplex = bp->duplex;
6079 }
6080 else {
6081 cmd->speed = -1;
6082 cmd->duplex = -1;
6083 }
7b6b8347 6084 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6085
6086 cmd->transceiver = XCVR_INTERNAL;
6087 cmd->phy_address = bp->phy_addr;
6088
6089 return 0;
6090}
6aa20a22 6091
b6016b76
MC		 6092static int
6093bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6094{
972ec0d4 6095 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6096 u8 autoneg = bp->autoneg;
6097 u8 req_duplex = bp->req_duplex;
6098 u16 req_line_speed = bp->req_line_speed;
6099 u32 advertising = bp->advertising;
7b6b8347
MC		 6100 int err = -EINVAL;
6101
6102 spin_lock_bh(&bp->phy_lock);
6103
6104 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6105 goto err_out_unlock;
6106
583c28e5
MC		 6107 if (cmd->port != bp->phy_port &&
6108 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6109 goto err_out_unlock;
b6016b76
MC		 6110
6111 if (cmd->autoneg == AUTONEG_ENABLE) {
6112 autoneg |= AUTONEG_SPEED;
6113
6aa20a22 6114 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6115
6116 /* allow advertising 1 speed */
6117 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6118 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6119 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6120 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6121
7b6b8347
MC		 6122 if (cmd->port == PORT_FIBRE)
6123 goto err_out_unlock;
b6016b76
MC		 6124
6125 advertising = cmd->advertising;
6126
27a005b8 6127 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
583c28e5 6128 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
7b6b8347
MC		 6129 (cmd->port == PORT_TP))
6130 goto err_out_unlock;
6131 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
b6016b76 6132 advertising = cmd->advertising;
7b6b8347
MC		 6133 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6134 goto err_out_unlock;
b6016b76 6135 else {
7b6b8347 6136 if (cmd->port == PORT_FIBRE)
b6016b76 6137 advertising = ETHTOOL_ALL_FIBRE_SPEED;
7b6b8347 6138 else
b6016b76 6139 advertising = ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6140 }
6141 advertising |= ADVERTISED_Autoneg;
6142 }
6143 else {
7b6b8347 6144 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6145 if ((cmd->speed != SPEED_1000 &&
6146 cmd->speed != SPEED_2500) ||
6147 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6148 goto err_out_unlock;
80be4434
MC		 6149
6150 if (cmd->speed == SPEED_2500 &&
583c28e5 6151 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6152 goto err_out_unlock;
b6016b76 6153 }
7b6b8347
MC		 6154 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6155 goto err_out_unlock;
6156
b6016b76
MC		 6157 autoneg &= ~AUTONEG_SPEED;
6158 req_line_speed = cmd->speed;
6159 req_duplex = cmd->duplex;
6160 advertising = 0;
6161 }
6162
6163 bp->autoneg = autoneg;
6164 bp->advertising = advertising;
6165 bp->req_line_speed = req_line_speed;
6166 bp->req_duplex = req_duplex;
6167
7b6b8347 6168 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6169
7b6b8347 6170err_out_unlock:
c770a65c 6171 spin_unlock_bh(&bp->phy_lock);
b6016b76 6172
7b6b8347 6173 return err;
b6016b76
MC		 6174}
6175
6176static void
6177bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6178{
972ec0d4 6179 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6180
6181 strcpy(info->driver, DRV_MODULE_NAME);
6182 strcpy(info->version, DRV_MODULE_VERSION);
6183 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6184 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6185}
6186
244ac4f4
MC		 6187#define BNX2_REGDUMP_LEN (32 * 1024)
6188
6189static int
6190bnx2_get_regs_len(struct net_device *dev)
6191{
6192 return BNX2_REGDUMP_LEN;
6193}
6194
6195static void
6196bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6197{
6198 u32 *p = _p, i, offset;
6199 u8 *orig_p = _p;
6200 struct bnx2 *bp = netdev_priv(dev);
6201 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6202 0x0800, 0x0880, 0x0c00, 0x0c10,
6203 0x0c30, 0x0d08, 0x1000, 0x101c,
6204 0x1040, 0x1048, 0x1080, 0x10a4,
6205 0x1400, 0x1490, 0x1498, 0x14f0,
6206 0x1500, 0x155c, 0x1580, 0x15dc,
6207 0x1600, 0x1658, 0x1680, 0x16d8,
6208 0x1800, 0x1820, 0x1840, 0x1854,
6209 0x1880, 0x1894, 0x1900, 0x1984,
6210 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6211 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6212 0x2000, 0x2030, 0x23c0, 0x2400,
6213 0x2800, 0x2820, 0x2830, 0x2850,
6214 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6215 0x3c00, 0x3c94, 0x4000, 0x4010,
6216 0x4080, 0x4090, 0x43c0, 0x4458,
6217 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6218 0x4fc0, 0x5010, 0x53c0, 0x5444,
6219 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6220 0x5fc0, 0x6000, 0x6400, 0x6428,
6221 0x6800, 0x6848, 0x684c, 0x6860,
6222 0x6888, 0x6910, 0x8000 };
6223
6224 regs->version = 0;
6225
6226 memset(p, 0, BNX2_REGDUMP_LEN);
6227
6228 if (!netif_running(bp->dev))
6229 return;
6230
6231 i = 0;
6232 offset = reg_boundaries[0];
6233 p += offset;
6234 while (offset < BNX2_REGDUMP_LEN) {
6235 *p++ = REG_RD(bp, offset);
6236 offset += 4;
6237 if (offset == reg_boundaries[i + 1]) {
6238 offset = reg_boundaries[i + 2];
6239 p = (u32 *) (orig_p + offset);
6240 i += 2;
6241 }
6242 }
6243}
6244
b6016b76
MC		 6245static void
6246bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6247{
972ec0d4 6248 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6249
f86e82fb 6250 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6251 wol->supported = 0;
6252 wol->wolopts = 0;
6253 }
6254 else {
6255 wol->supported = WAKE_MAGIC;
6256 if (bp->wol)
6257 wol->wolopts = WAKE_MAGIC;
6258 else
6259 wol->wolopts = 0;
6260 }
6261 memset(&wol->sopass, 0, sizeof(wol->sopass));
6262}
6263
6264static int
6265bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6266{
972ec0d4 6267 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6268
6269 if (wol->wolopts & ~WAKE_MAGIC)
6270 return -EINVAL;
6271
6272 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6273 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6274 return -EINVAL;
6275
6276 bp->wol = 1;
6277 }
6278 else {
6279 bp->wol = 0;
6280 }
6281 return 0;
6282}
6283
6284static int
6285bnx2_nway_reset(struct net_device *dev)
6286{
972ec0d4 6287 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6288 u32 bmcr;
6289
6290 if (!(bp->autoneg & AUTONEG_SPEED)) {
6291 return -EINVAL;
6292 }
6293
c770a65c 6294 spin_lock_bh(&bp->phy_lock);
b6016b76 6295
583c28e5 6296 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6297 int rc;
6298
6299 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6300 spin_unlock_bh(&bp->phy_lock);
6301 return rc;
6302 }
6303
b6016b76 6304 /* Force a link down visible on the other side */
583c28e5 6305 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6306 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6307 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6308
6309 msleep(20);
6310
c770a65c 6311 spin_lock_bh(&bp->phy_lock);
f8dd064e
MC		 6312
6313 bp->current_interval = SERDES_AN_TIMEOUT;
6314 bp->serdes_an_pending = 1;
6315 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6316 }
6317
ca58c3af 6318 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6319 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6320 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6321
c770a65c 6322 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6323
6324 return 0;
6325}
6326
6327static int
6328bnx2_get_eeprom_len(struct net_device *dev)
6329{
972ec0d4 6330 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6331
1122db71 6332 if (bp->flash_info == NULL)
b6016b76
MC		 6333 return 0;
6334
1122db71 6335 return (int) bp->flash_size;
b6016b76
MC		 6336}
6337
6338static int
6339bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6340 u8 *eebuf)
6341{
972ec0d4 6342 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6343 int rc;
6344
1064e944 6345 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6346
6347 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6348
6349 return rc;
6350}
6351
6352static int
6353bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6354 u8 *eebuf)
6355{
972ec0d4 6356 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6357 int rc;
6358
1064e944 6359 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6360
6361 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6362
6363 return rc;
6364}
6365
6366static int
6367bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6368{
972ec0d4 6369 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6370
6371 memset(coal, 0, sizeof(struct ethtool_coalesce));
6372
6373 coal->rx_coalesce_usecs = bp->rx_ticks;
6374 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6375 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6376 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6377
6378 coal->tx_coalesce_usecs = bp->tx_ticks;
6379 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6380 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6381 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6382
6383 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6384
6385 return 0;
6386}
6387
6388static int
6389bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6390{
972ec0d4 6391 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6392
6393 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6394 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6395
6aa20a22 6396 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 6397 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6398
6399 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6400 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6401
6402 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6403 if (bp->rx_quick_cons_trip_int > 0xff)
6404 bp->rx_quick_cons_trip_int = 0xff;
6405
6406 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6407 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6408
6409 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6410 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6411
6412 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6413 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6414
6415 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6416 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6417 0xff;
6418
6419 bp->stats_ticks = coal->stats_block_coalesce_usecs;
02537b06
MC		 6420 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6421 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6422 bp->stats_ticks = USEC_PER_SEC;
6423 }
7ea6920e
MC		 6424 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6425 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6426 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 6427
6428 if (netif_running(bp->dev)) {
6429 bnx2_netif_stop(bp);
9a120bc5 6430 bnx2_init_nic(bp, 0);
b6016b76
MC		 6431 bnx2_netif_start(bp);
6432 }
6433
6434 return 0;
6435}
6436
6437static void
6438bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6439{
972ec0d4 6440 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6441
13daffa2 6442 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 6443 ering->rx_mini_max_pending = 0;
47bf4246 6444 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 6445
6446 ering->rx_pending = bp->rx_ring_size;
6447 ering->rx_mini_pending = 0;
47bf4246 6448 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 6449
6450 ering->tx_max_pending = MAX_TX_DESC_CNT;
6451 ering->tx_pending = bp->tx_ring_size;
6452}
6453
6454static int
5d5d0015 6455bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 6456{
13daffa2
MC		 6457 if (netif_running(bp->dev)) {
6458 bnx2_netif_stop(bp);
6459 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6460 bnx2_free_skbs(bp);
6461 bnx2_free_mem(bp);
6462 }
6463
5d5d0015
MC		 6464 bnx2_set_rx_ring_size(bp, rx);
6465 bp->tx_ring_size = tx;
b6016b76
MC		 6466
6467 if (netif_running(bp->dev)) {
13daffa2
MC		 6468 int rc;
6469
6470 rc = bnx2_alloc_mem(bp);
6471 if (rc)
6472 return rc;
9a120bc5 6473 bnx2_init_nic(bp, 0);
b6016b76
MC		 6474 bnx2_netif_start(bp);
6475 }
b6016b76
MC		 6476 return 0;
6477}
6478
5d5d0015
MC		 6479static int
6480bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6481{
6482 struct bnx2 *bp = netdev_priv(dev);
6483 int rc;
6484
6485 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6486 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6487 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6488
6489 return -EINVAL;
6490 }
6491 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6492 return rc;
6493}
6494
b6016b76
MC		 6495static void
6496bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6497{
972ec0d4 6498 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6499
6500 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6501 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6502 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6503}
6504
6505static int
6506bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6507{
972ec0d4 6508 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6509
6510 bp->req_flow_ctrl = 0;
6511 if (epause->rx_pause)
6512 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6513 if (epause->tx_pause)
6514 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6515
6516 if (epause->autoneg) {
6517 bp->autoneg |= AUTONEG_FLOW_CTRL;
6518 }
6519 else {
6520 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6521 }
6522
c770a65c 6523 spin_lock_bh(&bp->phy_lock);
b6016b76 6524
0d8a6571 6525 bnx2_setup_phy(bp, bp->phy_port);
b6016b76 6526
c770a65c 6527 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6528
6529 return 0;
6530}
6531
6532static u32
6533bnx2_get_rx_csum(struct net_device *dev)
6534{
972ec0d4 6535 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6536
6537 return bp->rx_csum;
6538}
6539
6540static int
6541bnx2_set_rx_csum(struct net_device *dev, u32 data)
6542{
972ec0d4 6543 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6544
6545 bp->rx_csum = data;
6546 return 0;
6547}
6548
b11d6213
MC		 6549static int
6550bnx2_set_tso(struct net_device *dev, u32 data)
6551{
4666f87a
MC		 6552 struct bnx2 *bp = netdev_priv(dev);
6553
6554 if (data) {
b11d6213 6555 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 6556 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6557 dev->features |= NETIF_F_TSO6;
6558 } else
6559 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6560 NETIF_F_TSO_ECN);
b11d6213
MC		 6561 return 0;
6562}
6563
cea94db9 6564#define BNX2_NUM_STATS 46
b6016b76 6565
14ab9b86 6566static struct {
b6016b76
MC		 6567 char string[ETH_GSTRING_LEN];
6568} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6569 { "rx_bytes" },
6570 { "rx_error_bytes" },
6571 { "tx_bytes" },
6572 { "tx_error_bytes" },
6573 { "rx_ucast_packets" },
6574 { "rx_mcast_packets" },
6575 { "rx_bcast_packets" },
6576 { "tx_ucast_packets" },
6577 { "tx_mcast_packets" },
6578 { "tx_bcast_packets" },
6579 { "tx_mac_errors" },
6580 { "tx_carrier_errors" },
6581 { "rx_crc_errors" },
6582 { "rx_align_errors" },
6583 { "tx_single_collisions" },
6584 { "tx_multi_collisions" },
6585 { "tx_deferred" },
6586 { "tx_excess_collisions" },
6587 { "tx_late_collisions" },
6588 { "tx_total_collisions" },
6589 { "rx_fragments" },
6590 { "rx_jabbers" },
6591 { "rx_undersize_packets" },
6592 { "rx_oversize_packets" },
6593 { "rx_64_byte_packets" },
6594 { "rx_65_to_127_byte_packets" },
6595 { "rx_128_to_255_byte_packets" },
6596 { "rx_256_to_511_byte_packets" },
6597 { "rx_512_to_1023_byte_packets" },
6598 { "rx_1024_to_1522_byte_packets" },
6599 { "rx_1523_to_9022_byte_packets" },
6600 { "tx_64_byte_packets" },
6601 { "tx_65_to_127_byte_packets" },
6602 { "tx_128_to_255_byte_packets" },
6603 { "tx_256_to_511_byte_packets" },
6604 { "tx_512_to_1023_byte_packets" },
6605 { "tx_1024_to_1522_byte_packets" },
6606 { "tx_1523_to_9022_byte_packets" },
6607 { "rx_xon_frames" },
6608 { "rx_xoff_frames" },
6609 { "tx_xon_frames" },
6610 { "tx_xoff_frames" },
6611 { "rx_mac_ctrl_frames" },
6612 { "rx_filtered_packets" },
6613 { "rx_discards" },
cea94db9 6614 { "rx_fw_discards" },
b6016b76
MC		 6615};
6616
6617#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6618
f71e1309 6619static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6620 STATS_OFFSET32(stat_IfHCInOctets_hi),
6621 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6622 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6623 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6624 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6625 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6626 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6627 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6628 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6629 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6630 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 6631 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6632 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6633 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6634 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6635 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6636 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6637 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6638 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6639 STATS_OFFSET32(stat_EtherStatsCollisions),
6640 STATS_OFFSET32(stat_EtherStatsFragments),
6641 STATS_OFFSET32(stat_EtherStatsJabbers),
6642 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6643 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6644 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6645 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6646 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6647 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6648 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6649 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6650 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6651 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6652 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6653 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6654 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6655 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6656 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6657 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6658 STATS_OFFSET32(stat_XonPauseFramesReceived),
6659 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6660 STATS_OFFSET32(stat_OutXonSent),
6661 STATS_OFFSET32(stat_OutXoffSent),
6662 STATS_OFFSET32(stat_MacControlFramesReceived),
6663 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6664 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 6665 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 6666};
6667
6668/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6669 * skipped because of errata.
6aa20a22 6670 */
14ab9b86 6671static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6672 8,0,8,8,8,8,8,8,8,8,
6673 4,0,4,4,4,4,4,4,4,4,
6674 4,4,4,4,4,4,4,4,4,4,
6675 4,4,4,4,4,4,4,4,4,4,
cea94db9 6676 4,4,4,4,4,4,
b6016b76
MC		 6677};
6678
5b0c76ad
MC		 6679static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6680 8,0,8,8,8,8,8,8,8,8,
6681 4,4,4,4,4,4,4,4,4,4,
6682 4,4,4,4,4,4,4,4,4,4,
6683 4,4,4,4,4,4,4,4,4,4,
cea94db9 6684 4,4,4,4,4,4,
5b0c76ad
MC		 6685};
6686
b6016b76
MC		 6687#define BNX2_NUM_TESTS 6
6688
14ab9b86 6689static struct {
b6016b76
MC		 6690 char string[ETH_GSTRING_LEN];
6691} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6692 { "register_test (offline)" },
6693 { "memory_test (offline)" },
6694 { "loopback_test (offline)" },
6695 { "nvram_test (online)" },
6696 { "interrupt_test (online)" },
6697 { "link_test (online)" },
6698};
6699
6700static int
b9f2c044 6701bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 6702{
b9f2c044
JG		 6703 switch (sset) {
6704 case ETH_SS_TEST:
6705 return BNX2_NUM_TESTS;
6706 case ETH_SS_STATS:
6707 return BNX2_NUM_STATS;
6708 default:
6709 return -EOPNOTSUPP;
6710 }
b6016b76
MC		 6711}
6712
6713static void
6714bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6715{
972ec0d4 6716 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6717
6718 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6719 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 6720 int i;
6721
b6016b76
MC		 6722 bnx2_netif_stop(bp);
6723 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6724 bnx2_free_skbs(bp);
6725
6726 if (bnx2_test_registers(bp) != 0) {
6727 buf[0] = 1;
6728 etest->flags |= ETH_TEST_FL_FAILED;
6729 }
6730 if (bnx2_test_memory(bp) != 0) {
6731 buf[1] = 1;
6732 etest->flags |= ETH_TEST_FL_FAILED;
6733 }
bc5a0690 6734 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 6735 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76
MC		 6736
6737 if (!netif_running(bp->dev)) {
6738 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6739 }
6740 else {
9a120bc5 6741 bnx2_init_nic(bp, 1);
b6016b76
MC		 6742 bnx2_netif_start(bp);
6743 }
6744
6745 /* wait for link up */
80be4434
MC		 6746 for (i = 0; i < 7; i++) {
6747 if (bp->link_up)
6748 break;
6749 msleep_interruptible(1000);
6750 }
b6016b76
MC		 6751 }
6752
6753 if (bnx2_test_nvram(bp) != 0) {
6754 buf[3] = 1;
6755 etest->flags |= ETH_TEST_FL_FAILED;
6756 }
6757 if (bnx2_test_intr(bp) != 0) {
6758 buf[4] = 1;
6759 etest->flags |= ETH_TEST_FL_FAILED;
6760 }
6761
6762 if (bnx2_test_link(bp) != 0) {
6763 buf[5] = 1;
6764 etest->flags |= ETH_TEST_FL_FAILED;
6765
6766 }
6767}
6768
6769static void
6770bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6771{
6772 switch (stringset) {
6773 case ETH_SS_STATS:
6774 memcpy(buf, bnx2_stats_str_arr,
6775 sizeof(bnx2_stats_str_arr));
6776 break;
6777 case ETH_SS_TEST:
6778 memcpy(buf, bnx2_tests_str_arr,
6779 sizeof(bnx2_tests_str_arr));
6780 break;
6781 }
6782}
6783
b6016b76
MC		 6784static void
6785bnx2_get_ethtool_stats(struct net_device *dev,
6786 struct ethtool_stats *stats, u64 *buf)
6787{
972ec0d4 6788 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6789 int i;
6790 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 6791 u8 *stats_len_arr = NULL;
b6016b76
MC		 6792
6793 if (hw_stats == NULL) {
6794 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6795 return;
6796 }
6797
5b0c76ad
MC		 6798 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6799 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6800 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6801 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 6802 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 6803 else
6804 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 6805
6806 for (i = 0; i < BNX2_NUM_STATS; i++) {
6807 if (stats_len_arr[i] == 0) {
6808 /* skip this counter */
6809 buf[i] = 0;
6810 continue;
6811 }
6812 if (stats_len_arr[i] == 4) {
6813 /* 4-byte counter */
6814 buf[i] = (u64)
6815 *(hw_stats + bnx2_stats_offset_arr[i]);
6816 continue;
6817 }
6818 /* 8-byte counter */
6819 buf[i] = (((u64) *(hw_stats +
6820 bnx2_stats_offset_arr[i])) << 32) +
6821 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6822 }
6823}
6824
6825static int
6826bnx2_phys_id(struct net_device *dev, u32 data)
6827{
972ec0d4 6828 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6829 int i;
6830 u32 save;
6831
6832 if (data == 0)
6833 data = 2;
6834
6835 save = REG_RD(bp, BNX2_MISC_CFG);
6836 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6837
6838 for (i = 0; i < (data * 2); i++) {
6839 if ((i % 2) == 0) {
6840 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6841 }
6842 else {
6843 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6844 BNX2_EMAC_LED_1000MB_OVERRIDE |
6845 BNX2_EMAC_LED_100MB_OVERRIDE |
6846 BNX2_EMAC_LED_10MB_OVERRIDE |
6847 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6848 BNX2_EMAC_LED_TRAFFIC);
6849 }
6850 msleep_interruptible(500);
6851 if (signal_pending(current))
6852 break;
6853 }
6854 REG_WR(bp, BNX2_EMAC_LED, 0);
6855 REG_WR(bp, BNX2_MISC_CFG, save);
6856 return 0;
6857}
6858
4666f87a
MC		 6859static int
6860bnx2_set_tx_csum(struct net_device *dev, u32 data)
6861{
6862 struct bnx2 *bp = netdev_priv(dev);
6863
6864 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 6865 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 6866 else
6867 return (ethtool_op_set_tx_csum(dev, data));
6868}
6869
7282d491 6870static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 6871 .get_settings = bnx2_get_settings,
6872 .set_settings = bnx2_set_settings,
6873 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 6874 .get_regs_len = bnx2_get_regs_len,
6875 .get_regs = bnx2_get_regs,
b6016b76
MC		 6876 .get_wol = bnx2_get_wol,
6877 .set_wol = bnx2_set_wol,
6878 .nway_reset = bnx2_nway_reset,
6879 .get_link = ethtool_op_get_link,
6880 .get_eeprom_len = bnx2_get_eeprom_len,
6881 .get_eeprom = bnx2_get_eeprom,
6882 .set_eeprom = bnx2_set_eeprom,
6883 .get_coalesce = bnx2_get_coalesce,
6884 .set_coalesce = bnx2_set_coalesce,
6885 .get_ringparam = bnx2_get_ringparam,
6886 .set_ringparam = bnx2_set_ringparam,
6887 .get_pauseparam = bnx2_get_pauseparam,
6888 .set_pauseparam = bnx2_set_pauseparam,
6889 .get_rx_csum = bnx2_get_rx_csum,
6890 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 6891 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 6892 .set_sg = ethtool_op_set_sg,
b11d6213 6893 .set_tso = bnx2_set_tso,
b6016b76
MC		 6894 .self_test = bnx2_self_test,
6895 .get_strings = bnx2_get_strings,
6896 .phys_id = bnx2_phys_id,
b6016b76 6897 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 6898 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 6899};
6900
6901/* Called with rtnl_lock */
6902static int
6903bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6904{
14ab9b86 6905 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 6906 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6907 int err;
6908
6909 switch(cmd) {
6910 case SIOCGMIIPHY:
6911 data->phy_id = bp->phy_addr;
6912
6913 /* fallthru */
6914 case SIOCGMIIREG: {
6915 u32 mii_regval;
6916
583c28e5 6917 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6918 return -EOPNOTSUPP;
6919
dad3e452
MC		 6920 if (!netif_running(dev))
6921 return -EAGAIN;
6922
c770a65c 6923 spin_lock_bh(&bp->phy_lock);
b6016b76 6924 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 6925 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6926
6927 data->val_out = mii_regval;
6928
6929 return err;
6930 }
6931
6932 case SIOCSMIIREG:
6933 if (!capable(CAP_NET_ADMIN))
6934 return -EPERM;
6935
583c28e5 6936 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6937 return -EOPNOTSUPP;
6938
dad3e452
MC		 6939 if (!netif_running(dev))
6940 return -EAGAIN;
6941
c770a65c 6942 spin_lock_bh(&bp->phy_lock);
b6016b76 6943 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 6944 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6945
6946 return err;
6947
6948 default:
6949 /* do nothing */
6950 break;
6951 }
6952 return -EOPNOTSUPP;
6953}
6954
6955/* Called with rtnl_lock */
6956static int
6957bnx2_change_mac_addr(struct net_device *dev, void *p)
6958{
6959 struct sockaddr *addr = p;
972ec0d4 6960 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6961
73eef4cd
MC		 6962 if (!is_valid_ether_addr(addr->sa_data))
6963 return -EINVAL;
6964
b6016b76
MC		 6965 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6966 if (netif_running(dev))
6967 bnx2_set_mac_addr(bp);
6968
6969 return 0;
6970}
6971
6972/* Called with rtnl_lock */
6973static int
6974bnx2_change_mtu(struct net_device *dev, int new_mtu)
6975{
972ec0d4 6976 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6977
6978 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6979 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6980 return -EINVAL;
6981
6982 dev->mtu = new_mtu;
5d5d0015 6983 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 6984}
6985
6986#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6987static void
6988poll_bnx2(struct net_device *dev)
6989{
972ec0d4 6990 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6991
6992 disable_irq(bp->pdev->irq);
7d12e780 6993 bnx2_interrupt(bp->pdev->irq, dev);
b6016b76
MC		 6994 enable_irq(bp->pdev->irq);
6995}
6996#endif
6997
253c8b75
MC		 6998static void __devinit
6999bnx2_get_5709_media(struct bnx2 *bp)
7000{
7001 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7002 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7003 u32 strap;
7004
7005 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7006 return;
7007 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7008 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7009 return;
7010 }
7011
7012 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7013 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7014 else
7015 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7016
7017 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7018 switch (strap) {
7019 case 0x4:
7020 case 0x5:
7021 case 0x6:
583c28e5 7022 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7023 return;
7024 }
7025 } else {
7026 switch (strap) {
7027 case 0x1:
7028 case 0x2:
7029 case 0x4:
583c28e5 7030 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7031 return;
7032 }
7033 }
7034}
7035
883e5151
MC		 7036static void __devinit
7037bnx2_get_pci_speed(struct bnx2 *bp)
7038{
7039 u32 reg;
7040
7041 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7042 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7043 u32 clkreg;
7044
f86e82fb 7045 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7046
7047 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7048
7049 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7050 switch (clkreg) {
7051 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7052 bp->bus_speed_mhz = 133;
7053 break;
7054
7055 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7056 bp->bus_speed_mhz = 100;
7057 break;
7058
7059 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7060 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7061 bp->bus_speed_mhz = 66;
7062 break;
7063
7064 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7065 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7066 bp->bus_speed_mhz = 50;
7067 break;
7068
7069 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7070 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7071 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7072 bp->bus_speed_mhz = 33;
7073 break;
7074 }
7075 }
7076 else {
7077 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7078 bp->bus_speed_mhz = 66;
7079 else
7080 bp->bus_speed_mhz = 33;
7081 }
7082
7083 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7084 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7085
7086}
7087
b6016b76
MC		 7088static int __devinit
7089bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7090{
7091 struct bnx2 *bp;
7092 unsigned long mem_len;
58fc2ea4 7093 int rc, i, j;
b6016b76 7094 u32 reg;
40453c83 7095 u64 dma_mask, persist_dma_mask;
b6016b76 7096
b6016b76 7097 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7098 bp = netdev_priv(dev);
b6016b76
MC		 7099
7100 bp->flags = 0;
7101 bp->phy_flags = 0;
7102
7103 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7104 rc = pci_enable_device(pdev);
7105 if (rc) {
898eb71c 7106 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
b6016b76
MC		 7107 goto err_out;
7108 }
7109
7110 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7111 dev_err(&pdev->dev,
2e8a538d 7112 "Cannot find PCI device base address, aborting.\n");
b6016b76
MC		 7113 rc = -ENODEV;
7114 goto err_out_disable;
7115 }
7116
7117 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7118 if (rc) {
9b91cf9d 7119 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
b6016b76
MC		 7120 goto err_out_disable;
7121 }
7122
7123 pci_set_master(pdev);
6ff2da49 7124 pci_save_state(pdev);
b6016b76
MC		 7125
7126 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7127 if (bp->pm_cap == 0) {
9b91cf9d 7128 dev_err(&pdev->dev,
2e8a538d 7129 "Cannot find power management capability, aborting.\n");
b6016b76
MC		 7130 rc = -EIO;
7131 goto err_out_release;
7132 }
7133
b6016b76
MC		 7134 bp->dev = dev;
7135 bp->pdev = pdev;
7136
7137 spin_lock_init(&bp->phy_lock);
1b8227c4 7138 spin_lock_init(&bp->indirect_lock);
c4028958 7139 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7140
7141 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
59b47d8a 7142 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
b6016b76
MC		 7143 dev->mem_end = dev->mem_start + mem_len;
7144 dev->irq = pdev->irq;
7145
7146 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7147
7148 if (!bp->regview) {
9b91cf9d 7149 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
b6016b76
MC		 7150 rc = -ENOMEM;
7151 goto err_out_release;
7152 }
7153
7154 /* Configure byte swap and enable write to the reg_window registers.
7155 * Rely on CPU to do target byte swapping on big endian systems
7156 * The chip's target access swapping will not swap all accesses
7157 */
7158 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7159 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7160 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7161
829ca9a3 7162 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7163
7164 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7165
883e5151
MC		 7166 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7167 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7168 dev_err(&pdev->dev,
7169 "Cannot find PCIE capability, aborting.\n");
7170 rc = -EIO;
7171 goto err_out_unmap;
7172 }
f86e82fb 7173 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7174 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7175 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7176 } else {
59b47d8a
MC		 7177 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7178 if (bp->pcix_cap == 0) {
7179 dev_err(&pdev->dev,
7180 "Cannot find PCIX capability, aborting.\n");
7181 rc = -EIO;
7182 goto err_out_unmap;
7183 }
7184 }
7185
b4b36042
MC		 7186 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7187 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7188 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7189 }
7190
8e6a72c4
MC		 7191 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7192 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7193 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7194 }
7195
40453c83
MC		 7196 /* 5708 cannot support DMA addresses > 40-bit. */
7197 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7198 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7199 else
7200 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7201
7202 /* Configure DMA attributes. */
7203 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7204 dev->features |= NETIF_F_HIGHDMA;
7205 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7206 if (rc) {
7207 dev_err(&pdev->dev,
7208 "pci_set_consistent_dma_mask failed, aborting.\n");
7209 goto err_out_unmap;
7210 }
7211 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7212 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7213 goto err_out_unmap;
7214 }
7215
f86e82fb 7216 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7217 bnx2_get_pci_speed(bp);
b6016b76
MC		 7218
7219 /* 5706A0 may falsely detect SERR and PERR. */
7220 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7221 reg = REG_RD(bp, PCI_COMMAND);
7222 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7223 REG_WR(bp, PCI_COMMAND, reg);
7224 }
7225 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 7226 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 7227
9b91cf9d 7228 dev_err(&pdev->dev,
2e8a538d 7229 "5706 A1 can only be used in a PCIX bus, aborting.\n");
b6016b76
MC		 7230 goto err_out_unmap;
7231 }
7232
7233 bnx2_init_nvram(bp);
7234
2726d6e1 7235 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 7236
7237 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 7238 BNX2_SHM_HDR_SIGNATURE_SIG) {
7239 u32 off = PCI_FUNC(pdev->devfn) << 2;
7240
2726d6e1 7241 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 7242 } else
e3648b3d
MC		 7243 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7244
b6016b76
MC		 7245 /* Get the permanent MAC address. First we need to make sure the
7246 * firmware is actually running.
7247 */
2726d6e1 7248 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 7249
7250 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7251 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
9b91cf9d 7252 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
b6016b76
MC		 7253 rc = -ENODEV;
7254 goto err_out_unmap;
7255 }
7256
2726d6e1 7257 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
58fc2ea4
MC		 7258 for (i = 0, j = 0; i < 3; i++) {
7259 u8 num, k, skip0;
7260
7261 num = (u8) (reg >> (24 - (i * 8)));
7262 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7263 if (num >= k || !skip0 || k == 1) {
7264 bp->fw_version[j++] = (num / k) + '0';
7265 skip0 = 0;
7266 }
7267 }
7268 if (i != 2)
7269 bp->fw_version[j++] = '.';
7270 }
2726d6e1 7271 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 7272 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7273 bp->wol = 1;
7274
7275 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 7276 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 7277
7278 for (i = 0; i < 30; i++) {
2726d6e1 7279 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 7280 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7281 break;
7282 msleep(10);
7283 }
7284 }
2726d6e1 7285 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 7286 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7287 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7288 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7289 int i;
2726d6e1 7290 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4
MC		 7291
7292 bp->fw_version[j++] = ' ';
7293 for (i = 0; i < 3; i++) {
2726d6e1 7294 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 7295 reg = swab32(reg);
7296 memcpy(&bp->fw_version[j], &reg, 4);
7297 j += 4;
7298 }
7299 }
b6016b76 7300
2726d6e1 7301 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 7302 bp->mac_addr[0] = (u8) (reg >> 8);
7303 bp->mac_addr[1] = (u8) reg;
7304
2726d6e1 7305 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 7306 bp->mac_addr[2] = (u8) (reg >> 24);
7307 bp->mac_addr[3] = (u8) (reg >> 16);
7308 bp->mac_addr[4] = (u8) (reg >> 8);
7309 bp->mac_addr[5] = (u8) reg;
7310
7311 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 7312 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 7313
7314 bp->rx_csum = 1;
7315
b6016b76
MC		 7316 bp->tx_quick_cons_trip_int = 20;
7317 bp->tx_quick_cons_trip = 20;
7318 bp->tx_ticks_int = 80;
7319 bp->tx_ticks = 80;
6aa20a22 7320
b6016b76
MC		 7321 bp->rx_quick_cons_trip_int = 6;
7322 bp->rx_quick_cons_trip = 6;
7323 bp->rx_ticks_int = 18;
7324 bp->rx_ticks = 18;
7325
7ea6920e 7326 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7327
7328 bp->timer_interval = HZ;
cd339a0e 7329 bp->current_interval = HZ;
b6016b76 7330
5b0c76ad
MC		 7331 bp->phy_addr = 1;
7332
b6016b76 7333 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 7334 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7335 bnx2_get_5709_media(bp);
7336 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 7337 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 7338
0d8a6571 7339 bp->phy_port = PORT_TP;
583c28e5 7340 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 7341 bp->phy_port = PORT_FIBRE;
2726d6e1 7342 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 7343 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 7344 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7345 bp->wol = 0;
7346 }
38ea3686
MC		 7347 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7348 /* Don't do parallel detect on this board because of
7349 * some board problems. The link will not go down
7350 * if we do parallel detect.
7351 */
7352 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7353 pdev->subsystem_device == 0x310c)
7354 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7355 } else {
5b0c76ad 7356 bp->phy_addr = 2;
5b0c76ad 7357 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 7358 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 7359 }
0d8a6571
MC		 7360 bnx2_init_remote_phy(bp);
7361
261dd5ca
MC		 7362 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7363 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 7364 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 7365 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7366 (CHIP_REV(bp) == CHIP_REV_Ax ||
7367 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 7368 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 7369
16088272
MC		 7370 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7371 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
846f5c62 7372 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
f86e82fb 7373 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7374 bp->wol = 0;
7375 }
dda1e390 7376
b6016b76
MC		 7377 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7378 bp->tx_quick_cons_trip_int =
7379 bp->tx_quick_cons_trip;
7380 bp->tx_ticks_int = bp->tx_ticks;
7381 bp->rx_quick_cons_trip_int =
7382 bp->rx_quick_cons_trip;
7383 bp->rx_ticks_int = bp->rx_ticks;
7384 bp->comp_prod_trip_int = bp->comp_prod_trip;
7385 bp->com_ticks_int = bp->com_ticks;
7386 bp->cmd_ticks_int = bp->cmd_ticks;
7387 }
7388
f9317a40
MC		 7389 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7390 *
7391 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7392 * with byte enables disabled on the unused 32-bit word. This is legal
7393 * but causes problems on the AMD 8132 which will eventually stop
7394 * responding after a while.
7395 *
7396 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 7397 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 7398 */
7399 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7400 struct pci_dev *amd_8132 = NULL;
7401
7402 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7403 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7404 amd_8132))) {
f9317a40 7405
44c10138
AK		 7406 if (amd_8132->revision >= 0x10 &&
7407 amd_8132->revision <= 0x13) {
f9317a40
MC		 7408 disable_msi = 1;
7409 pci_dev_put(amd_8132);
7410 break;
7411 }
7412 }
7413 }
7414
deaf391b 7415 bnx2_set_default_link(bp);
b6016b76
MC		 7416 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7417
cd339a0e
MC		 7418 init_timer(&bp->timer);
7419 bp->timer.expires = RUN_AT(bp->timer_interval);
7420 bp->timer.data = (unsigned long) bp;
7421 bp->timer.function = bnx2_timer;
7422
b6016b76
MC		 7423 return 0;
7424
7425err_out_unmap:
7426 if (bp->regview) {
7427 iounmap(bp->regview);
73eef4cd 7428 bp->regview = NULL;
b6016b76
MC		 7429 }
7430
7431err_out_release:
7432 pci_release_regions(pdev);
7433
7434err_out_disable:
7435 pci_disable_device(pdev);
7436 pci_set_drvdata(pdev, NULL);
7437
7438err_out:
7439 return rc;
7440}
7441
883e5151
MC		 7442static char * __devinit
7443bnx2_bus_string(struct bnx2 *bp, char *str)
7444{
7445 char *s = str;
7446
f86e82fb 7447 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 7448 s += sprintf(s, "PCI Express");
7449 } else {
7450 s += sprintf(s, "PCI");
f86e82fb 7451 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 7452 s += sprintf(s, "-X");
f86e82fb 7453 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 7454 s += sprintf(s, " 32-bit");
7455 else
7456 s += sprintf(s, " 64-bit");
7457 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7458 }
7459 return str;
7460}
7461
2ba582b7 7462static void __devinit
35efa7c1
MC		 7463bnx2_init_napi(struct bnx2 *bp)
7464{
b4b36042
MC		 7465 int i;
7466 struct bnx2_napi *bnapi;
35efa7c1 7467
b4b36042
MC		 7468 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7469 bnapi = &bp->bnx2_napi[i];
7470 bnapi->bp = bp;
7471 }
7472 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
57851d84
MC		 7473 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7474 64);
35efa7c1
MC		 7475}
7476
b6016b76
MC		 7477static int __devinit
7478bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7479{
7480 static int version_printed = 0;
7481 struct net_device *dev = NULL;
7482 struct bnx2 *bp;
0795af57 7483 int rc;
883e5151 7484 char str[40];
0795af57 7485 DECLARE_MAC_BUF(mac);
b6016b76
MC		 7486
7487 if (version_printed++ == 0)
7488 printk(KERN_INFO "%s", version);
7489
7490 /* dev zeroed in init_etherdev */
7491 dev = alloc_etherdev(sizeof(*bp));
7492
7493 if (!dev)
7494 return -ENOMEM;
7495
7496 rc = bnx2_init_board(pdev, dev);
7497 if (rc < 0) {
7498 free_netdev(dev);
7499 return rc;
7500 }
7501
7502 dev->open = bnx2_open;
7503 dev->hard_start_xmit = bnx2_start_xmit;
7504 dev->stop = bnx2_close;
7505 dev->get_stats = bnx2_get_stats;
7506 dev->set_multicast_list = bnx2_set_rx_mode;
7507 dev->do_ioctl = bnx2_ioctl;
7508 dev->set_mac_address = bnx2_change_mac_addr;
7509 dev->change_mtu = bnx2_change_mtu;
7510 dev->tx_timeout = bnx2_tx_timeout;
7511 dev->watchdog_timeo = TX_TIMEOUT;
7512#ifdef BCM_VLAN
7513 dev->vlan_rx_register = bnx2_vlan_rx_register;
b6016b76 7514#endif
b6016b76 7515 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 7516
972ec0d4 7517 bp = netdev_priv(dev);
35efa7c1 7518 bnx2_init_napi(bp);
b6016b76
MC		 7519
7520#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7521 dev->poll_controller = poll_bnx2;
7522#endif
7523
1b2f922f
MC		 7524 pci_set_drvdata(pdev, dev);
7525
7526 memcpy(dev->dev_addr, bp->mac_addr, 6);
7527 memcpy(dev->perm_addr, bp->mac_addr, 6);
7528 bp->name = board_info[ent->driver_data].name;
7529
d212f87b 7530 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4666f87a 7531 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d212f87b
SH		 7532 dev->features |= NETIF_F_IPV6_CSUM;
7533
1b2f922f
MC		 7534#ifdef BCM_VLAN
7535 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7536#endif
7537 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7538 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7539 dev->features |= NETIF_F_TSO6;
1b2f922f 7540
b6016b76 7541 if ((rc = register_netdev(dev))) {
9b91cf9d 7542 dev_err(&pdev->dev, "Cannot register net device\n");
b6016b76
MC		 7543 if (bp->regview)
7544 iounmap(bp->regview);
7545 pci_release_regions(pdev);
7546 pci_disable_device(pdev);
7547 pci_set_drvdata(pdev, NULL);
7548 free_netdev(dev);
7549 return rc;
7550 }
7551
883e5151 7552 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
0795af57 7553 "IRQ %d, node addr %s\n",
b6016b76
MC		 7554 dev->name,
7555 bp->name,
7556 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7557 ((CHIP_ID(bp) & 0x0ff0) >> 4),
883e5151 7558 bnx2_bus_string(bp, str),
b6016b76 7559 dev->base_addr,
0795af57 7560 bp->pdev->irq, print_mac(mac, dev->dev_addr));
b6016b76 7561
b6016b76
MC		 7562 return 0;
7563}
7564
7565static void __devexit
7566bnx2_remove_one(struct pci_dev *pdev)
7567{
7568 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7569 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7570
afdc08b9
MC		 7571 flush_scheduled_work();
7572
b6016b76
MC		 7573 unregister_netdev(dev);
7574
7575 if (bp->regview)
7576 iounmap(bp->regview);
7577
7578 free_netdev(dev);
7579 pci_release_regions(pdev);
7580 pci_disable_device(pdev);
7581 pci_set_drvdata(pdev, NULL);
7582}
7583
7584static int
829ca9a3 7585bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 7586{
7587 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7588 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7589 u32 reset_code;
7590
6caebb02
MC		 7591 /* PCI register 4 needs to be saved whether netif_running() or not.
7592 * MSI address and data need to be saved if using MSI and
7593 * netif_running().
7594 */
7595 pci_save_state(pdev);
b6016b76
MC		 7596 if (!netif_running(dev))
7597 return 0;
7598
1d60290f 7599 flush_scheduled_work();
b6016b76
MC		 7600 bnx2_netif_stop(bp);
7601 netif_device_detach(dev);
7602 del_timer_sync(&bp->timer);
f86e82fb 7603 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 7604 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 7605 else if (bp->wol)
b6016b76
MC		 7606 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7607 else
7608 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7609 bnx2_reset_chip(bp, reset_code);
7610 bnx2_free_skbs(bp);
829ca9a3 7611 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 7612 return 0;
7613}
7614
7615static int
7616bnx2_resume(struct pci_dev *pdev)
7617{
7618 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7619 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7620
6caebb02 7621 pci_restore_state(pdev);
b6016b76
MC		 7622 if (!netif_running(dev))
7623 return 0;
7624
829ca9a3 7625 bnx2_set_power_state(bp, PCI_D0);
b6016b76 7626 netif_device_attach(dev);
9a120bc5 7627 bnx2_init_nic(bp, 1);
b6016b76
MC		 7628 bnx2_netif_start(bp);
7629 return 0;
7630}
7631
6ff2da49
WX		 7632/**
7633 * bnx2_io_error_detected - called when PCI error is detected
7634 * @pdev: Pointer to PCI device
7635 * @state: The current pci connection state
7636 *
7637 * This function is called after a PCI bus error affecting
7638 * this device has been detected.
7639 */
7640static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7641 pci_channel_state_t state)
7642{
7643 struct net_device *dev = pci_get_drvdata(pdev);
7644 struct bnx2 *bp = netdev_priv(dev);
7645
7646 rtnl_lock();
7647 netif_device_detach(dev);
7648
7649 if (netif_running(dev)) {
7650 bnx2_netif_stop(bp);
7651 del_timer_sync(&bp->timer);
7652 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7653 }
7654
7655 pci_disable_device(pdev);
7656 rtnl_unlock();
7657
7658 /* Request a slot slot reset. */
7659 return PCI_ERS_RESULT_NEED_RESET;
7660}
7661
7662/**
7663 * bnx2_io_slot_reset - called after the pci bus has been reset.
7664 * @pdev: Pointer to PCI device
7665 *
7666 * Restart the card from scratch, as if from a cold-boot.
7667 */
7668static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7669{
7670 struct net_device *dev = pci_get_drvdata(pdev);
7671 struct bnx2 *bp = netdev_priv(dev);
7672
7673 rtnl_lock();
7674 if (pci_enable_device(pdev)) {
7675 dev_err(&pdev->dev,
7676 "Cannot re-enable PCI device after reset.\n");
7677 rtnl_unlock();
7678 return PCI_ERS_RESULT_DISCONNECT;
7679 }
7680 pci_set_master(pdev);
7681 pci_restore_state(pdev);
7682
7683 if (netif_running(dev)) {
7684 bnx2_set_power_state(bp, PCI_D0);
7685 bnx2_init_nic(bp, 1);
7686 }
7687
7688 rtnl_unlock();
7689 return PCI_ERS_RESULT_RECOVERED;
7690}
7691
7692/**
7693 * bnx2_io_resume - called when traffic can start flowing again.
7694 * @pdev: Pointer to PCI device
7695 *
7696 * This callback is called when the error recovery driver tells us that
7697 * its OK to resume normal operation.
7698 */
7699static void bnx2_io_resume(struct pci_dev *pdev)
7700{
7701 struct net_device *dev = pci_get_drvdata(pdev);
7702 struct bnx2 *bp = netdev_priv(dev);
7703
7704 rtnl_lock();
7705 if (netif_running(dev))
7706 bnx2_netif_start(bp);
7707
7708 netif_device_attach(dev);
7709 rtnl_unlock();
7710}
7711
7712static struct pci_error_handlers bnx2_err_handler = {
7713 .error_detected = bnx2_io_error_detected,
7714 .slot_reset = bnx2_io_slot_reset,
7715 .resume = bnx2_io_resume,
7716};
7717
b6016b76 7718static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 7719 .name = DRV_MODULE_NAME,
7720 .id_table = bnx2_pci_tbl,
7721 .probe = bnx2_init_one,
7722 .remove = __devexit_p(bnx2_remove_one),
7723 .suspend = bnx2_suspend,
7724 .resume = bnx2_resume,
6ff2da49 7725 .err_handler = &bnx2_err_handler,
b6016b76
MC		 7726};
7727
7728static int __init bnx2_init(void)
7729{
29917620 7730 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 7731}
7732
7733static void __exit bnx2_cleanup(void)
7734{
7735 pci_unregister_driver(&bnx2_pci_driver);
7736}
7737
7738module_init(bnx2_init);
7739module_exit(bnx2_cleanup);
7740
7741
7742
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