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cxgb4vf: fix SGE resource resource deallocation bug
[mirror_ubuntu-eoan-kernel.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
bec92044 3 * Copyright (c) 2004-2010 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
17#include <linux/kernel.h>
18#include <linux/timer.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/slab.h>
22#include <linux/vmalloc.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/dma-mapping.h>
1977f032 30#include <linux/bitops.h>
f2a4f052
MC		 31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/delay.h>
34#include <asm/byteorder.h>
c86a31f4 35#include <asm/page.h>
f2a4f052
MC		 36#include <linux/time.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
f2a4f052 39#include <linux/if_vlan.h>
08013fa3 40#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
f2a4f052
MC		 41#define BCM_VLAN 1
42#endif
f2a4f052 43#include <net/ip.h>
de081fa5 44#include <net/tcp.h>
f2a4f052 45#include <net/checksum.h>
f2a4f052
MC		 46#include <linux/workqueue.h>
47#include <linux/crc32.h>
48#include <linux/prefetch.h>
29b12174 49#include <linux/cache.h>
57579f76 50#include <linux/firmware.h>
706bf240 51#include <linux/log2.h>
f2a4f052 52
4edd473f
MC		 53#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54#define BCM_CNIC 1
55#include "cnic_if.h"
56#endif
b6016b76
MC		 57#include "bnx2.h"
58#include "bnx2_fw.h"
b3448b0b 59
b6016b76 60#define DRV_MODULE_NAME "bnx2"
e5a0c1fd
MC		 61#define DRV_MODULE_VERSION "2.0.16"
62#define DRV_MODULE_RELDATE "July 2, 2010"
bec92044 63#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
078b0735 64#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
a931d294 65#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
bec92044
MC		 66#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
67#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
b6016b76
MC		 68
69#define RUN_AT(x) (jiffies + (x))
70
71/* Time in jiffies before concluding the transmitter is hung. */
72#define TX_TIMEOUT (5*HZ)
73
fefa8645 74static char version[] __devinitdata =
b6016b76
MC		 75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 78MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 79MODULE_LICENSE("GPL");
80MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 81MODULE_FIRMWARE(FW_MIPS_FILE_06);
82MODULE_FIRMWARE(FW_RV2P_FILE_06);
83MODULE_FIRMWARE(FW_MIPS_FILE_09);
84MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 85MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 86
87static int disable_msi = 0;
88
89module_param(disable_msi, int, 0);
90MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
5b0c76ad
MC		 98 BCM5708,
99 BCM5708S,
bac0dff6 100 BCM5709,
27a005b8 101 BCM5709S,
7bb0a04f 102 BCM5716,
1caacecb 103 BCM5716S,
b6016b76
MC		 104} board_t;
105
106/* indexed by board_t, above */
fefa8645 107static struct {
b6016b76
MC		 108 char *name;
109} board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 121 };
122
7bb0a04f 123static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 146 { 0, }
147};
148
0ced9d01 149static const struct flash_spec flash_table[] =
b6016b76 150{
e30372c9
MC		 151#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 153 /* Slow EEPROM */
37137709 154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
37137709
MC		 158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
b6016b76
MC		 163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
37137709 165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
37137709 171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
37137709
MC		 175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
b6016b76
MC		 236};
237
0ced9d01 238static const struct flash_spec flash_5709 = {
e30372c9
MC		 239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245};
246
b6016b76
MC		 247MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
4327ba43 249static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 250static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 251
35e9010b 252static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 253{
2f8af120 254 u32 diff;
e89bbf10 255
2f8af120 256 smp_mb();
faac9c4b
MC		 257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
35e9010b 261 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
e89bbf10
MC		 267 return (bp->tx_ring_size - diff);
268}
269
b6016b76
MC		 270static u32
271bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272{
1b8227c4
MC		 273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
b6016b76 276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
b6016b76
MC		 280}
281
282static void
283bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284{
1b8227c4 285 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 288 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 289}
290
2726d6e1
MC		 291static void
292bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293{
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295}
296
297static u32
298bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299{
300 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
301}
302
b6016b76
MC		 303static void
304bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305{
306 offset += cid_addr;
1b8227c4 307 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
59b47d8a
MC		 315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
1b8227c4 324 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 325}
326
4edd473f
MC		 327#ifdef BCM_CNIC
328static int
329bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330{
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348}
349
350static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351{
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375}
376
377static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379{
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
389 bp->cnic_data = data;
390 rcu_assign_pointer(bp->cnic_ops, ops);
391
392 cp->num_irq = 0;
393 cp->drv_state = CNIC_DRV_STATE_REGD;
394
395 bnx2_setup_cnic_irq_info(bp);
396
397 return 0;
398}
399
400static int bnx2_unregister_cnic(struct net_device *dev)
401{
402 struct bnx2 *bp = netdev_priv(dev);
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
405
c5a88950 406 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 407 cp->drv_state = 0;
408 bnapi->cnic_present = 0;
409 rcu_assign_pointer(bp->cnic_ops, NULL);
c5a88950 410 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 411 synchronize_rcu();
412 return 0;
413}
414
415struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
416{
417 struct bnx2 *bp = netdev_priv(dev);
418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
419
420 cp->drv_owner = THIS_MODULE;
421 cp->chip_id = bp->chip_id;
422 cp->pdev = bp->pdev;
423 cp->io_base = bp->regview;
424 cp->drv_ctl = bnx2_drv_ctl;
425 cp->drv_register_cnic = bnx2_register_cnic;
426 cp->drv_unregister_cnic = bnx2_unregister_cnic;
427
428 return cp;
429}
430EXPORT_SYMBOL(bnx2_cnic_probe);
431
432static void
433bnx2_cnic_stop(struct bnx2 *bp)
434{
435 struct cnic_ops *c_ops;
436 struct cnic_ctl_info info;
437
c5a88950
MC		 438 mutex_lock(&bp->cnic_lock);
439 c_ops = bp->cnic_ops;
4edd473f
MC		 440 if (c_ops) {
441 info.cmd = CNIC_CTL_STOP_CMD;
442 c_ops->cnic_ctl(bp->cnic_data, &info);
443 }
c5a88950 444 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 445}
446
447static void
448bnx2_cnic_start(struct bnx2 *bp)
449{
450 struct cnic_ops *c_ops;
451 struct cnic_ctl_info info;
452
c5a88950
MC		 453 mutex_lock(&bp->cnic_lock);
454 c_ops = bp->cnic_ops;
4edd473f
MC		 455 if (c_ops) {
456 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
457 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
458
459 bnapi->cnic_tag = bnapi->last_status_idx;
460 }
461 info.cmd = CNIC_CTL_START_CMD;
462 c_ops->cnic_ctl(bp->cnic_data, &info);
463 }
c5a88950 464 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 465}
466
467#else
468
469static void
470bnx2_cnic_stop(struct bnx2 *bp)
471{
472}
473
474static void
475bnx2_cnic_start(struct bnx2 *bp)
476{
477}
478
479#endif
480
b6016b76
MC		 481static int
482bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
483{
484 u32 val1;
485 int i, ret;
486
583c28e5 487 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 488 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
489 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
490
491 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
492 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
493
494 udelay(40);
495 }
496
497 val1 = (bp->phy_addr << 21) | (reg << 16) |
498 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
499 BNX2_EMAC_MDIO_COMM_START_BUSY;
500 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
501
502 for (i = 0; i < 50; i++) {
503 udelay(10);
504
505 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
506 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
507 udelay(5);
508
509 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
510 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
511
512 break;
513 }
514 }
515
516 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
517 *val = 0x0;
518 ret = -EBUSY;
519 }
520 else {
521 *val = val1;
522 ret = 0;
523 }
524
583c28e5 525 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 526 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
527 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
528
529 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
530 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
531
532 udelay(40);
533 }
534
535 return ret;
536}
537
538static int
539bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
540{
541 u32 val1;
542 int i, ret;
543
583c28e5 544 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 545 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
546 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
547
548 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
549 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
550
551 udelay(40);
552 }
553
554 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
555 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
556 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
557 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 558
b6016b76
MC		 559 for (i = 0; i < 50; i++) {
560 udelay(10);
561
562 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
563 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
564 udelay(5);
565 break;
566 }
567 }
568
569 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
570 ret = -EBUSY;
571 else
572 ret = 0;
573
583c28e5 574 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 575 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
576 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
577
578 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
579 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
580
581 udelay(40);
582 }
583
584 return ret;
585}
586
587static void
588bnx2_disable_int(struct bnx2 *bp)
589{
b4b36042
MC		 590 int i;
591 struct bnx2_napi *bnapi;
592
593 for (i = 0; i < bp->irq_nvecs; i++) {
594 bnapi = &bp->bnx2_napi[i];
595 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
596 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
597 }
b6016b76
MC		 598 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
599}
600
601static void
602bnx2_enable_int(struct bnx2 *bp)
603{
b4b36042
MC		 604 int i;
605 struct bnx2_napi *bnapi;
35efa7c1 606
b4b36042
MC		 607 for (i = 0; i < bp->irq_nvecs; i++) {
608 bnapi = &bp->bnx2_napi[i];
1269a8a6 609
b4b36042
MC		 610 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
611 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
612 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
613 bnapi->last_status_idx);
b6016b76 614
b4b36042
MC		 615 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
617 bnapi->last_status_idx);
618 }
bf5295bb 619 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 620}
621
622static void
623bnx2_disable_int_sync(struct bnx2 *bp)
624{
b4b36042
MC		 625 int i;
626
b6016b76 627 atomic_inc(&bp->intr_sem);
3767546c
MC		 628 if (!netif_running(bp->dev))
629 return;
630
b6016b76 631 bnx2_disable_int(bp);
b4b36042
MC		 632 for (i = 0; i < bp->irq_nvecs; i++)
633 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 634}
635
35efa7c1
MC		 636static void
637bnx2_napi_disable(struct bnx2 *bp)
638{
b4b36042
MC		 639 int i;
640
641 for (i = 0; i < bp->irq_nvecs; i++)
642 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 643}
644
645static void
646bnx2_napi_enable(struct bnx2 *bp)
647{
b4b36042
MC		 648 int i;
649
650 for (i = 0; i < bp->irq_nvecs; i++)
651 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 652}
653
b6016b76 654static void
212f9934 655bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 656{
212f9934
MC		 657 if (stop_cnic)
658 bnx2_cnic_stop(bp);
b6016b76 659 if (netif_running(bp->dev)) {
35efa7c1 660 bnx2_napi_disable(bp);
b6016b76 661 netif_tx_disable(bp->dev);
b6016b76 662 }
b7466560 663 bnx2_disable_int_sync(bp);
a0ba6760 664 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 665}
666
667static void
212f9934 668bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 669{
670 if (atomic_dec_and_test(&bp->intr_sem)) {
671 if (netif_running(bp->dev)) {
706bf240 672 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 673 spin_lock_bh(&bp->phy_lock);
674 if (bp->link_up)
675 netif_carrier_on(bp->dev);
676 spin_unlock_bh(&bp->phy_lock);
35efa7c1 677 bnx2_napi_enable(bp);
b6016b76 678 bnx2_enable_int(bp);
212f9934
MC		 679 if (start_cnic)
680 bnx2_cnic_start(bp);
b6016b76
MC		 681 }
682 }
683}
684
35e9010b
MC		 685static void
686bnx2_free_tx_mem(struct bnx2 *bp)
687{
688 int i;
689
690 for (i = 0; i < bp->num_tx_rings; i++) {
691 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
692 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
693
694 if (txr->tx_desc_ring) {
695 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
696 txr->tx_desc_ring,
697 txr->tx_desc_mapping);
698 txr->tx_desc_ring = NULL;
699 }
700 kfree(txr->tx_buf_ring);
701 txr->tx_buf_ring = NULL;
702 }
703}
704
bb4f98ab
MC		 705static void
706bnx2_free_rx_mem(struct bnx2 *bp)
707{
708 int i;
709
710 for (i = 0; i < bp->num_rx_rings; i++) {
711 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
712 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
713 int j;
714
715 for (j = 0; j < bp->rx_max_ring; j++) {
716 if (rxr->rx_desc_ring[j])
717 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
718 rxr->rx_desc_ring[j],
719 rxr->rx_desc_mapping[j]);
720 rxr->rx_desc_ring[j] = NULL;
721 }
25b0b999 722 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 723 rxr->rx_buf_ring = NULL;
724
725 for (j = 0; j < bp->rx_max_pg_ring; j++) {
726 if (rxr->rx_pg_desc_ring[j])
727 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
3298a738
MC		 728 rxr->rx_pg_desc_ring[j],
729 rxr->rx_pg_desc_mapping[j]);
730 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 731 }
25b0b999 732 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 733 rxr->rx_pg_ring = NULL;
734 }
735}
736
35e9010b
MC		 737static int
738bnx2_alloc_tx_mem(struct bnx2 *bp)
739{
740 int i;
741
742 for (i = 0; i < bp->num_tx_rings; i++) {
743 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
744 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
745
746 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
747 if (txr->tx_buf_ring == NULL)
748 return -ENOMEM;
749
750 txr->tx_desc_ring =
751 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
752 &txr->tx_desc_mapping);
753 if (txr->tx_desc_ring == NULL)
754 return -ENOMEM;
755 }
756 return 0;
757}
758
bb4f98ab
MC		 759static int
760bnx2_alloc_rx_mem(struct bnx2 *bp)
761{
762 int i;
763
764 for (i = 0; i < bp->num_rx_rings; i++) {
765 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
766 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
767 int j;
768
769 rxr->rx_buf_ring =
770 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
771 if (rxr->rx_buf_ring == NULL)
772 return -ENOMEM;
773
774 memset(rxr->rx_buf_ring, 0,
775 SW_RXBD_RING_SIZE * bp->rx_max_ring);
776
777 for (j = 0; j < bp->rx_max_ring; j++) {
778 rxr->rx_desc_ring[j] =
779 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
780 &rxr->rx_desc_mapping[j]);
781 if (rxr->rx_desc_ring[j] == NULL)
782 return -ENOMEM;
783
784 }
785
786 if (bp->rx_pg_ring_size) {
787 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
788 bp->rx_max_pg_ring);
789 if (rxr->rx_pg_ring == NULL)
790 return -ENOMEM;
791
792 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
793 bp->rx_max_pg_ring);
794 }
795
796 for (j = 0; j < bp->rx_max_pg_ring; j++) {
797 rxr->rx_pg_desc_ring[j] =
798 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
799 &rxr->rx_pg_desc_mapping[j]);
800 if (rxr->rx_pg_desc_ring[j] == NULL)
801 return -ENOMEM;
802
803 }
804 }
805 return 0;
806}
807
b6016b76
MC		 808static void
809bnx2_free_mem(struct bnx2 *bp)
810{
13daffa2 811 int i;
43e80b89 812 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 813
35e9010b 814 bnx2_free_tx_mem(bp);
bb4f98ab 815 bnx2_free_rx_mem(bp);
35e9010b 816
59b47d8a
MC		 817 for (i = 0; i < bp->ctx_pages; i++) {
818 if (bp->ctx_blk[i]) {
819 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
820 bp->ctx_blk[i],
821 bp->ctx_blk_mapping[i]);
822 bp->ctx_blk[i] = NULL;
823 }
824 }
43e80b89 825 if (bnapi->status_blk.msi) {
0f31f994 826 pci_free_consistent(bp->pdev, bp->status_stats_size,
43e80b89
MC		 827 bnapi->status_blk.msi,
828 bp->status_blk_mapping);
829 bnapi->status_blk.msi = NULL;
0f31f994 830 bp->stats_blk = NULL;
b6016b76 831 }
b6016b76
MC		 832}
833
834static int
835bnx2_alloc_mem(struct bnx2 *bp)
836{
35e9010b 837 int i, status_blk_size, err;
43e80b89
MC		 838 struct bnx2_napi *bnapi;
839 void *status_blk;
b6016b76 840
0f31f994
MC		 841 /* Combine status and statistics blocks into one allocation. */
842 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 843 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 844 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
845 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 846 bp->status_stats_size = status_blk_size +
847 sizeof(struct statistics_block);
848
43e80b89
MC		 849 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
850 &bp->status_blk_mapping);
851 if (status_blk == NULL)
b6016b76
MC		 852 goto alloc_mem_err;
853
43e80b89 854 memset(status_blk, 0, bp->status_stats_size);
b6016b76 855
43e80b89
MC		 856 bnapi = &bp->bnx2_napi[0];
857 bnapi->status_blk.msi = status_blk;
858 bnapi->hw_tx_cons_ptr =
859 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
860 bnapi->hw_rx_cons_ptr =
861 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 862 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042 863 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
43e80b89
MC		 864 struct status_block_msix *sblk;
865
866 bnapi = &bp->bnx2_napi[i];
b4b36042 867
43e80b89
MC		 868 sblk = (void *) (status_blk +
869 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
870 bnapi->status_blk.msix = sblk;
871 bnapi->hw_tx_cons_ptr =
872 &sblk->status_tx_quick_consumer_index;
873 bnapi->hw_rx_cons_ptr =
874 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 875 bnapi->int_num = i << 24;
876 }
877 }
35efa7c1 878
43e80b89 879 bp->stats_blk = status_blk + status_blk_size;
b6016b76 880
0f31f994 881 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 882
59b47d8a
MC		 883 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
884 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
885 if (bp->ctx_pages == 0)
886 bp->ctx_pages = 1;
887 for (i = 0; i < bp->ctx_pages; i++) {
888 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
889 BCM_PAGE_SIZE,
890 &bp->ctx_blk_mapping[i]);
891 if (bp->ctx_blk[i] == NULL)
892 goto alloc_mem_err;
893 }
894 }
35e9010b 895
bb4f98ab
MC		 896 err = bnx2_alloc_rx_mem(bp);
897 if (err)
898 goto alloc_mem_err;
899
35e9010b
MC		 900 err = bnx2_alloc_tx_mem(bp);
901 if (err)
902 goto alloc_mem_err;
903
b6016b76
MC		 904 return 0;
905
906alloc_mem_err:
907 bnx2_free_mem(bp);
908 return -ENOMEM;
909}
910
e3648b3d
MC		 911static void
912bnx2_report_fw_link(struct bnx2 *bp)
913{
914 u32 fw_link_status = 0;
915
583c28e5 916 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 917 return;
918
e3648b3d
MC		 919 if (bp->link_up) {
920 u32 bmsr;
921
922 switch (bp->line_speed) {
923 case SPEED_10:
924 if (bp->duplex == DUPLEX_HALF)
925 fw_link_status = BNX2_LINK_STATUS_10HALF;
926 else
927 fw_link_status = BNX2_LINK_STATUS_10FULL;
928 break;
929 case SPEED_100:
930 if (bp->duplex == DUPLEX_HALF)
931 fw_link_status = BNX2_LINK_STATUS_100HALF;
932 else
933 fw_link_status = BNX2_LINK_STATUS_100FULL;
934 break;
935 case SPEED_1000:
936 if (bp->duplex == DUPLEX_HALF)
937 fw_link_status = BNX2_LINK_STATUS_1000HALF;
938 else
939 fw_link_status = BNX2_LINK_STATUS_1000FULL;
940 break;
941 case SPEED_2500:
942 if (bp->duplex == DUPLEX_HALF)
943 fw_link_status = BNX2_LINK_STATUS_2500HALF;
944 else
945 fw_link_status = BNX2_LINK_STATUS_2500FULL;
946 break;
947 }
948
949 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
950
951 if (bp->autoneg) {
952 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
953
ca58c3af
MC		 954 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
955 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 956
957 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 958 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 959 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
960 else
961 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
962 }
963 }
964 else
965 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
966
2726d6e1 967 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 968}
969
9b1084b8
MC		 970static char *
971bnx2_xceiver_str(struct bnx2 *bp)
972{
973 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 974 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 975 "Copper"));
976}
977
b6016b76
MC		 978static void
979bnx2_report_link(struct bnx2 *bp)
980{
981 if (bp->link_up) {
982 netif_carrier_on(bp->dev);
3a9c6a49
JP		 983 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
984 bnx2_xceiver_str(bp),
985 bp->line_speed,
986 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 987
988 if (bp->flow_ctrl) {
989 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 990 pr_cont(", receive ");
b6016b76 991 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 992 pr_cont("& transmit ");
b6016b76
MC		 993 }
994 else {
3a9c6a49 995 pr_cont(", transmit ");
b6016b76 996 }
3a9c6a49 997 pr_cont("flow control ON");
b6016b76 998 }
3a9c6a49
JP		 999 pr_cont("\n");
1000 } else {
b6016b76 1001 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1002 netdev_err(bp->dev, "NIC %s Link is Down\n",
1003 bnx2_xceiver_str(bp));
b6016b76 1004 }
e3648b3d
MC		 1005
1006 bnx2_report_fw_link(bp);
b6016b76
MC		 1007}
1008
1009static void
1010bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1011{
1012 u32 local_adv, remote_adv;
1013
1014 bp->flow_ctrl = 0;
6aa20a22 1015 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1016 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1017
1018 if (bp->duplex == DUPLEX_FULL) {
1019 bp->flow_ctrl = bp->req_flow_ctrl;
1020 }
1021 return;
1022 }
1023
1024 if (bp->duplex != DUPLEX_FULL) {
1025 return;
1026 }
1027
583c28e5 1028 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 1029 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1030 u32 val;
1031
1032 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1033 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1034 bp->flow_ctrl |= FLOW_CTRL_TX;
1035 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1036 bp->flow_ctrl |= FLOW_CTRL_RX;
1037 return;
1038 }
1039
ca58c3af
MC		 1040 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1041 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1042
583c28e5 1043 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1044 u32 new_local_adv = 0;
1045 u32 new_remote_adv = 0;
1046
1047 if (local_adv & ADVERTISE_1000XPAUSE)
1048 new_local_adv |= ADVERTISE_PAUSE_CAP;
1049 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1050 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1051 if (remote_adv & ADVERTISE_1000XPAUSE)
1052 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1053 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1054 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1055
1056 local_adv = new_local_adv;
1057 remote_adv = new_remote_adv;
1058 }
1059
1060 /* See Table 28B-3 of 802.3ab-1999 spec. */
1061 if (local_adv & ADVERTISE_PAUSE_CAP) {
1062 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1063 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1064 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1065 }
1066 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1067 bp->flow_ctrl = FLOW_CTRL_RX;
1068 }
1069 }
1070 else {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 }
1075 }
1076 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1077 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1078 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1079
1080 bp->flow_ctrl = FLOW_CTRL_TX;
1081 }
1082 }
1083}
1084
27a005b8
MC		 1085static int
1086bnx2_5709s_linkup(struct bnx2 *bp)
1087{
1088 u32 val, speed;
1089
1090 bp->link_up = 1;
1091
1092 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1093 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1094 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1095
1096 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1097 bp->line_speed = bp->req_line_speed;
1098 bp->duplex = bp->req_duplex;
1099 return 0;
1100 }
1101 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1102 switch (speed) {
1103 case MII_BNX2_GP_TOP_AN_SPEED_10:
1104 bp->line_speed = SPEED_10;
1105 break;
1106 case MII_BNX2_GP_TOP_AN_SPEED_100:
1107 bp->line_speed = SPEED_100;
1108 break;
1109 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1110 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1111 bp->line_speed = SPEED_1000;
1112 break;
1113 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1114 bp->line_speed = SPEED_2500;
1115 break;
1116 }
1117 if (val & MII_BNX2_GP_TOP_AN_FD)
1118 bp->duplex = DUPLEX_FULL;
1119 else
1120 bp->duplex = DUPLEX_HALF;
1121 return 0;
1122}
1123
b6016b76 1124static int
5b0c76ad
MC		 1125bnx2_5708s_linkup(struct bnx2 *bp)
1126{
1127 u32 val;
1128
1129 bp->link_up = 1;
1130 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1131 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1132 case BCM5708S_1000X_STAT1_SPEED_10:
1133 bp->line_speed = SPEED_10;
1134 break;
1135 case BCM5708S_1000X_STAT1_SPEED_100:
1136 bp->line_speed = SPEED_100;
1137 break;
1138 case BCM5708S_1000X_STAT1_SPEED_1G:
1139 bp->line_speed = SPEED_1000;
1140 break;
1141 case BCM5708S_1000X_STAT1_SPEED_2G5:
1142 bp->line_speed = SPEED_2500;
1143 break;
1144 }
1145 if (val & BCM5708S_1000X_STAT1_FD)
1146 bp->duplex = DUPLEX_FULL;
1147 else
1148 bp->duplex = DUPLEX_HALF;
1149
1150 return 0;
1151}
1152
1153static int
1154bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1155{
1156 u32 bmcr, local_adv, remote_adv, common;
1157
1158 bp->link_up = 1;
1159 bp->line_speed = SPEED_1000;
1160
ca58c3af 1161 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1162 if (bmcr & BMCR_FULLDPLX) {
1163 bp->duplex = DUPLEX_FULL;
1164 }
1165 else {
1166 bp->duplex = DUPLEX_HALF;
1167 }
1168
1169 if (!(bmcr & BMCR_ANENABLE)) {
1170 return 0;
1171 }
1172
ca58c3af
MC		 1173 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1174 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1175
1176 common = local_adv & remote_adv;
1177 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1178
1179 if (common & ADVERTISE_1000XFULL) {
1180 bp->duplex = DUPLEX_FULL;
1181 }
1182 else {
1183 bp->duplex = DUPLEX_HALF;
1184 }
1185 }
1186
1187 return 0;
1188}
1189
1190static int
1191bnx2_copper_linkup(struct bnx2 *bp)
1192{
1193 u32 bmcr;
1194
ca58c3af 1195 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1196 if (bmcr & BMCR_ANENABLE) {
1197 u32 local_adv, remote_adv, common;
1198
1199 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1200 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1201
1202 common = local_adv & (remote_adv >> 2);
1203 if (common & ADVERTISE_1000FULL) {
1204 bp->line_speed = SPEED_1000;
1205 bp->duplex = DUPLEX_FULL;
1206 }
1207 else if (common & ADVERTISE_1000HALF) {
1208 bp->line_speed = SPEED_1000;
1209 bp->duplex = DUPLEX_HALF;
1210 }
1211 else {
ca58c3af
MC		 1212 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1213 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1214
1215 common = local_adv & remote_adv;
1216 if (common & ADVERTISE_100FULL) {
1217 bp->line_speed = SPEED_100;
1218 bp->duplex = DUPLEX_FULL;
1219 }
1220 else if (common & ADVERTISE_100HALF) {
1221 bp->line_speed = SPEED_100;
1222 bp->duplex = DUPLEX_HALF;
1223 }
1224 else if (common & ADVERTISE_10FULL) {
1225 bp->line_speed = SPEED_10;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_10HALF) {
1229 bp->line_speed = SPEED_10;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else {
1233 bp->line_speed = 0;
1234 bp->link_up = 0;
1235 }
1236 }
1237 }
1238 else {
1239 if (bmcr & BMCR_SPEED100) {
1240 bp->line_speed = SPEED_100;
1241 }
1242 else {
1243 bp->line_speed = SPEED_10;
1244 }
1245 if (bmcr & BMCR_FULLDPLX) {
1246 bp->duplex = DUPLEX_FULL;
1247 }
1248 else {
1249 bp->duplex = DUPLEX_HALF;
1250 }
1251 }
1252
1253 return 0;
1254}
1255
83e3fc89 1256static void
bb4f98ab 1257bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1258{
bb4f98ab 1259 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1260
1261 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1262 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1263 val |= 0x02 << 8;
1264
1265 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1266 u32 lo_water, hi_water;
1267
1268 if (bp->flow_ctrl & FLOW_CTRL_TX)
1269 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1270 else
1271 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1272 if (lo_water >= bp->rx_ring_size)
1273 lo_water = 0;
1274
5726026b 1275 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
83e3fc89
MC		 1276
1277 if (hi_water <= lo_water)
1278 lo_water = 0;
1279
1280 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1281 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1282
1283 if (hi_water > 0xf)
1284 hi_water = 0xf;
1285 else if (hi_water == 0)
1286 lo_water = 0;
1287 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1288 }
1289 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1290}
1291
bb4f98ab
MC		 1292static void
1293bnx2_init_all_rx_contexts(struct bnx2 *bp)
1294{
1295 int i;
1296 u32 cid;
1297
1298 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1299 if (i == 1)
1300 cid = RX_RSS_CID;
1301 bnx2_init_rx_context(bp, cid);
1302 }
1303}
1304
344478db 1305static void
b6016b76
MC		 1306bnx2_set_mac_link(struct bnx2 *bp)
1307{
1308 u32 val;
1309
1310 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1311 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1312 (bp->duplex == DUPLEX_HALF)) {
1313 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1314 }
1315
1316 /* Configure the EMAC mode register. */
1317 val = REG_RD(bp, BNX2_EMAC_MODE);
1318
1319 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1320 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1321 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1322
1323 if (bp->link_up) {
5b0c76ad
MC		 1324 switch (bp->line_speed) {
1325 case SPEED_10:
59b47d8a
MC		 1326 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1327 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1328 break;
1329 }
1330 /* fall through */
1331 case SPEED_100:
1332 val |= BNX2_EMAC_MODE_PORT_MII;
1333 break;
1334 case SPEED_2500:
59b47d8a 1335 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1336 /* fall through */
1337 case SPEED_1000:
1338 val |= BNX2_EMAC_MODE_PORT_GMII;
1339 break;
1340 }
b6016b76
MC		 1341 }
1342 else {
1343 val |= BNX2_EMAC_MODE_PORT_GMII;
1344 }
1345
1346 /* Set the MAC to operate in the appropriate duplex mode. */
1347 if (bp->duplex == DUPLEX_HALF)
1348 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1349 REG_WR(bp, BNX2_EMAC_MODE, val);
1350
1351 /* Enable/disable rx PAUSE. */
1352 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1353
1354 if (bp->flow_ctrl & FLOW_CTRL_RX)
1355 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1356 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1357
1358 /* Enable/disable tx PAUSE. */
1359 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1360 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1361
1362 if (bp->flow_ctrl & FLOW_CTRL_TX)
1363 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1364 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1365
1366 /* Acknowledge the interrupt. */
1367 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1368
83e3fc89 1369 if (CHIP_NUM(bp) == CHIP_NUM_5709)
bb4f98ab 1370 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1371}
1372
27a005b8
MC		 1373static void
1374bnx2_enable_bmsr1(struct bnx2 *bp)
1375{
583c28e5 1376 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1377 (CHIP_NUM(bp) == CHIP_NUM_5709))
1378 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1379 MII_BNX2_BLK_ADDR_GP_STATUS);
1380}
1381
1382static void
1383bnx2_disable_bmsr1(struct bnx2 *bp)
1384{
583c28e5 1385 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1386 (CHIP_NUM(bp) == CHIP_NUM_5709))
1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1388 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1389}
1390
605a9e20
MC		 1391static int
1392bnx2_test_and_enable_2g5(struct bnx2 *bp)
1393{
1394 u32 up1;
1395 int ret = 1;
1396
583c28e5 1397 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1398 return 0;
1399
1400 if (bp->autoneg & AUTONEG_SPEED)
1401 bp->advertising |= ADVERTISED_2500baseX_Full;
1402
27a005b8
MC		 1403 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1404 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1405
605a9e20
MC		 1406 bnx2_read_phy(bp, bp->mii_up1, &up1);
1407 if (!(up1 & BCM5708S_UP1_2G5)) {
1408 up1 |= BCM5708S_UP1_2G5;
1409 bnx2_write_phy(bp, bp->mii_up1, up1);
1410 ret = 0;
1411 }
1412
27a005b8
MC		 1413 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1414 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1415 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1416
605a9e20
MC		 1417 return ret;
1418}
1419
1420static int
1421bnx2_test_and_disable_2g5(struct bnx2 *bp)
1422{
1423 u32 up1;
1424 int ret = 0;
1425
583c28e5 1426 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1427 return 0;
1428
27a005b8
MC		 1429 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1430 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1431
605a9e20
MC		 1432 bnx2_read_phy(bp, bp->mii_up1, &up1);
1433 if (up1 & BCM5708S_UP1_2G5) {
1434 up1 &= ~BCM5708S_UP1_2G5;
1435 bnx2_write_phy(bp, bp->mii_up1, up1);
1436 ret = 1;
1437 }
1438
27a005b8
MC		 1439 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1440 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1441 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1442
605a9e20
MC		 1443 return ret;
1444}
1445
1446static void
1447bnx2_enable_forced_2g5(struct bnx2 *bp)
1448{
cbd6890c
MC		 1449 u32 uninitialized_var(bmcr);
1450 int err;
605a9e20 1451
583c28e5 1452 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1453 return;
1454
27a005b8
MC		 1455 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1456 u32 val;
1457
1458 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1459 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1460 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1461 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1462 val |= MII_BNX2_SD_MISC1_FORCE |
1463 MII_BNX2_SD_MISC1_FORCE_2_5G;
1464 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1465 }
27a005b8
MC		 1466
1467 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1468 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1469 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1470
1471 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1472 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1473 if (!err)
1474 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1475 } else {
1476 return;
605a9e20
MC		 1477 }
1478
cbd6890c
MC		 1479 if (err)
1480 return;
1481
605a9e20
MC		 1482 if (bp->autoneg & AUTONEG_SPEED) {
1483 bmcr &= ~BMCR_ANENABLE;
1484 if (bp->req_duplex == DUPLEX_FULL)
1485 bmcr |= BMCR_FULLDPLX;
1486 }
1487 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1488}
1489
1490static void
1491bnx2_disable_forced_2g5(struct bnx2 *bp)
1492{
cbd6890c
MC		 1493 u32 uninitialized_var(bmcr);
1494 int err;
605a9e20 1495
583c28e5 1496 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1497 return;
1498
27a005b8
MC		 1499 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1500 u32 val;
1501
1502 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1503 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1504 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1505 val &= ~MII_BNX2_SD_MISC1_FORCE;
1506 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1507 }
27a005b8
MC		 1508
1509 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1510 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1511 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1512
1513 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1514 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1515 if (!err)
1516 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1517 } else {
1518 return;
605a9e20
MC		 1519 }
1520
cbd6890c
MC		 1521 if (err)
1522 return;
1523
605a9e20
MC		 1524 if (bp->autoneg & AUTONEG_SPEED)
1525 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1526 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1527}
1528
b2fadeae
MC		 1529static void
1530bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1531{
1532 u32 val;
1533
1534 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1535 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1536 if (start)
1537 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1538 else
1539 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1540}
1541
b6016b76
MC		 1542static int
1543bnx2_set_link(struct bnx2 *bp)
1544{
1545 u32 bmsr;
1546 u8 link_up;
1547
80be4434 1548 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1549 bp->link_up = 1;
1550 return 0;
1551 }
1552
583c28e5 1553 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1554 return 0;
1555
b6016b76
MC		 1556 link_up = bp->link_up;
1557
27a005b8
MC		 1558 bnx2_enable_bmsr1(bp);
1559 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1560 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1561 bnx2_disable_bmsr1(bp);
b6016b76 1562
583c28e5 1563 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1564 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1565 u32 val, an_dbg;
b6016b76 1566
583c28e5 1567 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1568 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1569 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1570 }
b6016b76 1571 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1572
1573 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1574 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1575 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1576
1577 if ((val & BNX2_EMAC_STATUS_LINK) &&
1578 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1579 bmsr |= BMSR_LSTATUS;
1580 else
1581 bmsr &= ~BMSR_LSTATUS;
1582 }
1583
1584 if (bmsr & BMSR_LSTATUS) {
1585 bp->link_up = 1;
1586
583c28e5 1587 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1588 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1589 bnx2_5706s_linkup(bp);
1590 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1591 bnx2_5708s_linkup(bp);
27a005b8
MC		 1592 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1593 bnx2_5709s_linkup(bp);
b6016b76
MC		 1594 }
1595 else {
1596 bnx2_copper_linkup(bp);
1597 }
1598 bnx2_resolve_flow_ctrl(bp);
1599 }
1600 else {
583c28e5 1601 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1602 (bp->autoneg & AUTONEG_SPEED))
1603 bnx2_disable_forced_2g5(bp);
b6016b76 1604
583c28e5 1605 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1606 u32 bmcr;
1607
1608 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1609 bmcr |= BMCR_ANENABLE;
1610 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1611
583c28e5 1612 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1613 }
b6016b76
MC		 1614 bp->link_up = 0;
1615 }
1616
1617 if (bp->link_up != link_up) {
1618 bnx2_report_link(bp);
1619 }
1620
1621 bnx2_set_mac_link(bp);
1622
1623 return 0;
1624}
1625
1626static int
1627bnx2_reset_phy(struct bnx2 *bp)
1628{
1629 int i;
1630 u32 reg;
1631
ca58c3af 1632 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1633
1634#define PHY_RESET_MAX_WAIT 100
1635 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1636 udelay(10);
1637
ca58c3af 1638 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1639 if (!(reg & BMCR_RESET)) {
1640 udelay(20);
1641 break;
1642 }
1643 }
1644 if (i == PHY_RESET_MAX_WAIT) {
1645 return -EBUSY;
1646 }
1647 return 0;
1648}
1649
1650static u32
1651bnx2_phy_get_pause_adv(struct bnx2 *bp)
1652{
1653 u32 adv = 0;
1654
1655 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1656 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1657
583c28e5 1658 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1659 adv = ADVERTISE_1000XPAUSE;
1660 }
1661 else {
1662 adv = ADVERTISE_PAUSE_CAP;
1663 }
1664 }
1665 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1666 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1667 adv = ADVERTISE_1000XPSE_ASYM;
1668 }
1669 else {
1670 adv = ADVERTISE_PAUSE_ASYM;
1671 }
1672 }
1673 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1674 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1675 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1676 }
1677 else {
1678 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1679 }
1680 }
1681 return adv;
1682}
1683
a2f13890 1684static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1685
b6016b76 1686static int
0d8a6571 1687bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1688__releases(&bp->phy_lock)
1689__acquires(&bp->phy_lock)
0d8a6571
MC		 1690{
1691 u32 speed_arg = 0, pause_adv;
1692
1693 pause_adv = bnx2_phy_get_pause_adv(bp);
1694
1695 if (bp->autoneg & AUTONEG_SPEED) {
1696 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1697 if (bp->advertising & ADVERTISED_10baseT_Half)
1698 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1699 if (bp->advertising & ADVERTISED_10baseT_Full)
1700 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1701 if (bp->advertising & ADVERTISED_100baseT_Half)
1702 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1703 if (bp->advertising & ADVERTISED_100baseT_Full)
1704 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1705 if (bp->advertising & ADVERTISED_1000baseT_Full)
1706 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1707 if (bp->advertising & ADVERTISED_2500baseX_Full)
1708 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1709 } else {
1710 if (bp->req_line_speed == SPEED_2500)
1711 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1712 else if (bp->req_line_speed == SPEED_1000)
1713 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1714 else if (bp->req_line_speed == SPEED_100) {
1715 if (bp->req_duplex == DUPLEX_FULL)
1716 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1717 else
1718 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1719 } else if (bp->req_line_speed == SPEED_10) {
1720 if (bp->req_duplex == DUPLEX_FULL)
1721 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1722 else
1723 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1724 }
1725 }
1726
1727 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1728 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1729 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1730 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1731
1732 if (port == PORT_TP)
1733 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1734 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1735
2726d6e1 1736 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1737
1738 spin_unlock_bh(&bp->phy_lock);
a2f13890 1739 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1740 spin_lock_bh(&bp->phy_lock);
1741
1742 return 0;
1743}
1744
1745static int
1746bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1747__releases(&bp->phy_lock)
1748__acquires(&bp->phy_lock)
b6016b76 1749{
605a9e20 1750 u32 adv, bmcr;
b6016b76
MC		 1751 u32 new_adv = 0;
1752
583c28e5 1753 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1754 return (bnx2_setup_remote_phy(bp, port));
1755
b6016b76
MC		 1756 if (!(bp->autoneg & AUTONEG_SPEED)) {
1757 u32 new_bmcr;
5b0c76ad
MC		 1758 int force_link_down = 0;
1759
605a9e20
MC		 1760 if (bp->req_line_speed == SPEED_2500) {
1761 if (!bnx2_test_and_enable_2g5(bp))
1762 force_link_down = 1;
1763 } else if (bp->req_line_speed == SPEED_1000) {
1764 if (bnx2_test_and_disable_2g5(bp))
1765 force_link_down = 1;
1766 }
ca58c3af 1767 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1768 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1769
ca58c3af 1770 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1771 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1772 new_bmcr |= BMCR_SPEED1000;
605a9e20 1773
27a005b8
MC		 1774 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1775 if (bp->req_line_speed == SPEED_2500)
1776 bnx2_enable_forced_2g5(bp);
1777 else if (bp->req_line_speed == SPEED_1000) {
1778 bnx2_disable_forced_2g5(bp);
1779 new_bmcr &= ~0x2000;
1780 }
1781
1782 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1783 if (bp->req_line_speed == SPEED_2500)
1784 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1785 else
1786 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1787 }
1788
b6016b76 1789 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1790 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1791 new_bmcr |= BMCR_FULLDPLX;
1792 }
1793 else {
5b0c76ad 1794 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1795 new_bmcr &= ~BMCR_FULLDPLX;
1796 }
5b0c76ad 1797 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1798 /* Force a link down visible on the other side */
1799 if (bp->link_up) {
ca58c3af 1800 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1801 ~(ADVERTISE_1000XFULL |
1802 ADVERTISE_1000XHALF));
ca58c3af 1803 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1804 BMCR_ANRESTART | BMCR_ANENABLE);
1805
1806 bp->link_up = 0;
1807 netif_carrier_off(bp->dev);
ca58c3af 1808 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1809 bnx2_report_link(bp);
b6016b76 1810 }
ca58c3af
MC		 1811 bnx2_write_phy(bp, bp->mii_adv, adv);
1812 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1813 } else {
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
b6016b76
MC		 1816 }
1817 return 0;
1818 }
1819
605a9e20 1820 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1821
b6016b76
MC		 1822 if (bp->advertising & ADVERTISED_1000baseT_Full)
1823 new_adv |= ADVERTISE_1000XFULL;
1824
1825 new_adv |= bnx2_phy_get_pause_adv(bp);
1826
ca58c3af
MC		 1827 bnx2_read_phy(bp, bp->mii_adv, &adv);
1828 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1829
1830 bp->serdes_an_pending = 0;
1831 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1832 /* Force a link down visible on the other side */
1833 if (bp->link_up) {
ca58c3af 1834 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1835 spin_unlock_bh(&bp->phy_lock);
1836 msleep(20);
1837 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1838 }
1839
ca58c3af
MC		 1840 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1841 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1842 BMCR_ANENABLE);
f8dd064e
MC		 1843 /* Speed up link-up time when the link partner
1844 * does not autonegotiate which is very common
1845 * in blade servers. Some blade servers use
1846 * IPMI for kerboard input and it's important
1847 * to minimize link disruptions. Autoneg. involves
1848 * exchanging base pages plus 3 next pages and
1849 * normally completes in about 120 msec.
1850 */
40105c0b 1851 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1852 bp->serdes_an_pending = 1;
1853 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1854 } else {
1855 bnx2_resolve_flow_ctrl(bp);
1856 bnx2_set_mac_link(bp);
b6016b76
MC		 1857 }
1858
1859 return 0;
1860}
1861
1862#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1863 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1864 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1865 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1866
1867#define ETHTOOL_ALL_COPPER_SPEED \
1868 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1869 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1870 ADVERTISED_1000baseT_Full)
1871
1872#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1873 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1874
b6016b76
MC		 1875#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1876
0d8a6571
MC		 1877static void
1878bnx2_set_default_remote_link(struct bnx2 *bp)
1879{
1880 u32 link;
1881
1882 if (bp->phy_port == PORT_TP)
2726d6e1 1883 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1884 else
2726d6e1 1885 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1886
1887 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1888 bp->req_line_speed = 0;
1889 bp->autoneg |= AUTONEG_SPEED;
1890 bp->advertising = ADVERTISED_Autoneg;
1891 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1892 bp->advertising |= ADVERTISED_10baseT_Half;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1894 bp->advertising |= ADVERTISED_10baseT_Full;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1896 bp->advertising |= ADVERTISED_100baseT_Half;
1897 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1898 bp->advertising |= ADVERTISED_100baseT_Full;
1899 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1900 bp->advertising |= ADVERTISED_1000baseT_Full;
1901 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1902 bp->advertising |= ADVERTISED_2500baseX_Full;
1903 } else {
1904 bp->autoneg = 0;
1905 bp->advertising = 0;
1906 bp->req_duplex = DUPLEX_FULL;
1907 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1908 bp->req_line_speed = SPEED_10;
1909 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1910 bp->req_duplex = DUPLEX_HALF;
1911 }
1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1913 bp->req_line_speed = SPEED_100;
1914 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1915 bp->req_duplex = DUPLEX_HALF;
1916 }
1917 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1918 bp->req_line_speed = SPEED_1000;
1919 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1920 bp->req_line_speed = SPEED_2500;
1921 }
1922}
1923
deaf391b
MC		 1924static void
1925bnx2_set_default_link(struct bnx2 *bp)
1926{
ab59859d
HH		 1927 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1928 bnx2_set_default_remote_link(bp);
1929 return;
1930 }
0d8a6571 1931
deaf391b
MC		 1932 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1933 bp->req_line_speed = 0;
583c28e5 1934 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1935 u32 reg;
1936
1937 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1938
2726d6e1 1939 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1940 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1941 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1942 bp->autoneg = 0;
1943 bp->req_line_speed = bp->line_speed = SPEED_1000;
1944 bp->req_duplex = DUPLEX_FULL;
1945 }
1946 } else
1947 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1948}
1949
df149d70
MC		 1950static void
1951bnx2_send_heart_beat(struct bnx2 *bp)
1952{
1953 u32 msg;
1954 u32 addr;
1955
1956 spin_lock(&bp->indirect_lock);
1957 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1958 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1959 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1960 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1961 spin_unlock(&bp->indirect_lock);
1962}
1963
0d8a6571
MC		 1964static void
1965bnx2_remote_phy_event(struct bnx2 *bp)
1966{
1967 u32 msg;
1968 u8 link_up = bp->link_up;
1969 u8 old_port;
1970
2726d6e1 1971 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1972
df149d70
MC		 1973 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1974 bnx2_send_heart_beat(bp);
1975
1976 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1977
0d8a6571
MC		 1978 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1979 bp->link_up = 0;
1980 else {
1981 u32 speed;
1982
1983 bp->link_up = 1;
1984 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1985 bp->duplex = DUPLEX_FULL;
1986 switch (speed) {
1987 case BNX2_LINK_STATUS_10HALF:
1988 bp->duplex = DUPLEX_HALF;
1989 case BNX2_LINK_STATUS_10FULL:
1990 bp->line_speed = SPEED_10;
1991 break;
1992 case BNX2_LINK_STATUS_100HALF:
1993 bp->duplex = DUPLEX_HALF;
1994 case BNX2_LINK_STATUS_100BASE_T4:
1995 case BNX2_LINK_STATUS_100FULL:
1996 bp->line_speed = SPEED_100;
1997 break;
1998 case BNX2_LINK_STATUS_1000HALF:
1999 bp->duplex = DUPLEX_HALF;
2000 case BNX2_LINK_STATUS_1000FULL:
2001 bp->line_speed = SPEED_1000;
2002 break;
2003 case BNX2_LINK_STATUS_2500HALF:
2004 bp->duplex = DUPLEX_HALF;
2005 case BNX2_LINK_STATUS_2500FULL:
2006 bp->line_speed = SPEED_2500;
2007 break;
2008 default:
2009 bp->line_speed = 0;
2010 break;
2011 }
2012
0d8a6571
MC		 2013 bp->flow_ctrl = 0;
2014 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2015 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2016 if (bp->duplex == DUPLEX_FULL)
2017 bp->flow_ctrl = bp->req_flow_ctrl;
2018 } else {
2019 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2020 bp->flow_ctrl |= FLOW_CTRL_TX;
2021 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2022 bp->flow_ctrl |= FLOW_CTRL_RX;
2023 }
2024
2025 old_port = bp->phy_port;
2026 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2027 bp->phy_port = PORT_FIBRE;
2028 else
2029 bp->phy_port = PORT_TP;
2030
2031 if (old_port != bp->phy_port)
2032 bnx2_set_default_link(bp);
2033
0d8a6571
MC		 2034 }
2035 if (bp->link_up != link_up)
2036 bnx2_report_link(bp);
2037
2038 bnx2_set_mac_link(bp);
2039}
2040
2041static int
2042bnx2_set_remote_link(struct bnx2 *bp)
2043{
2044 u32 evt_code;
2045
2726d6e1 2046 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2047 switch (evt_code) {
2048 case BNX2_FW_EVT_CODE_LINK_EVENT:
2049 bnx2_remote_phy_event(bp);
2050 break;
2051 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2052 default:
df149d70 2053 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2054 break;
2055 }
2056 return 0;
2057}
2058
b6016b76
MC		 2059static int
2060bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2061__releases(&bp->phy_lock)
2062__acquires(&bp->phy_lock)
b6016b76
MC		 2063{
2064 u32 bmcr;
2065 u32 new_bmcr;
2066
ca58c3af 2067 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2068
2069 if (bp->autoneg & AUTONEG_SPEED) {
2070 u32 adv_reg, adv1000_reg;
2071 u32 new_adv_reg = 0;
2072 u32 new_adv1000_reg = 0;
2073
ca58c3af 2074 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2075 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2076 ADVERTISE_PAUSE_ASYM);
2077
2078 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2079 adv1000_reg &= PHY_ALL_1000_SPEED;
2080
2081 if (bp->advertising & ADVERTISED_10baseT_Half)
2082 new_adv_reg |= ADVERTISE_10HALF;
2083 if (bp->advertising & ADVERTISED_10baseT_Full)
2084 new_adv_reg |= ADVERTISE_10FULL;
2085 if (bp->advertising & ADVERTISED_100baseT_Half)
2086 new_adv_reg |= ADVERTISE_100HALF;
2087 if (bp->advertising & ADVERTISED_100baseT_Full)
2088 new_adv_reg |= ADVERTISE_100FULL;
2089 if (bp->advertising & ADVERTISED_1000baseT_Full)
2090 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 2091
b6016b76
MC		 2092 new_adv_reg |= ADVERTISE_CSMA;
2093
2094 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2095
2096 if ((adv1000_reg != new_adv1000_reg) ||
2097 (adv_reg != new_adv_reg) ||
2098 ((bmcr & BMCR_ANENABLE) == 0)) {
2099
ca58c3af 2100 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 2101 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 2102 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2103 BMCR_ANENABLE);
2104 }
2105 else if (bp->link_up) {
2106 /* Flow ctrl may have changed from auto to forced */
2107 /* or vice-versa. */
2108
2109 bnx2_resolve_flow_ctrl(bp);
2110 bnx2_set_mac_link(bp);
2111 }
2112 return 0;
2113 }
2114
2115 new_bmcr = 0;
2116 if (bp->req_line_speed == SPEED_100) {
2117 new_bmcr |= BMCR_SPEED100;
2118 }
2119 if (bp->req_duplex == DUPLEX_FULL) {
2120 new_bmcr |= BMCR_FULLDPLX;
2121 }
2122 if (new_bmcr != bmcr) {
2123 u32 bmsr;
b6016b76 2124
ca58c3af
MC		 2125 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2126 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2127
b6016b76
MC		 2128 if (bmsr & BMSR_LSTATUS) {
2129 /* Force link down */
ca58c3af 2130 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2131 spin_unlock_bh(&bp->phy_lock);
2132 msleep(50);
2133 spin_lock_bh(&bp->phy_lock);
2134
ca58c3af
MC		 2135 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2136 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2137 }
2138
ca58c3af 2139 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2140
2141 /* Normally, the new speed is setup after the link has
2142 * gone down and up again. In some cases, link will not go
2143 * down so we need to set up the new speed here.
2144 */
2145 if (bmsr & BMSR_LSTATUS) {
2146 bp->line_speed = bp->req_line_speed;
2147 bp->duplex = bp->req_duplex;
2148 bnx2_resolve_flow_ctrl(bp);
2149 bnx2_set_mac_link(bp);
2150 }
27a005b8
MC		 2151 } else {
2152 bnx2_resolve_flow_ctrl(bp);
2153 bnx2_set_mac_link(bp);
b6016b76
MC		 2154 }
2155 return 0;
2156}
2157
2158static int
0d8a6571 2159bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2160__releases(&bp->phy_lock)
2161__acquires(&bp->phy_lock)
b6016b76
MC		 2162{
2163 if (bp->loopback == MAC_LOOPBACK)
2164 return 0;
2165
583c28e5 2166 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 2167 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 2168 }
2169 else {
2170 return (bnx2_setup_copper_phy(bp));
2171 }
2172}
2173
27a005b8 2174static int
9a120bc5 2175bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2176{
2177 u32 val;
2178
2179 bp->mii_bmcr = MII_BMCR + 0x10;
2180 bp->mii_bmsr = MII_BMSR + 0x10;
2181 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2182 bp->mii_adv = MII_ADVERTISE + 0x10;
2183 bp->mii_lpa = MII_LPA + 0x10;
2184 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2185
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2187 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2188
2189 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2190 if (reset_phy)
2191 bnx2_reset_phy(bp);
27a005b8
MC		 2192
2193 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2194
2195 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2196 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2197 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2198 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2199
2200 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2201 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2202 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2203 val |= BCM5708S_UP1_2G5;
2204 else
2205 val &= ~BCM5708S_UP1_2G5;
2206 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2207
2208 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2209 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2210 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2211 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2212
2213 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2214
2215 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2216 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2217 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2218
2219 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2220
2221 return 0;
2222}
2223
b6016b76 2224static int
9a120bc5 2225bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2226{
2227 u32 val;
2228
9a120bc5
MC		 2229 if (reset_phy)
2230 bnx2_reset_phy(bp);
27a005b8
MC		 2231
2232 bp->mii_up1 = BCM5708S_UP1;
2233
5b0c76ad
MC		 2234 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2235 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2236 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2237
2238 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2239 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2240 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2241
2242 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2243 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2244 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2245
583c28e5 2246 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2247 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2248 val |= BCM5708S_UP1_2G5;
2249 bnx2_write_phy(bp, BCM5708S_UP1, val);
2250 }
2251
2252 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2253 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2254 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2255 /* increase tx signal amplitude */
2256 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2257 BCM5708S_BLK_ADDR_TX_MISC);
2258 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2259 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2260 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2262 }
2263
2726d6e1 2264 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2265 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2266
2267 if (val) {
2268 u32 is_backplane;
2269
2726d6e1 2270 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2271 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2272 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2273 BCM5708S_BLK_ADDR_TX_MISC);
2274 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2275 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2276 BCM5708S_BLK_ADDR_DIG);
2277 }
2278 }
2279 return 0;
2280}
2281
2282static int
9a120bc5 2283bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2284{
9a120bc5
MC		 2285 if (reset_phy)
2286 bnx2_reset_phy(bp);
27a005b8 2287
583c28e5 2288 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2289
59b47d8a
MC		 2290 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2291 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2292
2293 if (bp->dev->mtu > 1500) {
2294 u32 val;
2295
2296 /* Set extended packet length bit */
2297 bnx2_write_phy(bp, 0x18, 0x7);
2298 bnx2_read_phy(bp, 0x18, &val);
2299 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2300
2301 bnx2_write_phy(bp, 0x1c, 0x6c00);
2302 bnx2_read_phy(bp, 0x1c, &val);
2303 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2304 }
2305 else {
2306 u32 val;
2307
2308 bnx2_write_phy(bp, 0x18, 0x7);
2309 bnx2_read_phy(bp, 0x18, &val);
2310 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2311
2312 bnx2_write_phy(bp, 0x1c, 0x6c00);
2313 bnx2_read_phy(bp, 0x1c, &val);
2314 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2315 }
2316
2317 return 0;
2318}
2319
2320static int
9a120bc5 2321bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2322{
5b0c76ad
MC		 2323 u32 val;
2324
9a120bc5
MC		 2325 if (reset_phy)
2326 bnx2_reset_phy(bp);
27a005b8 2327
583c28e5 2328 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2329 bnx2_write_phy(bp, 0x18, 0x0c00);
2330 bnx2_write_phy(bp, 0x17, 0x000a);
2331 bnx2_write_phy(bp, 0x15, 0x310b);
2332 bnx2_write_phy(bp, 0x17, 0x201f);
2333 bnx2_write_phy(bp, 0x15, 0x9506);
2334 bnx2_write_phy(bp, 0x17, 0x401f);
2335 bnx2_write_phy(bp, 0x15, 0x14e2);
2336 bnx2_write_phy(bp, 0x18, 0x0400);
2337 }
2338
583c28e5 2339 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2340 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2341 MII_BNX2_DSP_EXPAND_REG | 0x8);
2342 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2343 val &= ~(1 << 8);
2344 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2345 }
2346
b6016b76 2347 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2348 /* Set extended packet length bit */
2349 bnx2_write_phy(bp, 0x18, 0x7);
2350 bnx2_read_phy(bp, 0x18, &val);
2351 bnx2_write_phy(bp, 0x18, val | 0x4000);
2352
2353 bnx2_read_phy(bp, 0x10, &val);
2354 bnx2_write_phy(bp, 0x10, val | 0x1);
2355 }
2356 else {
b6016b76
MC		 2357 bnx2_write_phy(bp, 0x18, 0x7);
2358 bnx2_read_phy(bp, 0x18, &val);
2359 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2360
2361 bnx2_read_phy(bp, 0x10, &val);
2362 bnx2_write_phy(bp, 0x10, val & ~0x1);
2363 }
2364
5b0c76ad
MC		 2365 /* ethernet@wirespeed */
2366 bnx2_write_phy(bp, 0x18, 0x7007);
2367 bnx2_read_phy(bp, 0x18, &val);
2368 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2369 return 0;
2370}
2371
2372
2373static int
9a120bc5 2374bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2375__releases(&bp->phy_lock)
2376__acquires(&bp->phy_lock)
b6016b76
MC		 2377{
2378 u32 val;
2379 int rc = 0;
2380
583c28e5
MC		 2381 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2382 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2383
ca58c3af
MC		 2384 bp->mii_bmcr = MII_BMCR;
2385 bp->mii_bmsr = MII_BMSR;
27a005b8 2386 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2387 bp->mii_adv = MII_ADVERTISE;
2388 bp->mii_lpa = MII_LPA;
2389
b6016b76
MC		 2390 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2391
583c28e5 2392 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2393 goto setup_phy;
2394
b6016b76
MC		 2395 bnx2_read_phy(bp, MII_PHYSID1, &val);
2396 bp->phy_id = val << 16;
2397 bnx2_read_phy(bp, MII_PHYSID2, &val);
2398 bp->phy_id |= val & 0xffff;
2399
583c28e5 2400 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2401 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2402 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2403 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2404 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2405 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2406 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2407 }
2408 else {
9a120bc5 2409 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2410 }
2411
0d8a6571
MC		 2412setup_phy:
2413 if (!rc)
2414 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2415
2416 return rc;
2417}
2418
2419static int
2420bnx2_set_mac_loopback(struct bnx2 *bp)
2421{
2422 u32 mac_mode;
2423
2424 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2425 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2426 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2427 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2428 bp->link_up = 1;
2429 return 0;
2430}
2431
bc5a0690
MC		 2432static int bnx2_test_link(struct bnx2 *);
2433
2434static int
2435bnx2_set_phy_loopback(struct bnx2 *bp)
2436{
2437 u32 mac_mode;
2438 int rc, i;
2439
2440 spin_lock_bh(&bp->phy_lock);
ca58c3af 2441 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2442 BMCR_SPEED1000);
2443 spin_unlock_bh(&bp->phy_lock);
2444 if (rc)
2445 return rc;
2446
2447 for (i = 0; i < 10; i++) {
2448 if (bnx2_test_link(bp) == 0)
2449 break;
80be4434 2450 msleep(100);
bc5a0690
MC		 2451 }
2452
2453 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2454 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2455 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2456 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2457
2458 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2459 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2460 bp->link_up = 1;
2461 return 0;
2462}
2463
b6016b76 2464static int
a2f13890 2465bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2466{
2467 int i;
2468 u32 val;
2469
b6016b76
MC		 2470 bp->fw_wr_seq++;
2471 msg_data |= bp->fw_wr_seq;
2472
2726d6e1 2473 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2474
a2f13890
MC		 2475 if (!ack)
2476 return 0;
2477
b6016b76 2478 /* wait for an acknowledgement. */
40105c0b 2479 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2480 msleep(10);
b6016b76 2481
2726d6e1 2482 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2483
2484 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2485 break;
2486 }
b090ae2b
MC		 2487 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2488 return 0;
b6016b76
MC		 2489
2490 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2491 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2492 if (!silent)
3a9c6a49 2493 pr_err("fw sync timeout, reset code = %x\n", msg_data);
b6016b76
MC		 2494
2495 msg_data &= ~BNX2_DRV_MSG_CODE;
2496 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2497
2726d6e1 2498 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2499
b6016b76
MC		 2500 return -EBUSY;
2501 }
2502
b090ae2b
MC		 2503 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2504 return -EIO;
2505
b6016b76
MC		 2506 return 0;
2507}
2508
59b47d8a
MC		 2509static int
2510bnx2_init_5709_context(struct bnx2 *bp)
2511{
2512 int i, ret = 0;
2513 u32 val;
2514
2515 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2516 val |= (BCM_PAGE_BITS - 8) << 16;
2517 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2518 for (i = 0; i < 10; i++) {
2519 val = REG_RD(bp, BNX2_CTX_COMMAND);
2520 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2521 break;
2522 udelay(2);
2523 }
2524 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2525 return -EBUSY;
2526
59b47d8a
MC		 2527 for (i = 0; i < bp->ctx_pages; i++) {
2528 int j;
2529
352f7687
MC		 2530 if (bp->ctx_blk[i])
2531 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2532 else
2533 return -ENOMEM;
2534
59b47d8a
MC		 2535 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2536 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2537 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2538 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2539 (u64) bp->ctx_blk_mapping[i] >> 32);
2540 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2541 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2542 for (j = 0; j < 10; j++) {
2543
2544 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2545 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2546 break;
2547 udelay(5);
2548 }
2549 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2550 ret = -EBUSY;
2551 break;
2552 }
2553 }
2554 return ret;
2555}
2556
b6016b76
MC		 2557static void
2558bnx2_init_context(struct bnx2 *bp)
2559{
2560 u32 vcid;
2561
2562 vcid = 96;
2563 while (vcid) {
2564 u32 vcid_addr, pcid_addr, offset;
7947b20e 2565 int i;
b6016b76
MC		 2566
2567 vcid--;
2568
2569 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2570 u32 new_vcid;
2571
2572 vcid_addr = GET_PCID_ADDR(vcid);
2573 if (vcid & 0x8) {
2574 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2575 }
2576 else {
2577 new_vcid = vcid;
2578 }
2579 pcid_addr = GET_PCID_ADDR(new_vcid);
2580 }
2581 else {
2582 vcid_addr = GET_CID_ADDR(vcid);
2583 pcid_addr = vcid_addr;
2584 }
2585
7947b20e
MC		 2586 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2587 vcid_addr += (i << PHY_CTX_SHIFT);
2588 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2589
5d5d0015 2590 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2591 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2592
7947b20e
MC		 2593 /* Zero out the context. */
2594 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2595 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2596 }
b6016b76
MC		 2597 }
2598}
2599
2600static int
2601bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2602{
2603 u16 *good_mbuf;
2604 u32 good_mbuf_cnt;
2605 u32 val;
2606
2607 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2608 if (good_mbuf == NULL) {
3a9c6a49 2609 pr_err("Failed to allocate memory in %s\n", __func__);
b6016b76
MC		 2610 return -ENOMEM;
2611 }
2612
2613 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2614 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2615
2616 good_mbuf_cnt = 0;
2617
2618 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2619 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2620 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2621 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2622 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2623
2726d6e1 2624 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2625
2626 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2627
2628 /* The addresses with Bit 9 set are bad memory blocks. */
2629 if (!(val & (1 << 9))) {
2630 good_mbuf[good_mbuf_cnt] = (u16) val;
2631 good_mbuf_cnt++;
2632 }
2633
2726d6e1 2634 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2635 }
2636
2637 /* Free the good ones back to the mbuf pool thus discarding
2638 * all the bad ones. */
2639 while (good_mbuf_cnt) {
2640 good_mbuf_cnt--;
2641
2642 val = good_mbuf[good_mbuf_cnt];
2643 val = (val << 9) | val | 1;
2644
2726d6e1 2645 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2646 }
2647 kfree(good_mbuf);
2648 return 0;
2649}
2650
2651static void
5fcaed01 2652bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2653{
2654 u32 val;
b6016b76
MC		 2655
2656 val = (mac_addr[0] << 8) | mac_addr[1];
2657
5fcaed01 2658 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2659
6aa20a22 2660 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2661 (mac_addr[4] << 8) | mac_addr[5];
2662
5fcaed01 2663 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2664}
2665
47bf4246 2666static inline int
bb4f98ab 2667bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246
MC		 2668{
2669 dma_addr_t mapping;
bb4f98ab 2670 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2671 struct rx_bd *rxbd =
bb4f98ab 2672 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
47bf4246
MC		 2673 struct page *page = alloc_page(GFP_ATOMIC);
2674
2675 if (!page)
2676 return -ENOMEM;
2677 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2678 PCI_DMA_FROMDEVICE);
3d16af86
BL		 2679 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2680 __free_page(page);
2681 return -EIO;
2682 }
2683
47bf4246 2684 rx_pg->page = page;
1a4ccc2d 2685 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2686 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2687 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2688 return 0;
2689}
2690
2691static void
bb4f98ab 2692bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2693{
bb4f98ab 2694 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2695 struct page *page = rx_pg->page;
2696
2697 if (!page)
2698 return;
2699
1a4ccc2d 2700 pci_unmap_page(bp->pdev, dma_unmap_addr(rx_pg, mapping), PAGE_SIZE,
47bf4246
MC		 2701 PCI_DMA_FROMDEVICE);
2702
2703 __free_page(page);
2704 rx_pg->page = NULL;
2705}
2706
b6016b76 2707static inline int
bb4f98ab 2708bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
b6016b76
MC		 2709{
2710 struct sk_buff *skb;
bb4f98ab 2711 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2712 dma_addr_t mapping;
bb4f98ab 2713 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2714 unsigned long align;
2715
932f3772 2716 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2717 if (skb == NULL) {
2718 return -ENOMEM;
2719 }
2720
59b47d8a
MC		 2721 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2722 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2723
b6016b76
MC		 2724 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2725 PCI_DMA_FROMDEVICE);
3d16af86
BL		 2726 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2727 dev_kfree_skb(skb);
2728 return -EIO;
2729 }
b6016b76
MC		 2730
2731 rx_buf->skb = skb;
a33fa66b 2732 rx_buf->desc = (struct l2_fhdr *) skb->data;
1a4ccc2d 2733 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2734
2735 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2736 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2737
bb4f98ab 2738 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2739
2740 return 0;
2741}
2742
da3e4fbe 2743static int
35efa7c1 2744bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2745{
43e80b89 2746 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2747 u32 new_link_state, old_link_state;
da3e4fbe 2748 int is_set = 1;
b6016b76 2749
da3e4fbe
MC		 2750 new_link_state = sblk->status_attn_bits & event;
2751 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2752 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2753 if (new_link_state)
2754 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2755 else
2756 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2757 } else
2758 is_set = 0;
2759
2760 return is_set;
2761}
2762
2763static void
35efa7c1 2764bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2765{
74ecc62d
MC		 2766 spin_lock(&bp->phy_lock);
2767
2768 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2769 bnx2_set_link(bp);
35efa7c1 2770 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2771 bnx2_set_remote_link(bp);
2772
74ecc62d
MC		 2773 spin_unlock(&bp->phy_lock);
2774
b6016b76
MC		 2775}
2776
ead7270b 2777static inline u16
35efa7c1 2778bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2779{
2780 u16 cons;
2781
43e80b89
MC		 2782 /* Tell compiler that status block fields can change. */
2783 barrier();
2784 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2785 barrier();
ead7270b
MC		 2786 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2787 cons++;
2788 return cons;
2789}
2790
57851d84
MC		 2791static int
2792bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2793{
35e9010b 2794 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2795 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2796 int tx_pkt = 0, index;
2797 struct netdev_queue *txq;
2798
2799 index = (bnapi - bp->bnx2_napi);
2800 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2801
35efa7c1 2802 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2803 sw_cons = txr->tx_cons;
b6016b76
MC		 2804
2805 while (sw_cons != hw_cons) {
3d16af86 2806 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2807 struct sk_buff *skb;
2808 int i, last;
2809
2810 sw_ring_cons = TX_RING_IDX(sw_cons);
2811
35e9010b 2812 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2813 skb = tx_buf->skb;
1d39ed56 2814
d62fda08
ED		 2815 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2816 prefetch(&skb->end);
2817
b6016b76 2818 /* partial BD completions possible with TSO packets */
d62fda08 2819 if (tx_buf->is_gso) {
b6016b76
MC		 2820 u16 last_idx, last_ring_idx;
2821
d62fda08
ED		 2822 last_idx = sw_cons + tx_buf->nr_frags + 1;
2823 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
b6016b76
MC		 2824 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2825 last_idx++;
2826 }
2827 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2828 break;
2829 }
2830 }
1d39ed56 2831
1a4ccc2d 2832 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2833 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2834
2835 tx_buf->skb = NULL;
d62fda08 2836 last = tx_buf->nr_frags;
b6016b76
MC		 2837
2838 for (i = 0; i < last; i++) {
2839 sw_cons = NEXT_TX_BD(sw_cons);
e95524a7
AD		 2840
2841 pci_unmap_page(bp->pdev,
1a4ccc2d 2842 dma_unmap_addr(
e95524a7
AD		 2843 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2844 mapping),
2845 skb_shinfo(skb)->frags[i].size,
2846 PCI_DMA_TODEVICE);
b6016b76
MC		 2847 }
2848
2849 sw_cons = NEXT_TX_BD(sw_cons);
2850
745720e5 2851 dev_kfree_skb(skb);
57851d84
MC		 2852 tx_pkt++;
2853 if (tx_pkt == budget)
2854 break;
b6016b76 2855
d62fda08
ED		 2856 if (hw_cons == sw_cons)
2857 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2858 }
2859
35e9010b
MC		 2860 txr->hw_tx_cons = hw_cons;
2861 txr->tx_cons = sw_cons;
706bf240 2862
2f8af120 2863 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2864 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2865 * memory barrier, there is a small possibility that bnx2_start_xmit()
2866 * will miss it and cause the queue to be stopped forever.
2867 */
2868 smp_mb();
b6016b76 2869
706bf240 2870 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2871 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2872 __netif_tx_lock(txq, smp_processor_id());
2873 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2874 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2875 netif_tx_wake_queue(txq);
2876 __netif_tx_unlock(txq);
b6016b76 2877 }
706bf240 2878
57851d84 2879 return tx_pkt;
b6016b76
MC		 2880}
2881
1db82f2a 2882static void
bb4f98ab 2883bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2884 struct sk_buff *skb, int count)
1db82f2a
MC		 2885{
2886 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2887 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2888 int i;
3d16af86 2889 u16 hw_prod, prod;
bb4f98ab 2890 u16 cons = rxr->rx_pg_cons;
1db82f2a 2891
3d16af86
BL		 2892 cons_rx_pg = &rxr->rx_pg_ring[cons];
2893
2894 /* The caller was unable to allocate a new page to replace the
2895 * last one in the frags array, so we need to recycle that page
2896 * and then free the skb.
2897 */
2898 if (skb) {
2899 struct page *page;
2900 struct skb_shared_info *shinfo;
2901
2902 shinfo = skb_shinfo(skb);
2903 shinfo->nr_frags--;
2904 page = shinfo->frags[shinfo->nr_frags].page;
2905 shinfo->frags[shinfo->nr_frags].page = NULL;
2906
2907 cons_rx_pg->page = page;
2908 dev_kfree_skb(skb);
2909 }
2910
2911 hw_prod = rxr->rx_pg_prod;
2912
1db82f2a
MC		 2913 for (i = 0; i < count; i++) {
2914 prod = RX_PG_RING_IDX(hw_prod);
2915
bb4f98ab
MC		 2916 prod_rx_pg = &rxr->rx_pg_ring[prod];
2917 cons_rx_pg = &rxr->rx_pg_ring[cons];
2918 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2919 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2920
1db82f2a
MC		 2921 if (prod != cons) {
2922 prod_rx_pg->page = cons_rx_pg->page;
2923 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2924 dma_unmap_addr_set(prod_rx_pg, mapping,
2925 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2926
2927 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2928 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2929
2930 }
2931 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2932 hw_prod = NEXT_RX_BD(hw_prod);
2933 }
bb4f98ab
MC		 2934 rxr->rx_pg_prod = hw_prod;
2935 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2936}
2937
b6016b76 2938static inline void
bb4f98ab
MC		 2939bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2940 struct sk_buff *skb, u16 cons, u16 prod)
b6016b76 2941{
236b6394
MC		 2942 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2943 struct rx_bd *cons_bd, *prod_bd;
2944
bb4f98ab
MC		 2945 cons_rx_buf = &rxr->rx_buf_ring[cons];
2946 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76
MC		 2947
2948 pci_dma_sync_single_for_device(bp->pdev,
1a4ccc2d 2949 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2950 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2951
bb4f98ab 2952 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2953
236b6394 2954 prod_rx_buf->skb = skb;
a33fa66b 2955 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
b6016b76 2956
236b6394
MC		 2957 if (cons == prod)
2958 return;
b6016b76 2959
1a4ccc2d
FT		 2960 dma_unmap_addr_set(prod_rx_buf, mapping,
2961 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2962
bb4f98ab
MC		 2963 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2964 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2965 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2966 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2967}
2968
85833c62 2969static int
bb4f98ab 2970bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
a1f60190
MC		 2971 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2972 u32 ring_idx)
85833c62
MC		 2973{
2974 int err;
2975 u16 prod = ring_idx & 0xffff;
2976
bb4f98ab 2977 err = bnx2_alloc_rx_skb(bp, rxr, prod);
85833c62 2978 if (unlikely(err)) {
bb4f98ab 2979 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2980 if (hdr_len) {
2981 unsigned int raw_len = len + 4;
2982 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2983
bb4f98ab 2984 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 2985 }
85833c62
MC		 2986 return err;
2987 }
2988
d89cb6af 2989 skb_reserve(skb, BNX2_RX_OFFSET);
85833c62
MC		 2990 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2991 PCI_DMA_FROMDEVICE);
2992
1db82f2a
MC		 2993 if (hdr_len == 0) {
2994 skb_put(skb, len);
2995 return 0;
2996 } else {
2997 unsigned int i, frag_len, frag_size, pages;
2998 struct sw_pg *rx_pg;
bb4f98ab
MC		 2999 u16 pg_cons = rxr->rx_pg_cons;
3000 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3001
3002 frag_size = len + 4 - hdr_len;
3003 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3004 skb_put(skb, hdr_len);
3005
3006 for (i = 0; i < pages; i++) {
3d16af86
BL		 3007 dma_addr_t mapping_old;
3008
1db82f2a
MC		 3009 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3010 if (unlikely(frag_len <= 4)) {
3011 unsigned int tail = 4 - frag_len;
3012
bb4f98ab
MC		 3013 rxr->rx_pg_cons = pg_cons;
3014 rxr->rx_pg_prod = pg_prod;
3015 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3016 pages - i);
1db82f2a
MC		 3017 skb->len -= tail;
3018 if (i == 0) {
3019 skb->tail -= tail;
3020 } else {
3021 skb_frag_t *frag =
3022 &skb_shinfo(skb)->frags[i - 1];
3023 frag->size -= tail;
3024 skb->data_len -= tail;
3025 skb->truesize -= tail;
3026 }
3027 return 0;
3028 }
bb4f98ab 3029 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3030
3d16af86
BL		 3031 /* Don't unmap yet. If we're unable to allocate a new
3032 * page, we need to recycle the page and the DMA addr.
3033 */
1a4ccc2d 3034 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3035 if (i == pages - 1)
3036 frag_len -= 4;
3037
3038 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3039 rx_pg->page = NULL;
3040
bb4f98ab
MC		 3041 err = bnx2_alloc_rx_page(bp, rxr,
3042 RX_PG_RING_IDX(pg_prod));
1db82f2a 3043 if (unlikely(err)) {
bb4f98ab
MC		 3044 rxr->rx_pg_cons = pg_cons;
3045 rxr->rx_pg_prod = pg_prod;
3046 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3047 pages - i);
1db82f2a
MC		 3048 return err;
3049 }
3050
3d16af86
BL		 3051 pci_unmap_page(bp->pdev, mapping_old,
3052 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3053
1db82f2a
MC		 3054 frag_size -= frag_len;
3055 skb->data_len += frag_len;
3056 skb->truesize += frag_len;
3057 skb->len += frag_len;
3058
3059 pg_prod = NEXT_RX_BD(pg_prod);
3060 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3061 }
bb4f98ab
MC		 3062 rxr->rx_pg_prod = pg_prod;
3063 rxr->rx_pg_cons = pg_cons;
1db82f2a 3064 }
85833c62
MC		 3065 return 0;
3066}
3067
c09c2627 3068static inline u16
35efa7c1 3069bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3070{
bb4f98ab
MC		 3071 u16 cons;
3072
43e80b89
MC		 3073 /* Tell compiler that status block fields can change. */
3074 barrier();
3075 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3076 barrier();
c09c2627
MC		 3077 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3078 cons++;
3079 return cons;
3080}
3081
b6016b76 3082static int
35efa7c1 3083bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3084{
bb4f98ab 3085 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3086 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3087 struct l2_fhdr *rx_hdr;
1db82f2a 3088 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3089
35efa7c1 3090 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3091 sw_cons = rxr->rx_cons;
3092 sw_prod = rxr->rx_prod;
b6016b76
MC		 3093
3094 /* Memory barrier necessary as speculative reads of the rx
3095 * buffer can be ahead of the index in the status block
3096 */
3097 rmb();
3098 while (sw_cons != hw_cons) {
1db82f2a 3099 unsigned int len, hdr_len;
ade2bfe7 3100 u32 status;
a33fa66b 3101 struct sw_bd *rx_buf, *next_rx_buf;
b6016b76 3102 struct sk_buff *skb;
236b6394 3103 dma_addr_t dma_addr;
f22828e8
MC		 3104 u16 vtag = 0;
3105 int hw_vlan __maybe_unused = 0;
b6016b76
MC		 3106
3107 sw_ring_cons = RX_RING_IDX(sw_cons);
3108 sw_ring_prod = RX_RING_IDX(sw_prod);
3109
bb4f98ab 3110 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
b6016b76 3111 skb = rx_buf->skb;
a33fa66b 3112 prefetchw(skb);
236b6394 3113
aabef8b2
FT		 3114 next_rx_buf =
3115 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3116 prefetch(next_rx_buf->desc);
3117
236b6394
MC		 3118 rx_buf->skb = NULL;
3119
1a4ccc2d 3120 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394
MC		 3121
3122 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
601d3d18
BL		 3123 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3124 PCI_DMA_FROMDEVICE);
b6016b76 3125
a33fa66b 3126 rx_hdr = rx_buf->desc;
1db82f2a 3127 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3128 status = rx_hdr->l2_fhdr_status;
b6016b76 3129
1db82f2a
MC		 3130 hdr_len = 0;
3131 if (status & L2_FHDR_STATUS_SPLIT) {
3132 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3133 pg_ring_used = 1;
3134 } else if (len > bp->rx_jumbo_thresh) {
3135 hdr_len = bp->rx_jumbo_thresh;
3136 pg_ring_used = 1;
3137 }
3138
990ec380
MC		 3139 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3140 L2_FHDR_ERRORS_PHY_DECODE |
3141 L2_FHDR_ERRORS_ALIGNMENT |
3142 L2_FHDR_ERRORS_TOO_SHORT |
3143 L2_FHDR_ERRORS_GIANT_FRAME))) {
3144
3145 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3146 sw_ring_prod);
3147 if (pg_ring_used) {
3148 int pages;
3149
3150 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3151
3152 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3153 }
3154 goto next_rx;
3155 }
3156
1db82f2a 3157 len -= 4;
b6016b76 3158
5d5d0015 3159 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 3160 struct sk_buff *new_skb;
3161
f22828e8 3162 new_skb = netdev_alloc_skb(bp->dev, len + 6);
85833c62 3163 if (new_skb == NULL) {
bb4f98ab 3164 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
85833c62
MC		 3165 sw_ring_prod);
3166 goto next_rx;
3167 }
b6016b76
MC		 3168
3169 /* aligned copy */
d89cb6af 3170 skb_copy_from_linear_data_offset(skb,
f22828e8
MC		 3171 BNX2_RX_OFFSET - 6,
3172 new_skb->data, len + 6);
3173 skb_reserve(new_skb, 6);
b6016b76 3174 skb_put(new_skb, len);
b6016b76 3175
bb4f98ab 3176 bnx2_reuse_rx_skb(bp, rxr, skb,
b6016b76
MC		 3177 sw_ring_cons, sw_ring_prod);
3178
3179 skb = new_skb;
bb4f98ab 3180 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
a1f60190 3181 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 3182 goto next_rx;
b6016b76 3183
f22828e8
MC		 3184 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3185 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3186 vtag = rx_hdr->l2_fhdr_vlan_tag;
3187#ifdef BCM_VLAN
3188 if (bp->vlgrp)
3189 hw_vlan = 1;
3190 else
3191#endif
3192 {
3193 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3194 __skb_push(skb, 4);
3195
3196 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3197 ve->h_vlan_proto = htons(ETH_P_8021Q);
3198 ve->h_vlan_TCI = htons(vtag);
3199 len += 4;
3200 }
3201 }
3202
b6016b76
MC		 3203 skb->protocol = eth_type_trans(skb, bp->dev);
3204
3205 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3206 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3207
745720e5 3208 dev_kfree_skb(skb);
b6016b76
MC		 3209 goto next_rx;
3210
3211 }
3212
b6016b76
MC		 3213 skb->ip_summed = CHECKSUM_NONE;
3214 if (bp->rx_csum &&
3215 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3216 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3217
ade2bfe7
MC		 3218 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3219 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3220 skb->ip_summed = CHECKSUM_UNNECESSARY;
3221 }
fdc8541d
MC		 3222 if ((bp->dev->features & NETIF_F_RXHASH) &&
3223 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3224 L2_FHDR_STATUS_USE_RXHASH))
3225 skb->rxhash = rx_hdr->l2_fhdr_hash;
b6016b76 3226
0c8dfc83
DM		 3227 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3228
b6016b76 3229#ifdef BCM_VLAN
f22828e8 3230 if (hw_vlan)
c67938a9 3231 vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
b6016b76
MC		 3232 else
3233#endif
c67938a9 3234 napi_gro_receive(&bnapi->napi, skb);
b6016b76 3235
b6016b76
MC		 3236 rx_pkt++;
3237
3238next_rx:
b6016b76
MC		 3239 sw_cons = NEXT_RX_BD(sw_cons);
3240 sw_prod = NEXT_RX_BD(sw_prod);
3241
3242 if ((rx_pkt == budget))
3243 break;
f4e418f7
MC		 3244
3245 /* Refresh hw_cons to see if there is new work */
3246 if (sw_cons == hw_cons) {
35efa7c1 3247 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3248 rmb();
3249 }
b6016b76 3250 }
bb4f98ab
MC		 3251 rxr->rx_cons = sw_cons;
3252 rxr->rx_prod = sw_prod;
b6016b76 3253
1db82f2a 3254 if (pg_ring_used)
bb4f98ab 3255 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3256
bb4f98ab 3257 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3258
bb4f98ab 3259 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3260
3261 mmiowb();
3262
3263 return rx_pkt;
3264
3265}
3266
3267/* MSI ISR - The only difference between this and the INTx ISR
3268 * is that the MSI interrupt is always serviced.
3269 */
3270static irqreturn_t
7d12e780 3271bnx2_msi(int irq, void *dev_instance)
b6016b76 3272{
f0ea2e63
MC		 3273 struct bnx2_napi *bnapi = dev_instance;
3274 struct bnx2 *bp = bnapi->bp;
b6016b76 3275
43e80b89 3276 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3277 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3278 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3279 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3280
3281 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3282 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3283 return IRQ_HANDLED;
b6016b76 3284
288379f0 3285 napi_schedule(&bnapi->napi);
b6016b76 3286
73eef4cd 3287 return IRQ_HANDLED;
b6016b76
MC		 3288}
3289
8e6a72c4
MC		 3290static irqreturn_t
3291bnx2_msi_1shot(int irq, void *dev_instance)
3292{
f0ea2e63
MC		 3293 struct bnx2_napi *bnapi = dev_instance;
3294 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3295
43e80b89 3296 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3297
3298 /* Return here if interrupt is disabled. */
3299 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3300 return IRQ_HANDLED;
3301
288379f0 3302 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3303
3304 return IRQ_HANDLED;
3305}
3306
b6016b76 3307static irqreturn_t
7d12e780 3308bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3309{
f0ea2e63
MC		 3310 struct bnx2_napi *bnapi = dev_instance;
3311 struct bnx2 *bp = bnapi->bp;
43e80b89 3312 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3313
3314 /* When using INTx, it is possible for the interrupt to arrive
3315 * at the CPU before the status block posted prior to the
3316 * interrupt. Reading a register will flush the status block.
3317 * When using MSI, the MSI message will always complete after
3318 * the status block write.
3319 */
35efa7c1 3320 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3321 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3322 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3323 return IRQ_NONE;
b6016b76
MC		 3324
3325 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3326 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3327 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3328
b8a7ce7b
MC		 3329 /* Read back to deassert IRQ immediately to avoid too many
3330 * spurious interrupts.
3331 */
3332 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3333
b6016b76 3334 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3335 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3336 return IRQ_HANDLED;
b6016b76 3337
288379f0 3338 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3339 bnapi->last_status_idx = sblk->status_idx;
288379f0 3340 __napi_schedule(&bnapi->napi);
b8a7ce7b 3341 }
b6016b76 3342
73eef4cd 3343 return IRQ_HANDLED;
b6016b76
MC		 3344}
3345
f4e418f7 3346static inline int
43e80b89 3347bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3348{
35e9010b 3349 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3350 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3351
bb4f98ab 3352 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3353 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3354 return 1;
43e80b89
MC		 3355 return 0;
3356}
3357
3358#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3359 STATUS_ATTN_BITS_TIMER_ABORT)
3360
3361static inline int
3362bnx2_has_work(struct bnx2_napi *bnapi)
3363{
3364 struct status_block *sblk = bnapi->status_blk.msi;
3365
3366 if (bnx2_has_fast_work(bnapi))
3367 return 1;
f4e418f7 3368
4edd473f
MC		 3369#ifdef BCM_CNIC
3370 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3371 return 1;
3372#endif
3373
da3e4fbe
MC		 3374 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3375 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3376 return 1;
3377
3378 return 0;
3379}
3380
efba0180
MC		 3381static void
3382bnx2_chk_missed_msi(struct bnx2 *bp)
3383{
3384 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3385 u32 msi_ctrl;
3386
3387 if (bnx2_has_work(bnapi)) {
3388 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3389 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3390 return;
3391
3392 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3393 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3394 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3395 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3396 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3397 }
3398 }
3399
3400 bp->idle_chk_status_idx = bnapi->last_status_idx;
3401}
3402
4edd473f
MC		 3403#ifdef BCM_CNIC
3404static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3405{
3406 struct cnic_ops *c_ops;
3407
3408 if (!bnapi->cnic_present)
3409 return;
3410
3411 rcu_read_lock();
3412 c_ops = rcu_dereference(bp->cnic_ops);
3413 if (c_ops)
3414 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3415 bnapi->status_blk.msi);
3416 rcu_read_unlock();
3417}
3418#endif
3419
43e80b89 3420static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3421{
43e80b89 3422 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3423 u32 status_attn_bits = sblk->status_attn_bits;
3424 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3425
da3e4fbe
MC		 3426 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3427 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3428
35efa7c1 3429 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3430
3431 /* This is needed to take care of transient status
3432 * during link changes.
3433 */
3434 REG_WR(bp, BNX2_HC_COMMAND,
3435 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3436 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3437 }
43e80b89
MC		 3438}
3439
3440static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3441 int work_done, int budget)
3442{
3443 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3444 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3445
35e9010b 3446 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3447 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3448
bb4f98ab 3449 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3450 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3451
6f535763
DM		 3452 return work_done;
3453}
3454
f0ea2e63
MC		 3455static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3456{
3457 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3458 struct bnx2 *bp = bnapi->bp;
3459 int work_done = 0;
3460 struct status_block_msix *sblk = bnapi->status_blk.msix;
3461
3462 while (1) {
3463 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3464 if (unlikely(work_done >= budget))
3465 break;
3466
3467 bnapi->last_status_idx = sblk->status_idx;
3468 /* status idx must be read before checking for more work. */
3469 rmb();
3470 if (likely(!bnx2_has_fast_work(bnapi))) {
3471
288379f0 3472 napi_complete(napi);
f0ea2e63
MC		 3473 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3474 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3475 bnapi->last_status_idx);
3476 break;
3477 }
3478 }
3479 return work_done;
3480}
3481
6f535763
DM		 3482static int bnx2_poll(struct napi_struct *napi, int budget)
3483{
35efa7c1
MC		 3484 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3485 struct bnx2 *bp = bnapi->bp;
6f535763 3486 int work_done = 0;
43e80b89 3487 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3488
3489 while (1) {
43e80b89
MC		 3490 bnx2_poll_link(bp, bnapi);
3491
35efa7c1 3492 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3493
4edd473f
MC		 3494#ifdef BCM_CNIC
3495 bnx2_poll_cnic(bp, bnapi);
3496#endif
3497
35efa7c1 3498 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3499 * much work has been processed, so we must read it before
3500 * checking for more work.
3501 */
35efa7c1 3502 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3503
3504 if (unlikely(work_done >= budget))
3505 break;
3506
6dee6421 3507 rmb();
35efa7c1 3508 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3509 napi_complete(napi);
f86e82fb 3510 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3511 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3512 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3513 bnapi->last_status_idx);
6dee6421 3514 break;
6f535763 3515 }
1269a8a6
MC		 3516 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3517 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3518 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3519 bnapi->last_status_idx);
1269a8a6 3520
6f535763
DM		 3521 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3522 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3523 bnapi->last_status_idx);
6f535763
DM		 3524 break;
3525 }
b6016b76
MC		 3526 }
3527
bea3348e 3528 return work_done;
b6016b76
MC		 3529}
3530
932ff279 3531/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3532 * from set_multicast.
3533 */
3534static void
3535bnx2_set_rx_mode(struct net_device *dev)
3536{
972ec0d4 3537 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3538 u32 rx_mode, sort_mode;
ccffad25 3539 struct netdev_hw_addr *ha;
b6016b76 3540 int i;
b6016b76 3541
9f52b564
MC		 3542 if (!netif_running(dev))
3543 return;
3544
c770a65c 3545 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3546
3547 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3548 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3549 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3550#ifdef BCM_VLAN
7c6337a1 3551 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3552 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3553#else
7c6337a1 3554 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
e29054f9 3555 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3556#endif
3557 if (dev->flags & IFF_PROMISC) {
3558 /* Promiscuous mode. */
3559 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3560 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3561 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3562 }
3563 else if (dev->flags & IFF_ALLMULTI) {
3564 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3565 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3566 0xffffffff);
3567 }
3568 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3569 }
3570 else {
3571 /* Accept one or more multicast(s). */
b6016b76
MC		 3572 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3573 u32 regidx;
3574 u32 bit;
3575 u32 crc;
3576
3577 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3578
22bedad3
JP		 3579 netdev_for_each_mc_addr(ha, dev) {
3580 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3581 bit = crc & 0xff;
3582 regidx = (bit & 0xe0) >> 5;
3583 bit &= 0x1f;
3584 mc_filter[regidx] |= (1 << bit);
3585 }
3586
3587 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3588 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3589 mc_filter[i]);
3590 }
3591
3592 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3593 }
3594
32e7bfc4 3595 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3596 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3597 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3598 BNX2_RPM_SORT_USER0_PROM_VLAN;
3599 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3600 /* Add all entries into to the match filter list */
ccffad25 3601 i = 0;
32e7bfc4 3602 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3603 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3604 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3605 sort_mode |= (1 <<
3606 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3607 i++;
5fcaed01
BL		 3608 }
3609
3610 }
3611
b6016b76
MC		 3612 if (rx_mode != bp->rx_mode) {
3613 bp->rx_mode = rx_mode;
3614 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3615 }
3616
3617 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3618 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3619 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3620
c770a65c 3621 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3622}
3623
57579f76
MC		 3624static int __devinit
3625check_fw_section(const struct firmware *fw,
3626 const struct bnx2_fw_file_section *section,
3627 u32 alignment, bool non_empty)
3628{
3629 u32 offset = be32_to_cpu(section->offset);
3630 u32 len = be32_to_cpu(section->len);
3631
3632 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3633 return -EINVAL;
3634 if ((non_empty && len == 0) || len > fw->size - offset ||
3635 len & (alignment - 1))
3636 return -EINVAL;
3637 return 0;
3638}
3639
3640static int __devinit
3641check_mips_fw_entry(const struct firmware *fw,
3642 const struct bnx2_mips_fw_file_entry *entry)
3643{
3644 if (check_fw_section(fw, &entry->text, 4, true) ||
3645 check_fw_section(fw, &entry->data, 4, false) ||
3646 check_fw_section(fw, &entry->rodata, 4, false))
3647 return -EINVAL;
3648 return 0;
3649}
3650
3651static int __devinit
3652bnx2_request_firmware(struct bnx2 *bp)
b6016b76 3653{
57579f76 3654 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3655 const struct bnx2_mips_fw_file *mips_fw;
3656 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3657 int rc;
3658
3659 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3660 mips_fw_file = FW_MIPS_FILE_09;
078b0735
MC		 3661 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3662 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3663 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3664 else
3665 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3666 } else {
3667 mips_fw_file = FW_MIPS_FILE_06;
3668 rv2p_fw_file = FW_RV2P_FILE_06;
3669 }
3670
3671 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3672 if (rc) {
3a9c6a49 3673 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
57579f76
MC		 3674 return rc;
3675 }
3676
3677 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3678 if (rc) {
3a9c6a49 3679 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
57579f76
MC		 3680 return rc;
3681 }
5ee1c326
BB		 3682 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3683 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3684 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3685 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3686 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3687 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3688 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3689 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3690 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
57579f76
MC		 3691 return -EINVAL;
3692 }
5ee1c326
BB		 3693 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3694 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3695 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3696 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
57579f76
MC		 3697 return -EINVAL;
3698 }
3699
3700 return 0;
3701}
3702
3703static u32
3704rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3705{
3706 switch (idx) {
3707 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3708 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3709 rv2p_code |= RV2P_BD_PAGE_SIZE;
3710 break;
3711 }
3712 return rv2p_code;
3713}
3714
3715static int
3716load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3717 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3718{
3719 u32 rv2p_code_len, file_offset;
3720 __be32 *rv2p_code;
b6016b76 3721 int i;
57579f76
MC		 3722 u32 val, cmd, addr;
3723
3724 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3725 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3726
3727 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3728
57579f76
MC		 3729 if (rv2p_proc == RV2P_PROC1) {
3730 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3731 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3732 } else {
3733 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3734 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3735 }
b6016b76
MC		 3736
3737 for (i = 0; i < rv2p_code_len; i += 8) {
57579f76 3738 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3739 rv2p_code++;
57579f76 3740 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3741 rv2p_code++;
3742
57579f76
MC		 3743 val = (i / 8) | cmd;
3744 REG_WR(bp, addr, val);
3745 }
3746
3747 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3748 for (i = 0; i < 8; i++) {
3749 u32 loc, code;
3750
3751 loc = be32_to_cpu(fw_entry->fixup[i]);
3752 if (loc && ((loc * 4) < rv2p_code_len)) {
3753 code = be32_to_cpu(*(rv2p_code + loc - 1));
3754 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3755 code = be32_to_cpu(*(rv2p_code + loc));
3756 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3757 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3758
3759 val = (loc / 2) | cmd;
3760 REG_WR(bp, addr, val);
b6016b76
MC		 3761 }
3762 }
3763
3764 /* Reset the processor, un-stall is done later. */
3765 if (rv2p_proc == RV2P_PROC1) {
3766 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3767 }
3768 else {
3769 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3770 }
57579f76
MC		 3771
3772 return 0;
b6016b76
MC		 3773}
3774
af3ee519 3775static int
57579f76
MC		 3776load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3777 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3778{
57579f76
MC		 3779 u32 addr, len, file_offset;
3780 __be32 *data;
b6016b76
MC		 3781 u32 offset;
3782 u32 val;
3783
3784 /* Halt the CPU. */
2726d6e1 3785 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3786 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3787 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3788 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3789
3790 /* Load the Text area. */
57579f76
MC		 3791 addr = be32_to_cpu(fw_entry->text.addr);
3792 len = be32_to_cpu(fw_entry->text.len);
3793 file_offset = be32_to_cpu(fw_entry->text.offset);
3794 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3795
57579f76
MC		 3796 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3797 if (len) {
b6016b76
MC		 3798 int j;
3799
57579f76
MC		 3800 for (j = 0; j < (len / 4); j++, offset += 4)
3801 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3802 }
3803
57579f76
MC		 3804 /* Load the Data area. */
3805 addr = be32_to_cpu(fw_entry->data.addr);
3806 len = be32_to_cpu(fw_entry->data.len);
3807 file_offset = be32_to_cpu(fw_entry->data.offset);
3808 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3809
57579f76
MC		 3810 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3811 if (len) {
b6016b76
MC		 3812 int j;
3813
57579f76
MC		 3814 for (j = 0; j < (len / 4); j++, offset += 4)
3815 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3816 }
3817
3818 /* Load the Read-Only area. */
57579f76
MC		 3819 addr = be32_to_cpu(fw_entry->rodata.addr);
3820 len = be32_to_cpu(fw_entry->rodata.len);
3821 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3822 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3823
3824 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3825 if (len) {
b6016b76
MC		 3826 int j;
3827
57579f76
MC		 3828 for (j = 0; j < (len / 4); j++, offset += 4)
3829 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3830 }
3831
3832 /* Clear the pre-fetch instruction. */
2726d6e1 3833 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3834
3835 val = be32_to_cpu(fw_entry->start_addr);
3836 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3837
3838 /* Start the CPU. */
2726d6e1 3839 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3840 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3841 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3842 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3843
3844 return 0;
b6016b76
MC		 3845}
3846
fba9fe91 3847static int
b6016b76
MC		 3848bnx2_init_cpus(struct bnx2 *bp)
3849{
57579f76
MC		 3850 const struct bnx2_mips_fw_file *mips_fw =
3851 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3852 const struct bnx2_rv2p_fw_file *rv2p_fw =
3853 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3854 int rc;
b6016b76
MC		 3855
3856 /* Initialize the RV2P processor. */
57579f76
MC		 3857 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3858 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3859
3860 /* Initialize the RX Processor. */
57579f76 3861 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3862 if (rc)
3863 goto init_cpu_err;
3864
b6016b76 3865 /* Initialize the TX Processor. */
57579f76 3866 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3867 if (rc)
3868 goto init_cpu_err;
3869
b6016b76 3870 /* Initialize the TX Patch-up Processor. */
57579f76 3871 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3872 if (rc)
3873 goto init_cpu_err;
3874
b6016b76 3875 /* Initialize the Completion Processor. */
57579f76 3876 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3877 if (rc)
3878 goto init_cpu_err;
3879
d43584c8 3880 /* Initialize the Command Processor. */
57579f76 3881 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3882
fba9fe91 3883init_cpu_err:
fba9fe91 3884 return rc;
b6016b76
MC		 3885}
3886
3887static int
829ca9a3 3888bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3889{
3890 u16 pmcsr;
3891
3892 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3893
3894 switch (state) {
829ca9a3 3895 case PCI_D0: {
b6016b76
MC		 3896 u32 val;
3897
3898 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3899 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3900 PCI_PM_CTRL_PME_STATUS);
3901
3902 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3903 /* delay required during transition out of D3hot */
3904 msleep(20);
3905
3906 val = REG_RD(bp, BNX2_EMAC_MODE);
3907 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3908 val &= ~BNX2_EMAC_MODE_MPKT;
3909 REG_WR(bp, BNX2_EMAC_MODE, val);
3910
3911 val = REG_RD(bp, BNX2_RPM_CONFIG);
3912 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3913 REG_WR(bp, BNX2_RPM_CONFIG, val);
3914 break;
3915 }
829ca9a3 3916 case PCI_D3hot: {
b6016b76
MC		 3917 int i;
3918 u32 val, wol_msg;
3919
3920 if (bp->wol) {
3921 u32 advertising;
3922 u8 autoneg;
3923
3924 autoneg = bp->autoneg;
3925 advertising = bp->advertising;
3926
239cd343
MC		 3927 if (bp->phy_port == PORT_TP) {
3928 bp->autoneg = AUTONEG_SPEED;
3929 bp->advertising = ADVERTISED_10baseT_Half |
3930 ADVERTISED_10baseT_Full |
3931 ADVERTISED_100baseT_Half |
3932 ADVERTISED_100baseT_Full |
3933 ADVERTISED_Autoneg;
3934 }
b6016b76 3935
239cd343
MC		 3936 spin_lock_bh(&bp->phy_lock);
3937 bnx2_setup_phy(bp, bp->phy_port);
3938 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3939
3940 bp->autoneg = autoneg;
3941 bp->advertising = advertising;
3942
5fcaed01 3943 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3944
3945 val = REG_RD(bp, BNX2_EMAC_MODE);
3946
3947 /* Enable port mode. */
3948 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3949 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3950 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3951 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3952 if (bp->phy_port == PORT_TP)
3953 val |= BNX2_EMAC_MODE_PORT_MII;
3954 else {
3955 val |= BNX2_EMAC_MODE_PORT_GMII;
3956 if (bp->line_speed == SPEED_2500)
3957 val |= BNX2_EMAC_MODE_25G_MODE;
3958 }
b6016b76
MC		 3959
3960 REG_WR(bp, BNX2_EMAC_MODE, val);
3961
3962 /* receive all multicast */
3963 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3964 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3965 0xffffffff);
3966 }
3967 REG_WR(bp, BNX2_EMAC_RX_MODE,
3968 BNX2_EMAC_RX_MODE_SORT_MODE);
3969
3970 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3971 BNX2_RPM_SORT_USER0_MC_EN;
3972 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3973 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3974 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3975 BNX2_RPM_SORT_USER0_ENA);
3976
3977 /* Need to enable EMAC and RPM for WOL. */
3978 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3979 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3980 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3981 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3982
3983 val = REG_RD(bp, BNX2_RPM_CONFIG);
3984 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3985 REG_WR(bp, BNX2_RPM_CONFIG, val);
3986
3987 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3988 }
3989 else {
3990 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3991 }
3992
f86e82fb 3993 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 3994 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3995 1, 0);
b6016b76
MC		 3996
3997 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3998 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3999 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4000
4001 if (bp->wol)
4002 pmcsr |= 3;
4003 }
4004 else {
4005 pmcsr |= 3;
4006 }
4007 if (bp->wol) {
4008 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4009 }
4010 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4011 pmcsr);
4012
4013 /* No more memory access after this point until
4014 * device is brought back to D0.
4015 */
4016 udelay(50);
4017 break;
4018 }
4019 default:
4020 return -EINVAL;
4021 }
4022 return 0;
4023}
4024
4025static int
4026bnx2_acquire_nvram_lock(struct bnx2 *bp)
4027{
4028 u32 val;
4029 int j;
4030
4031 /* Request access to the flash interface. */
4032 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4033 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4034 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4035 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4036 break;
4037
4038 udelay(5);
4039 }
4040
4041 if (j >= NVRAM_TIMEOUT_COUNT)
4042 return -EBUSY;
4043
4044 return 0;
4045}
4046
4047static int
4048bnx2_release_nvram_lock(struct bnx2 *bp)
4049{
4050 int j;
4051 u32 val;
4052
4053 /* Relinquish nvram interface. */
4054 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4055
4056 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4057 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4058 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4059 break;
4060
4061 udelay(5);
4062 }
4063
4064 if (j >= NVRAM_TIMEOUT_COUNT)
4065 return -EBUSY;
4066
4067 return 0;
4068}
4069
4070
4071static int
4072bnx2_enable_nvram_write(struct bnx2 *bp)
4073{
4074 u32 val;
4075
4076 val = REG_RD(bp, BNX2_MISC_CFG);
4077 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4078
e30372c9 4079 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4080 int j;
4081
4082 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4083 REG_WR(bp, BNX2_NVM_COMMAND,
4084 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4085
4086 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4087 udelay(5);
4088
4089 val = REG_RD(bp, BNX2_NVM_COMMAND);
4090 if (val & BNX2_NVM_COMMAND_DONE)
4091 break;
4092 }
4093
4094 if (j >= NVRAM_TIMEOUT_COUNT)
4095 return -EBUSY;
4096 }
4097 return 0;
4098}
4099
4100static void
4101bnx2_disable_nvram_write(struct bnx2 *bp)
4102{
4103 u32 val;
4104
4105 val = REG_RD(bp, BNX2_MISC_CFG);
4106 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4107}
4108
4109
4110static void
4111bnx2_enable_nvram_access(struct bnx2 *bp)
4112{
4113 u32 val;
4114
4115 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4116 /* Enable both bits, even on read. */
6aa20a22 4117 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4118 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4119}
4120
4121static void
4122bnx2_disable_nvram_access(struct bnx2 *bp)
4123{
4124 u32 val;
4125
4126 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4127 /* Disable both bits, even after read. */
6aa20a22 4128 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4129 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4130 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4131}
4132
4133static int
4134bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4135{
4136 u32 cmd;
4137 int j;
4138
e30372c9 4139 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4140 /* Buffered flash, no erase needed */
4141 return 0;
4142
4143 /* Build an erase command */
4144 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4145 BNX2_NVM_COMMAND_DOIT;
4146
4147 /* Need to clear DONE bit separately. */
4148 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4149
4150 /* Address of the NVRAM to read from. */
4151 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4152
4153 /* Issue an erase command. */
4154 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4155
4156 /* Wait for completion. */
4157 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4158 u32 val;
4159
4160 udelay(5);
4161
4162 val = REG_RD(bp, BNX2_NVM_COMMAND);
4163 if (val & BNX2_NVM_COMMAND_DONE)
4164 break;
4165 }
4166
4167 if (j >= NVRAM_TIMEOUT_COUNT)
4168 return -EBUSY;
4169
4170 return 0;
4171}
4172
4173static int
4174bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4175{
4176 u32 cmd;
4177 int j;
4178
4179 /* Build the command word. */
4180 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4181
e30372c9
MC		 4182 /* Calculate an offset of a buffered flash, not needed for 5709. */
4183 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4184 offset = ((offset / bp->flash_info->page_size) <<
4185 bp->flash_info->page_bits) +
4186 (offset % bp->flash_info->page_size);
4187 }
4188
4189 /* Need to clear DONE bit separately. */
4190 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4191
4192 /* Address of the NVRAM to read from. */
4193 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4194
4195 /* Issue a read command. */
4196 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4197
4198 /* Wait for completion. */
4199 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4200 u32 val;
4201
4202 udelay(5);
4203
4204 val = REG_RD(bp, BNX2_NVM_COMMAND);
4205 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 4206 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4207 memcpy(ret_val, &v, 4);
b6016b76
MC		 4208 break;
4209 }
4210 }
4211 if (j >= NVRAM_TIMEOUT_COUNT)
4212 return -EBUSY;
4213
4214 return 0;
4215}
4216
4217
4218static int
4219bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4220{
b491edd5
AV		 4221 u32 cmd;
4222 __be32 val32;
b6016b76
MC		 4223 int j;
4224
4225 /* Build the command word. */
4226 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4227
e30372c9
MC		 4228 /* Calculate an offset of a buffered flash, not needed for 5709. */
4229 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4230 offset = ((offset / bp->flash_info->page_size) <<
4231 bp->flash_info->page_bits) +
4232 (offset % bp->flash_info->page_size);
4233 }
4234
4235 /* Need to clear DONE bit separately. */
4236 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4237
4238 memcpy(&val32, val, 4);
b6016b76
MC		 4239
4240 /* Write the data. */
b491edd5 4241 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4242
4243 /* Address of the NVRAM to write to. */
4244 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4245
4246 /* Issue the write command. */
4247 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4248
4249 /* Wait for completion. */
4250 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4251 udelay(5);
4252
4253 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4254 break;
4255 }
4256 if (j >= NVRAM_TIMEOUT_COUNT)
4257 return -EBUSY;
4258
4259 return 0;
4260}
4261
4262static int
4263bnx2_init_nvram(struct bnx2 *bp)
4264{
4265 u32 val;
e30372c9 4266 int j, entry_count, rc = 0;
0ced9d01 4267 const struct flash_spec *flash;
b6016b76 4268
e30372c9
MC		 4269 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4270 bp->flash_info = &flash_5709;
4271 goto get_flash_size;
4272 }
4273
b6016b76
MC		 4274 /* Determine the selected interface. */
4275 val = REG_RD(bp, BNX2_NVM_CFG1);
4276
ff8ac609 4277 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4278
b6016b76
MC		 4279 if (val & 0x40000000) {
4280
4281 /* Flash interface has been reconfigured */
4282 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4283 j++, flash++) {
4284 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4285 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4286 bp->flash_info = flash;
4287 break;
4288 }
4289 }
4290 }
4291 else {
37137709 4292 u32 mask;
b6016b76
MC		 4293 /* Not yet been reconfigured */
4294
37137709
MC		 4295 if (val & (1 << 23))
4296 mask = FLASH_BACKUP_STRAP_MASK;
4297 else
4298 mask = FLASH_STRAP_MASK;
4299
b6016b76
MC		 4300 for (j = 0, flash = &flash_table[0]; j < entry_count;
4301 j++, flash++) {
4302
37137709 4303 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4304 bp->flash_info = flash;
4305
4306 /* Request access to the flash interface. */
4307 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4308 return rc;
4309
4310 /* Enable access to flash interface */
4311 bnx2_enable_nvram_access(bp);
4312
4313 /* Reconfigure the flash interface */
4314 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4315 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4316 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4317 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4318
4319 /* Disable access to flash interface */
4320 bnx2_disable_nvram_access(bp);
4321 bnx2_release_nvram_lock(bp);
4322
4323 break;
4324 }
4325 }
4326 } /* if (val & 0x40000000) */
4327
4328 if (j == entry_count) {
4329 bp->flash_info = NULL;
3a9c6a49 4330 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4331 return -ENODEV;
b6016b76
MC		 4332 }
4333
e30372c9 4334get_flash_size:
2726d6e1 4335 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4336 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4337 if (val)
4338 bp->flash_size = val;
4339 else
4340 bp->flash_size = bp->flash_info->total_size;
4341
b6016b76
MC		 4342 return rc;
4343}
4344
4345static int
4346bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4347 int buf_size)
4348{
4349 int rc = 0;
4350 u32 cmd_flags, offset32, len32, extra;
4351
4352 if (buf_size == 0)
4353 return 0;
4354
4355 /* Request access to the flash interface. */
4356 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4357 return rc;
4358
4359 /* Enable access to flash interface */
4360 bnx2_enable_nvram_access(bp);
4361
4362 len32 = buf_size;
4363 offset32 = offset;
4364 extra = 0;
4365
4366 cmd_flags = 0;
4367
4368 if (offset32 & 3) {
4369 u8 buf[4];
4370 u32 pre_len;
4371
4372 offset32 &= ~3;
4373 pre_len = 4 - (offset & 3);
4374
4375 if (pre_len >= len32) {
4376 pre_len = len32;
4377 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4378 BNX2_NVM_COMMAND_LAST;
4379 }
4380 else {
4381 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4382 }
4383
4384 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4385
4386 if (rc)
4387 return rc;
4388
4389 memcpy(ret_buf, buf + (offset & 3), pre_len);
4390
4391 offset32 += 4;
4392 ret_buf += pre_len;
4393 len32 -= pre_len;
4394 }
4395 if (len32 & 3) {
4396 extra = 4 - (len32 & 3);
4397 len32 = (len32 + 4) & ~3;
4398 }
4399
4400 if (len32 == 4) {
4401 u8 buf[4];
4402
4403 if (cmd_flags)
4404 cmd_flags = BNX2_NVM_COMMAND_LAST;
4405 else
4406 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4407 BNX2_NVM_COMMAND_LAST;
4408
4409 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4410
4411 memcpy(ret_buf, buf, 4 - extra);
4412 }
4413 else if (len32 > 0) {
4414 u8 buf[4];
4415
4416 /* Read the first word. */
4417 if (cmd_flags)
4418 cmd_flags = 0;
4419 else
4420 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4421
4422 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4423
4424 /* Advance to the next dword. */
4425 offset32 += 4;
4426 ret_buf += 4;
4427 len32 -= 4;
4428
4429 while (len32 > 4 && rc == 0) {
4430 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4431
4432 /* Advance to the next dword. */
4433 offset32 += 4;
4434 ret_buf += 4;
4435 len32 -= 4;
4436 }
4437
4438 if (rc)
4439 return rc;
4440
4441 cmd_flags = BNX2_NVM_COMMAND_LAST;
4442 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4443
4444 memcpy(ret_buf, buf, 4 - extra);
4445 }
4446
4447 /* Disable access to flash interface */
4448 bnx2_disable_nvram_access(bp);
4449
4450 bnx2_release_nvram_lock(bp);
4451
4452 return rc;
4453}
4454
4455static int
4456bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4457 int buf_size)
4458{
4459 u32 written, offset32, len32;
e6be763f 4460 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4461 int rc = 0;
4462 int align_start, align_end;
4463
4464 buf = data_buf;
4465 offset32 = offset;
4466 len32 = buf_size;
4467 align_start = align_end = 0;
4468
4469 if ((align_start = (offset32 & 3))) {
4470 offset32 &= ~3;
c873879c
MC		 4471 len32 += align_start;
4472 if (len32 < 4)
4473 len32 = 4;
b6016b76
MC		 4474 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4475 return rc;
4476 }
4477
4478 if (len32 & 3) {
c873879c
MC		 4479 align_end = 4 - (len32 & 3);
4480 len32 += align_end;
4481 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4482 return rc;
b6016b76
MC		 4483 }
4484
4485 if (align_start || align_end) {
e6be763f
MC		 4486 align_buf = kmalloc(len32, GFP_KERNEL);
4487 if (align_buf == NULL)
b6016b76
MC		 4488 return -ENOMEM;
4489 if (align_start) {
e6be763f 4490 memcpy(align_buf, start, 4);
b6016b76
MC		 4491 }
4492 if (align_end) {
e6be763f 4493 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4494 }
e6be763f
MC		 4495 memcpy(align_buf + align_start, data_buf, buf_size);
4496 buf = align_buf;
b6016b76
MC		 4497 }
4498
e30372c9 4499 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4500 flash_buffer = kmalloc(264, GFP_KERNEL);
4501 if (flash_buffer == NULL) {
4502 rc = -ENOMEM;
4503 goto nvram_write_end;
4504 }
4505 }
4506
b6016b76
MC		 4507 written = 0;
4508 while ((written < len32) && (rc == 0)) {
4509 u32 page_start, page_end, data_start, data_end;
4510 u32 addr, cmd_flags;
4511 int i;
b6016b76
MC		 4512
4513 /* Find the page_start addr */
4514 page_start = offset32 + written;
4515 page_start -= (page_start % bp->flash_info->page_size);
4516 /* Find the page_end addr */
4517 page_end = page_start + bp->flash_info->page_size;
4518 /* Find the data_start addr */
4519 data_start = (written == 0) ? offset32 : page_start;
4520 /* Find the data_end addr */
6aa20a22 4521 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4522 (offset32 + len32) : page_end;
4523
4524 /* Request access to the flash interface. */
4525 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4526 goto nvram_write_end;
4527
4528 /* Enable access to flash interface */
4529 bnx2_enable_nvram_access(bp);
4530
4531 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4532 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4533 int j;
4534
4535 /* Read the whole page into the buffer
4536 * (non-buffer flash only) */
4537 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4538 if (j == (bp->flash_info->page_size - 4)) {
4539 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4540 }
4541 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4542 page_start + j,
4543 &flash_buffer[j],
b6016b76
MC		 4544 cmd_flags);
4545
4546 if (rc)
4547 goto nvram_write_end;
4548
4549 cmd_flags = 0;
4550 }
4551 }
4552
4553 /* Enable writes to flash interface (unlock write-protect) */
4554 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4555 goto nvram_write_end;
4556
b6016b76
MC		 4557 /* Loop to write back the buffer data from page_start to
4558 * data_start */
4559 i = 0;
e30372c9 4560 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4561 /* Erase the page */
4562 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4563 goto nvram_write_end;
4564
4565 /* Re-enable the write again for the actual write */
4566 bnx2_enable_nvram_write(bp);
4567
b6016b76
MC		 4568 for (addr = page_start; addr < data_start;
4569 addr += 4, i += 4) {
6aa20a22 4570
b6016b76
MC		 4571 rc = bnx2_nvram_write_dword(bp, addr,
4572 &flash_buffer[i], cmd_flags);
4573
4574 if (rc != 0)
4575 goto nvram_write_end;
4576
4577 cmd_flags = 0;
4578 }
4579 }
4580
4581 /* Loop to write the new data from data_start to data_end */
bae25761 4582 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4583 if ((addr == page_end - 4) ||
e30372c9 4584 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4585 (addr == data_end - 4))) {
4586
4587 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4588 }
4589 rc = bnx2_nvram_write_dword(bp, addr, buf,
4590 cmd_flags);
4591
4592 if (rc != 0)
4593 goto nvram_write_end;
4594
4595 cmd_flags = 0;
4596 buf += 4;
4597 }
4598
4599 /* Loop to write back the buffer data from data_end
4600 * to page_end */
e30372c9 4601 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4602 for (addr = data_end; addr < page_end;
4603 addr += 4, i += 4) {
6aa20a22 4604
b6016b76
MC		 4605 if (addr == page_end-4) {
4606 cmd_flags = BNX2_NVM_COMMAND_LAST;
4607 }
4608 rc = bnx2_nvram_write_dword(bp, addr,
4609 &flash_buffer[i], cmd_flags);
4610
4611 if (rc != 0)
4612 goto nvram_write_end;
4613
4614 cmd_flags = 0;
4615 }
4616 }
4617
4618 /* Disable writes to flash interface (lock write-protect) */
4619 bnx2_disable_nvram_write(bp);
4620
4621 /* Disable access to flash interface */
4622 bnx2_disable_nvram_access(bp);
4623 bnx2_release_nvram_lock(bp);
4624
4625 /* Increment written */
4626 written += data_end - data_start;
4627 }
4628
4629nvram_write_end:
e6be763f
MC		 4630 kfree(flash_buffer);
4631 kfree(align_buf);
b6016b76
MC		 4632 return rc;
4633}
4634
0d8a6571 4635static void
7c62e83b 4636bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4637{
7c62e83b 4638 u32 val, sig = 0;
0d8a6571 4639
583c28e5 4640 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4641 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4642
4643 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4644 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4645
2726d6e1 4646 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4647 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4648 return;
4649
7c62e83b
MC		 4650 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4651 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4652 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4653 }
4654
4655 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4656 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4657 u32 link;
4658
583c28e5 4659 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4660
7c62e83b
MC		 4661 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4662 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4663 bp->phy_port = PORT_FIBRE;
4664 else
4665 bp->phy_port = PORT_TP;
489310a4 4666
7c62e83b
MC		 4667 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4668 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4669 }
7c62e83b
MC		 4670
4671 if (netif_running(bp->dev) && sig)
4672 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4673}
4674
b4b36042
MC		 4675static void
4676bnx2_setup_msix_tbl(struct bnx2 *bp)
4677{
4678 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4679
4680 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4681 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4682}
4683
b6016b76
MC		 4684static int
4685bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4686{
4687 u32 val;
4688 int i, rc = 0;
489310a4 4689 u8 old_port;
b6016b76
MC		 4690
4691 /* Wait for the current PCI transaction to complete before
4692 * issuing a reset. */
4693 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4694 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4695 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4696 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4697 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4698 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4699 udelay(5);
4700
b090ae2b 4701 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4702 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4703
b6016b76
MC		 4704 /* Deposit a driver reset signature so the firmware knows that
4705 * this is a soft reset. */
2726d6e1
MC		 4706 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4707 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4708
b6016b76
MC		 4709 /* Do a dummy read to force the chip to complete all current transaction
4710 * before we issue a reset. */
4711 val = REG_RD(bp, BNX2_MISC_ID);
4712
234754d5
MC		 4713 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4714 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4715 REG_RD(bp, BNX2_MISC_COMMAND);
4716 udelay(5);
b6016b76 4717
234754d5
MC		 4718 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4719 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4720
234754d5 4721 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4722
234754d5
MC		 4723 } else {
4724 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4725 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4726 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4727
4728 /* Chip reset. */
4729 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4730
594a9dfa
MC		 4731 /* Reading back any register after chip reset will hang the
4732 * bus on 5706 A0 and A1. The msleep below provides plenty
4733 * of margin for write posting.
4734 */
234754d5 4735 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4736 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4737 msleep(20);
b6016b76 4738
234754d5
MC		 4739 /* Reset takes approximate 30 usec */
4740 for (i = 0; i < 10; i++) {
4741 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4742 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4743 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4744 break;
4745 udelay(10);
4746 }
4747
4748 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4749 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4750 pr_err("Chip reset did not complete\n");
234754d5
MC		 4751 return -EBUSY;
4752 }
b6016b76
MC		 4753 }
4754
4755 /* Make sure byte swapping is properly configured. */
4756 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4757 if (val != 0x01020304) {
3a9c6a49 4758 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4759 return -ENODEV;
4760 }
4761
b6016b76 4762 /* Wait for the firmware to finish its initialization. */
a2f13890 4763 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4764 if (rc)
4765 return rc;
b6016b76 4766
0d8a6571 4767 spin_lock_bh(&bp->phy_lock);
489310a4 4768 old_port = bp->phy_port;
7c62e83b 4769 bnx2_init_fw_cap(bp);
583c28e5
MC		 4770 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4771 old_port != bp->phy_port)
0d8a6571
MC		 4772 bnx2_set_default_remote_link(bp);
4773 spin_unlock_bh(&bp->phy_lock);
4774
b6016b76
MC		 4775 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4776 /* Adjust the voltage regular to two steps lower. The default
4777 * of this register is 0x0000000e. */
4778 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4779
4780 /* Remove bad rbuf memory from the free pool. */
4781 rc = bnx2_alloc_bad_rbuf(bp);
4782 }
4783
c441b8d2 4784 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4785 bnx2_setup_msix_tbl(bp);
c441b8d2
MC		 4786 /* Prevent MSIX table reads and write from timing out */
4787 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4788 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4789 }
b4b36042 4790
b6016b76
MC		 4791 return rc;
4792}
4793
4794static int
4795bnx2_init_chip(struct bnx2 *bp)
4796{
d8026d93 4797 u32 val, mtu;
b4b36042 4798 int rc, i;
b6016b76
MC		 4799
4800 /* Make sure the interrupt is not active. */
4801 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4802
4803 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4804 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4805#ifdef __BIG_ENDIAN
6aa20a22 4806 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4807#endif
6aa20a22 4808 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4809 DMA_READ_CHANS << 12 |
4810 DMA_WRITE_CHANS << 16;
4811
4812 val |= (0x2 << 20) | (1 << 11);
4813
f86e82fb 4814 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4815 val |= (1 << 23);
4816
4817 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4818 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4819 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4820
4821 REG_WR(bp, BNX2_DMA_CONFIG, val);
4822
4823 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4824 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4825 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4826 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4827 }
4828
f86e82fb 4829 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4830 u16 val16;
4831
4832 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4833 &val16);
4834 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4835 val16 & ~PCI_X_CMD_ERO);
4836 }
4837
4838 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4839 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4840 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4841 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4842
4843 /* Initialize context mapping and zero out the quick contexts. The
4844 * context block must have already been enabled. */
641bdcd5
MC		 4845 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4846 rc = bnx2_init_5709_context(bp);
4847 if (rc)
4848 return rc;
4849 } else
59b47d8a 4850 bnx2_init_context(bp);
b6016b76 4851
fba9fe91
MC		 4852 if ((rc = bnx2_init_cpus(bp)) != 0)
4853 return rc;
4854
b6016b76
MC		 4855 bnx2_init_nvram(bp);
4856
5fcaed01 4857 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4858
4859 val = REG_RD(bp, BNX2_MQ_CONFIG);
4860 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4861 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4edd473f
MC		 4862 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4863 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4864 if (CHIP_REV(bp) == CHIP_REV_Ax)
4865 val |= BNX2_MQ_CONFIG_HALT_DIS;
4866 }
68c9f75a 4867
b6016b76
MC		 4868 REG_WR(bp, BNX2_MQ_CONFIG, val);
4869
4870 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4871 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4872 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4873
4874 val = (BCM_PAGE_BITS - 8) << 24;
4875 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4876
4877 /* Configure page size. */
4878 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4879 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4880 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4881 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4882
4883 val = bp->mac_addr[0] +
4884 (bp->mac_addr[1] << 8) +
4885 (bp->mac_addr[2] << 16) +
4886 bp->mac_addr[3] +
4887 (bp->mac_addr[4] << 8) +
4888 (bp->mac_addr[5] << 16);
4889 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4890
4891 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4892 mtu = bp->dev->mtu;
4893 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4894 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4895 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4896 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4897
d8026d93
MC		 4898 if (mtu < 1500)
4899 mtu = 1500;
4900
4901 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4902 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4903 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4904
155d5561 4905 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4906 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4907 bp->bnx2_napi[i].last_status_idx = 0;
4908
efba0180
MC		 4909 bp->idle_chk_status_idx = 0xffff;
4910
b6016b76
MC		 4911 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4912
4913 /* Set up how to generate a link change interrupt. */
4914 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4915
4916 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4917 (u64) bp->status_blk_mapping & 0xffffffff);
4918 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4919
4920 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4921 (u64) bp->stats_blk_mapping & 0xffffffff);
4922 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4923 (u64) bp->stats_blk_mapping >> 32);
4924
6aa20a22 4925 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4926 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4927
4928 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4929 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4930
4931 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4932 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4933
4934 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4935
4936 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4937
4938 REG_WR(bp, BNX2_HC_COM_TICKS,
4939 (bp->com_ticks_int << 16) | bp->com_ticks);
4940
4941 REG_WR(bp, BNX2_HC_CMD_TICKS,
4942 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4943
61d9e3fa 4944 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
02537b06
MC		 4945 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4946 else
7ea6920e 4947 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4948 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4949
4950 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4951 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4952 else {
8e6a72c4
MC		 4953 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4954 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4955 }
4956
efde73a3 4957 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4958 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4959 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4960
5e9ad9e1
MC		 4961 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4962 }
4963
4964 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 4965 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1
MC		 4966
4967 REG_WR(bp, BNX2_HC_CONFIG, val);
4968
4969 for (i = 1; i < bp->irq_nvecs; i++) {
4970 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4971 BNX2_HC_SB_CONFIG_1;
4972
6f743ca0 4973 REG_WR(bp, base,
c76c0475 4974 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 4975 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 4976 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4977
6f743ca0 4978 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4979 (bp->tx_quick_cons_trip_int << 16) |
4980 bp->tx_quick_cons_trip);
4981
6f743ca0 4982 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4983 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4984
5e9ad9e1
MC		 4985 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4986 (bp->rx_quick_cons_trip_int << 16) |
4987 bp->rx_quick_cons_trip);
8e6a72c4 4988
5e9ad9e1
MC		 4989 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4990 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4991 }
8e6a72c4 4992
b6016b76
MC		 4993 /* Clear internal stats counters. */
4994 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4995
da3e4fbe 4996 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4997
4998 /* Initialize the receive filter. */
4999 bnx2_set_rx_mode(bp->dev);
5000
0aa38df7
MC		 5001 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5002 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5003 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5004 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5005 }
b090ae2b 5006 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5007 1, 0);
b6016b76 5008
df149d70 5009 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 5010 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5011
5012 udelay(20);
5013
bf5295bb
MC		 5014 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5015
b090ae2b 5016 return rc;
b6016b76
MC		 5017}
5018
c76c0475
MC		 5019static void
5020bnx2_clear_ring_states(struct bnx2 *bp)
5021{
5022 struct bnx2_napi *bnapi;
35e9010b 5023 struct bnx2_tx_ring_info *txr;
bb4f98ab 5024 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5025 int i;
5026
5027 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5028 bnapi = &bp->bnx2_napi[i];
35e9010b 5029 txr = &bnapi->tx_ring;
bb4f98ab 5030 rxr = &bnapi->rx_ring;
c76c0475 5031
35e9010b
MC		 5032 txr->tx_cons = 0;
5033 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5034 rxr->rx_prod_bseq = 0;
5035 rxr->rx_prod = 0;
5036 rxr->rx_cons = 0;
5037 rxr->rx_pg_prod = 0;
5038 rxr->rx_pg_cons = 0;
c76c0475
MC		 5039 }
5040}
5041
59b47d8a 5042static void
35e9010b 5043bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5044{
5045 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5046 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 5047
5048 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5049 offset0 = BNX2_L2CTX_TYPE_XI;
5050 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5051 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5052 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5053 } else {
5054 offset0 = BNX2_L2CTX_TYPE;
5055 offset1 = BNX2_L2CTX_CMD_TYPE;
5056 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5057 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5058 }
5059 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5060 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5061
5062 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5063 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5064
35e9010b 5065 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5066 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5067
35e9010b 5068 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5069 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5070}
b6016b76
MC		 5071
5072static void
35e9010b 5073bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 5074{
5075 struct tx_bd *txbd;
c76c0475
MC		 5076 u32 cid = TX_CID;
5077 struct bnx2_napi *bnapi;
35e9010b 5078 struct bnx2_tx_ring_info *txr;
c76c0475 5079
35e9010b
MC		 5080 bnapi = &bp->bnx2_napi[ring_num];
5081 txr = &bnapi->tx_ring;
5082
5083 if (ring_num == 0)
5084 cid = TX_CID;
5085 else
5086 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5087
2f8af120
MC		 5088 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5089
35e9010b 5090 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 5091
35e9010b
MC		 5092 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5093 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5094
35e9010b
MC		 5095 txr->tx_prod = 0;
5096 txr->tx_prod_bseq = 0;
6aa20a22 5097
35e9010b
MC		 5098 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5099 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5100
35e9010b 5101 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5102}
5103
5104static void
5d5d0015
MC		 5105bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5106 int num_rings)
b6016b76 5107{
b6016b76 5108 int i;
5d5d0015 5109 struct rx_bd *rxbd;
6aa20a22 5110
5d5d0015 5111 for (i = 0; i < num_rings; i++) {
13daffa2 5112 int j;
b6016b76 5113
5d5d0015 5114 rxbd = &rx_ring[i][0];
13daffa2 5115 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5116 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5117 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5118 }
5d5d0015 5119 if (i == (num_rings - 1))
13daffa2
MC		 5120 j = 0;
5121 else
5122 j = i + 1;
5d5d0015
MC		 5123 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5124 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5125 }
5d5d0015
MC		 5126}
5127
5128static void
bb4f98ab 5129bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5130{
5131 int i;
5132 u16 prod, ring_prod;
bb4f98ab
MC		 5133 u32 cid, rx_cid_addr, val;
5134 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5135 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5136
5137 if (ring_num == 0)
5138 cid = RX_CID;
5139 else
5140 cid = RX_RSS_CID + ring_num - 1;
5141
5142 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5143
bb4f98ab 5144 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5145 bp->rx_buf_use_size, bp->rx_max_ring);
5146
bb4f98ab 5147 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 5148
5149 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5150 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5151 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5152 }
5153
62a8313c 5154 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5155 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5156 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5157 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5158 PAGE_SIZE, bp->rx_max_pg_ring);
5159 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5160 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5161 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5162 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5163
bb4f98ab 5164 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5165 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5166
bb4f98ab 5167 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5168 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 5169
5170 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5171 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5172 }
b6016b76 5173
bb4f98ab 5174 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5175 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5176
bb4f98ab 5177 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5178 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5179
bb4f98ab 5180 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5181 for (i = 0; i < bp->rx_pg_ring_size; i++) {
b929e53c 5182 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
3a9c6a49
JP		 5183 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5184 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5185 break;
b929e53c 5186 }
47bf4246
MC		 5187 prod = NEXT_RX_BD(prod);
5188 ring_prod = RX_PG_RING_IDX(prod);
5189 }
bb4f98ab 5190 rxr->rx_pg_prod = prod;
47bf4246 5191
bb4f98ab 5192 ring_prod = prod = rxr->rx_prod;
236b6394 5193 for (i = 0; i < bp->rx_ring_size; i++) {
b929e53c 5194 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
3a9c6a49
JP		 5195 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5196 ring_num, i, bp->rx_ring_size);
b6016b76 5197 break;
b929e53c 5198 }
b6016b76
MC		 5199 prod = NEXT_RX_BD(prod);
5200 ring_prod = RX_RING_IDX(prod);
5201 }
bb4f98ab 5202 rxr->rx_prod = prod;
b6016b76 5203
bb4f98ab
MC		 5204 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5205 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5206 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5207
bb4f98ab
MC		 5208 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5209 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5210
5211 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5212}
5213
35e9010b
MC		 5214static void
5215bnx2_init_all_rings(struct bnx2 *bp)
5216{
5217 int i;
5e9ad9e1 5218 u32 val;
35e9010b
MC		 5219
5220 bnx2_clear_ring_states(bp);
5221
5222 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5223 for (i = 0; i < bp->num_tx_rings; i++)
5224 bnx2_init_tx_ring(bp, i);
5225
5226 if (bp->num_tx_rings > 1)
5227 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5228 (TX_TSS_CID << 7));
5229
5e9ad9e1
MC		 5230 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5231 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5232
bb4f98ab
MC		 5233 for (i = 0; i < bp->num_rx_rings; i++)
5234 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5235
5236 if (bp->num_rx_rings > 1) {
5237 u32 tbl_32;
5238 u8 *tbl = (u8 *) &tbl_32;
5239
5240 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5241 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5242
5243 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5244 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5245 if ((i % 4) == 3)
5246 bnx2_reg_wr_ind(bp,
5247 BNX2_RXP_SCRATCH_RSS_TBL + i,
5248 cpu_to_be32(tbl_32));
5249 }
5250
5251 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5252 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5253
5254 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5255
5256 }
35e9010b
MC		 5257}
5258
5d5d0015 5259static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5260{
5d5d0015 5261 u32 max, num_rings = 1;
13daffa2 5262
5d5d0015
MC		 5263 while (ring_size > MAX_RX_DESC_CNT) {
5264 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 5265 num_rings++;
5266 }
5267 /* round to next power of 2 */
5d5d0015 5268 max = max_size;
13daffa2
MC		 5269 while ((max & num_rings) == 0)
5270 max >>= 1;
5271
5272 if (num_rings != max)
5273 max <<= 1;
5274
5d5d0015
MC		 5275 return max;
5276}
5277
5278static void
5279bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5280{
84eaa187 5281 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5282
5283 /* 8 for CRC and VLAN */
d89cb6af 5284 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5285
84eaa187
MC		 5286 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5287 sizeof(struct skb_shared_info);
5288
601d3d18 5289 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5290 bp->rx_pg_ring_size = 0;
5291 bp->rx_max_pg_ring = 0;
5292 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5293 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5294 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5295
5296 jumbo_size = size * pages;
5297 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5298 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5299
5300 bp->rx_pg_ring_size = jumbo_size;
5301 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5302 MAX_RX_PG_RINGS);
5303 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 5304 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5305 bp->rx_copy_thresh = 0;
5306 }
5d5d0015
MC		 5307
5308 bp->rx_buf_use_size = rx_size;
5309 /* hw alignment */
5310 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 5311 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 5312 bp->rx_ring_size = size;
5313 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 5314 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5315}
5316
b6016b76
MC		 5317static void
5318bnx2_free_tx_skbs(struct bnx2 *bp)
5319{
5320 int i;
5321
35e9010b
MC		 5322 for (i = 0; i < bp->num_tx_rings; i++) {
5323 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5324 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5325 int j;
b6016b76 5326
35e9010b 5327 if (txr->tx_buf_ring == NULL)
b6016b76 5328 continue;
b6016b76 5329
35e9010b 5330 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5331 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5332 struct sk_buff *skb = tx_buf->skb;
e95524a7 5333 int k, last;
35e9010b
MC		 5334
5335 if (skb == NULL) {
5336 j++;
5337 continue;
5338 }
5339
e95524a7 5340 pci_unmap_single(bp->pdev,
1a4ccc2d 5341 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5342 skb_headlen(skb),
5343 PCI_DMA_TODEVICE);
b6016b76 5344
35e9010b 5345 tx_buf->skb = NULL;
b6016b76 5346
e95524a7
AD		 5347 last = tx_buf->nr_frags;
5348 j++;
5349 for (k = 0; k < last; k++, j++) {
5350 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5351 pci_unmap_page(bp->pdev,
1a4ccc2d 5352 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5353 skb_shinfo(skb)->frags[k].size,
5354 PCI_DMA_TODEVICE);
5355 }
35e9010b 5356 dev_kfree_skb(skb);
b6016b76 5357 }
b6016b76 5358 }
b6016b76
MC		 5359}
5360
5361static void
5362bnx2_free_rx_skbs(struct bnx2 *bp)
5363{
5364 int i;
5365
bb4f98ab
MC		 5366 for (i = 0; i < bp->num_rx_rings; i++) {
5367 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5368 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5369 int j;
b6016b76 5370
bb4f98ab
MC		 5371 if (rxr->rx_buf_ring == NULL)
5372 return;
b6016b76 5373
bb4f98ab
MC		 5374 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5375 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5376 struct sk_buff *skb = rx_buf->skb;
b6016b76 5377
bb4f98ab
MC		 5378 if (skb == NULL)
5379 continue;
b6016b76 5380
bb4f98ab 5381 pci_unmap_single(bp->pdev,
1a4ccc2d 5382 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5383 bp->rx_buf_use_size,
5384 PCI_DMA_FROMDEVICE);
b6016b76 5385
bb4f98ab
MC		 5386 rx_buf->skb = NULL;
5387
5388 dev_kfree_skb(skb);
5389 }
5390 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5391 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5392 }
5393}
5394
5395static void
5396bnx2_free_skbs(struct bnx2 *bp)
5397{
5398 bnx2_free_tx_skbs(bp);
5399 bnx2_free_rx_skbs(bp);
5400}
5401
5402static int
5403bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5404{
5405 int rc;
5406
5407 rc = bnx2_reset_chip(bp, reset_code);
5408 bnx2_free_skbs(bp);
5409 if (rc)
5410 return rc;
5411
fba9fe91
MC		 5412 if ((rc = bnx2_init_chip(bp)) != 0)
5413 return rc;
5414
35e9010b 5415 bnx2_init_all_rings(bp);
b6016b76
MC		 5416 return 0;
5417}
5418
5419static int
9a120bc5 5420bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5421{
5422 int rc;
5423
5424 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5425 return rc;
5426
80be4434 5427 spin_lock_bh(&bp->phy_lock);
9a120bc5 5428 bnx2_init_phy(bp, reset_phy);
b6016b76 5429 bnx2_set_link(bp);
543a827d
MC		 5430 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5431 bnx2_remote_phy_event(bp);
0d8a6571 5432 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5433 return 0;
5434}
5435
74bf4ba3
MC		 5436static int
5437bnx2_shutdown_chip(struct bnx2 *bp)
5438{
5439 u32 reset_code;
5440
5441 if (bp->flags & BNX2_FLAG_NO_WOL)
5442 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5443 else if (bp->wol)
5444 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5445 else
5446 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5447
5448 return bnx2_reset_chip(bp, reset_code);
5449}
5450
b6016b76
MC		 5451static int
5452bnx2_test_registers(struct bnx2 *bp)
5453{
5454 int ret;
5bae30c9 5455 int i, is_5709;
f71e1309 5456 static const struct {
b6016b76
MC		 5457 u16 offset;
5458 u16 flags;
5bae30c9 5459#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5460 u32 rw_mask;
5461 u32 ro_mask;
5462 } reg_tbl[] = {
5463 { 0x006c, 0, 0x00000000, 0x0000003f },
5464 { 0x0090, 0, 0xffffffff, 0x00000000 },
5465 { 0x0094, 0, 0x00000000, 0x00000000 },
5466
5bae30c9
MC		 5467 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5468 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5469 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5470 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5471 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5472 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5473 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5474 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5475 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5476
5477 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5478 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5479 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5480 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5481 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5482 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5483
5484 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5485 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5486 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5487
5488 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5489 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5490
5491 { 0x1408, 0, 0x01c00800, 0x00000000 },
5492 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5493 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5494 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5495 { 0x14b0, 0, 0x00000002, 0x00000001 },
5496 { 0x14b8, 0, 0x00000000, 0x00000000 },
5497 { 0x14c0, 0, 0x00000000, 0x00000009 },
5498 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5499 { 0x14cc, 0, 0x00000000, 0x00000001 },
5500 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5501
5502 { 0x1800, 0, 0x00000000, 0x00000001 },
5503 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5504
5505 { 0x2800, 0, 0x00000000, 0x00000001 },
5506 { 0x2804, 0, 0x00000000, 0x00003f01 },
5507 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5508 { 0x2810, 0, 0xffff0000, 0x00000000 },
5509 { 0x2814, 0, 0xffff0000, 0x00000000 },
5510 { 0x2818, 0, 0xffff0000, 0x00000000 },
5511 { 0x281c, 0, 0xffff0000, 0x00000000 },
5512 { 0x2834, 0, 0xffffffff, 0x00000000 },
5513 { 0x2840, 0, 0x00000000, 0xffffffff },
5514 { 0x2844, 0, 0x00000000, 0xffffffff },
5515 { 0x2848, 0, 0xffffffff, 0x00000000 },
5516 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5517
5518 { 0x2c00, 0, 0x00000000, 0x00000011 },
5519 { 0x2c04, 0, 0x00000000, 0x00030007 },
5520
b6016b76
MC		 5521 { 0x3c00, 0, 0x00000000, 0x00000001 },
5522 { 0x3c04, 0, 0x00000000, 0x00070000 },
5523 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5524 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5525 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5526 { 0x3c14, 0, 0x00000000, 0xffffffff },
5527 { 0x3c18, 0, 0x00000000, 0xffffffff },
5528 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5529 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5530
5531 { 0x5004, 0, 0x00000000, 0x0000007f },
5532 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5533
b6016b76
MC		 5534 { 0x5c00, 0, 0x00000000, 0x00000001 },
5535 { 0x5c04, 0, 0x00000000, 0x0003000f },
5536 { 0x5c08, 0, 0x00000003, 0x00000000 },
5537 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5538 { 0x5c10, 0, 0x00000000, 0xffffffff },
5539 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5540 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5541 { 0x5c88, 0, 0x00000000, 0x00077373 },
5542 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5543
5544 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5545 { 0x680c, 0, 0xffffffff, 0x00000000 },
5546 { 0x6810, 0, 0xffffffff, 0x00000000 },
5547 { 0x6814, 0, 0xffffffff, 0x00000000 },
5548 { 0x6818, 0, 0xffffffff, 0x00000000 },
5549 { 0x681c, 0, 0xffffffff, 0x00000000 },
5550 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5551 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5552 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5553 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5554 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5555 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5556 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5557 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5558 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5559 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5560 { 0x684c, 0, 0xffffffff, 0x00000000 },
5561 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5562 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5563 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5564 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5565 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5566 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5567
5568 { 0xffff, 0, 0x00000000, 0x00000000 },
5569 };
5570
5571 ret = 0;
5bae30c9
MC		 5572 is_5709 = 0;
5573 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5574 is_5709 = 1;
5575
b6016b76
MC		 5576 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5577 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5578 u16 flags = reg_tbl[i].flags;
5579
5580 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5581 continue;
b6016b76
MC		 5582
5583 offset = (u32) reg_tbl[i].offset;
5584 rw_mask = reg_tbl[i].rw_mask;
5585 ro_mask = reg_tbl[i].ro_mask;
5586
14ab9b86 5587 save_val = readl(bp->regview + offset);
b6016b76 5588
14ab9b86 5589 writel(0, bp->regview + offset);
b6016b76 5590
14ab9b86 5591 val = readl(bp->regview + offset);
b6016b76
MC		 5592 if ((val & rw_mask) != 0) {
5593 goto reg_test_err;
5594 }
5595
5596 if ((val & ro_mask) != (save_val & ro_mask)) {
5597 goto reg_test_err;
5598 }
5599
14ab9b86 5600 writel(0xffffffff, bp->regview + offset);
b6016b76 5601
14ab9b86 5602 val = readl(bp->regview + offset);
b6016b76
MC		 5603 if ((val & rw_mask) != rw_mask) {
5604 goto reg_test_err;
5605 }
5606
5607 if ((val & ro_mask) != (save_val & ro_mask)) {
5608 goto reg_test_err;
5609 }
5610
14ab9b86 5611 writel(save_val, bp->regview + offset);
b6016b76
MC		 5612 continue;
5613
5614reg_test_err:
14ab9b86 5615 writel(save_val, bp->regview + offset);
b6016b76
MC		 5616 ret = -ENODEV;
5617 break;
5618 }
5619 return ret;
5620}
5621
5622static int
5623bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5624{
f71e1309 5625 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5626 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5627 int i;
5628
5629 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5630 u32 offset;
5631
5632 for (offset = 0; offset < size; offset += 4) {
5633
2726d6e1 5634 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5635
2726d6e1 5636 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5637 test_pattern[i]) {
5638 return -ENODEV;
5639 }
5640 }
5641 }
5642 return 0;
5643}
5644
5645static int
5646bnx2_test_memory(struct bnx2 *bp)
5647{
5648 int ret = 0;
5649 int i;
5bae30c9 5650 static struct mem_entry {
b6016b76
MC		 5651 u32 offset;
5652 u32 len;
5bae30c9 5653 } mem_tbl_5706[] = {
b6016b76 5654 { 0x60000, 0x4000 },
5b0c76ad 5655 { 0xa0000, 0x3000 },
b6016b76
MC		 5656 { 0xe0000, 0x4000 },
5657 { 0x120000, 0x4000 },
5658 { 0x1a0000, 0x4000 },
5659 { 0x160000, 0x4000 },
5660 { 0xffffffff, 0 },
5bae30c9
MC		 5661 },
5662 mem_tbl_5709[] = {
5663 { 0x60000, 0x4000 },
5664 { 0xa0000, 0x3000 },
5665 { 0xe0000, 0x4000 },
5666 { 0x120000, 0x4000 },
5667 { 0x1a0000, 0x4000 },
5668 { 0xffffffff, 0 },
b6016b76 5669 };
5bae30c9
MC		 5670 struct mem_entry *mem_tbl;
5671
5672 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5673 mem_tbl = mem_tbl_5709;
5674 else
5675 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5676
5677 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5678 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5679 mem_tbl[i].len)) != 0) {
5680 return ret;
5681 }
5682 }
6aa20a22 5683
b6016b76
MC		 5684 return ret;
5685}
5686
bc5a0690
MC		 5687#define BNX2_MAC_LOOPBACK 0
5688#define BNX2_PHY_LOOPBACK 1
5689
b6016b76 5690static int
bc5a0690 5691bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5692{
5693 unsigned int pkt_size, num_pkts, i;
5694 struct sk_buff *skb, *rx_skb;
5695 unsigned char *packet;
bc5a0690 5696 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5697 dma_addr_t map;
5698 struct tx_bd *txbd;
5699 struct sw_bd *rx_buf;
5700 struct l2_fhdr *rx_hdr;
5701 int ret = -ENODEV;
c76c0475 5702 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5703 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5704 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5705
5706 tx_napi = bnapi;
b6016b76 5707
35e9010b 5708 txr = &tx_napi->tx_ring;
bb4f98ab 5709 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5710 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5711 bp->loopback = MAC_LOOPBACK;
5712 bnx2_set_mac_loopback(bp);
5713 }
5714 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5715 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5716 return 0;
5717
80be4434 5718 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5719 bnx2_set_phy_loopback(bp);
5720 }
5721 else
5722 return -EINVAL;
b6016b76 5723
84eaa187 5724 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5725 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5726 if (!skb)
5727 return -ENOMEM;
b6016b76 5728 packet = skb_put(skb, pkt_size);
6634292b 5729 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5730 memset(packet + 6, 0x0, 8);
5731 for (i = 14; i < pkt_size; i++)
5732 packet[i] = (unsigned char) (i & 0xff);
5733
e95524a7
AD		 5734 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5735 PCI_DMA_TODEVICE);
5736 if (pci_dma_mapping_error(bp->pdev, map)) {
3d16af86
BL		 5737 dev_kfree_skb(skb);
5738 return -EIO;
5739 }
b6016b76 5740
bf5295bb
MC		 5741 REG_WR(bp, BNX2_HC_COMMAND,
5742 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5743
b6016b76
MC		 5744 REG_RD(bp, BNX2_HC_COMMAND);
5745
5746 udelay(5);
35efa7c1 5747 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5748
b6016b76
MC		 5749 num_pkts = 0;
5750
35e9010b 5751 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5752
5753 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5754 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5755 txbd->tx_bd_mss_nbytes = pkt_size;
5756 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5757
5758 num_pkts++;
35e9010b
MC		 5759 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5760 txr->tx_prod_bseq += pkt_size;
b6016b76 5761
35e9010b
MC		 5762 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5763 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5764
5765 udelay(100);
5766
bf5295bb
MC		 5767 REG_WR(bp, BNX2_HC_COMMAND,
5768 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5769
b6016b76
MC		 5770 REG_RD(bp, BNX2_HC_COMMAND);
5771
5772 udelay(5);
5773
e95524a7 5774 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5775 dev_kfree_skb(skb);
b6016b76 5776
35e9010b 5777 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5778 goto loopback_test_done;
b6016b76 5779
35efa7c1 5780 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5781 if (rx_idx != rx_start_idx + num_pkts) {
5782 goto loopback_test_done;
5783 }
5784
bb4f98ab 5785 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
b6016b76
MC		 5786 rx_skb = rx_buf->skb;
5787
a33fa66b 5788 rx_hdr = rx_buf->desc;
d89cb6af 5789 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76
MC		 5790
5791 pci_dma_sync_single_for_cpu(bp->pdev,
1a4ccc2d 5792 dma_unmap_addr(rx_buf, mapping),
b6016b76
MC		 5793 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5794
ade2bfe7 5795 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5796 (L2_FHDR_ERRORS_BAD_CRC |
5797 L2_FHDR_ERRORS_PHY_DECODE |
5798 L2_FHDR_ERRORS_ALIGNMENT |
5799 L2_FHDR_ERRORS_TOO_SHORT |
5800 L2_FHDR_ERRORS_GIANT_FRAME)) {
5801
5802 goto loopback_test_done;
5803 }
5804
5805 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5806 goto loopback_test_done;
5807 }
5808
5809 for (i = 14; i < pkt_size; i++) {
5810 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5811 goto loopback_test_done;
5812 }
5813 }
5814
5815 ret = 0;
5816
5817loopback_test_done:
5818 bp->loopback = 0;
5819 return ret;
5820}
5821
bc5a0690
MC		 5822#define BNX2_MAC_LOOPBACK_FAILED 1
5823#define BNX2_PHY_LOOPBACK_FAILED 2
5824#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5825 BNX2_PHY_LOOPBACK_FAILED)
5826
5827static int
5828bnx2_test_loopback(struct bnx2 *bp)
5829{
5830 int rc = 0;
5831
5832 if (!netif_running(bp->dev))
5833 return BNX2_LOOPBACK_FAILED;
5834
5835 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5836 spin_lock_bh(&bp->phy_lock);
9a120bc5 5837 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5838 spin_unlock_bh(&bp->phy_lock);
5839 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5840 rc |= BNX2_MAC_LOOPBACK_FAILED;
5841 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5842 rc |= BNX2_PHY_LOOPBACK_FAILED;
5843 return rc;
5844}
5845
b6016b76
MC		 5846#define NVRAM_SIZE 0x200
5847#define CRC32_RESIDUAL 0xdebb20e3
5848
5849static int
5850bnx2_test_nvram(struct bnx2 *bp)
5851{
b491edd5 5852 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5853 u8 *data = (u8 *) buf;
5854 int rc = 0;
5855 u32 magic, csum;
5856
5857 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5858 goto test_nvram_done;
5859
5860 magic = be32_to_cpu(buf[0]);
5861 if (magic != 0x669955aa) {
5862 rc = -ENODEV;
5863 goto test_nvram_done;
5864 }
5865
5866 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5867 goto test_nvram_done;
5868
5869 csum = ether_crc_le(0x100, data);
5870 if (csum != CRC32_RESIDUAL) {
5871 rc = -ENODEV;
5872 goto test_nvram_done;
5873 }
5874
5875 csum = ether_crc_le(0x100, data + 0x100);
5876 if (csum != CRC32_RESIDUAL) {
5877 rc = -ENODEV;
5878 }
5879
5880test_nvram_done:
5881 return rc;
5882}
5883
5884static int
5885bnx2_test_link(struct bnx2 *bp)
5886{
5887 u32 bmsr;
5888
9f52b564
MC		 5889 if (!netif_running(bp->dev))
5890 return -ENODEV;
5891
583c28e5 5892 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5893 if (bp->link_up)
5894 return 0;
5895 return -ENODEV;
5896 }
c770a65c 5897 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5898 bnx2_enable_bmsr1(bp);
5899 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5900 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5901 bnx2_disable_bmsr1(bp);
c770a65c 5902 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5903
b6016b76
MC		 5904 if (bmsr & BMSR_LSTATUS) {
5905 return 0;
5906 }
5907 return -ENODEV;
5908}
5909
5910static int
5911bnx2_test_intr(struct bnx2 *bp)
5912{
5913 int i;
b6016b76
MC		 5914 u16 status_idx;
5915
5916 if (!netif_running(bp->dev))
5917 return -ENODEV;
5918
5919 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5920
5921 /* This register is not touched during run-time. */
bf5295bb 5922 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5923 REG_RD(bp, BNX2_HC_COMMAND);
5924
5925 for (i = 0; i < 10; i++) {
5926 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5927 status_idx) {
5928
5929 break;
5930 }
5931
5932 msleep_interruptible(10);
5933 }
5934 if (i < 10)
5935 return 0;
5936
5937 return -ENODEV;
5938}
5939
38ea3686 5940/* Determining link for parallel detection. */
b2fadeae
MC		 5941static int
5942bnx2_5706_serdes_has_link(struct bnx2 *bp)
5943{
5944 u32 mode_ctl, an_dbg, exp;
5945
38ea3686
MC		 5946 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5947 return 0;
5948
b2fadeae
MC		 5949 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5950 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5951
5952 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5953 return 0;
5954
5955 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5956 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5957 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5958
f3014c0c 5959 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5960 return 0;
5961
5962 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5963 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5964 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5965
5966 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5967 return 0;
5968
5969 return 1;
5970}
5971
b6016b76 5972static void
48b01e2d 5973bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5974{
b2fadeae
MC		 5975 int check_link = 1;
5976
48b01e2d 5977 spin_lock(&bp->phy_lock);
b2fadeae 5978 if (bp->serdes_an_pending) {
48b01e2d 5979 bp->serdes_an_pending--;
b2fadeae
MC		 5980 check_link = 0;
5981 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5982 u32 bmcr;
b6016b76 5983
ac392abc 5984 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 5985
ca58c3af 5986 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5987
48b01e2d 5988 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5989 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5990 bmcr &= ~BMCR_ANENABLE;
5991 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5992 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5993 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5994 }
b6016b76 5995 }
48b01e2d
MC		 5996 }
5997 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5998 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5999 u32 phy2;
b6016b76 6000
48b01e2d
MC		 6001 bnx2_write_phy(bp, 0x17, 0x0f01);
6002 bnx2_read_phy(bp, 0x15, &phy2);
6003 if (phy2 & 0x20) {
6004 u32 bmcr;
cd339a0e 6005
ca58c3af 6006 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6007 bmcr |= BMCR_ANENABLE;
ca58c3af 6008 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6009
583c28e5 6010 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6011 }
6012 } else
ac392abc 6013 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6014
a2724e25 6015 if (check_link) {
b2fadeae
MC		 6016 u32 val;
6017
6018 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6019 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6020 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6021
a2724e25
MC		 6022 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6023 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6024 bnx2_5706s_force_link_dn(bp, 1);
6025 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6026 } else
6027 bnx2_set_link(bp);
6028 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6029 bnx2_set_link(bp);
b2fadeae 6030 }
48b01e2d
MC		 6031 spin_unlock(&bp->phy_lock);
6032}
b6016b76 6033
f8dd064e
MC		 6034static void
6035bnx2_5708_serdes_timer(struct bnx2 *bp)
6036{
583c28e5 6037 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6038 return;
6039
583c28e5 6040 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6041 bp->serdes_an_pending = 0;
6042 return;
6043 }
b6016b76 6044
f8dd064e
MC		 6045 spin_lock(&bp->phy_lock);
6046 if (bp->serdes_an_pending)
6047 bp->serdes_an_pending--;
6048 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6049 u32 bmcr;
b6016b76 6050
ca58c3af 6051 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6052 if (bmcr & BMCR_ANENABLE) {
605a9e20 6053 bnx2_enable_forced_2g5(bp);
40105c0b 6054 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6055 } else {
605a9e20 6056 bnx2_disable_forced_2g5(bp);
f8dd064e 6057 bp->serdes_an_pending = 2;
ac392abc 6058 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6059 }
b6016b76 6060
f8dd064e 6061 } else
ac392abc 6062 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6063
f8dd064e
MC		 6064 spin_unlock(&bp->phy_lock);
6065}
6066
48b01e2d
MC		 6067static void
6068bnx2_timer(unsigned long data)
6069{
6070 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6071
48b01e2d
MC		 6072 if (!netif_running(bp->dev))
6073 return;
b6016b76 6074
48b01e2d
MC		 6075 if (atomic_read(&bp->intr_sem) != 0)
6076 goto bnx2_restart_timer;
b6016b76 6077
efba0180
MC		 6078 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6079 BNX2_FLAG_USING_MSI)
6080 bnx2_chk_missed_msi(bp);
6081
df149d70 6082 bnx2_send_heart_beat(bp);
b6016b76 6083
2726d6e1
MC		 6084 bp->stats_blk->stat_FwRxDrop =
6085 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6086
02537b06 6087 /* workaround occasional corrupted counters */
61d9e3fa 6088 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
02537b06
MC		 6089 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6090 BNX2_HC_COMMAND_STATS_NOW);
6091
583c28e5 6092 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 6093 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6094 bnx2_5706_serdes_timer(bp);
27a005b8 6095 else
f8dd064e 6096 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6097 }
6098
6099bnx2_restart_timer:
cd339a0e 6100 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6101}
6102
8e6a72c4
MC		 6103static int
6104bnx2_request_irq(struct bnx2 *bp)
6105{
6d866ffc 6106 unsigned long flags;
b4b36042
MC		 6107 struct bnx2_irq *irq;
6108 int rc = 0, i;
8e6a72c4 6109
f86e82fb 6110 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6111 flags = 0;
6112 else
6113 flags = IRQF_SHARED;
b4b36042
MC		 6114
6115 for (i = 0; i < bp->irq_nvecs; i++) {
6116 irq = &bp->irq_tbl[i];
c76c0475 6117 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6118 &bp->bnx2_napi[i]);
b4b36042
MC		 6119 if (rc)
6120 break;
6121 irq->requested = 1;
6122 }
8e6a72c4
MC		 6123 return rc;
6124}
6125
6126static void
6127bnx2_free_irq(struct bnx2 *bp)
6128{
b4b36042
MC		 6129 struct bnx2_irq *irq;
6130 int i;
8e6a72c4 6131
b4b36042
MC		 6132 for (i = 0; i < bp->irq_nvecs; i++) {
6133 irq = &bp->irq_tbl[i];
6134 if (irq->requested)
f0ea2e63 6135 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6136 irq->requested = 0;
6d866ffc 6137 }
f86e82fb 6138 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6139 pci_disable_msi(bp->pdev);
f86e82fb 6140 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6141 pci_disable_msix(bp->pdev);
6142
f86e82fb 6143 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6144}
6145
6146static void
5e9ad9e1 6147bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6148{
57851d84
MC		 6149 int i, rc;
6150 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6151 struct net_device *dev = bp->dev;
6152 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6153
b4b36042
MC		 6154 bnx2_setup_msix_tbl(bp);
6155 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6156 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6157 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6158
e2eb8e38
BL		 6159 /* Need to flush the previous three writes to ensure MSI-X
6160 * is setup properly */
6161 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6162
57851d84
MC		 6163 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6164 msix_ent[i].entry = i;
6165 msix_ent[i].vector = 0;
6166 }
6167
6168 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6169 if (rc != 0)
6170 return;
6171
5e9ad9e1 6172 bp->irq_nvecs = msix_vecs;
f86e82fb 6173 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
69010313 6174 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
57851d84 6175 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6176 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6177 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6178 }
6d866ffc
MC		 6179}
6180
6181static void
6182bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6183{
5e9ad9e1 6184 int cpus = num_online_cpus();
706bf240 6185 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 6186
6d866ffc
MC		 6187 bp->irq_tbl[0].handler = bnx2_interrupt;
6188 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6189 bp->irq_nvecs = 1;
6190 bp->irq_tbl[0].vector = bp->pdev->irq;
6191
3d5f3a7b 6192 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6193 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6194
f86e82fb
DM		 6195 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6196 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6197 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6198 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 6199 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 6200 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6201 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6202 } else
6203 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6204
6205 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6206 }
6207 }
706bf240
BL		 6208
6209 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6210 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6211
5e9ad9e1 6212 bp->num_rx_rings = bp->irq_nvecs;
8e6a72c4
MC		 6213}
6214
b6016b76
MC		 6215/* Called with rtnl_lock */
6216static int
6217bnx2_open(struct net_device *dev)
6218{
972ec0d4 6219 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6220 int rc;
6221
1b2f922f
MC		 6222 netif_carrier_off(dev);
6223
829ca9a3 6224 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 6225 bnx2_disable_int(bp);
6226
35e9010b 6227 bnx2_setup_int_mode(bp, disable_msi);
4327ba43 6228 bnx2_init_napi(bp);
35e9010b 6229 bnx2_napi_enable(bp);
b6016b76 6230 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6231 if (rc)
6232 goto open_err;
b6016b76 6233
8e6a72c4 6234 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6235 if (rc)
6236 goto open_err;
b6016b76 6237
9a120bc5 6238 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6239 if (rc)
6240 goto open_err;
6aa20a22 6241
cd339a0e 6242 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6243
6244 atomic_set(&bp->intr_sem, 0);
6245
354fcd77
MC		 6246 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6247
b6016b76
MC		 6248 bnx2_enable_int(bp);
6249
f86e82fb 6250 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6251 /* Test MSI to make sure it is working
6252 * If MSI test fails, go back to INTx mode
6253 */
6254 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6255 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6256
6257 bnx2_disable_int(bp);
8e6a72c4 6258 bnx2_free_irq(bp);
b6016b76 6259
6d866ffc
MC		 6260 bnx2_setup_int_mode(bp, 1);
6261
9a120bc5 6262 rc = bnx2_init_nic(bp, 0);
b6016b76 6263
8e6a72c4
MC		 6264 if (!rc)
6265 rc = bnx2_request_irq(bp);
6266
b6016b76 6267 if (rc) {
b6016b76 6268 del_timer_sync(&bp->timer);
2739a8bb 6269 goto open_err;
b6016b76
MC		 6270 }
6271 bnx2_enable_int(bp);
6272 }
6273 }
f86e82fb 6274 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6275 netdev_info(dev, "using MSI\n");
f86e82fb 6276 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6277 netdev_info(dev, "using MSIX\n");
b6016b76 6278
706bf240 6279 netif_tx_start_all_queues(dev);
b6016b76
MC		 6280
6281 return 0;
2739a8bb
MC		 6282
6283open_err:
6284 bnx2_napi_disable(bp);
6285 bnx2_free_skbs(bp);
6286 bnx2_free_irq(bp);
6287 bnx2_free_mem(bp);
f048fa9c 6288 bnx2_del_napi(bp);
2739a8bb 6289 return rc;
b6016b76
MC		 6290}
6291
6292static void
c4028958 6293bnx2_reset_task(struct work_struct *work)
b6016b76 6294{
c4028958 6295 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 6296
51bf6bb4
MC		 6297 rtnl_lock();
6298 if (!netif_running(bp->dev)) {
6299 rtnl_unlock();
afdc08b9 6300 return;
51bf6bb4 6301 }
afdc08b9 6302
212f9934 6303 bnx2_netif_stop(bp, true);
b6016b76 6304
9a120bc5 6305 bnx2_init_nic(bp, 1);
b6016b76
MC		 6306
6307 atomic_set(&bp->intr_sem, 1);
212f9934 6308 bnx2_netif_start(bp, true);
51bf6bb4 6309 rtnl_unlock();
b6016b76
MC		 6310}
6311
20175c57
MC		 6312static void
6313bnx2_dump_state(struct bnx2 *bp)
6314{
6315 struct net_device *dev = bp->dev;
5804a8fb
MC		 6316 u32 mcp_p0, mcp_p1, val1, val2;
6317
6318 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6319 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6320 atomic_read(&bp->intr_sem), val1);
6321 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6322 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6323 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6324 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
3a9c6a49 6325 REG_RD(bp, BNX2_EMAC_TX_STATUS),
b98eba52
EW		 6326 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6327 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
3a9c6a49 6328 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
b98eba52
EW		 6329 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6330 mcp_p0 = BNX2_MCP_STATE_P0;
6331 mcp_p1 = BNX2_MCP_STATE_P1;
6332 } else {
6333 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6334 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6335 }
3a9c6a49 6336 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
b98eba52 6337 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
3a9c6a49
JP		 6338 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6339 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6340 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49
JP		 6341 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6342 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6343}
6344
b6016b76
MC		 6345static void
6346bnx2_tx_timeout(struct net_device *dev)
6347{
972ec0d4 6348 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6349
20175c57
MC		 6350 bnx2_dump_state(bp);
6351
b6016b76
MC		 6352 /* This allows the netif to be shutdown gracefully before resetting */
6353 schedule_work(&bp->reset_task);
6354}
6355
6356#ifdef BCM_VLAN
6357/* Called with rtnl_lock */
6358static void
6359bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6360{
972ec0d4 6361 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6362
3767546c 6363 if (netif_running(dev))
212f9934 6364 bnx2_netif_stop(bp, false);
b6016b76
MC		 6365
6366 bp->vlgrp = vlgrp;
3767546c
MC		 6367
6368 if (!netif_running(dev))
6369 return;
6370
b6016b76 6371 bnx2_set_rx_mode(dev);
7c62e83b
MC		 6372 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6373 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
b6016b76 6374
212f9934 6375 bnx2_netif_start(bp, false);
b6016b76 6376}
b6016b76
MC		 6377#endif
6378
932ff279 6379/* Called with netif_tx_lock.
2f8af120
MC		 6380 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6381 * netif_wake_queue().
b6016b76 6382 */
61357325 6383static netdev_tx_t
b6016b76
MC		 6384bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6385{
972ec0d4 6386 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6387 dma_addr_t mapping;
6388 struct tx_bd *txbd;
3d16af86 6389 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6390 u32 len, vlan_tag_flags, last_frag, mss;
6391 u16 prod, ring_prod;
6392 int i;
706bf240
BL		 6393 struct bnx2_napi *bnapi;
6394 struct bnx2_tx_ring_info *txr;
6395 struct netdev_queue *txq;
6396
6397 /* Determine which tx ring we will be placed on */
6398 i = skb_get_queue_mapping(skb);
6399 bnapi = &bp->bnx2_napi[i];
6400 txr = &bnapi->tx_ring;
6401 txq = netdev_get_tx_queue(dev, i);
b6016b76 6402
35e9010b 6403 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6404 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6405 netif_tx_stop_queue(txq);
3a9c6a49 6406 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6407
6408 return NETDEV_TX_BUSY;
6409 }
6410 len = skb_headlen(skb);
35e9010b 6411 prod = txr->tx_prod;
b6016b76
MC		 6412 ring_prod = TX_RING_IDX(prod);
6413
6414 vlan_tag_flags = 0;
84fa7933 6415 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6416 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6417 }
6418
729b85cd 6419#ifdef BCM_VLAN
79ea13ce 6420 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 6421 vlan_tag_flags |=
6422 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6423 }
729b85cd 6424#endif
fde82055 6425 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6426 u32 tcp_opt_len;
eddc9ec5 6427 struct iphdr *iph;
b6016b76 6428
b6016b76
MC		 6429 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6430
4666f87a
MC		 6431 tcp_opt_len = tcp_optlen(skb);
6432
6433 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6434 u32 tcp_off = skb_transport_offset(skb) -
6435 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6436
4666f87a
MC		 6437 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6438 TX_BD_FLAGS_SW_FLAGS;
6439 if (likely(tcp_off == 0))
6440 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6441 else {
6442 tcp_off >>= 3;
6443 vlan_tag_flags |= ((tcp_off & 0x3) <<
6444 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6445 ((tcp_off & 0x10) <<
6446 TX_BD_FLAGS_TCP6_OFF4_SHL);
6447 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6448 }
6449 } else {
4666f87a 6450 iph = ip_hdr(skb);
4666f87a
MC		 6451 if (tcp_opt_len || (iph->ihl > 5)) {
6452 vlan_tag_flags |= ((iph->ihl - 5) +
6453 (tcp_opt_len >> 2)) << 8;
6454 }
b6016b76 6455 }
4666f87a 6456 } else
b6016b76 6457 mss = 0;
b6016b76 6458
e95524a7
AD		 6459 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6460 if (pci_dma_mapping_error(bp->pdev, mapping)) {
3d16af86
BL		 6461 dev_kfree_skb(skb);
6462 return NETDEV_TX_OK;
6463 }
6464
35e9010b 6465 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6466 tx_buf->skb = skb;
1a4ccc2d 6467 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6468
35e9010b 6469 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6470
6471 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6472 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6473 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6474 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6475
6476 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6477 tx_buf->nr_frags = last_frag;
6478 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6479
6480 for (i = 0; i < last_frag; i++) {
6481 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6482
6483 prod = NEXT_TX_BD(prod);
6484 ring_prod = TX_RING_IDX(prod);
35e9010b 6485 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6486
6487 len = frag->size;
e95524a7
AD		 6488 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6489 len, PCI_DMA_TODEVICE);
6490 if (pci_dma_mapping_error(bp->pdev, mapping))
6491 goto dma_error;
1a4ccc2d 6492 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6493 mapping);
b6016b76
MC		 6494
6495 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6496 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6497 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6498 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6499
6500 }
6501 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6502
6503 prod = NEXT_TX_BD(prod);
35e9010b 6504 txr->tx_prod_bseq += skb->len;
b6016b76 6505
35e9010b
MC		 6506 REG_WR16(bp, txr->tx_bidx_addr, prod);
6507 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6508
6509 mmiowb();
6510
35e9010b 6511 txr->tx_prod = prod;
b6016b76 6512
35e9010b 6513 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6514 netif_tx_stop_queue(txq);
35e9010b 6515 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6516 netif_tx_wake_queue(txq);
b6016b76
MC		 6517 }
6518
e95524a7
AD		 6519 return NETDEV_TX_OK;
6520dma_error:
6521 /* save value of frag that failed */
6522 last_frag = i;
6523
6524 /* start back at beginning and unmap skb */
6525 prod = txr->tx_prod;
6526 ring_prod = TX_RING_IDX(prod);
6527 tx_buf = &txr->tx_buf_ring[ring_prod];
6528 tx_buf->skb = NULL;
1a4ccc2d 6529 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6530 skb_headlen(skb), PCI_DMA_TODEVICE);
6531
6532 /* unmap remaining mapped pages */
6533 for (i = 0; i < last_frag; i++) {
6534 prod = NEXT_TX_BD(prod);
6535 ring_prod = TX_RING_IDX(prod);
6536 tx_buf = &txr->tx_buf_ring[ring_prod];
1a4ccc2d 6537 pci_unmap_page(bp->pdev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6538 skb_shinfo(skb)->frags[i].size,
6539 PCI_DMA_TODEVICE);
6540 }
6541
6542 dev_kfree_skb(skb);
b6016b76
MC		 6543 return NETDEV_TX_OK;
6544}
6545
6546/* Called with rtnl_lock */
6547static int
6548bnx2_close(struct net_device *dev)
6549{
972ec0d4 6550 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6551
4bb073c0 6552 cancel_work_sync(&bp->reset_task);
afdc08b9 6553
bea3348e 6554 bnx2_disable_int_sync(bp);
35efa7c1 6555 bnx2_napi_disable(bp);
b6016b76 6556 del_timer_sync(&bp->timer);
74bf4ba3 6557 bnx2_shutdown_chip(bp);
8e6a72c4 6558 bnx2_free_irq(bp);
b6016b76
MC		 6559 bnx2_free_skbs(bp);
6560 bnx2_free_mem(bp);
f048fa9c 6561 bnx2_del_napi(bp);
b6016b76
MC		 6562 bp->link_up = 0;
6563 netif_carrier_off(bp->dev);
829ca9a3 6564 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6565 return 0;
6566}
6567
354fcd77
MC		 6568static void
6569bnx2_save_stats(struct bnx2 *bp)
6570{
6571 u32 *hw_stats = (u32 *) bp->stats_blk;
6572 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6573 int i;
6574
6575 /* The 1st 10 counters are 64-bit counters */
6576 for (i = 0; i < 20; i += 2) {
6577 u32 hi;
6578 u64 lo;
6579
c9885fe5
PR		 6580 hi = temp_stats[i] + hw_stats[i];
6581 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6582 if (lo > 0xffffffff)
6583 hi++;
c9885fe5
PR		 6584 temp_stats[i] = hi;
6585 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6586 }
6587
6588 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6589 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6590}
6591
5d07bf26
ED		 6592#define GET_64BIT_NET_STATS64(ctr) \
6593 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6594
a4743058 6595#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6596 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6597 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6598
a4743058 6599#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6600 (unsigned long) (bp->stats_blk->ctr + \
6601 bp->temp_stats_blk->ctr)
a4743058 6602
5d07bf26
ED		 6603static struct rtnl_link_stats64 *
6604bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6605{
972ec0d4 6606 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6607
5d07bf26 6608 if (bp->stats_blk == NULL)
b6016b76 6609 return net_stats;
5d07bf26 6610
b6016b76 6611 net_stats->rx_packets =
a4743058
MC		 6612 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6613 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6614 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6615
6616 net_stats->tx_packets =
a4743058
MC		 6617 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6618 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6619 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6620
6621 net_stats->rx_bytes =
a4743058 6622 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6623
6624 net_stats->tx_bytes =
a4743058 6625 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6626
6aa20a22 6627 net_stats->multicast =
a4743058 6628 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts);
b6016b76 6629
6aa20a22 6630 net_stats->collisions =
a4743058 6631 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6632
6aa20a22 6633 net_stats->rx_length_errors =
a4743058
MC		 6634 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6635 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6636
6aa20a22 6637 net_stats->rx_over_errors =
a4743058
MC		 6638 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6639 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6640
6aa20a22 6641 net_stats->rx_frame_errors =
a4743058 6642 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6643
6aa20a22 6644 net_stats->rx_crc_errors =
a4743058 6645 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6646
6647 net_stats->rx_errors = net_stats->rx_length_errors +
6648 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6649 net_stats->rx_crc_errors;
6650
6651 net_stats->tx_aborted_errors =
a4743058
MC		 6652 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6653 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6654
5b0c76ad
MC		 6655 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6656 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6657 net_stats->tx_carrier_errors = 0;
6658 else {
6659 net_stats->tx_carrier_errors =
a4743058 6660 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6661 }
6662
6663 net_stats->tx_errors =
a4743058 6664 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6665 net_stats->tx_aborted_errors +
6666 net_stats->tx_carrier_errors;
6667
cea94db9 6668 net_stats->rx_missed_errors =
a4743058
MC		 6669 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6670 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6671 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6672
b6016b76
MC		 6673 return net_stats;
6674}
6675
6676/* All ethtool functions called with rtnl_lock */
6677
6678static int
6679bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6680{
972ec0d4 6681 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6682 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6683
6684 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6685 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6686 support_serdes = 1;
6687 support_copper = 1;
6688 } else if (bp->phy_port == PORT_FIBRE)
6689 support_serdes = 1;
6690 else
6691 support_copper = 1;
6692
6693 if (support_serdes) {
b6016b76
MC		 6694 cmd->supported |= SUPPORTED_1000baseT_Full |
6695 SUPPORTED_FIBRE;
583c28e5 6696 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6697 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6698
b6016b76 6699 }
7b6b8347 6700 if (support_copper) {
b6016b76
MC		 6701 cmd->supported |= SUPPORTED_10baseT_Half |
6702 SUPPORTED_10baseT_Full |
6703 SUPPORTED_100baseT_Half |
6704 SUPPORTED_100baseT_Full |
6705 SUPPORTED_1000baseT_Full |
6706 SUPPORTED_TP;
6707
b6016b76
MC		 6708 }
6709
7b6b8347
MC		 6710 spin_lock_bh(&bp->phy_lock);
6711 cmd->port = bp->phy_port;
b6016b76
MC		 6712 cmd->advertising = bp->advertising;
6713
6714 if (bp->autoneg & AUTONEG_SPEED) {
6715 cmd->autoneg = AUTONEG_ENABLE;
6716 }
6717 else {
6718 cmd->autoneg = AUTONEG_DISABLE;
6719 }
6720
6721 if (netif_carrier_ok(dev)) {
6722 cmd->speed = bp->line_speed;
6723 cmd->duplex = bp->duplex;
6724 }
6725 else {
6726 cmd->speed = -1;
6727 cmd->duplex = -1;
6728 }
7b6b8347 6729 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6730
6731 cmd->transceiver = XCVR_INTERNAL;
6732 cmd->phy_address = bp->phy_addr;
6733
6734 return 0;
6735}
6aa20a22 6736
b6016b76
MC		 6737static int
6738bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6739{
972ec0d4 6740 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6741 u8 autoneg = bp->autoneg;
6742 u8 req_duplex = bp->req_duplex;
6743 u16 req_line_speed = bp->req_line_speed;
6744 u32 advertising = bp->advertising;
7b6b8347
MC		 6745 int err = -EINVAL;
6746
6747 spin_lock_bh(&bp->phy_lock);
6748
6749 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6750 goto err_out_unlock;
6751
583c28e5
MC		 6752 if (cmd->port != bp->phy_port &&
6753 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6754 goto err_out_unlock;
b6016b76 6755
d6b14486
MC		 6756 /* If device is down, we can store the settings only if the user
6757 * is setting the currently active port.
6758 */
6759 if (!netif_running(dev) && cmd->port != bp->phy_port)
6760 goto err_out_unlock;
6761
b6016b76
MC		 6762 if (cmd->autoneg == AUTONEG_ENABLE) {
6763 autoneg |= AUTONEG_SPEED;
6764
beb499af
MC		 6765 advertising = cmd->advertising;
6766 if (cmd->port == PORT_TP) {
6767 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6768 if (!advertising)
b6016b76 6769 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6770 } else {
6771 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6772 if (!advertising)
6773 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6774 }
6775 advertising |= ADVERTISED_Autoneg;
6776 }
6777 else {
7b6b8347 6778 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6779 if ((cmd->speed != SPEED_1000 &&
6780 cmd->speed != SPEED_2500) ||
6781 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6782 goto err_out_unlock;
80be4434
MC		 6783
6784 if (cmd->speed == SPEED_2500 &&
583c28e5 6785 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6786 goto err_out_unlock;
b6016b76 6787 }
7b6b8347
MC		 6788 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6789 goto err_out_unlock;
6790
b6016b76
MC		 6791 autoneg &= ~AUTONEG_SPEED;
6792 req_line_speed = cmd->speed;
6793 req_duplex = cmd->duplex;
6794 advertising = 0;
6795 }
6796
6797 bp->autoneg = autoneg;
6798 bp->advertising = advertising;
6799 bp->req_line_speed = req_line_speed;
6800 bp->req_duplex = req_duplex;
6801
d6b14486
MC		 6802 err = 0;
6803 /* If device is down, the new settings will be picked up when it is
6804 * brought up.
6805 */
6806 if (netif_running(dev))
6807 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6808
7b6b8347 6809err_out_unlock:
c770a65c 6810 spin_unlock_bh(&bp->phy_lock);
b6016b76 6811
7b6b8347 6812 return err;
b6016b76
MC		 6813}
6814
6815static void
6816bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6817{
972ec0d4 6818 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6819
6820 strcpy(info->driver, DRV_MODULE_NAME);
6821 strcpy(info->version, DRV_MODULE_VERSION);
6822 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6823 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6824}
6825
244ac4f4
MC		 6826#define BNX2_REGDUMP_LEN (32 * 1024)
6827
6828static int
6829bnx2_get_regs_len(struct net_device *dev)
6830{
6831 return BNX2_REGDUMP_LEN;
6832}
6833
6834static void
6835bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6836{
6837 u32 *p = _p, i, offset;
6838 u8 *orig_p = _p;
6839 struct bnx2 *bp = netdev_priv(dev);
6840 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6841 0x0800, 0x0880, 0x0c00, 0x0c10,
6842 0x0c30, 0x0d08, 0x1000, 0x101c,
6843 0x1040, 0x1048, 0x1080, 0x10a4,
6844 0x1400, 0x1490, 0x1498, 0x14f0,
6845 0x1500, 0x155c, 0x1580, 0x15dc,
6846 0x1600, 0x1658, 0x1680, 0x16d8,
6847 0x1800, 0x1820, 0x1840, 0x1854,
6848 0x1880, 0x1894, 0x1900, 0x1984,
6849 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6850 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6851 0x2000, 0x2030, 0x23c0, 0x2400,
6852 0x2800, 0x2820, 0x2830, 0x2850,
6853 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6854 0x3c00, 0x3c94, 0x4000, 0x4010,
6855 0x4080, 0x4090, 0x43c0, 0x4458,
6856 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6857 0x4fc0, 0x5010, 0x53c0, 0x5444,
6858 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6859 0x5fc0, 0x6000, 0x6400, 0x6428,
6860 0x6800, 0x6848, 0x684c, 0x6860,
6861 0x6888, 0x6910, 0x8000 };
6862
6863 regs->version = 0;
6864
6865 memset(p, 0, BNX2_REGDUMP_LEN);
6866
6867 if (!netif_running(bp->dev))
6868 return;
6869
6870 i = 0;
6871 offset = reg_boundaries[0];
6872 p += offset;
6873 while (offset < BNX2_REGDUMP_LEN) {
6874 *p++ = REG_RD(bp, offset);
6875 offset += 4;
6876 if (offset == reg_boundaries[i + 1]) {
6877 offset = reg_boundaries[i + 2];
6878 p = (u32 *) (orig_p + offset);
6879 i += 2;
6880 }
6881 }
6882}
6883
b6016b76
MC		 6884static void
6885bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6886{
972ec0d4 6887 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6888
f86e82fb 6889 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6890 wol->supported = 0;
6891 wol->wolopts = 0;
6892 }
6893 else {
6894 wol->supported = WAKE_MAGIC;
6895 if (bp->wol)
6896 wol->wolopts = WAKE_MAGIC;
6897 else
6898 wol->wolopts = 0;
6899 }
6900 memset(&wol->sopass, 0, sizeof(wol->sopass));
6901}
6902
6903static int
6904bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6905{
972ec0d4 6906 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6907
6908 if (wol->wolopts & ~WAKE_MAGIC)
6909 return -EINVAL;
6910
6911 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6912 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6913 return -EINVAL;
6914
6915 bp->wol = 1;
6916 }
6917 else {
6918 bp->wol = 0;
6919 }
6920 return 0;
6921}
6922
6923static int
6924bnx2_nway_reset(struct net_device *dev)
6925{
972ec0d4 6926 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6927 u32 bmcr;
6928
9f52b564
MC		 6929 if (!netif_running(dev))
6930 return -EAGAIN;
6931
b6016b76
MC		 6932 if (!(bp->autoneg & AUTONEG_SPEED)) {
6933 return -EINVAL;
6934 }
6935
c770a65c 6936 spin_lock_bh(&bp->phy_lock);
b6016b76 6937
583c28e5 6938 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6939 int rc;
6940
6941 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6942 spin_unlock_bh(&bp->phy_lock);
6943 return rc;
6944 }
6945
b6016b76 6946 /* Force a link down visible on the other side */
583c28e5 6947 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6948 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6949 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6950
6951 msleep(20);
6952
c770a65c 6953 spin_lock_bh(&bp->phy_lock);
f8dd064e 6954
40105c0b 6955 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 6956 bp->serdes_an_pending = 1;
6957 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6958 }
6959
ca58c3af 6960 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6961 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6962 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6963
c770a65c 6964 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6965
6966 return 0;
6967}
6968
7959ea25
ON		 6969static u32
6970bnx2_get_link(struct net_device *dev)
6971{
6972 struct bnx2 *bp = netdev_priv(dev);
6973
6974 return bp->link_up;
6975}
6976
b6016b76
MC		 6977static int
6978bnx2_get_eeprom_len(struct net_device *dev)
6979{
972ec0d4 6980 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6981
1122db71 6982 if (bp->flash_info == NULL)
b6016b76
MC		 6983 return 0;
6984
1122db71 6985 return (int) bp->flash_size;
b6016b76
MC		 6986}
6987
6988static int
6989bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6990 u8 *eebuf)
6991{
972ec0d4 6992 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6993 int rc;
6994
9f52b564
MC		 6995 if (!netif_running(dev))
6996 return -EAGAIN;
6997
1064e944 6998 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6999
7000 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7001
7002 return rc;
7003}
7004
7005static int
7006bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7007 u8 *eebuf)
7008{
972ec0d4 7009 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7010 int rc;
7011
9f52b564
MC		 7012 if (!netif_running(dev))
7013 return -EAGAIN;
7014
1064e944 7015 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7016
7017 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7018
7019 return rc;
7020}
7021
7022static int
7023bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7024{
972ec0d4 7025 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7026
7027 memset(coal, 0, sizeof(struct ethtool_coalesce));
7028
7029 coal->rx_coalesce_usecs = bp->rx_ticks;
7030 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7031 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7032 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7033
7034 coal->tx_coalesce_usecs = bp->tx_ticks;
7035 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7036 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7037 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7038
7039 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7040
7041 return 0;
7042}
7043
7044static int
7045bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7046{
972ec0d4 7047 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7048
7049 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7050 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7051
6aa20a22 7052 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7053 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7054
7055 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7056 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7057
7058 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7059 if (bp->rx_quick_cons_trip_int > 0xff)
7060 bp->rx_quick_cons_trip_int = 0xff;
7061
7062 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7063 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7064
7065 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7066 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7067
7068 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7069 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7070
7071 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7072 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7073 0xff;
7074
7075 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7076 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7077 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7078 bp->stats_ticks = USEC_PER_SEC;
7079 }
7ea6920e
MC		 7080 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7081 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7082 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7083
7084 if (netif_running(bp->dev)) {
212f9934 7085 bnx2_netif_stop(bp, true);
9a120bc5 7086 bnx2_init_nic(bp, 0);
212f9934 7087 bnx2_netif_start(bp, true);
b6016b76
MC		 7088 }
7089
7090 return 0;
7091}
7092
7093static void
7094bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7095{
972ec0d4 7096 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7097
13daffa2 7098 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 7099 ering->rx_mini_max_pending = 0;
47bf4246 7100 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7101
7102 ering->rx_pending = bp->rx_ring_size;
7103 ering->rx_mini_pending = 0;
47bf4246 7104 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 7105
7106 ering->tx_max_pending = MAX_TX_DESC_CNT;
7107 ering->tx_pending = bp->tx_ring_size;
7108}
7109
7110static int
5d5d0015 7111bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 7112{
13daffa2 7113 if (netif_running(bp->dev)) {
354fcd77
MC		 7114 /* Reset will erase chipset stats; save them */
7115 bnx2_save_stats(bp);
7116
212f9934 7117 bnx2_netif_stop(bp, true);
13daffa2
MC		 7118 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7119 bnx2_free_skbs(bp);
7120 bnx2_free_mem(bp);
7121 }
7122
5d5d0015
MC		 7123 bnx2_set_rx_ring_size(bp, rx);
7124 bp->tx_ring_size = tx;
b6016b76
MC		 7125
7126 if (netif_running(bp->dev)) {
13daffa2
MC		 7127 int rc;
7128
7129 rc = bnx2_alloc_mem(bp);
6fefb65e
MC		 7130 if (!rc)
7131 rc = bnx2_init_nic(bp, 0);
7132
7133 if (rc) {
7134 bnx2_napi_enable(bp);
7135 dev_close(bp->dev);
13daffa2 7136 return rc;
6fefb65e 7137 }
e9f26c49
MC		 7138#ifdef BCM_CNIC
7139 mutex_lock(&bp->cnic_lock);
7140 /* Let cnic know about the new status block. */
7141 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7142 bnx2_setup_cnic_irq_info(bp);
7143 mutex_unlock(&bp->cnic_lock);
7144#endif
212f9934 7145 bnx2_netif_start(bp, true);
b6016b76 7146 }
b6016b76
MC		 7147 return 0;
7148}
7149
5d5d0015
MC		 7150static int
7151bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7152{
7153 struct bnx2 *bp = netdev_priv(dev);
7154 int rc;
7155
7156 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7157 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7158 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7159
7160 return -EINVAL;
7161 }
7162 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7163 return rc;
7164}
7165
b6016b76
MC		 7166static void
7167bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7168{
972ec0d4 7169 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7170
7171 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7172 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7173 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7174}
7175
7176static int
7177bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7178{
972ec0d4 7179 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7180
7181 bp->req_flow_ctrl = 0;
7182 if (epause->rx_pause)
7183 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7184 if (epause->tx_pause)
7185 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7186
7187 if (epause->autoneg) {
7188 bp->autoneg |= AUTONEG_FLOW_CTRL;
7189 }
7190 else {
7191 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7192 }
7193
9f52b564
MC		 7194 if (netif_running(dev)) {
7195 spin_lock_bh(&bp->phy_lock);
7196 bnx2_setup_phy(bp, bp->phy_port);
7197 spin_unlock_bh(&bp->phy_lock);
7198 }
b6016b76
MC		 7199
7200 return 0;
7201}
7202
7203static u32
7204bnx2_get_rx_csum(struct net_device *dev)
7205{
972ec0d4 7206 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7207
7208 return bp->rx_csum;
7209}
7210
7211static int
7212bnx2_set_rx_csum(struct net_device *dev, u32 data)
7213{
972ec0d4 7214 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7215
7216 bp->rx_csum = data;
7217 return 0;
7218}
7219
b11d6213
MC		 7220static int
7221bnx2_set_tso(struct net_device *dev, u32 data)
7222{
4666f87a
MC		 7223 struct bnx2 *bp = netdev_priv(dev);
7224
7225 if (data) {
b11d6213 7226 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7227 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7228 dev->features |= NETIF_F_TSO6;
7229 } else
7230 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7231 NETIF_F_TSO_ECN);
b11d6213
MC		 7232 return 0;
7233}
7234
14ab9b86 7235static struct {
b6016b76 7236 char string[ETH_GSTRING_LEN];
790dab2f 7237} bnx2_stats_str_arr[] = {
b6016b76
MC		 7238 { "rx_bytes" },
7239 { "rx_error_bytes" },
7240 { "tx_bytes" },
7241 { "tx_error_bytes" },
7242 { "rx_ucast_packets" },
7243 { "rx_mcast_packets" },
7244 { "rx_bcast_packets" },
7245 { "tx_ucast_packets" },
7246 { "tx_mcast_packets" },
7247 { "tx_bcast_packets" },
7248 { "tx_mac_errors" },
7249 { "tx_carrier_errors" },
7250 { "rx_crc_errors" },
7251 { "rx_align_errors" },
7252 { "tx_single_collisions" },
7253 { "tx_multi_collisions" },
7254 { "tx_deferred" },
7255 { "tx_excess_collisions" },
7256 { "tx_late_collisions" },
7257 { "tx_total_collisions" },
7258 { "rx_fragments" },
7259 { "rx_jabbers" },
7260 { "rx_undersize_packets" },
7261 { "rx_oversize_packets" },
7262 { "rx_64_byte_packets" },
7263 { "rx_65_to_127_byte_packets" },
7264 { "rx_128_to_255_byte_packets" },
7265 { "rx_256_to_511_byte_packets" },
7266 { "rx_512_to_1023_byte_packets" },
7267 { "rx_1024_to_1522_byte_packets" },
7268 { "rx_1523_to_9022_byte_packets" },
7269 { "tx_64_byte_packets" },
7270 { "tx_65_to_127_byte_packets" },
7271 { "tx_128_to_255_byte_packets" },
7272 { "tx_256_to_511_byte_packets" },
7273 { "tx_512_to_1023_byte_packets" },
7274 { "tx_1024_to_1522_byte_packets" },
7275 { "tx_1523_to_9022_byte_packets" },
7276 { "rx_xon_frames" },
7277 { "rx_xoff_frames" },
7278 { "tx_xon_frames" },
7279 { "tx_xoff_frames" },
7280 { "rx_mac_ctrl_frames" },
7281 { "rx_filtered_packets" },
790dab2f 7282 { "rx_ftq_discards" },
b6016b76 7283 { "rx_discards" },
cea94db9 7284 { "rx_fw_discards" },
b6016b76
MC		 7285};
7286
790dab2f
MC		 7287#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7288 sizeof(bnx2_stats_str_arr[0]))
7289
b6016b76
MC		 7290#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7291
f71e1309 7292static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7293 STATS_OFFSET32(stat_IfHCInOctets_hi),
7294 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7295 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7296 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7297 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7298 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7299 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7300 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7301 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7302 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7303 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7304 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7305 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7306 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7307 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7308 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7309 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7310 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7311 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7312 STATS_OFFSET32(stat_EtherStatsCollisions),
7313 STATS_OFFSET32(stat_EtherStatsFragments),
7314 STATS_OFFSET32(stat_EtherStatsJabbers),
7315 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7316 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7317 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7318 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7319 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7320 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7321 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7322 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7323 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7324 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7325 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7326 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7327 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7328 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7329 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7330 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7331 STATS_OFFSET32(stat_XonPauseFramesReceived),
7332 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7333 STATS_OFFSET32(stat_OutXonSent),
7334 STATS_OFFSET32(stat_OutXoffSent),
7335 STATS_OFFSET32(stat_MacControlFramesReceived),
7336 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7337 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7338 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7339 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7340};
7341
7342/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7343 * skipped because of errata.
6aa20a22 7344 */
14ab9b86 7345static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7346 8,0,8,8,8,8,8,8,8,8,
7347 4,0,4,4,4,4,4,4,4,4,
7348 4,4,4,4,4,4,4,4,4,4,
7349 4,4,4,4,4,4,4,4,4,4,
790dab2f 7350 4,4,4,4,4,4,4,
b6016b76
MC		 7351};
7352
5b0c76ad
MC		 7353static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7354 8,0,8,8,8,8,8,8,8,8,
7355 4,4,4,4,4,4,4,4,4,4,
7356 4,4,4,4,4,4,4,4,4,4,
7357 4,4,4,4,4,4,4,4,4,4,
790dab2f 7358 4,4,4,4,4,4,4,
5b0c76ad
MC		 7359};
7360
b6016b76
MC		 7361#define BNX2_NUM_TESTS 6
7362
14ab9b86 7363static struct {
b6016b76
MC		 7364 char string[ETH_GSTRING_LEN];
7365} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7366 { "register_test (offline)" },
7367 { "memory_test (offline)" },
7368 { "loopback_test (offline)" },
7369 { "nvram_test (online)" },
7370 { "interrupt_test (online)" },
7371 { "link_test (online)" },
7372};
7373
7374static int
b9f2c044 7375bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7376{
b9f2c044
JG		 7377 switch (sset) {
7378 case ETH_SS_TEST:
7379 return BNX2_NUM_TESTS;
7380 case ETH_SS_STATS:
7381 return BNX2_NUM_STATS;
7382 default:
7383 return -EOPNOTSUPP;
7384 }
b6016b76
MC		 7385}
7386
7387static void
7388bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7389{
972ec0d4 7390 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7391
9f52b564
MC		 7392 bnx2_set_power_state(bp, PCI_D0);
7393
b6016b76
MC		 7394 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7395 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7396 int i;
7397
212f9934 7398 bnx2_netif_stop(bp, true);
b6016b76
MC		 7399 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7400 bnx2_free_skbs(bp);
7401
7402 if (bnx2_test_registers(bp) != 0) {
7403 buf[0] = 1;
7404 etest->flags |= ETH_TEST_FL_FAILED;
7405 }
7406 if (bnx2_test_memory(bp) != 0) {
7407 buf[1] = 1;
7408 etest->flags |= ETH_TEST_FL_FAILED;
7409 }
bc5a0690 7410 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7411 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7412
9f52b564
MC		 7413 if (!netif_running(bp->dev))
7414 bnx2_shutdown_chip(bp);
b6016b76 7415 else {
9a120bc5 7416 bnx2_init_nic(bp, 1);
212f9934 7417 bnx2_netif_start(bp, true);
b6016b76
MC		 7418 }
7419
7420 /* wait for link up */
80be4434
MC		 7421 for (i = 0; i < 7; i++) {
7422 if (bp->link_up)
7423 break;
7424 msleep_interruptible(1000);
7425 }
b6016b76
MC		 7426 }
7427
7428 if (bnx2_test_nvram(bp) != 0) {
7429 buf[3] = 1;
7430 etest->flags |= ETH_TEST_FL_FAILED;
7431 }
7432 if (bnx2_test_intr(bp) != 0) {
7433 buf[4] = 1;
7434 etest->flags |= ETH_TEST_FL_FAILED;
7435 }
7436
7437 if (bnx2_test_link(bp) != 0) {
7438 buf[5] = 1;
7439 etest->flags |= ETH_TEST_FL_FAILED;
7440
7441 }
9f52b564
MC		 7442 if (!netif_running(bp->dev))
7443 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7444}
7445
7446static void
7447bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7448{
7449 switch (stringset) {
7450 case ETH_SS_STATS:
7451 memcpy(buf, bnx2_stats_str_arr,
7452 sizeof(bnx2_stats_str_arr));
7453 break;
7454 case ETH_SS_TEST:
7455 memcpy(buf, bnx2_tests_str_arr,
7456 sizeof(bnx2_tests_str_arr));
7457 break;
7458 }
7459}
7460
b6016b76
MC		 7461static void
7462bnx2_get_ethtool_stats(struct net_device *dev,
7463 struct ethtool_stats *stats, u64 *buf)
7464{
972ec0d4 7465 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7466 int i;
7467 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7468 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7469 u8 *stats_len_arr = NULL;
b6016b76
MC		 7470
7471 if (hw_stats == NULL) {
7472 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7473 return;
7474 }
7475
5b0c76ad
MC		 7476 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7477 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7478 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7479 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7480 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7481 else
7482 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7483
7484 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7485 unsigned long offset;
7486
b6016b76
MC		 7487 if (stats_len_arr[i] == 0) {
7488 /* skip this counter */
7489 buf[i] = 0;
7490 continue;
7491 }
354fcd77
MC		 7492
7493 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7494 if (stats_len_arr[i] == 4) {
7495 /* 4-byte counter */
354fcd77
MC		 7496 buf[i] = (u64) *(hw_stats + offset) +
7497 *(temp_stats + offset);
b6016b76
MC		 7498 continue;
7499 }
7500 /* 8-byte counter */
354fcd77
MC		 7501 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7502 *(hw_stats + offset + 1) +
7503 (((u64) *(temp_stats + offset)) << 32) +
7504 *(temp_stats + offset + 1);
b6016b76
MC		 7505 }
7506}
7507
7508static int
7509bnx2_phys_id(struct net_device *dev, u32 data)
7510{
972ec0d4 7511 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7512 int i;
7513 u32 save;
7514
9f52b564
MC		 7515 bnx2_set_power_state(bp, PCI_D0);
7516
b6016b76
MC		 7517 if (data == 0)
7518 data = 2;
7519
7520 save = REG_RD(bp, BNX2_MISC_CFG);
7521 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7522
7523 for (i = 0; i < (data * 2); i++) {
7524 if ((i % 2) == 0) {
7525 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7526 }
7527 else {
7528 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7529 BNX2_EMAC_LED_1000MB_OVERRIDE |
7530 BNX2_EMAC_LED_100MB_OVERRIDE |
7531 BNX2_EMAC_LED_10MB_OVERRIDE |
7532 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7533 BNX2_EMAC_LED_TRAFFIC);
7534 }
7535 msleep_interruptible(500);
7536 if (signal_pending(current))
7537 break;
7538 }
7539 REG_WR(bp, BNX2_EMAC_LED, 0);
7540 REG_WR(bp, BNX2_MISC_CFG, save);
9f52b564
MC		 7541
7542 if (!netif_running(dev))
7543 bnx2_set_power_state(bp, PCI_D3hot);
7544
b6016b76
MC		 7545 return 0;
7546}
7547
4666f87a
MC		 7548static int
7549bnx2_set_tx_csum(struct net_device *dev, u32 data)
7550{
7551 struct bnx2 *bp = netdev_priv(dev);
7552
7553 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 7554 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 7555 else
7556 return (ethtool_op_set_tx_csum(dev, data));
7557}
7558
fdc8541d
MC		 7559static int
7560bnx2_set_flags(struct net_device *dev, u32 data)
7561{
7562 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
7563}
7564
7282d491 7565static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7566 .get_settings = bnx2_get_settings,
7567 .set_settings = bnx2_set_settings,
7568 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7569 .get_regs_len = bnx2_get_regs_len,
7570 .get_regs = bnx2_get_regs,
b6016b76
MC		 7571 .get_wol = bnx2_get_wol,
7572 .set_wol = bnx2_set_wol,
7573 .nway_reset = bnx2_nway_reset,
7959ea25 7574 .get_link = bnx2_get_link,
b6016b76
MC		 7575 .get_eeprom_len = bnx2_get_eeprom_len,
7576 .get_eeprom = bnx2_get_eeprom,
7577 .set_eeprom = bnx2_set_eeprom,
7578 .get_coalesce = bnx2_get_coalesce,
7579 .set_coalesce = bnx2_set_coalesce,
7580 .get_ringparam = bnx2_get_ringparam,
7581 .set_ringparam = bnx2_set_ringparam,
7582 .get_pauseparam = bnx2_get_pauseparam,
7583 .set_pauseparam = bnx2_set_pauseparam,
7584 .get_rx_csum = bnx2_get_rx_csum,
7585 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 7586 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 7587 .set_sg = ethtool_op_set_sg,
b11d6213 7588 .set_tso = bnx2_set_tso,
b6016b76
MC		 7589 .self_test = bnx2_self_test,
7590 .get_strings = bnx2_get_strings,
7591 .phys_id = bnx2_phys_id,
b6016b76 7592 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7593 .get_sset_count = bnx2_get_sset_count,
fdc8541d
MC		 7594 .set_flags = bnx2_set_flags,
7595 .get_flags = ethtool_op_get_flags,
b6016b76
MC		 7596};
7597
7598/* Called with rtnl_lock */
7599static int
7600bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7601{
14ab9b86 7602 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7603 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7604 int err;
7605
7606 switch(cmd) {
7607 case SIOCGMIIPHY:
7608 data->phy_id = bp->phy_addr;
7609
7610 /* fallthru */
7611 case SIOCGMIIREG: {
7612 u32 mii_regval;
7613
583c28e5 7614 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7615 return -EOPNOTSUPP;
7616
dad3e452
MC		 7617 if (!netif_running(dev))
7618 return -EAGAIN;
7619
c770a65c 7620 spin_lock_bh(&bp->phy_lock);
b6016b76 7621 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7622 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7623
7624 data->val_out = mii_regval;
7625
7626 return err;
7627 }
7628
7629 case SIOCSMIIREG:
583c28e5 7630 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7631 return -EOPNOTSUPP;
7632
dad3e452
MC		 7633 if (!netif_running(dev))
7634 return -EAGAIN;
7635
c770a65c 7636 spin_lock_bh(&bp->phy_lock);
b6016b76 7637 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7638 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7639
7640 return err;
7641
7642 default:
7643 /* do nothing */
7644 break;
7645 }
7646 return -EOPNOTSUPP;
7647}
7648
7649/* Called with rtnl_lock */
7650static int
7651bnx2_change_mac_addr(struct net_device *dev, void *p)
7652{
7653 struct sockaddr *addr = p;
972ec0d4 7654 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7655
73eef4cd
MC		 7656 if (!is_valid_ether_addr(addr->sa_data))
7657 return -EINVAL;
7658
b6016b76
MC		 7659 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7660 if (netif_running(dev))
5fcaed01 7661 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7662
7663 return 0;
7664}
7665
7666/* Called with rtnl_lock */
7667static int
7668bnx2_change_mtu(struct net_device *dev, int new_mtu)
7669{
972ec0d4 7670 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7671
7672 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7673 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7674 return -EINVAL;
7675
7676 dev->mtu = new_mtu;
5d5d0015 7677 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 7678}
7679
257ddbda 7680#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7681static void
7682poll_bnx2(struct net_device *dev)
7683{
972ec0d4 7684 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7685 int i;
b6016b76 7686
b2af2c1d 7687 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7688 struct bnx2_irq *irq = &bp->irq_tbl[i];
7689
7690 disable_irq(irq->vector);
7691 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7692 enable_irq(irq->vector);
b2af2c1d 7693 }
b6016b76
MC		 7694}
7695#endif
7696
253c8b75
MC		 7697static void __devinit
7698bnx2_get_5709_media(struct bnx2 *bp)
7699{
7700 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7701 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7702 u32 strap;
7703
7704 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7705 return;
7706 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7707 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7708 return;
7709 }
7710
7711 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7712 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7713 else
7714 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7715
7716 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7717 switch (strap) {
7718 case 0x4:
7719 case 0x5:
7720 case 0x6:
583c28e5 7721 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7722 return;
7723 }
7724 } else {
7725 switch (strap) {
7726 case 0x1:
7727 case 0x2:
7728 case 0x4:
583c28e5 7729 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7730 return;
7731 }
7732 }
7733}
7734
883e5151
MC		 7735static void __devinit
7736bnx2_get_pci_speed(struct bnx2 *bp)
7737{
7738 u32 reg;
7739
7740 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7741 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7742 u32 clkreg;
7743
f86e82fb 7744 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7745
7746 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7747
7748 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7749 switch (clkreg) {
7750 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7751 bp->bus_speed_mhz = 133;
7752 break;
7753
7754 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7755 bp->bus_speed_mhz = 100;
7756 break;
7757
7758 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7759 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7760 bp->bus_speed_mhz = 66;
7761 break;
7762
7763 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7764 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7765 bp->bus_speed_mhz = 50;
7766 break;
7767
7768 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7769 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7770 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7771 bp->bus_speed_mhz = 33;
7772 break;
7773 }
7774 }
7775 else {
7776 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7777 bp->bus_speed_mhz = 66;
7778 else
7779 bp->bus_speed_mhz = 33;
7780 }
7781
7782 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7783 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7784
7785}
7786
76d99061
MC		 7787static void __devinit
7788bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7789{
df25bc38 7790 int rc, i, j;
76d99061 7791 u8 *data;
df25bc38 7792 unsigned int block_end, rosize, len;
76d99061 7793
012093f6
MC		 7794#define BNX2_VPD_NVRAM_OFFSET 0x300
7795#define BNX2_VPD_LEN 128
76d99061
MC		 7796#define BNX2_MAX_VER_SLEN 30
7797
7798 data = kmalloc(256, GFP_KERNEL);
7799 if (!data)
7800 return;
7801
012093f6
MC		 7802 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7803 BNX2_VPD_LEN);
76d99061
MC		 7804 if (rc)
7805 goto vpd_done;
7806
012093f6
MC		 7807 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7808 data[i] = data[i + BNX2_VPD_LEN + 3];
7809 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7810 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7811 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 7812 }
7813
df25bc38
MC		 7814 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7815 if (i < 0)
7816 goto vpd_done;
76d99061 7817
df25bc38
MC		 7818 rosize = pci_vpd_lrdt_size(&data[i]);
7819 i += PCI_VPD_LRDT_TAG_SIZE;
7820 block_end = i + rosize;
76d99061 7821
df25bc38
MC		 7822 if (block_end > BNX2_VPD_LEN)
7823 goto vpd_done;
76d99061 7824
df25bc38
MC		 7825 j = pci_vpd_find_info_keyword(data, i, rosize,
7826 PCI_VPD_RO_KEYWORD_MFR_ID);
7827 if (j < 0)
7828 goto vpd_done;
76d99061 7829
df25bc38 7830 len = pci_vpd_info_field_size(&data[j]);
76d99061 7831
df25bc38
MC		 7832 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7833 if (j + len > block_end || len != 4 ||
7834 memcmp(&data[j], "1028", 4))
7835 goto vpd_done;
4067a854 7836
df25bc38
MC		 7837 j = pci_vpd_find_info_keyword(data, i, rosize,
7838 PCI_VPD_RO_KEYWORD_VENDOR0);
7839 if (j < 0)
7840 goto vpd_done;
4067a854 7841
df25bc38 7842 len = pci_vpd_info_field_size(&data[j]);
4067a854 7843
df25bc38
MC		 7844 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7845 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 7846 goto vpd_done;
df25bc38
MC		 7847
7848 memcpy(bp->fw_version, &data[j], len);
7849 bp->fw_version[len] = ' ';
76d99061
MC		 7850
7851vpd_done:
7852 kfree(data);
7853}
7854
b6016b76
MC		 7855static int __devinit
7856bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7857{
7858 struct bnx2 *bp;
7859 unsigned long mem_len;
58fc2ea4 7860 int rc, i, j;
b6016b76 7861 u32 reg;
40453c83 7862 u64 dma_mask, persist_dma_mask;
b6016b76 7863
b6016b76 7864 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7865 bp = netdev_priv(dev);
b6016b76
MC		 7866
7867 bp->flags = 0;
7868 bp->phy_flags = 0;
7869
354fcd77
MC		 7870 bp->temp_stats_blk =
7871 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7872
7873 if (bp->temp_stats_blk == NULL) {
7874 rc = -ENOMEM;
7875 goto err_out;
7876 }
7877
b6016b76
MC		 7878 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7879 rc = pci_enable_device(pdev);
7880 if (rc) {
3a9c6a49 7881 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 7882 goto err_out;
7883 }
7884
7885 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7886 dev_err(&pdev->dev,
3a9c6a49 7887 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 7888 rc = -ENODEV;
7889 goto err_out_disable;
7890 }
7891
7892 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7893 if (rc) {
3a9c6a49 7894 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 7895 goto err_out_disable;
7896 }
7897
7898 pci_set_master(pdev);
6ff2da49 7899 pci_save_state(pdev);
b6016b76
MC		 7900
7901 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7902 if (bp->pm_cap == 0) {
9b91cf9d 7903 dev_err(&pdev->dev,
3a9c6a49 7904 "Cannot find power management capability, aborting\n");
b6016b76
MC		 7905 rc = -EIO;
7906 goto err_out_release;
7907 }
7908
b6016b76
MC		 7909 bp->dev = dev;
7910 bp->pdev = pdev;
7911
7912 spin_lock_init(&bp->phy_lock);
1b8227c4 7913 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 7914#ifdef BCM_CNIC
7915 mutex_init(&bp->cnic_lock);
7916#endif
c4028958 7917 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7918
7919 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
4edd473f 7920 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
b6016b76
MC		 7921 dev->mem_end = dev->mem_start + mem_len;
7922 dev->irq = pdev->irq;
7923
7924 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7925
7926 if (!bp->regview) {
3a9c6a49 7927 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 7928 rc = -ENOMEM;
7929 goto err_out_release;
7930 }
7931
7932 /* Configure byte swap and enable write to the reg_window registers.
7933 * Rely on CPU to do target byte swapping on big endian systems
7934 * The chip's target access swapping will not swap all accesses
7935 */
7936 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7937 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7938 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7939
829ca9a3 7940 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7941
7942 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7943
883e5151
MC		 7944 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7945 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7946 dev_err(&pdev->dev,
3a9c6a49 7947 "Cannot find PCIE capability, aborting\n");
883e5151
MC		 7948 rc = -EIO;
7949 goto err_out_unmap;
7950 }
f86e82fb 7951 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7952 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7953 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7954 } else {
59b47d8a
MC		 7955 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7956 if (bp->pcix_cap == 0) {
7957 dev_err(&pdev->dev,
3a9c6a49 7958 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 7959 rc = -EIO;
7960 goto err_out_unmap;
7961 }
61d9e3fa 7962 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 7963 }
7964
b4b36042
MC		 7965 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7966 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7967 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7968 }
7969
8e6a72c4
MC		 7970 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7971 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7972 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7973 }
7974
40453c83
MC		 7975 /* 5708 cannot support DMA addresses > 40-bit. */
7976 if (CHIP_NUM(bp) == CHIP_NUM_5708)
50cf156a 7977 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 7978 else
6a35528a 7979 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 7980
7981 /* Configure DMA attributes. */
7982 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7983 dev->features |= NETIF_F_HIGHDMA;
7984 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7985 if (rc) {
7986 dev_err(&pdev->dev,
3a9c6a49 7987 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 7988 goto err_out_unmap;
7989 }
284901a9 7990 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 7991 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 7992 goto err_out_unmap;
7993 }
7994
f86e82fb 7995 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7996 bnx2_get_pci_speed(bp);
b6016b76
MC		 7997
7998 /* 5706A0 may falsely detect SERR and PERR. */
7999 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8000 reg = REG_RD(bp, PCI_COMMAND);
8001 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8002 REG_WR(bp, PCI_COMMAND, reg);
8003 }
8004 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 8005 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8006
9b91cf9d 8007 dev_err(&pdev->dev,
3a9c6a49 8008 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8009 goto err_out_unmap;
8010 }
8011
8012 bnx2_init_nvram(bp);
8013
2726d6e1 8014 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 8015
8016 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 8017 BNX2_SHM_HDR_SIGNATURE_SIG) {
8018 u32 off = PCI_FUNC(pdev->devfn) << 2;
8019
2726d6e1 8020 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8021 } else
e3648b3d
MC		 8022 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8023
b6016b76
MC		 8024 /* Get the permanent MAC address. First we need to make sure the
8025 * firmware is actually running.
8026 */
2726d6e1 8027 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8028
8029 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8030 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8031 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8032 rc = -ENODEV;
8033 goto err_out_unmap;
8034 }
8035
76d99061
MC		 8036 bnx2_read_vpd_fw_ver(bp);
8037
8038 j = strlen(bp->fw_version);
2726d6e1 8039 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8040 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8041 u8 num, k, skip0;
8042
76d99061
MC		 8043 if (i == 0) {
8044 bp->fw_version[j++] = 'b';
8045 bp->fw_version[j++] = 'c';
8046 bp->fw_version[j++] = ' ';
8047 }
58fc2ea4
MC		 8048 num = (u8) (reg >> (24 - (i * 8)));
8049 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8050 if (num >= k || !skip0 || k == 1) {
8051 bp->fw_version[j++] = (num / k) + '0';
8052 skip0 = 0;
8053 }
8054 }
8055 if (i != 2)
8056 bp->fw_version[j++] = '.';
8057 }
2726d6e1 8058 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8059 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8060 bp->wol = 1;
8061
8062 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8063 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8064
8065 for (i = 0; i < 30; i++) {
2726d6e1 8066 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8067 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8068 break;
8069 msleep(10);
8070 }
8071 }
2726d6e1 8072 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8073 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8074 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8075 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8076 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8077
76d99061
MC		 8078 if (j < 32)
8079 bp->fw_version[j++] = ' ';
8080 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8081 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 8082 reg = swab32(reg);
8083 memcpy(&bp->fw_version[j], &reg, 4);
8084 j += 4;
8085 }
8086 }
b6016b76 8087
2726d6e1 8088 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8089 bp->mac_addr[0] = (u8) (reg >> 8);
8090 bp->mac_addr[1] = (u8) reg;
8091
2726d6e1 8092 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8093 bp->mac_addr[2] = (u8) (reg >> 24);
8094 bp->mac_addr[3] = (u8) (reg >> 16);
8095 bp->mac_addr[4] = (u8) (reg >> 8);
8096 bp->mac_addr[5] = (u8) reg;
8097
8098 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 8099 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 8100
8101 bp->rx_csum = 1;
8102
cf7474a6 8103 bp->tx_quick_cons_trip_int = 2;
b6016b76 8104 bp->tx_quick_cons_trip = 20;
cf7474a6 8105 bp->tx_ticks_int = 18;
b6016b76 8106 bp->tx_ticks = 80;
6aa20a22 8107
cf7474a6
MC		 8108 bp->rx_quick_cons_trip_int = 2;
8109 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8110 bp->rx_ticks_int = 18;
8111 bp->rx_ticks = 18;
8112
7ea6920e 8113 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8114
ac392abc 8115 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8116
5b0c76ad
MC		 8117 bp->phy_addr = 1;
8118
b6016b76 8119 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 8120 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8121 bnx2_get_5709_media(bp);
8122 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 8123 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8124
0d8a6571 8125 bp->phy_port = PORT_TP;
583c28e5 8126 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8127 bp->phy_port = PORT_FIBRE;
2726d6e1 8128 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8129 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8130 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8131 bp->wol = 0;
8132 }
38ea3686
MC		 8133 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8134 /* Don't do parallel detect on this board because of
8135 * some board problems. The link will not go down
8136 * if we do parallel detect.
8137 */
8138 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8139 pdev->subsystem_device == 0x310c)
8140 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8141 } else {
5b0c76ad 8142 bp->phy_addr = 2;
5b0c76ad 8143 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8144 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8145 }
261dd5ca
MC		 8146 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8147 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 8148 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 8149 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8150 (CHIP_REV(bp) == CHIP_REV_Ax ||
8151 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 8152 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8153
7c62e83b
MC		 8154 bnx2_init_fw_cap(bp);
8155
16088272
MC		 8156 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8157 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5ec6d7bf
MC		 8158 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8159 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8160 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8161 bp->wol = 0;
8162 }
dda1e390 8163
b6016b76
MC		 8164 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8165 bp->tx_quick_cons_trip_int =
8166 bp->tx_quick_cons_trip;
8167 bp->tx_ticks_int = bp->tx_ticks;
8168 bp->rx_quick_cons_trip_int =
8169 bp->rx_quick_cons_trip;
8170 bp->rx_ticks_int = bp->rx_ticks;
8171 bp->comp_prod_trip_int = bp->comp_prod_trip;
8172 bp->com_ticks_int = bp->com_ticks;
8173 bp->cmd_ticks_int = bp->cmd_ticks;
8174 }
8175
f9317a40
MC		 8176 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8177 *
8178 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8179 * with byte enables disabled on the unused 32-bit word. This is legal
8180 * but causes problems on the AMD 8132 which will eventually stop
8181 * responding after a while.
8182 *
8183 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8184 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 8185 */
8186 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8187 struct pci_dev *amd_8132 = NULL;
8188
8189 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8190 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8191 amd_8132))) {
f9317a40 8192
44c10138
AK		 8193 if (amd_8132->revision >= 0x10 &&
8194 amd_8132->revision <= 0x13) {
f9317a40
MC		 8195 disable_msi = 1;
8196 pci_dev_put(amd_8132);
8197 break;
8198 }
8199 }
8200 }
8201
deaf391b 8202 bnx2_set_default_link(bp);
b6016b76
MC		 8203 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8204
cd339a0e 8205 init_timer(&bp->timer);
ac392abc 8206 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8207 bp->timer.data = (unsigned long) bp;
8208 bp->timer.function = bnx2_timer;
8209
b6016b76
MC		 8210 return 0;
8211
8212err_out_unmap:
8213 if (bp->regview) {
8214 iounmap(bp->regview);
73eef4cd 8215 bp->regview = NULL;
b6016b76
MC		 8216 }
8217
8218err_out_release:
8219 pci_release_regions(pdev);
8220
8221err_out_disable:
8222 pci_disable_device(pdev);
8223 pci_set_drvdata(pdev, NULL);
8224
8225err_out:
8226 return rc;
8227}
8228
883e5151
MC		 8229static char * __devinit
8230bnx2_bus_string(struct bnx2 *bp, char *str)
8231{
8232 char *s = str;
8233
f86e82fb 8234 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8235 s += sprintf(s, "PCI Express");
8236 } else {
8237 s += sprintf(s, "PCI");
f86e82fb 8238 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8239 s += sprintf(s, "-X");
f86e82fb 8240 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8241 s += sprintf(s, " 32-bit");
8242 else
8243 s += sprintf(s, " 64-bit");
8244 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8245 }
8246 return str;
8247}
8248
f048fa9c
MC		 8249static void
8250bnx2_del_napi(struct bnx2 *bp)
8251{
8252 int i;
8253
8254 for (i = 0; i < bp->irq_nvecs; i++)
8255 netif_napi_del(&bp->bnx2_napi[i].napi);
8256}
8257
8258static void
35efa7c1
MC		 8259bnx2_init_napi(struct bnx2 *bp)
8260{
b4b36042 8261 int i;
35efa7c1 8262
4327ba43 8263 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8264 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8265 int (*poll)(struct napi_struct *, int);
8266
8267 if (i == 0)
8268 poll = bnx2_poll;
8269 else
f0ea2e63 8270 poll = bnx2_poll_msix;
35e9010b
MC		 8271
8272 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8273 bnapi->bp = bp;
8274 }
35efa7c1
MC		 8275}
8276
0421eae6
SH		 8277static const struct net_device_ops bnx2_netdev_ops = {
8278 .ndo_open = bnx2_open,
8279 .ndo_start_xmit = bnx2_start_xmit,
8280 .ndo_stop = bnx2_close,
5d07bf26 8281 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8282 .ndo_set_rx_mode = bnx2_set_rx_mode,
8283 .ndo_do_ioctl = bnx2_ioctl,
8284 .ndo_validate_addr = eth_validate_addr,
8285 .ndo_set_mac_address = bnx2_change_mac_addr,
8286 .ndo_change_mtu = bnx2_change_mtu,
8287 .ndo_tx_timeout = bnx2_tx_timeout,
8288#ifdef BCM_VLAN
8289 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8290#endif
257ddbda 8291#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8292 .ndo_poll_controller = poll_bnx2,
8293#endif
8294};
8295
72dccb01
ED		 8296static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8297{
8298#ifdef BCM_VLAN
8299 dev->vlan_features |= flags;
8300#endif
8301}
8302
b6016b76
MC		 8303static int __devinit
8304bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8305{
8306 static int version_printed = 0;
8307 struct net_device *dev = NULL;
8308 struct bnx2 *bp;
0795af57 8309 int rc;
883e5151 8310 char str[40];
b6016b76
MC		 8311
8312 if (version_printed++ == 0)
3a9c6a49 8313 pr_info("%s", version);
b6016b76
MC		 8314
8315 /* dev zeroed in init_etherdev */
706bf240 8316 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8317
8318 if (!dev)
8319 return -ENOMEM;
8320
8321 rc = bnx2_init_board(pdev, dev);
8322 if (rc < 0) {
8323 free_netdev(dev);
8324 return rc;
8325 }
8326
0421eae6 8327 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8328 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8329 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8330
972ec0d4 8331 bp = netdev_priv(dev);
b6016b76 8332
1b2f922f
MC		 8333 pci_set_drvdata(pdev, dev);
8334
57579f76
MC		 8335 rc = bnx2_request_firmware(bp);
8336 if (rc)
8337 goto error;
8338
1b2f922f
MC		 8339 memcpy(dev->dev_addr, bp->mac_addr, 6);
8340 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 8341
fdc8541d
MC		 8342 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO |
8343 NETIF_F_RXHASH;
72dccb01
ED		 8344 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8345 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
d212f87b 8346 dev->features |= NETIF_F_IPV6_CSUM;
72dccb01
ED		 8347 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8348 }
1b2f922f
MC		 8349#ifdef BCM_VLAN
8350 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8351#endif
8352 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
72dccb01
ED		 8353 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8354 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4666f87a 8355 dev->features |= NETIF_F_TSO6;
72dccb01
ED		 8356 vlan_features_add(dev, NETIF_F_TSO6);
8357 }
b6016b76 8358 if ((rc = register_netdev(dev))) {
9b91cf9d 8359 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8360 goto error;
b6016b76
MC		 8361 }
8362
3a9c6a49
JP		 8363 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8364 board_info[ent->driver_data].name,
8365 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8366 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8367 bnx2_bus_string(bp, str),
8368 dev->base_addr,
8369 bp->pdev->irq, dev->dev_addr);
b6016b76 8370
b6016b76 8371 return 0;
57579f76
MC		 8372
8373error:
8374 if (bp->mips_firmware)
8375 release_firmware(bp->mips_firmware);
8376 if (bp->rv2p_firmware)
8377 release_firmware(bp->rv2p_firmware);
8378
8379 if (bp->regview)
8380 iounmap(bp->regview);
8381 pci_release_regions(pdev);
8382 pci_disable_device(pdev);
8383 pci_set_drvdata(pdev, NULL);
8384 free_netdev(dev);
8385 return rc;
b6016b76
MC		 8386}
8387
8388static void __devexit
8389bnx2_remove_one(struct pci_dev *pdev)
8390{
8391 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8392 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8393
afdc08b9
MC		 8394 flush_scheduled_work();
8395
b6016b76
MC		 8396 unregister_netdev(dev);
8397
57579f76
MC		 8398 if (bp->mips_firmware)
8399 release_firmware(bp->mips_firmware);
8400 if (bp->rv2p_firmware)
8401 release_firmware(bp->rv2p_firmware);
8402
b6016b76
MC		 8403 if (bp->regview)
8404 iounmap(bp->regview);
8405
354fcd77
MC		 8406 kfree(bp->temp_stats_blk);
8407
b6016b76
MC		 8408 free_netdev(dev);
8409 pci_release_regions(pdev);
8410 pci_disable_device(pdev);
8411 pci_set_drvdata(pdev, NULL);
8412}
8413
8414static int
829ca9a3 8415bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 8416{
8417 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8418 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8419
6caebb02
MC		 8420 /* PCI register 4 needs to be saved whether netif_running() or not.
8421 * MSI address and data need to be saved if using MSI and
8422 * netif_running().
8423 */
8424 pci_save_state(pdev);
b6016b76
MC		 8425 if (!netif_running(dev))
8426 return 0;
8427
1d60290f 8428 flush_scheduled_work();
212f9934 8429 bnx2_netif_stop(bp, true);
b6016b76
MC		 8430 netif_device_detach(dev);
8431 del_timer_sync(&bp->timer);
74bf4ba3 8432 bnx2_shutdown_chip(bp);
b6016b76 8433 bnx2_free_skbs(bp);
829ca9a3 8434 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 8435 return 0;
8436}
8437
8438static int
8439bnx2_resume(struct pci_dev *pdev)
8440{
8441 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8442 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8443
6caebb02 8444 pci_restore_state(pdev);
b6016b76
MC		 8445 if (!netif_running(dev))
8446 return 0;
8447
829ca9a3 8448 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8449 netif_device_attach(dev);
9a120bc5 8450 bnx2_init_nic(bp, 1);
212f9934 8451 bnx2_netif_start(bp, true);
b6016b76
MC		 8452 return 0;
8453}
8454
6ff2da49
WX		 8455/**
8456 * bnx2_io_error_detected - called when PCI error is detected
8457 * @pdev: Pointer to PCI device
8458 * @state: The current pci connection state
8459 *
8460 * This function is called after a PCI bus error affecting
8461 * this device has been detected.
8462 */
8463static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8464 pci_channel_state_t state)
8465{
8466 struct net_device *dev = pci_get_drvdata(pdev);
8467 struct bnx2 *bp = netdev_priv(dev);
8468
8469 rtnl_lock();
8470 netif_device_detach(dev);
8471
2ec3de26
DN		 8472 if (state == pci_channel_io_perm_failure) {
8473 rtnl_unlock();
8474 return PCI_ERS_RESULT_DISCONNECT;
8475 }
8476
6ff2da49 8477 if (netif_running(dev)) {
212f9934 8478 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8479 del_timer_sync(&bp->timer);
8480 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8481 }
8482
8483 pci_disable_device(pdev);
8484 rtnl_unlock();
8485
8486 /* Request a slot slot reset. */
8487 return PCI_ERS_RESULT_NEED_RESET;
8488}
8489
8490/**
8491 * bnx2_io_slot_reset - called after the pci bus has been reset.
8492 * @pdev: Pointer to PCI device
8493 *
8494 * Restart the card from scratch, as if from a cold-boot.
8495 */
8496static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8497{
8498 struct net_device *dev = pci_get_drvdata(pdev);
8499 struct bnx2 *bp = netdev_priv(dev);
8500
8501 rtnl_lock();
8502 if (pci_enable_device(pdev)) {
8503 dev_err(&pdev->dev,
3a9c6a49 8504 "Cannot re-enable PCI device after reset\n");
6ff2da49
WX		 8505 rtnl_unlock();
8506 return PCI_ERS_RESULT_DISCONNECT;
8507 }
8508 pci_set_master(pdev);
8509 pci_restore_state(pdev);
529fab67 8510 pci_save_state(pdev);
6ff2da49
WX		 8511
8512 if (netif_running(dev)) {
8513 bnx2_set_power_state(bp, PCI_D0);
8514 bnx2_init_nic(bp, 1);
8515 }
8516
8517 rtnl_unlock();
8518 return PCI_ERS_RESULT_RECOVERED;
8519}
8520
8521/**
8522 * bnx2_io_resume - called when traffic can start flowing again.
8523 * @pdev: Pointer to PCI device
8524 *
8525 * This callback is called when the error recovery driver tells us that
8526 * its OK to resume normal operation.
8527 */
8528static void bnx2_io_resume(struct pci_dev *pdev)
8529{
8530 struct net_device *dev = pci_get_drvdata(pdev);
8531 struct bnx2 *bp = netdev_priv(dev);
8532
8533 rtnl_lock();
8534 if (netif_running(dev))
212f9934 8535 bnx2_netif_start(bp, true);
6ff2da49
WX		 8536
8537 netif_device_attach(dev);
8538 rtnl_unlock();
8539}
8540
8541static struct pci_error_handlers bnx2_err_handler = {
8542 .error_detected = bnx2_io_error_detected,
8543 .slot_reset = bnx2_io_slot_reset,
8544 .resume = bnx2_io_resume,
8545};
8546
b6016b76 8547static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8548 .name = DRV_MODULE_NAME,
8549 .id_table = bnx2_pci_tbl,
8550 .probe = bnx2_init_one,
8551 .remove = __devexit_p(bnx2_remove_one),
8552 .suspend = bnx2_suspend,
8553 .resume = bnx2_resume,
6ff2da49 8554 .err_handler = &bnx2_err_handler,
b6016b76
MC		 8555};
8556
8557static int __init bnx2_init(void)
8558{
29917620 8559 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 8560}
8561
8562static void __exit bnx2_cleanup(void)
8563{
8564 pci_unregister_driver(&bnx2_pci_driver);
8565}
8566
8567module_init(bnx2_init);
8568module_exit(bnx2_cleanup);
8569
8570
8571
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