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b6016b76 MC |
1 | /* bnx2.c: Broadcom NX2 network driver. |
2 | * | |
72fbaeb6 | 3 | * Copyright (c) 2004-2007 Broadcom Corporation |
b6016b76 MC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Written by: Michael Chan (mchan@broadcom.com) | |
10 | */ | |
11 | ||
f2a4f052 MC |
12 | |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/vmalloc.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/skbuff.h> | |
28 | #include <linux/dma-mapping.h> | |
1977f032 | 29 | #include <linux/bitops.h> |
f2a4f052 MC |
30 | #include <asm/io.h> |
31 | #include <asm/irq.h> | |
32 | #include <linux/delay.h> | |
33 | #include <asm/byteorder.h> | |
c86a31f4 | 34 | #include <asm/page.h> |
f2a4f052 MC |
35 | #include <linux/time.h> |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/mii.h> | |
38 | #ifdef NETIF_F_HW_VLAN_TX | |
39 | #include <linux/if_vlan.h> | |
40 | #define BCM_VLAN 1 | |
41 | #endif | |
f2a4f052 | 42 | #include <net/ip.h> |
de081fa5 | 43 | #include <net/tcp.h> |
f2a4f052 | 44 | #include <net/checksum.h> |
f2a4f052 MC |
45 | #include <linux/workqueue.h> |
46 | #include <linux/crc32.h> | |
47 | #include <linux/prefetch.h> | |
29b12174 | 48 | #include <linux/cache.h> |
fba9fe91 | 49 | #include <linux/zlib.h> |
f2a4f052 | 50 | |
b6016b76 MC |
51 | #include "bnx2.h" |
52 | #include "bnx2_fw.h" | |
d43584c8 | 53 | #include "bnx2_fw2.h" |
b6016b76 | 54 | |
110d0ef9 | 55 | #define FW_BUF_SIZE 0x10000 |
b3448b0b | 56 | |
b6016b76 MC |
57 | #define DRV_MODULE_NAME "bnx2" |
58 | #define PFX DRV_MODULE_NAME ": " | |
a0d142c6 MC |
59 | #define DRV_MODULE_VERSION "1.7.0" |
60 | #define DRV_MODULE_RELDATE "December 11, 2007" | |
b6016b76 MC |
61 | |
62 | #define RUN_AT(x) (jiffies + (x)) | |
63 | ||
64 | /* Time in jiffies before concluding the transmitter is hung. */ | |
65 | #define TX_TIMEOUT (5*HZ) | |
66 | ||
e19360f2 | 67 | static const char version[] __devinitdata = |
b6016b76 MC |
68 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
69 | ||
70 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); | |
05d0f1cf | 71 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver"); |
b6016b76 MC |
72 | MODULE_LICENSE("GPL"); |
73 | MODULE_VERSION(DRV_MODULE_VERSION); | |
74 | ||
75 | static int disable_msi = 0; | |
76 | ||
77 | module_param(disable_msi, int, 0); | |
78 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
79 | ||
80 | typedef enum { | |
81 | BCM5706 = 0, | |
82 | NC370T, | |
83 | NC370I, | |
84 | BCM5706S, | |
85 | NC370F, | |
5b0c76ad MC |
86 | BCM5708, |
87 | BCM5708S, | |
bac0dff6 | 88 | BCM5709, |
27a005b8 | 89 | BCM5709S, |
b6016b76 MC |
90 | } board_t; |
91 | ||
92 | /* indexed by board_t, above */ | |
f71e1309 | 93 | static const struct { |
b6016b76 MC |
94 | char *name; |
95 | } board_info[] __devinitdata = { | |
96 | { "Broadcom NetXtreme II BCM5706 1000Base-T" }, | |
97 | { "HP NC370T Multifunction Gigabit Server Adapter" }, | |
98 | { "HP NC370i Multifunction Gigabit Server Adapter" }, | |
99 | { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, | |
100 | { "HP NC370F Multifunction Gigabit Server Adapter" }, | |
5b0c76ad MC |
101 | { "Broadcom NetXtreme II BCM5708 1000Base-T" }, |
102 | { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, | |
bac0dff6 | 103 | { "Broadcom NetXtreme II BCM5709 1000Base-T" }, |
27a005b8 | 104 | { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, |
b6016b76 MC |
105 | }; |
106 | ||
107 | static struct pci_device_id bnx2_pci_tbl[] = { | |
108 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
109 | PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, | |
110 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
111 | PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, | |
112 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
113 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, | |
5b0c76ad MC |
114 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, |
115 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 }, | |
b6016b76 MC |
116 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, |
117 | PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, | |
118 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | |
119 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, | |
5b0c76ad MC |
120 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, |
121 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, | |
bac0dff6 MC |
122 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, |
123 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, | |
27a005b8 MC |
124 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, |
125 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, | |
b6016b76 MC |
126 | { 0, } |
127 | }; | |
128 | ||
129 | static struct flash_spec flash_table[] = | |
130 | { | |
e30372c9 MC |
131 | #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) |
132 | #define NONBUFFERED_FLAGS (BNX2_NV_WREN) | |
b6016b76 | 133 | /* Slow EEPROM */ |
37137709 | 134 | {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, |
e30372c9 | 135 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
b6016b76 MC |
136 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
137 | "EEPROM - slow"}, | |
37137709 MC |
138 | /* Expansion entry 0001 */ |
139 | {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 140 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
141 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
142 | "Entry 0001"}, | |
b6016b76 MC |
143 | /* Saifun SA25F010 (non-buffered flash) */ |
144 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 145 | {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 146 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
147 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, |
148 | "Non-buffered flash (128kB)"}, | |
149 | /* Saifun SA25F020 (non-buffered flash) */ | |
150 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 151 | {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 152 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
153 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, |
154 | "Non-buffered flash (256kB)"}, | |
37137709 MC |
155 | /* Expansion entry 0100 */ |
156 | {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 157 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
158 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
159 | "Entry 0100"}, | |
160 | /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ | |
6aa20a22 | 161 | {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, |
e30372c9 | 162 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
163 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, |
164 | "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, | |
165 | /* Entry 0110: ST M45PE20 (non-buffered flash)*/ | |
166 | {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, | |
e30372c9 | 167 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
168 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, |
169 | "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, | |
170 | /* Saifun SA25F005 (non-buffered flash) */ | |
171 | /* strap, cfg1, & write1 need updates */ | |
172 | {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 173 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
174 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, |
175 | "Non-buffered flash (64kB)"}, | |
176 | /* Fast EEPROM */ | |
177 | {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, | |
e30372c9 | 178 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
37137709 MC |
179 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
180 | "EEPROM - fast"}, | |
181 | /* Expansion entry 1001 */ | |
182 | {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 183 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
184 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
185 | "Entry 1001"}, | |
186 | /* Expansion entry 1010 */ | |
187 | {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 188 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
189 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
190 | "Entry 1010"}, | |
191 | /* ATMEL AT45DB011B (buffered flash) */ | |
192 | {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 193 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
194 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, |
195 | "Buffered flash (128kB)"}, | |
196 | /* Expansion entry 1100 */ | |
197 | {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 198 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
199 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
200 | "Entry 1100"}, | |
201 | /* Expansion entry 1101 */ | |
202 | {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 203 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
204 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
205 | "Entry 1101"}, | |
206 | /* Ateml Expansion entry 1110 */ | |
207 | {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 208 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
209 | BUFFERED_FLASH_BYTE_ADDR_MASK, 0, |
210 | "Entry 1110 (Atmel)"}, | |
211 | /* ATMEL AT45DB021B (buffered flash) */ | |
212 | {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 213 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
214 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, |
215 | "Buffered flash (256kB)"}, | |
b6016b76 MC |
216 | }; |
217 | ||
e30372c9 MC |
218 | static struct flash_spec flash_5709 = { |
219 | .flags = BNX2_NV_BUFFERED, | |
220 | .page_bits = BCM5709_FLASH_PAGE_BITS, | |
221 | .page_size = BCM5709_FLASH_PAGE_SIZE, | |
222 | .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, | |
223 | .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, | |
224 | .name = "5709 Buffered flash (256kB)", | |
225 | }; | |
226 | ||
b6016b76 MC |
227 | MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); |
228 | ||
a550c99b | 229 | static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi) |
e89bbf10 | 230 | { |
2f8af120 | 231 | u32 diff; |
e89bbf10 | 232 | |
2f8af120 | 233 | smp_mb(); |
faac9c4b MC |
234 | |
235 | /* The ring uses 256 indices for 255 entries, one of them | |
236 | * needs to be skipped. | |
237 | */ | |
a550c99b | 238 | diff = bp->tx_prod - bnapi->tx_cons; |
faac9c4b MC |
239 | if (unlikely(diff >= TX_DESC_CNT)) { |
240 | diff &= 0xffff; | |
241 | if (diff == TX_DESC_CNT) | |
242 | diff = MAX_TX_DESC_CNT; | |
243 | } | |
e89bbf10 MC |
244 | return (bp->tx_ring_size - diff); |
245 | } | |
246 | ||
b6016b76 MC |
247 | static u32 |
248 | bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) | |
249 | { | |
1b8227c4 MC |
250 | u32 val; |
251 | ||
252 | spin_lock_bh(&bp->indirect_lock); | |
b6016b76 | 253 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
1b8227c4 MC |
254 | val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW); |
255 | spin_unlock_bh(&bp->indirect_lock); | |
256 | return val; | |
b6016b76 MC |
257 | } |
258 | ||
259 | static void | |
260 | bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) | |
261 | { | |
1b8227c4 | 262 | spin_lock_bh(&bp->indirect_lock); |
b6016b76 MC |
263 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
264 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); | |
1b8227c4 | 265 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
266 | } |
267 | ||
268 | static void | |
269 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) | |
270 | { | |
271 | offset += cid_addr; | |
1b8227c4 | 272 | spin_lock_bh(&bp->indirect_lock); |
59b47d8a MC |
273 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
274 | int i; | |
275 | ||
276 | REG_WR(bp, BNX2_CTX_CTX_DATA, val); | |
277 | REG_WR(bp, BNX2_CTX_CTX_CTRL, | |
278 | offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); | |
279 | for (i = 0; i < 5; i++) { | |
280 | u32 val; | |
281 | val = REG_RD(bp, BNX2_CTX_CTX_CTRL); | |
282 | if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) | |
283 | break; | |
284 | udelay(5); | |
285 | } | |
286 | } else { | |
287 | REG_WR(bp, BNX2_CTX_DATA_ADR, offset); | |
288 | REG_WR(bp, BNX2_CTX_DATA, val); | |
289 | } | |
1b8227c4 | 290 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
291 | } |
292 | ||
293 | static int | |
294 | bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | |
295 | { | |
296 | u32 val1; | |
297 | int i, ret; | |
298 | ||
299 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
300 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
301 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
302 | ||
303 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
304 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
305 | ||
306 | udelay(40); | |
307 | } | |
308 | ||
309 | val1 = (bp->phy_addr << 21) | (reg << 16) | | |
310 | BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | | |
311 | BNX2_EMAC_MDIO_COMM_START_BUSY; | |
312 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | |
313 | ||
314 | for (i = 0; i < 50; i++) { | |
315 | udelay(10); | |
316 | ||
317 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
318 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | |
319 | udelay(5); | |
320 | ||
321 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
322 | val1 &= BNX2_EMAC_MDIO_COMM_DATA; | |
323 | ||
324 | break; | |
325 | } | |
326 | } | |
327 | ||
328 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { | |
329 | *val = 0x0; | |
330 | ret = -EBUSY; | |
331 | } | |
332 | else { | |
333 | *val = val1; | |
334 | ret = 0; | |
335 | } | |
336 | ||
337 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
338 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
339 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
340 | ||
341 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
342 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
343 | ||
344 | udelay(40); | |
345 | } | |
346 | ||
347 | return ret; | |
348 | } | |
349 | ||
350 | static int | |
351 | bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | |
352 | { | |
353 | u32 val1; | |
354 | int i, ret; | |
355 | ||
356 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
357 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
358 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
359 | ||
360 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
361 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
362 | ||
363 | udelay(40); | |
364 | } | |
365 | ||
366 | val1 = (bp->phy_addr << 21) | (reg << 16) | val | | |
367 | BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | | |
368 | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; | |
369 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | |
6aa20a22 | 370 | |
b6016b76 MC |
371 | for (i = 0; i < 50; i++) { |
372 | udelay(10); | |
373 | ||
374 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
375 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | |
376 | udelay(5); | |
377 | break; | |
378 | } | |
379 | } | |
380 | ||
381 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) | |
382 | ret = -EBUSY; | |
383 | else | |
384 | ret = 0; | |
385 | ||
386 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
387 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
388 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
389 | ||
390 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
391 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
392 | ||
393 | udelay(40); | |
394 | } | |
395 | ||
396 | return ret; | |
397 | } | |
398 | ||
399 | static void | |
400 | bnx2_disable_int(struct bnx2 *bp) | |
401 | { | |
b4b36042 MC |
402 | int i; |
403 | struct bnx2_napi *bnapi; | |
404 | ||
405 | for (i = 0; i < bp->irq_nvecs; i++) { | |
406 | bnapi = &bp->bnx2_napi[i]; | |
407 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | | |
408 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
409 | } | |
b6016b76 MC |
410 | REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); |
411 | } | |
412 | ||
413 | static void | |
414 | bnx2_enable_int(struct bnx2 *bp) | |
415 | { | |
b4b36042 MC |
416 | int i; |
417 | struct bnx2_napi *bnapi; | |
35efa7c1 | 418 | |
b4b36042 MC |
419 | for (i = 0; i < bp->irq_nvecs; i++) { |
420 | bnapi = &bp->bnx2_napi[i]; | |
1269a8a6 | 421 | |
b4b36042 MC |
422 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
423 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
424 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | | |
425 | bnapi->last_status_idx); | |
b6016b76 | 426 | |
b4b36042 MC |
427 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
428 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
429 | bnapi->last_status_idx); | |
430 | } | |
bf5295bb | 431 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
b6016b76 MC |
432 | } |
433 | ||
434 | static void | |
435 | bnx2_disable_int_sync(struct bnx2 *bp) | |
436 | { | |
b4b36042 MC |
437 | int i; |
438 | ||
b6016b76 MC |
439 | atomic_inc(&bp->intr_sem); |
440 | bnx2_disable_int(bp); | |
b4b36042 MC |
441 | for (i = 0; i < bp->irq_nvecs; i++) |
442 | synchronize_irq(bp->irq_tbl[i].vector); | |
b6016b76 MC |
443 | } |
444 | ||
35efa7c1 MC |
445 | static void |
446 | bnx2_napi_disable(struct bnx2 *bp) | |
447 | { | |
b4b36042 MC |
448 | int i; |
449 | ||
450 | for (i = 0; i < bp->irq_nvecs; i++) | |
451 | napi_disable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
452 | } |
453 | ||
454 | static void | |
455 | bnx2_napi_enable(struct bnx2 *bp) | |
456 | { | |
b4b36042 MC |
457 | int i; |
458 | ||
459 | for (i = 0; i < bp->irq_nvecs; i++) | |
460 | napi_enable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
461 | } |
462 | ||
b6016b76 MC |
463 | static void |
464 | bnx2_netif_stop(struct bnx2 *bp) | |
465 | { | |
466 | bnx2_disable_int_sync(bp); | |
467 | if (netif_running(bp->dev)) { | |
35efa7c1 | 468 | bnx2_napi_disable(bp); |
b6016b76 MC |
469 | netif_tx_disable(bp->dev); |
470 | bp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
471 | } | |
472 | } | |
473 | ||
474 | static void | |
475 | bnx2_netif_start(struct bnx2 *bp) | |
476 | { | |
477 | if (atomic_dec_and_test(&bp->intr_sem)) { | |
478 | if (netif_running(bp->dev)) { | |
479 | netif_wake_queue(bp->dev); | |
35efa7c1 | 480 | bnx2_napi_enable(bp); |
b6016b76 MC |
481 | bnx2_enable_int(bp); |
482 | } | |
483 | } | |
484 | } | |
485 | ||
486 | static void | |
487 | bnx2_free_mem(struct bnx2 *bp) | |
488 | { | |
13daffa2 MC |
489 | int i; |
490 | ||
59b47d8a MC |
491 | for (i = 0; i < bp->ctx_pages; i++) { |
492 | if (bp->ctx_blk[i]) { | |
493 | pci_free_consistent(bp->pdev, BCM_PAGE_SIZE, | |
494 | bp->ctx_blk[i], | |
495 | bp->ctx_blk_mapping[i]); | |
496 | bp->ctx_blk[i] = NULL; | |
497 | } | |
498 | } | |
b6016b76 | 499 | if (bp->status_blk) { |
0f31f994 | 500 | pci_free_consistent(bp->pdev, bp->status_stats_size, |
b6016b76 MC |
501 | bp->status_blk, bp->status_blk_mapping); |
502 | bp->status_blk = NULL; | |
0f31f994 | 503 | bp->stats_blk = NULL; |
b6016b76 MC |
504 | } |
505 | if (bp->tx_desc_ring) { | |
e343d55c | 506 | pci_free_consistent(bp->pdev, TXBD_RING_SIZE, |
b6016b76 MC |
507 | bp->tx_desc_ring, bp->tx_desc_mapping); |
508 | bp->tx_desc_ring = NULL; | |
509 | } | |
b4558ea9 JJ |
510 | kfree(bp->tx_buf_ring); |
511 | bp->tx_buf_ring = NULL; | |
13daffa2 MC |
512 | for (i = 0; i < bp->rx_max_ring; i++) { |
513 | if (bp->rx_desc_ring[i]) | |
e343d55c | 514 | pci_free_consistent(bp->pdev, RXBD_RING_SIZE, |
13daffa2 MC |
515 | bp->rx_desc_ring[i], |
516 | bp->rx_desc_mapping[i]); | |
517 | bp->rx_desc_ring[i] = NULL; | |
518 | } | |
519 | vfree(bp->rx_buf_ring); | |
b4558ea9 | 520 | bp->rx_buf_ring = NULL; |
47bf4246 MC |
521 | for (i = 0; i < bp->rx_max_pg_ring; i++) { |
522 | if (bp->rx_pg_desc_ring[i]) | |
523 | pci_free_consistent(bp->pdev, RXBD_RING_SIZE, | |
524 | bp->rx_pg_desc_ring[i], | |
525 | bp->rx_pg_desc_mapping[i]); | |
526 | bp->rx_pg_desc_ring[i] = NULL; | |
527 | } | |
528 | if (bp->rx_pg_ring) | |
529 | vfree(bp->rx_pg_ring); | |
530 | bp->rx_pg_ring = NULL; | |
b6016b76 MC |
531 | } |
532 | ||
533 | static int | |
534 | bnx2_alloc_mem(struct bnx2 *bp) | |
535 | { | |
0f31f994 | 536 | int i, status_blk_size; |
13daffa2 | 537 | |
e343d55c | 538 | bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); |
b6016b76 MC |
539 | if (bp->tx_buf_ring == NULL) |
540 | return -ENOMEM; | |
541 | ||
e343d55c | 542 | bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE, |
b6016b76 MC |
543 | &bp->tx_desc_mapping); |
544 | if (bp->tx_desc_ring == NULL) | |
545 | goto alloc_mem_err; | |
546 | ||
e343d55c | 547 | bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); |
b6016b76 MC |
548 | if (bp->rx_buf_ring == NULL) |
549 | goto alloc_mem_err; | |
550 | ||
e343d55c | 551 | memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring); |
13daffa2 MC |
552 | |
553 | for (i = 0; i < bp->rx_max_ring; i++) { | |
554 | bp->rx_desc_ring[i] = | |
e343d55c | 555 | pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, |
13daffa2 MC |
556 | &bp->rx_desc_mapping[i]); |
557 | if (bp->rx_desc_ring[i] == NULL) | |
558 | goto alloc_mem_err; | |
559 | ||
560 | } | |
b6016b76 | 561 | |
47bf4246 MC |
562 | if (bp->rx_pg_ring_size) { |
563 | bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE * | |
564 | bp->rx_max_pg_ring); | |
565 | if (bp->rx_pg_ring == NULL) | |
566 | goto alloc_mem_err; | |
567 | ||
568 | memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE * | |
569 | bp->rx_max_pg_ring); | |
570 | } | |
571 | ||
572 | for (i = 0; i < bp->rx_max_pg_ring; i++) { | |
573 | bp->rx_pg_desc_ring[i] = | |
574 | pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, | |
575 | &bp->rx_pg_desc_mapping[i]); | |
576 | if (bp->rx_pg_desc_ring[i] == NULL) | |
577 | goto alloc_mem_err; | |
578 | ||
579 | } | |
580 | ||
0f31f994 MC |
581 | /* Combine status and statistics blocks into one allocation. */ |
582 | status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); | |
b4b36042 MC |
583 | if (bp->flags & MSIX_CAP_FLAG) |
584 | status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * | |
585 | BNX2_SBLK_MSIX_ALIGN_SIZE); | |
0f31f994 MC |
586 | bp->status_stats_size = status_blk_size + |
587 | sizeof(struct statistics_block); | |
588 | ||
589 | bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size, | |
b6016b76 MC |
590 | &bp->status_blk_mapping); |
591 | if (bp->status_blk == NULL) | |
592 | goto alloc_mem_err; | |
593 | ||
0f31f994 | 594 | memset(bp->status_blk, 0, bp->status_stats_size); |
b6016b76 | 595 | |
b4b36042 MC |
596 | bp->bnx2_napi[0].status_blk = bp->status_blk; |
597 | if (bp->flags & MSIX_CAP_FLAG) { | |
598 | for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) { | |
599 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
600 | ||
601 | bnapi->status_blk = (void *) | |
602 | ((unsigned long) bp->status_blk + | |
603 | BNX2_SBLK_MSIX_ALIGN_SIZE * i); | |
604 | bnapi->int_num = i << 24; | |
605 | } | |
606 | } | |
35efa7c1 | 607 | |
0f31f994 MC |
608 | bp->stats_blk = (void *) ((unsigned long) bp->status_blk + |
609 | status_blk_size); | |
b6016b76 | 610 | |
0f31f994 | 611 | bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; |
b6016b76 | 612 | |
59b47d8a MC |
613 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
614 | bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE; | |
615 | if (bp->ctx_pages == 0) | |
616 | bp->ctx_pages = 1; | |
617 | for (i = 0; i < bp->ctx_pages; i++) { | |
618 | bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev, | |
619 | BCM_PAGE_SIZE, | |
620 | &bp->ctx_blk_mapping[i]); | |
621 | if (bp->ctx_blk[i] == NULL) | |
622 | goto alloc_mem_err; | |
623 | } | |
624 | } | |
b6016b76 MC |
625 | return 0; |
626 | ||
627 | alloc_mem_err: | |
628 | bnx2_free_mem(bp); | |
629 | return -ENOMEM; | |
630 | } | |
631 | ||
e3648b3d MC |
632 | static void |
633 | bnx2_report_fw_link(struct bnx2 *bp) | |
634 | { | |
635 | u32 fw_link_status = 0; | |
636 | ||
0d8a6571 MC |
637 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
638 | return; | |
639 | ||
e3648b3d MC |
640 | if (bp->link_up) { |
641 | u32 bmsr; | |
642 | ||
643 | switch (bp->line_speed) { | |
644 | case SPEED_10: | |
645 | if (bp->duplex == DUPLEX_HALF) | |
646 | fw_link_status = BNX2_LINK_STATUS_10HALF; | |
647 | else | |
648 | fw_link_status = BNX2_LINK_STATUS_10FULL; | |
649 | break; | |
650 | case SPEED_100: | |
651 | if (bp->duplex == DUPLEX_HALF) | |
652 | fw_link_status = BNX2_LINK_STATUS_100HALF; | |
653 | else | |
654 | fw_link_status = BNX2_LINK_STATUS_100FULL; | |
655 | break; | |
656 | case SPEED_1000: | |
657 | if (bp->duplex == DUPLEX_HALF) | |
658 | fw_link_status = BNX2_LINK_STATUS_1000HALF; | |
659 | else | |
660 | fw_link_status = BNX2_LINK_STATUS_1000FULL; | |
661 | break; | |
662 | case SPEED_2500: | |
663 | if (bp->duplex == DUPLEX_HALF) | |
664 | fw_link_status = BNX2_LINK_STATUS_2500HALF; | |
665 | else | |
666 | fw_link_status = BNX2_LINK_STATUS_2500FULL; | |
667 | break; | |
668 | } | |
669 | ||
670 | fw_link_status |= BNX2_LINK_STATUS_LINK_UP; | |
671 | ||
672 | if (bp->autoneg) { | |
673 | fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; | |
674 | ||
ca58c3af MC |
675 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
676 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
e3648b3d MC |
677 | |
678 | if (!(bmsr & BMSR_ANEGCOMPLETE) || | |
679 | bp->phy_flags & PHY_PARALLEL_DETECT_FLAG) | |
680 | fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; | |
681 | else | |
682 | fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; | |
683 | } | |
684 | } | |
685 | else | |
686 | fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; | |
687 | ||
688 | REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status); | |
689 | } | |
690 | ||
9b1084b8 MC |
691 | static char * |
692 | bnx2_xceiver_str(struct bnx2 *bp) | |
693 | { | |
694 | return ((bp->phy_port == PORT_FIBRE) ? "SerDes" : | |
695 | ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" : | |
696 | "Copper")); | |
697 | } | |
698 | ||
b6016b76 MC |
699 | static void |
700 | bnx2_report_link(struct bnx2 *bp) | |
701 | { | |
702 | if (bp->link_up) { | |
703 | netif_carrier_on(bp->dev); | |
9b1084b8 MC |
704 | printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name, |
705 | bnx2_xceiver_str(bp)); | |
b6016b76 MC |
706 | |
707 | printk("%d Mbps ", bp->line_speed); | |
708 | ||
709 | if (bp->duplex == DUPLEX_FULL) | |
710 | printk("full duplex"); | |
711 | else | |
712 | printk("half duplex"); | |
713 | ||
714 | if (bp->flow_ctrl) { | |
715 | if (bp->flow_ctrl & FLOW_CTRL_RX) { | |
716 | printk(", receive "); | |
717 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
718 | printk("& transmit "); | |
719 | } | |
720 | else { | |
721 | printk(", transmit "); | |
722 | } | |
723 | printk("flow control ON"); | |
724 | } | |
725 | printk("\n"); | |
726 | } | |
727 | else { | |
728 | netif_carrier_off(bp->dev); | |
9b1084b8 MC |
729 | printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name, |
730 | bnx2_xceiver_str(bp)); | |
b6016b76 | 731 | } |
e3648b3d MC |
732 | |
733 | bnx2_report_fw_link(bp); | |
b6016b76 MC |
734 | } |
735 | ||
736 | static void | |
737 | bnx2_resolve_flow_ctrl(struct bnx2 *bp) | |
738 | { | |
739 | u32 local_adv, remote_adv; | |
740 | ||
741 | bp->flow_ctrl = 0; | |
6aa20a22 | 742 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != |
b6016b76 MC |
743 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { |
744 | ||
745 | if (bp->duplex == DUPLEX_FULL) { | |
746 | bp->flow_ctrl = bp->req_flow_ctrl; | |
747 | } | |
748 | return; | |
749 | } | |
750 | ||
751 | if (bp->duplex != DUPLEX_FULL) { | |
752 | return; | |
753 | } | |
754 | ||
5b0c76ad MC |
755 | if ((bp->phy_flags & PHY_SERDES_FLAG) && |
756 | (CHIP_NUM(bp) == CHIP_NUM_5708)) { | |
757 | u32 val; | |
758 | ||
759 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
760 | if (val & BCM5708S_1000X_STAT1_TX_PAUSE) | |
761 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
762 | if (val & BCM5708S_1000X_STAT1_RX_PAUSE) | |
763 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
764 | return; | |
765 | } | |
766 | ||
ca58c3af MC |
767 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
768 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
769 | |
770 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
771 | u32 new_local_adv = 0; | |
772 | u32 new_remote_adv = 0; | |
773 | ||
774 | if (local_adv & ADVERTISE_1000XPAUSE) | |
775 | new_local_adv |= ADVERTISE_PAUSE_CAP; | |
776 | if (local_adv & ADVERTISE_1000XPSE_ASYM) | |
777 | new_local_adv |= ADVERTISE_PAUSE_ASYM; | |
778 | if (remote_adv & ADVERTISE_1000XPAUSE) | |
779 | new_remote_adv |= ADVERTISE_PAUSE_CAP; | |
780 | if (remote_adv & ADVERTISE_1000XPSE_ASYM) | |
781 | new_remote_adv |= ADVERTISE_PAUSE_ASYM; | |
782 | ||
783 | local_adv = new_local_adv; | |
784 | remote_adv = new_remote_adv; | |
785 | } | |
786 | ||
787 | /* See Table 28B-3 of 802.3ab-1999 spec. */ | |
788 | if (local_adv & ADVERTISE_PAUSE_CAP) { | |
789 | if(local_adv & ADVERTISE_PAUSE_ASYM) { | |
790 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
791 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
792 | } | |
793 | else if (remote_adv & ADVERTISE_PAUSE_ASYM) { | |
794 | bp->flow_ctrl = FLOW_CTRL_RX; | |
795 | } | |
796 | } | |
797 | else { | |
798 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
799 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
800 | } | |
801 | } | |
802 | } | |
803 | else if (local_adv & ADVERTISE_PAUSE_ASYM) { | |
804 | if ((remote_adv & ADVERTISE_PAUSE_CAP) && | |
805 | (remote_adv & ADVERTISE_PAUSE_ASYM)) { | |
806 | ||
807 | bp->flow_ctrl = FLOW_CTRL_TX; | |
808 | } | |
809 | } | |
810 | } | |
811 | ||
27a005b8 MC |
812 | static int |
813 | bnx2_5709s_linkup(struct bnx2 *bp) | |
814 | { | |
815 | u32 val, speed; | |
816 | ||
817 | bp->link_up = 1; | |
818 | ||
819 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); | |
820 | bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); | |
821 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
822 | ||
823 | if ((bp->autoneg & AUTONEG_SPEED) == 0) { | |
824 | bp->line_speed = bp->req_line_speed; | |
825 | bp->duplex = bp->req_duplex; | |
826 | return 0; | |
827 | } | |
828 | speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; | |
829 | switch (speed) { | |
830 | case MII_BNX2_GP_TOP_AN_SPEED_10: | |
831 | bp->line_speed = SPEED_10; | |
832 | break; | |
833 | case MII_BNX2_GP_TOP_AN_SPEED_100: | |
834 | bp->line_speed = SPEED_100; | |
835 | break; | |
836 | case MII_BNX2_GP_TOP_AN_SPEED_1G: | |
837 | case MII_BNX2_GP_TOP_AN_SPEED_1GKV: | |
838 | bp->line_speed = SPEED_1000; | |
839 | break; | |
840 | case MII_BNX2_GP_TOP_AN_SPEED_2_5G: | |
841 | bp->line_speed = SPEED_2500; | |
842 | break; | |
843 | } | |
844 | if (val & MII_BNX2_GP_TOP_AN_FD) | |
845 | bp->duplex = DUPLEX_FULL; | |
846 | else | |
847 | bp->duplex = DUPLEX_HALF; | |
848 | return 0; | |
849 | } | |
850 | ||
b6016b76 | 851 | static int |
5b0c76ad MC |
852 | bnx2_5708s_linkup(struct bnx2 *bp) |
853 | { | |
854 | u32 val; | |
855 | ||
856 | bp->link_up = 1; | |
857 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
858 | switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { | |
859 | case BCM5708S_1000X_STAT1_SPEED_10: | |
860 | bp->line_speed = SPEED_10; | |
861 | break; | |
862 | case BCM5708S_1000X_STAT1_SPEED_100: | |
863 | bp->line_speed = SPEED_100; | |
864 | break; | |
865 | case BCM5708S_1000X_STAT1_SPEED_1G: | |
866 | bp->line_speed = SPEED_1000; | |
867 | break; | |
868 | case BCM5708S_1000X_STAT1_SPEED_2G5: | |
869 | bp->line_speed = SPEED_2500; | |
870 | break; | |
871 | } | |
872 | if (val & BCM5708S_1000X_STAT1_FD) | |
873 | bp->duplex = DUPLEX_FULL; | |
874 | else | |
875 | bp->duplex = DUPLEX_HALF; | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | static int | |
881 | bnx2_5706s_linkup(struct bnx2 *bp) | |
b6016b76 MC |
882 | { |
883 | u32 bmcr, local_adv, remote_adv, common; | |
884 | ||
885 | bp->link_up = 1; | |
886 | bp->line_speed = SPEED_1000; | |
887 | ||
ca58c3af | 888 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
889 | if (bmcr & BMCR_FULLDPLX) { |
890 | bp->duplex = DUPLEX_FULL; | |
891 | } | |
892 | else { | |
893 | bp->duplex = DUPLEX_HALF; | |
894 | } | |
895 | ||
896 | if (!(bmcr & BMCR_ANENABLE)) { | |
897 | return 0; | |
898 | } | |
899 | ||
ca58c3af MC |
900 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
901 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
902 | |
903 | common = local_adv & remote_adv; | |
904 | if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { | |
905 | ||
906 | if (common & ADVERTISE_1000XFULL) { | |
907 | bp->duplex = DUPLEX_FULL; | |
908 | } | |
909 | else { | |
910 | bp->duplex = DUPLEX_HALF; | |
911 | } | |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static int | |
918 | bnx2_copper_linkup(struct bnx2 *bp) | |
919 | { | |
920 | u32 bmcr; | |
921 | ||
ca58c3af | 922 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
923 | if (bmcr & BMCR_ANENABLE) { |
924 | u32 local_adv, remote_adv, common; | |
925 | ||
926 | bnx2_read_phy(bp, MII_CTRL1000, &local_adv); | |
927 | bnx2_read_phy(bp, MII_STAT1000, &remote_adv); | |
928 | ||
929 | common = local_adv & (remote_adv >> 2); | |
930 | if (common & ADVERTISE_1000FULL) { | |
931 | bp->line_speed = SPEED_1000; | |
932 | bp->duplex = DUPLEX_FULL; | |
933 | } | |
934 | else if (common & ADVERTISE_1000HALF) { | |
935 | bp->line_speed = SPEED_1000; | |
936 | bp->duplex = DUPLEX_HALF; | |
937 | } | |
938 | else { | |
ca58c3af MC |
939 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
940 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
941 | |
942 | common = local_adv & remote_adv; | |
943 | if (common & ADVERTISE_100FULL) { | |
944 | bp->line_speed = SPEED_100; | |
945 | bp->duplex = DUPLEX_FULL; | |
946 | } | |
947 | else if (common & ADVERTISE_100HALF) { | |
948 | bp->line_speed = SPEED_100; | |
949 | bp->duplex = DUPLEX_HALF; | |
950 | } | |
951 | else if (common & ADVERTISE_10FULL) { | |
952 | bp->line_speed = SPEED_10; | |
953 | bp->duplex = DUPLEX_FULL; | |
954 | } | |
955 | else if (common & ADVERTISE_10HALF) { | |
956 | bp->line_speed = SPEED_10; | |
957 | bp->duplex = DUPLEX_HALF; | |
958 | } | |
959 | else { | |
960 | bp->line_speed = 0; | |
961 | bp->link_up = 0; | |
962 | } | |
963 | } | |
964 | } | |
965 | else { | |
966 | if (bmcr & BMCR_SPEED100) { | |
967 | bp->line_speed = SPEED_100; | |
968 | } | |
969 | else { | |
970 | bp->line_speed = SPEED_10; | |
971 | } | |
972 | if (bmcr & BMCR_FULLDPLX) { | |
973 | bp->duplex = DUPLEX_FULL; | |
974 | } | |
975 | else { | |
976 | bp->duplex = DUPLEX_HALF; | |
977 | } | |
978 | } | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | static int | |
984 | bnx2_set_mac_link(struct bnx2 *bp) | |
985 | { | |
986 | u32 val; | |
987 | ||
988 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); | |
989 | if (bp->link_up && (bp->line_speed == SPEED_1000) && | |
990 | (bp->duplex == DUPLEX_HALF)) { | |
991 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); | |
992 | } | |
993 | ||
994 | /* Configure the EMAC mode register. */ | |
995 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
996 | ||
997 | val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | |
5b0c76ad | 998 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | |
59b47d8a | 999 | BNX2_EMAC_MODE_25G_MODE); |
b6016b76 MC |
1000 | |
1001 | if (bp->link_up) { | |
5b0c76ad MC |
1002 | switch (bp->line_speed) { |
1003 | case SPEED_10: | |
59b47d8a MC |
1004 | if (CHIP_NUM(bp) != CHIP_NUM_5706) { |
1005 | val |= BNX2_EMAC_MODE_PORT_MII_10M; | |
5b0c76ad MC |
1006 | break; |
1007 | } | |
1008 | /* fall through */ | |
1009 | case SPEED_100: | |
1010 | val |= BNX2_EMAC_MODE_PORT_MII; | |
1011 | break; | |
1012 | case SPEED_2500: | |
59b47d8a | 1013 | val |= BNX2_EMAC_MODE_25G_MODE; |
5b0c76ad MC |
1014 | /* fall through */ |
1015 | case SPEED_1000: | |
1016 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1017 | break; | |
1018 | } | |
b6016b76 MC |
1019 | } |
1020 | else { | |
1021 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1022 | } | |
1023 | ||
1024 | /* Set the MAC to operate in the appropriate duplex mode. */ | |
1025 | if (bp->duplex == DUPLEX_HALF) | |
1026 | val |= BNX2_EMAC_MODE_HALF_DUPLEX; | |
1027 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
1028 | ||
1029 | /* Enable/disable rx PAUSE. */ | |
1030 | bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; | |
1031 | ||
1032 | if (bp->flow_ctrl & FLOW_CTRL_RX) | |
1033 | bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; | |
1034 | REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); | |
1035 | ||
1036 | /* Enable/disable tx PAUSE. */ | |
1037 | val = REG_RD(bp, BNX2_EMAC_TX_MODE); | |
1038 | val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; | |
1039 | ||
1040 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
1041 | val |= BNX2_EMAC_TX_MODE_FLOW_EN; | |
1042 | REG_WR(bp, BNX2_EMAC_TX_MODE, val); | |
1043 | ||
1044 | /* Acknowledge the interrupt. */ | |
1045 | REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
27a005b8 MC |
1050 | static void |
1051 | bnx2_enable_bmsr1(struct bnx2 *bp) | |
1052 | { | |
1053 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | |
1054 | (CHIP_NUM(bp) == CHIP_NUM_5709)) | |
1055 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1056 | MII_BNX2_BLK_ADDR_GP_STATUS); | |
1057 | } | |
1058 | ||
1059 | static void | |
1060 | bnx2_disable_bmsr1(struct bnx2 *bp) | |
1061 | { | |
1062 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | |
1063 | (CHIP_NUM(bp) == CHIP_NUM_5709)) | |
1064 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1065 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1066 | } | |
1067 | ||
605a9e20 MC |
1068 | static int |
1069 | bnx2_test_and_enable_2g5(struct bnx2 *bp) | |
1070 | { | |
1071 | u32 up1; | |
1072 | int ret = 1; | |
1073 | ||
1074 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | |
1075 | return 0; | |
1076 | ||
1077 | if (bp->autoneg & AUTONEG_SPEED) | |
1078 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1079 | ||
27a005b8 MC |
1080 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1081 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
1082 | ||
605a9e20 MC |
1083 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1084 | if (!(up1 & BCM5708S_UP1_2G5)) { | |
1085 | up1 |= BCM5708S_UP1_2G5; | |
1086 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1087 | ret = 0; | |
1088 | } | |
1089 | ||
27a005b8 MC |
1090 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1091 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1092 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1093 | ||
605a9e20 MC |
1094 | return ret; |
1095 | } | |
1096 | ||
1097 | static int | |
1098 | bnx2_test_and_disable_2g5(struct bnx2 *bp) | |
1099 | { | |
1100 | u32 up1; | |
1101 | int ret = 0; | |
1102 | ||
1103 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | |
1104 | return 0; | |
1105 | ||
27a005b8 MC |
1106 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1107 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
1108 | ||
605a9e20 MC |
1109 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1110 | if (up1 & BCM5708S_UP1_2G5) { | |
1111 | up1 &= ~BCM5708S_UP1_2G5; | |
1112 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1113 | ret = 1; | |
1114 | } | |
1115 | ||
27a005b8 MC |
1116 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1117 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1118 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1119 | ||
605a9e20 MC |
1120 | return ret; |
1121 | } | |
1122 | ||
1123 | static void | |
1124 | bnx2_enable_forced_2g5(struct bnx2 *bp) | |
1125 | { | |
1126 | u32 bmcr; | |
1127 | ||
1128 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | |
1129 | return; | |
1130 | ||
27a005b8 MC |
1131 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
1132 | u32 val; | |
1133 | ||
1134 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1135 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
1136 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); | |
1137 | val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; | |
1138 | val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G; | |
1139 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1140 | ||
1141 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1142 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1143 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
1144 | ||
1145 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | |
605a9e20 MC |
1146 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1147 | bmcr |= BCM5708S_BMCR_FORCE_2500; | |
1148 | } | |
1149 | ||
1150 | if (bp->autoneg & AUTONEG_SPEED) { | |
1151 | bmcr &= ~BMCR_ANENABLE; | |
1152 | if (bp->req_duplex == DUPLEX_FULL) | |
1153 | bmcr |= BMCR_FULLDPLX; | |
1154 | } | |
1155 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1156 | } | |
1157 | ||
1158 | static void | |
1159 | bnx2_disable_forced_2g5(struct bnx2 *bp) | |
1160 | { | |
1161 | u32 bmcr; | |
1162 | ||
1163 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | |
1164 | return; | |
1165 | ||
27a005b8 MC |
1166 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
1167 | u32 val; | |
1168 | ||
1169 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1170 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
1171 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); | |
1172 | val &= ~MII_BNX2_SD_MISC1_FORCE; | |
1173 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1174 | ||
1175 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1176 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1177 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
1178 | ||
1179 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | |
605a9e20 MC |
1180 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1181 | bmcr &= ~BCM5708S_BMCR_FORCE_2500; | |
1182 | } | |
1183 | ||
1184 | if (bp->autoneg & AUTONEG_SPEED) | |
1185 | bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; | |
1186 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1187 | } | |
1188 | ||
b6016b76 MC |
1189 | static int |
1190 | bnx2_set_link(struct bnx2 *bp) | |
1191 | { | |
1192 | u32 bmsr; | |
1193 | u8 link_up; | |
1194 | ||
80be4434 | 1195 | if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { |
b6016b76 MC |
1196 | bp->link_up = 1; |
1197 | return 0; | |
1198 | } | |
1199 | ||
0d8a6571 MC |
1200 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
1201 | return 0; | |
1202 | ||
b6016b76 MC |
1203 | link_up = bp->link_up; |
1204 | ||
27a005b8 MC |
1205 | bnx2_enable_bmsr1(bp); |
1206 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1207 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1208 | bnx2_disable_bmsr1(bp); | |
b6016b76 MC |
1209 | |
1210 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | |
1211 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { | |
1212 | u32 val; | |
1213 | ||
1214 | val = REG_RD(bp, BNX2_EMAC_STATUS); | |
1215 | if (val & BNX2_EMAC_STATUS_LINK) | |
1216 | bmsr |= BMSR_LSTATUS; | |
1217 | else | |
1218 | bmsr &= ~BMSR_LSTATUS; | |
1219 | } | |
1220 | ||
1221 | if (bmsr & BMSR_LSTATUS) { | |
1222 | bp->link_up = 1; | |
1223 | ||
1224 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
5b0c76ad MC |
1225 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
1226 | bnx2_5706s_linkup(bp); | |
1227 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) | |
1228 | bnx2_5708s_linkup(bp); | |
27a005b8 MC |
1229 | else if (CHIP_NUM(bp) == CHIP_NUM_5709) |
1230 | bnx2_5709s_linkup(bp); | |
b6016b76 MC |
1231 | } |
1232 | else { | |
1233 | bnx2_copper_linkup(bp); | |
1234 | } | |
1235 | bnx2_resolve_flow_ctrl(bp); | |
1236 | } | |
1237 | else { | |
1238 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | |
605a9e20 MC |
1239 | (bp->autoneg & AUTONEG_SPEED)) |
1240 | bnx2_disable_forced_2g5(bp); | |
b6016b76 | 1241 | |
b6016b76 MC |
1242 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; |
1243 | bp->link_up = 0; | |
1244 | } | |
1245 | ||
1246 | if (bp->link_up != link_up) { | |
1247 | bnx2_report_link(bp); | |
1248 | } | |
1249 | ||
1250 | bnx2_set_mac_link(bp); | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static int | |
1256 | bnx2_reset_phy(struct bnx2 *bp) | |
1257 | { | |
1258 | int i; | |
1259 | u32 reg; | |
1260 | ||
ca58c3af | 1261 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); |
b6016b76 MC |
1262 | |
1263 | #define PHY_RESET_MAX_WAIT 100 | |
1264 | for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { | |
1265 | udelay(10); | |
1266 | ||
ca58c3af | 1267 | bnx2_read_phy(bp, bp->mii_bmcr, ®); |
b6016b76 MC |
1268 | if (!(reg & BMCR_RESET)) { |
1269 | udelay(20); | |
1270 | break; | |
1271 | } | |
1272 | } | |
1273 | if (i == PHY_RESET_MAX_WAIT) { | |
1274 | return -EBUSY; | |
1275 | } | |
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | static u32 | |
1280 | bnx2_phy_get_pause_adv(struct bnx2 *bp) | |
1281 | { | |
1282 | u32 adv = 0; | |
1283 | ||
1284 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == | |
1285 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { | |
1286 | ||
1287 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
1288 | adv = ADVERTISE_1000XPAUSE; | |
1289 | } | |
1290 | else { | |
1291 | adv = ADVERTISE_PAUSE_CAP; | |
1292 | } | |
1293 | } | |
1294 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { | |
1295 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
1296 | adv = ADVERTISE_1000XPSE_ASYM; | |
1297 | } | |
1298 | else { | |
1299 | adv = ADVERTISE_PAUSE_ASYM; | |
1300 | } | |
1301 | } | |
1302 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { | |
1303 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
1304 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | |
1305 | } | |
1306 | else { | |
1307 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1308 | } | |
1309 | } | |
1310 | return adv; | |
1311 | } | |
1312 | ||
0d8a6571 MC |
1313 | static int bnx2_fw_sync(struct bnx2 *, u32, int); |
1314 | ||
b6016b76 | 1315 | static int |
0d8a6571 MC |
1316 | bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) |
1317 | { | |
1318 | u32 speed_arg = 0, pause_adv; | |
1319 | ||
1320 | pause_adv = bnx2_phy_get_pause_adv(bp); | |
1321 | ||
1322 | if (bp->autoneg & AUTONEG_SPEED) { | |
1323 | speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; | |
1324 | if (bp->advertising & ADVERTISED_10baseT_Half) | |
1325 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1326 | if (bp->advertising & ADVERTISED_10baseT_Full) | |
1327 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1328 | if (bp->advertising & ADVERTISED_100baseT_Half) | |
1329 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1330 | if (bp->advertising & ADVERTISED_100baseT_Full) | |
1331 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1332 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
1333 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1334 | if (bp->advertising & ADVERTISED_2500baseX_Full) | |
1335 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1336 | } else { | |
1337 | if (bp->req_line_speed == SPEED_2500) | |
1338 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1339 | else if (bp->req_line_speed == SPEED_1000) | |
1340 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1341 | else if (bp->req_line_speed == SPEED_100) { | |
1342 | if (bp->req_duplex == DUPLEX_FULL) | |
1343 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1344 | else | |
1345 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1346 | } else if (bp->req_line_speed == SPEED_10) { | |
1347 | if (bp->req_duplex == DUPLEX_FULL) | |
1348 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1349 | else | |
1350 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) | |
1355 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; | |
1356 | if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM)) | |
1357 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; | |
1358 | ||
1359 | if (port == PORT_TP) | |
1360 | speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | | |
1361 | BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; | |
1362 | ||
1363 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg); | |
1364 | ||
1365 | spin_unlock_bh(&bp->phy_lock); | |
1366 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0); | |
1367 | spin_lock_bh(&bp->phy_lock); | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | static int | |
1373 | bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) | |
b6016b76 | 1374 | { |
605a9e20 | 1375 | u32 adv, bmcr; |
b6016b76 MC |
1376 | u32 new_adv = 0; |
1377 | ||
0d8a6571 MC |
1378 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
1379 | return (bnx2_setup_remote_phy(bp, port)); | |
1380 | ||
b6016b76 MC |
1381 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
1382 | u32 new_bmcr; | |
5b0c76ad MC |
1383 | int force_link_down = 0; |
1384 | ||
605a9e20 MC |
1385 | if (bp->req_line_speed == SPEED_2500) { |
1386 | if (!bnx2_test_and_enable_2g5(bp)) | |
1387 | force_link_down = 1; | |
1388 | } else if (bp->req_line_speed == SPEED_1000) { | |
1389 | if (bnx2_test_and_disable_2g5(bp)) | |
1390 | force_link_down = 1; | |
1391 | } | |
ca58c3af | 1392 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
80be4434 MC |
1393 | adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); |
1394 | ||
ca58c3af | 1395 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
605a9e20 | 1396 | new_bmcr = bmcr & ~BMCR_ANENABLE; |
80be4434 | 1397 | new_bmcr |= BMCR_SPEED1000; |
605a9e20 | 1398 | |
27a005b8 MC |
1399 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
1400 | if (bp->req_line_speed == SPEED_2500) | |
1401 | bnx2_enable_forced_2g5(bp); | |
1402 | else if (bp->req_line_speed == SPEED_1000) { | |
1403 | bnx2_disable_forced_2g5(bp); | |
1404 | new_bmcr &= ~0x2000; | |
1405 | } | |
1406 | ||
1407 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | |
605a9e20 MC |
1408 | if (bp->req_line_speed == SPEED_2500) |
1409 | new_bmcr |= BCM5708S_BMCR_FORCE_2500; | |
1410 | else | |
1411 | new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; | |
5b0c76ad MC |
1412 | } |
1413 | ||
b6016b76 | 1414 | if (bp->req_duplex == DUPLEX_FULL) { |
5b0c76ad | 1415 | adv |= ADVERTISE_1000XFULL; |
b6016b76 MC |
1416 | new_bmcr |= BMCR_FULLDPLX; |
1417 | } | |
1418 | else { | |
5b0c76ad | 1419 | adv |= ADVERTISE_1000XHALF; |
b6016b76 MC |
1420 | new_bmcr &= ~BMCR_FULLDPLX; |
1421 | } | |
5b0c76ad | 1422 | if ((new_bmcr != bmcr) || (force_link_down)) { |
b6016b76 MC |
1423 | /* Force a link down visible on the other side */ |
1424 | if (bp->link_up) { | |
ca58c3af | 1425 | bnx2_write_phy(bp, bp->mii_adv, adv & |
5b0c76ad MC |
1426 | ~(ADVERTISE_1000XFULL | |
1427 | ADVERTISE_1000XHALF)); | |
ca58c3af | 1428 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | |
b6016b76 MC |
1429 | BMCR_ANRESTART | BMCR_ANENABLE); |
1430 | ||
1431 | bp->link_up = 0; | |
1432 | netif_carrier_off(bp->dev); | |
ca58c3af | 1433 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
80be4434 | 1434 | bnx2_report_link(bp); |
b6016b76 | 1435 | } |
ca58c3af MC |
1436 | bnx2_write_phy(bp, bp->mii_adv, adv); |
1437 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); | |
605a9e20 MC |
1438 | } else { |
1439 | bnx2_resolve_flow_ctrl(bp); | |
1440 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1441 | } |
1442 | return 0; | |
1443 | } | |
1444 | ||
605a9e20 | 1445 | bnx2_test_and_enable_2g5(bp); |
5b0c76ad | 1446 | |
b6016b76 MC |
1447 | if (bp->advertising & ADVERTISED_1000baseT_Full) |
1448 | new_adv |= ADVERTISE_1000XFULL; | |
1449 | ||
1450 | new_adv |= bnx2_phy_get_pause_adv(bp); | |
1451 | ||
ca58c3af MC |
1452 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
1453 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
b6016b76 MC |
1454 | |
1455 | bp->serdes_an_pending = 0; | |
1456 | if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { | |
1457 | /* Force a link down visible on the other side */ | |
1458 | if (bp->link_up) { | |
ca58c3af | 1459 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
80be4434 MC |
1460 | spin_unlock_bh(&bp->phy_lock); |
1461 | msleep(20); | |
1462 | spin_lock_bh(&bp->phy_lock); | |
b6016b76 MC |
1463 | } |
1464 | ||
ca58c3af MC |
1465 | bnx2_write_phy(bp, bp->mii_adv, new_adv); |
1466 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | | |
b6016b76 | 1467 | BMCR_ANENABLE); |
f8dd064e MC |
1468 | /* Speed up link-up time when the link partner |
1469 | * does not autonegotiate which is very common | |
1470 | * in blade servers. Some blade servers use | |
1471 | * IPMI for kerboard input and it's important | |
1472 | * to minimize link disruptions. Autoneg. involves | |
1473 | * exchanging base pages plus 3 next pages and | |
1474 | * normally completes in about 120 msec. | |
1475 | */ | |
1476 | bp->current_interval = SERDES_AN_TIMEOUT; | |
1477 | bp->serdes_an_pending = 1; | |
1478 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
605a9e20 MC |
1479 | } else { |
1480 | bnx2_resolve_flow_ctrl(bp); | |
1481 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1482 | } |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
1487 | #define ETHTOOL_ALL_FIBRE_SPEED \ | |
deaf391b MC |
1488 | (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ? \ |
1489 | (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ | |
1490 | (ADVERTISED_1000baseT_Full) | |
b6016b76 MC |
1491 | |
1492 | #define ETHTOOL_ALL_COPPER_SPEED \ | |
1493 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ | |
1494 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ | |
1495 | ADVERTISED_1000baseT_Full) | |
1496 | ||
1497 | #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ | |
1498 | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) | |
6aa20a22 | 1499 | |
b6016b76 MC |
1500 | #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) |
1501 | ||
0d8a6571 MC |
1502 | static void |
1503 | bnx2_set_default_remote_link(struct bnx2 *bp) | |
1504 | { | |
1505 | u32 link; | |
1506 | ||
1507 | if (bp->phy_port == PORT_TP) | |
1508 | link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK); | |
1509 | else | |
1510 | link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK); | |
1511 | ||
1512 | if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { | |
1513 | bp->req_line_speed = 0; | |
1514 | bp->autoneg |= AUTONEG_SPEED; | |
1515 | bp->advertising = ADVERTISED_Autoneg; | |
1516 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1517 | bp->advertising |= ADVERTISED_10baseT_Half; | |
1518 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) | |
1519 | bp->advertising |= ADVERTISED_10baseT_Full; | |
1520 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1521 | bp->advertising |= ADVERTISED_100baseT_Half; | |
1522 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) | |
1523 | bp->advertising |= ADVERTISED_100baseT_Full; | |
1524 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1525 | bp->advertising |= ADVERTISED_1000baseT_Full; | |
1526 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1527 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1528 | } else { | |
1529 | bp->autoneg = 0; | |
1530 | bp->advertising = 0; | |
1531 | bp->req_duplex = DUPLEX_FULL; | |
1532 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { | |
1533 | bp->req_line_speed = SPEED_10; | |
1534 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1535 | bp->req_duplex = DUPLEX_HALF; | |
1536 | } | |
1537 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { | |
1538 | bp->req_line_speed = SPEED_100; | |
1539 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1540 | bp->req_duplex = DUPLEX_HALF; | |
1541 | } | |
1542 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1543 | bp->req_line_speed = SPEED_1000; | |
1544 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1545 | bp->req_line_speed = SPEED_2500; | |
1546 | } | |
1547 | } | |
1548 | ||
deaf391b MC |
1549 | static void |
1550 | bnx2_set_default_link(struct bnx2 *bp) | |
1551 | { | |
0d8a6571 MC |
1552 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
1553 | return bnx2_set_default_remote_link(bp); | |
1554 | ||
deaf391b MC |
1555 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; |
1556 | bp->req_line_speed = 0; | |
1557 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
1558 | u32 reg; | |
1559 | ||
1560 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | |
1561 | ||
1562 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG); | |
1563 | reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; | |
1564 | if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { | |
1565 | bp->autoneg = 0; | |
1566 | bp->req_line_speed = bp->line_speed = SPEED_1000; | |
1567 | bp->req_duplex = DUPLEX_FULL; | |
1568 | } | |
1569 | } else | |
1570 | bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; | |
1571 | } | |
1572 | ||
df149d70 MC |
1573 | static void |
1574 | bnx2_send_heart_beat(struct bnx2 *bp) | |
1575 | { | |
1576 | u32 msg; | |
1577 | u32 addr; | |
1578 | ||
1579 | spin_lock(&bp->indirect_lock); | |
1580 | msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); | |
1581 | addr = bp->shmem_base + BNX2_DRV_PULSE_MB; | |
1582 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); | |
1583 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); | |
1584 | spin_unlock(&bp->indirect_lock); | |
1585 | } | |
1586 | ||
0d8a6571 MC |
1587 | static void |
1588 | bnx2_remote_phy_event(struct bnx2 *bp) | |
1589 | { | |
1590 | u32 msg; | |
1591 | u8 link_up = bp->link_up; | |
1592 | u8 old_port; | |
1593 | ||
1594 | msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); | |
1595 | ||
df149d70 MC |
1596 | if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) |
1597 | bnx2_send_heart_beat(bp); | |
1598 | ||
1599 | msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; | |
1600 | ||
0d8a6571 MC |
1601 | if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) |
1602 | bp->link_up = 0; | |
1603 | else { | |
1604 | u32 speed; | |
1605 | ||
1606 | bp->link_up = 1; | |
1607 | speed = msg & BNX2_LINK_STATUS_SPEED_MASK; | |
1608 | bp->duplex = DUPLEX_FULL; | |
1609 | switch (speed) { | |
1610 | case BNX2_LINK_STATUS_10HALF: | |
1611 | bp->duplex = DUPLEX_HALF; | |
1612 | case BNX2_LINK_STATUS_10FULL: | |
1613 | bp->line_speed = SPEED_10; | |
1614 | break; | |
1615 | case BNX2_LINK_STATUS_100HALF: | |
1616 | bp->duplex = DUPLEX_HALF; | |
1617 | case BNX2_LINK_STATUS_100BASE_T4: | |
1618 | case BNX2_LINK_STATUS_100FULL: | |
1619 | bp->line_speed = SPEED_100; | |
1620 | break; | |
1621 | case BNX2_LINK_STATUS_1000HALF: | |
1622 | bp->duplex = DUPLEX_HALF; | |
1623 | case BNX2_LINK_STATUS_1000FULL: | |
1624 | bp->line_speed = SPEED_1000; | |
1625 | break; | |
1626 | case BNX2_LINK_STATUS_2500HALF: | |
1627 | bp->duplex = DUPLEX_HALF; | |
1628 | case BNX2_LINK_STATUS_2500FULL: | |
1629 | bp->line_speed = SPEED_2500; | |
1630 | break; | |
1631 | default: | |
1632 | bp->line_speed = 0; | |
1633 | break; | |
1634 | } | |
1635 | ||
1636 | spin_lock(&bp->phy_lock); | |
1637 | bp->flow_ctrl = 0; | |
1638 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != | |
1639 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { | |
1640 | if (bp->duplex == DUPLEX_FULL) | |
1641 | bp->flow_ctrl = bp->req_flow_ctrl; | |
1642 | } else { | |
1643 | if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED) | |
1644 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
1645 | if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED) | |
1646 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
1647 | } | |
1648 | ||
1649 | old_port = bp->phy_port; | |
1650 | if (msg & BNX2_LINK_STATUS_SERDES_LINK) | |
1651 | bp->phy_port = PORT_FIBRE; | |
1652 | else | |
1653 | bp->phy_port = PORT_TP; | |
1654 | ||
1655 | if (old_port != bp->phy_port) | |
1656 | bnx2_set_default_link(bp); | |
1657 | ||
1658 | spin_unlock(&bp->phy_lock); | |
1659 | } | |
1660 | if (bp->link_up != link_up) | |
1661 | bnx2_report_link(bp); | |
1662 | ||
1663 | bnx2_set_mac_link(bp); | |
1664 | } | |
1665 | ||
1666 | static int | |
1667 | bnx2_set_remote_link(struct bnx2 *bp) | |
1668 | { | |
1669 | u32 evt_code; | |
1670 | ||
1671 | evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB); | |
1672 | switch (evt_code) { | |
1673 | case BNX2_FW_EVT_CODE_LINK_EVENT: | |
1674 | bnx2_remote_phy_event(bp); | |
1675 | break; | |
1676 | case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: | |
1677 | default: | |
df149d70 | 1678 | bnx2_send_heart_beat(bp); |
0d8a6571 MC |
1679 | break; |
1680 | } | |
1681 | return 0; | |
1682 | } | |
1683 | ||
b6016b76 MC |
1684 | static int |
1685 | bnx2_setup_copper_phy(struct bnx2 *bp) | |
1686 | { | |
1687 | u32 bmcr; | |
1688 | u32 new_bmcr; | |
1689 | ||
ca58c3af | 1690 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
1691 | |
1692 | if (bp->autoneg & AUTONEG_SPEED) { | |
1693 | u32 adv_reg, adv1000_reg; | |
1694 | u32 new_adv_reg = 0; | |
1695 | u32 new_adv1000_reg = 0; | |
1696 | ||
ca58c3af | 1697 | bnx2_read_phy(bp, bp->mii_adv, &adv_reg); |
b6016b76 MC |
1698 | adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | |
1699 | ADVERTISE_PAUSE_ASYM); | |
1700 | ||
1701 | bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); | |
1702 | adv1000_reg &= PHY_ALL_1000_SPEED; | |
1703 | ||
1704 | if (bp->advertising & ADVERTISED_10baseT_Half) | |
1705 | new_adv_reg |= ADVERTISE_10HALF; | |
1706 | if (bp->advertising & ADVERTISED_10baseT_Full) | |
1707 | new_adv_reg |= ADVERTISE_10FULL; | |
1708 | if (bp->advertising & ADVERTISED_100baseT_Half) | |
1709 | new_adv_reg |= ADVERTISE_100HALF; | |
1710 | if (bp->advertising & ADVERTISED_100baseT_Full) | |
1711 | new_adv_reg |= ADVERTISE_100FULL; | |
1712 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
1713 | new_adv1000_reg |= ADVERTISE_1000FULL; | |
6aa20a22 | 1714 | |
b6016b76 MC |
1715 | new_adv_reg |= ADVERTISE_CSMA; |
1716 | ||
1717 | new_adv_reg |= bnx2_phy_get_pause_adv(bp); | |
1718 | ||
1719 | if ((adv1000_reg != new_adv1000_reg) || | |
1720 | (adv_reg != new_adv_reg) || | |
1721 | ((bmcr & BMCR_ANENABLE) == 0)) { | |
1722 | ||
ca58c3af | 1723 | bnx2_write_phy(bp, bp->mii_adv, new_adv_reg); |
b6016b76 | 1724 | bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg); |
ca58c3af | 1725 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | |
b6016b76 MC |
1726 | BMCR_ANENABLE); |
1727 | } | |
1728 | else if (bp->link_up) { | |
1729 | /* Flow ctrl may have changed from auto to forced */ | |
1730 | /* or vice-versa. */ | |
1731 | ||
1732 | bnx2_resolve_flow_ctrl(bp); | |
1733 | bnx2_set_mac_link(bp); | |
1734 | } | |
1735 | return 0; | |
1736 | } | |
1737 | ||
1738 | new_bmcr = 0; | |
1739 | if (bp->req_line_speed == SPEED_100) { | |
1740 | new_bmcr |= BMCR_SPEED100; | |
1741 | } | |
1742 | if (bp->req_duplex == DUPLEX_FULL) { | |
1743 | new_bmcr |= BMCR_FULLDPLX; | |
1744 | } | |
1745 | if (new_bmcr != bmcr) { | |
1746 | u32 bmsr; | |
b6016b76 | 1747 | |
ca58c3af MC |
1748 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
1749 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
6aa20a22 | 1750 | |
b6016b76 MC |
1751 | if (bmsr & BMSR_LSTATUS) { |
1752 | /* Force link down */ | |
ca58c3af | 1753 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
a16dda0e MC |
1754 | spin_unlock_bh(&bp->phy_lock); |
1755 | msleep(50); | |
1756 | spin_lock_bh(&bp->phy_lock); | |
1757 | ||
ca58c3af MC |
1758 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
1759 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
b6016b76 MC |
1760 | } |
1761 | ||
ca58c3af | 1762 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
b6016b76 MC |
1763 | |
1764 | /* Normally, the new speed is setup after the link has | |
1765 | * gone down and up again. In some cases, link will not go | |
1766 | * down so we need to set up the new speed here. | |
1767 | */ | |
1768 | if (bmsr & BMSR_LSTATUS) { | |
1769 | bp->line_speed = bp->req_line_speed; | |
1770 | bp->duplex = bp->req_duplex; | |
1771 | bnx2_resolve_flow_ctrl(bp); | |
1772 | bnx2_set_mac_link(bp); | |
1773 | } | |
27a005b8 MC |
1774 | } else { |
1775 | bnx2_resolve_flow_ctrl(bp); | |
1776 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1777 | } |
1778 | return 0; | |
1779 | } | |
1780 | ||
1781 | static int | |
0d8a6571 | 1782 | bnx2_setup_phy(struct bnx2 *bp, u8 port) |
b6016b76 MC |
1783 | { |
1784 | if (bp->loopback == MAC_LOOPBACK) | |
1785 | return 0; | |
1786 | ||
1787 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
0d8a6571 | 1788 | return (bnx2_setup_serdes_phy(bp, port)); |
b6016b76 MC |
1789 | } |
1790 | else { | |
1791 | return (bnx2_setup_copper_phy(bp)); | |
1792 | } | |
1793 | } | |
1794 | ||
27a005b8 MC |
1795 | static int |
1796 | bnx2_init_5709s_phy(struct bnx2 *bp) | |
1797 | { | |
1798 | u32 val; | |
1799 | ||
1800 | bp->mii_bmcr = MII_BMCR + 0x10; | |
1801 | bp->mii_bmsr = MII_BMSR + 0x10; | |
1802 | bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; | |
1803 | bp->mii_adv = MII_ADVERTISE + 0x10; | |
1804 | bp->mii_lpa = MII_LPA + 0x10; | |
1805 | bp->mii_up1 = MII_BNX2_OVER1G_UP1; | |
1806 | ||
1807 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); | |
1808 | bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); | |
1809 | ||
1810 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1811 | bnx2_reset_phy(bp); | |
1812 | ||
1813 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); | |
1814 | ||
1815 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); | |
1816 | val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; | |
1817 | val |= MII_BNX2_SD_1000XCTL1_FIBER; | |
1818 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); | |
1819 | ||
1820 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
1821 | bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); | |
1822 | if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) | |
1823 | val |= BCM5708S_UP1_2G5; | |
1824 | else | |
1825 | val &= ~BCM5708S_UP1_2G5; | |
1826 | bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); | |
1827 | ||
1828 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); | |
1829 | bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); | |
1830 | val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; | |
1831 | bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); | |
1832 | ||
1833 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); | |
1834 | ||
1835 | val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | | |
1836 | MII_BNX2_CL73_BAM_NP_AFT_BP_EN; | |
1837 | bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); | |
1838 | ||
1839 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1840 | ||
1841 | return 0; | |
1842 | } | |
1843 | ||
b6016b76 | 1844 | static int |
5b0c76ad MC |
1845 | bnx2_init_5708s_phy(struct bnx2 *bp) |
1846 | { | |
1847 | u32 val; | |
1848 | ||
27a005b8 MC |
1849 | bnx2_reset_phy(bp); |
1850 | ||
1851 | bp->mii_up1 = BCM5708S_UP1; | |
1852 | ||
5b0c76ad MC |
1853 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); |
1854 | bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); | |
1855 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
1856 | ||
1857 | bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); | |
1858 | val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; | |
1859 | bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); | |
1860 | ||
1861 | bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); | |
1862 | val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; | |
1863 | bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); | |
1864 | ||
1865 | if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) { | |
1866 | bnx2_read_phy(bp, BCM5708S_UP1, &val); | |
1867 | val |= BCM5708S_UP1_2G5; | |
1868 | bnx2_write_phy(bp, BCM5708S_UP1, val); | |
1869 | } | |
1870 | ||
1871 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || | |
dda1e390 MC |
1872 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || |
1873 | (CHIP_ID(bp) == CHIP_ID_5708_B1)) { | |
5b0c76ad MC |
1874 | /* increase tx signal amplitude */ |
1875 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
1876 | BCM5708S_BLK_ADDR_TX_MISC); | |
1877 | bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); | |
1878 | val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; | |
1879 | bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); | |
1880 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
1881 | } | |
1882 | ||
e3648b3d | 1883 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) & |
5b0c76ad MC |
1884 | BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; |
1885 | ||
1886 | if (val) { | |
1887 | u32 is_backplane; | |
1888 | ||
e3648b3d | 1889 | is_backplane = REG_RD_IND(bp, bp->shmem_base + |
5b0c76ad MC |
1890 | BNX2_SHARED_HW_CFG_CONFIG); |
1891 | if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { | |
1892 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
1893 | BCM5708S_BLK_ADDR_TX_MISC); | |
1894 | bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); | |
1895 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
1896 | BCM5708S_BLK_ADDR_DIG); | |
1897 | } | |
1898 | } | |
1899 | return 0; | |
1900 | } | |
1901 | ||
1902 | static int | |
1903 | bnx2_init_5706s_phy(struct bnx2 *bp) | |
b6016b76 | 1904 | { |
27a005b8 MC |
1905 | bnx2_reset_phy(bp); |
1906 | ||
b6016b76 MC |
1907 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; |
1908 | ||
59b47d8a MC |
1909 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
1910 | REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); | |
b6016b76 MC |
1911 | |
1912 | if (bp->dev->mtu > 1500) { | |
1913 | u32 val; | |
1914 | ||
1915 | /* Set extended packet length bit */ | |
1916 | bnx2_write_phy(bp, 0x18, 0x7); | |
1917 | bnx2_read_phy(bp, 0x18, &val); | |
1918 | bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); | |
1919 | ||
1920 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
1921 | bnx2_read_phy(bp, 0x1c, &val); | |
1922 | bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); | |
1923 | } | |
1924 | else { | |
1925 | u32 val; | |
1926 | ||
1927 | bnx2_write_phy(bp, 0x18, 0x7); | |
1928 | bnx2_read_phy(bp, 0x18, &val); | |
1929 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
1930 | ||
1931 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
1932 | bnx2_read_phy(bp, 0x1c, &val); | |
1933 | bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); | |
1934 | } | |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
1939 | static int | |
1940 | bnx2_init_copper_phy(struct bnx2 *bp) | |
1941 | { | |
5b0c76ad MC |
1942 | u32 val; |
1943 | ||
27a005b8 MC |
1944 | bnx2_reset_phy(bp); |
1945 | ||
b6016b76 MC |
1946 | if (bp->phy_flags & PHY_CRC_FIX_FLAG) { |
1947 | bnx2_write_phy(bp, 0x18, 0x0c00); | |
1948 | bnx2_write_phy(bp, 0x17, 0x000a); | |
1949 | bnx2_write_phy(bp, 0x15, 0x310b); | |
1950 | bnx2_write_phy(bp, 0x17, 0x201f); | |
1951 | bnx2_write_phy(bp, 0x15, 0x9506); | |
1952 | bnx2_write_phy(bp, 0x17, 0x401f); | |
1953 | bnx2_write_phy(bp, 0x15, 0x14e2); | |
1954 | bnx2_write_phy(bp, 0x18, 0x0400); | |
1955 | } | |
1956 | ||
b659f44e MC |
1957 | if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) { |
1958 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, | |
1959 | MII_BNX2_DSP_EXPAND_REG | 0x8); | |
1960 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
1961 | val &= ~(1 << 8); | |
1962 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); | |
1963 | } | |
1964 | ||
b6016b76 | 1965 | if (bp->dev->mtu > 1500) { |
b6016b76 MC |
1966 | /* Set extended packet length bit */ |
1967 | bnx2_write_phy(bp, 0x18, 0x7); | |
1968 | bnx2_read_phy(bp, 0x18, &val); | |
1969 | bnx2_write_phy(bp, 0x18, val | 0x4000); | |
1970 | ||
1971 | bnx2_read_phy(bp, 0x10, &val); | |
1972 | bnx2_write_phy(bp, 0x10, val | 0x1); | |
1973 | } | |
1974 | else { | |
b6016b76 MC |
1975 | bnx2_write_phy(bp, 0x18, 0x7); |
1976 | bnx2_read_phy(bp, 0x18, &val); | |
1977 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
1978 | ||
1979 | bnx2_read_phy(bp, 0x10, &val); | |
1980 | bnx2_write_phy(bp, 0x10, val & ~0x1); | |
1981 | } | |
1982 | ||
5b0c76ad MC |
1983 | /* ethernet@wirespeed */ |
1984 | bnx2_write_phy(bp, 0x18, 0x7007); | |
1985 | bnx2_read_phy(bp, 0x18, &val); | |
1986 | bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4)); | |
b6016b76 MC |
1987 | return 0; |
1988 | } | |
1989 | ||
1990 | ||
1991 | static int | |
1992 | bnx2_init_phy(struct bnx2 *bp) | |
1993 | { | |
1994 | u32 val; | |
1995 | int rc = 0; | |
1996 | ||
1997 | bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG; | |
1998 | bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG; | |
1999 | ||
ca58c3af MC |
2000 | bp->mii_bmcr = MII_BMCR; |
2001 | bp->mii_bmsr = MII_BMSR; | |
27a005b8 | 2002 | bp->mii_bmsr1 = MII_BMSR; |
ca58c3af MC |
2003 | bp->mii_adv = MII_ADVERTISE; |
2004 | bp->mii_lpa = MII_LPA; | |
2005 | ||
b6016b76 MC |
2006 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); |
2007 | ||
0d8a6571 MC |
2008 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
2009 | goto setup_phy; | |
2010 | ||
b6016b76 MC |
2011 | bnx2_read_phy(bp, MII_PHYSID1, &val); |
2012 | bp->phy_id = val << 16; | |
2013 | bnx2_read_phy(bp, MII_PHYSID2, &val); | |
2014 | bp->phy_id |= val & 0xffff; | |
2015 | ||
2016 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
5b0c76ad MC |
2017 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
2018 | rc = bnx2_init_5706s_phy(bp); | |
2019 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) | |
2020 | rc = bnx2_init_5708s_phy(bp); | |
27a005b8 MC |
2021 | else if (CHIP_NUM(bp) == CHIP_NUM_5709) |
2022 | rc = bnx2_init_5709s_phy(bp); | |
b6016b76 MC |
2023 | } |
2024 | else { | |
2025 | rc = bnx2_init_copper_phy(bp); | |
2026 | } | |
2027 | ||
0d8a6571 MC |
2028 | setup_phy: |
2029 | if (!rc) | |
2030 | rc = bnx2_setup_phy(bp, bp->phy_port); | |
b6016b76 MC |
2031 | |
2032 | return rc; | |
2033 | } | |
2034 | ||
2035 | static int | |
2036 | bnx2_set_mac_loopback(struct bnx2 *bp) | |
2037 | { | |
2038 | u32 mac_mode; | |
2039 | ||
2040 | mac_mode = REG_RD(bp, BNX2_EMAC_MODE); | |
2041 | mac_mode &= ~BNX2_EMAC_MODE_PORT; | |
2042 | mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; | |
2043 | REG_WR(bp, BNX2_EMAC_MODE, mac_mode); | |
2044 | bp->link_up = 1; | |
2045 | return 0; | |
2046 | } | |
2047 | ||
bc5a0690 MC |
2048 | static int bnx2_test_link(struct bnx2 *); |
2049 | ||
2050 | static int | |
2051 | bnx2_set_phy_loopback(struct bnx2 *bp) | |
2052 | { | |
2053 | u32 mac_mode; | |
2054 | int rc, i; | |
2055 | ||
2056 | spin_lock_bh(&bp->phy_lock); | |
ca58c3af | 2057 | rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | |
bc5a0690 MC |
2058 | BMCR_SPEED1000); |
2059 | spin_unlock_bh(&bp->phy_lock); | |
2060 | if (rc) | |
2061 | return rc; | |
2062 | ||
2063 | for (i = 0; i < 10; i++) { | |
2064 | if (bnx2_test_link(bp) == 0) | |
2065 | break; | |
80be4434 | 2066 | msleep(100); |
bc5a0690 MC |
2067 | } |
2068 | ||
2069 | mac_mode = REG_RD(bp, BNX2_EMAC_MODE); | |
2070 | mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | |
2071 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | | |
59b47d8a | 2072 | BNX2_EMAC_MODE_25G_MODE); |
bc5a0690 MC |
2073 | |
2074 | mac_mode |= BNX2_EMAC_MODE_PORT_GMII; | |
2075 | REG_WR(bp, BNX2_EMAC_MODE, mac_mode); | |
2076 | bp->link_up = 1; | |
2077 | return 0; | |
2078 | } | |
2079 | ||
b6016b76 | 2080 | static int |
b090ae2b | 2081 | bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) |
b6016b76 MC |
2082 | { |
2083 | int i; | |
2084 | u32 val; | |
2085 | ||
b6016b76 MC |
2086 | bp->fw_wr_seq++; |
2087 | msg_data |= bp->fw_wr_seq; | |
2088 | ||
e3648b3d | 2089 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); |
b6016b76 MC |
2090 | |
2091 | /* wait for an acknowledgement. */ | |
b090ae2b MC |
2092 | for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { |
2093 | msleep(10); | |
b6016b76 | 2094 | |
e3648b3d | 2095 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB); |
b6016b76 MC |
2096 | |
2097 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) | |
2098 | break; | |
2099 | } | |
b090ae2b MC |
2100 | if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) |
2101 | return 0; | |
b6016b76 MC |
2102 | |
2103 | /* If we timed out, inform the firmware that this is the case. */ | |
b090ae2b MC |
2104 | if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { |
2105 | if (!silent) | |
2106 | printk(KERN_ERR PFX "fw sync timeout, reset code = " | |
2107 | "%x\n", msg_data); | |
b6016b76 MC |
2108 | |
2109 | msg_data &= ~BNX2_DRV_MSG_CODE; | |
2110 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; | |
2111 | ||
e3648b3d | 2112 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); |
b6016b76 | 2113 | |
b6016b76 MC |
2114 | return -EBUSY; |
2115 | } | |
2116 | ||
b090ae2b MC |
2117 | if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) |
2118 | return -EIO; | |
2119 | ||
b6016b76 MC |
2120 | return 0; |
2121 | } | |
2122 | ||
59b47d8a MC |
2123 | static int |
2124 | bnx2_init_5709_context(struct bnx2 *bp) | |
2125 | { | |
2126 | int i, ret = 0; | |
2127 | u32 val; | |
2128 | ||
2129 | val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); | |
2130 | val |= (BCM_PAGE_BITS - 8) << 16; | |
2131 | REG_WR(bp, BNX2_CTX_COMMAND, val); | |
641bdcd5 MC |
2132 | for (i = 0; i < 10; i++) { |
2133 | val = REG_RD(bp, BNX2_CTX_COMMAND); | |
2134 | if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) | |
2135 | break; | |
2136 | udelay(2); | |
2137 | } | |
2138 | if (val & BNX2_CTX_COMMAND_MEM_INIT) | |
2139 | return -EBUSY; | |
2140 | ||
59b47d8a MC |
2141 | for (i = 0; i < bp->ctx_pages; i++) { |
2142 | int j; | |
2143 | ||
2144 | REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, | |
2145 | (bp->ctx_blk_mapping[i] & 0xffffffff) | | |
2146 | BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); | |
2147 | REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, | |
2148 | (u64) bp->ctx_blk_mapping[i] >> 32); | |
2149 | REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | | |
2150 | BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); | |
2151 | for (j = 0; j < 10; j++) { | |
2152 | ||
2153 | val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); | |
2154 | if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) | |
2155 | break; | |
2156 | udelay(5); | |
2157 | } | |
2158 | if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { | |
2159 | ret = -EBUSY; | |
2160 | break; | |
2161 | } | |
2162 | } | |
2163 | return ret; | |
2164 | } | |
2165 | ||
b6016b76 MC |
2166 | static void |
2167 | bnx2_init_context(struct bnx2 *bp) | |
2168 | { | |
2169 | u32 vcid; | |
2170 | ||
2171 | vcid = 96; | |
2172 | while (vcid) { | |
2173 | u32 vcid_addr, pcid_addr, offset; | |
7947b20e | 2174 | int i; |
b6016b76 MC |
2175 | |
2176 | vcid--; | |
2177 | ||
2178 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
2179 | u32 new_vcid; | |
2180 | ||
2181 | vcid_addr = GET_PCID_ADDR(vcid); | |
2182 | if (vcid & 0x8) { | |
2183 | new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); | |
2184 | } | |
2185 | else { | |
2186 | new_vcid = vcid; | |
2187 | } | |
2188 | pcid_addr = GET_PCID_ADDR(new_vcid); | |
2189 | } | |
2190 | else { | |
2191 | vcid_addr = GET_CID_ADDR(vcid); | |
2192 | pcid_addr = vcid_addr; | |
2193 | } | |
2194 | ||
7947b20e MC |
2195 | for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { |
2196 | vcid_addr += (i << PHY_CTX_SHIFT); | |
2197 | pcid_addr += (i << PHY_CTX_SHIFT); | |
b6016b76 | 2198 | |
5d5d0015 | 2199 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); |
7947b20e | 2200 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); |
b6016b76 | 2201 | |
7947b20e MC |
2202 | /* Zero out the context. */ |
2203 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) | |
5d5d0015 | 2204 | CTX_WR(bp, vcid_addr, offset, 0); |
7947b20e | 2205 | } |
b6016b76 MC |
2206 | } |
2207 | } | |
2208 | ||
2209 | static int | |
2210 | bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |
2211 | { | |
2212 | u16 *good_mbuf; | |
2213 | u32 good_mbuf_cnt; | |
2214 | u32 val; | |
2215 | ||
2216 | good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); | |
2217 | if (good_mbuf == NULL) { | |
2218 | printk(KERN_ERR PFX "Failed to allocate memory in " | |
2219 | "bnx2_alloc_bad_rbuf\n"); | |
2220 | return -ENOMEM; | |
2221 | } | |
2222 | ||
2223 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
2224 | BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); | |
2225 | ||
2226 | good_mbuf_cnt = 0; | |
2227 | ||
2228 | /* Allocate a bunch of mbufs and save the good ones in an array. */ | |
2229 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | |
2230 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { | |
2231 | REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ); | |
2232 | ||
2233 | val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC); | |
2234 | ||
2235 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; | |
2236 | ||
2237 | /* The addresses with Bit 9 set are bad memory blocks. */ | |
2238 | if (!(val & (1 << 9))) { | |
2239 | good_mbuf[good_mbuf_cnt] = (u16) val; | |
2240 | good_mbuf_cnt++; | |
2241 | } | |
2242 | ||
2243 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | |
2244 | } | |
2245 | ||
2246 | /* Free the good ones back to the mbuf pool thus discarding | |
2247 | * all the bad ones. */ | |
2248 | while (good_mbuf_cnt) { | |
2249 | good_mbuf_cnt--; | |
2250 | ||
2251 | val = good_mbuf[good_mbuf_cnt]; | |
2252 | val = (val << 9) | val | 1; | |
2253 | ||
2254 | REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val); | |
2255 | } | |
2256 | kfree(good_mbuf); | |
2257 | return 0; | |
2258 | } | |
2259 | ||
2260 | static void | |
6aa20a22 | 2261 | bnx2_set_mac_addr(struct bnx2 *bp) |
b6016b76 MC |
2262 | { |
2263 | u32 val; | |
2264 | u8 *mac_addr = bp->dev->dev_addr; | |
2265 | ||
2266 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
2267 | ||
2268 | REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val); | |
2269 | ||
6aa20a22 | 2270 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | |
b6016b76 MC |
2271 | (mac_addr[4] << 8) | mac_addr[5]; |
2272 | ||
2273 | REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val); | |
2274 | } | |
2275 | ||
47bf4246 MC |
2276 | static inline int |
2277 | bnx2_alloc_rx_page(struct bnx2 *bp, u16 index) | |
2278 | { | |
2279 | dma_addr_t mapping; | |
2280 | struct sw_pg *rx_pg = &bp->rx_pg_ring[index]; | |
2281 | struct rx_bd *rxbd = | |
2282 | &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; | |
2283 | struct page *page = alloc_page(GFP_ATOMIC); | |
2284 | ||
2285 | if (!page) | |
2286 | return -ENOMEM; | |
2287 | mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE, | |
2288 | PCI_DMA_FROMDEVICE); | |
2289 | rx_pg->page = page; | |
2290 | pci_unmap_addr_set(rx_pg, mapping, mapping); | |
2291 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | |
2292 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2293 | return 0; | |
2294 | } | |
2295 | ||
2296 | static void | |
2297 | bnx2_free_rx_page(struct bnx2 *bp, u16 index) | |
2298 | { | |
2299 | struct sw_pg *rx_pg = &bp->rx_pg_ring[index]; | |
2300 | struct page *page = rx_pg->page; | |
2301 | ||
2302 | if (!page) | |
2303 | return; | |
2304 | ||
2305 | pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE, | |
2306 | PCI_DMA_FROMDEVICE); | |
2307 | ||
2308 | __free_page(page); | |
2309 | rx_pg->page = NULL; | |
2310 | } | |
2311 | ||
b6016b76 | 2312 | static inline int |
a1f60190 | 2313 | bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index) |
b6016b76 MC |
2314 | { |
2315 | struct sk_buff *skb; | |
2316 | struct sw_bd *rx_buf = &bp->rx_buf_ring[index]; | |
2317 | dma_addr_t mapping; | |
13daffa2 | 2318 | struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; |
b6016b76 MC |
2319 | unsigned long align; |
2320 | ||
932f3772 | 2321 | skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); |
b6016b76 MC |
2322 | if (skb == NULL) { |
2323 | return -ENOMEM; | |
2324 | } | |
2325 | ||
59b47d8a MC |
2326 | if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1)))) |
2327 | skb_reserve(skb, BNX2_RX_ALIGN - align); | |
b6016b76 | 2328 | |
b6016b76 MC |
2329 | mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, |
2330 | PCI_DMA_FROMDEVICE); | |
2331 | ||
2332 | rx_buf->skb = skb; | |
2333 | pci_unmap_addr_set(rx_buf, mapping, mapping); | |
2334 | ||
2335 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | |
2336 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2337 | ||
a1f60190 | 2338 | bnapi->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 MC |
2339 | |
2340 | return 0; | |
2341 | } | |
2342 | ||
da3e4fbe | 2343 | static int |
35efa7c1 | 2344 | bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) |
b6016b76 | 2345 | { |
35efa7c1 | 2346 | struct status_block *sblk = bnapi->status_blk; |
b6016b76 | 2347 | u32 new_link_state, old_link_state; |
da3e4fbe | 2348 | int is_set = 1; |
b6016b76 | 2349 | |
da3e4fbe MC |
2350 | new_link_state = sblk->status_attn_bits & event; |
2351 | old_link_state = sblk->status_attn_bits_ack & event; | |
b6016b76 | 2352 | if (new_link_state != old_link_state) { |
da3e4fbe MC |
2353 | if (new_link_state) |
2354 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); | |
2355 | else | |
2356 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); | |
2357 | } else | |
2358 | is_set = 0; | |
2359 | ||
2360 | return is_set; | |
2361 | } | |
2362 | ||
2363 | static void | |
35efa7c1 | 2364 | bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi) |
da3e4fbe | 2365 | { |
35efa7c1 | 2366 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) { |
da3e4fbe | 2367 | spin_lock(&bp->phy_lock); |
b6016b76 | 2368 | bnx2_set_link(bp); |
da3e4fbe | 2369 | spin_unlock(&bp->phy_lock); |
b6016b76 | 2370 | } |
35efa7c1 | 2371 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT)) |
0d8a6571 MC |
2372 | bnx2_set_remote_link(bp); |
2373 | ||
b6016b76 MC |
2374 | } |
2375 | ||
ead7270b | 2376 | static inline u16 |
35efa7c1 | 2377 | bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) |
ead7270b MC |
2378 | { |
2379 | u16 cons; | |
2380 | ||
c76c0475 MC |
2381 | if (bnapi->int_num == 0) |
2382 | cons = bnapi->status_blk->status_tx_quick_consumer_index0; | |
2383 | else | |
2384 | cons = bnapi->status_blk_msix->status_tx_quick_consumer_index; | |
ead7270b MC |
2385 | |
2386 | if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) | |
2387 | cons++; | |
2388 | return cons; | |
2389 | } | |
2390 | ||
b6016b76 | 2391 | static void |
35efa7c1 | 2392 | bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi) |
b6016b76 MC |
2393 | { |
2394 | u16 hw_cons, sw_cons, sw_ring_cons; | |
b6016b76 | 2395 | |
35efa7c1 | 2396 | hw_cons = bnx2_get_hw_tx_cons(bnapi); |
a550c99b | 2397 | sw_cons = bnapi->tx_cons; |
b6016b76 MC |
2398 | |
2399 | while (sw_cons != hw_cons) { | |
2400 | struct sw_bd *tx_buf; | |
2401 | struct sk_buff *skb; | |
2402 | int i, last; | |
2403 | ||
2404 | sw_ring_cons = TX_RING_IDX(sw_cons); | |
2405 | ||
2406 | tx_buf = &bp->tx_buf_ring[sw_ring_cons]; | |
2407 | skb = tx_buf->skb; | |
1d39ed56 | 2408 | |
b6016b76 | 2409 | /* partial BD completions possible with TSO packets */ |
89114afd | 2410 | if (skb_is_gso(skb)) { |
b6016b76 MC |
2411 | u16 last_idx, last_ring_idx; |
2412 | ||
2413 | last_idx = sw_cons + | |
2414 | skb_shinfo(skb)->nr_frags + 1; | |
2415 | last_ring_idx = sw_ring_cons + | |
2416 | skb_shinfo(skb)->nr_frags + 1; | |
2417 | if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) { | |
2418 | last_idx++; | |
2419 | } | |
2420 | if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { | |
2421 | break; | |
2422 | } | |
2423 | } | |
1d39ed56 | 2424 | |
b6016b76 MC |
2425 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), |
2426 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
2427 | ||
2428 | tx_buf->skb = NULL; | |
2429 | last = skb_shinfo(skb)->nr_frags; | |
2430 | ||
2431 | for (i = 0; i < last; i++) { | |
2432 | sw_cons = NEXT_TX_BD(sw_cons); | |
2433 | ||
2434 | pci_unmap_page(bp->pdev, | |
2435 | pci_unmap_addr( | |
2436 | &bp->tx_buf_ring[TX_RING_IDX(sw_cons)], | |
2437 | mapping), | |
2438 | skb_shinfo(skb)->frags[i].size, | |
2439 | PCI_DMA_TODEVICE); | |
2440 | } | |
2441 | ||
2442 | sw_cons = NEXT_TX_BD(sw_cons); | |
2443 | ||
745720e5 | 2444 | dev_kfree_skb(skb); |
b6016b76 | 2445 | |
35efa7c1 | 2446 | hw_cons = bnx2_get_hw_tx_cons(bnapi); |
b6016b76 MC |
2447 | } |
2448 | ||
a550c99b MC |
2449 | bnapi->hw_tx_cons = hw_cons; |
2450 | bnapi->tx_cons = sw_cons; | |
2f8af120 MC |
2451 | /* Need to make the tx_cons update visible to bnx2_start_xmit() |
2452 | * before checking for netif_queue_stopped(). Without the | |
2453 | * memory barrier, there is a small possibility that bnx2_start_xmit() | |
2454 | * will miss it and cause the queue to be stopped forever. | |
2455 | */ | |
2456 | smp_mb(); | |
b6016b76 | 2457 | |
2f8af120 | 2458 | if (unlikely(netif_queue_stopped(bp->dev)) && |
a550c99b | 2459 | (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) { |
2f8af120 | 2460 | netif_tx_lock(bp->dev); |
b6016b76 | 2461 | if ((netif_queue_stopped(bp->dev)) && |
a550c99b | 2462 | (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) |
b6016b76 | 2463 | netif_wake_queue(bp->dev); |
2f8af120 | 2464 | netif_tx_unlock(bp->dev); |
b6016b76 | 2465 | } |
b6016b76 MC |
2466 | } |
2467 | ||
1db82f2a | 2468 | static void |
a1f60190 MC |
2469 | bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi, |
2470 | struct sk_buff *skb, int count) | |
1db82f2a MC |
2471 | { |
2472 | struct sw_pg *cons_rx_pg, *prod_rx_pg; | |
2473 | struct rx_bd *cons_bd, *prod_bd; | |
2474 | dma_addr_t mapping; | |
2475 | int i; | |
a1f60190 MC |
2476 | u16 hw_prod = bnapi->rx_pg_prod, prod; |
2477 | u16 cons = bnapi->rx_pg_cons; | |
1db82f2a MC |
2478 | |
2479 | for (i = 0; i < count; i++) { | |
2480 | prod = RX_PG_RING_IDX(hw_prod); | |
2481 | ||
2482 | prod_rx_pg = &bp->rx_pg_ring[prod]; | |
2483 | cons_rx_pg = &bp->rx_pg_ring[cons]; | |
2484 | cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; | |
2485 | prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
2486 | ||
2487 | if (i == 0 && skb) { | |
2488 | struct page *page; | |
2489 | struct skb_shared_info *shinfo; | |
2490 | ||
2491 | shinfo = skb_shinfo(skb); | |
2492 | shinfo->nr_frags--; | |
2493 | page = shinfo->frags[shinfo->nr_frags].page; | |
2494 | shinfo->frags[shinfo->nr_frags].page = NULL; | |
2495 | mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE, | |
2496 | PCI_DMA_FROMDEVICE); | |
2497 | cons_rx_pg->page = page; | |
2498 | pci_unmap_addr_set(cons_rx_pg, mapping, mapping); | |
2499 | dev_kfree_skb(skb); | |
2500 | } | |
2501 | if (prod != cons) { | |
2502 | prod_rx_pg->page = cons_rx_pg->page; | |
2503 | cons_rx_pg->page = NULL; | |
2504 | pci_unmap_addr_set(prod_rx_pg, mapping, | |
2505 | pci_unmap_addr(cons_rx_pg, mapping)); | |
2506 | ||
2507 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; | |
2508 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
2509 | ||
2510 | } | |
2511 | cons = RX_PG_RING_IDX(NEXT_RX_BD(cons)); | |
2512 | hw_prod = NEXT_RX_BD(hw_prod); | |
2513 | } | |
a1f60190 MC |
2514 | bnapi->rx_pg_prod = hw_prod; |
2515 | bnapi->rx_pg_cons = cons; | |
1db82f2a MC |
2516 | } |
2517 | ||
b6016b76 | 2518 | static inline void |
a1f60190 | 2519 | bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, |
b6016b76 MC |
2520 | u16 cons, u16 prod) |
2521 | { | |
236b6394 MC |
2522 | struct sw_bd *cons_rx_buf, *prod_rx_buf; |
2523 | struct rx_bd *cons_bd, *prod_bd; | |
2524 | ||
2525 | cons_rx_buf = &bp->rx_buf_ring[cons]; | |
2526 | prod_rx_buf = &bp->rx_buf_ring[prod]; | |
b6016b76 MC |
2527 | |
2528 | pci_dma_sync_single_for_device(bp->pdev, | |
2529 | pci_unmap_addr(cons_rx_buf, mapping), | |
2530 | bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); | |
2531 | ||
a1f60190 | 2532 | bnapi->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 | 2533 | |
236b6394 | 2534 | prod_rx_buf->skb = skb; |
b6016b76 | 2535 | |
236b6394 MC |
2536 | if (cons == prod) |
2537 | return; | |
b6016b76 | 2538 | |
236b6394 MC |
2539 | pci_unmap_addr_set(prod_rx_buf, mapping, |
2540 | pci_unmap_addr(cons_rx_buf, mapping)); | |
2541 | ||
3fdfcc2c MC |
2542 | cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; |
2543 | prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; | |
236b6394 MC |
2544 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; |
2545 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
b6016b76 MC |
2546 | } |
2547 | ||
85833c62 | 2548 | static int |
a1f60190 MC |
2549 | bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, |
2550 | unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, | |
2551 | u32 ring_idx) | |
85833c62 MC |
2552 | { |
2553 | int err; | |
2554 | u16 prod = ring_idx & 0xffff; | |
2555 | ||
a1f60190 | 2556 | err = bnx2_alloc_rx_skb(bp, bnapi, prod); |
85833c62 | 2557 | if (unlikely(err)) { |
a1f60190 | 2558 | bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod); |
1db82f2a MC |
2559 | if (hdr_len) { |
2560 | unsigned int raw_len = len + 4; | |
2561 | int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; | |
2562 | ||
a1f60190 | 2563 | bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages); |
1db82f2a | 2564 | } |
85833c62 MC |
2565 | return err; |
2566 | } | |
2567 | ||
2568 | skb_reserve(skb, bp->rx_offset); | |
2569 | pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size, | |
2570 | PCI_DMA_FROMDEVICE); | |
2571 | ||
1db82f2a MC |
2572 | if (hdr_len == 0) { |
2573 | skb_put(skb, len); | |
2574 | return 0; | |
2575 | } else { | |
2576 | unsigned int i, frag_len, frag_size, pages; | |
2577 | struct sw_pg *rx_pg; | |
a1f60190 MC |
2578 | u16 pg_cons = bnapi->rx_pg_cons; |
2579 | u16 pg_prod = bnapi->rx_pg_prod; | |
1db82f2a MC |
2580 | |
2581 | frag_size = len + 4 - hdr_len; | |
2582 | pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; | |
2583 | skb_put(skb, hdr_len); | |
2584 | ||
2585 | for (i = 0; i < pages; i++) { | |
2586 | frag_len = min(frag_size, (unsigned int) PAGE_SIZE); | |
2587 | if (unlikely(frag_len <= 4)) { | |
2588 | unsigned int tail = 4 - frag_len; | |
2589 | ||
a1f60190 MC |
2590 | bnapi->rx_pg_cons = pg_cons; |
2591 | bnapi->rx_pg_prod = pg_prod; | |
2592 | bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, | |
2593 | pages - i); | |
1db82f2a MC |
2594 | skb->len -= tail; |
2595 | if (i == 0) { | |
2596 | skb->tail -= tail; | |
2597 | } else { | |
2598 | skb_frag_t *frag = | |
2599 | &skb_shinfo(skb)->frags[i - 1]; | |
2600 | frag->size -= tail; | |
2601 | skb->data_len -= tail; | |
2602 | skb->truesize -= tail; | |
2603 | } | |
2604 | return 0; | |
2605 | } | |
2606 | rx_pg = &bp->rx_pg_ring[pg_cons]; | |
2607 | ||
2608 | pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), | |
2609 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | |
2610 | ||
2611 | if (i == pages - 1) | |
2612 | frag_len -= 4; | |
2613 | ||
2614 | skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); | |
2615 | rx_pg->page = NULL; | |
2616 | ||
2617 | err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod)); | |
2618 | if (unlikely(err)) { | |
a1f60190 MC |
2619 | bnapi->rx_pg_cons = pg_cons; |
2620 | bnapi->rx_pg_prod = pg_prod; | |
2621 | bnx2_reuse_rx_skb_pages(bp, bnapi, skb, | |
2622 | pages - i); | |
1db82f2a MC |
2623 | return err; |
2624 | } | |
2625 | ||
2626 | frag_size -= frag_len; | |
2627 | skb->data_len += frag_len; | |
2628 | skb->truesize += frag_len; | |
2629 | skb->len += frag_len; | |
2630 | ||
2631 | pg_prod = NEXT_RX_BD(pg_prod); | |
2632 | pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); | |
2633 | } | |
a1f60190 MC |
2634 | bnapi->rx_pg_prod = pg_prod; |
2635 | bnapi->rx_pg_cons = pg_cons; | |
1db82f2a | 2636 | } |
85833c62 MC |
2637 | return 0; |
2638 | } | |
2639 | ||
c09c2627 | 2640 | static inline u16 |
35efa7c1 | 2641 | bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) |
c09c2627 | 2642 | { |
35efa7c1 | 2643 | u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0; |
c09c2627 MC |
2644 | |
2645 | if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) | |
2646 | cons++; | |
2647 | return cons; | |
2648 | } | |
2649 | ||
b6016b76 | 2650 | static int |
35efa7c1 | 2651 | bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) |
b6016b76 MC |
2652 | { |
2653 | u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; | |
2654 | struct l2_fhdr *rx_hdr; | |
1db82f2a | 2655 | int rx_pkt = 0, pg_ring_used = 0; |
b6016b76 | 2656 | |
35efa7c1 | 2657 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
a1f60190 MC |
2658 | sw_cons = bnapi->rx_cons; |
2659 | sw_prod = bnapi->rx_prod; | |
b6016b76 MC |
2660 | |
2661 | /* Memory barrier necessary as speculative reads of the rx | |
2662 | * buffer can be ahead of the index in the status block | |
2663 | */ | |
2664 | rmb(); | |
2665 | while (sw_cons != hw_cons) { | |
1db82f2a | 2666 | unsigned int len, hdr_len; |
ade2bfe7 | 2667 | u32 status; |
b6016b76 MC |
2668 | struct sw_bd *rx_buf; |
2669 | struct sk_buff *skb; | |
236b6394 | 2670 | dma_addr_t dma_addr; |
b6016b76 MC |
2671 | |
2672 | sw_ring_cons = RX_RING_IDX(sw_cons); | |
2673 | sw_ring_prod = RX_RING_IDX(sw_prod); | |
2674 | ||
2675 | rx_buf = &bp->rx_buf_ring[sw_ring_cons]; | |
2676 | skb = rx_buf->skb; | |
236b6394 MC |
2677 | |
2678 | rx_buf->skb = NULL; | |
2679 | ||
2680 | dma_addr = pci_unmap_addr(rx_buf, mapping); | |
2681 | ||
2682 | pci_dma_sync_single_for_cpu(bp->pdev, dma_addr, | |
b6016b76 MC |
2683 | bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); |
2684 | ||
2685 | rx_hdr = (struct l2_fhdr *) skb->data; | |
1db82f2a | 2686 | len = rx_hdr->l2_fhdr_pkt_len; |
b6016b76 | 2687 | |
ade2bfe7 | 2688 | if ((status = rx_hdr->l2_fhdr_status) & |
b6016b76 MC |
2689 | (L2_FHDR_ERRORS_BAD_CRC | |
2690 | L2_FHDR_ERRORS_PHY_DECODE | | |
2691 | L2_FHDR_ERRORS_ALIGNMENT | | |
2692 | L2_FHDR_ERRORS_TOO_SHORT | | |
2693 | L2_FHDR_ERRORS_GIANT_FRAME)) { | |
2694 | ||
a1f60190 MC |
2695 | bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons, |
2696 | sw_ring_prod); | |
85833c62 | 2697 | goto next_rx; |
b6016b76 | 2698 | } |
1db82f2a MC |
2699 | hdr_len = 0; |
2700 | if (status & L2_FHDR_STATUS_SPLIT) { | |
2701 | hdr_len = rx_hdr->l2_fhdr_ip_xsum; | |
2702 | pg_ring_used = 1; | |
2703 | } else if (len > bp->rx_jumbo_thresh) { | |
2704 | hdr_len = bp->rx_jumbo_thresh; | |
2705 | pg_ring_used = 1; | |
2706 | } | |
2707 | ||
2708 | len -= 4; | |
b6016b76 | 2709 | |
5d5d0015 | 2710 | if (len <= bp->rx_copy_thresh) { |
b6016b76 MC |
2711 | struct sk_buff *new_skb; |
2712 | ||
932f3772 | 2713 | new_skb = netdev_alloc_skb(bp->dev, len + 2); |
85833c62 | 2714 | if (new_skb == NULL) { |
a1f60190 | 2715 | bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons, |
85833c62 MC |
2716 | sw_ring_prod); |
2717 | goto next_rx; | |
2718 | } | |
b6016b76 MC |
2719 | |
2720 | /* aligned copy */ | |
d626f62b ACM |
2721 | skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2, |
2722 | new_skb->data, len + 2); | |
b6016b76 MC |
2723 | skb_reserve(new_skb, 2); |
2724 | skb_put(new_skb, len); | |
b6016b76 | 2725 | |
a1f60190 | 2726 | bnx2_reuse_rx_skb(bp, bnapi, skb, |
b6016b76 MC |
2727 | sw_ring_cons, sw_ring_prod); |
2728 | ||
2729 | skb = new_skb; | |
a1f60190 MC |
2730 | } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len, |
2731 | dma_addr, (sw_ring_cons << 16) | sw_ring_prod))) | |
b6016b76 | 2732 | goto next_rx; |
b6016b76 MC |
2733 | |
2734 | skb->protocol = eth_type_trans(skb, bp->dev); | |
2735 | ||
2736 | if ((len > (bp->dev->mtu + ETH_HLEN)) && | |
d1e100ba | 2737 | (ntohs(skb->protocol) != 0x8100)) { |
b6016b76 | 2738 | |
745720e5 | 2739 | dev_kfree_skb(skb); |
b6016b76 MC |
2740 | goto next_rx; |
2741 | ||
2742 | } | |
2743 | ||
b6016b76 MC |
2744 | skb->ip_summed = CHECKSUM_NONE; |
2745 | if (bp->rx_csum && | |
2746 | (status & (L2_FHDR_STATUS_TCP_SEGMENT | | |
2747 | L2_FHDR_STATUS_UDP_DATAGRAM))) { | |
2748 | ||
ade2bfe7 MC |
2749 | if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM | |
2750 | L2_FHDR_ERRORS_UDP_XSUM)) == 0)) | |
b6016b76 MC |
2751 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2752 | } | |
2753 | ||
2754 | #ifdef BCM_VLAN | |
2755 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) { | |
2756 | vlan_hwaccel_receive_skb(skb, bp->vlgrp, | |
2757 | rx_hdr->l2_fhdr_vlan_tag); | |
2758 | } | |
2759 | else | |
2760 | #endif | |
2761 | netif_receive_skb(skb); | |
2762 | ||
2763 | bp->dev->last_rx = jiffies; | |
2764 | rx_pkt++; | |
2765 | ||
2766 | next_rx: | |
b6016b76 MC |
2767 | sw_cons = NEXT_RX_BD(sw_cons); |
2768 | sw_prod = NEXT_RX_BD(sw_prod); | |
2769 | ||
2770 | if ((rx_pkt == budget)) | |
2771 | break; | |
f4e418f7 MC |
2772 | |
2773 | /* Refresh hw_cons to see if there is new work */ | |
2774 | if (sw_cons == hw_cons) { | |
35efa7c1 | 2775 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
f4e418f7 MC |
2776 | rmb(); |
2777 | } | |
b6016b76 | 2778 | } |
a1f60190 MC |
2779 | bnapi->rx_cons = sw_cons; |
2780 | bnapi->rx_prod = sw_prod; | |
b6016b76 | 2781 | |
1db82f2a MC |
2782 | if (pg_ring_used) |
2783 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, | |
a1f60190 | 2784 | bnapi->rx_pg_prod); |
1db82f2a | 2785 | |
b6016b76 MC |
2786 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod); |
2787 | ||
a1f60190 | 2788 | REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq); |
b6016b76 MC |
2789 | |
2790 | mmiowb(); | |
2791 | ||
2792 | return rx_pkt; | |
2793 | ||
2794 | } | |
2795 | ||
2796 | /* MSI ISR - The only difference between this and the INTx ISR | |
2797 | * is that the MSI interrupt is always serviced. | |
2798 | */ | |
2799 | static irqreturn_t | |
7d12e780 | 2800 | bnx2_msi(int irq, void *dev_instance) |
b6016b76 MC |
2801 | { |
2802 | struct net_device *dev = dev_instance; | |
972ec0d4 | 2803 | struct bnx2 *bp = netdev_priv(dev); |
b4b36042 | 2804 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
b6016b76 | 2805 | |
35efa7c1 | 2806 | prefetch(bnapi->status_blk); |
b6016b76 MC |
2807 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
2808 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | |
2809 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
2810 | ||
2811 | /* Return here if interrupt is disabled. */ | |
73eef4cd MC |
2812 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
2813 | return IRQ_HANDLED; | |
b6016b76 | 2814 | |
35efa7c1 | 2815 | netif_rx_schedule(dev, &bnapi->napi); |
b6016b76 | 2816 | |
73eef4cd | 2817 | return IRQ_HANDLED; |
b6016b76 MC |
2818 | } |
2819 | ||
8e6a72c4 MC |
2820 | static irqreturn_t |
2821 | bnx2_msi_1shot(int irq, void *dev_instance) | |
2822 | { | |
2823 | struct net_device *dev = dev_instance; | |
2824 | struct bnx2 *bp = netdev_priv(dev); | |
b4b36042 | 2825 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
8e6a72c4 | 2826 | |
35efa7c1 | 2827 | prefetch(bnapi->status_blk); |
8e6a72c4 MC |
2828 | |
2829 | /* Return here if interrupt is disabled. */ | |
2830 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
2831 | return IRQ_HANDLED; | |
2832 | ||
35efa7c1 | 2833 | netif_rx_schedule(dev, &bnapi->napi); |
8e6a72c4 MC |
2834 | |
2835 | return IRQ_HANDLED; | |
2836 | } | |
2837 | ||
b6016b76 | 2838 | static irqreturn_t |
7d12e780 | 2839 | bnx2_interrupt(int irq, void *dev_instance) |
b6016b76 MC |
2840 | { |
2841 | struct net_device *dev = dev_instance; | |
972ec0d4 | 2842 | struct bnx2 *bp = netdev_priv(dev); |
b4b36042 | 2843 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
35efa7c1 | 2844 | struct status_block *sblk = bnapi->status_blk; |
b6016b76 MC |
2845 | |
2846 | /* When using INTx, it is possible for the interrupt to arrive | |
2847 | * at the CPU before the status block posted prior to the | |
2848 | * interrupt. Reading a register will flush the status block. | |
2849 | * When using MSI, the MSI message will always complete after | |
2850 | * the status block write. | |
2851 | */ | |
35efa7c1 | 2852 | if ((sblk->status_idx == bnapi->last_status_idx) && |
b6016b76 MC |
2853 | (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & |
2854 | BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) | |
73eef4cd | 2855 | return IRQ_NONE; |
b6016b76 MC |
2856 | |
2857 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
2858 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | |
2859 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
2860 | ||
b8a7ce7b MC |
2861 | /* Read back to deassert IRQ immediately to avoid too many |
2862 | * spurious interrupts. | |
2863 | */ | |
2864 | REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); | |
2865 | ||
b6016b76 | 2866 | /* Return here if interrupt is shared and is disabled. */ |
73eef4cd MC |
2867 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
2868 | return IRQ_HANDLED; | |
b6016b76 | 2869 | |
35efa7c1 MC |
2870 | if (netif_rx_schedule_prep(dev, &bnapi->napi)) { |
2871 | bnapi->last_status_idx = sblk->status_idx; | |
2872 | __netif_rx_schedule(dev, &bnapi->napi); | |
b8a7ce7b | 2873 | } |
b6016b76 | 2874 | |
73eef4cd | 2875 | return IRQ_HANDLED; |
b6016b76 MC |
2876 | } |
2877 | ||
0d8a6571 MC |
2878 | #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ |
2879 | STATUS_ATTN_BITS_TIMER_ABORT) | |
da3e4fbe | 2880 | |
f4e418f7 | 2881 | static inline int |
35efa7c1 | 2882 | bnx2_has_work(struct bnx2_napi *bnapi) |
f4e418f7 | 2883 | { |
35efa7c1 | 2884 | struct bnx2 *bp = bnapi->bp; |
f4e418f7 MC |
2885 | struct status_block *sblk = bp->status_blk; |
2886 | ||
a1f60190 | 2887 | if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) || |
a550c99b | 2888 | (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)) |
f4e418f7 MC |
2889 | return 1; |
2890 | ||
da3e4fbe MC |
2891 | if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != |
2892 | (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) | |
f4e418f7 MC |
2893 | return 1; |
2894 | ||
2895 | return 0; | |
2896 | } | |
2897 | ||
35efa7c1 MC |
2898 | static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, |
2899 | int work_done, int budget) | |
b6016b76 | 2900 | { |
35efa7c1 | 2901 | struct status_block *sblk = bnapi->status_blk; |
da3e4fbe MC |
2902 | u32 status_attn_bits = sblk->status_attn_bits; |
2903 | u32 status_attn_bits_ack = sblk->status_attn_bits_ack; | |
b6016b76 | 2904 | |
da3e4fbe MC |
2905 | if ((status_attn_bits & STATUS_ATTN_EVENTS) != |
2906 | (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { | |
b6016b76 | 2907 | |
35efa7c1 | 2908 | bnx2_phy_int(bp, bnapi); |
bf5295bb MC |
2909 | |
2910 | /* This is needed to take care of transient status | |
2911 | * during link changes. | |
2912 | */ | |
2913 | REG_WR(bp, BNX2_HC_COMMAND, | |
2914 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
2915 | REG_RD(bp, BNX2_HC_COMMAND); | |
b6016b76 MC |
2916 | } |
2917 | ||
a550c99b | 2918 | if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons) |
35efa7c1 | 2919 | bnx2_tx_int(bp, bnapi); |
b6016b76 | 2920 | |
a1f60190 | 2921 | if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) |
35efa7c1 | 2922 | work_done += bnx2_rx_int(bp, bnapi, budget - work_done); |
6aa20a22 | 2923 | |
6f535763 DM |
2924 | return work_done; |
2925 | } | |
2926 | ||
2927 | static int bnx2_poll(struct napi_struct *napi, int budget) | |
2928 | { | |
35efa7c1 MC |
2929 | struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); |
2930 | struct bnx2 *bp = bnapi->bp; | |
6f535763 | 2931 | int work_done = 0; |
35efa7c1 | 2932 | struct status_block *sblk = bnapi->status_blk; |
6f535763 DM |
2933 | |
2934 | while (1) { | |
35efa7c1 | 2935 | work_done = bnx2_poll_work(bp, bnapi, work_done, budget); |
f4e418f7 | 2936 | |
6f535763 DM |
2937 | if (unlikely(work_done >= budget)) |
2938 | break; | |
2939 | ||
35efa7c1 | 2940 | /* bnapi->last_status_idx is used below to tell the hw how |
6dee6421 MC |
2941 | * much work has been processed, so we must read it before |
2942 | * checking for more work. | |
2943 | */ | |
35efa7c1 | 2944 | bnapi->last_status_idx = sblk->status_idx; |
6dee6421 | 2945 | rmb(); |
35efa7c1 | 2946 | if (likely(!bnx2_has_work(bnapi))) { |
6f535763 | 2947 | netif_rx_complete(bp->dev, napi); |
b4b36042 | 2948 | if (likely(bp->flags & USING_MSI_OR_MSIX_FLAG)) { |
6f535763 DM |
2949 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
2950 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
35efa7c1 | 2951 | bnapi->last_status_idx); |
6dee6421 | 2952 | break; |
6f535763 | 2953 | } |
1269a8a6 MC |
2954 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
2955 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
6f535763 | 2956 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | |
35efa7c1 | 2957 | bnapi->last_status_idx); |
1269a8a6 | 2958 | |
6f535763 DM |
2959 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
2960 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
35efa7c1 | 2961 | bnapi->last_status_idx); |
6f535763 DM |
2962 | break; |
2963 | } | |
b6016b76 MC |
2964 | } |
2965 | ||
bea3348e | 2966 | return work_done; |
b6016b76 MC |
2967 | } |
2968 | ||
932ff279 | 2969 | /* Called with rtnl_lock from vlan functions and also netif_tx_lock |
b6016b76 MC |
2970 | * from set_multicast. |
2971 | */ | |
2972 | static void | |
2973 | bnx2_set_rx_mode(struct net_device *dev) | |
2974 | { | |
972ec0d4 | 2975 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
2976 | u32 rx_mode, sort_mode; |
2977 | int i; | |
b6016b76 | 2978 | |
c770a65c | 2979 | spin_lock_bh(&bp->phy_lock); |
b6016b76 MC |
2980 | |
2981 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | | |
2982 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); | |
2983 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; | |
2984 | #ifdef BCM_VLAN | |
e29054f9 | 2985 | if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG)) |
b6016b76 | 2986 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; |
b6016b76 | 2987 | #else |
e29054f9 MC |
2988 | if (!(bp->flags & ASF_ENABLE_FLAG)) |
2989 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; | |
b6016b76 MC |
2990 | #endif |
2991 | if (dev->flags & IFF_PROMISC) { | |
2992 | /* Promiscuous mode. */ | |
2993 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; | |
7510873d MC |
2994 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | |
2995 | BNX2_RPM_SORT_USER0_PROM_VLAN; | |
b6016b76 MC |
2996 | } |
2997 | else if (dev->flags & IFF_ALLMULTI) { | |
2998 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
2999 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
3000 | 0xffffffff); | |
3001 | } | |
3002 | sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; | |
3003 | } | |
3004 | else { | |
3005 | /* Accept one or more multicast(s). */ | |
3006 | struct dev_mc_list *mclist; | |
3007 | u32 mc_filter[NUM_MC_HASH_REGISTERS]; | |
3008 | u32 regidx; | |
3009 | u32 bit; | |
3010 | u32 crc; | |
3011 | ||
3012 | memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); | |
3013 | ||
3014 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
3015 | i++, mclist = mclist->next) { | |
3016 | ||
3017 | crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr); | |
3018 | bit = crc & 0xff; | |
3019 | regidx = (bit & 0xe0) >> 5; | |
3020 | bit &= 0x1f; | |
3021 | mc_filter[regidx] |= (1 << bit); | |
3022 | } | |
3023 | ||
3024 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
3025 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
3026 | mc_filter[i]); | |
3027 | } | |
3028 | ||
3029 | sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; | |
3030 | } | |
3031 | ||
3032 | if (rx_mode != bp->rx_mode) { | |
3033 | bp->rx_mode = rx_mode; | |
3034 | REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); | |
3035 | } | |
3036 | ||
3037 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | |
3038 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); | |
3039 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); | |
3040 | ||
c770a65c | 3041 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
3042 | } |
3043 | ||
3044 | static void | |
3045 | load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, | |
3046 | u32 rv2p_proc) | |
3047 | { | |
3048 | int i; | |
3049 | u32 val; | |
3050 | ||
3051 | ||
3052 | for (i = 0; i < rv2p_code_len; i += 8) { | |
fba9fe91 | 3053 | REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code)); |
b6016b76 | 3054 | rv2p_code++; |
fba9fe91 | 3055 | REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code)); |
b6016b76 MC |
3056 | rv2p_code++; |
3057 | ||
3058 | if (rv2p_proc == RV2P_PROC1) { | |
3059 | val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR; | |
3060 | REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val); | |
3061 | } | |
3062 | else { | |
3063 | val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR; | |
3064 | REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val); | |
3065 | } | |
3066 | } | |
3067 | ||
3068 | /* Reset the processor, un-stall is done later. */ | |
3069 | if (rv2p_proc == RV2P_PROC1) { | |
3070 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); | |
3071 | } | |
3072 | else { | |
3073 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); | |
3074 | } | |
3075 | } | |
3076 | ||
af3ee519 | 3077 | static int |
b6016b76 MC |
3078 | load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) |
3079 | { | |
3080 | u32 offset; | |
3081 | u32 val; | |
af3ee519 | 3082 | int rc; |
b6016b76 MC |
3083 | |
3084 | /* Halt the CPU. */ | |
3085 | val = REG_RD_IND(bp, cpu_reg->mode); | |
3086 | val |= cpu_reg->mode_value_halt; | |
3087 | REG_WR_IND(bp, cpu_reg->mode, val); | |
3088 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | |
3089 | ||
3090 | /* Load the Text area. */ | |
3091 | offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); | |
af3ee519 | 3092 | if (fw->gz_text) { |
b6016b76 MC |
3093 | int j; |
3094 | ||
ea1f8d5c MC |
3095 | rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text, |
3096 | fw->gz_text_len); | |
3097 | if (rc < 0) | |
b3448b0b | 3098 | return rc; |
ea1f8d5c | 3099 | |
b6016b76 | 3100 | for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { |
ea1f8d5c | 3101 | REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j])); |
b6016b76 MC |
3102 | } |
3103 | } | |
3104 | ||
3105 | /* Load the Data area. */ | |
3106 | offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); | |
3107 | if (fw->data) { | |
3108 | int j; | |
3109 | ||
3110 | for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { | |
3111 | REG_WR_IND(bp, offset, fw->data[j]); | |
3112 | } | |
3113 | } | |
3114 | ||
3115 | /* Load the SBSS area. */ | |
3116 | offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); | |
ea1f8d5c | 3117 | if (fw->sbss_len) { |
b6016b76 MC |
3118 | int j; |
3119 | ||
3120 | for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { | |
ea1f8d5c | 3121 | REG_WR_IND(bp, offset, 0); |
b6016b76 MC |
3122 | } |
3123 | } | |
3124 | ||
3125 | /* Load the BSS area. */ | |
3126 | offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); | |
ea1f8d5c | 3127 | if (fw->bss_len) { |
b6016b76 MC |
3128 | int j; |
3129 | ||
3130 | for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { | |
ea1f8d5c | 3131 | REG_WR_IND(bp, offset, 0); |
b6016b76 MC |
3132 | } |
3133 | } | |
3134 | ||
3135 | /* Load the Read-Only area. */ | |
3136 | offset = cpu_reg->spad_base + | |
3137 | (fw->rodata_addr - cpu_reg->mips_view_base); | |
3138 | if (fw->rodata) { | |
3139 | int j; | |
3140 | ||
3141 | for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { | |
3142 | REG_WR_IND(bp, offset, fw->rodata[j]); | |
3143 | } | |
3144 | } | |
3145 | ||
3146 | /* Clear the pre-fetch instruction. */ | |
3147 | REG_WR_IND(bp, cpu_reg->inst, 0); | |
3148 | REG_WR_IND(bp, cpu_reg->pc, fw->start_addr); | |
3149 | ||
3150 | /* Start the CPU. */ | |
3151 | val = REG_RD_IND(bp, cpu_reg->mode); | |
3152 | val &= ~cpu_reg->mode_value_halt; | |
3153 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | |
3154 | REG_WR_IND(bp, cpu_reg->mode, val); | |
af3ee519 MC |
3155 | |
3156 | return 0; | |
b6016b76 MC |
3157 | } |
3158 | ||
fba9fe91 | 3159 | static int |
b6016b76 MC |
3160 | bnx2_init_cpus(struct bnx2 *bp) |
3161 | { | |
3162 | struct cpu_reg cpu_reg; | |
af3ee519 | 3163 | struct fw_info *fw; |
110d0ef9 MC |
3164 | int rc, rv2p_len; |
3165 | void *text, *rv2p; | |
b6016b76 MC |
3166 | |
3167 | /* Initialize the RV2P processor. */ | |
b3448b0b DV |
3168 | text = vmalloc(FW_BUF_SIZE); |
3169 | if (!text) | |
3170 | return -ENOMEM; | |
110d0ef9 MC |
3171 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
3172 | rv2p = bnx2_xi_rv2p_proc1; | |
3173 | rv2p_len = sizeof(bnx2_xi_rv2p_proc1); | |
3174 | } else { | |
3175 | rv2p = bnx2_rv2p_proc1; | |
3176 | rv2p_len = sizeof(bnx2_rv2p_proc1); | |
3177 | } | |
3178 | rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len); | |
ea1f8d5c | 3179 | if (rc < 0) |
fba9fe91 | 3180 | goto init_cpu_err; |
ea1f8d5c | 3181 | |
b3448b0b | 3182 | load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1); |
fba9fe91 | 3183 | |
110d0ef9 MC |
3184 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
3185 | rv2p = bnx2_xi_rv2p_proc2; | |
3186 | rv2p_len = sizeof(bnx2_xi_rv2p_proc2); | |
3187 | } else { | |
3188 | rv2p = bnx2_rv2p_proc2; | |
3189 | rv2p_len = sizeof(bnx2_rv2p_proc2); | |
3190 | } | |
3191 | rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len); | |
ea1f8d5c | 3192 | if (rc < 0) |
fba9fe91 | 3193 | goto init_cpu_err; |
ea1f8d5c | 3194 | |
b3448b0b | 3195 | load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2); |
b6016b76 MC |
3196 | |
3197 | /* Initialize the RX Processor. */ | |
3198 | cpu_reg.mode = BNX2_RXP_CPU_MODE; | |
3199 | cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT; | |
3200 | cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA; | |
3201 | cpu_reg.state = BNX2_RXP_CPU_STATE; | |
3202 | cpu_reg.state_value_clear = 0xffffff; | |
3203 | cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE; | |
3204 | cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK; | |
3205 | cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER; | |
3206 | cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION; | |
3207 | cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT; | |
3208 | cpu_reg.spad_base = BNX2_RXP_SCRATCH; | |
3209 | cpu_reg.mips_view_base = 0x8000000; | |
6aa20a22 | 3210 | |
d43584c8 MC |
3211 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
3212 | fw = &bnx2_rxp_fw_09; | |
3213 | else | |
3214 | fw = &bnx2_rxp_fw_06; | |
fba9fe91 | 3215 | |
ea1f8d5c | 3216 | fw->text = text; |
af3ee519 | 3217 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
fba9fe91 MC |
3218 | if (rc) |
3219 | goto init_cpu_err; | |
3220 | ||
b6016b76 MC |
3221 | /* Initialize the TX Processor. */ |
3222 | cpu_reg.mode = BNX2_TXP_CPU_MODE; | |
3223 | cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; | |
3224 | cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA; | |
3225 | cpu_reg.state = BNX2_TXP_CPU_STATE; | |
3226 | cpu_reg.state_value_clear = 0xffffff; | |
3227 | cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE; | |
3228 | cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK; | |
3229 | cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER; | |
3230 | cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION; | |
3231 | cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT; | |
3232 | cpu_reg.spad_base = BNX2_TXP_SCRATCH; | |
3233 | cpu_reg.mips_view_base = 0x8000000; | |
6aa20a22 | 3234 | |
d43584c8 MC |
3235 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
3236 | fw = &bnx2_txp_fw_09; | |
3237 | else | |
3238 | fw = &bnx2_txp_fw_06; | |
fba9fe91 | 3239 | |
ea1f8d5c | 3240 | fw->text = text; |
af3ee519 | 3241 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
fba9fe91 MC |
3242 | if (rc) |
3243 | goto init_cpu_err; | |
3244 | ||
b6016b76 MC |
3245 | /* Initialize the TX Patch-up Processor. */ |
3246 | cpu_reg.mode = BNX2_TPAT_CPU_MODE; | |
3247 | cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; | |
3248 | cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA; | |
3249 | cpu_reg.state = BNX2_TPAT_CPU_STATE; | |
3250 | cpu_reg.state_value_clear = 0xffffff; | |
3251 | cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE; | |
3252 | cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK; | |
3253 | cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER; | |
3254 | cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION; | |
3255 | cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT; | |
3256 | cpu_reg.spad_base = BNX2_TPAT_SCRATCH; | |
3257 | cpu_reg.mips_view_base = 0x8000000; | |
6aa20a22 | 3258 | |
d43584c8 MC |
3259 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
3260 | fw = &bnx2_tpat_fw_09; | |
3261 | else | |
3262 | fw = &bnx2_tpat_fw_06; | |
fba9fe91 | 3263 | |
ea1f8d5c | 3264 | fw->text = text; |
af3ee519 | 3265 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
fba9fe91 MC |
3266 | if (rc) |
3267 | goto init_cpu_err; | |
3268 | ||
b6016b76 MC |
3269 | /* Initialize the Completion Processor. */ |
3270 | cpu_reg.mode = BNX2_COM_CPU_MODE; | |
3271 | cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; | |
3272 | cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA; | |
3273 | cpu_reg.state = BNX2_COM_CPU_STATE; | |
3274 | cpu_reg.state_value_clear = 0xffffff; | |
3275 | cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE; | |
3276 | cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK; | |
3277 | cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER; | |
3278 | cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION; | |
3279 | cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT; | |
3280 | cpu_reg.spad_base = BNX2_COM_SCRATCH; | |
3281 | cpu_reg.mips_view_base = 0x8000000; | |
6aa20a22 | 3282 | |
d43584c8 MC |
3283 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
3284 | fw = &bnx2_com_fw_09; | |
3285 | else | |
3286 | fw = &bnx2_com_fw_06; | |
fba9fe91 | 3287 | |
ea1f8d5c | 3288 | fw->text = text; |
af3ee519 | 3289 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
fba9fe91 MC |
3290 | if (rc) |
3291 | goto init_cpu_err; | |
3292 | ||
d43584c8 MC |
3293 | /* Initialize the Command Processor. */ |
3294 | cpu_reg.mode = BNX2_CP_CPU_MODE; | |
3295 | cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT; | |
3296 | cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA; | |
3297 | cpu_reg.state = BNX2_CP_CPU_STATE; | |
3298 | cpu_reg.state_value_clear = 0xffffff; | |
3299 | cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE; | |
3300 | cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK; | |
3301 | cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER; | |
3302 | cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION; | |
3303 | cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT; | |
3304 | cpu_reg.spad_base = BNX2_CP_SCRATCH; | |
3305 | cpu_reg.mips_view_base = 0x8000000; | |
b6016b76 | 3306 | |
110d0ef9 | 3307 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
d43584c8 | 3308 | fw = &bnx2_cp_fw_09; |
110d0ef9 MC |
3309 | else |
3310 | fw = &bnx2_cp_fw_06; | |
3311 | ||
3312 | fw->text = text; | |
3313 | rc = load_cpu_fw(bp, &cpu_reg, fw); | |
b6016b76 | 3314 | |
fba9fe91 | 3315 | init_cpu_err: |
ea1f8d5c | 3316 | vfree(text); |
fba9fe91 | 3317 | return rc; |
b6016b76 MC |
3318 | } |
3319 | ||
3320 | static int | |
829ca9a3 | 3321 | bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) |
b6016b76 MC |
3322 | { |
3323 | u16 pmcsr; | |
3324 | ||
3325 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
3326 | ||
3327 | switch (state) { | |
829ca9a3 | 3328 | case PCI_D0: { |
b6016b76 MC |
3329 | u32 val; |
3330 | ||
3331 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | |
3332 | (pmcsr & ~PCI_PM_CTRL_STATE_MASK) | | |
3333 | PCI_PM_CTRL_PME_STATUS); | |
3334 | ||
3335 | if (pmcsr & PCI_PM_CTRL_STATE_MASK) | |
3336 | /* delay required during transition out of D3hot */ | |
3337 | msleep(20); | |
3338 | ||
3339 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
3340 | val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; | |
3341 | val &= ~BNX2_EMAC_MODE_MPKT; | |
3342 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
3343 | ||
3344 | val = REG_RD(bp, BNX2_RPM_CONFIG); | |
3345 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | |
3346 | REG_WR(bp, BNX2_RPM_CONFIG, val); | |
3347 | break; | |
3348 | } | |
829ca9a3 | 3349 | case PCI_D3hot: { |
b6016b76 MC |
3350 | int i; |
3351 | u32 val, wol_msg; | |
3352 | ||
3353 | if (bp->wol) { | |
3354 | u32 advertising; | |
3355 | u8 autoneg; | |
3356 | ||
3357 | autoneg = bp->autoneg; | |
3358 | advertising = bp->advertising; | |
3359 | ||
239cd343 MC |
3360 | if (bp->phy_port == PORT_TP) { |
3361 | bp->autoneg = AUTONEG_SPEED; | |
3362 | bp->advertising = ADVERTISED_10baseT_Half | | |
3363 | ADVERTISED_10baseT_Full | | |
3364 | ADVERTISED_100baseT_Half | | |
3365 | ADVERTISED_100baseT_Full | | |
3366 | ADVERTISED_Autoneg; | |
3367 | } | |
b6016b76 | 3368 | |
239cd343 MC |
3369 | spin_lock_bh(&bp->phy_lock); |
3370 | bnx2_setup_phy(bp, bp->phy_port); | |
3371 | spin_unlock_bh(&bp->phy_lock); | |
b6016b76 MC |
3372 | |
3373 | bp->autoneg = autoneg; | |
3374 | bp->advertising = advertising; | |
3375 | ||
3376 | bnx2_set_mac_addr(bp); | |
3377 | ||
3378 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
3379 | ||
3380 | /* Enable port mode. */ | |
3381 | val &= ~BNX2_EMAC_MODE_PORT; | |
239cd343 | 3382 | val |= BNX2_EMAC_MODE_MPKT_RCVD | |
b6016b76 | 3383 | BNX2_EMAC_MODE_ACPI_RCVD | |
b6016b76 | 3384 | BNX2_EMAC_MODE_MPKT; |
239cd343 MC |
3385 | if (bp->phy_port == PORT_TP) |
3386 | val |= BNX2_EMAC_MODE_PORT_MII; | |
3387 | else { | |
3388 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
3389 | if (bp->line_speed == SPEED_2500) | |
3390 | val |= BNX2_EMAC_MODE_25G_MODE; | |
3391 | } | |
b6016b76 MC |
3392 | |
3393 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
3394 | ||
3395 | /* receive all multicast */ | |
3396 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
3397 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
3398 | 0xffffffff); | |
3399 | } | |
3400 | REG_WR(bp, BNX2_EMAC_RX_MODE, | |
3401 | BNX2_EMAC_RX_MODE_SORT_MODE); | |
3402 | ||
3403 | val = 1 | BNX2_RPM_SORT_USER0_BC_EN | | |
3404 | BNX2_RPM_SORT_USER0_MC_EN; | |
3405 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | |
3406 | REG_WR(bp, BNX2_RPM_SORT_USER0, val); | |
3407 | REG_WR(bp, BNX2_RPM_SORT_USER0, val | | |
3408 | BNX2_RPM_SORT_USER0_ENA); | |
3409 | ||
3410 | /* Need to enable EMAC and RPM for WOL. */ | |
3411 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
3412 | BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | | |
3413 | BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | | |
3414 | BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); | |
3415 | ||
3416 | val = REG_RD(bp, BNX2_RPM_CONFIG); | |
3417 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | |
3418 | REG_WR(bp, BNX2_RPM_CONFIG, val); | |
3419 | ||
3420 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
3421 | } | |
3422 | else { | |
3423 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
3424 | } | |
3425 | ||
dda1e390 MC |
3426 | if (!(bp->flags & NO_WOL_FLAG)) |
3427 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0); | |
b6016b76 MC |
3428 | |
3429 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
3430 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || | |
3431 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) { | |
3432 | ||
3433 | if (bp->wol) | |
3434 | pmcsr |= 3; | |
3435 | } | |
3436 | else { | |
3437 | pmcsr |= 3; | |
3438 | } | |
3439 | if (bp->wol) { | |
3440 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
3441 | } | |
3442 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | |
3443 | pmcsr); | |
3444 | ||
3445 | /* No more memory access after this point until | |
3446 | * device is brought back to D0. | |
3447 | */ | |
3448 | udelay(50); | |
3449 | break; | |
3450 | } | |
3451 | default: | |
3452 | return -EINVAL; | |
3453 | } | |
3454 | return 0; | |
3455 | } | |
3456 | ||
3457 | static int | |
3458 | bnx2_acquire_nvram_lock(struct bnx2 *bp) | |
3459 | { | |
3460 | u32 val; | |
3461 | int j; | |
3462 | ||
3463 | /* Request access to the flash interface. */ | |
3464 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); | |
3465 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
3466 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | |
3467 | if (val & BNX2_NVM_SW_ARB_ARB_ARB2) | |
3468 | break; | |
3469 | ||
3470 | udelay(5); | |
3471 | } | |
3472 | ||
3473 | if (j >= NVRAM_TIMEOUT_COUNT) | |
3474 | return -EBUSY; | |
3475 | ||
3476 | return 0; | |
3477 | } | |
3478 | ||
3479 | static int | |
3480 | bnx2_release_nvram_lock(struct bnx2 *bp) | |
3481 | { | |
3482 | int j; | |
3483 | u32 val; | |
3484 | ||
3485 | /* Relinquish nvram interface. */ | |
3486 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); | |
3487 | ||
3488 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
3489 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | |
3490 | if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) | |
3491 | break; | |
3492 | ||
3493 | udelay(5); | |
3494 | } | |
3495 | ||
3496 | if (j >= NVRAM_TIMEOUT_COUNT) | |
3497 | return -EBUSY; | |
3498 | ||
3499 | return 0; | |
3500 | } | |
3501 | ||
3502 | ||
3503 | static int | |
3504 | bnx2_enable_nvram_write(struct bnx2 *bp) | |
3505 | { | |
3506 | u32 val; | |
3507 | ||
3508 | val = REG_RD(bp, BNX2_MISC_CFG); | |
3509 | REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); | |
3510 | ||
e30372c9 | 3511 | if (bp->flash_info->flags & BNX2_NV_WREN) { |
b6016b76 MC |
3512 | int j; |
3513 | ||
3514 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
3515 | REG_WR(bp, BNX2_NVM_COMMAND, | |
3516 | BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); | |
3517 | ||
3518 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
3519 | udelay(5); | |
3520 | ||
3521 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
3522 | if (val & BNX2_NVM_COMMAND_DONE) | |
3523 | break; | |
3524 | } | |
3525 | ||
3526 | if (j >= NVRAM_TIMEOUT_COUNT) | |
3527 | return -EBUSY; | |
3528 | } | |
3529 | return 0; | |
3530 | } | |
3531 | ||
3532 | static void | |
3533 | bnx2_disable_nvram_write(struct bnx2 *bp) | |
3534 | { | |
3535 | u32 val; | |
3536 | ||
3537 | val = REG_RD(bp, BNX2_MISC_CFG); | |
3538 | REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); | |
3539 | } | |
3540 | ||
3541 | ||
3542 | static void | |
3543 | bnx2_enable_nvram_access(struct bnx2 *bp) | |
3544 | { | |
3545 | u32 val; | |
3546 | ||
3547 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | |
3548 | /* Enable both bits, even on read. */ | |
6aa20a22 | 3549 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
b6016b76 MC |
3550 | val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); |
3551 | } | |
3552 | ||
3553 | static void | |
3554 | bnx2_disable_nvram_access(struct bnx2 *bp) | |
3555 | { | |
3556 | u32 val; | |
3557 | ||
3558 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | |
3559 | /* Disable both bits, even after read. */ | |
6aa20a22 | 3560 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
b6016b76 MC |
3561 | val & ~(BNX2_NVM_ACCESS_ENABLE_EN | |
3562 | BNX2_NVM_ACCESS_ENABLE_WR_EN)); | |
3563 | } | |
3564 | ||
3565 | static int | |
3566 | bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) | |
3567 | { | |
3568 | u32 cmd; | |
3569 | int j; | |
3570 | ||
e30372c9 | 3571 | if (bp->flash_info->flags & BNX2_NV_BUFFERED) |
b6016b76 MC |
3572 | /* Buffered flash, no erase needed */ |
3573 | return 0; | |
3574 | ||
3575 | /* Build an erase command */ | |
3576 | cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | | |
3577 | BNX2_NVM_COMMAND_DOIT; | |
3578 | ||
3579 | /* Need to clear DONE bit separately. */ | |
3580 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
3581 | ||
3582 | /* Address of the NVRAM to read from. */ | |
3583 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
3584 | ||
3585 | /* Issue an erase command. */ | |
3586 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
3587 | ||
3588 | /* Wait for completion. */ | |
3589 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
3590 | u32 val; | |
3591 | ||
3592 | udelay(5); | |
3593 | ||
3594 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
3595 | if (val & BNX2_NVM_COMMAND_DONE) | |
3596 | break; | |
3597 | } | |
3598 | ||
3599 | if (j >= NVRAM_TIMEOUT_COUNT) | |
3600 | return -EBUSY; | |
3601 | ||
3602 | return 0; | |
3603 | } | |
3604 | ||
3605 | static int | |
3606 | bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) | |
3607 | { | |
3608 | u32 cmd; | |
3609 | int j; | |
3610 | ||
3611 | /* Build the command word. */ | |
3612 | cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; | |
3613 | ||
e30372c9 MC |
3614 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
3615 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
3616 | offset = ((offset / bp->flash_info->page_size) << |
3617 | bp->flash_info->page_bits) + | |
3618 | (offset % bp->flash_info->page_size); | |
3619 | } | |
3620 | ||
3621 | /* Need to clear DONE bit separately. */ | |
3622 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
3623 | ||
3624 | /* Address of the NVRAM to read from. */ | |
3625 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
3626 | ||
3627 | /* Issue a read command. */ | |
3628 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
3629 | ||
3630 | /* Wait for completion. */ | |
3631 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
3632 | u32 val; | |
3633 | ||
3634 | udelay(5); | |
3635 | ||
3636 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
3637 | if (val & BNX2_NVM_COMMAND_DONE) { | |
3638 | val = REG_RD(bp, BNX2_NVM_READ); | |
3639 | ||
3640 | val = be32_to_cpu(val); | |
3641 | memcpy(ret_val, &val, 4); | |
3642 | break; | |
3643 | } | |
3644 | } | |
3645 | if (j >= NVRAM_TIMEOUT_COUNT) | |
3646 | return -EBUSY; | |
3647 | ||
3648 | return 0; | |
3649 | } | |
3650 | ||
3651 | ||
3652 | static int | |
3653 | bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) | |
3654 | { | |
3655 | u32 cmd, val32; | |
3656 | int j; | |
3657 | ||
3658 | /* Build the command word. */ | |
3659 | cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; | |
3660 | ||
e30372c9 MC |
3661 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
3662 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
3663 | offset = ((offset / bp->flash_info->page_size) << |
3664 | bp->flash_info->page_bits) + | |
3665 | (offset % bp->flash_info->page_size); | |
3666 | } | |
3667 | ||
3668 | /* Need to clear DONE bit separately. */ | |
3669 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
3670 | ||
3671 | memcpy(&val32, val, 4); | |
3672 | val32 = cpu_to_be32(val32); | |
3673 | ||
3674 | /* Write the data. */ | |
3675 | REG_WR(bp, BNX2_NVM_WRITE, val32); | |
3676 | ||
3677 | /* Address of the NVRAM to write to. */ | |
3678 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
3679 | ||
3680 | /* Issue the write command. */ | |
3681 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
3682 | ||
3683 | /* Wait for completion. */ | |
3684 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
3685 | udelay(5); | |
3686 | ||
3687 | if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) | |
3688 | break; | |
3689 | } | |
3690 | if (j >= NVRAM_TIMEOUT_COUNT) | |
3691 | return -EBUSY; | |
3692 | ||
3693 | return 0; | |
3694 | } | |
3695 | ||
3696 | static int | |
3697 | bnx2_init_nvram(struct bnx2 *bp) | |
3698 | { | |
3699 | u32 val; | |
e30372c9 | 3700 | int j, entry_count, rc = 0; |
b6016b76 MC |
3701 | struct flash_spec *flash; |
3702 | ||
e30372c9 MC |
3703 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
3704 | bp->flash_info = &flash_5709; | |
3705 | goto get_flash_size; | |
3706 | } | |
3707 | ||
b6016b76 MC |
3708 | /* Determine the selected interface. */ |
3709 | val = REG_RD(bp, BNX2_NVM_CFG1); | |
3710 | ||
ff8ac609 | 3711 | entry_count = ARRAY_SIZE(flash_table); |
b6016b76 | 3712 | |
b6016b76 MC |
3713 | if (val & 0x40000000) { |
3714 | ||
3715 | /* Flash interface has been reconfigured */ | |
3716 | for (j = 0, flash = &flash_table[0]; j < entry_count; | |
37137709 MC |
3717 | j++, flash++) { |
3718 | if ((val & FLASH_BACKUP_STRAP_MASK) == | |
3719 | (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { | |
b6016b76 MC |
3720 | bp->flash_info = flash; |
3721 | break; | |
3722 | } | |
3723 | } | |
3724 | } | |
3725 | else { | |
37137709 | 3726 | u32 mask; |
b6016b76 MC |
3727 | /* Not yet been reconfigured */ |
3728 | ||
37137709 MC |
3729 | if (val & (1 << 23)) |
3730 | mask = FLASH_BACKUP_STRAP_MASK; | |
3731 | else | |
3732 | mask = FLASH_STRAP_MASK; | |
3733 | ||
b6016b76 MC |
3734 | for (j = 0, flash = &flash_table[0]; j < entry_count; |
3735 | j++, flash++) { | |
3736 | ||
37137709 | 3737 | if ((val & mask) == (flash->strapping & mask)) { |
b6016b76 MC |
3738 | bp->flash_info = flash; |
3739 | ||
3740 | /* Request access to the flash interface. */ | |
3741 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
3742 | return rc; | |
3743 | ||
3744 | /* Enable access to flash interface */ | |
3745 | bnx2_enable_nvram_access(bp); | |
3746 | ||
3747 | /* Reconfigure the flash interface */ | |
3748 | REG_WR(bp, BNX2_NVM_CFG1, flash->config1); | |
3749 | REG_WR(bp, BNX2_NVM_CFG2, flash->config2); | |
3750 | REG_WR(bp, BNX2_NVM_CFG3, flash->config3); | |
3751 | REG_WR(bp, BNX2_NVM_WRITE1, flash->write1); | |
3752 | ||
3753 | /* Disable access to flash interface */ | |
3754 | bnx2_disable_nvram_access(bp); | |
3755 | bnx2_release_nvram_lock(bp); | |
3756 | ||
3757 | break; | |
3758 | } | |
3759 | } | |
3760 | } /* if (val & 0x40000000) */ | |
3761 | ||
3762 | if (j == entry_count) { | |
3763 | bp->flash_info = NULL; | |
2f23c523 | 3764 | printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n"); |
1122db71 | 3765 | return -ENODEV; |
b6016b76 MC |
3766 | } |
3767 | ||
e30372c9 | 3768 | get_flash_size: |
1122db71 MC |
3769 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2); |
3770 | val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; | |
3771 | if (val) | |
3772 | bp->flash_size = val; | |
3773 | else | |
3774 | bp->flash_size = bp->flash_info->total_size; | |
3775 | ||
b6016b76 MC |
3776 | return rc; |
3777 | } | |
3778 | ||
3779 | static int | |
3780 | bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, | |
3781 | int buf_size) | |
3782 | { | |
3783 | int rc = 0; | |
3784 | u32 cmd_flags, offset32, len32, extra; | |
3785 | ||
3786 | if (buf_size == 0) | |
3787 | return 0; | |
3788 | ||
3789 | /* Request access to the flash interface. */ | |
3790 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
3791 | return rc; | |
3792 | ||
3793 | /* Enable access to flash interface */ | |
3794 | bnx2_enable_nvram_access(bp); | |
3795 | ||
3796 | len32 = buf_size; | |
3797 | offset32 = offset; | |
3798 | extra = 0; | |
3799 | ||
3800 | cmd_flags = 0; | |
3801 | ||
3802 | if (offset32 & 3) { | |
3803 | u8 buf[4]; | |
3804 | u32 pre_len; | |
3805 | ||
3806 | offset32 &= ~3; | |
3807 | pre_len = 4 - (offset & 3); | |
3808 | ||
3809 | if (pre_len >= len32) { | |
3810 | pre_len = len32; | |
3811 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
3812 | BNX2_NVM_COMMAND_LAST; | |
3813 | } | |
3814 | else { | |
3815 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
3816 | } | |
3817 | ||
3818 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
3819 | ||
3820 | if (rc) | |
3821 | return rc; | |
3822 | ||
3823 | memcpy(ret_buf, buf + (offset & 3), pre_len); | |
3824 | ||
3825 | offset32 += 4; | |
3826 | ret_buf += pre_len; | |
3827 | len32 -= pre_len; | |
3828 | } | |
3829 | if (len32 & 3) { | |
3830 | extra = 4 - (len32 & 3); | |
3831 | len32 = (len32 + 4) & ~3; | |
3832 | } | |
3833 | ||
3834 | if (len32 == 4) { | |
3835 | u8 buf[4]; | |
3836 | ||
3837 | if (cmd_flags) | |
3838 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
3839 | else | |
3840 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
3841 | BNX2_NVM_COMMAND_LAST; | |
3842 | ||
3843 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
3844 | ||
3845 | memcpy(ret_buf, buf, 4 - extra); | |
3846 | } | |
3847 | else if (len32 > 0) { | |
3848 | u8 buf[4]; | |
3849 | ||
3850 | /* Read the first word. */ | |
3851 | if (cmd_flags) | |
3852 | cmd_flags = 0; | |
3853 | else | |
3854 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
3855 | ||
3856 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); | |
3857 | ||
3858 | /* Advance to the next dword. */ | |
3859 | offset32 += 4; | |
3860 | ret_buf += 4; | |
3861 | len32 -= 4; | |
3862 | ||
3863 | while (len32 > 4 && rc == 0) { | |
3864 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); | |
3865 | ||
3866 | /* Advance to the next dword. */ | |
3867 | offset32 += 4; | |
3868 | ret_buf += 4; | |
3869 | len32 -= 4; | |
3870 | } | |
3871 | ||
3872 | if (rc) | |
3873 | return rc; | |
3874 | ||
3875 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
3876 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
3877 | ||
3878 | memcpy(ret_buf, buf, 4 - extra); | |
3879 | } | |
3880 | ||
3881 | /* Disable access to flash interface */ | |
3882 | bnx2_disable_nvram_access(bp); | |
3883 | ||
3884 | bnx2_release_nvram_lock(bp); | |
3885 | ||
3886 | return rc; | |
3887 | } | |
3888 | ||
3889 | static int | |
3890 | bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | |
3891 | int buf_size) | |
3892 | { | |
3893 | u32 written, offset32, len32; | |
e6be763f | 3894 | u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; |
b6016b76 MC |
3895 | int rc = 0; |
3896 | int align_start, align_end; | |
3897 | ||
3898 | buf = data_buf; | |
3899 | offset32 = offset; | |
3900 | len32 = buf_size; | |
3901 | align_start = align_end = 0; | |
3902 | ||
3903 | if ((align_start = (offset32 & 3))) { | |
3904 | offset32 &= ~3; | |
c873879c MC |
3905 | len32 += align_start; |
3906 | if (len32 < 4) | |
3907 | len32 = 4; | |
b6016b76 MC |
3908 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) |
3909 | return rc; | |
3910 | } | |
3911 | ||
3912 | if (len32 & 3) { | |
c873879c MC |
3913 | align_end = 4 - (len32 & 3); |
3914 | len32 += align_end; | |
3915 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) | |
3916 | return rc; | |
b6016b76 MC |
3917 | } |
3918 | ||
3919 | if (align_start || align_end) { | |
e6be763f MC |
3920 | align_buf = kmalloc(len32, GFP_KERNEL); |
3921 | if (align_buf == NULL) | |
b6016b76 MC |
3922 | return -ENOMEM; |
3923 | if (align_start) { | |
e6be763f | 3924 | memcpy(align_buf, start, 4); |
b6016b76 MC |
3925 | } |
3926 | if (align_end) { | |
e6be763f | 3927 | memcpy(align_buf + len32 - 4, end, 4); |
b6016b76 | 3928 | } |
e6be763f MC |
3929 | memcpy(align_buf + align_start, data_buf, buf_size); |
3930 | buf = align_buf; | |
b6016b76 MC |
3931 | } |
3932 | ||
e30372c9 | 3933 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
ae181bc4 MC |
3934 | flash_buffer = kmalloc(264, GFP_KERNEL); |
3935 | if (flash_buffer == NULL) { | |
3936 | rc = -ENOMEM; | |
3937 | goto nvram_write_end; | |
3938 | } | |
3939 | } | |
3940 | ||
b6016b76 MC |
3941 | written = 0; |
3942 | while ((written < len32) && (rc == 0)) { | |
3943 | u32 page_start, page_end, data_start, data_end; | |
3944 | u32 addr, cmd_flags; | |
3945 | int i; | |
b6016b76 MC |
3946 | |
3947 | /* Find the page_start addr */ | |
3948 | page_start = offset32 + written; | |
3949 | page_start -= (page_start % bp->flash_info->page_size); | |
3950 | /* Find the page_end addr */ | |
3951 | page_end = page_start + bp->flash_info->page_size; | |
3952 | /* Find the data_start addr */ | |
3953 | data_start = (written == 0) ? offset32 : page_start; | |
3954 | /* Find the data_end addr */ | |
6aa20a22 | 3955 | data_end = (page_end > offset32 + len32) ? |
b6016b76 MC |
3956 | (offset32 + len32) : page_end; |
3957 | ||
3958 | /* Request access to the flash interface. */ | |
3959 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
3960 | goto nvram_write_end; | |
3961 | ||
3962 | /* Enable access to flash interface */ | |
3963 | bnx2_enable_nvram_access(bp); | |
3964 | ||
3965 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
e30372c9 | 3966 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
3967 | int j; |
3968 | ||
3969 | /* Read the whole page into the buffer | |
3970 | * (non-buffer flash only) */ | |
3971 | for (j = 0; j < bp->flash_info->page_size; j += 4) { | |
3972 | if (j == (bp->flash_info->page_size - 4)) { | |
3973 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
3974 | } | |
3975 | rc = bnx2_nvram_read_dword(bp, | |
6aa20a22 JG |
3976 | page_start + j, |
3977 | &flash_buffer[j], | |
b6016b76 MC |
3978 | cmd_flags); |
3979 | ||
3980 | if (rc) | |
3981 | goto nvram_write_end; | |
3982 | ||
3983 | cmd_flags = 0; | |
3984 | } | |
3985 | } | |
3986 | ||
3987 | /* Enable writes to flash interface (unlock write-protect) */ | |
3988 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) | |
3989 | goto nvram_write_end; | |
3990 | ||
b6016b76 MC |
3991 | /* Loop to write back the buffer data from page_start to |
3992 | * data_start */ | |
3993 | i = 0; | |
e30372c9 | 3994 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
c873879c MC |
3995 | /* Erase the page */ |
3996 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | |
3997 | goto nvram_write_end; | |
3998 | ||
3999 | /* Re-enable the write again for the actual write */ | |
4000 | bnx2_enable_nvram_write(bp); | |
4001 | ||
b6016b76 MC |
4002 | for (addr = page_start; addr < data_start; |
4003 | addr += 4, i += 4) { | |
6aa20a22 | 4004 | |
b6016b76 MC |
4005 | rc = bnx2_nvram_write_dword(bp, addr, |
4006 | &flash_buffer[i], cmd_flags); | |
4007 | ||
4008 | if (rc != 0) | |
4009 | goto nvram_write_end; | |
4010 | ||
4011 | cmd_flags = 0; | |
4012 | } | |
4013 | } | |
4014 | ||
4015 | /* Loop to write the new data from data_start to data_end */ | |
bae25761 | 4016 | for (addr = data_start; addr < data_end; addr += 4, i += 4) { |
b6016b76 | 4017 | if ((addr == page_end - 4) || |
e30372c9 | 4018 | ((bp->flash_info->flags & BNX2_NV_BUFFERED) && |
b6016b76 MC |
4019 | (addr == data_end - 4))) { |
4020 | ||
4021 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
4022 | } | |
4023 | rc = bnx2_nvram_write_dword(bp, addr, buf, | |
4024 | cmd_flags); | |
4025 | ||
4026 | if (rc != 0) | |
4027 | goto nvram_write_end; | |
4028 | ||
4029 | cmd_flags = 0; | |
4030 | buf += 4; | |
4031 | } | |
4032 | ||
4033 | /* Loop to write back the buffer data from data_end | |
4034 | * to page_end */ | |
e30372c9 | 4035 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
4036 | for (addr = data_end; addr < page_end; |
4037 | addr += 4, i += 4) { | |
6aa20a22 | 4038 | |
b6016b76 MC |
4039 | if (addr == page_end-4) { |
4040 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4041 | } | |
4042 | rc = bnx2_nvram_write_dword(bp, addr, | |
4043 | &flash_buffer[i], cmd_flags); | |
4044 | ||
4045 | if (rc != 0) | |
4046 | goto nvram_write_end; | |
4047 | ||
4048 | cmd_flags = 0; | |
4049 | } | |
4050 | } | |
4051 | ||
4052 | /* Disable writes to flash interface (lock write-protect) */ | |
4053 | bnx2_disable_nvram_write(bp); | |
4054 | ||
4055 | /* Disable access to flash interface */ | |
4056 | bnx2_disable_nvram_access(bp); | |
4057 | bnx2_release_nvram_lock(bp); | |
4058 | ||
4059 | /* Increment written */ | |
4060 | written += data_end - data_start; | |
4061 | } | |
4062 | ||
4063 | nvram_write_end: | |
e6be763f MC |
4064 | kfree(flash_buffer); |
4065 | kfree(align_buf); | |
b6016b76 MC |
4066 | return rc; |
4067 | } | |
4068 | ||
0d8a6571 MC |
4069 | static void |
4070 | bnx2_init_remote_phy(struct bnx2 *bp) | |
4071 | { | |
4072 | u32 val; | |
4073 | ||
4074 | bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG; | |
4075 | if (!(bp->phy_flags & PHY_SERDES_FLAG)) | |
4076 | return; | |
4077 | ||
4078 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB); | |
4079 | if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) | |
4080 | return; | |
4081 | ||
4082 | if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) { | |
0d8a6571 MC |
4083 | bp->phy_flags |= REMOTE_PHY_CAP_FLAG; |
4084 | ||
4085 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); | |
4086 | if (val & BNX2_LINK_STATUS_SERDES_LINK) | |
4087 | bp->phy_port = PORT_FIBRE; | |
4088 | else | |
4089 | bp->phy_port = PORT_TP; | |
489310a4 MC |
4090 | |
4091 | if (netif_running(bp->dev)) { | |
4092 | u32 sig; | |
4093 | ||
4094 | if (val & BNX2_LINK_STATUS_LINK_UP) { | |
4095 | bp->link_up = 1; | |
4096 | netif_carrier_on(bp->dev); | |
4097 | } else { | |
4098 | bp->link_up = 0; | |
4099 | netif_carrier_off(bp->dev); | |
4100 | } | |
4101 | sig = BNX2_DRV_ACK_CAP_SIGNATURE | | |
4102 | BNX2_FW_CAP_REMOTE_PHY_CAPABLE; | |
4103 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB, | |
4104 | sig); | |
4105 | } | |
0d8a6571 MC |
4106 | } |
4107 | } | |
4108 | ||
b4b36042 MC |
4109 | static void |
4110 | bnx2_setup_msix_tbl(struct bnx2 *bp) | |
4111 | { | |
4112 | REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); | |
4113 | ||
4114 | REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); | |
4115 | REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); | |
4116 | } | |
4117 | ||
b6016b76 MC |
4118 | static int |
4119 | bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |
4120 | { | |
4121 | u32 val; | |
4122 | int i, rc = 0; | |
489310a4 | 4123 | u8 old_port; |
b6016b76 MC |
4124 | |
4125 | /* Wait for the current PCI transaction to complete before | |
4126 | * issuing a reset. */ | |
4127 | REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, | |
4128 | BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | | |
4129 | BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | | |
4130 | BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | | |
4131 | BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); | |
4132 | val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); | |
4133 | udelay(5); | |
4134 | ||
b090ae2b MC |
4135 | /* Wait for the firmware to tell us it is ok to issue a reset. */ |
4136 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1); | |
4137 | ||
b6016b76 MC |
4138 | /* Deposit a driver reset signature so the firmware knows that |
4139 | * this is a soft reset. */ | |
e3648b3d | 4140 | REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE, |
b6016b76 MC |
4141 | BNX2_DRV_RESET_SIGNATURE_MAGIC); |
4142 | ||
b6016b76 MC |
4143 | /* Do a dummy read to force the chip to complete all current transaction |
4144 | * before we issue a reset. */ | |
4145 | val = REG_RD(bp, BNX2_MISC_ID); | |
4146 | ||
234754d5 MC |
4147 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4148 | REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); | |
4149 | REG_RD(bp, BNX2_MISC_COMMAND); | |
4150 | udelay(5); | |
b6016b76 | 4151 | |
234754d5 MC |
4152 | val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | |
4153 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
b6016b76 | 4154 | |
234754d5 | 4155 | pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val); |
b6016b76 | 4156 | |
234754d5 MC |
4157 | } else { |
4158 | val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4159 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
4160 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
4161 | ||
4162 | /* Chip reset. */ | |
4163 | REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); | |
4164 | ||
594a9dfa MC |
4165 | /* Reading back any register after chip reset will hang the |
4166 | * bus on 5706 A0 and A1. The msleep below provides plenty | |
4167 | * of margin for write posting. | |
4168 | */ | |
234754d5 | 4169 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || |
8e545881 AV |
4170 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) |
4171 | msleep(20); | |
b6016b76 | 4172 | |
234754d5 MC |
4173 | /* Reset takes approximate 30 usec */ |
4174 | for (i = 0; i < 10; i++) { | |
4175 | val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); | |
4176 | if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4177 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) | |
4178 | break; | |
4179 | udelay(10); | |
4180 | } | |
4181 | ||
4182 | if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4183 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { | |
4184 | printk(KERN_ERR PFX "Chip reset did not complete\n"); | |
4185 | return -EBUSY; | |
4186 | } | |
b6016b76 MC |
4187 | } |
4188 | ||
4189 | /* Make sure byte swapping is properly configured. */ | |
4190 | val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); | |
4191 | if (val != 0x01020304) { | |
4192 | printk(KERN_ERR PFX "Chip not in correct endian mode\n"); | |
4193 | return -ENODEV; | |
4194 | } | |
4195 | ||
b6016b76 | 4196 | /* Wait for the firmware to finish its initialization. */ |
b090ae2b MC |
4197 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0); |
4198 | if (rc) | |
4199 | return rc; | |
b6016b76 | 4200 | |
0d8a6571 | 4201 | spin_lock_bh(&bp->phy_lock); |
489310a4 | 4202 | old_port = bp->phy_port; |
0d8a6571 | 4203 | bnx2_init_remote_phy(bp); |
489310a4 | 4204 | if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port) |
0d8a6571 MC |
4205 | bnx2_set_default_remote_link(bp); |
4206 | spin_unlock_bh(&bp->phy_lock); | |
4207 | ||
b6016b76 MC |
4208 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { |
4209 | /* Adjust the voltage regular to two steps lower. The default | |
4210 | * of this register is 0x0000000e. */ | |
4211 | REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); | |
4212 | ||
4213 | /* Remove bad rbuf memory from the free pool. */ | |
4214 | rc = bnx2_alloc_bad_rbuf(bp); | |
4215 | } | |
4216 | ||
b4b36042 MC |
4217 | if (bp->flags & USING_MSIX_FLAG) |
4218 | bnx2_setup_msix_tbl(bp); | |
4219 | ||
b6016b76 MC |
4220 | return rc; |
4221 | } | |
4222 | ||
4223 | static int | |
4224 | bnx2_init_chip(struct bnx2 *bp) | |
4225 | { | |
4226 | u32 val; | |
b4b36042 | 4227 | int rc, i; |
b6016b76 MC |
4228 | |
4229 | /* Make sure the interrupt is not active. */ | |
4230 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
4231 | ||
4232 | val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | | |
4233 | BNX2_DMA_CONFIG_DATA_WORD_SWAP | | |
4234 | #ifdef __BIG_ENDIAN | |
6aa20a22 | 4235 | BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | |
b6016b76 | 4236 | #endif |
6aa20a22 | 4237 | BNX2_DMA_CONFIG_CNTL_WORD_SWAP | |
b6016b76 MC |
4238 | DMA_READ_CHANS << 12 | |
4239 | DMA_WRITE_CHANS << 16; | |
4240 | ||
4241 | val |= (0x2 << 20) | (1 << 11); | |
4242 | ||
dda1e390 | 4243 | if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133)) |
b6016b76 MC |
4244 | val |= (1 << 23); |
4245 | ||
4246 | if ((CHIP_NUM(bp) == CHIP_NUM_5706) && | |
4247 | (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG)) | |
4248 | val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; | |
4249 | ||
4250 | REG_WR(bp, BNX2_DMA_CONFIG, val); | |
4251 | ||
4252 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
4253 | val = REG_RD(bp, BNX2_TDMA_CONFIG); | |
4254 | val |= BNX2_TDMA_CONFIG_ONE_DMA; | |
4255 | REG_WR(bp, BNX2_TDMA_CONFIG, val); | |
4256 | } | |
4257 | ||
4258 | if (bp->flags & PCIX_FLAG) { | |
4259 | u16 val16; | |
4260 | ||
4261 | pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4262 | &val16); | |
4263 | pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4264 | val16 & ~PCI_X_CMD_ERO); | |
4265 | } | |
4266 | ||
4267 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
4268 | BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | | |
4269 | BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | | |
4270 | BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); | |
4271 | ||
4272 | /* Initialize context mapping and zero out the quick contexts. The | |
4273 | * context block must have already been enabled. */ | |
641bdcd5 MC |
4274 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4275 | rc = bnx2_init_5709_context(bp); | |
4276 | if (rc) | |
4277 | return rc; | |
4278 | } else | |
59b47d8a | 4279 | bnx2_init_context(bp); |
b6016b76 | 4280 | |
fba9fe91 MC |
4281 | if ((rc = bnx2_init_cpus(bp)) != 0) |
4282 | return rc; | |
4283 | ||
b6016b76 MC |
4284 | bnx2_init_nvram(bp); |
4285 | ||
4286 | bnx2_set_mac_addr(bp); | |
4287 | ||
4288 | val = REG_RD(bp, BNX2_MQ_CONFIG); | |
4289 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; | |
4290 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; | |
68c9f75a MC |
4291 | if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1) |
4292 | val |= BNX2_MQ_CONFIG_HALT_DIS; | |
4293 | ||
b6016b76 MC |
4294 | REG_WR(bp, BNX2_MQ_CONFIG, val); |
4295 | ||
4296 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); | |
4297 | REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); | |
4298 | REG_WR(bp, BNX2_MQ_KNL_WIND_END, val); | |
4299 | ||
4300 | val = (BCM_PAGE_BITS - 8) << 24; | |
4301 | REG_WR(bp, BNX2_RV2P_CONFIG, val); | |
4302 | ||
4303 | /* Configure page size. */ | |
4304 | val = REG_RD(bp, BNX2_TBDR_CONFIG); | |
4305 | val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; | |
4306 | val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; | |
4307 | REG_WR(bp, BNX2_TBDR_CONFIG, val); | |
4308 | ||
4309 | val = bp->mac_addr[0] + | |
4310 | (bp->mac_addr[1] << 8) + | |
4311 | (bp->mac_addr[2] << 16) + | |
4312 | bp->mac_addr[3] + | |
4313 | (bp->mac_addr[4] << 8) + | |
4314 | (bp->mac_addr[5] << 16); | |
4315 | REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); | |
4316 | ||
4317 | /* Program the MTU. Also include 4 bytes for CRC32. */ | |
4318 | val = bp->dev->mtu + ETH_HLEN + 4; | |
4319 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) | |
4320 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; | |
4321 | REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); | |
4322 | ||
b4b36042 MC |
4323 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) |
4324 | bp->bnx2_napi[i].last_status_idx = 0; | |
4325 | ||
b6016b76 MC |
4326 | bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; |
4327 | ||
4328 | /* Set up how to generate a link change interrupt. */ | |
4329 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); | |
4330 | ||
4331 | REG_WR(bp, BNX2_HC_STATUS_ADDR_L, | |
4332 | (u64) bp->status_blk_mapping & 0xffffffff); | |
4333 | REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); | |
4334 | ||
4335 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L, | |
4336 | (u64) bp->stats_blk_mapping & 0xffffffff); | |
4337 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, | |
4338 | (u64) bp->stats_blk_mapping >> 32); | |
4339 | ||
6aa20a22 | 4340 | REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, |
b6016b76 MC |
4341 | (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); |
4342 | ||
4343 | REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, | |
4344 | (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); | |
4345 | ||
4346 | REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, | |
4347 | (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); | |
4348 | ||
4349 | REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); | |
4350 | ||
4351 | REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); | |
4352 | ||
4353 | REG_WR(bp, BNX2_HC_COM_TICKS, | |
4354 | (bp->com_ticks_int << 16) | bp->com_ticks); | |
4355 | ||
4356 | REG_WR(bp, BNX2_HC_CMD_TICKS, | |
4357 | (bp->cmd_ticks_int << 16) | bp->cmd_ticks); | |
4358 | ||
02537b06 MC |
4359 | if (CHIP_NUM(bp) == CHIP_NUM_5708) |
4360 | REG_WR(bp, BNX2_HC_STATS_TICKS, 0); | |
4361 | else | |
7ea6920e | 4362 | REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); |
b6016b76 MC |
4363 | REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ |
4364 | ||
4365 | if (CHIP_ID(bp) == CHIP_ID_5706_A1) | |
8e6a72c4 | 4366 | val = BNX2_HC_CONFIG_COLLECT_STATS; |
b6016b76 | 4367 | else { |
8e6a72c4 MC |
4368 | val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | |
4369 | BNX2_HC_CONFIG_COLLECT_STATS; | |
b6016b76 MC |
4370 | } |
4371 | ||
c76c0475 MC |
4372 | if (bp->flags & USING_MSIX_FLAG) { |
4373 | REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, | |
4374 | BNX2_HC_MSIX_BIT_VECTOR_VAL); | |
4375 | ||
4376 | REG_WR(bp, BNX2_HC_SB_CONFIG_1, | |
4377 | BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | | |
4378 | BNX2_HC_SB_CONFIG_1_ONE_SHOT); | |
4379 | ||
4380 | REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP_1, | |
4381 | (bp->tx_quick_cons_trip_int << 16) | | |
4382 | bp->tx_quick_cons_trip); | |
4383 | ||
4384 | REG_WR(bp, BNX2_HC_TX_TICKS_1, | |
4385 | (bp->tx_ticks_int << 16) | bp->tx_ticks); | |
4386 | ||
4387 | val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; | |
4388 | } | |
4389 | ||
8e6a72c4 MC |
4390 | if (bp->flags & ONE_SHOT_MSI_FLAG) |
4391 | val |= BNX2_HC_CONFIG_ONE_SHOT; | |
4392 | ||
4393 | REG_WR(bp, BNX2_HC_CONFIG, val); | |
4394 | ||
b6016b76 MC |
4395 | /* Clear internal stats counters. */ |
4396 | REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); | |
4397 | ||
da3e4fbe | 4398 | REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); |
b6016b76 MC |
4399 | |
4400 | /* Initialize the receive filter. */ | |
4401 | bnx2_set_rx_mode(bp->dev); | |
4402 | ||
0aa38df7 MC |
4403 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4404 | val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); | |
4405 | val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; | |
4406 | REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); | |
4407 | } | |
b090ae2b MC |
4408 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, |
4409 | 0); | |
b6016b76 | 4410 | |
df149d70 | 4411 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); |
b6016b76 MC |
4412 | REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); |
4413 | ||
4414 | udelay(20); | |
4415 | ||
bf5295bb MC |
4416 | bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND); |
4417 | ||
b090ae2b | 4418 | return rc; |
b6016b76 MC |
4419 | } |
4420 | ||
c76c0475 MC |
4421 | static void |
4422 | bnx2_clear_ring_states(struct bnx2 *bp) | |
4423 | { | |
4424 | struct bnx2_napi *bnapi; | |
4425 | int i; | |
4426 | ||
4427 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { | |
4428 | bnapi = &bp->bnx2_napi[i]; | |
4429 | ||
4430 | bnapi->tx_cons = 0; | |
4431 | bnapi->hw_tx_cons = 0; | |
4432 | bnapi->rx_prod_bseq = 0; | |
4433 | bnapi->rx_prod = 0; | |
4434 | bnapi->rx_cons = 0; | |
4435 | bnapi->rx_pg_prod = 0; | |
4436 | bnapi->rx_pg_cons = 0; | |
4437 | } | |
4438 | } | |
4439 | ||
59b47d8a MC |
4440 | static void |
4441 | bnx2_init_tx_context(struct bnx2 *bp, u32 cid) | |
4442 | { | |
4443 | u32 val, offset0, offset1, offset2, offset3; | |
4444 | ||
4445 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
4446 | offset0 = BNX2_L2CTX_TYPE_XI; | |
4447 | offset1 = BNX2_L2CTX_CMD_TYPE_XI; | |
4448 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; | |
4449 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; | |
4450 | } else { | |
4451 | offset0 = BNX2_L2CTX_TYPE; | |
4452 | offset1 = BNX2_L2CTX_CMD_TYPE; | |
4453 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; | |
4454 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; | |
4455 | } | |
4456 | val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; | |
4457 | CTX_WR(bp, GET_CID_ADDR(cid), offset0, val); | |
4458 | ||
4459 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); | |
4460 | CTX_WR(bp, GET_CID_ADDR(cid), offset1, val); | |
4461 | ||
4462 | val = (u64) bp->tx_desc_mapping >> 32; | |
4463 | CTX_WR(bp, GET_CID_ADDR(cid), offset2, val); | |
4464 | ||
4465 | val = (u64) bp->tx_desc_mapping & 0xffffffff; | |
4466 | CTX_WR(bp, GET_CID_ADDR(cid), offset3, val); | |
4467 | } | |
b6016b76 MC |
4468 | |
4469 | static void | |
4470 | bnx2_init_tx_ring(struct bnx2 *bp) | |
4471 | { | |
4472 | struct tx_bd *txbd; | |
c76c0475 MC |
4473 | u32 cid = TX_CID; |
4474 | struct bnx2_napi *bnapi; | |
4475 | ||
4476 | bp->tx_vec = 0; | |
4477 | if (bp->flags & USING_MSIX_FLAG) { | |
4478 | cid = TX_TSS_CID; | |
4479 | bp->tx_vec = BNX2_TX_VEC; | |
4480 | REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM | | |
4481 | (TX_TSS_CID << 7)); | |
4482 | } | |
4483 | bnapi = &bp->bnx2_napi[bp->tx_vec]; | |
b6016b76 | 4484 | |
2f8af120 MC |
4485 | bp->tx_wake_thresh = bp->tx_ring_size / 2; |
4486 | ||
b6016b76 | 4487 | txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; |
6aa20a22 | 4488 | |
b6016b76 MC |
4489 | txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32; |
4490 | txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff; | |
4491 | ||
4492 | bp->tx_prod = 0; | |
b6016b76 | 4493 | bp->tx_prod_bseq = 0; |
6aa20a22 | 4494 | |
59b47d8a MC |
4495 | bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; |
4496 | bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; | |
b6016b76 | 4497 | |
59b47d8a | 4498 | bnx2_init_tx_context(bp, cid); |
b6016b76 MC |
4499 | } |
4500 | ||
4501 | static void | |
5d5d0015 MC |
4502 | bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size, |
4503 | int num_rings) | |
b6016b76 | 4504 | { |
b6016b76 | 4505 | int i; |
5d5d0015 | 4506 | struct rx_bd *rxbd; |
6aa20a22 | 4507 | |
5d5d0015 | 4508 | for (i = 0; i < num_rings; i++) { |
13daffa2 | 4509 | int j; |
b6016b76 | 4510 | |
5d5d0015 | 4511 | rxbd = &rx_ring[i][0]; |
13daffa2 | 4512 | for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) { |
5d5d0015 | 4513 | rxbd->rx_bd_len = buf_size; |
13daffa2 MC |
4514 | rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; |
4515 | } | |
5d5d0015 | 4516 | if (i == (num_rings - 1)) |
13daffa2 MC |
4517 | j = 0; |
4518 | else | |
4519 | j = i + 1; | |
5d5d0015 MC |
4520 | rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; |
4521 | rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; | |
13daffa2 | 4522 | } |
5d5d0015 MC |
4523 | } |
4524 | ||
4525 | static void | |
4526 | bnx2_init_rx_ring(struct bnx2 *bp) | |
4527 | { | |
4528 | int i; | |
4529 | u16 prod, ring_prod; | |
4530 | u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID); | |
b4b36042 | 4531 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
5d5d0015 | 4532 | |
5d5d0015 MC |
4533 | bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping, |
4534 | bp->rx_buf_use_size, bp->rx_max_ring); | |
4535 | ||
4536 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); | |
47bf4246 MC |
4537 | if (bp->rx_pg_ring_size) { |
4538 | bnx2_init_rxbd_rings(bp->rx_pg_desc_ring, | |
4539 | bp->rx_pg_desc_mapping, | |
4540 | PAGE_SIZE, bp->rx_max_pg_ring); | |
4541 | val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; | |
4542 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); | |
4543 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, | |
4544 | BNX2_L2CTX_RBDC_JUMBO_KEY); | |
4545 | ||
4546 | val = (u64) bp->rx_pg_desc_mapping[0] >> 32; | |
4547 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); | |
4548 | ||
4549 | val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff; | |
4550 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); | |
4551 | ||
4552 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
4553 | REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); | |
4554 | } | |
b6016b76 MC |
4555 | |
4556 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; | |
4557 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; | |
4558 | val |= 0x02 << 8; | |
5d5d0015 | 4559 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); |
b6016b76 | 4560 | |
13daffa2 | 4561 | val = (u64) bp->rx_desc_mapping[0] >> 32; |
5d5d0015 | 4562 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); |
b6016b76 | 4563 | |
13daffa2 | 4564 | val = (u64) bp->rx_desc_mapping[0] & 0xffffffff; |
5d5d0015 | 4565 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); |
b6016b76 | 4566 | |
a1f60190 | 4567 | ring_prod = prod = bnapi->rx_pg_prod; |
47bf4246 MC |
4568 | for (i = 0; i < bp->rx_pg_ring_size; i++) { |
4569 | if (bnx2_alloc_rx_page(bp, ring_prod) < 0) | |
4570 | break; | |
4571 | prod = NEXT_RX_BD(prod); | |
4572 | ring_prod = RX_PG_RING_IDX(prod); | |
4573 | } | |
a1f60190 | 4574 | bnapi->rx_pg_prod = prod; |
47bf4246 | 4575 | |
a1f60190 | 4576 | ring_prod = prod = bnapi->rx_prod; |
236b6394 | 4577 | for (i = 0; i < bp->rx_ring_size; i++) { |
a1f60190 | 4578 | if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) { |
b6016b76 MC |
4579 | break; |
4580 | } | |
4581 | prod = NEXT_RX_BD(prod); | |
4582 | ring_prod = RX_RING_IDX(prod); | |
4583 | } | |
a1f60190 | 4584 | bnapi->rx_prod = prod; |
b6016b76 | 4585 | |
a1f60190 MC |
4586 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, |
4587 | bnapi->rx_pg_prod); | |
b6016b76 MC |
4588 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod); |
4589 | ||
a1f60190 | 4590 | REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq); |
b6016b76 MC |
4591 | } |
4592 | ||
5d5d0015 | 4593 | static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) |
13daffa2 | 4594 | { |
5d5d0015 | 4595 | u32 max, num_rings = 1; |
13daffa2 | 4596 | |
5d5d0015 MC |
4597 | while (ring_size > MAX_RX_DESC_CNT) { |
4598 | ring_size -= MAX_RX_DESC_CNT; | |
13daffa2 MC |
4599 | num_rings++; |
4600 | } | |
4601 | /* round to next power of 2 */ | |
5d5d0015 | 4602 | max = max_size; |
13daffa2 MC |
4603 | while ((max & num_rings) == 0) |
4604 | max >>= 1; | |
4605 | ||
4606 | if (num_rings != max) | |
4607 | max <<= 1; | |
4608 | ||
5d5d0015 MC |
4609 | return max; |
4610 | } | |
4611 | ||
4612 | static void | |
4613 | bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) | |
4614 | { | |
84eaa187 | 4615 | u32 rx_size, rx_space, jumbo_size; |
5d5d0015 MC |
4616 | |
4617 | /* 8 for CRC and VLAN */ | |
4618 | rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8; | |
4619 | ||
84eaa187 MC |
4620 | rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + |
4621 | sizeof(struct skb_shared_info); | |
4622 | ||
5d5d0015 | 4623 | bp->rx_copy_thresh = RX_COPY_THRESH; |
47bf4246 MC |
4624 | bp->rx_pg_ring_size = 0; |
4625 | bp->rx_max_pg_ring = 0; | |
4626 | bp->rx_max_pg_ring_idx = 0; | |
84eaa187 MC |
4627 | if (rx_space > PAGE_SIZE) { |
4628 | int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; | |
4629 | ||
4630 | jumbo_size = size * pages; | |
4631 | if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT) | |
4632 | jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT; | |
4633 | ||
4634 | bp->rx_pg_ring_size = jumbo_size; | |
4635 | bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, | |
4636 | MAX_RX_PG_RINGS); | |
4637 | bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1; | |
4638 | rx_size = RX_COPY_THRESH + bp->rx_offset; | |
4639 | bp->rx_copy_thresh = 0; | |
4640 | } | |
5d5d0015 MC |
4641 | |
4642 | bp->rx_buf_use_size = rx_size; | |
4643 | /* hw alignment */ | |
4644 | bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN; | |
1db82f2a | 4645 | bp->rx_jumbo_thresh = rx_size - bp->rx_offset; |
5d5d0015 MC |
4646 | bp->rx_ring_size = size; |
4647 | bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS); | |
13daffa2 MC |
4648 | bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1; |
4649 | } | |
4650 | ||
b6016b76 MC |
4651 | static void |
4652 | bnx2_free_tx_skbs(struct bnx2 *bp) | |
4653 | { | |
4654 | int i; | |
4655 | ||
4656 | if (bp->tx_buf_ring == NULL) | |
4657 | return; | |
4658 | ||
4659 | for (i = 0; i < TX_DESC_CNT; ) { | |
4660 | struct sw_bd *tx_buf = &bp->tx_buf_ring[i]; | |
4661 | struct sk_buff *skb = tx_buf->skb; | |
4662 | int j, last; | |
4663 | ||
4664 | if (skb == NULL) { | |
4665 | i++; | |
4666 | continue; | |
4667 | } | |
4668 | ||
4669 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), | |
4670 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
4671 | ||
4672 | tx_buf->skb = NULL; | |
4673 | ||
4674 | last = skb_shinfo(skb)->nr_frags; | |
4675 | for (j = 0; j < last; j++) { | |
4676 | tx_buf = &bp->tx_buf_ring[i + j + 1]; | |
4677 | pci_unmap_page(bp->pdev, | |
4678 | pci_unmap_addr(tx_buf, mapping), | |
4679 | skb_shinfo(skb)->frags[j].size, | |
4680 | PCI_DMA_TODEVICE); | |
4681 | } | |
745720e5 | 4682 | dev_kfree_skb(skb); |
b6016b76 MC |
4683 | i += j + 1; |
4684 | } | |
4685 | ||
4686 | } | |
4687 | ||
4688 | static void | |
4689 | bnx2_free_rx_skbs(struct bnx2 *bp) | |
4690 | { | |
4691 | int i; | |
4692 | ||
4693 | if (bp->rx_buf_ring == NULL) | |
4694 | return; | |
4695 | ||
13daffa2 | 4696 | for (i = 0; i < bp->rx_max_ring_idx; i++) { |
b6016b76 MC |
4697 | struct sw_bd *rx_buf = &bp->rx_buf_ring[i]; |
4698 | struct sk_buff *skb = rx_buf->skb; | |
4699 | ||
05d0f1cf | 4700 | if (skb == NULL) |
b6016b76 MC |
4701 | continue; |
4702 | ||
4703 | pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), | |
4704 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); | |
4705 | ||
4706 | rx_buf->skb = NULL; | |
4707 | ||
745720e5 | 4708 | dev_kfree_skb(skb); |
b6016b76 | 4709 | } |
47bf4246 MC |
4710 | for (i = 0; i < bp->rx_max_pg_ring_idx; i++) |
4711 | bnx2_free_rx_page(bp, i); | |
b6016b76 MC |
4712 | } |
4713 | ||
4714 | static void | |
4715 | bnx2_free_skbs(struct bnx2 *bp) | |
4716 | { | |
4717 | bnx2_free_tx_skbs(bp); | |
4718 | bnx2_free_rx_skbs(bp); | |
4719 | } | |
4720 | ||
4721 | static int | |
4722 | bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) | |
4723 | { | |
4724 | int rc; | |
4725 | ||
4726 | rc = bnx2_reset_chip(bp, reset_code); | |
4727 | bnx2_free_skbs(bp); | |
4728 | if (rc) | |
4729 | return rc; | |
4730 | ||
fba9fe91 MC |
4731 | if ((rc = bnx2_init_chip(bp)) != 0) |
4732 | return rc; | |
4733 | ||
c76c0475 | 4734 | bnx2_clear_ring_states(bp); |
b6016b76 MC |
4735 | bnx2_init_tx_ring(bp); |
4736 | bnx2_init_rx_ring(bp); | |
4737 | return 0; | |
4738 | } | |
4739 | ||
4740 | static int | |
4741 | bnx2_init_nic(struct bnx2 *bp) | |
4742 | { | |
4743 | int rc; | |
4744 | ||
4745 | if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) | |
4746 | return rc; | |
4747 | ||
80be4434 | 4748 | spin_lock_bh(&bp->phy_lock); |
b6016b76 MC |
4749 | bnx2_init_phy(bp); |
4750 | bnx2_set_link(bp); | |
0d8a6571 | 4751 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
4752 | return 0; |
4753 | } | |
4754 | ||
4755 | static int | |
4756 | bnx2_test_registers(struct bnx2 *bp) | |
4757 | { | |
4758 | int ret; | |
5bae30c9 | 4759 | int i, is_5709; |
f71e1309 | 4760 | static const struct { |
b6016b76 MC |
4761 | u16 offset; |
4762 | u16 flags; | |
5bae30c9 | 4763 | #define BNX2_FL_NOT_5709 1 |
b6016b76 MC |
4764 | u32 rw_mask; |
4765 | u32 ro_mask; | |
4766 | } reg_tbl[] = { | |
4767 | { 0x006c, 0, 0x00000000, 0x0000003f }, | |
4768 | { 0x0090, 0, 0xffffffff, 0x00000000 }, | |
4769 | { 0x0094, 0, 0x00000000, 0x00000000 }, | |
4770 | ||
5bae30c9 MC |
4771 | { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, |
4772 | { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
4773 | { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
4774 | { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, | |
4775 | { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, | |
4776 | { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
4777 | { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, | |
4778 | { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
4779 | { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
4780 | ||
4781 | { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
4782 | { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
4783 | { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
4784 | { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
4785 | { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
4786 | { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
4787 | ||
4788 | { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
4789 | { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, | |
4790 | { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, | |
b6016b76 MC |
4791 | |
4792 | { 0x1000, 0, 0x00000000, 0x00000001 }, | |
4793 | { 0x1004, 0, 0x00000000, 0x000f0001 }, | |
b6016b76 MC |
4794 | |
4795 | { 0x1408, 0, 0x01c00800, 0x00000000 }, | |
4796 | { 0x149c, 0, 0x8000ffff, 0x00000000 }, | |
4797 | { 0x14a8, 0, 0x00000000, 0x000001ff }, | |
5b0c76ad | 4798 | { 0x14ac, 0, 0x0fffffff, 0x10000000 }, |
b6016b76 MC |
4799 | { 0x14b0, 0, 0x00000002, 0x00000001 }, |
4800 | { 0x14b8, 0, 0x00000000, 0x00000000 }, | |
4801 | { 0x14c0, 0, 0x00000000, 0x00000009 }, | |
4802 | { 0x14c4, 0, 0x00003fff, 0x00000000 }, | |
4803 | { 0x14cc, 0, 0x00000000, 0x00000001 }, | |
4804 | { 0x14d0, 0, 0xffffffff, 0x00000000 }, | |
b6016b76 MC |
4805 | |
4806 | { 0x1800, 0, 0x00000000, 0x00000001 }, | |
4807 | { 0x1804, 0, 0x00000000, 0x00000003 }, | |
b6016b76 MC |
4808 | |
4809 | { 0x2800, 0, 0x00000000, 0x00000001 }, | |
4810 | { 0x2804, 0, 0x00000000, 0x00003f01 }, | |
4811 | { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, | |
4812 | { 0x2810, 0, 0xffff0000, 0x00000000 }, | |
4813 | { 0x2814, 0, 0xffff0000, 0x00000000 }, | |
4814 | { 0x2818, 0, 0xffff0000, 0x00000000 }, | |
4815 | { 0x281c, 0, 0xffff0000, 0x00000000 }, | |
4816 | { 0x2834, 0, 0xffffffff, 0x00000000 }, | |
4817 | { 0x2840, 0, 0x00000000, 0xffffffff }, | |
4818 | { 0x2844, 0, 0x00000000, 0xffffffff }, | |
4819 | { 0x2848, 0, 0xffffffff, 0x00000000 }, | |
4820 | { 0x284c, 0, 0xf800f800, 0x07ff07ff }, | |
4821 | ||
4822 | { 0x2c00, 0, 0x00000000, 0x00000011 }, | |
4823 | { 0x2c04, 0, 0x00000000, 0x00030007 }, | |
4824 | ||
b6016b76 MC |
4825 | { 0x3c00, 0, 0x00000000, 0x00000001 }, |
4826 | { 0x3c04, 0, 0x00000000, 0x00070000 }, | |
4827 | { 0x3c08, 0, 0x00007f71, 0x07f00000 }, | |
4828 | { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, | |
4829 | { 0x3c10, 0, 0xffffffff, 0x00000000 }, | |
4830 | { 0x3c14, 0, 0x00000000, 0xffffffff }, | |
4831 | { 0x3c18, 0, 0x00000000, 0xffffffff }, | |
4832 | { 0x3c1c, 0, 0xfffff000, 0x00000000 }, | |
4833 | { 0x3c20, 0, 0xffffff00, 0x00000000 }, | |
b6016b76 MC |
4834 | |
4835 | { 0x5004, 0, 0x00000000, 0x0000007f }, | |
4836 | { 0x5008, 0, 0x0f0007ff, 0x00000000 }, | |
b6016b76 | 4837 | |
b6016b76 MC |
4838 | { 0x5c00, 0, 0x00000000, 0x00000001 }, |
4839 | { 0x5c04, 0, 0x00000000, 0x0003000f }, | |
4840 | { 0x5c08, 0, 0x00000003, 0x00000000 }, | |
4841 | { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, | |
4842 | { 0x5c10, 0, 0x00000000, 0xffffffff }, | |
4843 | { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, | |
4844 | { 0x5c84, 0, 0x00000000, 0x0000f333 }, | |
4845 | { 0x5c88, 0, 0x00000000, 0x00077373 }, | |
4846 | { 0x5c8c, 0, 0x00000000, 0x0007f737 }, | |
4847 | ||
4848 | { 0x6808, 0, 0x0000ff7f, 0x00000000 }, | |
4849 | { 0x680c, 0, 0xffffffff, 0x00000000 }, | |
4850 | { 0x6810, 0, 0xffffffff, 0x00000000 }, | |
4851 | { 0x6814, 0, 0xffffffff, 0x00000000 }, | |
4852 | { 0x6818, 0, 0xffffffff, 0x00000000 }, | |
4853 | { 0x681c, 0, 0xffffffff, 0x00000000 }, | |
4854 | { 0x6820, 0, 0x00ff00ff, 0x00000000 }, | |
4855 | { 0x6824, 0, 0x00ff00ff, 0x00000000 }, | |
4856 | { 0x6828, 0, 0x00ff00ff, 0x00000000 }, | |
4857 | { 0x682c, 0, 0x03ff03ff, 0x00000000 }, | |
4858 | { 0x6830, 0, 0x03ff03ff, 0x00000000 }, | |
4859 | { 0x6834, 0, 0x03ff03ff, 0x00000000 }, | |
4860 | { 0x6838, 0, 0x03ff03ff, 0x00000000 }, | |
4861 | { 0x683c, 0, 0x0000ffff, 0x00000000 }, | |
4862 | { 0x6840, 0, 0x00000ff0, 0x00000000 }, | |
4863 | { 0x6844, 0, 0x00ffff00, 0x00000000 }, | |
4864 | { 0x684c, 0, 0xffffffff, 0x00000000 }, | |
4865 | { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, | |
4866 | { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, | |
4867 | { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, | |
4868 | { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, | |
4869 | { 0x6908, 0, 0x00000000, 0x0001ff0f }, | |
4870 | { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, | |
4871 | ||
4872 | { 0xffff, 0, 0x00000000, 0x00000000 }, | |
4873 | }; | |
4874 | ||
4875 | ret = 0; | |
5bae30c9 MC |
4876 | is_5709 = 0; |
4877 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
4878 | is_5709 = 1; | |
4879 | ||
b6016b76 MC |
4880 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { |
4881 | u32 offset, rw_mask, ro_mask, save_val, val; | |
5bae30c9 MC |
4882 | u16 flags = reg_tbl[i].flags; |
4883 | ||
4884 | if (is_5709 && (flags & BNX2_FL_NOT_5709)) | |
4885 | continue; | |
b6016b76 MC |
4886 | |
4887 | offset = (u32) reg_tbl[i].offset; | |
4888 | rw_mask = reg_tbl[i].rw_mask; | |
4889 | ro_mask = reg_tbl[i].ro_mask; | |
4890 | ||
14ab9b86 | 4891 | save_val = readl(bp->regview + offset); |
b6016b76 | 4892 | |
14ab9b86 | 4893 | writel(0, bp->regview + offset); |
b6016b76 | 4894 | |
14ab9b86 | 4895 | val = readl(bp->regview + offset); |
b6016b76 MC |
4896 | if ((val & rw_mask) != 0) { |
4897 | goto reg_test_err; | |
4898 | } | |
4899 | ||
4900 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
4901 | goto reg_test_err; | |
4902 | } | |
4903 | ||
14ab9b86 | 4904 | writel(0xffffffff, bp->regview + offset); |
b6016b76 | 4905 | |
14ab9b86 | 4906 | val = readl(bp->regview + offset); |
b6016b76 MC |
4907 | if ((val & rw_mask) != rw_mask) { |
4908 | goto reg_test_err; | |
4909 | } | |
4910 | ||
4911 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
4912 | goto reg_test_err; | |
4913 | } | |
4914 | ||
14ab9b86 | 4915 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
4916 | continue; |
4917 | ||
4918 | reg_test_err: | |
14ab9b86 | 4919 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
4920 | ret = -ENODEV; |
4921 | break; | |
4922 | } | |
4923 | return ret; | |
4924 | } | |
4925 | ||
4926 | static int | |
4927 | bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) | |
4928 | { | |
f71e1309 | 4929 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, |
b6016b76 MC |
4930 | 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; |
4931 | int i; | |
4932 | ||
4933 | for (i = 0; i < sizeof(test_pattern) / 4; i++) { | |
4934 | u32 offset; | |
4935 | ||
4936 | for (offset = 0; offset < size; offset += 4) { | |
4937 | ||
4938 | REG_WR_IND(bp, start + offset, test_pattern[i]); | |
4939 | ||
4940 | if (REG_RD_IND(bp, start + offset) != | |
4941 | test_pattern[i]) { | |
4942 | return -ENODEV; | |
4943 | } | |
4944 | } | |
4945 | } | |
4946 | return 0; | |
4947 | } | |
4948 | ||
4949 | static int | |
4950 | bnx2_test_memory(struct bnx2 *bp) | |
4951 | { | |
4952 | int ret = 0; | |
4953 | int i; | |
5bae30c9 | 4954 | static struct mem_entry { |
b6016b76 MC |
4955 | u32 offset; |
4956 | u32 len; | |
5bae30c9 | 4957 | } mem_tbl_5706[] = { |
b6016b76 | 4958 | { 0x60000, 0x4000 }, |
5b0c76ad | 4959 | { 0xa0000, 0x3000 }, |
b6016b76 MC |
4960 | { 0xe0000, 0x4000 }, |
4961 | { 0x120000, 0x4000 }, | |
4962 | { 0x1a0000, 0x4000 }, | |
4963 | { 0x160000, 0x4000 }, | |
4964 | { 0xffffffff, 0 }, | |
5bae30c9 MC |
4965 | }, |
4966 | mem_tbl_5709[] = { | |
4967 | { 0x60000, 0x4000 }, | |
4968 | { 0xa0000, 0x3000 }, | |
4969 | { 0xe0000, 0x4000 }, | |
4970 | { 0x120000, 0x4000 }, | |
4971 | { 0x1a0000, 0x4000 }, | |
4972 | { 0xffffffff, 0 }, | |
b6016b76 | 4973 | }; |
5bae30c9 MC |
4974 | struct mem_entry *mem_tbl; |
4975 | ||
4976 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
4977 | mem_tbl = mem_tbl_5709; | |
4978 | else | |
4979 | mem_tbl = mem_tbl_5706; | |
b6016b76 MC |
4980 | |
4981 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
4982 | if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, | |
4983 | mem_tbl[i].len)) != 0) { | |
4984 | return ret; | |
4985 | } | |
4986 | } | |
6aa20a22 | 4987 | |
b6016b76 MC |
4988 | return ret; |
4989 | } | |
4990 | ||
bc5a0690 MC |
4991 | #define BNX2_MAC_LOOPBACK 0 |
4992 | #define BNX2_PHY_LOOPBACK 1 | |
4993 | ||
b6016b76 | 4994 | static int |
bc5a0690 | 4995 | bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) |
b6016b76 MC |
4996 | { |
4997 | unsigned int pkt_size, num_pkts, i; | |
4998 | struct sk_buff *skb, *rx_skb; | |
4999 | unsigned char *packet; | |
bc5a0690 | 5000 | u16 rx_start_idx, rx_idx; |
b6016b76 MC |
5001 | dma_addr_t map; |
5002 | struct tx_bd *txbd; | |
5003 | struct sw_bd *rx_buf; | |
5004 | struct l2_fhdr *rx_hdr; | |
5005 | int ret = -ENODEV; | |
c76c0475 MC |
5006 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; |
5007 | ||
5008 | tx_napi = bnapi; | |
5009 | if (bp->flags & USING_MSIX_FLAG) | |
5010 | tx_napi = &bp->bnx2_napi[BNX2_TX_VEC]; | |
b6016b76 | 5011 | |
bc5a0690 MC |
5012 | if (loopback_mode == BNX2_MAC_LOOPBACK) { |
5013 | bp->loopback = MAC_LOOPBACK; | |
5014 | bnx2_set_mac_loopback(bp); | |
5015 | } | |
5016 | else if (loopback_mode == BNX2_PHY_LOOPBACK) { | |
489310a4 MC |
5017 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
5018 | return 0; | |
5019 | ||
80be4434 | 5020 | bp->loopback = PHY_LOOPBACK; |
bc5a0690 MC |
5021 | bnx2_set_phy_loopback(bp); |
5022 | } | |
5023 | else | |
5024 | return -EINVAL; | |
b6016b76 | 5025 | |
84eaa187 | 5026 | pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); |
932f3772 | 5027 | skb = netdev_alloc_skb(bp->dev, pkt_size); |
b6cbc3b6 JL |
5028 | if (!skb) |
5029 | return -ENOMEM; | |
b6016b76 | 5030 | packet = skb_put(skb, pkt_size); |
6634292b | 5031 | memcpy(packet, bp->dev->dev_addr, 6); |
b6016b76 MC |
5032 | memset(packet + 6, 0x0, 8); |
5033 | for (i = 14; i < pkt_size; i++) | |
5034 | packet[i] = (unsigned char) (i & 0xff); | |
5035 | ||
5036 | map = pci_map_single(bp->pdev, skb->data, pkt_size, | |
5037 | PCI_DMA_TODEVICE); | |
5038 | ||
bf5295bb MC |
5039 | REG_WR(bp, BNX2_HC_COMMAND, |
5040 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
5041 | ||
b6016b76 MC |
5042 | REG_RD(bp, BNX2_HC_COMMAND); |
5043 | ||
5044 | udelay(5); | |
35efa7c1 | 5045 | rx_start_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 | 5046 | |
b6016b76 MC |
5047 | num_pkts = 0; |
5048 | ||
bc5a0690 | 5049 | txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)]; |
b6016b76 MC |
5050 | |
5051 | txbd->tx_bd_haddr_hi = (u64) map >> 32; | |
5052 | txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; | |
5053 | txbd->tx_bd_mss_nbytes = pkt_size; | |
5054 | txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; | |
5055 | ||
5056 | num_pkts++; | |
bc5a0690 MC |
5057 | bp->tx_prod = NEXT_TX_BD(bp->tx_prod); |
5058 | bp->tx_prod_bseq += pkt_size; | |
b6016b76 | 5059 | |
234754d5 MC |
5060 | REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod); |
5061 | REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); | |
b6016b76 MC |
5062 | |
5063 | udelay(100); | |
5064 | ||
bf5295bb MC |
5065 | REG_WR(bp, BNX2_HC_COMMAND, |
5066 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
5067 | ||
b6016b76 MC |
5068 | REG_RD(bp, BNX2_HC_COMMAND); |
5069 | ||
5070 | udelay(5); | |
5071 | ||
5072 | pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); | |
745720e5 | 5073 | dev_kfree_skb(skb); |
b6016b76 | 5074 | |
c76c0475 | 5075 | if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod) |
b6016b76 | 5076 | goto loopback_test_done; |
b6016b76 | 5077 | |
35efa7c1 | 5078 | rx_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 MC |
5079 | if (rx_idx != rx_start_idx + num_pkts) { |
5080 | goto loopback_test_done; | |
5081 | } | |
5082 | ||
5083 | rx_buf = &bp->rx_buf_ring[rx_start_idx]; | |
5084 | rx_skb = rx_buf->skb; | |
5085 | ||
5086 | rx_hdr = (struct l2_fhdr *) rx_skb->data; | |
5087 | skb_reserve(rx_skb, bp->rx_offset); | |
5088 | ||
5089 | pci_dma_sync_single_for_cpu(bp->pdev, | |
5090 | pci_unmap_addr(rx_buf, mapping), | |
5091 | bp->rx_buf_size, PCI_DMA_FROMDEVICE); | |
5092 | ||
ade2bfe7 | 5093 | if (rx_hdr->l2_fhdr_status & |
b6016b76 MC |
5094 | (L2_FHDR_ERRORS_BAD_CRC | |
5095 | L2_FHDR_ERRORS_PHY_DECODE | | |
5096 | L2_FHDR_ERRORS_ALIGNMENT | | |
5097 | L2_FHDR_ERRORS_TOO_SHORT | | |
5098 | L2_FHDR_ERRORS_GIANT_FRAME)) { | |
5099 | ||
5100 | goto loopback_test_done; | |
5101 | } | |
5102 | ||
5103 | if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { | |
5104 | goto loopback_test_done; | |
5105 | } | |
5106 | ||
5107 | for (i = 14; i < pkt_size; i++) { | |
5108 | if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) { | |
5109 | goto loopback_test_done; | |
5110 | } | |
5111 | } | |
5112 | ||
5113 | ret = 0; | |
5114 | ||
5115 | loopback_test_done: | |
5116 | bp->loopback = 0; | |
5117 | return ret; | |
5118 | } | |
5119 | ||
bc5a0690 MC |
5120 | #define BNX2_MAC_LOOPBACK_FAILED 1 |
5121 | #define BNX2_PHY_LOOPBACK_FAILED 2 | |
5122 | #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \ | |
5123 | BNX2_PHY_LOOPBACK_FAILED) | |
5124 | ||
5125 | static int | |
5126 | bnx2_test_loopback(struct bnx2 *bp) | |
5127 | { | |
5128 | int rc = 0; | |
5129 | ||
5130 | if (!netif_running(bp->dev)) | |
5131 | return BNX2_LOOPBACK_FAILED; | |
5132 | ||
5133 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); | |
5134 | spin_lock_bh(&bp->phy_lock); | |
5135 | bnx2_init_phy(bp); | |
5136 | spin_unlock_bh(&bp->phy_lock); | |
5137 | if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) | |
5138 | rc |= BNX2_MAC_LOOPBACK_FAILED; | |
5139 | if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK)) | |
5140 | rc |= BNX2_PHY_LOOPBACK_FAILED; | |
5141 | return rc; | |
5142 | } | |
5143 | ||
b6016b76 MC |
5144 | #define NVRAM_SIZE 0x200 |
5145 | #define CRC32_RESIDUAL 0xdebb20e3 | |
5146 | ||
5147 | static int | |
5148 | bnx2_test_nvram(struct bnx2 *bp) | |
5149 | { | |
5150 | u32 buf[NVRAM_SIZE / 4]; | |
5151 | u8 *data = (u8 *) buf; | |
5152 | int rc = 0; | |
5153 | u32 magic, csum; | |
5154 | ||
5155 | if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) | |
5156 | goto test_nvram_done; | |
5157 | ||
5158 | magic = be32_to_cpu(buf[0]); | |
5159 | if (magic != 0x669955aa) { | |
5160 | rc = -ENODEV; | |
5161 | goto test_nvram_done; | |
5162 | } | |
5163 | ||
5164 | if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) | |
5165 | goto test_nvram_done; | |
5166 | ||
5167 | csum = ether_crc_le(0x100, data); | |
5168 | if (csum != CRC32_RESIDUAL) { | |
5169 | rc = -ENODEV; | |
5170 | goto test_nvram_done; | |
5171 | } | |
5172 | ||
5173 | csum = ether_crc_le(0x100, data + 0x100); | |
5174 | if (csum != CRC32_RESIDUAL) { | |
5175 | rc = -ENODEV; | |
5176 | } | |
5177 | ||
5178 | test_nvram_done: | |
5179 | return rc; | |
5180 | } | |
5181 | ||
5182 | static int | |
5183 | bnx2_test_link(struct bnx2 *bp) | |
5184 | { | |
5185 | u32 bmsr; | |
5186 | ||
489310a4 MC |
5187 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) { |
5188 | if (bp->link_up) | |
5189 | return 0; | |
5190 | return -ENODEV; | |
5191 | } | |
c770a65c | 5192 | spin_lock_bh(&bp->phy_lock); |
27a005b8 MC |
5193 | bnx2_enable_bmsr1(bp); |
5194 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5195 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5196 | bnx2_disable_bmsr1(bp); | |
c770a65c | 5197 | spin_unlock_bh(&bp->phy_lock); |
6aa20a22 | 5198 | |
b6016b76 MC |
5199 | if (bmsr & BMSR_LSTATUS) { |
5200 | return 0; | |
5201 | } | |
5202 | return -ENODEV; | |
5203 | } | |
5204 | ||
5205 | static int | |
5206 | bnx2_test_intr(struct bnx2 *bp) | |
5207 | { | |
5208 | int i; | |
b6016b76 MC |
5209 | u16 status_idx; |
5210 | ||
5211 | if (!netif_running(bp->dev)) | |
5212 | return -ENODEV; | |
5213 | ||
5214 | status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; | |
5215 | ||
5216 | /* This register is not touched during run-time. */ | |
bf5295bb | 5217 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
b6016b76 MC |
5218 | REG_RD(bp, BNX2_HC_COMMAND); |
5219 | ||
5220 | for (i = 0; i < 10; i++) { | |
5221 | if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != | |
5222 | status_idx) { | |
5223 | ||
5224 | break; | |
5225 | } | |
5226 | ||
5227 | msleep_interruptible(10); | |
5228 | } | |
5229 | if (i < 10) | |
5230 | return 0; | |
5231 | ||
5232 | return -ENODEV; | |
5233 | } | |
5234 | ||
5235 | static void | |
48b01e2d | 5236 | bnx2_5706_serdes_timer(struct bnx2 *bp) |
b6016b76 | 5237 | { |
48b01e2d MC |
5238 | spin_lock(&bp->phy_lock); |
5239 | if (bp->serdes_an_pending) | |
5240 | bp->serdes_an_pending--; | |
5241 | else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
5242 | u32 bmcr; | |
b6016b76 | 5243 | |
48b01e2d | 5244 | bp->current_interval = bp->timer_interval; |
cd339a0e | 5245 | |
ca58c3af | 5246 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 5247 | |
48b01e2d MC |
5248 | if (bmcr & BMCR_ANENABLE) { |
5249 | u32 phy1, phy2; | |
b6016b76 | 5250 | |
48b01e2d MC |
5251 | bnx2_write_phy(bp, 0x1c, 0x7c00); |
5252 | bnx2_read_phy(bp, 0x1c, &phy1); | |
cea94db9 | 5253 | |
48b01e2d MC |
5254 | bnx2_write_phy(bp, 0x17, 0x0f01); |
5255 | bnx2_read_phy(bp, 0x15, &phy2); | |
5256 | bnx2_write_phy(bp, 0x17, 0x0f01); | |
5257 | bnx2_read_phy(bp, 0x15, &phy2); | |
b6016b76 | 5258 | |
48b01e2d MC |
5259 | if ((phy1 & 0x10) && /* SIGNAL DETECT */ |
5260 | !(phy2 & 0x20)) { /* no CONFIG */ | |
5261 | ||
5262 | bmcr &= ~BMCR_ANENABLE; | |
5263 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
ca58c3af | 5264 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
48b01e2d MC |
5265 | bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG; |
5266 | } | |
b6016b76 | 5267 | } |
48b01e2d MC |
5268 | } |
5269 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && | |
5270 | (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { | |
5271 | u32 phy2; | |
b6016b76 | 5272 | |
48b01e2d MC |
5273 | bnx2_write_phy(bp, 0x17, 0x0f01); |
5274 | bnx2_read_phy(bp, 0x15, &phy2); | |
5275 | if (phy2 & 0x20) { | |
5276 | u32 bmcr; | |
cd339a0e | 5277 | |
ca58c3af | 5278 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
48b01e2d | 5279 | bmcr |= BMCR_ANENABLE; |
ca58c3af | 5280 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
b6016b76 | 5281 | |
48b01e2d MC |
5282 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; |
5283 | } | |
5284 | } else | |
5285 | bp->current_interval = bp->timer_interval; | |
b6016b76 | 5286 | |
48b01e2d MC |
5287 | spin_unlock(&bp->phy_lock); |
5288 | } | |
b6016b76 | 5289 | |
f8dd064e MC |
5290 | static void |
5291 | bnx2_5708_serdes_timer(struct bnx2 *bp) | |
5292 | { | |
0d8a6571 MC |
5293 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
5294 | return; | |
5295 | ||
f8dd064e MC |
5296 | if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) { |
5297 | bp->serdes_an_pending = 0; | |
5298 | return; | |
5299 | } | |
b6016b76 | 5300 | |
f8dd064e MC |
5301 | spin_lock(&bp->phy_lock); |
5302 | if (bp->serdes_an_pending) | |
5303 | bp->serdes_an_pending--; | |
5304 | else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
5305 | u32 bmcr; | |
b6016b76 | 5306 | |
ca58c3af | 5307 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
f8dd064e | 5308 | if (bmcr & BMCR_ANENABLE) { |
605a9e20 | 5309 | bnx2_enable_forced_2g5(bp); |
f8dd064e MC |
5310 | bp->current_interval = SERDES_FORCED_TIMEOUT; |
5311 | } else { | |
605a9e20 | 5312 | bnx2_disable_forced_2g5(bp); |
f8dd064e MC |
5313 | bp->serdes_an_pending = 2; |
5314 | bp->current_interval = bp->timer_interval; | |
b6016b76 | 5315 | } |
b6016b76 | 5316 | |
f8dd064e MC |
5317 | } else |
5318 | bp->current_interval = bp->timer_interval; | |
b6016b76 | 5319 | |
f8dd064e MC |
5320 | spin_unlock(&bp->phy_lock); |
5321 | } | |
5322 | ||
48b01e2d MC |
5323 | static void |
5324 | bnx2_timer(unsigned long data) | |
5325 | { | |
5326 | struct bnx2 *bp = (struct bnx2 *) data; | |
b6016b76 | 5327 | |
48b01e2d MC |
5328 | if (!netif_running(bp->dev)) |
5329 | return; | |
b6016b76 | 5330 | |
48b01e2d MC |
5331 | if (atomic_read(&bp->intr_sem) != 0) |
5332 | goto bnx2_restart_timer; | |
b6016b76 | 5333 | |
df149d70 | 5334 | bnx2_send_heart_beat(bp); |
b6016b76 | 5335 | |
48b01e2d | 5336 | bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); |
b6016b76 | 5337 | |
02537b06 MC |
5338 | /* workaround occasional corrupted counters */ |
5339 | if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks) | |
5340 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | | |
5341 | BNX2_HC_COMMAND_STATS_NOW); | |
5342 | ||
f8dd064e MC |
5343 | if (bp->phy_flags & PHY_SERDES_FLAG) { |
5344 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | |
5345 | bnx2_5706_serdes_timer(bp); | |
27a005b8 | 5346 | else |
f8dd064e | 5347 | bnx2_5708_serdes_timer(bp); |
b6016b76 MC |
5348 | } |
5349 | ||
5350 | bnx2_restart_timer: | |
cd339a0e | 5351 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
5352 | } |
5353 | ||
8e6a72c4 MC |
5354 | static int |
5355 | bnx2_request_irq(struct bnx2 *bp) | |
5356 | { | |
5357 | struct net_device *dev = bp->dev; | |
6d866ffc | 5358 | unsigned long flags; |
b4b36042 MC |
5359 | struct bnx2_irq *irq; |
5360 | int rc = 0, i; | |
8e6a72c4 | 5361 | |
b4b36042 | 5362 | if (bp->flags & USING_MSI_OR_MSIX_FLAG) |
6d866ffc MC |
5363 | flags = 0; |
5364 | else | |
5365 | flags = IRQF_SHARED; | |
b4b36042 MC |
5366 | |
5367 | for (i = 0; i < bp->irq_nvecs; i++) { | |
5368 | irq = &bp->irq_tbl[i]; | |
c76c0475 | 5369 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, |
b4b36042 MC |
5370 | dev); |
5371 | if (rc) | |
5372 | break; | |
5373 | irq->requested = 1; | |
5374 | } | |
8e6a72c4 MC |
5375 | return rc; |
5376 | } | |
5377 | ||
5378 | static void | |
5379 | bnx2_free_irq(struct bnx2 *bp) | |
5380 | { | |
5381 | struct net_device *dev = bp->dev; | |
b4b36042 MC |
5382 | struct bnx2_irq *irq; |
5383 | int i; | |
8e6a72c4 | 5384 | |
b4b36042 MC |
5385 | for (i = 0; i < bp->irq_nvecs; i++) { |
5386 | irq = &bp->irq_tbl[i]; | |
5387 | if (irq->requested) | |
5388 | free_irq(irq->vector, dev); | |
5389 | irq->requested = 0; | |
6d866ffc | 5390 | } |
b4b36042 MC |
5391 | if (bp->flags & USING_MSI_FLAG) |
5392 | pci_disable_msi(bp->pdev); | |
5393 | else if (bp->flags & USING_MSIX_FLAG) | |
5394 | pci_disable_msix(bp->pdev); | |
5395 | ||
5396 | bp->flags &= ~(USING_MSI_OR_MSIX_FLAG | ONE_SHOT_MSI_FLAG); | |
5397 | } | |
5398 | ||
5399 | static void | |
5400 | bnx2_enable_msix(struct bnx2 *bp) | |
5401 | { | |
5402 | bnx2_setup_msix_tbl(bp); | |
5403 | REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); | |
5404 | REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); | |
5405 | REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); | |
6d866ffc MC |
5406 | } |
5407 | ||
5408 | static void | |
5409 | bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) | |
5410 | { | |
5411 | bp->irq_tbl[0].handler = bnx2_interrupt; | |
5412 | strcpy(bp->irq_tbl[0].name, bp->dev->name); | |
b4b36042 MC |
5413 | bp->irq_nvecs = 1; |
5414 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
5415 | ||
5416 | if ((bp->flags & MSIX_CAP_FLAG) && !dis_msi) | |
5417 | bnx2_enable_msix(bp); | |
6d866ffc | 5418 | |
b4b36042 MC |
5419 | if ((bp->flags & MSI_CAP_FLAG) && !dis_msi && |
5420 | !(bp->flags & USING_MSIX_FLAG)) { | |
6d866ffc MC |
5421 | if (pci_enable_msi(bp->pdev) == 0) { |
5422 | bp->flags |= USING_MSI_FLAG; | |
5423 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | |
5424 | bp->flags |= ONE_SHOT_MSI_FLAG; | |
5425 | bp->irq_tbl[0].handler = bnx2_msi_1shot; | |
5426 | } else | |
5427 | bp->irq_tbl[0].handler = bnx2_msi; | |
b4b36042 MC |
5428 | |
5429 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
6d866ffc MC |
5430 | } |
5431 | } | |
8e6a72c4 MC |
5432 | } |
5433 | ||
b6016b76 MC |
5434 | /* Called with rtnl_lock */ |
5435 | static int | |
5436 | bnx2_open(struct net_device *dev) | |
5437 | { | |
972ec0d4 | 5438 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5439 | int rc; |
5440 | ||
1b2f922f MC |
5441 | netif_carrier_off(dev); |
5442 | ||
829ca9a3 | 5443 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 MC |
5444 | bnx2_disable_int(bp); |
5445 | ||
5446 | rc = bnx2_alloc_mem(bp); | |
5447 | if (rc) | |
5448 | return rc; | |
5449 | ||
6d866ffc | 5450 | bnx2_setup_int_mode(bp, disable_msi); |
35efa7c1 | 5451 | bnx2_napi_enable(bp); |
8e6a72c4 MC |
5452 | rc = bnx2_request_irq(bp); |
5453 | ||
b6016b76 | 5454 | if (rc) { |
35efa7c1 | 5455 | bnx2_napi_disable(bp); |
b6016b76 MC |
5456 | bnx2_free_mem(bp); |
5457 | return rc; | |
5458 | } | |
5459 | ||
5460 | rc = bnx2_init_nic(bp); | |
5461 | ||
5462 | if (rc) { | |
35efa7c1 | 5463 | bnx2_napi_disable(bp); |
8e6a72c4 | 5464 | bnx2_free_irq(bp); |
b6016b76 MC |
5465 | bnx2_free_skbs(bp); |
5466 | bnx2_free_mem(bp); | |
5467 | return rc; | |
5468 | } | |
6aa20a22 | 5469 | |
cd339a0e | 5470 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
5471 | |
5472 | atomic_set(&bp->intr_sem, 0); | |
5473 | ||
5474 | bnx2_enable_int(bp); | |
5475 | ||
5476 | if (bp->flags & USING_MSI_FLAG) { | |
5477 | /* Test MSI to make sure it is working | |
5478 | * If MSI test fails, go back to INTx mode | |
5479 | */ | |
5480 | if (bnx2_test_intr(bp) != 0) { | |
5481 | printk(KERN_WARNING PFX "%s: No interrupt was generated" | |
5482 | " using MSI, switching to INTx mode. Please" | |
5483 | " report this failure to the PCI maintainer" | |
5484 | " and include system chipset information.\n", | |
5485 | bp->dev->name); | |
5486 | ||
5487 | bnx2_disable_int(bp); | |
8e6a72c4 | 5488 | bnx2_free_irq(bp); |
b6016b76 | 5489 | |
6d866ffc MC |
5490 | bnx2_setup_int_mode(bp, 1); |
5491 | ||
b6016b76 MC |
5492 | rc = bnx2_init_nic(bp); |
5493 | ||
8e6a72c4 MC |
5494 | if (!rc) |
5495 | rc = bnx2_request_irq(bp); | |
5496 | ||
b6016b76 | 5497 | if (rc) { |
35efa7c1 | 5498 | bnx2_napi_disable(bp); |
b6016b76 MC |
5499 | bnx2_free_skbs(bp); |
5500 | bnx2_free_mem(bp); | |
5501 | del_timer_sync(&bp->timer); | |
5502 | return rc; | |
5503 | } | |
5504 | bnx2_enable_int(bp); | |
5505 | } | |
5506 | } | |
5507 | if (bp->flags & USING_MSI_FLAG) { | |
5508 | printk(KERN_INFO PFX "%s: using MSI\n", dev->name); | |
5509 | } | |
5510 | ||
5511 | netif_start_queue(dev); | |
5512 | ||
5513 | return 0; | |
5514 | } | |
5515 | ||
5516 | static void | |
c4028958 | 5517 | bnx2_reset_task(struct work_struct *work) |
b6016b76 | 5518 | { |
c4028958 | 5519 | struct bnx2 *bp = container_of(work, struct bnx2, reset_task); |
b6016b76 | 5520 | |
afdc08b9 MC |
5521 | if (!netif_running(bp->dev)) |
5522 | return; | |
5523 | ||
5524 | bp->in_reset_task = 1; | |
b6016b76 MC |
5525 | bnx2_netif_stop(bp); |
5526 | ||
5527 | bnx2_init_nic(bp); | |
5528 | ||
5529 | atomic_set(&bp->intr_sem, 1); | |
5530 | bnx2_netif_start(bp); | |
afdc08b9 | 5531 | bp->in_reset_task = 0; |
b6016b76 MC |
5532 | } |
5533 | ||
5534 | static void | |
5535 | bnx2_tx_timeout(struct net_device *dev) | |
5536 | { | |
972ec0d4 | 5537 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5538 | |
5539 | /* This allows the netif to be shutdown gracefully before resetting */ | |
5540 | schedule_work(&bp->reset_task); | |
5541 | } | |
5542 | ||
5543 | #ifdef BCM_VLAN | |
5544 | /* Called with rtnl_lock */ | |
5545 | static void | |
5546 | bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp) | |
5547 | { | |
972ec0d4 | 5548 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5549 | |
5550 | bnx2_netif_stop(bp); | |
5551 | ||
5552 | bp->vlgrp = vlgrp; | |
5553 | bnx2_set_rx_mode(dev); | |
5554 | ||
5555 | bnx2_netif_start(bp); | |
5556 | } | |
b6016b76 MC |
5557 | #endif |
5558 | ||
932ff279 | 5559 | /* Called with netif_tx_lock. |
2f8af120 MC |
5560 | * bnx2_tx_int() runs without netif_tx_lock unless it needs to call |
5561 | * netif_wake_queue(). | |
b6016b76 MC |
5562 | */ |
5563 | static int | |
5564 | bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
5565 | { | |
972ec0d4 | 5566 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5567 | dma_addr_t mapping; |
5568 | struct tx_bd *txbd; | |
5569 | struct sw_bd *tx_buf; | |
5570 | u32 len, vlan_tag_flags, last_frag, mss; | |
5571 | u16 prod, ring_prod; | |
5572 | int i; | |
b4b36042 | 5573 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
b6016b76 | 5574 | |
a550c99b MC |
5575 | if (unlikely(bnx2_tx_avail(bp, bnapi) < |
5576 | (skb_shinfo(skb)->nr_frags + 1))) { | |
b6016b76 MC |
5577 | netif_stop_queue(dev); |
5578 | printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n", | |
5579 | dev->name); | |
5580 | ||
5581 | return NETDEV_TX_BUSY; | |
5582 | } | |
5583 | len = skb_headlen(skb); | |
5584 | prod = bp->tx_prod; | |
5585 | ring_prod = TX_RING_IDX(prod); | |
5586 | ||
5587 | vlan_tag_flags = 0; | |
84fa7933 | 5588 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
b6016b76 MC |
5589 | vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; |
5590 | } | |
5591 | ||
5592 | if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) { | |
5593 | vlan_tag_flags |= | |
5594 | (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); | |
5595 | } | |
fde82055 | 5596 | if ((mss = skb_shinfo(skb)->gso_size)) { |
b6016b76 | 5597 | u32 tcp_opt_len, ip_tcp_len; |
eddc9ec5 | 5598 | struct iphdr *iph; |
b6016b76 | 5599 | |
b6016b76 MC |
5600 | vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; |
5601 | ||
4666f87a MC |
5602 | tcp_opt_len = tcp_optlen(skb); |
5603 | ||
5604 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { | |
5605 | u32 tcp_off = skb_transport_offset(skb) - | |
5606 | sizeof(struct ipv6hdr) - ETH_HLEN; | |
ab6a5bb6 | 5607 | |
4666f87a MC |
5608 | vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | |
5609 | TX_BD_FLAGS_SW_FLAGS; | |
5610 | if (likely(tcp_off == 0)) | |
5611 | vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; | |
5612 | else { | |
5613 | tcp_off >>= 3; | |
5614 | vlan_tag_flags |= ((tcp_off & 0x3) << | |
5615 | TX_BD_FLAGS_TCP6_OFF0_SHL) | | |
5616 | ((tcp_off & 0x10) << | |
5617 | TX_BD_FLAGS_TCP6_OFF4_SHL); | |
5618 | mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; | |
5619 | } | |
5620 | } else { | |
5621 | if (skb_header_cloned(skb) && | |
5622 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5623 | dev_kfree_skb(skb); | |
5624 | return NETDEV_TX_OK; | |
5625 | } | |
b6016b76 | 5626 | |
4666f87a MC |
5627 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
5628 | ||
5629 | iph = ip_hdr(skb); | |
5630 | iph->check = 0; | |
5631 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
5632 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5633 | iph->daddr, 0, | |
5634 | IPPROTO_TCP, | |
5635 | 0); | |
5636 | if (tcp_opt_len || (iph->ihl > 5)) { | |
5637 | vlan_tag_flags |= ((iph->ihl - 5) + | |
5638 | (tcp_opt_len >> 2)) << 8; | |
5639 | } | |
b6016b76 | 5640 | } |
4666f87a | 5641 | } else |
b6016b76 | 5642 | mss = 0; |
b6016b76 MC |
5643 | |
5644 | mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
6aa20a22 | 5645 | |
b6016b76 MC |
5646 | tx_buf = &bp->tx_buf_ring[ring_prod]; |
5647 | tx_buf->skb = skb; | |
5648 | pci_unmap_addr_set(tx_buf, mapping, mapping); | |
5649 | ||
5650 | txbd = &bp->tx_desc_ring[ring_prod]; | |
5651 | ||
5652 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
5653 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
5654 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
5655 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; | |
5656 | ||
5657 | last_frag = skb_shinfo(skb)->nr_frags; | |
5658 | ||
5659 | for (i = 0; i < last_frag; i++) { | |
5660 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5661 | ||
5662 | prod = NEXT_TX_BD(prod); | |
5663 | ring_prod = TX_RING_IDX(prod); | |
5664 | txbd = &bp->tx_desc_ring[ring_prod]; | |
5665 | ||
5666 | len = frag->size; | |
5667 | mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset, | |
5668 | len, PCI_DMA_TODEVICE); | |
5669 | pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod], | |
5670 | mapping, mapping); | |
5671 | ||
5672 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
5673 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
5674 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
5675 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; | |
5676 | ||
5677 | } | |
5678 | txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; | |
5679 | ||
5680 | prod = NEXT_TX_BD(prod); | |
5681 | bp->tx_prod_bseq += skb->len; | |
5682 | ||
234754d5 MC |
5683 | REG_WR16(bp, bp->tx_bidx_addr, prod); |
5684 | REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); | |
b6016b76 MC |
5685 | |
5686 | mmiowb(); | |
5687 | ||
5688 | bp->tx_prod = prod; | |
5689 | dev->trans_start = jiffies; | |
5690 | ||
a550c99b | 5691 | if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) { |
e89bbf10 | 5692 | netif_stop_queue(dev); |
a550c99b | 5693 | if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh) |
e89bbf10 | 5694 | netif_wake_queue(dev); |
b6016b76 MC |
5695 | } |
5696 | ||
5697 | return NETDEV_TX_OK; | |
5698 | } | |
5699 | ||
5700 | /* Called with rtnl_lock */ | |
5701 | static int | |
5702 | bnx2_close(struct net_device *dev) | |
5703 | { | |
972ec0d4 | 5704 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5705 | u32 reset_code; |
5706 | ||
afdc08b9 MC |
5707 | /* Calling flush_scheduled_work() may deadlock because |
5708 | * linkwatch_event() may be on the workqueue and it will try to get | |
5709 | * the rtnl_lock which we are holding. | |
5710 | */ | |
5711 | while (bp->in_reset_task) | |
5712 | msleep(1); | |
5713 | ||
bea3348e | 5714 | bnx2_disable_int_sync(bp); |
35efa7c1 | 5715 | bnx2_napi_disable(bp); |
b6016b76 | 5716 | del_timer_sync(&bp->timer); |
dda1e390 | 5717 | if (bp->flags & NO_WOL_FLAG) |
6c4f095e | 5718 | reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; |
dda1e390 | 5719 | else if (bp->wol) |
b6016b76 MC |
5720 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; |
5721 | else | |
5722 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
5723 | bnx2_reset_chip(bp, reset_code); | |
8e6a72c4 | 5724 | bnx2_free_irq(bp); |
b6016b76 MC |
5725 | bnx2_free_skbs(bp); |
5726 | bnx2_free_mem(bp); | |
5727 | bp->link_up = 0; | |
5728 | netif_carrier_off(bp->dev); | |
829ca9a3 | 5729 | bnx2_set_power_state(bp, PCI_D3hot); |
b6016b76 MC |
5730 | return 0; |
5731 | } | |
5732 | ||
5733 | #define GET_NET_STATS64(ctr) \ | |
5734 | (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \ | |
5735 | (unsigned long) (ctr##_lo) | |
5736 | ||
5737 | #define GET_NET_STATS32(ctr) \ | |
5738 | (ctr##_lo) | |
5739 | ||
5740 | #if (BITS_PER_LONG == 64) | |
5741 | #define GET_NET_STATS GET_NET_STATS64 | |
5742 | #else | |
5743 | #define GET_NET_STATS GET_NET_STATS32 | |
5744 | #endif | |
5745 | ||
5746 | static struct net_device_stats * | |
5747 | bnx2_get_stats(struct net_device *dev) | |
5748 | { | |
972ec0d4 | 5749 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5750 | struct statistics_block *stats_blk = bp->stats_blk; |
5751 | struct net_device_stats *net_stats = &bp->net_stats; | |
5752 | ||
5753 | if (bp->stats_blk == NULL) { | |
5754 | return net_stats; | |
5755 | } | |
5756 | net_stats->rx_packets = | |
5757 | GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) + | |
5758 | GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) + | |
5759 | GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts); | |
5760 | ||
5761 | net_stats->tx_packets = | |
5762 | GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) + | |
5763 | GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) + | |
5764 | GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts); | |
5765 | ||
5766 | net_stats->rx_bytes = | |
5767 | GET_NET_STATS(stats_blk->stat_IfHCInOctets); | |
5768 | ||
5769 | net_stats->tx_bytes = | |
5770 | GET_NET_STATS(stats_blk->stat_IfHCOutOctets); | |
5771 | ||
6aa20a22 | 5772 | net_stats->multicast = |
b6016b76 MC |
5773 | GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts); |
5774 | ||
6aa20a22 | 5775 | net_stats->collisions = |
b6016b76 MC |
5776 | (unsigned long) stats_blk->stat_EtherStatsCollisions; |
5777 | ||
6aa20a22 | 5778 | net_stats->rx_length_errors = |
b6016b76 MC |
5779 | (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts + |
5780 | stats_blk->stat_EtherStatsOverrsizePkts); | |
5781 | ||
6aa20a22 | 5782 | net_stats->rx_over_errors = |
b6016b76 MC |
5783 | (unsigned long) stats_blk->stat_IfInMBUFDiscards; |
5784 | ||
6aa20a22 | 5785 | net_stats->rx_frame_errors = |
b6016b76 MC |
5786 | (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors; |
5787 | ||
6aa20a22 | 5788 | net_stats->rx_crc_errors = |
b6016b76 MC |
5789 | (unsigned long) stats_blk->stat_Dot3StatsFCSErrors; |
5790 | ||
5791 | net_stats->rx_errors = net_stats->rx_length_errors + | |
5792 | net_stats->rx_over_errors + net_stats->rx_frame_errors + | |
5793 | net_stats->rx_crc_errors; | |
5794 | ||
5795 | net_stats->tx_aborted_errors = | |
5796 | (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions + | |
5797 | stats_blk->stat_Dot3StatsLateCollisions); | |
5798 | ||
5b0c76ad MC |
5799 | if ((CHIP_NUM(bp) == CHIP_NUM_5706) || |
5800 | (CHIP_ID(bp) == CHIP_ID_5708_A0)) | |
b6016b76 MC |
5801 | net_stats->tx_carrier_errors = 0; |
5802 | else { | |
5803 | net_stats->tx_carrier_errors = | |
5804 | (unsigned long) | |
5805 | stats_blk->stat_Dot3StatsCarrierSenseErrors; | |
5806 | } | |
5807 | ||
5808 | net_stats->tx_errors = | |
6aa20a22 | 5809 | (unsigned long) |
b6016b76 MC |
5810 | stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors |
5811 | + | |
5812 | net_stats->tx_aborted_errors + | |
5813 | net_stats->tx_carrier_errors; | |
5814 | ||
cea94db9 MC |
5815 | net_stats->rx_missed_errors = |
5816 | (unsigned long) (stats_blk->stat_IfInMBUFDiscards + | |
5817 | stats_blk->stat_FwRxDrop); | |
5818 | ||
b6016b76 MC |
5819 | return net_stats; |
5820 | } | |
5821 | ||
5822 | /* All ethtool functions called with rtnl_lock */ | |
5823 | ||
5824 | static int | |
5825 | bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
5826 | { | |
972ec0d4 | 5827 | struct bnx2 *bp = netdev_priv(dev); |
7b6b8347 | 5828 | int support_serdes = 0, support_copper = 0; |
b6016b76 MC |
5829 | |
5830 | cmd->supported = SUPPORTED_Autoneg; | |
7b6b8347 MC |
5831 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) { |
5832 | support_serdes = 1; | |
5833 | support_copper = 1; | |
5834 | } else if (bp->phy_port == PORT_FIBRE) | |
5835 | support_serdes = 1; | |
5836 | else | |
5837 | support_copper = 1; | |
5838 | ||
5839 | if (support_serdes) { | |
b6016b76 MC |
5840 | cmd->supported |= SUPPORTED_1000baseT_Full | |
5841 | SUPPORTED_FIBRE; | |
605a9e20 MC |
5842 | if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) |
5843 | cmd->supported |= SUPPORTED_2500baseX_Full; | |
b6016b76 | 5844 | |
b6016b76 | 5845 | } |
7b6b8347 | 5846 | if (support_copper) { |
b6016b76 MC |
5847 | cmd->supported |= SUPPORTED_10baseT_Half | |
5848 | SUPPORTED_10baseT_Full | | |
5849 | SUPPORTED_100baseT_Half | | |
5850 | SUPPORTED_100baseT_Full | | |
5851 | SUPPORTED_1000baseT_Full | | |
5852 | SUPPORTED_TP; | |
5853 | ||
b6016b76 MC |
5854 | } |
5855 | ||
7b6b8347 MC |
5856 | spin_lock_bh(&bp->phy_lock); |
5857 | cmd->port = bp->phy_port; | |
b6016b76 MC |
5858 | cmd->advertising = bp->advertising; |
5859 | ||
5860 | if (bp->autoneg & AUTONEG_SPEED) { | |
5861 | cmd->autoneg = AUTONEG_ENABLE; | |
5862 | } | |
5863 | else { | |
5864 | cmd->autoneg = AUTONEG_DISABLE; | |
5865 | } | |
5866 | ||
5867 | if (netif_carrier_ok(dev)) { | |
5868 | cmd->speed = bp->line_speed; | |
5869 | cmd->duplex = bp->duplex; | |
5870 | } | |
5871 | else { | |
5872 | cmd->speed = -1; | |
5873 | cmd->duplex = -1; | |
5874 | } | |
7b6b8347 | 5875 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
5876 | |
5877 | cmd->transceiver = XCVR_INTERNAL; | |
5878 | cmd->phy_address = bp->phy_addr; | |
5879 | ||
5880 | return 0; | |
5881 | } | |
6aa20a22 | 5882 | |
b6016b76 MC |
5883 | static int |
5884 | bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
5885 | { | |
972ec0d4 | 5886 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5887 | u8 autoneg = bp->autoneg; |
5888 | u8 req_duplex = bp->req_duplex; | |
5889 | u16 req_line_speed = bp->req_line_speed; | |
5890 | u32 advertising = bp->advertising; | |
7b6b8347 MC |
5891 | int err = -EINVAL; |
5892 | ||
5893 | spin_lock_bh(&bp->phy_lock); | |
5894 | ||
5895 | if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) | |
5896 | goto err_out_unlock; | |
5897 | ||
5898 | if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG)) | |
5899 | goto err_out_unlock; | |
b6016b76 MC |
5900 | |
5901 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
5902 | autoneg |= AUTONEG_SPEED; | |
5903 | ||
6aa20a22 | 5904 | cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; |
b6016b76 MC |
5905 | |
5906 | /* allow advertising 1 speed */ | |
5907 | if ((cmd->advertising == ADVERTISED_10baseT_Half) || | |
5908 | (cmd->advertising == ADVERTISED_10baseT_Full) || | |
5909 | (cmd->advertising == ADVERTISED_100baseT_Half) || | |
5910 | (cmd->advertising == ADVERTISED_100baseT_Full)) { | |
5911 | ||
7b6b8347 MC |
5912 | if (cmd->port == PORT_FIBRE) |
5913 | goto err_out_unlock; | |
b6016b76 MC |
5914 | |
5915 | advertising = cmd->advertising; | |
5916 | ||
27a005b8 | 5917 | } else if (cmd->advertising == ADVERTISED_2500baseX_Full) { |
7b6b8347 MC |
5918 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) || |
5919 | (cmd->port == PORT_TP)) | |
5920 | goto err_out_unlock; | |
5921 | } else if (cmd->advertising == ADVERTISED_1000baseT_Full) | |
b6016b76 | 5922 | advertising = cmd->advertising; |
7b6b8347 MC |
5923 | else if (cmd->advertising == ADVERTISED_1000baseT_Half) |
5924 | goto err_out_unlock; | |
b6016b76 | 5925 | else { |
7b6b8347 | 5926 | if (cmd->port == PORT_FIBRE) |
b6016b76 | 5927 | advertising = ETHTOOL_ALL_FIBRE_SPEED; |
7b6b8347 | 5928 | else |
b6016b76 | 5929 | advertising = ETHTOOL_ALL_COPPER_SPEED; |
b6016b76 MC |
5930 | } |
5931 | advertising |= ADVERTISED_Autoneg; | |
5932 | } | |
5933 | else { | |
7b6b8347 | 5934 | if (cmd->port == PORT_FIBRE) { |
80be4434 MC |
5935 | if ((cmd->speed != SPEED_1000 && |
5936 | cmd->speed != SPEED_2500) || | |
5937 | (cmd->duplex != DUPLEX_FULL)) | |
7b6b8347 | 5938 | goto err_out_unlock; |
80be4434 MC |
5939 | |
5940 | if (cmd->speed == SPEED_2500 && | |
5941 | !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | |
7b6b8347 | 5942 | goto err_out_unlock; |
b6016b76 | 5943 | } |
7b6b8347 MC |
5944 | else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500) |
5945 | goto err_out_unlock; | |
5946 | ||
b6016b76 MC |
5947 | autoneg &= ~AUTONEG_SPEED; |
5948 | req_line_speed = cmd->speed; | |
5949 | req_duplex = cmd->duplex; | |
5950 | advertising = 0; | |
5951 | } | |
5952 | ||
5953 | bp->autoneg = autoneg; | |
5954 | bp->advertising = advertising; | |
5955 | bp->req_line_speed = req_line_speed; | |
5956 | bp->req_duplex = req_duplex; | |
5957 | ||
7b6b8347 | 5958 | err = bnx2_setup_phy(bp, cmd->port); |
b6016b76 | 5959 | |
7b6b8347 | 5960 | err_out_unlock: |
c770a65c | 5961 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 | 5962 | |
7b6b8347 | 5963 | return err; |
b6016b76 MC |
5964 | } |
5965 | ||
5966 | static void | |
5967 | bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
5968 | { | |
972ec0d4 | 5969 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
5970 | |
5971 | strcpy(info->driver, DRV_MODULE_NAME); | |
5972 | strcpy(info->version, DRV_MODULE_VERSION); | |
5973 | strcpy(info->bus_info, pci_name(bp->pdev)); | |
58fc2ea4 | 5974 | strcpy(info->fw_version, bp->fw_version); |
b6016b76 MC |
5975 | } |
5976 | ||
244ac4f4 MC |
5977 | #define BNX2_REGDUMP_LEN (32 * 1024) |
5978 | ||
5979 | static int | |
5980 | bnx2_get_regs_len(struct net_device *dev) | |
5981 | { | |
5982 | return BNX2_REGDUMP_LEN; | |
5983 | } | |
5984 | ||
5985 | static void | |
5986 | bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) | |
5987 | { | |
5988 | u32 *p = _p, i, offset; | |
5989 | u8 *orig_p = _p; | |
5990 | struct bnx2 *bp = netdev_priv(dev); | |
5991 | u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c, | |
5992 | 0x0800, 0x0880, 0x0c00, 0x0c10, | |
5993 | 0x0c30, 0x0d08, 0x1000, 0x101c, | |
5994 | 0x1040, 0x1048, 0x1080, 0x10a4, | |
5995 | 0x1400, 0x1490, 0x1498, 0x14f0, | |
5996 | 0x1500, 0x155c, 0x1580, 0x15dc, | |
5997 | 0x1600, 0x1658, 0x1680, 0x16d8, | |
5998 | 0x1800, 0x1820, 0x1840, 0x1854, | |
5999 | 0x1880, 0x1894, 0x1900, 0x1984, | |
6000 | 0x1c00, 0x1c0c, 0x1c40, 0x1c54, | |
6001 | 0x1c80, 0x1c94, 0x1d00, 0x1d84, | |
6002 | 0x2000, 0x2030, 0x23c0, 0x2400, | |
6003 | 0x2800, 0x2820, 0x2830, 0x2850, | |
6004 | 0x2b40, 0x2c10, 0x2fc0, 0x3058, | |
6005 | 0x3c00, 0x3c94, 0x4000, 0x4010, | |
6006 | 0x4080, 0x4090, 0x43c0, 0x4458, | |
6007 | 0x4c00, 0x4c18, 0x4c40, 0x4c54, | |
6008 | 0x4fc0, 0x5010, 0x53c0, 0x5444, | |
6009 | 0x5c00, 0x5c18, 0x5c80, 0x5c90, | |
6010 | 0x5fc0, 0x6000, 0x6400, 0x6428, | |
6011 | 0x6800, 0x6848, 0x684c, 0x6860, | |
6012 | 0x6888, 0x6910, 0x8000 }; | |
6013 | ||
6014 | regs->version = 0; | |
6015 | ||
6016 | memset(p, 0, BNX2_REGDUMP_LEN); | |
6017 | ||
6018 | if (!netif_running(bp->dev)) | |
6019 | return; | |
6020 | ||
6021 | i = 0; | |
6022 | offset = reg_boundaries[0]; | |
6023 | p += offset; | |
6024 | while (offset < BNX2_REGDUMP_LEN) { | |
6025 | *p++ = REG_RD(bp, offset); | |
6026 | offset += 4; | |
6027 | if (offset == reg_boundaries[i + 1]) { | |
6028 | offset = reg_boundaries[i + 2]; | |
6029 | p = (u32 *) (orig_p + offset); | |
6030 | i += 2; | |
6031 | } | |
6032 | } | |
6033 | } | |
6034 | ||
b6016b76 MC |
6035 | static void |
6036 | bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
6037 | { | |
972ec0d4 | 6038 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6039 | |
6040 | if (bp->flags & NO_WOL_FLAG) { | |
6041 | wol->supported = 0; | |
6042 | wol->wolopts = 0; | |
6043 | } | |
6044 | else { | |
6045 | wol->supported = WAKE_MAGIC; | |
6046 | if (bp->wol) | |
6047 | wol->wolopts = WAKE_MAGIC; | |
6048 | else | |
6049 | wol->wolopts = 0; | |
6050 | } | |
6051 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
6052 | } | |
6053 | ||
6054 | static int | |
6055 | bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
6056 | { | |
972ec0d4 | 6057 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6058 | |
6059 | if (wol->wolopts & ~WAKE_MAGIC) | |
6060 | return -EINVAL; | |
6061 | ||
6062 | if (wol->wolopts & WAKE_MAGIC) { | |
6063 | if (bp->flags & NO_WOL_FLAG) | |
6064 | return -EINVAL; | |
6065 | ||
6066 | bp->wol = 1; | |
6067 | } | |
6068 | else { | |
6069 | bp->wol = 0; | |
6070 | } | |
6071 | return 0; | |
6072 | } | |
6073 | ||
6074 | static int | |
6075 | bnx2_nway_reset(struct net_device *dev) | |
6076 | { | |
972ec0d4 | 6077 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6078 | u32 bmcr; |
6079 | ||
6080 | if (!(bp->autoneg & AUTONEG_SPEED)) { | |
6081 | return -EINVAL; | |
6082 | } | |
6083 | ||
c770a65c | 6084 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 6085 | |
7b6b8347 MC |
6086 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) { |
6087 | int rc; | |
6088 | ||
6089 | rc = bnx2_setup_remote_phy(bp, bp->phy_port); | |
6090 | spin_unlock_bh(&bp->phy_lock); | |
6091 | return rc; | |
6092 | } | |
6093 | ||
b6016b76 MC |
6094 | /* Force a link down visible on the other side */ |
6095 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
ca58c3af | 6096 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
c770a65c | 6097 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6098 | |
6099 | msleep(20); | |
6100 | ||
c770a65c | 6101 | spin_lock_bh(&bp->phy_lock); |
f8dd064e MC |
6102 | |
6103 | bp->current_interval = SERDES_AN_TIMEOUT; | |
6104 | bp->serdes_an_pending = 1; | |
6105 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
b6016b76 MC |
6106 | } |
6107 | ||
ca58c3af | 6108 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 6109 | bmcr &= ~BMCR_LOOPBACK; |
ca58c3af | 6110 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); |
b6016b76 | 6111 | |
c770a65c | 6112 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6113 | |
6114 | return 0; | |
6115 | } | |
6116 | ||
6117 | static int | |
6118 | bnx2_get_eeprom_len(struct net_device *dev) | |
6119 | { | |
972ec0d4 | 6120 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6121 | |
1122db71 | 6122 | if (bp->flash_info == NULL) |
b6016b76 MC |
6123 | return 0; |
6124 | ||
1122db71 | 6125 | return (int) bp->flash_size; |
b6016b76 MC |
6126 | } |
6127 | ||
6128 | static int | |
6129 | bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
6130 | u8 *eebuf) | |
6131 | { | |
972ec0d4 | 6132 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6133 | int rc; |
6134 | ||
1064e944 | 6135 | /* parameters already validated in ethtool_get_eeprom */ |
b6016b76 MC |
6136 | |
6137 | rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | |
6138 | ||
6139 | return rc; | |
6140 | } | |
6141 | ||
6142 | static int | |
6143 | bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
6144 | u8 *eebuf) | |
6145 | { | |
972ec0d4 | 6146 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6147 | int rc; |
6148 | ||
1064e944 | 6149 | /* parameters already validated in ethtool_set_eeprom */ |
b6016b76 MC |
6150 | |
6151 | rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
6152 | ||
6153 | return rc; | |
6154 | } | |
6155 | ||
6156 | static int | |
6157 | bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
6158 | { | |
972ec0d4 | 6159 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6160 | |
6161 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
6162 | ||
6163 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
6164 | coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; | |
6165 | coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; | |
6166 | coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; | |
6167 | ||
6168 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
6169 | coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; | |
6170 | coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; | |
6171 | coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; | |
6172 | ||
6173 | coal->stats_block_coalesce_usecs = bp->stats_ticks; | |
6174 | ||
6175 | return 0; | |
6176 | } | |
6177 | ||
6178 | static int | |
6179 | bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
6180 | { | |
972ec0d4 | 6181 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6182 | |
6183 | bp->rx_ticks = (u16) coal->rx_coalesce_usecs; | |
6184 | if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; | |
6185 | ||
6aa20a22 | 6186 | bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; |
b6016b76 MC |
6187 | if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; |
6188 | ||
6189 | bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; | |
6190 | if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; | |
6191 | ||
6192 | bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; | |
6193 | if (bp->rx_quick_cons_trip_int > 0xff) | |
6194 | bp->rx_quick_cons_trip_int = 0xff; | |
6195 | ||
6196 | bp->tx_ticks = (u16) coal->tx_coalesce_usecs; | |
6197 | if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; | |
6198 | ||
6199 | bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; | |
6200 | if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; | |
6201 | ||
6202 | bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; | |
6203 | if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; | |
6204 | ||
6205 | bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; | |
6206 | if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = | |
6207 | 0xff; | |
6208 | ||
6209 | bp->stats_ticks = coal->stats_block_coalesce_usecs; | |
02537b06 MC |
6210 | if (CHIP_NUM(bp) == CHIP_NUM_5708) { |
6211 | if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) | |
6212 | bp->stats_ticks = USEC_PER_SEC; | |
6213 | } | |
7ea6920e MC |
6214 | if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) |
6215 | bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
6216 | bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
b6016b76 MC |
6217 | |
6218 | if (netif_running(bp->dev)) { | |
6219 | bnx2_netif_stop(bp); | |
6220 | bnx2_init_nic(bp); | |
6221 | bnx2_netif_start(bp); | |
6222 | } | |
6223 | ||
6224 | return 0; | |
6225 | } | |
6226 | ||
6227 | static void | |
6228 | bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
6229 | { | |
972ec0d4 | 6230 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6231 | |
13daffa2 | 6232 | ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT; |
b6016b76 | 6233 | ering->rx_mini_max_pending = 0; |
47bf4246 | 6234 | ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT; |
b6016b76 MC |
6235 | |
6236 | ering->rx_pending = bp->rx_ring_size; | |
6237 | ering->rx_mini_pending = 0; | |
47bf4246 | 6238 | ering->rx_jumbo_pending = bp->rx_pg_ring_size; |
b6016b76 MC |
6239 | |
6240 | ering->tx_max_pending = MAX_TX_DESC_CNT; | |
6241 | ering->tx_pending = bp->tx_ring_size; | |
6242 | } | |
6243 | ||
6244 | static int | |
5d5d0015 | 6245 | bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx) |
b6016b76 | 6246 | { |
13daffa2 MC |
6247 | if (netif_running(bp->dev)) { |
6248 | bnx2_netif_stop(bp); | |
6249 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); | |
6250 | bnx2_free_skbs(bp); | |
6251 | bnx2_free_mem(bp); | |
6252 | } | |
6253 | ||
5d5d0015 MC |
6254 | bnx2_set_rx_ring_size(bp, rx); |
6255 | bp->tx_ring_size = tx; | |
b6016b76 MC |
6256 | |
6257 | if (netif_running(bp->dev)) { | |
13daffa2 MC |
6258 | int rc; |
6259 | ||
6260 | rc = bnx2_alloc_mem(bp); | |
6261 | if (rc) | |
6262 | return rc; | |
b6016b76 MC |
6263 | bnx2_init_nic(bp); |
6264 | bnx2_netif_start(bp); | |
6265 | } | |
b6016b76 MC |
6266 | return 0; |
6267 | } | |
6268 | ||
5d5d0015 MC |
6269 | static int |
6270 | bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
6271 | { | |
6272 | struct bnx2 *bp = netdev_priv(dev); | |
6273 | int rc; | |
6274 | ||
6275 | if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) || | |
6276 | (ering->tx_pending > MAX_TX_DESC_CNT) || | |
6277 | (ering->tx_pending <= MAX_SKB_FRAGS)) { | |
6278 | ||
6279 | return -EINVAL; | |
6280 | } | |
6281 | rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending); | |
6282 | return rc; | |
6283 | } | |
6284 | ||
b6016b76 MC |
6285 | static void |
6286 | bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
6287 | { | |
972ec0d4 | 6288 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6289 | |
6290 | epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); | |
6291 | epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); | |
6292 | epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); | |
6293 | } | |
6294 | ||
6295 | static int | |
6296 | bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
6297 | { | |
972ec0d4 | 6298 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6299 | |
6300 | bp->req_flow_ctrl = 0; | |
6301 | if (epause->rx_pause) | |
6302 | bp->req_flow_ctrl |= FLOW_CTRL_RX; | |
6303 | if (epause->tx_pause) | |
6304 | bp->req_flow_ctrl |= FLOW_CTRL_TX; | |
6305 | ||
6306 | if (epause->autoneg) { | |
6307 | bp->autoneg |= AUTONEG_FLOW_CTRL; | |
6308 | } | |
6309 | else { | |
6310 | bp->autoneg &= ~AUTONEG_FLOW_CTRL; | |
6311 | } | |
6312 | ||
c770a65c | 6313 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 6314 | |
0d8a6571 | 6315 | bnx2_setup_phy(bp, bp->phy_port); |
b6016b76 | 6316 | |
c770a65c | 6317 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6318 | |
6319 | return 0; | |
6320 | } | |
6321 | ||
6322 | static u32 | |
6323 | bnx2_get_rx_csum(struct net_device *dev) | |
6324 | { | |
972ec0d4 | 6325 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6326 | |
6327 | return bp->rx_csum; | |
6328 | } | |
6329 | ||
6330 | static int | |
6331 | bnx2_set_rx_csum(struct net_device *dev, u32 data) | |
6332 | { | |
972ec0d4 | 6333 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6334 | |
6335 | bp->rx_csum = data; | |
6336 | return 0; | |
6337 | } | |
6338 | ||
b11d6213 MC |
6339 | static int |
6340 | bnx2_set_tso(struct net_device *dev, u32 data) | |
6341 | { | |
4666f87a MC |
6342 | struct bnx2 *bp = netdev_priv(dev); |
6343 | ||
6344 | if (data) { | |
b11d6213 | 6345 | dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; |
4666f87a MC |
6346 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
6347 | dev->features |= NETIF_F_TSO6; | |
6348 | } else | |
6349 | dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 | | |
6350 | NETIF_F_TSO_ECN); | |
b11d6213 MC |
6351 | return 0; |
6352 | } | |
6353 | ||
cea94db9 | 6354 | #define BNX2_NUM_STATS 46 |
b6016b76 | 6355 | |
14ab9b86 | 6356 | static struct { |
b6016b76 MC |
6357 | char string[ETH_GSTRING_LEN]; |
6358 | } bnx2_stats_str_arr[BNX2_NUM_STATS] = { | |
6359 | { "rx_bytes" }, | |
6360 | { "rx_error_bytes" }, | |
6361 | { "tx_bytes" }, | |
6362 | { "tx_error_bytes" }, | |
6363 | { "rx_ucast_packets" }, | |
6364 | { "rx_mcast_packets" }, | |
6365 | { "rx_bcast_packets" }, | |
6366 | { "tx_ucast_packets" }, | |
6367 | { "tx_mcast_packets" }, | |
6368 | { "tx_bcast_packets" }, | |
6369 | { "tx_mac_errors" }, | |
6370 | { "tx_carrier_errors" }, | |
6371 | { "rx_crc_errors" }, | |
6372 | { "rx_align_errors" }, | |
6373 | { "tx_single_collisions" }, | |
6374 | { "tx_multi_collisions" }, | |
6375 | { "tx_deferred" }, | |
6376 | { "tx_excess_collisions" }, | |
6377 | { "tx_late_collisions" }, | |
6378 | { "tx_total_collisions" }, | |
6379 | { "rx_fragments" }, | |
6380 | { "rx_jabbers" }, | |
6381 | { "rx_undersize_packets" }, | |
6382 | { "rx_oversize_packets" }, | |
6383 | { "rx_64_byte_packets" }, | |
6384 | { "rx_65_to_127_byte_packets" }, | |
6385 | { "rx_128_to_255_byte_packets" }, | |
6386 | { "rx_256_to_511_byte_packets" }, | |
6387 | { "rx_512_to_1023_byte_packets" }, | |
6388 | { "rx_1024_to_1522_byte_packets" }, | |
6389 | { "rx_1523_to_9022_byte_packets" }, | |
6390 | { "tx_64_byte_packets" }, | |
6391 | { "tx_65_to_127_byte_packets" }, | |
6392 | { "tx_128_to_255_byte_packets" }, | |
6393 | { "tx_256_to_511_byte_packets" }, | |
6394 | { "tx_512_to_1023_byte_packets" }, | |
6395 | { "tx_1024_to_1522_byte_packets" }, | |
6396 | { "tx_1523_to_9022_byte_packets" }, | |
6397 | { "rx_xon_frames" }, | |
6398 | { "rx_xoff_frames" }, | |
6399 | { "tx_xon_frames" }, | |
6400 | { "tx_xoff_frames" }, | |
6401 | { "rx_mac_ctrl_frames" }, | |
6402 | { "rx_filtered_packets" }, | |
6403 | { "rx_discards" }, | |
cea94db9 | 6404 | { "rx_fw_discards" }, |
b6016b76 MC |
6405 | }; |
6406 | ||
6407 | #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) | |
6408 | ||
f71e1309 | 6409 | static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
6410 | STATS_OFFSET32(stat_IfHCInOctets_hi), |
6411 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), | |
6412 | STATS_OFFSET32(stat_IfHCOutOctets_hi), | |
6413 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), | |
6414 | STATS_OFFSET32(stat_IfHCInUcastPkts_hi), | |
6415 | STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), | |
6416 | STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), | |
6417 | STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), | |
6418 | STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), | |
6419 | STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), | |
6420 | STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), | |
6aa20a22 JG |
6421 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), |
6422 | STATS_OFFSET32(stat_Dot3StatsFCSErrors), | |
6423 | STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), | |
6424 | STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), | |
6425 | STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), | |
6426 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), | |
6427 | STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), | |
6428 | STATS_OFFSET32(stat_Dot3StatsLateCollisions), | |
6429 | STATS_OFFSET32(stat_EtherStatsCollisions), | |
6430 | STATS_OFFSET32(stat_EtherStatsFragments), | |
6431 | STATS_OFFSET32(stat_EtherStatsJabbers), | |
6432 | STATS_OFFSET32(stat_EtherStatsUndersizePkts), | |
6433 | STATS_OFFSET32(stat_EtherStatsOverrsizePkts), | |
6434 | STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), | |
6435 | STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), | |
6436 | STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), | |
6437 | STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), | |
6438 | STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), | |
6439 | STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), | |
6440 | STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), | |
6441 | STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), | |
6442 | STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), | |
6443 | STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), | |
6444 | STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), | |
6445 | STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), | |
6446 | STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), | |
6447 | STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), | |
6448 | STATS_OFFSET32(stat_XonPauseFramesReceived), | |
6449 | STATS_OFFSET32(stat_XoffPauseFramesReceived), | |
6450 | STATS_OFFSET32(stat_OutXonSent), | |
6451 | STATS_OFFSET32(stat_OutXoffSent), | |
6452 | STATS_OFFSET32(stat_MacControlFramesReceived), | |
6453 | STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), | |
6454 | STATS_OFFSET32(stat_IfInMBUFDiscards), | |
cea94db9 | 6455 | STATS_OFFSET32(stat_FwRxDrop), |
b6016b76 MC |
6456 | }; |
6457 | ||
6458 | /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are | |
6459 | * skipped because of errata. | |
6aa20a22 | 6460 | */ |
14ab9b86 | 6461 | static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
6462 | 8,0,8,8,8,8,8,8,8,8, |
6463 | 4,0,4,4,4,4,4,4,4,4, | |
6464 | 4,4,4,4,4,4,4,4,4,4, | |
6465 | 4,4,4,4,4,4,4,4,4,4, | |
cea94db9 | 6466 | 4,4,4,4,4,4, |
b6016b76 MC |
6467 | }; |
6468 | ||
5b0c76ad MC |
6469 | static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { |
6470 | 8,0,8,8,8,8,8,8,8,8, | |
6471 | 4,4,4,4,4,4,4,4,4,4, | |
6472 | 4,4,4,4,4,4,4,4,4,4, | |
6473 | 4,4,4,4,4,4,4,4,4,4, | |
cea94db9 | 6474 | 4,4,4,4,4,4, |
5b0c76ad MC |
6475 | }; |
6476 | ||
b6016b76 MC |
6477 | #define BNX2_NUM_TESTS 6 |
6478 | ||
14ab9b86 | 6479 | static struct { |
b6016b76 MC |
6480 | char string[ETH_GSTRING_LEN]; |
6481 | } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { | |
6482 | { "register_test (offline)" }, | |
6483 | { "memory_test (offline)" }, | |
6484 | { "loopback_test (offline)" }, | |
6485 | { "nvram_test (online)" }, | |
6486 | { "interrupt_test (online)" }, | |
6487 | { "link_test (online)" }, | |
6488 | }; | |
6489 | ||
6490 | static int | |
b9f2c044 | 6491 | bnx2_get_sset_count(struct net_device *dev, int sset) |
b6016b76 | 6492 | { |
b9f2c044 JG |
6493 | switch (sset) { |
6494 | case ETH_SS_TEST: | |
6495 | return BNX2_NUM_TESTS; | |
6496 | case ETH_SS_STATS: | |
6497 | return BNX2_NUM_STATS; | |
6498 | default: | |
6499 | return -EOPNOTSUPP; | |
6500 | } | |
b6016b76 MC |
6501 | } |
6502 | ||
6503 | static void | |
6504 | bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) | |
6505 | { | |
972ec0d4 | 6506 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6507 | |
6508 | memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); | |
6509 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
80be4434 MC |
6510 | int i; |
6511 | ||
b6016b76 MC |
6512 | bnx2_netif_stop(bp); |
6513 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); | |
6514 | bnx2_free_skbs(bp); | |
6515 | ||
6516 | if (bnx2_test_registers(bp) != 0) { | |
6517 | buf[0] = 1; | |
6518 | etest->flags |= ETH_TEST_FL_FAILED; | |
6519 | } | |
6520 | if (bnx2_test_memory(bp) != 0) { | |
6521 | buf[1] = 1; | |
6522 | etest->flags |= ETH_TEST_FL_FAILED; | |
6523 | } | |
bc5a0690 | 6524 | if ((buf[2] = bnx2_test_loopback(bp)) != 0) |
b6016b76 | 6525 | etest->flags |= ETH_TEST_FL_FAILED; |
b6016b76 MC |
6526 | |
6527 | if (!netif_running(bp->dev)) { | |
6528 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); | |
6529 | } | |
6530 | else { | |
6531 | bnx2_init_nic(bp); | |
6532 | bnx2_netif_start(bp); | |
6533 | } | |
6534 | ||
6535 | /* wait for link up */ | |
80be4434 MC |
6536 | for (i = 0; i < 7; i++) { |
6537 | if (bp->link_up) | |
6538 | break; | |
6539 | msleep_interruptible(1000); | |
6540 | } | |
b6016b76 MC |
6541 | } |
6542 | ||
6543 | if (bnx2_test_nvram(bp) != 0) { | |
6544 | buf[3] = 1; | |
6545 | etest->flags |= ETH_TEST_FL_FAILED; | |
6546 | } | |
6547 | if (bnx2_test_intr(bp) != 0) { | |
6548 | buf[4] = 1; | |
6549 | etest->flags |= ETH_TEST_FL_FAILED; | |
6550 | } | |
6551 | ||
6552 | if (bnx2_test_link(bp) != 0) { | |
6553 | buf[5] = 1; | |
6554 | etest->flags |= ETH_TEST_FL_FAILED; | |
6555 | ||
6556 | } | |
6557 | } | |
6558 | ||
6559 | static void | |
6560 | bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
6561 | { | |
6562 | switch (stringset) { | |
6563 | case ETH_SS_STATS: | |
6564 | memcpy(buf, bnx2_stats_str_arr, | |
6565 | sizeof(bnx2_stats_str_arr)); | |
6566 | break; | |
6567 | case ETH_SS_TEST: | |
6568 | memcpy(buf, bnx2_tests_str_arr, | |
6569 | sizeof(bnx2_tests_str_arr)); | |
6570 | break; | |
6571 | } | |
6572 | } | |
6573 | ||
b6016b76 MC |
6574 | static void |
6575 | bnx2_get_ethtool_stats(struct net_device *dev, | |
6576 | struct ethtool_stats *stats, u64 *buf) | |
6577 | { | |
972ec0d4 | 6578 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6579 | int i; |
6580 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
14ab9b86 | 6581 | u8 *stats_len_arr = NULL; |
b6016b76 MC |
6582 | |
6583 | if (hw_stats == NULL) { | |
6584 | memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); | |
6585 | return; | |
6586 | } | |
6587 | ||
5b0c76ad MC |
6588 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || |
6589 | (CHIP_ID(bp) == CHIP_ID_5706_A1) || | |
6590 | (CHIP_ID(bp) == CHIP_ID_5706_A2) || | |
6591 | (CHIP_ID(bp) == CHIP_ID_5708_A0)) | |
b6016b76 | 6592 | stats_len_arr = bnx2_5706_stats_len_arr; |
5b0c76ad MC |
6593 | else |
6594 | stats_len_arr = bnx2_5708_stats_len_arr; | |
b6016b76 MC |
6595 | |
6596 | for (i = 0; i < BNX2_NUM_STATS; i++) { | |
6597 | if (stats_len_arr[i] == 0) { | |
6598 | /* skip this counter */ | |
6599 | buf[i] = 0; | |
6600 | continue; | |
6601 | } | |
6602 | if (stats_len_arr[i] == 4) { | |
6603 | /* 4-byte counter */ | |
6604 | buf[i] = (u64) | |
6605 | *(hw_stats + bnx2_stats_offset_arr[i]); | |
6606 | continue; | |
6607 | } | |
6608 | /* 8-byte counter */ | |
6609 | buf[i] = (((u64) *(hw_stats + | |
6610 | bnx2_stats_offset_arr[i])) << 32) + | |
6611 | *(hw_stats + bnx2_stats_offset_arr[i] + 1); | |
6612 | } | |
6613 | } | |
6614 | ||
6615 | static int | |
6616 | bnx2_phys_id(struct net_device *dev, u32 data) | |
6617 | { | |
972ec0d4 | 6618 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6619 | int i; |
6620 | u32 save; | |
6621 | ||
6622 | if (data == 0) | |
6623 | data = 2; | |
6624 | ||
6625 | save = REG_RD(bp, BNX2_MISC_CFG); | |
6626 | REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); | |
6627 | ||
6628 | for (i = 0; i < (data * 2); i++) { | |
6629 | if ((i % 2) == 0) { | |
6630 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); | |
6631 | } | |
6632 | else { | |
6633 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | | |
6634 | BNX2_EMAC_LED_1000MB_OVERRIDE | | |
6635 | BNX2_EMAC_LED_100MB_OVERRIDE | | |
6636 | BNX2_EMAC_LED_10MB_OVERRIDE | | |
6637 | BNX2_EMAC_LED_TRAFFIC_OVERRIDE | | |
6638 | BNX2_EMAC_LED_TRAFFIC); | |
6639 | } | |
6640 | msleep_interruptible(500); | |
6641 | if (signal_pending(current)) | |
6642 | break; | |
6643 | } | |
6644 | REG_WR(bp, BNX2_EMAC_LED, 0); | |
6645 | REG_WR(bp, BNX2_MISC_CFG, save); | |
6646 | return 0; | |
6647 | } | |
6648 | ||
4666f87a MC |
6649 | static int |
6650 | bnx2_set_tx_csum(struct net_device *dev, u32 data) | |
6651 | { | |
6652 | struct bnx2 *bp = netdev_priv(dev); | |
6653 | ||
6654 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | |
6460d948 | 6655 | return (ethtool_op_set_tx_ipv6_csum(dev, data)); |
4666f87a MC |
6656 | else |
6657 | return (ethtool_op_set_tx_csum(dev, data)); | |
6658 | } | |
6659 | ||
7282d491 | 6660 | static const struct ethtool_ops bnx2_ethtool_ops = { |
b6016b76 MC |
6661 | .get_settings = bnx2_get_settings, |
6662 | .set_settings = bnx2_set_settings, | |
6663 | .get_drvinfo = bnx2_get_drvinfo, | |
244ac4f4 MC |
6664 | .get_regs_len = bnx2_get_regs_len, |
6665 | .get_regs = bnx2_get_regs, | |
b6016b76 MC |
6666 | .get_wol = bnx2_get_wol, |
6667 | .set_wol = bnx2_set_wol, | |
6668 | .nway_reset = bnx2_nway_reset, | |
6669 | .get_link = ethtool_op_get_link, | |
6670 | .get_eeprom_len = bnx2_get_eeprom_len, | |
6671 | .get_eeprom = bnx2_get_eeprom, | |
6672 | .set_eeprom = bnx2_set_eeprom, | |
6673 | .get_coalesce = bnx2_get_coalesce, | |
6674 | .set_coalesce = bnx2_set_coalesce, | |
6675 | .get_ringparam = bnx2_get_ringparam, | |
6676 | .set_ringparam = bnx2_set_ringparam, | |
6677 | .get_pauseparam = bnx2_get_pauseparam, | |
6678 | .set_pauseparam = bnx2_set_pauseparam, | |
6679 | .get_rx_csum = bnx2_get_rx_csum, | |
6680 | .set_rx_csum = bnx2_set_rx_csum, | |
4666f87a | 6681 | .set_tx_csum = bnx2_set_tx_csum, |
b6016b76 | 6682 | .set_sg = ethtool_op_set_sg, |
b11d6213 | 6683 | .set_tso = bnx2_set_tso, |
b6016b76 MC |
6684 | .self_test = bnx2_self_test, |
6685 | .get_strings = bnx2_get_strings, | |
6686 | .phys_id = bnx2_phys_id, | |
b6016b76 | 6687 | .get_ethtool_stats = bnx2_get_ethtool_stats, |
b9f2c044 | 6688 | .get_sset_count = bnx2_get_sset_count, |
b6016b76 MC |
6689 | }; |
6690 | ||
6691 | /* Called with rtnl_lock */ | |
6692 | static int | |
6693 | bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
6694 | { | |
14ab9b86 | 6695 | struct mii_ioctl_data *data = if_mii(ifr); |
972ec0d4 | 6696 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6697 | int err; |
6698 | ||
6699 | switch(cmd) { | |
6700 | case SIOCGMIIPHY: | |
6701 | data->phy_id = bp->phy_addr; | |
6702 | ||
6703 | /* fallthru */ | |
6704 | case SIOCGMIIREG: { | |
6705 | u32 mii_regval; | |
6706 | ||
7b6b8347 MC |
6707 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
6708 | return -EOPNOTSUPP; | |
6709 | ||
dad3e452 MC |
6710 | if (!netif_running(dev)) |
6711 | return -EAGAIN; | |
6712 | ||
c770a65c | 6713 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 6714 | err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); |
c770a65c | 6715 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6716 | |
6717 | data->val_out = mii_regval; | |
6718 | ||
6719 | return err; | |
6720 | } | |
6721 | ||
6722 | case SIOCSMIIREG: | |
6723 | if (!capable(CAP_NET_ADMIN)) | |
6724 | return -EPERM; | |
6725 | ||
7b6b8347 MC |
6726 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) |
6727 | return -EOPNOTSUPP; | |
6728 | ||
dad3e452 MC |
6729 | if (!netif_running(dev)) |
6730 | return -EAGAIN; | |
6731 | ||
c770a65c | 6732 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 6733 | err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); |
c770a65c | 6734 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6735 | |
6736 | return err; | |
6737 | ||
6738 | default: | |
6739 | /* do nothing */ | |
6740 | break; | |
6741 | } | |
6742 | return -EOPNOTSUPP; | |
6743 | } | |
6744 | ||
6745 | /* Called with rtnl_lock */ | |
6746 | static int | |
6747 | bnx2_change_mac_addr(struct net_device *dev, void *p) | |
6748 | { | |
6749 | struct sockaddr *addr = p; | |
972ec0d4 | 6750 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6751 | |
73eef4cd MC |
6752 | if (!is_valid_ether_addr(addr->sa_data)) |
6753 | return -EINVAL; | |
6754 | ||
b6016b76 MC |
6755 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
6756 | if (netif_running(dev)) | |
6757 | bnx2_set_mac_addr(bp); | |
6758 | ||
6759 | return 0; | |
6760 | } | |
6761 | ||
6762 | /* Called with rtnl_lock */ | |
6763 | static int | |
6764 | bnx2_change_mtu(struct net_device *dev, int new_mtu) | |
6765 | { | |
972ec0d4 | 6766 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6767 | |
6768 | if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || | |
6769 | ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) | |
6770 | return -EINVAL; | |
6771 | ||
6772 | dev->mtu = new_mtu; | |
5d5d0015 | 6773 | return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size)); |
b6016b76 MC |
6774 | } |
6775 | ||
6776 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | |
6777 | static void | |
6778 | poll_bnx2(struct net_device *dev) | |
6779 | { | |
972ec0d4 | 6780 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6781 | |
6782 | disable_irq(bp->pdev->irq); | |
7d12e780 | 6783 | bnx2_interrupt(bp->pdev->irq, dev); |
b6016b76 MC |
6784 | enable_irq(bp->pdev->irq); |
6785 | } | |
6786 | #endif | |
6787 | ||
253c8b75 MC |
6788 | static void __devinit |
6789 | bnx2_get_5709_media(struct bnx2 *bp) | |
6790 | { | |
6791 | u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); | |
6792 | u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; | |
6793 | u32 strap; | |
6794 | ||
6795 | if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) | |
6796 | return; | |
6797 | else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { | |
6798 | bp->phy_flags |= PHY_SERDES_FLAG; | |
6799 | return; | |
6800 | } | |
6801 | ||
6802 | if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) | |
6803 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; | |
6804 | else | |
6805 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; | |
6806 | ||
6807 | if (PCI_FUNC(bp->pdev->devfn) == 0) { | |
6808 | switch (strap) { | |
6809 | case 0x4: | |
6810 | case 0x5: | |
6811 | case 0x6: | |
6812 | bp->phy_flags |= PHY_SERDES_FLAG; | |
6813 | return; | |
6814 | } | |
6815 | } else { | |
6816 | switch (strap) { | |
6817 | case 0x1: | |
6818 | case 0x2: | |
6819 | case 0x4: | |
6820 | bp->phy_flags |= PHY_SERDES_FLAG; | |
6821 | return; | |
6822 | } | |
6823 | } | |
6824 | } | |
6825 | ||
883e5151 MC |
6826 | static void __devinit |
6827 | bnx2_get_pci_speed(struct bnx2 *bp) | |
6828 | { | |
6829 | u32 reg; | |
6830 | ||
6831 | reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); | |
6832 | if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { | |
6833 | u32 clkreg; | |
6834 | ||
6835 | bp->flags |= PCIX_FLAG; | |
6836 | ||
6837 | clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); | |
6838 | ||
6839 | clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; | |
6840 | switch (clkreg) { | |
6841 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: | |
6842 | bp->bus_speed_mhz = 133; | |
6843 | break; | |
6844 | ||
6845 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: | |
6846 | bp->bus_speed_mhz = 100; | |
6847 | break; | |
6848 | ||
6849 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: | |
6850 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: | |
6851 | bp->bus_speed_mhz = 66; | |
6852 | break; | |
6853 | ||
6854 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: | |
6855 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: | |
6856 | bp->bus_speed_mhz = 50; | |
6857 | break; | |
6858 | ||
6859 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: | |
6860 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: | |
6861 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: | |
6862 | bp->bus_speed_mhz = 33; | |
6863 | break; | |
6864 | } | |
6865 | } | |
6866 | else { | |
6867 | if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) | |
6868 | bp->bus_speed_mhz = 66; | |
6869 | else | |
6870 | bp->bus_speed_mhz = 33; | |
6871 | } | |
6872 | ||
6873 | if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) | |
6874 | bp->flags |= PCI_32BIT_FLAG; | |
6875 | ||
6876 | } | |
6877 | ||
b6016b76 MC |
6878 | static int __devinit |
6879 | bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |
6880 | { | |
6881 | struct bnx2 *bp; | |
6882 | unsigned long mem_len; | |
58fc2ea4 | 6883 | int rc, i, j; |
b6016b76 | 6884 | u32 reg; |
40453c83 | 6885 | u64 dma_mask, persist_dma_mask; |
b6016b76 | 6886 | |
b6016b76 | 6887 | SET_NETDEV_DEV(dev, &pdev->dev); |
972ec0d4 | 6888 | bp = netdev_priv(dev); |
b6016b76 MC |
6889 | |
6890 | bp->flags = 0; | |
6891 | bp->phy_flags = 0; | |
6892 | ||
6893 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ | |
6894 | rc = pci_enable_device(pdev); | |
6895 | if (rc) { | |
898eb71c | 6896 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n"); |
b6016b76 MC |
6897 | goto err_out; |
6898 | } | |
6899 | ||
6900 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
9b91cf9d | 6901 | dev_err(&pdev->dev, |
2e8a538d | 6902 | "Cannot find PCI device base address, aborting.\n"); |
b6016b76 MC |
6903 | rc = -ENODEV; |
6904 | goto err_out_disable; | |
6905 | } | |
6906 | ||
6907 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
6908 | if (rc) { | |
9b91cf9d | 6909 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n"); |
b6016b76 MC |
6910 | goto err_out_disable; |
6911 | } | |
6912 | ||
6913 | pci_set_master(pdev); | |
6914 | ||
6915 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
6916 | if (bp->pm_cap == 0) { | |
9b91cf9d | 6917 | dev_err(&pdev->dev, |
2e8a538d | 6918 | "Cannot find power management capability, aborting.\n"); |
b6016b76 MC |
6919 | rc = -EIO; |
6920 | goto err_out_release; | |
6921 | } | |
6922 | ||
b6016b76 MC |
6923 | bp->dev = dev; |
6924 | bp->pdev = pdev; | |
6925 | ||
6926 | spin_lock_init(&bp->phy_lock); | |
1b8227c4 | 6927 | spin_lock_init(&bp->indirect_lock); |
c4028958 | 6928 | INIT_WORK(&bp->reset_task, bnx2_reset_task); |
b6016b76 MC |
6929 | |
6930 | dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); | |
59b47d8a | 6931 | mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1); |
b6016b76 MC |
6932 | dev->mem_end = dev->mem_start + mem_len; |
6933 | dev->irq = pdev->irq; | |
6934 | ||
6935 | bp->regview = ioremap_nocache(dev->base_addr, mem_len); | |
6936 | ||
6937 | if (!bp->regview) { | |
9b91cf9d | 6938 | dev_err(&pdev->dev, "Cannot map register space, aborting.\n"); |
b6016b76 MC |
6939 | rc = -ENOMEM; |
6940 | goto err_out_release; | |
6941 | } | |
6942 | ||
6943 | /* Configure byte swap and enable write to the reg_window registers. | |
6944 | * Rely on CPU to do target byte swapping on big endian systems | |
6945 | * The chip's target access swapping will not swap all accesses | |
6946 | */ | |
6947 | pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, | |
6948 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
6949 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); | |
6950 | ||
829ca9a3 | 6951 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 MC |
6952 | |
6953 | bp->chip_id = REG_RD(bp, BNX2_MISC_ID); | |
6954 | ||
883e5151 MC |
6955 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
6956 | if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) { | |
6957 | dev_err(&pdev->dev, | |
6958 | "Cannot find PCIE capability, aborting.\n"); | |
6959 | rc = -EIO; | |
6960 | goto err_out_unmap; | |
6961 | } | |
6962 | bp->flags |= PCIE_FLAG; | |
6963 | } else { | |
59b47d8a MC |
6964 | bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); |
6965 | if (bp->pcix_cap == 0) { | |
6966 | dev_err(&pdev->dev, | |
6967 | "Cannot find PCIX capability, aborting.\n"); | |
6968 | rc = -EIO; | |
6969 | goto err_out_unmap; | |
6970 | } | |
6971 | } | |
6972 | ||
b4b36042 MC |
6973 | if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) { |
6974 | if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) | |
6975 | bp->flags |= MSIX_CAP_FLAG; | |
6976 | } | |
6977 | ||
8e6a72c4 MC |
6978 | if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) { |
6979 | if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) | |
6980 | bp->flags |= MSI_CAP_FLAG; | |
6981 | } | |
6982 | ||
40453c83 MC |
6983 | /* 5708 cannot support DMA addresses > 40-bit. */ |
6984 | if (CHIP_NUM(bp) == CHIP_NUM_5708) | |
6985 | persist_dma_mask = dma_mask = DMA_40BIT_MASK; | |
6986 | else | |
6987 | persist_dma_mask = dma_mask = DMA_64BIT_MASK; | |
6988 | ||
6989 | /* Configure DMA attributes. */ | |
6990 | if (pci_set_dma_mask(pdev, dma_mask) == 0) { | |
6991 | dev->features |= NETIF_F_HIGHDMA; | |
6992 | rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); | |
6993 | if (rc) { | |
6994 | dev_err(&pdev->dev, | |
6995 | "pci_set_consistent_dma_mask failed, aborting.\n"); | |
6996 | goto err_out_unmap; | |
6997 | } | |
6998 | } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) { | |
6999 | dev_err(&pdev->dev, "System does not support DMA, aborting.\n"); | |
7000 | goto err_out_unmap; | |
7001 | } | |
7002 | ||
883e5151 MC |
7003 | if (!(bp->flags & PCIE_FLAG)) |
7004 | bnx2_get_pci_speed(bp); | |
b6016b76 MC |
7005 | |
7006 | /* 5706A0 may falsely detect SERR and PERR. */ | |
7007 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
7008 | reg = REG_RD(bp, PCI_COMMAND); | |
7009 | reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | |
7010 | REG_WR(bp, PCI_COMMAND, reg); | |
7011 | } | |
7012 | else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && | |
7013 | !(bp->flags & PCIX_FLAG)) { | |
7014 | ||
9b91cf9d | 7015 | dev_err(&pdev->dev, |
2e8a538d | 7016 | "5706 A1 can only be used in a PCIX bus, aborting.\n"); |
b6016b76 MC |
7017 | goto err_out_unmap; |
7018 | } | |
7019 | ||
7020 | bnx2_init_nvram(bp); | |
7021 | ||
e3648b3d MC |
7022 | reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE); |
7023 | ||
7024 | if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == | |
24cb230b MC |
7025 | BNX2_SHM_HDR_SIGNATURE_SIG) { |
7026 | u32 off = PCI_FUNC(pdev->devfn) << 2; | |
7027 | ||
7028 | bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off); | |
7029 | } else | |
e3648b3d MC |
7030 | bp->shmem_base = HOST_VIEW_SHMEM_BASE; |
7031 | ||
b6016b76 MC |
7032 | /* Get the permanent MAC address. First we need to make sure the |
7033 | * firmware is actually running. | |
7034 | */ | |
e3648b3d | 7035 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE); |
b6016b76 MC |
7036 | |
7037 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != | |
7038 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { | |
9b91cf9d | 7039 | dev_err(&pdev->dev, "Firmware not running, aborting.\n"); |
b6016b76 MC |
7040 | rc = -ENODEV; |
7041 | goto err_out_unmap; | |
7042 | } | |
7043 | ||
58fc2ea4 MC |
7044 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV); |
7045 | for (i = 0, j = 0; i < 3; i++) { | |
7046 | u8 num, k, skip0; | |
7047 | ||
7048 | num = (u8) (reg >> (24 - (i * 8))); | |
7049 | for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { | |
7050 | if (num >= k || !skip0 || k == 1) { | |
7051 | bp->fw_version[j++] = (num / k) + '0'; | |
7052 | skip0 = 0; | |
7053 | } | |
7054 | } | |
7055 | if (i != 2) | |
7056 | bp->fw_version[j++] = '.'; | |
7057 | } | |
846f5c62 MC |
7058 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE); |
7059 | if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) | |
7060 | bp->wol = 1; | |
7061 | ||
7062 | if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { | |
c2d3db8c MC |
7063 | bp->flags |= ASF_ENABLE_FLAG; |
7064 | ||
7065 | for (i = 0; i < 30; i++) { | |
7066 | reg = REG_RD_IND(bp, bp->shmem_base + | |
7067 | BNX2_BC_STATE_CONDITION); | |
7068 | if (reg & BNX2_CONDITION_MFW_RUN_MASK) | |
7069 | break; | |
7070 | msleep(10); | |
7071 | } | |
7072 | } | |
58fc2ea4 MC |
7073 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION); |
7074 | reg &= BNX2_CONDITION_MFW_RUN_MASK; | |
7075 | if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && | |
7076 | reg != BNX2_CONDITION_MFW_RUN_NONE) { | |
7077 | int i; | |
7078 | u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR); | |
7079 | ||
7080 | bp->fw_version[j++] = ' '; | |
7081 | for (i = 0; i < 3; i++) { | |
7082 | reg = REG_RD_IND(bp, addr + i * 4); | |
7083 | reg = swab32(reg); | |
7084 | memcpy(&bp->fw_version[j], ®, 4); | |
7085 | j += 4; | |
7086 | } | |
7087 | } | |
b6016b76 | 7088 | |
e3648b3d | 7089 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER); |
b6016b76 MC |
7090 | bp->mac_addr[0] = (u8) (reg >> 8); |
7091 | bp->mac_addr[1] = (u8) reg; | |
7092 | ||
e3648b3d | 7093 | reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER); |
b6016b76 MC |
7094 | bp->mac_addr[2] = (u8) (reg >> 24); |
7095 | bp->mac_addr[3] = (u8) (reg >> 16); | |
7096 | bp->mac_addr[4] = (u8) (reg >> 8); | |
7097 | bp->mac_addr[5] = (u8) reg; | |
7098 | ||
5d5d0015 MC |
7099 | bp->rx_offset = sizeof(struct l2_fhdr) + 2; |
7100 | ||
b6016b76 | 7101 | bp->tx_ring_size = MAX_TX_DESC_CNT; |
932f3772 | 7102 | bnx2_set_rx_ring_size(bp, 255); |
b6016b76 MC |
7103 | |
7104 | bp->rx_csum = 1; | |
7105 | ||
b6016b76 MC |
7106 | bp->tx_quick_cons_trip_int = 20; |
7107 | bp->tx_quick_cons_trip = 20; | |
7108 | bp->tx_ticks_int = 80; | |
7109 | bp->tx_ticks = 80; | |
6aa20a22 | 7110 | |
b6016b76 MC |
7111 | bp->rx_quick_cons_trip_int = 6; |
7112 | bp->rx_quick_cons_trip = 6; | |
7113 | bp->rx_ticks_int = 18; | |
7114 | bp->rx_ticks = 18; | |
7115 | ||
7ea6920e | 7116 | bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; |
b6016b76 MC |
7117 | |
7118 | bp->timer_interval = HZ; | |
cd339a0e | 7119 | bp->current_interval = HZ; |
b6016b76 | 7120 | |
5b0c76ad MC |
7121 | bp->phy_addr = 1; |
7122 | ||
b6016b76 | 7123 | /* Disable WOL support if we are running on a SERDES chip. */ |
253c8b75 MC |
7124 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
7125 | bnx2_get_5709_media(bp); | |
7126 | else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) | |
b6016b76 | 7127 | bp->phy_flags |= PHY_SERDES_FLAG; |
bac0dff6 | 7128 | |
0d8a6571 | 7129 | bp->phy_port = PORT_TP; |
bac0dff6 | 7130 | if (bp->phy_flags & PHY_SERDES_FLAG) { |
0d8a6571 | 7131 | bp->phy_port = PORT_FIBRE; |
846f5c62 MC |
7132 | reg = REG_RD_IND(bp, bp->shmem_base + |
7133 | BNX2_SHARED_HW_CFG_CONFIG); | |
7134 | if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { | |
7135 | bp->flags |= NO_WOL_FLAG; | |
7136 | bp->wol = 0; | |
7137 | } | |
bac0dff6 | 7138 | if (CHIP_NUM(bp) != CHIP_NUM_5706) { |
5b0c76ad | 7139 | bp->phy_addr = 2; |
5b0c76ad MC |
7140 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) |
7141 | bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG; | |
7142 | } | |
0d8a6571 MC |
7143 | bnx2_init_remote_phy(bp); |
7144 | ||
261dd5ca MC |
7145 | } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || |
7146 | CHIP_NUM(bp) == CHIP_NUM_5708) | |
7147 | bp->phy_flags |= PHY_CRC_FIX_FLAG; | |
fb0c18bd MC |
7148 | else if (CHIP_NUM(bp) == CHIP_NUM_5709 && |
7149 | (CHIP_REV(bp) == CHIP_REV_Ax || | |
7150 | CHIP_REV(bp) == CHIP_REV_Bx)) | |
b659f44e | 7151 | bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG; |
b6016b76 | 7152 | |
16088272 MC |
7153 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || |
7154 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || | |
846f5c62 | 7155 | (CHIP_ID(bp) == CHIP_ID_5708_B1)) { |
dda1e390 | 7156 | bp->flags |= NO_WOL_FLAG; |
846f5c62 MC |
7157 | bp->wol = 0; |
7158 | } | |
dda1e390 | 7159 | |
b6016b76 MC |
7160 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { |
7161 | bp->tx_quick_cons_trip_int = | |
7162 | bp->tx_quick_cons_trip; | |
7163 | bp->tx_ticks_int = bp->tx_ticks; | |
7164 | bp->rx_quick_cons_trip_int = | |
7165 | bp->rx_quick_cons_trip; | |
7166 | bp->rx_ticks_int = bp->rx_ticks; | |
7167 | bp->comp_prod_trip_int = bp->comp_prod_trip; | |
7168 | bp->com_ticks_int = bp->com_ticks; | |
7169 | bp->cmd_ticks_int = bp->cmd_ticks; | |
7170 | } | |
7171 | ||
f9317a40 MC |
7172 | /* Disable MSI on 5706 if AMD 8132 bridge is found. |
7173 | * | |
7174 | * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes | |
7175 | * with byte enables disabled on the unused 32-bit word. This is legal | |
7176 | * but causes problems on the AMD 8132 which will eventually stop | |
7177 | * responding after a while. | |
7178 | * | |
7179 | * AMD believes this incompatibility is unique to the 5706, and | |
88187dfa | 7180 | * prefers to locally disable MSI rather than globally disabling it. |
f9317a40 MC |
7181 | */ |
7182 | if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) { | |
7183 | struct pci_dev *amd_8132 = NULL; | |
7184 | ||
7185 | while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, | |
7186 | PCI_DEVICE_ID_AMD_8132_BRIDGE, | |
7187 | amd_8132))) { | |
f9317a40 | 7188 | |
44c10138 AK |
7189 | if (amd_8132->revision >= 0x10 && |
7190 | amd_8132->revision <= 0x13) { | |
f9317a40 MC |
7191 | disable_msi = 1; |
7192 | pci_dev_put(amd_8132); | |
7193 | break; | |
7194 | } | |
7195 | } | |
7196 | } | |
7197 | ||
deaf391b | 7198 | bnx2_set_default_link(bp); |
b6016b76 MC |
7199 | bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; |
7200 | ||
cd339a0e MC |
7201 | init_timer(&bp->timer); |
7202 | bp->timer.expires = RUN_AT(bp->timer_interval); | |
7203 | bp->timer.data = (unsigned long) bp; | |
7204 | bp->timer.function = bnx2_timer; | |
7205 | ||
b6016b76 MC |
7206 | return 0; |
7207 | ||
7208 | err_out_unmap: | |
7209 | if (bp->regview) { | |
7210 | iounmap(bp->regview); | |
73eef4cd | 7211 | bp->regview = NULL; |
b6016b76 MC |
7212 | } |
7213 | ||
7214 | err_out_release: | |
7215 | pci_release_regions(pdev); | |
7216 | ||
7217 | err_out_disable: | |
7218 | pci_disable_device(pdev); | |
7219 | pci_set_drvdata(pdev, NULL); | |
7220 | ||
7221 | err_out: | |
7222 | return rc; | |
7223 | } | |
7224 | ||
883e5151 MC |
7225 | static char * __devinit |
7226 | bnx2_bus_string(struct bnx2 *bp, char *str) | |
7227 | { | |
7228 | char *s = str; | |
7229 | ||
7230 | if (bp->flags & PCIE_FLAG) { | |
7231 | s += sprintf(s, "PCI Express"); | |
7232 | } else { | |
7233 | s += sprintf(s, "PCI"); | |
7234 | if (bp->flags & PCIX_FLAG) | |
7235 | s += sprintf(s, "-X"); | |
7236 | if (bp->flags & PCI_32BIT_FLAG) | |
7237 | s += sprintf(s, " 32-bit"); | |
7238 | else | |
7239 | s += sprintf(s, " 64-bit"); | |
7240 | s += sprintf(s, " %dMHz", bp->bus_speed_mhz); | |
7241 | } | |
7242 | return str; | |
7243 | } | |
7244 | ||
35efa7c1 MC |
7245 | static int __devinit |
7246 | bnx2_init_napi(struct bnx2 *bp) | |
7247 | { | |
b4b36042 MC |
7248 | int i; |
7249 | struct bnx2_napi *bnapi; | |
35efa7c1 | 7250 | |
b4b36042 MC |
7251 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
7252 | bnapi = &bp->bnx2_napi[i]; | |
7253 | bnapi->bp = bp; | |
7254 | } | |
7255 | netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64); | |
35efa7c1 MC |
7256 | } |
7257 | ||
b6016b76 MC |
7258 | static int __devinit |
7259 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
7260 | { | |
7261 | static int version_printed = 0; | |
7262 | struct net_device *dev = NULL; | |
7263 | struct bnx2 *bp; | |
0795af57 | 7264 | int rc; |
883e5151 | 7265 | char str[40]; |
0795af57 | 7266 | DECLARE_MAC_BUF(mac); |
b6016b76 MC |
7267 | |
7268 | if (version_printed++ == 0) | |
7269 | printk(KERN_INFO "%s", version); | |
7270 | ||
7271 | /* dev zeroed in init_etherdev */ | |
7272 | dev = alloc_etherdev(sizeof(*bp)); | |
7273 | ||
7274 | if (!dev) | |
7275 | return -ENOMEM; | |
7276 | ||
7277 | rc = bnx2_init_board(pdev, dev); | |
7278 | if (rc < 0) { | |
7279 | free_netdev(dev); | |
7280 | return rc; | |
7281 | } | |
7282 | ||
7283 | dev->open = bnx2_open; | |
7284 | dev->hard_start_xmit = bnx2_start_xmit; | |
7285 | dev->stop = bnx2_close; | |
7286 | dev->get_stats = bnx2_get_stats; | |
7287 | dev->set_multicast_list = bnx2_set_rx_mode; | |
7288 | dev->do_ioctl = bnx2_ioctl; | |
7289 | dev->set_mac_address = bnx2_change_mac_addr; | |
7290 | dev->change_mtu = bnx2_change_mtu; | |
7291 | dev->tx_timeout = bnx2_tx_timeout; | |
7292 | dev->watchdog_timeo = TX_TIMEOUT; | |
7293 | #ifdef BCM_VLAN | |
7294 | dev->vlan_rx_register = bnx2_vlan_rx_register; | |
b6016b76 | 7295 | #endif |
b6016b76 | 7296 | dev->ethtool_ops = &bnx2_ethtool_ops; |
b6016b76 | 7297 | |
972ec0d4 | 7298 | bp = netdev_priv(dev); |
35efa7c1 | 7299 | bnx2_init_napi(bp); |
b6016b76 MC |
7300 | |
7301 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | |
7302 | dev->poll_controller = poll_bnx2; | |
7303 | #endif | |
7304 | ||
1b2f922f MC |
7305 | pci_set_drvdata(pdev, dev); |
7306 | ||
7307 | memcpy(dev->dev_addr, bp->mac_addr, 6); | |
7308 | memcpy(dev->perm_addr, bp->mac_addr, 6); | |
7309 | bp->name = board_info[ent->driver_data].name; | |
7310 | ||
d212f87b | 7311 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
4666f87a | 7312 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
d212f87b SH |
7313 | dev->features |= NETIF_F_IPV6_CSUM; |
7314 | ||
1b2f922f MC |
7315 | #ifdef BCM_VLAN |
7316 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
7317 | #endif | |
7318 | dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; | |
4666f87a MC |
7319 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
7320 | dev->features |= NETIF_F_TSO6; | |
1b2f922f | 7321 | |
b6016b76 | 7322 | if ((rc = register_netdev(dev))) { |
9b91cf9d | 7323 | dev_err(&pdev->dev, "Cannot register net device\n"); |
b6016b76 MC |
7324 | if (bp->regview) |
7325 | iounmap(bp->regview); | |
7326 | pci_release_regions(pdev); | |
7327 | pci_disable_device(pdev); | |
7328 | pci_set_drvdata(pdev, NULL); | |
7329 | free_netdev(dev); | |
7330 | return rc; | |
7331 | } | |
7332 | ||
883e5151 | 7333 | printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " |
0795af57 | 7334 | "IRQ %d, node addr %s\n", |
b6016b76 MC |
7335 | dev->name, |
7336 | bp->name, | |
7337 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', | |
7338 | ((CHIP_ID(bp) & 0x0ff0) >> 4), | |
883e5151 | 7339 | bnx2_bus_string(bp, str), |
b6016b76 | 7340 | dev->base_addr, |
0795af57 | 7341 | bp->pdev->irq, print_mac(mac, dev->dev_addr)); |
b6016b76 | 7342 | |
b6016b76 MC |
7343 | return 0; |
7344 | } | |
7345 | ||
7346 | static void __devexit | |
7347 | bnx2_remove_one(struct pci_dev *pdev) | |
7348 | { | |
7349 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 7350 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7351 | |
afdc08b9 MC |
7352 | flush_scheduled_work(); |
7353 | ||
b6016b76 MC |
7354 | unregister_netdev(dev); |
7355 | ||
7356 | if (bp->regview) | |
7357 | iounmap(bp->regview); | |
7358 | ||
7359 | free_netdev(dev); | |
7360 | pci_release_regions(pdev); | |
7361 | pci_disable_device(pdev); | |
7362 | pci_set_drvdata(pdev, NULL); | |
7363 | } | |
7364 | ||
7365 | static int | |
829ca9a3 | 7366 | bnx2_suspend(struct pci_dev *pdev, pm_message_t state) |
b6016b76 MC |
7367 | { |
7368 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 7369 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7370 | u32 reset_code; |
7371 | ||
6caebb02 MC |
7372 | /* PCI register 4 needs to be saved whether netif_running() or not. |
7373 | * MSI address and data need to be saved if using MSI and | |
7374 | * netif_running(). | |
7375 | */ | |
7376 | pci_save_state(pdev); | |
b6016b76 MC |
7377 | if (!netif_running(dev)) |
7378 | return 0; | |
7379 | ||
1d60290f | 7380 | flush_scheduled_work(); |
b6016b76 MC |
7381 | bnx2_netif_stop(bp); |
7382 | netif_device_detach(dev); | |
7383 | del_timer_sync(&bp->timer); | |
dda1e390 | 7384 | if (bp->flags & NO_WOL_FLAG) |
6c4f095e | 7385 | reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; |
dda1e390 | 7386 | else if (bp->wol) |
b6016b76 MC |
7387 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; |
7388 | else | |
7389 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
7390 | bnx2_reset_chip(bp, reset_code); | |
7391 | bnx2_free_skbs(bp); | |
829ca9a3 | 7392 | bnx2_set_power_state(bp, pci_choose_state(pdev, state)); |
b6016b76 MC |
7393 | return 0; |
7394 | } | |
7395 | ||
7396 | static int | |
7397 | bnx2_resume(struct pci_dev *pdev) | |
7398 | { | |
7399 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 7400 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7401 | |
6caebb02 | 7402 | pci_restore_state(pdev); |
b6016b76 MC |
7403 | if (!netif_running(dev)) |
7404 | return 0; | |
7405 | ||
829ca9a3 | 7406 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 MC |
7407 | netif_device_attach(dev); |
7408 | bnx2_init_nic(bp); | |
7409 | bnx2_netif_start(bp); | |
7410 | return 0; | |
7411 | } | |
7412 | ||
7413 | static struct pci_driver bnx2_pci_driver = { | |
14ab9b86 PH |
7414 | .name = DRV_MODULE_NAME, |
7415 | .id_table = bnx2_pci_tbl, | |
7416 | .probe = bnx2_init_one, | |
7417 | .remove = __devexit_p(bnx2_remove_one), | |
7418 | .suspend = bnx2_suspend, | |
7419 | .resume = bnx2_resume, | |
b6016b76 MC |
7420 | }; |
7421 | ||
7422 | static int __init bnx2_init(void) | |
7423 | { | |
29917620 | 7424 | return pci_register_driver(&bnx2_pci_driver); |
b6016b76 MC |
7425 | } |
7426 | ||
7427 | static void __exit bnx2_cleanup(void) | |
7428 | { | |
7429 | pci_unregister_driver(&bnx2_pci_driver); | |
7430 | } | |
7431 | ||
7432 | module_init(bnx2_init); | |
7433 | module_exit(bnx2_cleanup); | |
7434 | ||
7435 | ||
7436 |