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[BNX2]: Misc. fixes
[mirror_ubuntu-eoan-kernel.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12#include "bnx2.h"
13#include "bnx2_fw.h"
14
15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": "
05d0f1cf
MC		 17#define DRV_MODULE_VERSION "1.4.30"
18#define DRV_MODULE_RELDATE "October 11, 2005"
b6016b76
MC		 19
20#define RUN_AT(x) (jiffies + (x))
21
22/* Time in jiffies before concluding the transmitter is hung. */
23#define TX_TIMEOUT (5*HZ)
24
25static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 29MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 30MODULE_LICENSE("GPL");
31MODULE_VERSION(DRV_MODULE_VERSION);
32
33static int disable_msi = 0;
34
35module_param(disable_msi, int, 0);
36MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
5b0c76ad
MC		 44 BCM5708,
45 BCM5708S,
b6016b76
MC		 46} board_t;
47
48/* indexed by board_t, above */
49static struct {
50 char *name;
51} board_info[] __devinitdata = {
52 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
53 { "HP NC370T Multifunction Gigabit Server Adapter" },
54 { "HP NC370i Multifunction Gigabit Server Adapter" },
55 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
56 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 57 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
b6016b76
MC		 59 };
60
61static struct pci_device_id bnx2_pci_tbl[] = {
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
65 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 68 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 70 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
71 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
72 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 74 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
b6016b76
MC		 76 { 0, }
77};
78
79static struct flash_spec flash_table[] =
80{
81 /* Slow EEPROM */
37137709 82 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
b6016b76
MC		 83 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
84 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
85 "EEPROM - slow"},
37137709
MC		 86 /* Expansion entry 0001 */
87 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76 88 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 89 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
90 "Entry 0001"},
b6016b76
MC		 91 /* Saifun SA25F010 (non-buffered flash) */
92 /* strap, cfg1, & write1 need updates */
37137709 93 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 94 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
95 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
96 "Non-buffered flash (128kB)"},
97 /* Saifun SA25F020 (non-buffered flash) */
98 /* strap, cfg1, & write1 need updates */
37137709 99 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 100 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
101 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
102 "Non-buffered flash (256kB)"},
37137709
MC		 103 /* Expansion entry 0100 */
104 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
105 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
107 "Entry 0100"},
108 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
109 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
110 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
111 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
112 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
113 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
114 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
115 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
116 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
117 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
118 /* Saifun SA25F005 (non-buffered flash) */
119 /* strap, cfg1, & write1 need updates */
120 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
121 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
122 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
123 "Non-buffered flash (64kB)"},
124 /* Fast EEPROM */
125 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
126 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
127 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128 "EEPROM - fast"},
129 /* Expansion entry 1001 */
130 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
131 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
132 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133 "Entry 1001"},
134 /* Expansion entry 1010 */
135 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138 "Entry 1010"},
139 /* ATMEL AT45DB011B (buffered flash) */
140 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
141 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
142 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
143 "Buffered flash (128kB)"},
144 /* Expansion entry 1100 */
145 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 "Entry 1100"},
149 /* Expansion entry 1101 */
150 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
151 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
153 "Entry 1101"},
154 /* Ateml Expansion entry 1110 */
155 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
156 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
157 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
158 "Entry 1110 (Atmel)"},
159 /* ATMEL AT45DB021B (buffered flash) */
160 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
161 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
162 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
163 "Buffered flash (256kB)"},
b6016b76
MC		 164};
165
166MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
167
e89bbf10
MC		 168static inline u32 bnx2_tx_avail(struct bnx2 *bp)
169{
170 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
171
172 if (diff > MAX_TX_DESC_CNT)
173 diff = (diff & MAX_TX_DESC_CNT) - 1;
174 return (bp->tx_ring_size - diff);
175}
176
b6016b76
MC		 177static u32
178bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
179{
180 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
181 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
182}
183
184static void
185bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
186{
187 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
188 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
189}
190
191static void
192bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
193{
194 offset += cid_addr;
195 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
196 REG_WR(bp, BNX2_CTX_DATA, val);
197}
198
199static int
200bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
201{
202 u32 val1;
203 int i, ret;
204
205 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
206 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
207 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
208
209 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
210 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
211
212 udelay(40);
213 }
214
215 val1 = (bp->phy_addr << 21) | (reg << 16) |
216 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
217 BNX2_EMAC_MDIO_COMM_START_BUSY;
218 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
219
220 for (i = 0; i < 50; i++) {
221 udelay(10);
222
223 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
224 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
225 udelay(5);
226
227 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
228 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
229
230 break;
231 }
232 }
233
234 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
235 *val = 0x0;
236 ret = -EBUSY;
237 }
238 else {
239 *val = val1;
240 ret = 0;
241 }
242
243 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
244 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
245 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
246
247 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
248 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249
250 udelay(40);
251 }
252
253 return ret;
254}
255
256static int
257bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
258{
259 u32 val1;
260 int i, ret;
261
262 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
263 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
264 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
265
266 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
267 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
268
269 udelay(40);
270 }
271
272 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
273 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
274 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
275 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
276
277 for (i = 0; i < 50; i++) {
278 udelay(10);
279
280 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
281 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
282 udelay(5);
283 break;
284 }
285 }
286
287 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
288 ret = -EBUSY;
289 else
290 ret = 0;
291
292 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
293 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
294 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
295
296 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
297 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
298
299 udelay(40);
300 }
301
302 return ret;
303}
304
305static void
306bnx2_disable_int(struct bnx2 *bp)
307{
308 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
309 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
310 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
311}
312
313static void
314bnx2_enable_int(struct bnx2 *bp)
315{
316 u32 val;
317
318 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
320
321 val = REG_RD(bp, BNX2_HC_COMMAND);
322 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
323}
324
325static void
326bnx2_disable_int_sync(struct bnx2 *bp)
327{
328 atomic_inc(&bp->intr_sem);
329 bnx2_disable_int(bp);
330 synchronize_irq(bp->pdev->irq);
331}
332
333static void
334bnx2_netif_stop(struct bnx2 *bp)
335{
336 bnx2_disable_int_sync(bp);
337 if (netif_running(bp->dev)) {
338 netif_poll_disable(bp->dev);
339 netif_tx_disable(bp->dev);
340 bp->dev->trans_start = jiffies; /* prevent tx timeout */
341 }
342}
343
344static void
345bnx2_netif_start(struct bnx2 *bp)
346{
347 if (atomic_dec_and_test(&bp->intr_sem)) {
348 if (netif_running(bp->dev)) {
349 netif_wake_queue(bp->dev);
350 netif_poll_enable(bp->dev);
351 bnx2_enable_int(bp);
352 }
353 }
354}
355
356static void
357bnx2_free_mem(struct bnx2 *bp)
358{
359 if (bp->stats_blk) {
360 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
361 bp->stats_blk, bp->stats_blk_mapping);
362 bp->stats_blk = NULL;
363 }
364 if (bp->status_blk) {
365 pci_free_consistent(bp->pdev, sizeof(struct status_block),
366 bp->status_blk, bp->status_blk_mapping);
367 bp->status_blk = NULL;
368 }
369 if (bp->tx_desc_ring) {
370 pci_free_consistent(bp->pdev,
371 sizeof(struct tx_bd) * TX_DESC_CNT,
372 bp->tx_desc_ring, bp->tx_desc_mapping);
373 bp->tx_desc_ring = NULL;
374 }
b4558ea9
JJ		 375 kfree(bp->tx_buf_ring);
376 bp->tx_buf_ring = NULL;
b6016b76
MC		 377 if (bp->rx_desc_ring) {
378 pci_free_consistent(bp->pdev,
379 sizeof(struct rx_bd) * RX_DESC_CNT,
380 bp->rx_desc_ring, bp->rx_desc_mapping);
381 bp->rx_desc_ring = NULL;
382 }
b4558ea9
JJ		 383 kfree(bp->rx_buf_ring);
384 bp->rx_buf_ring = NULL;
b6016b76
MC		 385}
386
387static int
388bnx2_alloc_mem(struct bnx2 *bp)
389{
390 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
391 GFP_KERNEL);
392 if (bp->tx_buf_ring == NULL)
393 return -ENOMEM;
394
395 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
396 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
397 sizeof(struct tx_bd) *
398 TX_DESC_CNT,
399 &bp->tx_desc_mapping);
400 if (bp->tx_desc_ring == NULL)
401 goto alloc_mem_err;
402
403 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
404 GFP_KERNEL);
405 if (bp->rx_buf_ring == NULL)
406 goto alloc_mem_err;
407
408 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
409 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
410 sizeof(struct rx_bd) *
411 RX_DESC_CNT,
412 &bp->rx_desc_mapping);
413 if (bp->rx_desc_ring == NULL)
414 goto alloc_mem_err;
415
416 bp->status_blk = pci_alloc_consistent(bp->pdev,
417 sizeof(struct status_block),
418 &bp->status_blk_mapping);
419 if (bp->status_blk == NULL)
420 goto alloc_mem_err;
421
422 memset(bp->status_blk, 0, sizeof(struct status_block));
423
424 bp->stats_blk = pci_alloc_consistent(bp->pdev,
425 sizeof(struct statistics_block),
426 &bp->stats_blk_mapping);
427 if (bp->stats_blk == NULL)
428 goto alloc_mem_err;
429
430 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
431
432 return 0;
433
434alloc_mem_err:
435 bnx2_free_mem(bp);
436 return -ENOMEM;
437}
438
e3648b3d
MC		 439static void
440bnx2_report_fw_link(struct bnx2 *bp)
441{
442 u32 fw_link_status = 0;
443
444 if (bp->link_up) {
445 u32 bmsr;
446
447 switch (bp->line_speed) {
448 case SPEED_10:
449 if (bp->duplex == DUPLEX_HALF)
450 fw_link_status = BNX2_LINK_STATUS_10HALF;
451 else
452 fw_link_status = BNX2_LINK_STATUS_10FULL;
453 break;
454 case SPEED_100:
455 if (bp->duplex == DUPLEX_HALF)
456 fw_link_status = BNX2_LINK_STATUS_100HALF;
457 else
458 fw_link_status = BNX2_LINK_STATUS_100FULL;
459 break;
460 case SPEED_1000:
461 if (bp->duplex == DUPLEX_HALF)
462 fw_link_status = BNX2_LINK_STATUS_1000HALF;
463 else
464 fw_link_status = BNX2_LINK_STATUS_1000FULL;
465 break;
466 case SPEED_2500:
467 if (bp->duplex == DUPLEX_HALF)
468 fw_link_status = BNX2_LINK_STATUS_2500HALF;
469 else
470 fw_link_status = BNX2_LINK_STATUS_2500FULL;
471 break;
472 }
473
474 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
475
476 if (bp->autoneg) {
477 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
478
479 bnx2_read_phy(bp, MII_BMSR, &bmsr);
480 bnx2_read_phy(bp, MII_BMSR, &bmsr);
481
482 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
483 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
484 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
485 else
486 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
487 }
488 }
489 else
490 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
491
492 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
493}
494
b6016b76
MC		 495static void
496bnx2_report_link(struct bnx2 *bp)
497{
498 if (bp->link_up) {
499 netif_carrier_on(bp->dev);
500 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
501
502 printk("%d Mbps ", bp->line_speed);
503
504 if (bp->duplex == DUPLEX_FULL)
505 printk("full duplex");
506 else
507 printk("half duplex");
508
509 if (bp->flow_ctrl) {
510 if (bp->flow_ctrl & FLOW_CTRL_RX) {
511 printk(", receive ");
512 if (bp->flow_ctrl & FLOW_CTRL_TX)
513 printk("& transmit ");
514 }
515 else {
516 printk(", transmit ");
517 }
518 printk("flow control ON");
519 }
520 printk("\n");
521 }
522 else {
523 netif_carrier_off(bp->dev);
524 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
525 }
e3648b3d
MC		 526
527 bnx2_report_fw_link(bp);
b6016b76
MC		 528}
529
530static void
531bnx2_resolve_flow_ctrl(struct bnx2 *bp)
532{
533 u32 local_adv, remote_adv;
534
535 bp->flow_ctrl = 0;
536 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
537 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
538
539 if (bp->duplex == DUPLEX_FULL) {
540 bp->flow_ctrl = bp->req_flow_ctrl;
541 }
542 return;
543 }
544
545 if (bp->duplex != DUPLEX_FULL) {
546 return;
547 }
548
5b0c76ad
MC		 549 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
550 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
551 u32 val;
552
553 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
554 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
555 bp->flow_ctrl |= FLOW_CTRL_TX;
556 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
557 bp->flow_ctrl |= FLOW_CTRL_RX;
558 return;
559 }
560
b6016b76
MC		 561 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
562 bnx2_read_phy(bp, MII_LPA, &remote_adv);
563
564 if (bp->phy_flags & PHY_SERDES_FLAG) {
565 u32 new_local_adv = 0;
566 u32 new_remote_adv = 0;
567
568 if (local_adv & ADVERTISE_1000XPAUSE)
569 new_local_adv |= ADVERTISE_PAUSE_CAP;
570 if (local_adv & ADVERTISE_1000XPSE_ASYM)
571 new_local_adv |= ADVERTISE_PAUSE_ASYM;
572 if (remote_adv & ADVERTISE_1000XPAUSE)
573 new_remote_adv |= ADVERTISE_PAUSE_CAP;
574 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
575 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
576
577 local_adv = new_local_adv;
578 remote_adv = new_remote_adv;
579 }
580
581 /* See Table 28B-3 of 802.3ab-1999 spec. */
582 if (local_adv & ADVERTISE_PAUSE_CAP) {
583 if(local_adv & ADVERTISE_PAUSE_ASYM) {
584 if (remote_adv & ADVERTISE_PAUSE_CAP) {
585 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
586 }
587 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
588 bp->flow_ctrl = FLOW_CTRL_RX;
589 }
590 }
591 else {
592 if (remote_adv & ADVERTISE_PAUSE_CAP) {
593 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
594 }
595 }
596 }
597 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
598 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
599 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
600
601 bp->flow_ctrl = FLOW_CTRL_TX;
602 }
603 }
604}
605
606static int
5b0c76ad
MC		 607bnx2_5708s_linkup(struct bnx2 *bp)
608{
609 u32 val;
610
611 bp->link_up = 1;
612 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
613 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
614 case BCM5708S_1000X_STAT1_SPEED_10:
615 bp->line_speed = SPEED_10;
616 break;
617 case BCM5708S_1000X_STAT1_SPEED_100:
618 bp->line_speed = SPEED_100;
619 break;
620 case BCM5708S_1000X_STAT1_SPEED_1G:
621 bp->line_speed = SPEED_1000;
622 break;
623 case BCM5708S_1000X_STAT1_SPEED_2G5:
624 bp->line_speed = SPEED_2500;
625 break;
626 }
627 if (val & BCM5708S_1000X_STAT1_FD)
628 bp->duplex = DUPLEX_FULL;
629 else
630 bp->duplex = DUPLEX_HALF;
631
632 return 0;
633}
634
635static int
636bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 637{
638 u32 bmcr, local_adv, remote_adv, common;
639
640 bp->link_up = 1;
641 bp->line_speed = SPEED_1000;
642
643 bnx2_read_phy(bp, MII_BMCR, &bmcr);
644 if (bmcr & BMCR_FULLDPLX) {
645 bp->duplex = DUPLEX_FULL;
646 }
647 else {
648 bp->duplex = DUPLEX_HALF;
649 }
650
651 if (!(bmcr & BMCR_ANENABLE)) {
652 return 0;
653 }
654
655 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
656 bnx2_read_phy(bp, MII_LPA, &remote_adv);
657
658 common = local_adv & remote_adv;
659 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
660
661 if (common & ADVERTISE_1000XFULL) {
662 bp->duplex = DUPLEX_FULL;
663 }
664 else {
665 bp->duplex = DUPLEX_HALF;
666 }
667 }
668
669 return 0;
670}
671
672static int
673bnx2_copper_linkup(struct bnx2 *bp)
674{
675 u32 bmcr;
676
677 bnx2_read_phy(bp, MII_BMCR, &bmcr);
678 if (bmcr & BMCR_ANENABLE) {
679 u32 local_adv, remote_adv, common;
680
681 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
682 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
683
684 common = local_adv & (remote_adv >> 2);
685 if (common & ADVERTISE_1000FULL) {
686 bp->line_speed = SPEED_1000;
687 bp->duplex = DUPLEX_FULL;
688 }
689 else if (common & ADVERTISE_1000HALF) {
690 bp->line_speed = SPEED_1000;
691 bp->duplex = DUPLEX_HALF;
692 }
693 else {
694 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
695 bnx2_read_phy(bp, MII_LPA, &remote_adv);
696
697 common = local_adv & remote_adv;
698 if (common & ADVERTISE_100FULL) {
699 bp->line_speed = SPEED_100;
700 bp->duplex = DUPLEX_FULL;
701 }
702 else if (common & ADVERTISE_100HALF) {
703 bp->line_speed = SPEED_100;
704 bp->duplex = DUPLEX_HALF;
705 }
706 else if (common & ADVERTISE_10FULL) {
707 bp->line_speed = SPEED_10;
708 bp->duplex = DUPLEX_FULL;
709 }
710 else if (common & ADVERTISE_10HALF) {
711 bp->line_speed = SPEED_10;
712 bp->duplex = DUPLEX_HALF;
713 }
714 else {
715 bp->line_speed = 0;
716 bp->link_up = 0;
717 }
718 }
719 }
720 else {
721 if (bmcr & BMCR_SPEED100) {
722 bp->line_speed = SPEED_100;
723 }
724 else {
725 bp->line_speed = SPEED_10;
726 }
727 if (bmcr & BMCR_FULLDPLX) {
728 bp->duplex = DUPLEX_FULL;
729 }
730 else {
731 bp->duplex = DUPLEX_HALF;
732 }
733 }
734
735 return 0;
736}
737
738static int
739bnx2_set_mac_link(struct bnx2 *bp)
740{
741 u32 val;
742
743 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
744 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
745 (bp->duplex == DUPLEX_HALF)) {
746 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
747 }
748
749 /* Configure the EMAC mode register. */
750 val = REG_RD(bp, BNX2_EMAC_MODE);
751
752 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad
MC		 753 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
754 BNX2_EMAC_MODE_25G);
b6016b76
MC		 755
756 if (bp->link_up) {
5b0c76ad
MC		 757 switch (bp->line_speed) {
758 case SPEED_10:
759 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
760 val |= BNX2_EMAC_MODE_PORT_MII_10;
761 break;
762 }
763 /* fall through */
764 case SPEED_100:
765 val |= BNX2_EMAC_MODE_PORT_MII;
766 break;
767 case SPEED_2500:
768 val |= BNX2_EMAC_MODE_25G;
769 /* fall through */
770 case SPEED_1000:
771 val |= BNX2_EMAC_MODE_PORT_GMII;
772 break;
773 }
b6016b76
MC		 774 }
775 else {
776 val |= BNX2_EMAC_MODE_PORT_GMII;
777 }
778
779 /* Set the MAC to operate in the appropriate duplex mode. */
780 if (bp->duplex == DUPLEX_HALF)
781 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
782 REG_WR(bp, BNX2_EMAC_MODE, val);
783
784 /* Enable/disable rx PAUSE. */
785 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
786
787 if (bp->flow_ctrl & FLOW_CTRL_RX)
788 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
789 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
790
791 /* Enable/disable tx PAUSE. */
792 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
793 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
794
795 if (bp->flow_ctrl & FLOW_CTRL_TX)
796 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
797 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
798
799 /* Acknowledge the interrupt. */
800 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
801
802 return 0;
803}
804
805static int
806bnx2_set_link(struct bnx2 *bp)
807{
808 u32 bmsr;
809 u8 link_up;
810
811 if (bp->loopback == MAC_LOOPBACK) {
812 bp->link_up = 1;
813 return 0;
814 }
815
816 link_up = bp->link_up;
817
818 bnx2_read_phy(bp, MII_BMSR, &bmsr);
819 bnx2_read_phy(bp, MII_BMSR, &bmsr);
820
821 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
822 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
823 u32 val;
824
825 val = REG_RD(bp, BNX2_EMAC_STATUS);
826 if (val & BNX2_EMAC_STATUS_LINK)
827 bmsr |= BMSR_LSTATUS;
828 else
829 bmsr &= ~BMSR_LSTATUS;
830 }
831
832 if (bmsr & BMSR_LSTATUS) {
833 bp->link_up = 1;
834
835 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 836 if (CHIP_NUM(bp) == CHIP_NUM_5706)
837 bnx2_5706s_linkup(bp);
838 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
839 bnx2_5708s_linkup(bp);
b6016b76
MC		 840 }
841 else {
842 bnx2_copper_linkup(bp);
843 }
844 bnx2_resolve_flow_ctrl(bp);
845 }
846 else {
847 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
848 (bp->autoneg & AUTONEG_SPEED)) {
849
850 u32 bmcr;
851
852 bnx2_read_phy(bp, MII_BMCR, &bmcr);
853 if (!(bmcr & BMCR_ANENABLE)) {
854 bnx2_write_phy(bp, MII_BMCR, bmcr |
855 BMCR_ANENABLE);
856 }
857 }
858 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
859 bp->link_up = 0;
860 }
861
862 if (bp->link_up != link_up) {
863 bnx2_report_link(bp);
864 }
865
866 bnx2_set_mac_link(bp);
867
868 return 0;
869}
870
871static int
872bnx2_reset_phy(struct bnx2 *bp)
873{
874 int i;
875 u32 reg;
876
877 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
878
879#define PHY_RESET_MAX_WAIT 100
880 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
881 udelay(10);
882
883 bnx2_read_phy(bp, MII_BMCR, &reg);
884 if (!(reg & BMCR_RESET)) {
885 udelay(20);
886 break;
887 }
888 }
889 if (i == PHY_RESET_MAX_WAIT) {
890 return -EBUSY;
891 }
892 return 0;
893}
894
895static u32
896bnx2_phy_get_pause_adv(struct bnx2 *bp)
897{
898 u32 adv = 0;
899
900 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
901 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
902
903 if (bp->phy_flags & PHY_SERDES_FLAG) {
904 adv = ADVERTISE_1000XPAUSE;
905 }
906 else {
907 adv = ADVERTISE_PAUSE_CAP;
908 }
909 }
910 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
911 if (bp->phy_flags & PHY_SERDES_FLAG) {
912 adv = ADVERTISE_1000XPSE_ASYM;
913 }
914 else {
915 adv = ADVERTISE_PAUSE_ASYM;
916 }
917 }
918 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
919 if (bp->phy_flags & PHY_SERDES_FLAG) {
920 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
921 }
922 else {
923 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
924 }
925 }
926 return adv;
927}
928
929static int
930bnx2_setup_serdes_phy(struct bnx2 *bp)
931{
5b0c76ad 932 u32 adv, bmcr, up1;
b6016b76
MC		 933 u32 new_adv = 0;
934
935 if (!(bp->autoneg & AUTONEG_SPEED)) {
936 u32 new_bmcr;
5b0c76ad
MC		 937 int force_link_down = 0;
938
939 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
940 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
941 if (up1 & BCM5708S_UP1_2G5) {
942 up1 &= ~BCM5708S_UP1_2G5;
943 bnx2_write_phy(bp, BCM5708S_UP1, up1);
944 force_link_down = 1;
945 }
946 }
947
948 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
949 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
b6016b76
MC		 950
951 bnx2_read_phy(bp, MII_BMCR, &bmcr);
952 new_bmcr = bmcr & ~BMCR_ANENABLE;
953 new_bmcr |= BMCR_SPEED1000;
954 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 955 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 956 new_bmcr |= BMCR_FULLDPLX;
957 }
958 else {
5b0c76ad 959 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 960 new_bmcr &= ~BMCR_FULLDPLX;
961 }
5b0c76ad 962 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 963 /* Force a link down visible on the other side */
964 if (bp->link_up) {
5b0c76ad
MC		 965 bnx2_write_phy(bp, MII_ADVERTISE, adv &
966 ~(ADVERTISE_1000XFULL |
967 ADVERTISE_1000XHALF));
b6016b76
MC		 968 bnx2_write_phy(bp, MII_BMCR, bmcr |
969 BMCR_ANRESTART | BMCR_ANENABLE);
970
971 bp->link_up = 0;
972 netif_carrier_off(bp->dev);
5b0c76ad 973 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
b6016b76 974 }
5b0c76ad 975 bnx2_write_phy(bp, MII_ADVERTISE, adv);
b6016b76
MC		 976 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
977 }
978 return 0;
979 }
980
5b0c76ad
MC		 981 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
982 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
983 up1 |= BCM5708S_UP1_2G5;
984 bnx2_write_phy(bp, BCM5708S_UP1, up1);
985 }
986
b6016b76
MC		 987 if (bp->advertising & ADVERTISED_1000baseT_Full)
988 new_adv |= ADVERTISE_1000XFULL;
989
990 new_adv |= bnx2_phy_get_pause_adv(bp);
991
992 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
993 bnx2_read_phy(bp, MII_BMCR, &bmcr);
994
995 bp->serdes_an_pending = 0;
996 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
997 /* Force a link down visible on the other side */
998 if (bp->link_up) {
999 int i;
1000
1001 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1002 for (i = 0; i < 110; i++) {
1003 udelay(100);
1004 }
1005 }
1006
1007 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1008 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1009 BMCR_ANENABLE);
cd339a0e
MC		 1010 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1011 /* Speed up link-up time when the link partner
1012 * does not autonegotiate which is very common
1013 * in blade servers. Some blade servers use
1014 * IPMI for kerboard input and it's important
1015 * to minimize link disruptions. Autoneg. involves
1016 * exchanging base pages plus 3 next pages and
1017 * normally completes in about 120 msec.
1018 */
1019 bp->current_interval = SERDES_AN_TIMEOUT;
1020 bp->serdes_an_pending = 1;
1021 mod_timer(&bp->timer, jiffies + bp->current_interval);
1022 }
b6016b76
MC		 1023 }
1024
1025 return 0;
1026}
1027
1028#define ETHTOOL_ALL_FIBRE_SPEED \
1029 (ADVERTISED_1000baseT_Full)
1030
1031#define ETHTOOL_ALL_COPPER_SPEED \
1032 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1033 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1034 ADVERTISED_1000baseT_Full)
1035
1036#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1037 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1038
1039#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1040
1041static int
1042bnx2_setup_copper_phy(struct bnx2 *bp)
1043{
1044 u32 bmcr;
1045 u32 new_bmcr;
1046
1047 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1048
1049 if (bp->autoneg & AUTONEG_SPEED) {
1050 u32 adv_reg, adv1000_reg;
1051 u32 new_adv_reg = 0;
1052 u32 new_adv1000_reg = 0;
1053
1054 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1055 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1056 ADVERTISE_PAUSE_ASYM);
1057
1058 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1059 adv1000_reg &= PHY_ALL_1000_SPEED;
1060
1061 if (bp->advertising & ADVERTISED_10baseT_Half)
1062 new_adv_reg |= ADVERTISE_10HALF;
1063 if (bp->advertising & ADVERTISED_10baseT_Full)
1064 new_adv_reg |= ADVERTISE_10FULL;
1065 if (bp->advertising & ADVERTISED_100baseT_Half)
1066 new_adv_reg |= ADVERTISE_100HALF;
1067 if (bp->advertising & ADVERTISED_100baseT_Full)
1068 new_adv_reg |= ADVERTISE_100FULL;
1069 if (bp->advertising & ADVERTISED_1000baseT_Full)
1070 new_adv1000_reg |= ADVERTISE_1000FULL;
1071
1072 new_adv_reg |= ADVERTISE_CSMA;
1073
1074 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1075
1076 if ((adv1000_reg != new_adv1000_reg) ||
1077 (adv_reg != new_adv_reg) ||
1078 ((bmcr & BMCR_ANENABLE) == 0)) {
1079
1080 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1081 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1082 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1083 BMCR_ANENABLE);
1084 }
1085 else if (bp->link_up) {
1086 /* Flow ctrl may have changed from auto to forced */
1087 /* or vice-versa. */
1088
1089 bnx2_resolve_flow_ctrl(bp);
1090 bnx2_set_mac_link(bp);
1091 }
1092 return 0;
1093 }
1094
1095 new_bmcr = 0;
1096 if (bp->req_line_speed == SPEED_100) {
1097 new_bmcr |= BMCR_SPEED100;
1098 }
1099 if (bp->req_duplex == DUPLEX_FULL) {
1100 new_bmcr |= BMCR_FULLDPLX;
1101 }
1102 if (new_bmcr != bmcr) {
1103 u32 bmsr;
1104 int i = 0;
1105
1106 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1107 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1108
1109 if (bmsr & BMSR_LSTATUS) {
1110 /* Force link down */
1111 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1112 do {
1113 udelay(100);
1114 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1115 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1116 i++;
1117 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1118 }
1119
1120 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1121
1122 /* Normally, the new speed is setup after the link has
1123 * gone down and up again. In some cases, link will not go
1124 * down so we need to set up the new speed here.
1125 */
1126 if (bmsr & BMSR_LSTATUS) {
1127 bp->line_speed = bp->req_line_speed;
1128 bp->duplex = bp->req_duplex;
1129 bnx2_resolve_flow_ctrl(bp);
1130 bnx2_set_mac_link(bp);
1131 }
1132 }
1133 return 0;
1134}
1135
1136static int
1137bnx2_setup_phy(struct bnx2 *bp)
1138{
1139 if (bp->loopback == MAC_LOOPBACK)
1140 return 0;
1141
1142 if (bp->phy_flags & PHY_SERDES_FLAG) {
1143 return (bnx2_setup_serdes_phy(bp));
1144 }
1145 else {
1146 return (bnx2_setup_copper_phy(bp));
1147 }
1148}
1149
1150static int
5b0c76ad
MC		 1151bnx2_init_5708s_phy(struct bnx2 *bp)
1152{
1153 u32 val;
1154
1155 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1156 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1157 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1158
1159 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1160 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1161 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1162
1163 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1164 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1165 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1166
1167 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1168 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1169 val |= BCM5708S_UP1_2G5;
1170 bnx2_write_phy(bp, BCM5708S_UP1, val);
1171 }
1172
1173 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1174 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1175 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1176 /* increase tx signal amplitude */
1177 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1178 BCM5708S_BLK_ADDR_TX_MISC);
1179 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1180 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1181 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1182 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1183 }
1184
e3648b3d 1185 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1186 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1187
1188 if (val) {
1189 u32 is_backplane;
1190
e3648b3d 1191 is_backplane = REG_RD_IND(bp, bp->shmem_base +
5b0c76ad
MC		 1192 BNX2_SHARED_HW_CFG_CONFIG);
1193 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1194 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1195 BCM5708S_BLK_ADDR_TX_MISC);
1196 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1197 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1198 BCM5708S_BLK_ADDR_DIG);
1199 }
1200 }
1201 return 0;
1202}
1203
1204static int
1205bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76
MC		 1206{
1207 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1208
1209 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1210 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1211 }
1212
1213 if (bp->dev->mtu > 1500) {
1214 u32 val;
1215
1216 /* Set extended packet length bit */
1217 bnx2_write_phy(bp, 0x18, 0x7);
1218 bnx2_read_phy(bp, 0x18, &val);
1219 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1220
1221 bnx2_write_phy(bp, 0x1c, 0x6c00);
1222 bnx2_read_phy(bp, 0x1c, &val);
1223 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1224 }
1225 else {
1226 u32 val;
1227
1228 bnx2_write_phy(bp, 0x18, 0x7);
1229 bnx2_read_phy(bp, 0x18, &val);
1230 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1231
1232 bnx2_write_phy(bp, 0x1c, 0x6c00);
1233 bnx2_read_phy(bp, 0x1c, &val);
1234 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1235 }
1236
1237 return 0;
1238}
1239
1240static int
1241bnx2_init_copper_phy(struct bnx2 *bp)
1242{
5b0c76ad
MC		 1243 u32 val;
1244
b6016b76
MC		 1245 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1246
1247 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1248 bnx2_write_phy(bp, 0x18, 0x0c00);
1249 bnx2_write_phy(bp, 0x17, 0x000a);
1250 bnx2_write_phy(bp, 0x15, 0x310b);
1251 bnx2_write_phy(bp, 0x17, 0x201f);
1252 bnx2_write_phy(bp, 0x15, 0x9506);
1253 bnx2_write_phy(bp, 0x17, 0x401f);
1254 bnx2_write_phy(bp, 0x15, 0x14e2);
1255 bnx2_write_phy(bp, 0x18, 0x0400);
1256 }
1257
1258 if (bp->dev->mtu > 1500) {
b6016b76
MC		 1259 /* Set extended packet length bit */
1260 bnx2_write_phy(bp, 0x18, 0x7);
1261 bnx2_read_phy(bp, 0x18, &val);
1262 bnx2_write_phy(bp, 0x18, val | 0x4000);
1263
1264 bnx2_read_phy(bp, 0x10, &val);
1265 bnx2_write_phy(bp, 0x10, val | 0x1);
1266 }
1267 else {
b6016b76
MC		 1268 bnx2_write_phy(bp, 0x18, 0x7);
1269 bnx2_read_phy(bp, 0x18, &val);
1270 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1271
1272 bnx2_read_phy(bp, 0x10, &val);
1273 bnx2_write_phy(bp, 0x10, val & ~0x1);
1274 }
1275
5b0c76ad
MC		 1276 /* ethernet@wirespeed */
1277 bnx2_write_phy(bp, 0x18, 0x7007);
1278 bnx2_read_phy(bp, 0x18, &val);
1279 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 1280 return 0;
1281}
1282
1283
1284static int
1285bnx2_init_phy(struct bnx2 *bp)
1286{
1287 u32 val;
1288 int rc = 0;
1289
1290 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1291 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1292
1293 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1294
1295 bnx2_reset_phy(bp);
1296
1297 bnx2_read_phy(bp, MII_PHYSID1, &val);
1298 bp->phy_id = val << 16;
1299 bnx2_read_phy(bp, MII_PHYSID2, &val);
1300 bp->phy_id |= val & 0xffff;
1301
1302 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 1303 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1304 rc = bnx2_init_5706s_phy(bp);
1305 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1306 rc = bnx2_init_5708s_phy(bp);
b6016b76
MC		 1307 }
1308 else {
1309 rc = bnx2_init_copper_phy(bp);
1310 }
1311
1312 bnx2_setup_phy(bp);
1313
1314 return rc;
1315}
1316
1317static int
1318bnx2_set_mac_loopback(struct bnx2 *bp)
1319{
1320 u32 mac_mode;
1321
1322 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1323 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1324 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1325 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1326 bp->link_up = 1;
1327 return 0;
1328}
1329
1330static int
b090ae2b 1331bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 1332{
1333 int i;
1334 u32 val;
1335
b6016b76
MC		 1336 bp->fw_wr_seq++;
1337 msg_data |= bp->fw_wr_seq;
1338
e3648b3d 1339 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76
MC		 1340
1341 /* wait for an acknowledgement. */
b090ae2b
MC		 1342 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1343 msleep(10);
b6016b76 1344
e3648b3d 1345 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
b6016b76
MC		 1346
1347 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1348 break;
1349 }
b090ae2b
MC		 1350 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1351 return 0;
b6016b76
MC		 1352
1353 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 1354 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1355 if (!silent)
1356 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1357 "%x\n", msg_data);
b6016b76
MC		 1358
1359 msg_data &= ~BNX2_DRV_MSG_CODE;
1360 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1361
e3648b3d 1362 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76 1363
b6016b76
MC		 1364 return -EBUSY;
1365 }
1366
b090ae2b
MC		 1367 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1368 return -EIO;
1369
b6016b76
MC		 1370 return 0;
1371}
1372
1373static void
1374bnx2_init_context(struct bnx2 *bp)
1375{
1376 u32 vcid;
1377
1378 vcid = 96;
1379 while (vcid) {
1380 u32 vcid_addr, pcid_addr, offset;
1381
1382 vcid--;
1383
1384 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1385 u32 new_vcid;
1386
1387 vcid_addr = GET_PCID_ADDR(vcid);
1388 if (vcid & 0x8) {
1389 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1390 }
1391 else {
1392 new_vcid = vcid;
1393 }
1394 pcid_addr = GET_PCID_ADDR(new_vcid);
1395 }
1396 else {
1397 vcid_addr = GET_CID_ADDR(vcid);
1398 pcid_addr = vcid_addr;
1399 }
1400
1401 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1402 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1403
1404 /* Zero out the context. */
1405 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1406 CTX_WR(bp, 0x00, offset, 0);
1407 }
1408
1409 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1410 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1411 }
1412}
1413
1414static int
1415bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1416{
1417 u16 *good_mbuf;
1418 u32 good_mbuf_cnt;
1419 u32 val;
1420
1421 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1422 if (good_mbuf == NULL) {
1423 printk(KERN_ERR PFX "Failed to allocate memory in "
1424 "bnx2_alloc_bad_rbuf\n");
1425 return -ENOMEM;
1426 }
1427
1428 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1429 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1430
1431 good_mbuf_cnt = 0;
1432
1433 /* Allocate a bunch of mbufs and save the good ones in an array. */
1434 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1435 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1436 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1437
1438 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1439
1440 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1441
1442 /* The addresses with Bit 9 set are bad memory blocks. */
1443 if (!(val & (1 << 9))) {
1444 good_mbuf[good_mbuf_cnt] = (u16) val;
1445 good_mbuf_cnt++;
1446 }
1447
1448 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1449 }
1450
1451 /* Free the good ones back to the mbuf pool thus discarding
1452 * all the bad ones. */
1453 while (good_mbuf_cnt) {
1454 good_mbuf_cnt--;
1455
1456 val = good_mbuf[good_mbuf_cnt];
1457 val = (val << 9) | val | 1;
1458
1459 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1460 }
1461 kfree(good_mbuf);
1462 return 0;
1463}
1464
1465static void
1466bnx2_set_mac_addr(struct bnx2 *bp)
1467{
1468 u32 val;
1469 u8 *mac_addr = bp->dev->dev_addr;
1470
1471 val = (mac_addr[0] << 8) | mac_addr[1];
1472
1473 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1474
1475 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1476 (mac_addr[4] << 8) | mac_addr[5];
1477
1478 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1479}
1480
1481static inline int
1482bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1483{
1484 struct sk_buff *skb;
1485 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1486 dma_addr_t mapping;
1487 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1488 unsigned long align;
1489
1490 skb = dev_alloc_skb(bp->rx_buf_size);
1491 if (skb == NULL) {
1492 return -ENOMEM;
1493 }
1494
1495 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1496 skb_reserve(skb, 8 - align);
1497 }
1498
1499 skb->dev = bp->dev;
1500 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1501 PCI_DMA_FROMDEVICE);
1502
1503 rx_buf->skb = skb;
1504 pci_unmap_addr_set(rx_buf, mapping, mapping);
1505
1506 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1507 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1508
1509 bp->rx_prod_bseq += bp->rx_buf_use_size;
1510
1511 return 0;
1512}
1513
1514static void
1515bnx2_phy_int(struct bnx2 *bp)
1516{
1517 u32 new_link_state, old_link_state;
1518
1519 new_link_state = bp->status_blk->status_attn_bits &
1520 STATUS_ATTN_BITS_LINK_STATE;
1521 old_link_state = bp->status_blk->status_attn_bits_ack &
1522 STATUS_ATTN_BITS_LINK_STATE;
1523 if (new_link_state != old_link_state) {
1524 if (new_link_state) {
1525 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1526 STATUS_ATTN_BITS_LINK_STATE);
1527 }
1528 else {
1529 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1530 STATUS_ATTN_BITS_LINK_STATE);
1531 }
1532 bnx2_set_link(bp);
1533 }
1534}
1535
1536static void
1537bnx2_tx_int(struct bnx2 *bp)
1538{
f4e418f7 1539 struct status_block *sblk = bp->status_blk;
b6016b76
MC		 1540 u16 hw_cons, sw_cons, sw_ring_cons;
1541 int tx_free_bd = 0;
1542
f4e418f7 1543 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
b6016b76
MC		 1544 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1545 hw_cons++;
1546 }
1547 sw_cons = bp->tx_cons;
1548
1549 while (sw_cons != hw_cons) {
1550 struct sw_bd *tx_buf;
1551 struct sk_buff *skb;
1552 int i, last;
1553
1554 sw_ring_cons = TX_RING_IDX(sw_cons);
1555
1556 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1557 skb = tx_buf->skb;
1558#ifdef BCM_TSO
1559 /* partial BD completions possible with TSO packets */
1560 if (skb_shinfo(skb)->tso_size) {
1561 u16 last_idx, last_ring_idx;
1562
1563 last_idx = sw_cons +
1564 skb_shinfo(skb)->nr_frags + 1;
1565 last_ring_idx = sw_ring_cons +
1566 skb_shinfo(skb)->nr_frags + 1;
1567 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1568 last_idx++;
1569 }
1570 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1571 break;
1572 }
1573 }
1574#endif
1575 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1576 skb_headlen(skb), PCI_DMA_TODEVICE);
1577
1578 tx_buf->skb = NULL;
1579 last = skb_shinfo(skb)->nr_frags;
1580
1581 for (i = 0; i < last; i++) {
1582 sw_cons = NEXT_TX_BD(sw_cons);
1583
1584 pci_unmap_page(bp->pdev,
1585 pci_unmap_addr(
1586 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1587 mapping),
1588 skb_shinfo(skb)->frags[i].size,
1589 PCI_DMA_TODEVICE);
1590 }
1591
1592 sw_cons = NEXT_TX_BD(sw_cons);
1593
1594 tx_free_bd += last + 1;
1595
1596 dev_kfree_skb_irq(skb);
1597
f4e418f7
MC		 1598 hw_cons = bp->hw_tx_cons =
1599 sblk->status_tx_quick_consumer_index0;
1600
b6016b76
MC		 1601 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1602 hw_cons++;
1603 }
1604 }
1605
e89bbf10 1606 bp->tx_cons = sw_cons;
b6016b76
MC		 1607
1608 if (unlikely(netif_queue_stopped(bp->dev))) {
c770a65c 1609 spin_lock(&bp->tx_lock);
b6016b76 1610 if ((netif_queue_stopped(bp->dev)) &&
e89bbf10 1611 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
b6016b76
MC		 1612
1613 netif_wake_queue(bp->dev);
1614 }
c770a65c 1615 spin_unlock(&bp->tx_lock);
b6016b76 1616 }
b6016b76
MC		 1617}
1618
1619static inline void
1620bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1621 u16 cons, u16 prod)
1622{
1623 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1624 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1625 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1626 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1627
1628 pci_dma_sync_single_for_device(bp->pdev,
1629 pci_unmap_addr(cons_rx_buf, mapping),
1630 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1631
1632 prod_rx_buf->skb = cons_rx_buf->skb;
1633 pci_unmap_addr_set(prod_rx_buf, mapping,
1634 pci_unmap_addr(cons_rx_buf, mapping));
1635
1636 memcpy(prod_bd, cons_bd, 8);
1637
1638 bp->rx_prod_bseq += bp->rx_buf_use_size;
1639
1640}
1641
1642static int
1643bnx2_rx_int(struct bnx2 *bp, int budget)
1644{
f4e418f7 1645 struct status_block *sblk = bp->status_blk;
b6016b76
MC		 1646 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1647 struct l2_fhdr *rx_hdr;
1648 int rx_pkt = 0;
1649
f4e418f7 1650 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
b6016b76
MC		 1651 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1652 hw_cons++;
1653 }
1654 sw_cons = bp->rx_cons;
1655 sw_prod = bp->rx_prod;
1656
1657 /* Memory barrier necessary as speculative reads of the rx
1658 * buffer can be ahead of the index in the status block
1659 */
1660 rmb();
1661 while (sw_cons != hw_cons) {
1662 unsigned int len;
1663 u16 status;
1664 struct sw_bd *rx_buf;
1665 struct sk_buff *skb;
1666
1667 sw_ring_cons = RX_RING_IDX(sw_cons);
1668 sw_ring_prod = RX_RING_IDX(sw_prod);
1669
1670 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1671 skb = rx_buf->skb;
1672 pci_dma_sync_single_for_cpu(bp->pdev,
1673 pci_unmap_addr(rx_buf, mapping),
1674 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1675
1676 rx_hdr = (struct l2_fhdr *) skb->data;
1677 len = rx_hdr->l2_fhdr_pkt_len - 4;
1678
1679 if (rx_hdr->l2_fhdr_errors &
1680 (L2_FHDR_ERRORS_BAD_CRC |
1681 L2_FHDR_ERRORS_PHY_DECODE |
1682 L2_FHDR_ERRORS_ALIGNMENT |
1683 L2_FHDR_ERRORS_TOO_SHORT |
1684 L2_FHDR_ERRORS_GIANT_FRAME)) {
1685
1686 goto reuse_rx;
1687 }
1688
1689 /* Since we don't have a jumbo ring, copy small packets
1690 * if mtu > 1500
1691 */
1692 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1693 struct sk_buff *new_skb;
1694
1695 new_skb = dev_alloc_skb(len + 2);
1696 if (new_skb == NULL)
1697 goto reuse_rx;
1698
1699 /* aligned copy */
1700 memcpy(new_skb->data,
1701 skb->data + bp->rx_offset - 2,
1702 len + 2);
1703
1704 skb_reserve(new_skb, 2);
1705 skb_put(new_skb, len);
1706 new_skb->dev = bp->dev;
1707
1708 bnx2_reuse_rx_skb(bp, skb,
1709 sw_ring_cons, sw_ring_prod);
1710
1711 skb = new_skb;
1712 }
1713 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1714 pci_unmap_single(bp->pdev,
1715 pci_unmap_addr(rx_buf, mapping),
1716 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1717
1718 skb_reserve(skb, bp->rx_offset);
1719 skb_put(skb, len);
1720 }
1721 else {
1722reuse_rx:
1723 bnx2_reuse_rx_skb(bp, skb,
1724 sw_ring_cons, sw_ring_prod);
1725 goto next_rx;
1726 }
1727
1728 skb->protocol = eth_type_trans(skb, bp->dev);
1729
1730 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1731 (htons(skb->protocol) != 0x8100)) {
1732
1733 dev_kfree_skb_irq(skb);
1734 goto next_rx;
1735
1736 }
1737
1738 status = rx_hdr->l2_fhdr_status;
1739 skb->ip_summed = CHECKSUM_NONE;
1740 if (bp->rx_csum &&
1741 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1742 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1743
1744 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1745
1746 if (cksum == 0xffff)
1747 skb->ip_summed = CHECKSUM_UNNECESSARY;
1748 }
1749
1750#ifdef BCM_VLAN
1751 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1752 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1753 rx_hdr->l2_fhdr_vlan_tag);
1754 }
1755 else
1756#endif
1757 netif_receive_skb(skb);
1758
1759 bp->dev->last_rx = jiffies;
1760 rx_pkt++;
1761
1762next_rx:
1763 rx_buf->skb = NULL;
1764
1765 sw_cons = NEXT_RX_BD(sw_cons);
1766 sw_prod = NEXT_RX_BD(sw_prod);
1767
1768 if ((rx_pkt == budget))
1769 break;
f4e418f7
MC		 1770
1771 /* Refresh hw_cons to see if there is new work */
1772 if (sw_cons == hw_cons) {
1773 hw_cons = bp->hw_rx_cons =
1774 sblk->status_rx_quick_consumer_index0;
1775 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1776 hw_cons++;
1777 rmb();
1778 }
b6016b76
MC		 1779 }
1780 bp->rx_cons = sw_cons;
1781 bp->rx_prod = sw_prod;
1782
1783 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1784
1785 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1786
1787 mmiowb();
1788
1789 return rx_pkt;
1790
1791}
1792
1793/* MSI ISR - The only difference between this and the INTx ISR
1794 * is that the MSI interrupt is always serviced.
1795 */
1796static irqreturn_t
1797bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1798{
1799 struct net_device *dev = dev_instance;
1800 struct bnx2 *bp = dev->priv;
1801
c921e4c4 1802 prefetch(bp->status_blk);
b6016b76
MC		 1803 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1804 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1805 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1806
1807 /* Return here if interrupt is disabled. */
73eef4cd
MC		 1808 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1809 return IRQ_HANDLED;
b6016b76 1810
73eef4cd 1811 netif_rx_schedule(dev);
b6016b76 1812
73eef4cd 1813 return IRQ_HANDLED;
b6016b76
MC		 1814}
1815
1816static irqreturn_t
1817bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1818{
1819 struct net_device *dev = dev_instance;
1820 struct bnx2 *bp = dev->priv;
1821
1822 /* When using INTx, it is possible for the interrupt to arrive
1823 * at the CPU before the status block posted prior to the
1824 * interrupt. Reading a register will flush the status block.
1825 * When using MSI, the MSI message will always complete after
1826 * the status block write.
1827 */
c921e4c4 1828 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
b6016b76
MC		 1829 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1830 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 1831 return IRQ_NONE;
b6016b76
MC		 1832
1833 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1834 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1835 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1836
1837 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 1838 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1839 return IRQ_HANDLED;
b6016b76 1840
73eef4cd 1841 netif_rx_schedule(dev);
b6016b76 1842
73eef4cd 1843 return IRQ_HANDLED;
b6016b76
MC		 1844}
1845
f4e418f7
MC		 1846static inline int
1847bnx2_has_work(struct bnx2 *bp)
1848{
1849 struct status_block *sblk = bp->status_blk;
1850
1851 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1852 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1853 return 1;
1854
1855 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1856 bp->link_up)
1857 return 1;
1858
1859 return 0;
1860}
1861
b6016b76
MC		 1862static int
1863bnx2_poll(struct net_device *dev, int *budget)
1864{
1865 struct bnx2 *bp = dev->priv;
b6016b76 1866
b6016b76
MC		 1867 if ((bp->status_blk->status_attn_bits &
1868 STATUS_ATTN_BITS_LINK_STATE) !=
1869 (bp->status_blk->status_attn_bits_ack &
1870 STATUS_ATTN_BITS_LINK_STATE)) {
1871
c770a65c 1872 spin_lock(&bp->phy_lock);
b6016b76 1873 bnx2_phy_int(bp);
c770a65c 1874 spin_unlock(&bp->phy_lock);
b6016b76
MC		 1875 }
1876
f4e418f7 1877 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
b6016b76 1878 bnx2_tx_int(bp);
b6016b76 1879
f4e418f7 1880 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
b6016b76
MC		 1881 int orig_budget = *budget;
1882 int work_done;
1883
1884 if (orig_budget > dev->quota)
1885 orig_budget = dev->quota;
1886
1887 work_done = bnx2_rx_int(bp, orig_budget);
1888 *budget -= work_done;
1889 dev->quota -= work_done;
b6016b76
MC		 1890 }
1891
f4e418f7
MC		 1892 bp->last_status_idx = bp->status_blk->status_idx;
1893 rmb();
1894
1895 if (!bnx2_has_work(bp)) {
b6016b76
MC		 1896 netif_rx_complete(dev);
1897 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1898 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1899 bp->last_status_idx);
1900 return 0;
1901 }
1902
1903 return 1;
1904}
1905
1906/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1907 * from set_multicast.
1908 */
1909static void
1910bnx2_set_rx_mode(struct net_device *dev)
1911{
1912 struct bnx2 *bp = dev->priv;
1913 u32 rx_mode, sort_mode;
1914 int i;
b6016b76 1915
c770a65c 1916 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1917
1918 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1919 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1920 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1921#ifdef BCM_VLAN
e29054f9 1922 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
b6016b76 1923 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 1924#else
e29054f9
MC		 1925 if (!(bp->flags & ASF_ENABLE_FLAG))
1926 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 1927#endif
1928 if (dev->flags & IFF_PROMISC) {
1929 /* Promiscuous mode. */
1930 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1931 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1932 }
1933 else if (dev->flags & IFF_ALLMULTI) {
1934 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1935 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1936 0xffffffff);
1937 }
1938 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1939 }
1940 else {
1941 /* Accept one or more multicast(s). */
1942 struct dev_mc_list *mclist;
1943 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1944 u32 regidx;
1945 u32 bit;
1946 u32 crc;
1947
1948 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1949
1950 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1951 i++, mclist = mclist->next) {
1952
1953 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1954 bit = crc & 0xff;
1955 regidx = (bit & 0xe0) >> 5;
1956 bit &= 0x1f;
1957 mc_filter[regidx] |= (1 << bit);
1958 }
1959
1960 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1961 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1962 mc_filter[i]);
1963 }
1964
1965 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1966 }
1967
1968 if (rx_mode != bp->rx_mode) {
1969 bp->rx_mode = rx_mode;
1970 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1971 }
1972
1973 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1974 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1975 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1976
c770a65c 1977 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 1978}
1979
1980static void
1981load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1982 u32 rv2p_proc)
1983{
1984 int i;
1985 u32 val;
1986
1987
1988 for (i = 0; i < rv2p_code_len; i += 8) {
1989 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1990 rv2p_code++;
1991 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1992 rv2p_code++;
1993
1994 if (rv2p_proc == RV2P_PROC1) {
1995 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1996 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1997 }
1998 else {
1999 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2000 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2001 }
2002 }
2003
2004 /* Reset the processor, un-stall is done later. */
2005 if (rv2p_proc == RV2P_PROC1) {
2006 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2007 }
2008 else {
2009 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2010 }
2011}
2012
2013static void
2014load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2015{
2016 u32 offset;
2017 u32 val;
2018
2019 /* Halt the CPU. */
2020 val = REG_RD_IND(bp, cpu_reg->mode);
2021 val |= cpu_reg->mode_value_halt;
2022 REG_WR_IND(bp, cpu_reg->mode, val);
2023 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2024
2025 /* Load the Text area. */
2026 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2027 if (fw->text) {
2028 int j;
2029
2030 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2031 REG_WR_IND(bp, offset, fw->text[j]);
2032 }
2033 }
2034
2035 /* Load the Data area. */
2036 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2037 if (fw->data) {
2038 int j;
2039
2040 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2041 REG_WR_IND(bp, offset, fw->data[j]);
2042 }
2043 }
2044
2045 /* Load the SBSS area. */
2046 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2047 if (fw->sbss) {
2048 int j;
2049
2050 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2051 REG_WR_IND(bp, offset, fw->sbss[j]);
2052 }
2053 }
2054
2055 /* Load the BSS area. */
2056 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2057 if (fw->bss) {
2058 int j;
2059
2060 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2061 REG_WR_IND(bp, offset, fw->bss[j]);
2062 }
2063 }
2064
2065 /* Load the Read-Only area. */
2066 offset = cpu_reg->spad_base +
2067 (fw->rodata_addr - cpu_reg->mips_view_base);
2068 if (fw->rodata) {
2069 int j;
2070
2071 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2072 REG_WR_IND(bp, offset, fw->rodata[j]);
2073 }
2074 }
2075
2076 /* Clear the pre-fetch instruction. */
2077 REG_WR_IND(bp, cpu_reg->inst, 0);
2078 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2079
2080 /* Start the CPU. */
2081 val = REG_RD_IND(bp, cpu_reg->mode);
2082 val &= ~cpu_reg->mode_value_halt;
2083 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2084 REG_WR_IND(bp, cpu_reg->mode, val);
2085}
2086
2087static void
2088bnx2_init_cpus(struct bnx2 *bp)
2089{
2090 struct cpu_reg cpu_reg;
2091 struct fw_info fw;
2092
2093 /* Initialize the RV2P processor. */
2094 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2095 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2096
2097 /* Initialize the RX Processor. */
2098 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2099 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2100 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2101 cpu_reg.state = BNX2_RXP_CPU_STATE;
2102 cpu_reg.state_value_clear = 0xffffff;
2103 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2104 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2105 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2106 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2107 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2108 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2109 cpu_reg.mips_view_base = 0x8000000;
2110
2111 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2112 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2113 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2114 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2115
2116 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2117 fw.text_len = bnx2_RXP_b06FwTextLen;
2118 fw.text_index = 0;
2119 fw.text = bnx2_RXP_b06FwText;
2120
2121 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2122 fw.data_len = bnx2_RXP_b06FwDataLen;
2123 fw.data_index = 0;
2124 fw.data = bnx2_RXP_b06FwData;
2125
2126 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2127 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2128 fw.sbss_index = 0;
2129 fw.sbss = bnx2_RXP_b06FwSbss;
2130
2131 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2132 fw.bss_len = bnx2_RXP_b06FwBssLen;
2133 fw.bss_index = 0;
2134 fw.bss = bnx2_RXP_b06FwBss;
2135
2136 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2137 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2138 fw.rodata_index = 0;
2139 fw.rodata = bnx2_RXP_b06FwRodata;
2140
2141 load_cpu_fw(bp, &cpu_reg, &fw);
2142
2143 /* Initialize the TX Processor. */
2144 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2145 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2146 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2147 cpu_reg.state = BNX2_TXP_CPU_STATE;
2148 cpu_reg.state_value_clear = 0xffffff;
2149 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2150 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2151 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2152 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2153 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2154 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2155 cpu_reg.mips_view_base = 0x8000000;
2156
2157 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2158 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2159 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2160 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2161
2162 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2163 fw.text_len = bnx2_TXP_b06FwTextLen;
2164 fw.text_index = 0;
2165 fw.text = bnx2_TXP_b06FwText;
2166
2167 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2168 fw.data_len = bnx2_TXP_b06FwDataLen;
2169 fw.data_index = 0;
2170 fw.data = bnx2_TXP_b06FwData;
2171
2172 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2173 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2174 fw.sbss_index = 0;
2175 fw.sbss = bnx2_TXP_b06FwSbss;
2176
2177 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2178 fw.bss_len = bnx2_TXP_b06FwBssLen;
2179 fw.bss_index = 0;
2180 fw.bss = bnx2_TXP_b06FwBss;
2181
2182 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2183 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2184 fw.rodata_index = 0;
2185 fw.rodata = bnx2_TXP_b06FwRodata;
2186
2187 load_cpu_fw(bp, &cpu_reg, &fw);
2188
2189 /* Initialize the TX Patch-up Processor. */
2190 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2191 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2192 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2193 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2194 cpu_reg.state_value_clear = 0xffffff;
2195 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2196 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2197 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2198 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2199 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2200 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2201 cpu_reg.mips_view_base = 0x8000000;
2202
2203 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2204 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2205 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2206 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2207
2208 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2209 fw.text_len = bnx2_TPAT_b06FwTextLen;
2210 fw.text_index = 0;
2211 fw.text = bnx2_TPAT_b06FwText;
2212
2213 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2214 fw.data_len = bnx2_TPAT_b06FwDataLen;
2215 fw.data_index = 0;
2216 fw.data = bnx2_TPAT_b06FwData;
2217
2218 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2219 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2220 fw.sbss_index = 0;
2221 fw.sbss = bnx2_TPAT_b06FwSbss;
2222
2223 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2224 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2225 fw.bss_index = 0;
2226 fw.bss = bnx2_TPAT_b06FwBss;
2227
2228 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2229 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2230 fw.rodata_index = 0;
2231 fw.rodata = bnx2_TPAT_b06FwRodata;
2232
2233 load_cpu_fw(bp, &cpu_reg, &fw);
2234
2235 /* Initialize the Completion Processor. */
2236 cpu_reg.mode = BNX2_COM_CPU_MODE;
2237 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2238 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2239 cpu_reg.state = BNX2_COM_CPU_STATE;
2240 cpu_reg.state_value_clear = 0xffffff;
2241 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2242 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2243 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2244 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2245 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2246 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2247 cpu_reg.mips_view_base = 0x8000000;
2248
2249 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2250 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2251 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2252 fw.start_addr = bnx2_COM_b06FwStartAddr;
2253
2254 fw.text_addr = bnx2_COM_b06FwTextAddr;
2255 fw.text_len = bnx2_COM_b06FwTextLen;
2256 fw.text_index = 0;
2257 fw.text = bnx2_COM_b06FwText;
2258
2259 fw.data_addr = bnx2_COM_b06FwDataAddr;
2260 fw.data_len = bnx2_COM_b06FwDataLen;
2261 fw.data_index = 0;
2262 fw.data = bnx2_COM_b06FwData;
2263
2264 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2265 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2266 fw.sbss_index = 0;
2267 fw.sbss = bnx2_COM_b06FwSbss;
2268
2269 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2270 fw.bss_len = bnx2_COM_b06FwBssLen;
2271 fw.bss_index = 0;
2272 fw.bss = bnx2_COM_b06FwBss;
2273
2274 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2275 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2276 fw.rodata_index = 0;
2277 fw.rodata = bnx2_COM_b06FwRodata;
2278
2279 load_cpu_fw(bp, &cpu_reg, &fw);
2280
2281}
2282
2283static int
829ca9a3 2284bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 2285{
2286 u16 pmcsr;
2287
2288 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2289
2290 switch (state) {
829ca9a3 2291 case PCI_D0: {
b6016b76
MC		 2292 u32 val;
2293
2294 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2295 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2296 PCI_PM_CTRL_PME_STATUS);
2297
2298 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2299 /* delay required during transition out of D3hot */
2300 msleep(20);
2301
2302 val = REG_RD(bp, BNX2_EMAC_MODE);
2303 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2304 val &= ~BNX2_EMAC_MODE_MPKT;
2305 REG_WR(bp, BNX2_EMAC_MODE, val);
2306
2307 val = REG_RD(bp, BNX2_RPM_CONFIG);
2308 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2309 REG_WR(bp, BNX2_RPM_CONFIG, val);
2310 break;
2311 }
829ca9a3 2312 case PCI_D3hot: {
b6016b76
MC		 2313 int i;
2314 u32 val, wol_msg;
2315
2316 if (bp->wol) {
2317 u32 advertising;
2318 u8 autoneg;
2319
2320 autoneg = bp->autoneg;
2321 advertising = bp->advertising;
2322
2323 bp->autoneg = AUTONEG_SPEED;
2324 bp->advertising = ADVERTISED_10baseT_Half |
2325 ADVERTISED_10baseT_Full |
2326 ADVERTISED_100baseT_Half |
2327 ADVERTISED_100baseT_Full |
2328 ADVERTISED_Autoneg;
2329
2330 bnx2_setup_copper_phy(bp);
2331
2332 bp->autoneg = autoneg;
2333 bp->advertising = advertising;
2334
2335 bnx2_set_mac_addr(bp);
2336
2337 val = REG_RD(bp, BNX2_EMAC_MODE);
2338
2339 /* Enable port mode. */
2340 val &= ~BNX2_EMAC_MODE_PORT;
2341 val |= BNX2_EMAC_MODE_PORT_MII |
2342 BNX2_EMAC_MODE_MPKT_RCVD |
2343 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76
MC		 2344 BNX2_EMAC_MODE_MPKT;
2345
2346 REG_WR(bp, BNX2_EMAC_MODE, val);
2347
2348 /* receive all multicast */
2349 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2350 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2351 0xffffffff);
2352 }
2353 REG_WR(bp, BNX2_EMAC_RX_MODE,
2354 BNX2_EMAC_RX_MODE_SORT_MODE);
2355
2356 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2357 BNX2_RPM_SORT_USER0_MC_EN;
2358 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2359 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2360 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2361 BNX2_RPM_SORT_USER0_ENA);
2362
2363 /* Need to enable EMAC and RPM for WOL. */
2364 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2365 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2366 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2367 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2368
2369 val = REG_RD(bp, BNX2_RPM_CONFIG);
2370 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2371 REG_WR(bp, BNX2_RPM_CONFIG, val);
2372
2373 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2374 }
2375 else {
2376 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2377 }
2378
dda1e390
MC		 2379 if (!(bp->flags & NO_WOL_FLAG))
2380 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 2381
2382 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2383 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2384 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2385
2386 if (bp->wol)
2387 pmcsr |= 3;
2388 }
2389 else {
2390 pmcsr |= 3;
2391 }
2392 if (bp->wol) {
2393 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2394 }
2395 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2396 pmcsr);
2397
2398 /* No more memory access after this point until
2399 * device is brought back to D0.
2400 */
2401 udelay(50);
2402 break;
2403 }
2404 default:
2405 return -EINVAL;
2406 }
2407 return 0;
2408}
2409
2410static int
2411bnx2_acquire_nvram_lock(struct bnx2 *bp)
2412{
2413 u32 val;
2414 int j;
2415
2416 /* Request access to the flash interface. */
2417 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2418 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2419 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2420 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2421 break;
2422
2423 udelay(5);
2424 }
2425
2426 if (j >= NVRAM_TIMEOUT_COUNT)
2427 return -EBUSY;
2428
2429 return 0;
2430}
2431
2432static int
2433bnx2_release_nvram_lock(struct bnx2 *bp)
2434{
2435 int j;
2436 u32 val;
2437
2438 /* Relinquish nvram interface. */
2439 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2440
2441 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2442 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2443 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2444 break;
2445
2446 udelay(5);
2447 }
2448
2449 if (j >= NVRAM_TIMEOUT_COUNT)
2450 return -EBUSY;
2451
2452 return 0;
2453}
2454
2455
2456static int
2457bnx2_enable_nvram_write(struct bnx2 *bp)
2458{
2459 u32 val;
2460
2461 val = REG_RD(bp, BNX2_MISC_CFG);
2462 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2463
2464 if (!bp->flash_info->buffered) {
2465 int j;
2466
2467 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2468 REG_WR(bp, BNX2_NVM_COMMAND,
2469 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2470
2471 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2472 udelay(5);
2473
2474 val = REG_RD(bp, BNX2_NVM_COMMAND);
2475 if (val & BNX2_NVM_COMMAND_DONE)
2476 break;
2477 }
2478
2479 if (j >= NVRAM_TIMEOUT_COUNT)
2480 return -EBUSY;
2481 }
2482 return 0;
2483}
2484
2485static void
2486bnx2_disable_nvram_write(struct bnx2 *bp)
2487{
2488 u32 val;
2489
2490 val = REG_RD(bp, BNX2_MISC_CFG);
2491 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2492}
2493
2494
2495static void
2496bnx2_enable_nvram_access(struct bnx2 *bp)
2497{
2498 u32 val;
2499
2500 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2501 /* Enable both bits, even on read. */
2502 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2503 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2504}
2505
2506static void
2507bnx2_disable_nvram_access(struct bnx2 *bp)
2508{
2509 u32 val;
2510
2511 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2512 /* Disable both bits, even after read. */
2513 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2514 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2515 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2516}
2517
2518static int
2519bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2520{
2521 u32 cmd;
2522 int j;
2523
2524 if (bp->flash_info->buffered)
2525 /* Buffered flash, no erase needed */
2526 return 0;
2527
2528 /* Build an erase command */
2529 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2530 BNX2_NVM_COMMAND_DOIT;
2531
2532 /* Need to clear DONE bit separately. */
2533 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2534
2535 /* Address of the NVRAM to read from. */
2536 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2537
2538 /* Issue an erase command. */
2539 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2540
2541 /* Wait for completion. */
2542 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2543 u32 val;
2544
2545 udelay(5);
2546
2547 val = REG_RD(bp, BNX2_NVM_COMMAND);
2548 if (val & BNX2_NVM_COMMAND_DONE)
2549 break;
2550 }
2551
2552 if (j >= NVRAM_TIMEOUT_COUNT)
2553 return -EBUSY;
2554
2555 return 0;
2556}
2557
2558static int
2559bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2560{
2561 u32 cmd;
2562 int j;
2563
2564 /* Build the command word. */
2565 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2566
2567 /* Calculate an offset of a buffered flash. */
2568 if (bp->flash_info->buffered) {
2569 offset = ((offset / bp->flash_info->page_size) <<
2570 bp->flash_info->page_bits) +
2571 (offset % bp->flash_info->page_size);
2572 }
2573
2574 /* Need to clear DONE bit separately. */
2575 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2576
2577 /* Address of the NVRAM to read from. */
2578 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2579
2580 /* Issue a read command. */
2581 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2582
2583 /* Wait for completion. */
2584 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2585 u32 val;
2586
2587 udelay(5);
2588
2589 val = REG_RD(bp, BNX2_NVM_COMMAND);
2590 if (val & BNX2_NVM_COMMAND_DONE) {
2591 val = REG_RD(bp, BNX2_NVM_READ);
2592
2593 val = be32_to_cpu(val);
2594 memcpy(ret_val, &val, 4);
2595 break;
2596 }
2597 }
2598 if (j >= NVRAM_TIMEOUT_COUNT)
2599 return -EBUSY;
2600
2601 return 0;
2602}
2603
2604
2605static int
2606bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2607{
2608 u32 cmd, val32;
2609 int j;
2610
2611 /* Build the command word. */
2612 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2613
2614 /* Calculate an offset of a buffered flash. */
2615 if (bp->flash_info->buffered) {
2616 offset = ((offset / bp->flash_info->page_size) <<
2617 bp->flash_info->page_bits) +
2618 (offset % bp->flash_info->page_size);
2619 }
2620
2621 /* Need to clear DONE bit separately. */
2622 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2623
2624 memcpy(&val32, val, 4);
2625 val32 = cpu_to_be32(val32);
2626
2627 /* Write the data. */
2628 REG_WR(bp, BNX2_NVM_WRITE, val32);
2629
2630 /* Address of the NVRAM to write to. */
2631 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2632
2633 /* Issue the write command. */
2634 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2635
2636 /* Wait for completion. */
2637 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2638 udelay(5);
2639
2640 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2641 break;
2642 }
2643 if (j >= NVRAM_TIMEOUT_COUNT)
2644 return -EBUSY;
2645
2646 return 0;
2647}
2648
2649static int
2650bnx2_init_nvram(struct bnx2 *bp)
2651{
2652 u32 val;
2653 int j, entry_count, rc;
2654 struct flash_spec *flash;
2655
2656 /* Determine the selected interface. */
2657 val = REG_RD(bp, BNX2_NVM_CFG1);
2658
2659 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2660
2661 rc = 0;
2662 if (val & 0x40000000) {
2663
2664 /* Flash interface has been reconfigured */
2665 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 2666 j++, flash++) {
2667 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2668 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 2669 bp->flash_info = flash;
2670 break;
2671 }
2672 }
2673 }
2674 else {
37137709 2675 u32 mask;
b6016b76
MC		 2676 /* Not yet been reconfigured */
2677
37137709
MC		 2678 if (val & (1 << 23))
2679 mask = FLASH_BACKUP_STRAP_MASK;
2680 else
2681 mask = FLASH_STRAP_MASK;
2682
b6016b76
MC		 2683 for (j = 0, flash = &flash_table[0]; j < entry_count;
2684 j++, flash++) {
2685
37137709 2686 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 2687 bp->flash_info = flash;
2688
2689 /* Request access to the flash interface. */
2690 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2691 return rc;
2692
2693 /* Enable access to flash interface */
2694 bnx2_enable_nvram_access(bp);
2695
2696 /* Reconfigure the flash interface */
2697 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2698 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2699 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2700 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2701
2702 /* Disable access to flash interface */
2703 bnx2_disable_nvram_access(bp);
2704 bnx2_release_nvram_lock(bp);
2705
2706 break;
2707 }
2708 }
2709 } /* if (val & 0x40000000) */
2710
2711 if (j == entry_count) {
2712 bp->flash_info = NULL;
2f23c523 2713 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
b6016b76
MC		 2714 rc = -ENODEV;
2715 }
2716
2717 return rc;
2718}
2719
2720static int
2721bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2722 int buf_size)
2723{
2724 int rc = 0;
2725 u32 cmd_flags, offset32, len32, extra;
2726
2727 if (buf_size == 0)
2728 return 0;
2729
2730 /* Request access to the flash interface. */
2731 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2732 return rc;
2733
2734 /* Enable access to flash interface */
2735 bnx2_enable_nvram_access(bp);
2736
2737 len32 = buf_size;
2738 offset32 = offset;
2739 extra = 0;
2740
2741 cmd_flags = 0;
2742
2743 if (offset32 & 3) {
2744 u8 buf[4];
2745 u32 pre_len;
2746
2747 offset32 &= ~3;
2748 pre_len = 4 - (offset & 3);
2749
2750 if (pre_len >= len32) {
2751 pre_len = len32;
2752 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2753 BNX2_NVM_COMMAND_LAST;
2754 }
2755 else {
2756 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2757 }
2758
2759 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2760
2761 if (rc)
2762 return rc;
2763
2764 memcpy(ret_buf, buf + (offset & 3), pre_len);
2765
2766 offset32 += 4;
2767 ret_buf += pre_len;
2768 len32 -= pre_len;
2769 }
2770 if (len32 & 3) {
2771 extra = 4 - (len32 & 3);
2772 len32 = (len32 + 4) & ~3;
2773 }
2774
2775 if (len32 == 4) {
2776 u8 buf[4];
2777
2778 if (cmd_flags)
2779 cmd_flags = BNX2_NVM_COMMAND_LAST;
2780 else
2781 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2782 BNX2_NVM_COMMAND_LAST;
2783
2784 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2785
2786 memcpy(ret_buf, buf, 4 - extra);
2787 }
2788 else if (len32 > 0) {
2789 u8 buf[4];
2790
2791 /* Read the first word. */
2792 if (cmd_flags)
2793 cmd_flags = 0;
2794 else
2795 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2796
2797 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2798
2799 /* Advance to the next dword. */
2800 offset32 += 4;
2801 ret_buf += 4;
2802 len32 -= 4;
2803
2804 while (len32 > 4 && rc == 0) {
2805 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2806
2807 /* Advance to the next dword. */
2808 offset32 += 4;
2809 ret_buf += 4;
2810 len32 -= 4;
2811 }
2812
2813 if (rc)
2814 return rc;
2815
2816 cmd_flags = BNX2_NVM_COMMAND_LAST;
2817 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2818
2819 memcpy(ret_buf, buf, 4 - extra);
2820 }
2821
2822 /* Disable access to flash interface */
2823 bnx2_disable_nvram_access(bp);
2824
2825 bnx2_release_nvram_lock(bp);
2826
2827 return rc;
2828}
2829
2830static int
2831bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2832 int buf_size)
2833{
2834 u32 written, offset32, len32;
2835 u8 *buf, start[4], end[4];
2836 int rc = 0;
2837 int align_start, align_end;
2838
2839 buf = data_buf;
2840 offset32 = offset;
2841 len32 = buf_size;
2842 align_start = align_end = 0;
2843
2844 if ((align_start = (offset32 & 3))) {
2845 offset32 &= ~3;
2846 len32 += align_start;
2847 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2848 return rc;
2849 }
2850
2851 if (len32 & 3) {
2852 if ((len32 > 4) || !align_start) {
2853 align_end = 4 - (len32 & 3);
2854 len32 += align_end;
2855 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2856 end, 4))) {
2857 return rc;
2858 }
2859 }
2860 }
2861
2862 if (align_start || align_end) {
2863 buf = kmalloc(len32, GFP_KERNEL);
2864 if (buf == 0)
2865 return -ENOMEM;
2866 if (align_start) {
2867 memcpy(buf, start, 4);
2868 }
2869 if (align_end) {
2870 memcpy(buf + len32 - 4, end, 4);
2871 }
2872 memcpy(buf + align_start, data_buf, buf_size);
2873 }
2874
2875 written = 0;
2876 while ((written < len32) && (rc == 0)) {
2877 u32 page_start, page_end, data_start, data_end;
2878 u32 addr, cmd_flags;
2879 int i;
2880 u8 flash_buffer[264];
2881
2882 /* Find the page_start addr */
2883 page_start = offset32 + written;
2884 page_start -= (page_start % bp->flash_info->page_size);
2885 /* Find the page_end addr */
2886 page_end = page_start + bp->flash_info->page_size;
2887 /* Find the data_start addr */
2888 data_start = (written == 0) ? offset32 : page_start;
2889 /* Find the data_end addr */
2890 data_end = (page_end > offset32 + len32) ?
2891 (offset32 + len32) : page_end;
2892
2893 /* Request access to the flash interface. */
2894 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2895 goto nvram_write_end;
2896
2897 /* Enable access to flash interface */
2898 bnx2_enable_nvram_access(bp);
2899
2900 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2901 if (bp->flash_info->buffered == 0) {
2902 int j;
2903
2904 /* Read the whole page into the buffer
2905 * (non-buffer flash only) */
2906 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2907 if (j == (bp->flash_info->page_size - 4)) {
2908 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2909 }
2910 rc = bnx2_nvram_read_dword(bp,
2911 page_start + j,
2912 &flash_buffer[j],
2913 cmd_flags);
2914
2915 if (rc)
2916 goto nvram_write_end;
2917
2918 cmd_flags = 0;
2919 }
2920 }
2921
2922 /* Enable writes to flash interface (unlock write-protect) */
2923 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2924 goto nvram_write_end;
2925
2926 /* Erase the page */
2927 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2928 goto nvram_write_end;
2929
2930 /* Re-enable the write again for the actual write */
2931 bnx2_enable_nvram_write(bp);
2932
2933 /* Loop to write back the buffer data from page_start to
2934 * data_start */
2935 i = 0;
2936 if (bp->flash_info->buffered == 0) {
2937 for (addr = page_start; addr < data_start;
2938 addr += 4, i += 4) {
2939
2940 rc = bnx2_nvram_write_dword(bp, addr,
2941 &flash_buffer[i], cmd_flags);
2942
2943 if (rc != 0)
2944 goto nvram_write_end;
2945
2946 cmd_flags = 0;
2947 }
2948 }
2949
2950 /* Loop to write the new data from data_start to data_end */
2951 for (addr = data_start; addr < data_end; addr += 4, i++) {
2952 if ((addr == page_end - 4) ||
2953 ((bp->flash_info->buffered) &&
2954 (addr == data_end - 4))) {
2955
2956 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2957 }
2958 rc = bnx2_nvram_write_dword(bp, addr, buf,
2959 cmd_flags);
2960
2961 if (rc != 0)
2962 goto nvram_write_end;
2963
2964 cmd_flags = 0;
2965 buf += 4;
2966 }
2967
2968 /* Loop to write back the buffer data from data_end
2969 * to page_end */
2970 if (bp->flash_info->buffered == 0) {
2971 for (addr = data_end; addr < page_end;
2972 addr += 4, i += 4) {
2973
2974 if (addr == page_end-4) {
2975 cmd_flags = BNX2_NVM_COMMAND_LAST;
2976 }
2977 rc = bnx2_nvram_write_dword(bp, addr,
2978 &flash_buffer[i], cmd_flags);
2979
2980 if (rc != 0)
2981 goto nvram_write_end;
2982
2983 cmd_flags = 0;
2984 }
2985 }
2986
2987 /* Disable writes to flash interface (lock write-protect) */
2988 bnx2_disable_nvram_write(bp);
2989
2990 /* Disable access to flash interface */
2991 bnx2_disable_nvram_access(bp);
2992 bnx2_release_nvram_lock(bp);
2993
2994 /* Increment written */
2995 written += data_end - data_start;
2996 }
2997
2998nvram_write_end:
2999 if (align_start || align_end)
3000 kfree(buf);
3001 return rc;
3002}
3003
3004static int
3005bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3006{
3007 u32 val;
3008 int i, rc = 0;
3009
3010 /* Wait for the current PCI transaction to complete before
3011 * issuing a reset. */
3012 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3013 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3014 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3015 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3016 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3017 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3018 udelay(5);
3019
b090ae2b
MC		 3020 /* Wait for the firmware to tell us it is ok to issue a reset. */
3021 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3022
b6016b76
MC		 3023 /* Deposit a driver reset signature so the firmware knows that
3024 * this is a soft reset. */
e3648b3d 3025 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
b6016b76
MC		 3026 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3027
b6016b76
MC		 3028 /* Do a dummy read to force the chip to complete all current transaction
3029 * before we issue a reset. */
3030 val = REG_RD(bp, BNX2_MISC_ID);
3031
3032 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3033 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3034 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3035
3036 /* Chip reset. */
3037 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3038
3039 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3040 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3041 msleep(15);
3042
3043 /* Reset takes approximate 30 usec */
3044 for (i = 0; i < 10; i++) {
3045 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3046 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3047 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3048 break;
3049 }
3050 udelay(10);
3051 }
3052
3053 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3054 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3055 printk(KERN_ERR PFX "Chip reset did not complete\n");
3056 return -EBUSY;
3057 }
3058
3059 /* Make sure byte swapping is properly configured. */
3060 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3061 if (val != 0x01020304) {
3062 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3063 return -ENODEV;
3064 }
3065
b6016b76 3066 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 3067 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3068 if (rc)
3069 return rc;
b6016b76
MC		 3070
3071 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3072 /* Adjust the voltage regular to two steps lower. The default
3073 * of this register is 0x0000000e. */
3074 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3075
3076 /* Remove bad rbuf memory from the free pool. */
3077 rc = bnx2_alloc_bad_rbuf(bp);
3078 }
3079
3080 return rc;
3081}
3082
3083static int
3084bnx2_init_chip(struct bnx2 *bp)
3085{
3086 u32 val;
b090ae2b 3087 int rc;
b6016b76
MC		 3088
3089 /* Make sure the interrupt is not active. */
3090 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3091
3092 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3093 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3094#ifdef __BIG_ENDIAN
3095 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3096#endif
3097 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3098 DMA_READ_CHANS << 12 |
3099 DMA_WRITE_CHANS << 16;
3100
3101 val |= (0x2 << 20) | (1 << 11);
3102
dda1e390 3103 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 3104 val |= (1 << 23);
3105
3106 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3107 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3108 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3109
3110 REG_WR(bp, BNX2_DMA_CONFIG, val);
3111
3112 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3113 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3114 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3115 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3116 }
3117
3118 if (bp->flags & PCIX_FLAG) {
3119 u16 val16;
3120
3121 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3122 &val16);
3123 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3124 val16 & ~PCI_X_CMD_ERO);
3125 }
3126
3127 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3128 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3129 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3130 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3131
3132 /* Initialize context mapping and zero out the quick contexts. The
3133 * context block must have already been enabled. */
3134 bnx2_init_context(bp);
3135
3136 bnx2_init_cpus(bp);
3137 bnx2_init_nvram(bp);
3138
3139 bnx2_set_mac_addr(bp);
3140
3141 val = REG_RD(bp, BNX2_MQ_CONFIG);
3142 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3143 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3144 REG_WR(bp, BNX2_MQ_CONFIG, val);
3145
3146 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3147 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3148 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3149
3150 val = (BCM_PAGE_BITS - 8) << 24;
3151 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3152
3153 /* Configure page size. */
3154 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3155 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3156 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3157 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3158
3159 val = bp->mac_addr[0] +
3160 (bp->mac_addr[1] << 8) +
3161 (bp->mac_addr[2] << 16) +
3162 bp->mac_addr[3] +
3163 (bp->mac_addr[4] << 8) +
3164 (bp->mac_addr[5] << 16);
3165 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3166
3167 /* Program the MTU. Also include 4 bytes for CRC32. */
3168 val = bp->dev->mtu + ETH_HLEN + 4;
3169 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3170 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3171 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3172
3173 bp->last_status_idx = 0;
3174 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3175
3176 /* Set up how to generate a link change interrupt. */
3177 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3178
3179 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3180 (u64) bp->status_blk_mapping & 0xffffffff);
3181 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3182
3183 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3184 (u64) bp->stats_blk_mapping & 0xffffffff);
3185 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3186 (u64) bp->stats_blk_mapping >> 32);
3187
3188 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3189 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3190
3191 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3192 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3193
3194 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3195 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3196
3197 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3198
3199 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3200
3201 REG_WR(bp, BNX2_HC_COM_TICKS,
3202 (bp->com_ticks_int << 16) | bp->com_ticks);
3203
3204 REG_WR(bp, BNX2_HC_CMD_TICKS,
3205 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3206
3207 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3208 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3209
3210 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3211 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3212 else {
3213 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3214 BNX2_HC_CONFIG_TX_TMR_MODE |
3215 BNX2_HC_CONFIG_COLLECT_STATS);
3216 }
3217
3218 /* Clear internal stats counters. */
3219 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3220
3221 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3222
e29054f9
MC		 3223 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3224 BNX2_PORT_FEATURE_ASF_ENABLED)
3225 bp->flags |= ASF_ENABLE_FLAG;
3226
b6016b76
MC		 3227 /* Initialize the receive filter. */
3228 bnx2_set_rx_mode(bp->dev);
3229
b090ae2b
MC		 3230 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3231 0);
b6016b76
MC		 3232
3233 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3234 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3235
3236 udelay(20);
3237
b090ae2b 3238 return rc;
b6016b76
MC		 3239}
3240
3241
3242static void
3243bnx2_init_tx_ring(struct bnx2 *bp)
3244{
3245 struct tx_bd *txbd;
3246 u32 val;
3247
3248 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3249
3250 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3251 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3252
3253 bp->tx_prod = 0;
3254 bp->tx_cons = 0;
f4e418f7 3255 bp->hw_tx_cons = 0;
b6016b76 3256 bp->tx_prod_bseq = 0;
b6016b76
MC		 3257
3258 val = BNX2_L2CTX_TYPE_TYPE_L2;
3259 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3260 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3261
3262 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3263 val |= 8 << 16;
3264 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3265
3266 val = (u64) bp->tx_desc_mapping >> 32;
3267 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3268
3269 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3270 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3271}
3272
3273static void
3274bnx2_init_rx_ring(struct bnx2 *bp)
3275{
3276 struct rx_bd *rxbd;
3277 int i;
3278 u16 prod, ring_prod;
3279 u32 val;
3280
3281 /* 8 for CRC and VLAN */
3282 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3283 /* 8 for alignment */
3284 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3285
3286 ring_prod = prod = bp->rx_prod = 0;
3287 bp->rx_cons = 0;
f4e418f7 3288 bp->hw_rx_cons = 0;
b6016b76
MC		 3289 bp->rx_prod_bseq = 0;
3290
3291 rxbd = &bp->rx_desc_ring[0];
3292 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3293 rxbd->rx_bd_len = bp->rx_buf_use_size;
3294 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3295 }
3296
3297 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3298 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3299
3300 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3301 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3302 val |= 0x02 << 8;
3303 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3304
3305 val = (u64) bp->rx_desc_mapping >> 32;
3306 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3307
3308 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3309 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3310
3311 for ( ;ring_prod < bp->rx_ring_size; ) {
3312 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3313 break;
3314 }
3315 prod = NEXT_RX_BD(prod);
3316 ring_prod = RX_RING_IDX(prod);
3317 }
3318 bp->rx_prod = prod;
3319
3320 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3321
3322 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3323}
3324
3325static void
3326bnx2_free_tx_skbs(struct bnx2 *bp)
3327{
3328 int i;
3329
3330 if (bp->tx_buf_ring == NULL)
3331 return;
3332
3333 for (i = 0; i < TX_DESC_CNT; ) {
3334 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3335 struct sk_buff *skb = tx_buf->skb;
3336 int j, last;
3337
3338 if (skb == NULL) {
3339 i++;
3340 continue;
3341 }
3342
3343 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3344 skb_headlen(skb), PCI_DMA_TODEVICE);
3345
3346 tx_buf->skb = NULL;
3347
3348 last = skb_shinfo(skb)->nr_frags;
3349 for (j = 0; j < last; j++) {
3350 tx_buf = &bp->tx_buf_ring[i + j + 1];
3351 pci_unmap_page(bp->pdev,
3352 pci_unmap_addr(tx_buf, mapping),
3353 skb_shinfo(skb)->frags[j].size,
3354 PCI_DMA_TODEVICE);
3355 }
3356 dev_kfree_skb_any(skb);
3357 i += j + 1;
3358 }
3359
3360}
3361
3362static void
3363bnx2_free_rx_skbs(struct bnx2 *bp)
3364{
3365 int i;
3366
3367 if (bp->rx_buf_ring == NULL)
3368 return;
3369
3370 for (i = 0; i < RX_DESC_CNT; i++) {
3371 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3372 struct sk_buff *skb = rx_buf->skb;
3373
05d0f1cf 3374 if (skb == NULL)
b6016b76
MC		 3375 continue;
3376
3377 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3378 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3379
3380 rx_buf->skb = NULL;
3381
3382 dev_kfree_skb_any(skb);
3383 }
3384}
3385
3386static void
3387bnx2_free_skbs(struct bnx2 *bp)
3388{
3389 bnx2_free_tx_skbs(bp);
3390 bnx2_free_rx_skbs(bp);
3391}
3392
3393static int
3394bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3395{
3396 int rc;
3397
3398 rc = bnx2_reset_chip(bp, reset_code);
3399 bnx2_free_skbs(bp);
3400 if (rc)
3401 return rc;
3402
3403 bnx2_init_chip(bp);
3404 bnx2_init_tx_ring(bp);
3405 bnx2_init_rx_ring(bp);
3406 return 0;
3407}
3408
3409static int
3410bnx2_init_nic(struct bnx2 *bp)
3411{
3412 int rc;
3413
3414 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3415 return rc;
3416
3417 bnx2_init_phy(bp);
3418 bnx2_set_link(bp);
3419 return 0;
3420}
3421
3422static int
3423bnx2_test_registers(struct bnx2 *bp)
3424{
3425 int ret;
3426 int i;
3427 static struct {
3428 u16 offset;
3429 u16 flags;
3430 u32 rw_mask;
3431 u32 ro_mask;
3432 } reg_tbl[] = {
3433 { 0x006c, 0, 0x00000000, 0x0000003f },
3434 { 0x0090, 0, 0xffffffff, 0x00000000 },
3435 { 0x0094, 0, 0x00000000, 0x00000000 },
3436
3437 { 0x0404, 0, 0x00003f00, 0x00000000 },
3438 { 0x0418, 0, 0x00000000, 0xffffffff },
3439 { 0x041c, 0, 0x00000000, 0xffffffff },
3440 { 0x0420, 0, 0x00000000, 0x80ffffff },
3441 { 0x0424, 0, 0x00000000, 0x00000000 },
3442 { 0x0428, 0, 0x00000000, 0x00000001 },
3443 { 0x0450, 0, 0x00000000, 0x0000ffff },
3444 { 0x0454, 0, 0x00000000, 0xffffffff },
3445 { 0x0458, 0, 0x00000000, 0xffffffff },
3446
3447 { 0x0808, 0, 0x00000000, 0xffffffff },
3448 { 0x0854, 0, 0x00000000, 0xffffffff },
3449 { 0x0868, 0, 0x00000000, 0x77777777 },
3450 { 0x086c, 0, 0x00000000, 0x77777777 },
3451 { 0x0870, 0, 0x00000000, 0x77777777 },
3452 { 0x0874, 0, 0x00000000, 0x77777777 },
3453
3454 { 0x0c00, 0, 0x00000000, 0x00000001 },
3455 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3456 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3457 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3458 { 0x0c30, 0, 0x00000000, 0xffffffff },
3459 { 0x0c34, 0, 0x00000000, 0xffffffff },
3460 { 0x0c38, 0, 0x00000000, 0xffffffff },
3461 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3462 { 0x0c40, 0, 0x00000000, 0xffffffff },
3463 { 0x0c44, 0, 0x00000000, 0xffffffff },
3464 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3465 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3466 { 0x0c50, 0, 0x00000000, 0xffffffff },
3467 { 0x0c54, 0, 0x00000000, 0xffffffff },
3468 { 0x0c58, 0, 0x00000000, 0xffffffff },
3469 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3470 { 0x0c60, 0, 0x00000000, 0xffffffff },
3471 { 0x0c64, 0, 0x00000000, 0xffffffff },
3472 { 0x0c68, 0, 0x00000000, 0xffffffff },
3473 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3474 { 0x0c70, 0, 0x00000000, 0xffffffff },
3475 { 0x0c74, 0, 0x00000000, 0xffffffff },
3476 { 0x0c78, 0, 0x00000000, 0xffffffff },
3477 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3478 { 0x0c80, 0, 0x00000000, 0xffffffff },
3479 { 0x0c84, 0, 0x00000000, 0xffffffff },
3480 { 0x0c88, 0, 0x00000000, 0xffffffff },
3481 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3482 { 0x0c90, 0, 0x00000000, 0xffffffff },
3483 { 0x0c94, 0, 0x00000000, 0xffffffff },
3484 { 0x0c98, 0, 0x00000000, 0xffffffff },
3485 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3486 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3487 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3488 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3489 { 0x0cac, 0, 0x00000000, 0xffffffff },
3490 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3491 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3492 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3493 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3494 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3495 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3496 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3497 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3498 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3499 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3500 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3501 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3502 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3503 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3504 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3505 { 0x0cec, 0, 0x00000000, 0xffffffff },
3506 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3507 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3508 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3509 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3510 { 0x0d00, 0, 0x00000000, 0xffffffff },
3511 { 0x0d04, 0, 0x00000000, 0xffffffff },
3512
3513 { 0x1000, 0, 0x00000000, 0x00000001 },
3514 { 0x1004, 0, 0x00000000, 0x000f0001 },
3515 { 0x1044, 0, 0x00000000, 0xffc003ff },
3516 { 0x1080, 0, 0x00000000, 0x0001ffff },
3517 { 0x1084, 0, 0x00000000, 0xffffffff },
3518 { 0x1088, 0, 0x00000000, 0xffffffff },
3519 { 0x108c, 0, 0x00000000, 0xffffffff },
3520 { 0x1090, 0, 0x00000000, 0xffffffff },
3521 { 0x1094, 0, 0x00000000, 0xffffffff },
3522 { 0x1098, 0, 0x00000000, 0xffffffff },
3523 { 0x109c, 0, 0x00000000, 0xffffffff },
3524 { 0x10a0, 0, 0x00000000, 0xffffffff },
3525
3526 { 0x1408, 0, 0x01c00800, 0x00000000 },
3527 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3528 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 3529 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 3530 { 0x14b0, 0, 0x00000002, 0x00000001 },
3531 { 0x14b8, 0, 0x00000000, 0x00000000 },
3532 { 0x14c0, 0, 0x00000000, 0x00000009 },
3533 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3534 { 0x14cc, 0, 0x00000000, 0x00000001 },
3535 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3536 { 0x1500, 0, 0x00000000, 0xffffffff },
3537 { 0x1504, 0, 0x00000000, 0xffffffff },
3538 { 0x1508, 0, 0x00000000, 0xffffffff },
3539 { 0x150c, 0, 0x00000000, 0xffffffff },
3540 { 0x1510, 0, 0x00000000, 0xffffffff },
3541 { 0x1514, 0, 0x00000000, 0xffffffff },
3542 { 0x1518, 0, 0x00000000, 0xffffffff },
3543 { 0x151c, 0, 0x00000000, 0xffffffff },
3544 { 0x1520, 0, 0x00000000, 0xffffffff },
3545 { 0x1524, 0, 0x00000000, 0xffffffff },
3546 { 0x1528, 0, 0x00000000, 0xffffffff },
3547 { 0x152c, 0, 0x00000000, 0xffffffff },
3548 { 0x1530, 0, 0x00000000, 0xffffffff },
3549 { 0x1534, 0, 0x00000000, 0xffffffff },
3550 { 0x1538, 0, 0x00000000, 0xffffffff },
3551 { 0x153c, 0, 0x00000000, 0xffffffff },
3552 { 0x1540, 0, 0x00000000, 0xffffffff },
3553 { 0x1544, 0, 0x00000000, 0xffffffff },
3554 { 0x1548, 0, 0x00000000, 0xffffffff },
3555 { 0x154c, 0, 0x00000000, 0xffffffff },
3556 { 0x1550, 0, 0x00000000, 0xffffffff },
3557 { 0x1554, 0, 0x00000000, 0xffffffff },
3558 { 0x1558, 0, 0x00000000, 0xffffffff },
3559 { 0x1600, 0, 0x00000000, 0xffffffff },
3560 { 0x1604, 0, 0x00000000, 0xffffffff },
3561 { 0x1608, 0, 0x00000000, 0xffffffff },
3562 { 0x160c, 0, 0x00000000, 0xffffffff },
3563 { 0x1610, 0, 0x00000000, 0xffffffff },
3564 { 0x1614, 0, 0x00000000, 0xffffffff },
3565 { 0x1618, 0, 0x00000000, 0xffffffff },
3566 { 0x161c, 0, 0x00000000, 0xffffffff },
3567 { 0x1620, 0, 0x00000000, 0xffffffff },
3568 { 0x1624, 0, 0x00000000, 0xffffffff },
3569 { 0x1628, 0, 0x00000000, 0xffffffff },
3570 { 0x162c, 0, 0x00000000, 0xffffffff },
3571 { 0x1630, 0, 0x00000000, 0xffffffff },
3572 { 0x1634, 0, 0x00000000, 0xffffffff },
3573 { 0x1638, 0, 0x00000000, 0xffffffff },
3574 { 0x163c, 0, 0x00000000, 0xffffffff },
3575 { 0x1640, 0, 0x00000000, 0xffffffff },
3576 { 0x1644, 0, 0x00000000, 0xffffffff },
3577 { 0x1648, 0, 0x00000000, 0xffffffff },
3578 { 0x164c, 0, 0x00000000, 0xffffffff },
3579 { 0x1650, 0, 0x00000000, 0xffffffff },
3580 { 0x1654, 0, 0x00000000, 0xffffffff },
3581
3582 { 0x1800, 0, 0x00000000, 0x00000001 },
3583 { 0x1804, 0, 0x00000000, 0x00000003 },
3584 { 0x1840, 0, 0x00000000, 0xffffffff },
3585 { 0x1844, 0, 0x00000000, 0xffffffff },
3586 { 0x1848, 0, 0x00000000, 0xffffffff },
3587 { 0x184c, 0, 0x00000000, 0xffffffff },
3588 { 0x1850, 0, 0x00000000, 0xffffffff },
3589 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3590 { 0x1904, 0, 0xffffffff, 0x00000000 },
3591 { 0x190c, 0, 0xffffffff, 0x00000000 },
3592 { 0x1914, 0, 0xffffffff, 0x00000000 },
3593 { 0x191c, 0, 0xffffffff, 0x00000000 },
3594 { 0x1924, 0, 0xffffffff, 0x00000000 },
3595 { 0x192c, 0, 0xffffffff, 0x00000000 },
3596 { 0x1934, 0, 0xffffffff, 0x00000000 },
3597 { 0x193c, 0, 0xffffffff, 0x00000000 },
3598 { 0x1944, 0, 0xffffffff, 0x00000000 },
3599 { 0x194c, 0, 0xffffffff, 0x00000000 },
3600 { 0x1954, 0, 0xffffffff, 0x00000000 },
3601 { 0x195c, 0, 0xffffffff, 0x00000000 },
3602 { 0x1964, 0, 0xffffffff, 0x00000000 },
3603 { 0x196c, 0, 0xffffffff, 0x00000000 },
3604 { 0x1974, 0, 0xffffffff, 0x00000000 },
3605 { 0x197c, 0, 0xffffffff, 0x00000000 },
3606 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3607
3608 { 0x1c00, 0, 0x00000000, 0x00000001 },
3609 { 0x1c04, 0, 0x00000000, 0x00000003 },
3610 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3611 { 0x1c40, 0, 0x00000000, 0xffffffff },
3612 { 0x1c44, 0, 0x00000000, 0xffffffff },
3613 { 0x1c48, 0, 0x00000000, 0xffffffff },
3614 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3615 { 0x1c50, 0, 0x00000000, 0xffffffff },
3616 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3617 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3618 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3619 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3620 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3621 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3622 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3623 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3624 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3625 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3626 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3627 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3628 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3629 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3630 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3631 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3632 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3633 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3634
3635 { 0x2004, 0, 0x00000000, 0x0337000f },
3636 { 0x2008, 0, 0xffffffff, 0x00000000 },
3637 { 0x200c, 0, 0xffffffff, 0x00000000 },
3638 { 0x2010, 0, 0xffffffff, 0x00000000 },
3639 { 0x2014, 0, 0x801fff80, 0x00000000 },
3640 { 0x2018, 0, 0x000003ff, 0x00000000 },
3641
3642 { 0x2800, 0, 0x00000000, 0x00000001 },
3643 { 0x2804, 0, 0x00000000, 0x00003f01 },
3644 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3645 { 0x2810, 0, 0xffff0000, 0x00000000 },
3646 { 0x2814, 0, 0xffff0000, 0x00000000 },
3647 { 0x2818, 0, 0xffff0000, 0x00000000 },
3648 { 0x281c, 0, 0xffff0000, 0x00000000 },
3649 { 0x2834, 0, 0xffffffff, 0x00000000 },
3650 { 0x2840, 0, 0x00000000, 0xffffffff },
3651 { 0x2844, 0, 0x00000000, 0xffffffff },
3652 { 0x2848, 0, 0xffffffff, 0x00000000 },
3653 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3654
3655 { 0x2c00, 0, 0x00000000, 0x00000011 },
3656 { 0x2c04, 0, 0x00000000, 0x00030007 },
3657
3658 { 0x3000, 0, 0x00000000, 0x00000001 },
3659 { 0x3004, 0, 0x00000000, 0x007007ff },
3660 { 0x3008, 0, 0x00000003, 0x00000000 },
3661 { 0x300c, 0, 0xffffffff, 0x00000000 },
3662 { 0x3010, 0, 0xffffffff, 0x00000000 },
3663 { 0x3014, 0, 0xffffffff, 0x00000000 },
3664 { 0x3034, 0, 0xffffffff, 0x00000000 },
3665 { 0x3038, 0, 0xffffffff, 0x00000000 },
3666 { 0x3050, 0, 0x00000001, 0x00000000 },
3667
3668 { 0x3c00, 0, 0x00000000, 0x00000001 },
3669 { 0x3c04, 0, 0x00000000, 0x00070000 },
3670 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3671 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3672 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3673 { 0x3c14, 0, 0x00000000, 0xffffffff },
3674 { 0x3c18, 0, 0x00000000, 0xffffffff },
3675 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3676 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3677 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3678 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3679 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3680 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3681 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3682 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3683 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3684 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3685 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3686 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3687 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3688 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3689 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3690 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3691 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3692 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3693 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3694 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3695 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3696 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3697 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3698 { 0x3c78, 0, 0x00000000, 0x00000000 },
3699 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3700 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3701 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3702 { 0x3c88, 0, 0x00000000, 0xffffffff },
3703 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3704
3705 { 0x4000, 0, 0x00000000, 0x00000001 },
3706 { 0x4004, 0, 0x00000000, 0x00030000 },
3707 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3708 { 0x400c, 0, 0xffffffff, 0x00000000 },
3709 { 0x4088, 0, 0x00000000, 0x00070303 },
3710
3711 { 0x4400, 0, 0x00000000, 0x00000001 },
3712 { 0x4404, 0, 0x00000000, 0x00003f01 },
3713 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3714 { 0x440c, 0, 0xffffffff, 0x00000000 },
3715 { 0x4410, 0, 0xffff, 0x0000 },
3716 { 0x4414, 0, 0xffff, 0x0000 },
3717 { 0x4418, 0, 0xffff, 0x0000 },
3718 { 0x441c, 0, 0xffff, 0x0000 },
3719 { 0x4428, 0, 0xffffffff, 0x00000000 },
3720 { 0x442c, 0, 0xffffffff, 0x00000000 },
3721 { 0x4430, 0, 0xffffffff, 0x00000000 },
3722 { 0x4434, 0, 0xffffffff, 0x00000000 },
3723 { 0x4438, 0, 0xffffffff, 0x00000000 },
3724 { 0x443c, 0, 0xffffffff, 0x00000000 },
3725 { 0x4440, 0, 0xffffffff, 0x00000000 },
3726 { 0x4444, 0, 0xffffffff, 0x00000000 },
3727
3728 { 0x4c00, 0, 0x00000000, 0x00000001 },
3729 { 0x4c04, 0, 0x00000000, 0x0000003f },
3730 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3731 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3732 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3733 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3734 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3735 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3736 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3737 { 0x4c50, 0, 0x00000000, 0xffffffff },
3738
3739 { 0x5004, 0, 0x00000000, 0x0000007f },
3740 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3741 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3742
3743 { 0x5400, 0, 0x00000008, 0x00000001 },
3744 { 0x5404, 0, 0x00000000, 0x0000003f },
3745 { 0x5408, 0, 0x0000001f, 0x00000000 },
3746 { 0x540c, 0, 0xffffffff, 0x00000000 },
3747 { 0x5410, 0, 0xffffffff, 0x00000000 },
3748 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3749 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3750 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3751 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3752 { 0x5428, 0, 0x000000ff, 0x00000000 },
3753 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3754 { 0x5430, 0, 0x001fff80, 0x00000000 },
3755 { 0x5438, 0, 0xffffffff, 0x00000000 },
3756 { 0x543c, 0, 0xffffffff, 0x00000000 },
3757 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3758
3759 { 0x5c00, 0, 0x00000000, 0x00000001 },
3760 { 0x5c04, 0, 0x00000000, 0x0003000f },
3761 { 0x5c08, 0, 0x00000003, 0x00000000 },
3762 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3763 { 0x5c10, 0, 0x00000000, 0xffffffff },
3764 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3765 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3766 { 0x5c88, 0, 0x00000000, 0x00077373 },
3767 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3768
3769 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3770 { 0x680c, 0, 0xffffffff, 0x00000000 },
3771 { 0x6810, 0, 0xffffffff, 0x00000000 },
3772 { 0x6814, 0, 0xffffffff, 0x00000000 },
3773 { 0x6818, 0, 0xffffffff, 0x00000000 },
3774 { 0x681c, 0, 0xffffffff, 0x00000000 },
3775 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3776 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3777 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3778 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3779 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3780 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3781 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3782 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3783 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3784 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3785 { 0x684c, 0, 0xffffffff, 0x00000000 },
3786 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3787 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3788 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3789 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3790 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3791 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3792
3793 { 0xffff, 0, 0x00000000, 0x00000000 },
3794 };
3795
3796 ret = 0;
3797 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3798 u32 offset, rw_mask, ro_mask, save_val, val;
3799
3800 offset = (u32) reg_tbl[i].offset;
3801 rw_mask = reg_tbl[i].rw_mask;
3802 ro_mask = reg_tbl[i].ro_mask;
3803
14ab9b86 3804 save_val = readl(bp->regview + offset);
b6016b76 3805
14ab9b86 3806 writel(0, bp->regview + offset);
b6016b76 3807
14ab9b86 3808 val = readl(bp->regview + offset);
b6016b76
MC		 3809 if ((val & rw_mask) != 0) {
3810 goto reg_test_err;
3811 }
3812
3813 if ((val & ro_mask) != (save_val & ro_mask)) {
3814 goto reg_test_err;
3815 }
3816
14ab9b86 3817 writel(0xffffffff, bp->regview + offset);
b6016b76 3818
14ab9b86 3819 val = readl(bp->regview + offset);
b6016b76
MC		 3820 if ((val & rw_mask) != rw_mask) {
3821 goto reg_test_err;
3822 }
3823
3824 if ((val & ro_mask) != (save_val & ro_mask)) {
3825 goto reg_test_err;
3826 }
3827
14ab9b86 3828 writel(save_val, bp->regview + offset);
b6016b76
MC		 3829 continue;
3830
3831reg_test_err:
14ab9b86 3832 writel(save_val, bp->regview + offset);
b6016b76
MC		 3833 ret = -ENODEV;
3834 break;
3835 }
3836 return ret;
3837}
3838
3839static int
3840bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3841{
3842 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3843 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3844 int i;
3845
3846 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3847 u32 offset;
3848
3849 for (offset = 0; offset < size; offset += 4) {
3850
3851 REG_WR_IND(bp, start + offset, test_pattern[i]);
3852
3853 if (REG_RD_IND(bp, start + offset) !=
3854 test_pattern[i]) {
3855 return -ENODEV;
3856 }
3857 }
3858 }
3859 return 0;
3860}
3861
3862static int
3863bnx2_test_memory(struct bnx2 *bp)
3864{
3865 int ret = 0;
3866 int i;
3867 static struct {
3868 u32 offset;
3869 u32 len;
3870 } mem_tbl[] = {
3871 { 0x60000, 0x4000 },
5b0c76ad 3872 { 0xa0000, 0x3000 },
b6016b76
MC		 3873 { 0xe0000, 0x4000 },
3874 { 0x120000, 0x4000 },
3875 { 0x1a0000, 0x4000 },
3876 { 0x160000, 0x4000 },
3877 { 0xffffffff, 0 },
3878 };
3879
3880 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3881 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3882 mem_tbl[i].len)) != 0) {
3883 return ret;
3884 }
3885 }
3886
3887 return ret;
3888}
3889
3890static int
3891bnx2_test_loopback(struct bnx2 *bp)
3892{
3893 unsigned int pkt_size, num_pkts, i;
3894 struct sk_buff *skb, *rx_skb;
3895 unsigned char *packet;
3896 u16 rx_start_idx, rx_idx, send_idx;
3897 u32 send_bseq, val;
3898 dma_addr_t map;
3899 struct tx_bd *txbd;
3900 struct sw_bd *rx_buf;
3901 struct l2_fhdr *rx_hdr;
3902 int ret = -ENODEV;
3903
3904 if (!netif_running(bp->dev))
3905 return -ENODEV;
3906
3907 bp->loopback = MAC_LOOPBACK;
3908 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3909 bnx2_set_mac_loopback(bp);
3910
3911 pkt_size = 1514;
3912 skb = dev_alloc_skb(pkt_size);
b6cbc3b6
JL		 3913 if (!skb)
3914 return -ENOMEM;
b6016b76
MC		 3915 packet = skb_put(skb, pkt_size);
3916 memcpy(packet, bp->mac_addr, 6);
3917 memset(packet + 6, 0x0, 8);
3918 for (i = 14; i < pkt_size; i++)
3919 packet[i] = (unsigned char) (i & 0xff);
3920
3921 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3922 PCI_DMA_TODEVICE);
3923
3924 val = REG_RD(bp, BNX2_HC_COMMAND);
3925 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3926 REG_RD(bp, BNX2_HC_COMMAND);
3927
3928 udelay(5);
3929 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3930
3931 send_idx = 0;
3932 send_bseq = 0;
3933 num_pkts = 0;
3934
3935 txbd = &bp->tx_desc_ring[send_idx];
3936
3937 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3938 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3939 txbd->tx_bd_mss_nbytes = pkt_size;
3940 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3941
3942 num_pkts++;
3943 send_idx = NEXT_TX_BD(send_idx);
3944
3945 send_bseq += pkt_size;
3946
3947 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3948 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3949
3950
3951 udelay(100);
3952
3953 val = REG_RD(bp, BNX2_HC_COMMAND);
3954 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3955 REG_RD(bp, BNX2_HC_COMMAND);
3956
3957 udelay(5);
3958
3959 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3960 dev_kfree_skb_irq(skb);
3961
3962 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3963 goto loopback_test_done;
3964 }
3965
3966 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3967 if (rx_idx != rx_start_idx + num_pkts) {
3968 goto loopback_test_done;
3969 }
3970
3971 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3972 rx_skb = rx_buf->skb;
3973
3974 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3975 skb_reserve(rx_skb, bp->rx_offset);
3976
3977 pci_dma_sync_single_for_cpu(bp->pdev,
3978 pci_unmap_addr(rx_buf, mapping),
3979 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3980
3981 if (rx_hdr->l2_fhdr_errors &
3982 (L2_FHDR_ERRORS_BAD_CRC |
3983 L2_FHDR_ERRORS_PHY_DECODE |
3984 L2_FHDR_ERRORS_ALIGNMENT |
3985 L2_FHDR_ERRORS_TOO_SHORT |
3986 L2_FHDR_ERRORS_GIANT_FRAME)) {
3987
3988 goto loopback_test_done;
3989 }
3990
3991 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3992 goto loopback_test_done;
3993 }
3994
3995 for (i = 14; i < pkt_size; i++) {
3996 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3997 goto loopback_test_done;
3998 }
3999 }
4000
4001 ret = 0;
4002
4003loopback_test_done:
4004 bp->loopback = 0;
4005 return ret;
4006}
4007
4008#define NVRAM_SIZE 0x200
4009#define CRC32_RESIDUAL 0xdebb20e3
4010
4011static int
4012bnx2_test_nvram(struct bnx2 *bp)
4013{
4014 u32 buf[NVRAM_SIZE / 4];
4015 u8 *data = (u8 *) buf;
4016 int rc = 0;
4017 u32 magic, csum;
4018
4019 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4020 goto test_nvram_done;
4021
4022 magic = be32_to_cpu(buf[0]);
4023 if (magic != 0x669955aa) {
4024 rc = -ENODEV;
4025 goto test_nvram_done;
4026 }
4027
4028 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4029 goto test_nvram_done;
4030
4031 csum = ether_crc_le(0x100, data);
4032 if (csum != CRC32_RESIDUAL) {
4033 rc = -ENODEV;
4034 goto test_nvram_done;
4035 }
4036
4037 csum = ether_crc_le(0x100, data + 0x100);
4038 if (csum != CRC32_RESIDUAL) {
4039 rc = -ENODEV;
4040 }
4041
4042test_nvram_done:
4043 return rc;
4044}
4045
4046static int
4047bnx2_test_link(struct bnx2 *bp)
4048{
4049 u32 bmsr;
4050
c770a65c 4051 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4052 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4053 bnx2_read_phy(bp, MII_BMSR, &bmsr);
c770a65c 4054 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4055
4056 if (bmsr & BMSR_LSTATUS) {
4057 return 0;
4058 }
4059 return -ENODEV;
4060}
4061
4062static int
4063bnx2_test_intr(struct bnx2 *bp)
4064{
4065 int i;
4066 u32 val;
4067 u16 status_idx;
4068
4069 if (!netif_running(bp->dev))
4070 return -ENODEV;
4071
4072 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4073
4074 /* This register is not touched during run-time. */
4075 val = REG_RD(bp, BNX2_HC_COMMAND);
4076 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
4077 REG_RD(bp, BNX2_HC_COMMAND);
4078
4079 for (i = 0; i < 10; i++) {
4080 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4081 status_idx) {
4082
4083 break;
4084 }
4085
4086 msleep_interruptible(10);
4087 }
4088 if (i < 10)
4089 return 0;
4090
4091 return -ENODEV;
4092}
4093
4094static void
4095bnx2_timer(unsigned long data)
4096{
4097 struct bnx2 *bp = (struct bnx2 *) data;
4098 u32 msg;
4099
cd339a0e
MC		 4100 if (!netif_running(bp->dev))
4101 return;
4102
b6016b76
MC		 4103 if (atomic_read(&bp->intr_sem) != 0)
4104 goto bnx2_restart_timer;
4105
4106 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
e3648b3d 4107 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
b6016b76
MC		 4108
4109 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4110 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
b6016b76 4111
c770a65c 4112 spin_lock(&bp->phy_lock);
b6016b76
MC		 4113 if (bp->serdes_an_pending) {
4114 bp->serdes_an_pending--;
4115 }
4116 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4117 u32 bmcr;
4118
cd339a0e
MC		 4119 bp->current_interval = bp->timer_interval;
4120
b6016b76
MC		 4121 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4122
4123 if (bmcr & BMCR_ANENABLE) {
4124 u32 phy1, phy2;
4125
4126 bnx2_write_phy(bp, 0x1c, 0x7c00);
4127 bnx2_read_phy(bp, 0x1c, &phy1);
4128
4129 bnx2_write_phy(bp, 0x17, 0x0f01);
4130 bnx2_read_phy(bp, 0x15, &phy2);
4131 bnx2_write_phy(bp, 0x17, 0x0f01);
4132 bnx2_read_phy(bp, 0x15, &phy2);
4133
4134 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4135 !(phy2 & 0x20)) { /* no CONFIG */
4136
4137 bmcr &= ~BMCR_ANENABLE;
4138 bmcr |= BMCR_SPEED1000 |
4139 BMCR_FULLDPLX;
4140 bnx2_write_phy(bp, MII_BMCR, bmcr);
4141 bp->phy_flags |=
4142 PHY_PARALLEL_DETECT_FLAG;
4143 }
4144 }
4145 }
4146 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4147 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4148 u32 phy2;
4149
4150 bnx2_write_phy(bp, 0x17, 0x0f01);
4151 bnx2_read_phy(bp, 0x15, &phy2);
4152 if (phy2 & 0x20) {
4153 u32 bmcr;
4154
4155 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4156 bmcr |= BMCR_ANENABLE;
4157 bnx2_write_phy(bp, MII_BMCR, bmcr);
4158
4159 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4160
4161 }
4162 }
cd339a0e
MC		 4163 else
4164 bp->current_interval = bp->timer_interval;
b6016b76 4165
c770a65c 4166 spin_unlock(&bp->phy_lock);
b6016b76
MC		 4167 }
4168
4169bnx2_restart_timer:
cd339a0e 4170 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4171}
4172
4173/* Called with rtnl_lock */
4174static int
4175bnx2_open(struct net_device *dev)
4176{
4177 struct bnx2 *bp = dev->priv;
4178 int rc;
4179
829ca9a3 4180 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 4181 bnx2_disable_int(bp);
4182
4183 rc = bnx2_alloc_mem(bp);
4184 if (rc)
4185 return rc;
4186
4187 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4188 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4189 !disable_msi) {
4190
4191 if (pci_enable_msi(bp->pdev) == 0) {
4192 bp->flags |= USING_MSI_FLAG;
4193 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4194 dev);
4195 }
4196 else {
4197 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4198 SA_SHIRQ, dev->name, dev);
4199 }
4200 }
4201 else {
4202 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4203 dev->name, dev);
4204 }
4205 if (rc) {
4206 bnx2_free_mem(bp);
4207 return rc;
4208 }
4209
4210 rc = bnx2_init_nic(bp);
4211
4212 if (rc) {
4213 free_irq(bp->pdev->irq, dev);
4214 if (bp->flags & USING_MSI_FLAG) {
4215 pci_disable_msi(bp->pdev);
4216 bp->flags &= ~USING_MSI_FLAG;
4217 }
4218 bnx2_free_skbs(bp);
4219 bnx2_free_mem(bp);
4220 return rc;
4221 }
4222
cd339a0e 4223 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4224
4225 atomic_set(&bp->intr_sem, 0);
4226
4227 bnx2_enable_int(bp);
4228
4229 if (bp->flags & USING_MSI_FLAG) {
4230 /* Test MSI to make sure it is working
4231 * If MSI test fails, go back to INTx mode
4232 */
4233 if (bnx2_test_intr(bp) != 0) {
4234 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4235 " using MSI, switching to INTx mode. Please"
4236 " report this failure to the PCI maintainer"
4237 " and include system chipset information.\n",
4238 bp->dev->name);
4239
4240 bnx2_disable_int(bp);
4241 free_irq(bp->pdev->irq, dev);
4242 pci_disable_msi(bp->pdev);
4243 bp->flags &= ~USING_MSI_FLAG;
4244
4245 rc = bnx2_init_nic(bp);
4246
4247 if (!rc) {
4248 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4249 SA_SHIRQ, dev->name, dev);
4250 }
4251 if (rc) {
4252 bnx2_free_skbs(bp);
4253 bnx2_free_mem(bp);
4254 del_timer_sync(&bp->timer);
4255 return rc;
4256 }
4257 bnx2_enable_int(bp);
4258 }
4259 }
4260 if (bp->flags & USING_MSI_FLAG) {
4261 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4262 }
4263
4264 netif_start_queue(dev);
4265
4266 return 0;
4267}
4268
4269static void
4270bnx2_reset_task(void *data)
4271{
4272 struct bnx2 *bp = data;
4273
afdc08b9
MC		 4274 if (!netif_running(bp->dev))
4275 return;
4276
4277 bp->in_reset_task = 1;
b6016b76
MC		 4278 bnx2_netif_stop(bp);
4279
4280 bnx2_init_nic(bp);
4281
4282 atomic_set(&bp->intr_sem, 1);
4283 bnx2_netif_start(bp);
afdc08b9 4284 bp->in_reset_task = 0;
b6016b76
MC		 4285}
4286
4287static void
4288bnx2_tx_timeout(struct net_device *dev)
4289{
4290 struct bnx2 *bp = dev->priv;
4291
4292 /* This allows the netif to be shutdown gracefully before resetting */
4293 schedule_work(&bp->reset_task);
4294}
4295
4296#ifdef BCM_VLAN
4297/* Called with rtnl_lock */
4298static void
4299bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4300{
4301 struct bnx2 *bp = dev->priv;
4302
4303 bnx2_netif_stop(bp);
4304
4305 bp->vlgrp = vlgrp;
4306 bnx2_set_rx_mode(dev);
4307
4308 bnx2_netif_start(bp);
4309}
4310
4311/* Called with rtnl_lock */
4312static void
4313bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4314{
4315 struct bnx2 *bp = dev->priv;
4316
4317 bnx2_netif_stop(bp);
4318
4319 if (bp->vlgrp)
4320 bp->vlgrp->vlan_devices[vid] = NULL;
4321 bnx2_set_rx_mode(dev);
4322
4323 bnx2_netif_start(bp);
4324}
4325#endif
4326
4327/* Called with dev->xmit_lock.
4328 * hard_start_xmit is pseudo-lockless - a lock is only required when
4329 * the tx queue is full. This way, we get the benefit of lockless
4330 * operations most of the time without the complexities to handle
4331 * netif_stop_queue/wake_queue race conditions.
4332 */
4333static int
4334bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4335{
4336 struct bnx2 *bp = dev->priv;
4337 dma_addr_t mapping;
4338 struct tx_bd *txbd;
4339 struct sw_bd *tx_buf;
4340 u32 len, vlan_tag_flags, last_frag, mss;
4341 u16 prod, ring_prod;
4342 int i;
4343
e89bbf10 4344 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 4345 netif_stop_queue(dev);
4346 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4347 dev->name);
4348
4349 return NETDEV_TX_BUSY;
4350 }
4351 len = skb_headlen(skb);
4352 prod = bp->tx_prod;
4353 ring_prod = TX_RING_IDX(prod);
4354
4355 vlan_tag_flags = 0;
4356 if (skb->ip_summed == CHECKSUM_HW) {
4357 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4358 }
4359
4360 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4361 vlan_tag_flags |=
4362 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4363 }
4364#ifdef BCM_TSO
4365 if ((mss = skb_shinfo(skb)->tso_size) &&
4366 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4367 u32 tcp_opt_len, ip_tcp_len;
4368
4369 if (skb_header_cloned(skb) &&
4370 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4371 dev_kfree_skb(skb);
4372 return NETDEV_TX_OK;
4373 }
4374
4375 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4376 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4377
4378 tcp_opt_len = 0;
4379 if (skb->h.th->doff > 5) {
4380 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4381 }
4382 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4383
4384 skb->nh.iph->check = 0;
4385 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4386 skb->h.th->check =
4387 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4388 skb->nh.iph->daddr,
4389 0, IPPROTO_TCP, 0);
4390
4391 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4392 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4393 (tcp_opt_len >> 2)) << 8;
4394 }
4395 }
4396 else
4397#endif
4398 {
4399 mss = 0;
4400 }
4401
4402 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4403
4404 tx_buf = &bp->tx_buf_ring[ring_prod];
4405 tx_buf->skb = skb;
4406 pci_unmap_addr_set(tx_buf, mapping, mapping);
4407
4408 txbd = &bp->tx_desc_ring[ring_prod];
4409
4410 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4411 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4412 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4413 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4414
4415 last_frag = skb_shinfo(skb)->nr_frags;
4416
4417 for (i = 0; i < last_frag; i++) {
4418 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4419
4420 prod = NEXT_TX_BD(prod);
4421 ring_prod = TX_RING_IDX(prod);
4422 txbd = &bp->tx_desc_ring[ring_prod];
4423
4424 len = frag->size;
4425 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4426 len, PCI_DMA_TODEVICE);
4427 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4428 mapping, mapping);
4429
4430 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4431 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4432 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4433 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4434
4435 }
4436 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4437
4438 prod = NEXT_TX_BD(prod);
4439 bp->tx_prod_bseq += skb->len;
4440
b6016b76
MC		 4441 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4442 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4443
4444 mmiowb();
4445
4446 bp->tx_prod = prod;
4447 dev->trans_start = jiffies;
4448
e89bbf10 4449 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
c770a65c 4450 spin_lock(&bp->tx_lock);
e89bbf10
MC		 4451 netif_stop_queue(dev);
4452
4453 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4454 netif_wake_queue(dev);
c770a65c 4455 spin_unlock(&bp->tx_lock);
b6016b76
MC		 4456 }
4457
4458 return NETDEV_TX_OK;
4459}
4460
4461/* Called with rtnl_lock */
4462static int
4463bnx2_close(struct net_device *dev)
4464{
4465 struct bnx2 *bp = dev->priv;
4466 u32 reset_code;
4467
afdc08b9
MC		 4468 /* Calling flush_scheduled_work() may deadlock because
4469 * linkwatch_event() may be on the workqueue and it will try to get
4470 * the rtnl_lock which we are holding.
4471 */
4472 while (bp->in_reset_task)
4473 msleep(1);
4474
b6016b76
MC		 4475 bnx2_netif_stop(bp);
4476 del_timer_sync(&bp->timer);
dda1e390
MC		 4477 if (bp->flags & NO_WOL_FLAG)
4478 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
4479 else if (bp->wol)
b6016b76
MC		 4480 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4481 else
4482 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4483 bnx2_reset_chip(bp, reset_code);
4484 free_irq(bp->pdev->irq, dev);
4485 if (bp->flags & USING_MSI_FLAG) {
4486 pci_disable_msi(bp->pdev);
4487 bp->flags &= ~USING_MSI_FLAG;
4488 }
4489 bnx2_free_skbs(bp);
4490 bnx2_free_mem(bp);
4491 bp->link_up = 0;
4492 netif_carrier_off(bp->dev);
829ca9a3 4493 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 4494 return 0;
4495}
4496
4497#define GET_NET_STATS64(ctr) \
4498 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4499 (unsigned long) (ctr##_lo)
4500
4501#define GET_NET_STATS32(ctr) \
4502 (ctr##_lo)
4503
4504#if (BITS_PER_LONG == 64)
4505#define GET_NET_STATS GET_NET_STATS64
4506#else
4507#define GET_NET_STATS GET_NET_STATS32
4508#endif
4509
4510static struct net_device_stats *
4511bnx2_get_stats(struct net_device *dev)
4512{
4513 struct bnx2 *bp = dev->priv;
4514 struct statistics_block *stats_blk = bp->stats_blk;
4515 struct net_device_stats *net_stats = &bp->net_stats;
4516
4517 if (bp->stats_blk == NULL) {
4518 return net_stats;
4519 }
4520 net_stats->rx_packets =
4521 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4522 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4523 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4524
4525 net_stats->tx_packets =
4526 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4527 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4528 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4529
4530 net_stats->rx_bytes =
4531 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4532
4533 net_stats->tx_bytes =
4534 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4535
4536 net_stats->multicast =
4537 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4538
4539 net_stats->collisions =
4540 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4541
4542 net_stats->rx_length_errors =
4543 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4544 stats_blk->stat_EtherStatsOverrsizePkts);
4545
4546 net_stats->rx_over_errors =
4547 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4548
4549 net_stats->rx_frame_errors =
4550 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4551
4552 net_stats->rx_crc_errors =
4553 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4554
4555 net_stats->rx_errors = net_stats->rx_length_errors +
4556 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4557 net_stats->rx_crc_errors;
4558
4559 net_stats->tx_aborted_errors =
4560 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4561 stats_blk->stat_Dot3StatsLateCollisions);
4562
5b0c76ad
MC		 4563 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4564 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 4565 net_stats->tx_carrier_errors = 0;
4566 else {
4567 net_stats->tx_carrier_errors =
4568 (unsigned long)
4569 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4570 }
4571
4572 net_stats->tx_errors =
4573 (unsigned long)
4574 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4575 +
4576 net_stats->tx_aborted_errors +
4577 net_stats->tx_carrier_errors;
4578
4579 return net_stats;
4580}
4581
4582/* All ethtool functions called with rtnl_lock */
4583
4584static int
4585bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4586{
4587 struct bnx2 *bp = dev->priv;
4588
4589 cmd->supported = SUPPORTED_Autoneg;
4590 if (bp->phy_flags & PHY_SERDES_FLAG) {
4591 cmd->supported |= SUPPORTED_1000baseT_Full |
4592 SUPPORTED_FIBRE;
4593
4594 cmd->port = PORT_FIBRE;
4595 }
4596 else {
4597 cmd->supported |= SUPPORTED_10baseT_Half |
4598 SUPPORTED_10baseT_Full |
4599 SUPPORTED_100baseT_Half |
4600 SUPPORTED_100baseT_Full |
4601 SUPPORTED_1000baseT_Full |
4602 SUPPORTED_TP;
4603
4604 cmd->port = PORT_TP;
4605 }
4606
4607 cmd->advertising = bp->advertising;
4608
4609 if (bp->autoneg & AUTONEG_SPEED) {
4610 cmd->autoneg = AUTONEG_ENABLE;
4611 }
4612 else {
4613 cmd->autoneg = AUTONEG_DISABLE;
4614 }
4615
4616 if (netif_carrier_ok(dev)) {
4617 cmd->speed = bp->line_speed;
4618 cmd->duplex = bp->duplex;
4619 }
4620 else {
4621 cmd->speed = -1;
4622 cmd->duplex = -1;
4623 }
4624
4625 cmd->transceiver = XCVR_INTERNAL;
4626 cmd->phy_address = bp->phy_addr;
4627
4628 return 0;
4629}
4630
4631static int
4632bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4633{
4634 struct bnx2 *bp = dev->priv;
4635 u8 autoneg = bp->autoneg;
4636 u8 req_duplex = bp->req_duplex;
4637 u16 req_line_speed = bp->req_line_speed;
4638 u32 advertising = bp->advertising;
4639
4640 if (cmd->autoneg == AUTONEG_ENABLE) {
4641 autoneg |= AUTONEG_SPEED;
4642
4643 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4644
4645 /* allow advertising 1 speed */
4646 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4647 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4648 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4649 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4650
4651 if (bp->phy_flags & PHY_SERDES_FLAG)
4652 return -EINVAL;
4653
4654 advertising = cmd->advertising;
4655
4656 }
4657 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4658 advertising = cmd->advertising;
4659 }
4660 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4661 return -EINVAL;
4662 }
4663 else {
4664 if (bp->phy_flags & PHY_SERDES_FLAG) {
4665 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4666 }
4667 else {
4668 advertising = ETHTOOL_ALL_COPPER_SPEED;
4669 }
4670 }
4671 advertising |= ADVERTISED_Autoneg;
4672 }
4673 else {
4674 if (bp->phy_flags & PHY_SERDES_FLAG) {
4675 if ((cmd->speed != SPEED_1000) ||
4676 (cmd->duplex != DUPLEX_FULL)) {
4677 return -EINVAL;
4678 }
4679 }
4680 else if (cmd->speed == SPEED_1000) {
4681 return -EINVAL;
4682 }
4683 autoneg &= ~AUTONEG_SPEED;
4684 req_line_speed = cmd->speed;
4685 req_duplex = cmd->duplex;
4686 advertising = 0;
4687 }
4688
4689 bp->autoneg = autoneg;
4690 bp->advertising = advertising;
4691 bp->req_line_speed = req_line_speed;
4692 bp->req_duplex = req_duplex;
4693
c770a65c 4694 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4695
4696 bnx2_setup_phy(bp);
4697
c770a65c 4698 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4699
4700 return 0;
4701}
4702
4703static void
4704bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4705{
4706 struct bnx2 *bp = dev->priv;
4707
4708 strcpy(info->driver, DRV_MODULE_NAME);
4709 strcpy(info->version, DRV_MODULE_VERSION);
4710 strcpy(info->bus_info, pci_name(bp->pdev));
4711 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4712 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4713 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4714 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4715 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4716 info->fw_version[7] = 0;
4717}
4718
4719static void
4720bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4721{
4722 struct bnx2 *bp = dev->priv;
4723
4724 if (bp->flags & NO_WOL_FLAG) {
4725 wol->supported = 0;
4726 wol->wolopts = 0;
4727 }
4728 else {
4729 wol->supported = WAKE_MAGIC;
4730 if (bp->wol)
4731 wol->wolopts = WAKE_MAGIC;
4732 else
4733 wol->wolopts = 0;
4734 }
4735 memset(&wol->sopass, 0, sizeof(wol->sopass));
4736}
4737
4738static int
4739bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4740{
4741 struct bnx2 *bp = dev->priv;
4742
4743 if (wol->wolopts & ~WAKE_MAGIC)
4744 return -EINVAL;
4745
4746 if (wol->wolopts & WAKE_MAGIC) {
4747 if (bp->flags & NO_WOL_FLAG)
4748 return -EINVAL;
4749
4750 bp->wol = 1;
4751 }
4752 else {
4753 bp->wol = 0;
4754 }
4755 return 0;
4756}
4757
4758static int
4759bnx2_nway_reset(struct net_device *dev)
4760{
4761 struct bnx2 *bp = dev->priv;
4762 u32 bmcr;
4763
4764 if (!(bp->autoneg & AUTONEG_SPEED)) {
4765 return -EINVAL;
4766 }
4767
c770a65c 4768 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4769
4770 /* Force a link down visible on the other side */
4771 if (bp->phy_flags & PHY_SERDES_FLAG) {
4772 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
c770a65c 4773 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4774
4775 msleep(20);
4776
c770a65c 4777 spin_lock_bh(&bp->phy_lock);
b6016b76 4778 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
cd339a0e
MC		 4779 bp->current_interval = SERDES_AN_TIMEOUT;
4780 bp->serdes_an_pending = 1;
4781 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4782 }
4783 }
4784
4785 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4786 bmcr &= ~BMCR_LOOPBACK;
4787 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4788
c770a65c 4789 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4790
4791 return 0;
4792}
4793
4794static int
4795bnx2_get_eeprom_len(struct net_device *dev)
4796{
4797 struct bnx2 *bp = dev->priv;
4798
4799 if (bp->flash_info == 0)
4800 return 0;
4801
4802 return (int) bp->flash_info->total_size;
4803}
4804
4805static int
4806bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4807 u8 *eebuf)
4808{
4809 struct bnx2 *bp = dev->priv;
4810 int rc;
4811
1064e944 4812 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 4813
4814 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4815
4816 return rc;
4817}
4818
4819static int
4820bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4821 u8 *eebuf)
4822{
4823 struct bnx2 *bp = dev->priv;
4824 int rc;
4825
1064e944 4826 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 4827
4828 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4829
4830 return rc;
4831}
4832
4833static int
4834bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4835{
4836 struct bnx2 *bp = dev->priv;
4837
4838 memset(coal, 0, sizeof(struct ethtool_coalesce));
4839
4840 coal->rx_coalesce_usecs = bp->rx_ticks;
4841 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4842 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4843 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4844
4845 coal->tx_coalesce_usecs = bp->tx_ticks;
4846 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4847 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4848 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4849
4850 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4851
4852 return 0;
4853}
4854
4855static int
4856bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4857{
4858 struct bnx2 *bp = dev->priv;
4859
4860 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4861 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4862
4863 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4864 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4865
4866 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4867 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4868
4869 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4870 if (bp->rx_quick_cons_trip_int > 0xff)
4871 bp->rx_quick_cons_trip_int = 0xff;
4872
4873 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4874 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4875
4876 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4877 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4878
4879 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4880 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4881
4882 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4883 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4884 0xff;
4885
4886 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4887 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4888 bp->stats_ticks &= 0xffff00;
4889
4890 if (netif_running(bp->dev)) {
4891 bnx2_netif_stop(bp);
4892 bnx2_init_nic(bp);
4893 bnx2_netif_start(bp);
4894 }
4895
4896 return 0;
4897}
4898
4899static void
4900bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4901{
4902 struct bnx2 *bp = dev->priv;
4903
4904 ering->rx_max_pending = MAX_RX_DESC_CNT;
4905 ering->rx_mini_max_pending = 0;
4906 ering->rx_jumbo_max_pending = 0;
4907
4908 ering->rx_pending = bp->rx_ring_size;
4909 ering->rx_mini_pending = 0;
4910 ering->rx_jumbo_pending = 0;
4911
4912 ering->tx_max_pending = MAX_TX_DESC_CNT;
4913 ering->tx_pending = bp->tx_ring_size;
4914}
4915
4916static int
4917bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4918{
4919 struct bnx2 *bp = dev->priv;
4920
4921 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4922 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4923 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4924
4925 return -EINVAL;
4926 }
4927 bp->rx_ring_size = ering->rx_pending;
4928 bp->tx_ring_size = ering->tx_pending;
4929
4930 if (netif_running(bp->dev)) {
4931 bnx2_netif_stop(bp);
4932 bnx2_init_nic(bp);
4933 bnx2_netif_start(bp);
4934 }
4935
4936 return 0;
4937}
4938
4939static void
4940bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4941{
4942 struct bnx2 *bp = dev->priv;
4943
4944 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4945 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4946 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4947}
4948
4949static int
4950bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4951{
4952 struct bnx2 *bp = dev->priv;
4953
4954 bp->req_flow_ctrl = 0;
4955 if (epause->rx_pause)
4956 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4957 if (epause->tx_pause)
4958 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4959
4960 if (epause->autoneg) {
4961 bp->autoneg |= AUTONEG_FLOW_CTRL;
4962 }
4963 else {
4964 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4965 }
4966
c770a65c 4967 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4968
4969 bnx2_setup_phy(bp);
4970
c770a65c 4971 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4972
4973 return 0;
4974}
4975
4976static u32
4977bnx2_get_rx_csum(struct net_device *dev)
4978{
4979 struct bnx2 *bp = dev->priv;
4980
4981 return bp->rx_csum;
4982}
4983
4984static int
4985bnx2_set_rx_csum(struct net_device *dev, u32 data)
4986{
4987 struct bnx2 *bp = dev->priv;
4988
4989 bp->rx_csum = data;
4990 return 0;
4991}
4992
4993#define BNX2_NUM_STATS 45
4994
14ab9b86 4995static struct {
b6016b76
MC		 4996 char string[ETH_GSTRING_LEN];
4997} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4998 { "rx_bytes" },
4999 { "rx_error_bytes" },
5000 { "tx_bytes" },
5001 { "tx_error_bytes" },
5002 { "rx_ucast_packets" },
5003 { "rx_mcast_packets" },
5004 { "rx_bcast_packets" },
5005 { "tx_ucast_packets" },
5006 { "tx_mcast_packets" },
5007 { "tx_bcast_packets" },
5008 { "tx_mac_errors" },
5009 { "tx_carrier_errors" },
5010 { "rx_crc_errors" },
5011 { "rx_align_errors" },
5012 { "tx_single_collisions" },
5013 { "tx_multi_collisions" },
5014 { "tx_deferred" },
5015 { "tx_excess_collisions" },
5016 { "tx_late_collisions" },
5017 { "tx_total_collisions" },
5018 { "rx_fragments" },
5019 { "rx_jabbers" },
5020 { "rx_undersize_packets" },
5021 { "rx_oversize_packets" },
5022 { "rx_64_byte_packets" },
5023 { "rx_65_to_127_byte_packets" },
5024 { "rx_128_to_255_byte_packets" },
5025 { "rx_256_to_511_byte_packets" },
5026 { "rx_512_to_1023_byte_packets" },
5027 { "rx_1024_to_1522_byte_packets" },
5028 { "rx_1523_to_9022_byte_packets" },
5029 { "tx_64_byte_packets" },
5030 { "tx_65_to_127_byte_packets" },
5031 { "tx_128_to_255_byte_packets" },
5032 { "tx_256_to_511_byte_packets" },
5033 { "tx_512_to_1023_byte_packets" },
5034 { "tx_1024_to_1522_byte_packets" },
5035 { "tx_1523_to_9022_byte_packets" },
5036 { "rx_xon_frames" },
5037 { "rx_xoff_frames" },
5038 { "tx_xon_frames" },
5039 { "tx_xoff_frames" },
5040 { "rx_mac_ctrl_frames" },
5041 { "rx_filtered_packets" },
5042 { "rx_discards" },
5043};
5044
5045#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5046
14ab9b86 5047static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 5048 STATS_OFFSET32(stat_IfHCInOctets_hi),
5049 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5050 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5051 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5052 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5053 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5054 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5055 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5056 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5057 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5058 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5059 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5060 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5061 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5062 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5063 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5064 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5065 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5066 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5067 STATS_OFFSET32(stat_EtherStatsCollisions),
5068 STATS_OFFSET32(stat_EtherStatsFragments),
5069 STATS_OFFSET32(stat_EtherStatsJabbers),
5070 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5071 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5072 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5073 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5074 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5075 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5076 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5077 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5078 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5079 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5080 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5081 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5082 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5083 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5084 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5085 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5086 STATS_OFFSET32(stat_XonPauseFramesReceived),
5087 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5088 STATS_OFFSET32(stat_OutXonSent),
5089 STATS_OFFSET32(stat_OutXoffSent),
5090 STATS_OFFSET32(stat_MacControlFramesReceived),
5091 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5092 STATS_OFFSET32(stat_IfInMBUFDiscards),
5093};
5094
5095/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5096 * skipped because of errata.
5097 */
14ab9b86 5098static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 5099 8,0,8,8,8,8,8,8,8,8,
5100 4,0,4,4,4,4,4,4,4,4,
5101 4,4,4,4,4,4,4,4,4,4,
5102 4,4,4,4,4,4,4,4,4,4,
5103 4,4,4,4,4,
5104};
5105
5b0c76ad
MC		 5106static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5107 8,0,8,8,8,8,8,8,8,8,
5108 4,4,4,4,4,4,4,4,4,4,
5109 4,4,4,4,4,4,4,4,4,4,
5110 4,4,4,4,4,4,4,4,4,4,
5111 4,4,4,4,4,
5112};
5113
b6016b76
MC		 5114#define BNX2_NUM_TESTS 6
5115
14ab9b86 5116static struct {
b6016b76
MC		 5117 char string[ETH_GSTRING_LEN];
5118} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5119 { "register_test (offline)" },
5120 { "memory_test (offline)" },
5121 { "loopback_test (offline)" },
5122 { "nvram_test (online)" },
5123 { "interrupt_test (online)" },
5124 { "link_test (online)" },
5125};
5126
5127static int
5128bnx2_self_test_count(struct net_device *dev)
5129{
5130 return BNX2_NUM_TESTS;
5131}
5132
5133static void
5134bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5135{
5136 struct bnx2 *bp = dev->priv;
5137
5138 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5139 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5140 bnx2_netif_stop(bp);
5141 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5142 bnx2_free_skbs(bp);
5143
5144 if (bnx2_test_registers(bp) != 0) {
5145 buf[0] = 1;
5146 etest->flags |= ETH_TEST_FL_FAILED;
5147 }
5148 if (bnx2_test_memory(bp) != 0) {
5149 buf[1] = 1;
5150 etest->flags |= ETH_TEST_FL_FAILED;
5151 }
5152 if (bnx2_test_loopback(bp) != 0) {
5153 buf[2] = 1;
5154 etest->flags |= ETH_TEST_FL_FAILED;
5155 }
5156
5157 if (!netif_running(bp->dev)) {
5158 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5159 }
5160 else {
5161 bnx2_init_nic(bp);
5162 bnx2_netif_start(bp);
5163 }
5164
5165 /* wait for link up */
5166 msleep_interruptible(3000);
5167 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5168 msleep_interruptible(4000);
5169 }
5170
5171 if (bnx2_test_nvram(bp) != 0) {
5172 buf[3] = 1;
5173 etest->flags |= ETH_TEST_FL_FAILED;
5174 }
5175 if (bnx2_test_intr(bp) != 0) {
5176 buf[4] = 1;
5177 etest->flags |= ETH_TEST_FL_FAILED;
5178 }
5179
5180 if (bnx2_test_link(bp) != 0) {
5181 buf[5] = 1;
5182 etest->flags |= ETH_TEST_FL_FAILED;
5183
5184 }
5185}
5186
5187static void
5188bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5189{
5190 switch (stringset) {
5191 case ETH_SS_STATS:
5192 memcpy(buf, bnx2_stats_str_arr,
5193 sizeof(bnx2_stats_str_arr));
5194 break;
5195 case ETH_SS_TEST:
5196 memcpy(buf, bnx2_tests_str_arr,
5197 sizeof(bnx2_tests_str_arr));
5198 break;
5199 }
5200}
5201
5202static int
5203bnx2_get_stats_count(struct net_device *dev)
5204{
5205 return BNX2_NUM_STATS;
5206}
5207
5208static void
5209bnx2_get_ethtool_stats(struct net_device *dev,
5210 struct ethtool_stats *stats, u64 *buf)
5211{
5212 struct bnx2 *bp = dev->priv;
5213 int i;
5214 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 5215 u8 *stats_len_arr = NULL;
b6016b76
MC		 5216
5217 if (hw_stats == NULL) {
5218 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5219 return;
5220 }
5221
5b0c76ad
MC		 5222 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5223 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5224 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5225 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 5226 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 5227 else
5228 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 5229
5230 for (i = 0; i < BNX2_NUM_STATS; i++) {
5231 if (stats_len_arr[i] == 0) {
5232 /* skip this counter */
5233 buf[i] = 0;
5234 continue;
5235 }
5236 if (stats_len_arr[i] == 4) {
5237 /* 4-byte counter */
5238 buf[i] = (u64)
5239 *(hw_stats + bnx2_stats_offset_arr[i]);
5240 continue;
5241 }
5242 /* 8-byte counter */
5243 buf[i] = (((u64) *(hw_stats +
5244 bnx2_stats_offset_arr[i])) << 32) +
5245 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5246 }
5247}
5248
5249static int
5250bnx2_phys_id(struct net_device *dev, u32 data)
5251{
5252 struct bnx2 *bp = dev->priv;
5253 int i;
5254 u32 save;
5255
5256 if (data == 0)
5257 data = 2;
5258
5259 save = REG_RD(bp, BNX2_MISC_CFG);
5260 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5261
5262 for (i = 0; i < (data * 2); i++) {
5263 if ((i % 2) == 0) {
5264 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5265 }
5266 else {
5267 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5268 BNX2_EMAC_LED_1000MB_OVERRIDE |
5269 BNX2_EMAC_LED_100MB_OVERRIDE |
5270 BNX2_EMAC_LED_10MB_OVERRIDE |
5271 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5272 BNX2_EMAC_LED_TRAFFIC);
5273 }
5274 msleep_interruptible(500);
5275 if (signal_pending(current))
5276 break;
5277 }
5278 REG_WR(bp, BNX2_EMAC_LED, 0);
5279 REG_WR(bp, BNX2_MISC_CFG, save);
5280 return 0;
5281}
5282
5283static struct ethtool_ops bnx2_ethtool_ops = {
5284 .get_settings = bnx2_get_settings,
5285 .set_settings = bnx2_set_settings,
5286 .get_drvinfo = bnx2_get_drvinfo,
5287 .get_wol = bnx2_get_wol,
5288 .set_wol = bnx2_set_wol,
5289 .nway_reset = bnx2_nway_reset,
5290 .get_link = ethtool_op_get_link,
5291 .get_eeprom_len = bnx2_get_eeprom_len,
5292 .get_eeprom = bnx2_get_eeprom,
5293 .set_eeprom = bnx2_set_eeprom,
5294 .get_coalesce = bnx2_get_coalesce,
5295 .set_coalesce = bnx2_set_coalesce,
5296 .get_ringparam = bnx2_get_ringparam,
5297 .set_ringparam = bnx2_set_ringparam,
5298 .get_pauseparam = bnx2_get_pauseparam,
5299 .set_pauseparam = bnx2_set_pauseparam,
5300 .get_rx_csum = bnx2_get_rx_csum,
5301 .set_rx_csum = bnx2_set_rx_csum,
5302 .get_tx_csum = ethtool_op_get_tx_csum,
5303 .set_tx_csum = ethtool_op_set_tx_csum,
5304 .get_sg = ethtool_op_get_sg,
5305 .set_sg = ethtool_op_set_sg,
5306#ifdef BCM_TSO
5307 .get_tso = ethtool_op_get_tso,
5308 .set_tso = ethtool_op_set_tso,
5309#endif
5310 .self_test_count = bnx2_self_test_count,
5311 .self_test = bnx2_self_test,
5312 .get_strings = bnx2_get_strings,
5313 .phys_id = bnx2_phys_id,
5314 .get_stats_count = bnx2_get_stats_count,
5315 .get_ethtool_stats = bnx2_get_ethtool_stats,
24b8e05d 5316 .get_perm_addr = ethtool_op_get_perm_addr,
b6016b76
MC		 5317};
5318
5319/* Called with rtnl_lock */
5320static int
5321bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5322{
14ab9b86 5323 struct mii_ioctl_data *data = if_mii(ifr);
b6016b76
MC		 5324 struct bnx2 *bp = dev->priv;
5325 int err;
5326
5327 switch(cmd) {
5328 case SIOCGMIIPHY:
5329 data->phy_id = bp->phy_addr;
5330
5331 /* fallthru */
5332 case SIOCGMIIREG: {
5333 u32 mii_regval;
5334
c770a65c 5335 spin_lock_bh(&bp->phy_lock);
b6016b76 5336 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 5337 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5338
5339 data->val_out = mii_regval;
5340
5341 return err;
5342 }
5343
5344 case SIOCSMIIREG:
5345 if (!capable(CAP_NET_ADMIN))
5346 return -EPERM;
5347
c770a65c 5348 spin_lock_bh(&bp->phy_lock);
b6016b76 5349 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 5350 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5351
5352 return err;
5353
5354 default:
5355 /* do nothing */
5356 break;
5357 }
5358 return -EOPNOTSUPP;
5359}
5360
5361/* Called with rtnl_lock */
5362static int
5363bnx2_change_mac_addr(struct net_device *dev, void *p)
5364{
5365 struct sockaddr *addr = p;
5366 struct bnx2 *bp = dev->priv;
5367
73eef4cd
MC		 5368 if (!is_valid_ether_addr(addr->sa_data))
5369 return -EINVAL;
5370
b6016b76
MC		 5371 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5372 if (netif_running(dev))
5373 bnx2_set_mac_addr(bp);
5374
5375 return 0;
5376}
5377
5378/* Called with rtnl_lock */
5379static int
5380bnx2_change_mtu(struct net_device *dev, int new_mtu)
5381{
5382 struct bnx2 *bp = dev->priv;
5383
5384 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5385 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5386 return -EINVAL;
5387
5388 dev->mtu = new_mtu;
5389 if (netif_running(dev)) {
5390 bnx2_netif_stop(bp);
5391
5392 bnx2_init_nic(bp);
5393
5394 bnx2_netif_start(bp);
5395 }
5396 return 0;
5397}
5398
5399#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5400static void
5401poll_bnx2(struct net_device *dev)
5402{
5403 struct bnx2 *bp = dev->priv;
5404
5405 disable_irq(bp->pdev->irq);
5406 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5407 enable_irq(bp->pdev->irq);
5408}
5409#endif
5410
5411static int __devinit
5412bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5413{
5414 struct bnx2 *bp;
5415 unsigned long mem_len;
5416 int rc;
5417 u32 reg;
5418
5419 SET_MODULE_OWNER(dev);
5420 SET_NETDEV_DEV(dev, &pdev->dev);
5421 bp = dev->priv;
5422
5423 bp->flags = 0;
5424 bp->phy_flags = 0;
5425
5426 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5427 rc = pci_enable_device(pdev);
5428 if (rc) {
5429 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5430 goto err_out;
5431 }
5432
5433 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5434 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5435 "aborting.\n");
5436 rc = -ENODEV;
5437 goto err_out_disable;
5438 }
5439
5440 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5441 if (rc) {
5442 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5443 goto err_out_disable;
5444 }
5445
5446 pci_set_master(pdev);
5447
5448 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5449 if (bp->pm_cap == 0) {
5450 printk(KERN_ERR PFX "Cannot find power management capability, "
5451 "aborting.\n");
5452 rc = -EIO;
5453 goto err_out_release;
5454 }
5455
5456 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5457 if (bp->pcix_cap == 0) {
5458 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5459 rc = -EIO;
5460 goto err_out_release;
5461 }
5462
5463 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5464 bp->flags |= USING_DAC_FLAG;
5465 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5466 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5467 "failed, aborting.\n");
5468 rc = -EIO;
5469 goto err_out_release;
5470 }
5471 }
5472 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5473 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5474 rc = -EIO;
5475 goto err_out_release;
5476 }
5477
5478 bp->dev = dev;
5479 bp->pdev = pdev;
5480
5481 spin_lock_init(&bp->phy_lock);
5482 spin_lock_init(&bp->tx_lock);
5483 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5484
5485 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5486 mem_len = MB_GET_CID_ADDR(17);
5487 dev->mem_end = dev->mem_start + mem_len;
5488 dev->irq = pdev->irq;
5489
5490 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5491
5492 if (!bp->regview) {
5493 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5494 rc = -ENOMEM;
5495 goto err_out_release;
5496 }
5497
5498 /* Configure byte swap and enable write to the reg_window registers.
5499 * Rely on CPU to do target byte swapping on big endian systems
5500 * The chip's target access swapping will not swap all accesses
5501 */
5502 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5503 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5504 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5505
829ca9a3 5506 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5507
5508 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5509
b6016b76
MC		 5510 /* Get bus information. */
5511 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5512 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5513 u32 clkreg;
5514
5515 bp->flags |= PCIX_FLAG;
5516
5517 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5518
5519 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5520 switch (clkreg) {
5521 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5522 bp->bus_speed_mhz = 133;
5523 break;
5524
5525 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5526 bp->bus_speed_mhz = 100;
5527 break;
5528
5529 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5530 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5531 bp->bus_speed_mhz = 66;
5532 break;
5533
5534 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5535 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5536 bp->bus_speed_mhz = 50;
5537 break;
5538
5539 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5540 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5541 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5542 bp->bus_speed_mhz = 33;
5543 break;
5544 }
5545 }
5546 else {
5547 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5548 bp->bus_speed_mhz = 66;
5549 else
5550 bp->bus_speed_mhz = 33;
5551 }
5552
5553 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5554 bp->flags |= PCI_32BIT_FLAG;
5555
5556 /* 5706A0 may falsely detect SERR and PERR. */
5557 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5558 reg = REG_RD(bp, PCI_COMMAND);
5559 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5560 REG_WR(bp, PCI_COMMAND, reg);
5561 }
5562 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5563 !(bp->flags & PCIX_FLAG)) {
5564
5565 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5566 "aborting.\n");
5567 goto err_out_unmap;
5568 }
5569
5570 bnx2_init_nvram(bp);
5571
e3648b3d
MC		 5572 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5573
5574 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5575 BNX2_SHM_HDR_SIGNATURE_SIG)
5576 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5577 else
5578 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5579
b6016b76
MC		 5580 /* Get the permanent MAC address. First we need to make sure the
5581 * firmware is actually running.
5582 */
e3648b3d 5583 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 5584
5585 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5586 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5587 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5588 rc = -ENODEV;
5589 goto err_out_unmap;
5590 }
5591
e3648b3d 5592 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
b6016b76 5593
e3648b3d 5594 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 5595 bp->mac_addr[0] = (u8) (reg >> 8);
5596 bp->mac_addr[1] = (u8) reg;
5597
e3648b3d 5598 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 5599 bp->mac_addr[2] = (u8) (reg >> 24);
5600 bp->mac_addr[3] = (u8) (reg >> 16);
5601 bp->mac_addr[4] = (u8) (reg >> 8);
5602 bp->mac_addr[5] = (u8) reg;
5603
5604 bp->tx_ring_size = MAX_TX_DESC_CNT;
5605 bp->rx_ring_size = 100;
5606
5607 bp->rx_csum = 1;
5608
5609 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5610
5611 bp->tx_quick_cons_trip_int = 20;
5612 bp->tx_quick_cons_trip = 20;
5613 bp->tx_ticks_int = 80;
5614 bp->tx_ticks = 80;
5615
5616 bp->rx_quick_cons_trip_int = 6;
5617 bp->rx_quick_cons_trip = 6;
5618 bp->rx_ticks_int = 18;
5619 bp->rx_ticks = 18;
5620
5621 bp->stats_ticks = 1000000 & 0xffff00;
5622
5623 bp->timer_interval = HZ;
cd339a0e 5624 bp->current_interval = HZ;
b6016b76 5625
5b0c76ad
MC		 5626 bp->phy_addr = 1;
5627
b6016b76
MC		 5628 /* Disable WOL support if we are running on a SERDES chip. */
5629 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5630 bp->phy_flags |= PHY_SERDES_FLAG;
5631 bp->flags |= NO_WOL_FLAG;
5b0c76ad
MC		 5632 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5633 bp->phy_addr = 2;
e3648b3d 5634 reg = REG_RD_IND(bp, bp->shmem_base +
5b0c76ad
MC		 5635 BNX2_SHARED_HW_CFG_CONFIG);
5636 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5637 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5638 }
b6016b76
MC		 5639 }
5640
dda1e390
MC		 5641 if (CHIP_NUM(bp) == CHIP_NUM_5708)
5642 bp->flags |= NO_WOL_FLAG;
5643
b6016b76
MC		 5644 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5645 bp->tx_quick_cons_trip_int =
5646 bp->tx_quick_cons_trip;
5647 bp->tx_ticks_int = bp->tx_ticks;
5648 bp->rx_quick_cons_trip_int =
5649 bp->rx_quick_cons_trip;
5650 bp->rx_ticks_int = bp->rx_ticks;
5651 bp->comp_prod_trip_int = bp->comp_prod_trip;
5652 bp->com_ticks_int = bp->com_ticks;
5653 bp->cmd_ticks_int = bp->cmd_ticks;
5654 }
5655
5656 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5657 bp->req_line_speed = 0;
5658 if (bp->phy_flags & PHY_SERDES_FLAG) {
5659 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
cd339a0e 5660
e3648b3d 5661 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
cd339a0e
MC		 5662 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5663 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5664 bp->autoneg = 0;
5665 bp->req_line_speed = bp->line_speed = SPEED_1000;
5666 bp->req_duplex = DUPLEX_FULL;
5667 }
b6016b76
MC		 5668 }
5669 else {
5670 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5671 }
5672
5673 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5674
cd339a0e
MC		 5675 init_timer(&bp->timer);
5676 bp->timer.expires = RUN_AT(bp->timer_interval);
5677 bp->timer.data = (unsigned long) bp;
5678 bp->timer.function = bnx2_timer;
5679
b6016b76
MC		 5680 return 0;
5681
5682err_out_unmap:
5683 if (bp->regview) {
5684 iounmap(bp->regview);
73eef4cd 5685 bp->regview = NULL;
b6016b76
MC		 5686 }
5687
5688err_out_release:
5689 pci_release_regions(pdev);
5690
5691err_out_disable:
5692 pci_disable_device(pdev);
5693 pci_set_drvdata(pdev, NULL);
5694
5695err_out:
5696 return rc;
5697}
5698
5699static int __devinit
5700bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5701{
5702 static int version_printed = 0;
5703 struct net_device *dev = NULL;
5704 struct bnx2 *bp;
5705 int rc, i;
5706
5707 if (version_printed++ == 0)
5708 printk(KERN_INFO "%s", version);
5709
5710 /* dev zeroed in init_etherdev */
5711 dev = alloc_etherdev(sizeof(*bp));
5712
5713 if (!dev)
5714 return -ENOMEM;
5715
5716 rc = bnx2_init_board(pdev, dev);
5717 if (rc < 0) {
5718 free_netdev(dev);
5719 return rc;
5720 }
5721
5722 dev->open = bnx2_open;
5723 dev->hard_start_xmit = bnx2_start_xmit;
5724 dev->stop = bnx2_close;
5725 dev->get_stats = bnx2_get_stats;
5726 dev->set_multicast_list = bnx2_set_rx_mode;
5727 dev->do_ioctl = bnx2_ioctl;
5728 dev->set_mac_address = bnx2_change_mac_addr;
5729 dev->change_mtu = bnx2_change_mtu;
5730 dev->tx_timeout = bnx2_tx_timeout;
5731 dev->watchdog_timeo = TX_TIMEOUT;
5732#ifdef BCM_VLAN
5733 dev->vlan_rx_register = bnx2_vlan_rx_register;
5734 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5735#endif
5736 dev->poll = bnx2_poll;
5737 dev->ethtool_ops = &bnx2_ethtool_ops;
5738 dev->weight = 64;
5739
5740 bp = dev->priv;
5741
5742#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5743 dev->poll_controller = poll_bnx2;
5744#endif
5745
5746 if ((rc = register_netdev(dev))) {
5747 printk(KERN_ERR PFX "Cannot register net device\n");
5748 if (bp->regview)
5749 iounmap(bp->regview);
5750 pci_release_regions(pdev);
5751 pci_disable_device(pdev);
5752 pci_set_drvdata(pdev, NULL);
5753 free_netdev(dev);
5754 return rc;
5755 }
5756
5757 pci_set_drvdata(pdev, dev);
5758
5759 memcpy(dev->dev_addr, bp->mac_addr, 6);
24b8e05d 5760 memcpy(dev->perm_addr, bp->mac_addr, 6);
b6016b76
MC		 5761 bp->name = board_info[ent->driver_data].name,
5762 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5763 "IRQ %d, ",
5764 dev->name,
5765 bp->name,
5766 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5767 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5768 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5769 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5770 bp->bus_speed_mhz,
5771 dev->base_addr,
5772 bp->pdev->irq);
5773
5774 printk("node addr ");
5775 for (i = 0; i < 6; i++)
5776 printk("%2.2x", dev->dev_addr[i]);
5777 printk("\n");
5778
5779 dev->features |= NETIF_F_SG;
5780 if (bp->flags & USING_DAC_FLAG)
5781 dev->features |= NETIF_F_HIGHDMA;
5782 dev->features |= NETIF_F_IP_CSUM;
5783#ifdef BCM_VLAN
5784 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5785#endif
5786#ifdef BCM_TSO
5787 dev->features |= NETIF_F_TSO;
5788#endif
5789
5790 netif_carrier_off(bp->dev);
5791
5792 return 0;
5793}
5794
5795static void __devexit
5796bnx2_remove_one(struct pci_dev *pdev)
5797{
5798 struct net_device *dev = pci_get_drvdata(pdev);
5799 struct bnx2 *bp = dev->priv;
5800
afdc08b9
MC		 5801 flush_scheduled_work();
5802
b6016b76
MC		 5803 unregister_netdev(dev);
5804
5805 if (bp->regview)
5806 iounmap(bp->regview);
5807
5808 free_netdev(dev);
5809 pci_release_regions(pdev);
5810 pci_disable_device(pdev);
5811 pci_set_drvdata(pdev, NULL);
5812}
5813
5814static int
829ca9a3 5815bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 5816{
5817 struct net_device *dev = pci_get_drvdata(pdev);
5818 struct bnx2 *bp = dev->priv;
5819 u32 reset_code;
5820
5821 if (!netif_running(dev))
5822 return 0;
5823
5824 bnx2_netif_stop(bp);
5825 netif_device_detach(dev);
5826 del_timer_sync(&bp->timer);
dda1e390
MC		 5827 if (bp->flags & NO_WOL_FLAG)
5828 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
5829 else if (bp->wol)
b6016b76
MC		 5830 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5831 else
5832 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5833 bnx2_reset_chip(bp, reset_code);
5834 bnx2_free_skbs(bp);
829ca9a3 5835 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 5836 return 0;
5837}
5838
5839static int
5840bnx2_resume(struct pci_dev *pdev)
5841{
5842 struct net_device *dev = pci_get_drvdata(pdev);
5843 struct bnx2 *bp = dev->priv;
5844
5845 if (!netif_running(dev))
5846 return 0;
5847
829ca9a3 5848 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5849 netif_device_attach(dev);
5850 bnx2_init_nic(bp);
5851 bnx2_netif_start(bp);
5852 return 0;
5853}
5854
5855static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 5856 .name = DRV_MODULE_NAME,
5857 .id_table = bnx2_pci_tbl,
5858 .probe = bnx2_init_one,
5859 .remove = __devexit_p(bnx2_remove_one),
5860 .suspend = bnx2_suspend,
5861 .resume = bnx2_resume,
b6016b76
MC		 5862};
5863
5864static int __init bnx2_init(void)
5865{
5866 return pci_module_init(&bnx2_pci_driver);
5867}
5868
5869static void __exit bnx2_cleanup(void)
5870{
5871 pci_unregister_driver(&bnx2_pci_driver);
5872}
5873
5874module_init(bnx2_init);
5875module_exit(bnx2_cleanup);
5876
5877
5878
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