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b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
feebb331 3 * Copyright (c) 2004-2008 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
1977f032 29#include <linux/bitops.h>
f2a4f052
MC		 30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
c86a31f4 34#include <asm/page.h>
f2a4f052
MC		 35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h>
40#define BCM_VLAN 1
41#endif
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
fba9fe91 49#include <linux/zlib.h>
f2a4f052 50
b6016b76
MC		 51#include "bnx2.h"
52#include "bnx2_fw.h"
d43584c8 53#include "bnx2_fw2.h"
b6016b76 54
110d0ef9 55#define FW_BUF_SIZE 0x10000
b3448b0b 56
b6016b76
MC		 57#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": "
feebb331
MC		 59#define DRV_MODULE_VERSION "1.7.2"
60#define DRV_MODULE_RELDATE "January 21, 2008"
b6016b76
MC		 61
62#define RUN_AT(x) (jiffies + (x))
63
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (5*HZ)
66
e19360f2 67static const char version[] __devinitdata =
b6016b76
MC		 68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 71MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 72MODULE_LICENSE("GPL");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75static int disable_msi = 0;
76
77module_param(disable_msi, int, 0);
78MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
5b0c76ad
MC		 86 BCM5708,
87 BCM5708S,
bac0dff6 88 BCM5709,
27a005b8 89 BCM5709S,
b6016b76
MC		 90} board_t;
91
92/* indexed by board_t, above */
f71e1309 93static const struct {
b6016b76
MC		 94 char *name;
95} board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
b6016b76
MC		 105 };
106
107static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
b6016b76
MC		 126 { 0, }
127};
128
129static struct flash_spec flash_table[] =
130{
e30372c9
MC		 131#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 133 /* Slow EEPROM */
37137709 134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
37137709
MC		 138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
b6016b76
MC		 143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
37137709 145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
37137709 151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
37137709
MC		 155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
b6016b76
MC		 216};
217
e30372c9
MC		 218static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225};
226
b6016b76
MC		 227MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
a550c99b 229static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
e89bbf10 230{
2f8af120 231 u32 diff;
e89bbf10 232
2f8af120 233 smp_mb();
faac9c4b
MC		 234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
a550c99b 238 diff = bp->tx_prod - bnapi->tx_cons;
faac9c4b
MC		 239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
e89bbf10
MC		 244 return (bp->tx_ring_size - diff);
245}
246
b6016b76
MC		 247static u32
248bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249{
1b8227c4
MC		 250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
b6016b76 253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
b6016b76
MC		 257}
258
259static void
260bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261{
1b8227c4 262 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 265 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 266}
267
268static void
269bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
270{
271 offset += cid_addr;
1b8227c4 272 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 273 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
274 int i;
275
276 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
277 REG_WR(bp, BNX2_CTX_CTX_CTRL,
278 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
279 for (i = 0; i < 5; i++) {
280 u32 val;
281 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
282 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
283 break;
284 udelay(5);
285 }
286 } else {
287 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
288 REG_WR(bp, BNX2_CTX_DATA, val);
289 }
1b8227c4 290 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 291}
292
293static int
294bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
295{
296 u32 val1;
297 int i, ret;
298
583c28e5 299 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 300 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
301 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
302
303 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
304 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
305
306 udelay(40);
307 }
308
309 val1 = (bp->phy_addr << 21) | (reg << 16) |
310 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
311 BNX2_EMAC_MDIO_COMM_START_BUSY;
312 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
313
314 for (i = 0; i < 50; i++) {
315 udelay(10);
316
317 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
318 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
319 udelay(5);
320
321 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
322 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
323
324 break;
325 }
326 }
327
328 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
329 *val = 0x0;
330 ret = -EBUSY;
331 }
332 else {
333 *val = val1;
334 ret = 0;
335 }
336
583c28e5 337 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 338 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
339 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
340
341 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
342 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
343
344 udelay(40);
345 }
346
347 return ret;
348}
349
350static int
351bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
352{
353 u32 val1;
354 int i, ret;
355
583c28e5 356 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 357 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
358 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
359
360 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
361 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
362
363 udelay(40);
364 }
365
366 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
367 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
368 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
369 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 370
b6016b76
MC		 371 for (i = 0; i < 50; i++) {
372 udelay(10);
373
374 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
375 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
376 udelay(5);
377 break;
378 }
379 }
380
381 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
382 ret = -EBUSY;
383 else
384 ret = 0;
385
583c28e5 386 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 387 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
388 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
389
390 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
391 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
392
393 udelay(40);
394 }
395
396 return ret;
397}
398
399static void
400bnx2_disable_int(struct bnx2 *bp)
401{
b4b36042
MC		 402 int i;
403 struct bnx2_napi *bnapi;
404
405 for (i = 0; i < bp->irq_nvecs; i++) {
406 bnapi = &bp->bnx2_napi[i];
407 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
408 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
409 }
b6016b76
MC		 410 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
411}
412
413static void
414bnx2_enable_int(struct bnx2 *bp)
415{
b4b36042
MC		 416 int i;
417 struct bnx2_napi *bnapi;
35efa7c1 418
b4b36042
MC		 419 for (i = 0; i < bp->irq_nvecs; i++) {
420 bnapi = &bp->bnx2_napi[i];
1269a8a6 421
b4b36042
MC		 422 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
423 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
424 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
425 bnapi->last_status_idx);
b6016b76 426
b4b36042
MC		 427 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
428 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
429 bnapi->last_status_idx);
430 }
bf5295bb 431 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 432}
433
434static void
435bnx2_disable_int_sync(struct bnx2 *bp)
436{
b4b36042
MC		 437 int i;
438
b6016b76
MC		 439 atomic_inc(&bp->intr_sem);
440 bnx2_disable_int(bp);
b4b36042
MC		 441 for (i = 0; i < bp->irq_nvecs; i++)
442 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 443}
444
35efa7c1
MC		 445static void
446bnx2_napi_disable(struct bnx2 *bp)
447{
b4b36042
MC		 448 int i;
449
450 for (i = 0; i < bp->irq_nvecs; i++)
451 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 452}
453
454static void
455bnx2_napi_enable(struct bnx2 *bp)
456{
b4b36042
MC		 457 int i;
458
459 for (i = 0; i < bp->irq_nvecs; i++)
460 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 461}
462
b6016b76
MC		 463static void
464bnx2_netif_stop(struct bnx2 *bp)
465{
466 bnx2_disable_int_sync(bp);
467 if (netif_running(bp->dev)) {
35efa7c1 468 bnx2_napi_disable(bp);
b6016b76
MC		 469 netif_tx_disable(bp->dev);
470 bp->dev->trans_start = jiffies; /* prevent tx timeout */
471 }
472}
473
474static void
475bnx2_netif_start(struct bnx2 *bp)
476{
477 if (atomic_dec_and_test(&bp->intr_sem)) {
478 if (netif_running(bp->dev)) {
479 netif_wake_queue(bp->dev);
35efa7c1 480 bnx2_napi_enable(bp);
b6016b76
MC		 481 bnx2_enable_int(bp);
482 }
483 }
484}
485
486static void
487bnx2_free_mem(struct bnx2 *bp)
488{
13daffa2
MC		 489 int i;
490
59b47d8a
MC		 491 for (i = 0; i < bp->ctx_pages; i++) {
492 if (bp->ctx_blk[i]) {
493 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
494 bp->ctx_blk[i],
495 bp->ctx_blk_mapping[i]);
496 bp->ctx_blk[i] = NULL;
497 }
498 }
b6016b76 499 if (bp->status_blk) {
0f31f994 500 pci_free_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 501 bp->status_blk, bp->status_blk_mapping);
502 bp->status_blk = NULL;
0f31f994 503 bp->stats_blk = NULL;
b6016b76
MC		 504 }
505 if (bp->tx_desc_ring) {
e343d55c 506 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 507 bp->tx_desc_ring, bp->tx_desc_mapping);
508 bp->tx_desc_ring = NULL;
509 }
b4558ea9
JJ		 510 kfree(bp->tx_buf_ring);
511 bp->tx_buf_ring = NULL;
13daffa2
MC		 512 for (i = 0; i < bp->rx_max_ring; i++) {
513 if (bp->rx_desc_ring[i])
e343d55c 514 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 515 bp->rx_desc_ring[i],
516 bp->rx_desc_mapping[i]);
517 bp->rx_desc_ring[i] = NULL;
518 }
519 vfree(bp->rx_buf_ring);
b4558ea9 520 bp->rx_buf_ring = NULL;
47bf4246
MC		 521 for (i = 0; i < bp->rx_max_pg_ring; i++) {
522 if (bp->rx_pg_desc_ring[i])
523 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
524 bp->rx_pg_desc_ring[i],
525 bp->rx_pg_desc_mapping[i]);
526 bp->rx_pg_desc_ring[i] = NULL;
527 }
528 if (bp->rx_pg_ring)
529 vfree(bp->rx_pg_ring);
530 bp->rx_pg_ring = NULL;
b6016b76
MC		 531}
532
533static int
534bnx2_alloc_mem(struct bnx2 *bp)
535{
0f31f994 536 int i, status_blk_size;
13daffa2 537
e343d55c 538 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
b6016b76
MC		 539 if (bp->tx_buf_ring == NULL)
540 return -ENOMEM;
541
e343d55c 542 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 543 &bp->tx_desc_mapping);
544 if (bp->tx_desc_ring == NULL)
545 goto alloc_mem_err;
546
e343d55c 547 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
b6016b76
MC		 548 if (bp->rx_buf_ring == NULL)
549 goto alloc_mem_err;
550
e343d55c 551 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
13daffa2
MC		 552
553 for (i = 0; i < bp->rx_max_ring; i++) {
554 bp->rx_desc_ring[i] =
e343d55c 555 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 556 &bp->rx_desc_mapping[i]);
557 if (bp->rx_desc_ring[i] == NULL)
558 goto alloc_mem_err;
559
560 }
b6016b76 561
47bf4246
MC		 562 if (bp->rx_pg_ring_size) {
563 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
564 bp->rx_max_pg_ring);
565 if (bp->rx_pg_ring == NULL)
566 goto alloc_mem_err;
567
568 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
569 bp->rx_max_pg_ring);
570 }
571
572 for (i = 0; i < bp->rx_max_pg_ring; i++) {
573 bp->rx_pg_desc_ring[i] =
574 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
575 &bp->rx_pg_desc_mapping[i]);
576 if (bp->rx_pg_desc_ring[i] == NULL)
577 goto alloc_mem_err;
578
579 }
580
0f31f994
MC		 581 /* Combine status and statistics blocks into one allocation. */
582 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 583 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 584 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
585 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 586 bp->status_stats_size = status_blk_size +
587 sizeof(struct statistics_block);
588
589 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 590 &bp->status_blk_mapping);
591 if (bp->status_blk == NULL)
592 goto alloc_mem_err;
593
0f31f994 594 memset(bp->status_blk, 0, bp->status_stats_size);
b6016b76 595
b4b36042 596 bp->bnx2_napi[0].status_blk = bp->status_blk;
f86e82fb 597 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042
MC		 598 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
599 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
600
57851d84 601 bnapi->status_blk_msix = (void *)
b4b36042
MC		 602 ((unsigned long) bp->status_blk +
603 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
604 bnapi->int_num = i << 24;
605 }
606 }
35efa7c1 607
0f31f994
MC		 608 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
609 status_blk_size);
b6016b76 610
0f31f994 611 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 612
59b47d8a
MC		 613 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
614 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
615 if (bp->ctx_pages == 0)
616 bp->ctx_pages = 1;
617 for (i = 0; i < bp->ctx_pages; i++) {
618 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
619 BCM_PAGE_SIZE,
620 &bp->ctx_blk_mapping[i]);
621 if (bp->ctx_blk[i] == NULL)
622 goto alloc_mem_err;
623 }
624 }
b6016b76
MC		 625 return 0;
626
627alloc_mem_err:
628 bnx2_free_mem(bp);
629 return -ENOMEM;
630}
631
e3648b3d
MC		 632static void
633bnx2_report_fw_link(struct bnx2 *bp)
634{
635 u32 fw_link_status = 0;
636
583c28e5 637 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 638 return;
639
e3648b3d
MC		 640 if (bp->link_up) {
641 u32 bmsr;
642
643 switch (bp->line_speed) {
644 case SPEED_10:
645 if (bp->duplex == DUPLEX_HALF)
646 fw_link_status = BNX2_LINK_STATUS_10HALF;
647 else
648 fw_link_status = BNX2_LINK_STATUS_10FULL;
649 break;
650 case SPEED_100:
651 if (bp->duplex == DUPLEX_HALF)
652 fw_link_status = BNX2_LINK_STATUS_100HALF;
653 else
654 fw_link_status = BNX2_LINK_STATUS_100FULL;
655 break;
656 case SPEED_1000:
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_1000HALF;
659 else
660 fw_link_status = BNX2_LINK_STATUS_1000FULL;
661 break;
662 case SPEED_2500:
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_2500HALF;
665 else
666 fw_link_status = BNX2_LINK_STATUS_2500FULL;
667 break;
668 }
669
670 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
671
672 if (bp->autoneg) {
673 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
674
ca58c3af
MC		 675 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
676 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 677
678 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 679 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 680 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
681 else
682 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
683 }
684 }
685 else
686 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
687
688 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
689}
690
9b1084b8
MC		 691static char *
692bnx2_xceiver_str(struct bnx2 *bp)
693{
694 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 695 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 696 "Copper"));
697}
698
b6016b76
MC		 699static void
700bnx2_report_link(struct bnx2 *bp)
701{
702 if (bp->link_up) {
703 netif_carrier_on(bp->dev);
9b1084b8
MC		 704 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
705 bnx2_xceiver_str(bp));
b6016b76
MC		 706
707 printk("%d Mbps ", bp->line_speed);
708
709 if (bp->duplex == DUPLEX_FULL)
710 printk("full duplex");
711 else
712 printk("half duplex");
713
714 if (bp->flow_ctrl) {
715 if (bp->flow_ctrl & FLOW_CTRL_RX) {
716 printk(", receive ");
717 if (bp->flow_ctrl & FLOW_CTRL_TX)
718 printk("& transmit ");
719 }
720 else {
721 printk(", transmit ");
722 }
723 printk("flow control ON");
724 }
725 printk("\n");
726 }
727 else {
728 netif_carrier_off(bp->dev);
9b1084b8
MC		 729 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
730 bnx2_xceiver_str(bp));
b6016b76 731 }
e3648b3d
MC		 732
733 bnx2_report_fw_link(bp);
b6016b76
MC		 734}
735
736static void
737bnx2_resolve_flow_ctrl(struct bnx2 *bp)
738{
739 u32 local_adv, remote_adv;
740
741 bp->flow_ctrl = 0;
6aa20a22 742 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 743 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
744
745 if (bp->duplex == DUPLEX_FULL) {
746 bp->flow_ctrl = bp->req_flow_ctrl;
747 }
748 return;
749 }
750
751 if (bp->duplex != DUPLEX_FULL) {
752 return;
753 }
754
583c28e5 755 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 756 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
757 u32 val;
758
759 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
760 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
761 bp->flow_ctrl |= FLOW_CTRL_TX;
762 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
763 bp->flow_ctrl |= FLOW_CTRL_RX;
764 return;
765 }
766
ca58c3af
MC		 767 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
768 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 769
583c28e5 770 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 771 u32 new_local_adv = 0;
772 u32 new_remote_adv = 0;
773
774 if (local_adv & ADVERTISE_1000XPAUSE)
775 new_local_adv |= ADVERTISE_PAUSE_CAP;
776 if (local_adv & ADVERTISE_1000XPSE_ASYM)
777 new_local_adv |= ADVERTISE_PAUSE_ASYM;
778 if (remote_adv & ADVERTISE_1000XPAUSE)
779 new_remote_adv |= ADVERTISE_PAUSE_CAP;
780 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
781 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
782
783 local_adv = new_local_adv;
784 remote_adv = new_remote_adv;
785 }
786
787 /* See Table 28B-3 of 802.3ab-1999 spec. */
788 if (local_adv & ADVERTISE_PAUSE_CAP) {
789 if(local_adv & ADVERTISE_PAUSE_ASYM) {
790 if (remote_adv & ADVERTISE_PAUSE_CAP) {
791 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
792 }
793 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
794 bp->flow_ctrl = FLOW_CTRL_RX;
795 }
796 }
797 else {
798 if (remote_adv & ADVERTISE_PAUSE_CAP) {
799 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
800 }
801 }
802 }
803 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
804 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
805 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
806
807 bp->flow_ctrl = FLOW_CTRL_TX;
808 }
809 }
810}
811
27a005b8
MC		 812static int
813bnx2_5709s_linkup(struct bnx2 *bp)
814{
815 u32 val, speed;
816
817 bp->link_up = 1;
818
819 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
820 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
821 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
822
823 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
824 bp->line_speed = bp->req_line_speed;
825 bp->duplex = bp->req_duplex;
826 return 0;
827 }
828 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
829 switch (speed) {
830 case MII_BNX2_GP_TOP_AN_SPEED_10:
831 bp->line_speed = SPEED_10;
832 break;
833 case MII_BNX2_GP_TOP_AN_SPEED_100:
834 bp->line_speed = SPEED_100;
835 break;
836 case MII_BNX2_GP_TOP_AN_SPEED_1G:
837 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
838 bp->line_speed = SPEED_1000;
839 break;
840 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
841 bp->line_speed = SPEED_2500;
842 break;
843 }
844 if (val & MII_BNX2_GP_TOP_AN_FD)
845 bp->duplex = DUPLEX_FULL;
846 else
847 bp->duplex = DUPLEX_HALF;
848 return 0;
849}
850
b6016b76 851static int
5b0c76ad
MC		 852bnx2_5708s_linkup(struct bnx2 *bp)
853{
854 u32 val;
855
856 bp->link_up = 1;
857 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
858 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
859 case BCM5708S_1000X_STAT1_SPEED_10:
860 bp->line_speed = SPEED_10;
861 break;
862 case BCM5708S_1000X_STAT1_SPEED_100:
863 bp->line_speed = SPEED_100;
864 break;
865 case BCM5708S_1000X_STAT1_SPEED_1G:
866 bp->line_speed = SPEED_1000;
867 break;
868 case BCM5708S_1000X_STAT1_SPEED_2G5:
869 bp->line_speed = SPEED_2500;
870 break;
871 }
872 if (val & BCM5708S_1000X_STAT1_FD)
873 bp->duplex = DUPLEX_FULL;
874 else
875 bp->duplex = DUPLEX_HALF;
876
877 return 0;
878}
879
880static int
881bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 882{
883 u32 bmcr, local_adv, remote_adv, common;
884
885 bp->link_up = 1;
886 bp->line_speed = SPEED_1000;
887
ca58c3af 888 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 889 if (bmcr & BMCR_FULLDPLX) {
890 bp->duplex = DUPLEX_FULL;
891 }
892 else {
893 bp->duplex = DUPLEX_HALF;
894 }
895
896 if (!(bmcr & BMCR_ANENABLE)) {
897 return 0;
898 }
899
ca58c3af
MC		 900 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
901 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 902
903 common = local_adv & remote_adv;
904 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
905
906 if (common & ADVERTISE_1000XFULL) {
907 bp->duplex = DUPLEX_FULL;
908 }
909 else {
910 bp->duplex = DUPLEX_HALF;
911 }
912 }
913
914 return 0;
915}
916
917static int
918bnx2_copper_linkup(struct bnx2 *bp)
919{
920 u32 bmcr;
921
ca58c3af 922 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 923 if (bmcr & BMCR_ANENABLE) {
924 u32 local_adv, remote_adv, common;
925
926 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
927 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
928
929 common = local_adv & (remote_adv >> 2);
930 if (common & ADVERTISE_1000FULL) {
931 bp->line_speed = SPEED_1000;
932 bp->duplex = DUPLEX_FULL;
933 }
934 else if (common & ADVERTISE_1000HALF) {
935 bp->line_speed = SPEED_1000;
936 bp->duplex = DUPLEX_HALF;
937 }
938 else {
ca58c3af
MC		 939 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
940 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 941
942 common = local_adv & remote_adv;
943 if (common & ADVERTISE_100FULL) {
944 bp->line_speed = SPEED_100;
945 bp->duplex = DUPLEX_FULL;
946 }
947 else if (common & ADVERTISE_100HALF) {
948 bp->line_speed = SPEED_100;
949 bp->duplex = DUPLEX_HALF;
950 }
951 else if (common & ADVERTISE_10FULL) {
952 bp->line_speed = SPEED_10;
953 bp->duplex = DUPLEX_FULL;
954 }
955 else if (common & ADVERTISE_10HALF) {
956 bp->line_speed = SPEED_10;
957 bp->duplex = DUPLEX_HALF;
958 }
959 else {
960 bp->line_speed = 0;
961 bp->link_up = 0;
962 }
963 }
964 }
965 else {
966 if (bmcr & BMCR_SPEED100) {
967 bp->line_speed = SPEED_100;
968 }
969 else {
970 bp->line_speed = SPEED_10;
971 }
972 if (bmcr & BMCR_FULLDPLX) {
973 bp->duplex = DUPLEX_FULL;
974 }
975 else {
976 bp->duplex = DUPLEX_HALF;
977 }
978 }
979
980 return 0;
981}
982
983static int
984bnx2_set_mac_link(struct bnx2 *bp)
985{
986 u32 val;
987
988 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
989 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
990 (bp->duplex == DUPLEX_HALF)) {
991 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
992 }
993
994 /* Configure the EMAC mode register. */
995 val = REG_RD(bp, BNX2_EMAC_MODE);
996
997 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 998 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 999 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1000
1001 if (bp->link_up) {
5b0c76ad
MC		 1002 switch (bp->line_speed) {
1003 case SPEED_10:
59b47d8a
MC		 1004 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1005 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1006 break;
1007 }
1008 /* fall through */
1009 case SPEED_100:
1010 val |= BNX2_EMAC_MODE_PORT_MII;
1011 break;
1012 case SPEED_2500:
59b47d8a 1013 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1014 /* fall through */
1015 case SPEED_1000:
1016 val |= BNX2_EMAC_MODE_PORT_GMII;
1017 break;
1018 }
b6016b76
MC		 1019 }
1020 else {
1021 val |= BNX2_EMAC_MODE_PORT_GMII;
1022 }
1023
1024 /* Set the MAC to operate in the appropriate duplex mode. */
1025 if (bp->duplex == DUPLEX_HALF)
1026 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1027 REG_WR(bp, BNX2_EMAC_MODE, val);
1028
1029 /* Enable/disable rx PAUSE. */
1030 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1031
1032 if (bp->flow_ctrl & FLOW_CTRL_RX)
1033 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1034 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1035
1036 /* Enable/disable tx PAUSE. */
1037 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1038 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1039
1040 if (bp->flow_ctrl & FLOW_CTRL_TX)
1041 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1042 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1043
1044 /* Acknowledge the interrupt. */
1045 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1046
1047 return 0;
1048}
1049
27a005b8
MC		 1050static void
1051bnx2_enable_bmsr1(struct bnx2 *bp)
1052{
583c28e5 1053 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1054 (CHIP_NUM(bp) == CHIP_NUM_5709))
1055 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1056 MII_BNX2_BLK_ADDR_GP_STATUS);
1057}
1058
1059static void
1060bnx2_disable_bmsr1(struct bnx2 *bp)
1061{
583c28e5 1062 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1063 (CHIP_NUM(bp) == CHIP_NUM_5709))
1064 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1065 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1066}
1067
605a9e20
MC		 1068static int
1069bnx2_test_and_enable_2g5(struct bnx2 *bp)
1070{
1071 u32 up1;
1072 int ret = 1;
1073
583c28e5 1074 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1075 return 0;
1076
1077 if (bp->autoneg & AUTONEG_SPEED)
1078 bp->advertising |= ADVERTISED_2500baseX_Full;
1079
27a005b8
MC		 1080 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1081 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1082
605a9e20
MC		 1083 bnx2_read_phy(bp, bp->mii_up1, &up1);
1084 if (!(up1 & BCM5708S_UP1_2G5)) {
1085 up1 |= BCM5708S_UP1_2G5;
1086 bnx2_write_phy(bp, bp->mii_up1, up1);
1087 ret = 0;
1088 }
1089
27a005b8
MC		 1090 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1091 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1092 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1093
605a9e20
MC		 1094 return ret;
1095}
1096
1097static int
1098bnx2_test_and_disable_2g5(struct bnx2 *bp)
1099{
1100 u32 up1;
1101 int ret = 0;
1102
583c28e5 1103 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1104 return 0;
1105
27a005b8
MC		 1106 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1107 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1108
605a9e20
MC		 1109 bnx2_read_phy(bp, bp->mii_up1, &up1);
1110 if (up1 & BCM5708S_UP1_2G5) {
1111 up1 &= ~BCM5708S_UP1_2G5;
1112 bnx2_write_phy(bp, bp->mii_up1, up1);
1113 ret = 1;
1114 }
1115
27a005b8
MC		 1116 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1117 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1118 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1119
605a9e20
MC		 1120 return ret;
1121}
1122
1123static void
1124bnx2_enable_forced_2g5(struct bnx2 *bp)
1125{
1126 u32 bmcr;
1127
583c28e5 1128 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1129 return;
1130
27a005b8
MC		 1131 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1132 u32 val;
1133
1134 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1135 MII_BNX2_BLK_ADDR_SERDES_DIG);
1136 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1137 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1138 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1139 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1140
1141 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1142 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1143 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1144
1145 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1146 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1147 bmcr |= BCM5708S_BMCR_FORCE_2500;
1148 }
1149
1150 if (bp->autoneg & AUTONEG_SPEED) {
1151 bmcr &= ~BMCR_ANENABLE;
1152 if (bp->req_duplex == DUPLEX_FULL)
1153 bmcr |= BMCR_FULLDPLX;
1154 }
1155 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1156}
1157
1158static void
1159bnx2_disable_forced_2g5(struct bnx2 *bp)
1160{
1161 u32 bmcr;
1162
583c28e5 1163 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1164 return;
1165
27a005b8
MC		 1166 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1167 u32 val;
1168
1169 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1170 MII_BNX2_BLK_ADDR_SERDES_DIG);
1171 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1172 val &= ~MII_BNX2_SD_MISC1_FORCE;
1173 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1174
1175 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1176 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1177 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1178
1179 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1180 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1181 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1182 }
1183
1184 if (bp->autoneg & AUTONEG_SPEED)
1185 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1186 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1187}
1188
b2fadeae
MC		 1189static void
1190bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1191{
1192 u32 val;
1193
1194 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1195 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1196 if (start)
1197 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1198 else
1199 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1200}
1201
b6016b76
MC		 1202static int
1203bnx2_set_link(struct bnx2 *bp)
1204{
1205 u32 bmsr;
1206 u8 link_up;
1207
80be4434 1208 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1209 bp->link_up = 1;
1210 return 0;
1211 }
1212
583c28e5 1213 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1214 return 0;
1215
b6016b76
MC		 1216 link_up = bp->link_up;
1217
27a005b8
MC		 1218 bnx2_enable_bmsr1(bp);
1219 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1220 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1221 bnx2_disable_bmsr1(bp);
b6016b76 1222
583c28e5 1223 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76
MC		 1224 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1225 u32 val;
1226
583c28e5 1227 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1228 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1229 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1230 }
b6016b76
MC		 1231 val = REG_RD(bp, BNX2_EMAC_STATUS);
1232 if (val & BNX2_EMAC_STATUS_LINK)
1233 bmsr |= BMSR_LSTATUS;
1234 else
1235 bmsr &= ~BMSR_LSTATUS;
1236 }
1237
1238 if (bmsr & BMSR_LSTATUS) {
1239 bp->link_up = 1;
1240
583c28e5 1241 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1242 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1243 bnx2_5706s_linkup(bp);
1244 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1245 bnx2_5708s_linkup(bp);
27a005b8
MC		 1246 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1247 bnx2_5709s_linkup(bp);
b6016b76
MC		 1248 }
1249 else {
1250 bnx2_copper_linkup(bp);
1251 }
1252 bnx2_resolve_flow_ctrl(bp);
1253 }
1254 else {
583c28e5 1255 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1256 (bp->autoneg & AUTONEG_SPEED))
1257 bnx2_disable_forced_2g5(bp);
b6016b76 1258
583c28e5 1259 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1260 u32 bmcr;
1261
1262 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1263 bmcr |= BMCR_ANENABLE;
1264 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1265
583c28e5 1266 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1267 }
b6016b76
MC		 1268 bp->link_up = 0;
1269 }
1270
1271 if (bp->link_up != link_up) {
1272 bnx2_report_link(bp);
1273 }
1274
1275 bnx2_set_mac_link(bp);
1276
1277 return 0;
1278}
1279
1280static int
1281bnx2_reset_phy(struct bnx2 *bp)
1282{
1283 int i;
1284 u32 reg;
1285
ca58c3af 1286 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1287
1288#define PHY_RESET_MAX_WAIT 100
1289 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1290 udelay(10);
1291
ca58c3af 1292 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1293 if (!(reg & BMCR_RESET)) {
1294 udelay(20);
1295 break;
1296 }
1297 }
1298 if (i == PHY_RESET_MAX_WAIT) {
1299 return -EBUSY;
1300 }
1301 return 0;
1302}
1303
1304static u32
1305bnx2_phy_get_pause_adv(struct bnx2 *bp)
1306{
1307 u32 adv = 0;
1308
1309 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1310 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1311
583c28e5 1312 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1313 adv = ADVERTISE_1000XPAUSE;
1314 }
1315 else {
1316 adv = ADVERTISE_PAUSE_CAP;
1317 }
1318 }
1319 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1320 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1321 adv = ADVERTISE_1000XPSE_ASYM;
1322 }
1323 else {
1324 adv = ADVERTISE_PAUSE_ASYM;
1325 }
1326 }
1327 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1328 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1329 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1330 }
1331 else {
1332 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333 }
1334 }
1335 return adv;
1336}
1337
0d8a6571
MC		 1338static int bnx2_fw_sync(struct bnx2 *, u32, int);
1339
b6016b76 1340static int
0d8a6571
MC		 1341bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1342{
1343 u32 speed_arg = 0, pause_adv;
1344
1345 pause_adv = bnx2_phy_get_pause_adv(bp);
1346
1347 if (bp->autoneg & AUTONEG_SPEED) {
1348 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1349 if (bp->advertising & ADVERTISED_10baseT_Half)
1350 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1351 if (bp->advertising & ADVERTISED_10baseT_Full)
1352 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1353 if (bp->advertising & ADVERTISED_100baseT_Half)
1354 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1355 if (bp->advertising & ADVERTISED_100baseT_Full)
1356 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1357 if (bp->advertising & ADVERTISED_1000baseT_Full)
1358 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1359 if (bp->advertising & ADVERTISED_2500baseX_Full)
1360 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1361 } else {
1362 if (bp->req_line_speed == SPEED_2500)
1363 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1364 else if (bp->req_line_speed == SPEED_1000)
1365 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1366 else if (bp->req_line_speed == SPEED_100) {
1367 if (bp->req_duplex == DUPLEX_FULL)
1368 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1369 else
1370 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1371 } else if (bp->req_line_speed == SPEED_10) {
1372 if (bp->req_duplex == DUPLEX_FULL)
1373 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1374 else
1375 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1376 }
1377 }
1378
1379 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1380 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1381 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1382 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1383
1384 if (port == PORT_TP)
1385 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1386 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1387
1388 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1389
1390 spin_unlock_bh(&bp->phy_lock);
1391 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1392 spin_lock_bh(&bp->phy_lock);
1393
1394 return 0;
1395}
1396
1397static int
1398bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
b6016b76 1399{
605a9e20 1400 u32 adv, bmcr;
b6016b76
MC		 1401 u32 new_adv = 0;
1402
583c28e5 1403 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1404 return (bnx2_setup_remote_phy(bp, port));
1405
b6016b76
MC		 1406 if (!(bp->autoneg & AUTONEG_SPEED)) {
1407 u32 new_bmcr;
5b0c76ad
MC		 1408 int force_link_down = 0;
1409
605a9e20
MC		 1410 if (bp->req_line_speed == SPEED_2500) {
1411 if (!bnx2_test_and_enable_2g5(bp))
1412 force_link_down = 1;
1413 } else if (bp->req_line_speed == SPEED_1000) {
1414 if (bnx2_test_and_disable_2g5(bp))
1415 force_link_down = 1;
1416 }
ca58c3af 1417 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1418 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1419
ca58c3af 1420 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1421 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1422 new_bmcr |= BMCR_SPEED1000;
605a9e20 1423
27a005b8
MC		 1424 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1425 if (bp->req_line_speed == SPEED_2500)
1426 bnx2_enable_forced_2g5(bp);
1427 else if (bp->req_line_speed == SPEED_1000) {
1428 bnx2_disable_forced_2g5(bp);
1429 new_bmcr &= ~0x2000;
1430 }
1431
1432 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1433 if (bp->req_line_speed == SPEED_2500)
1434 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1435 else
1436 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1437 }
1438
b6016b76 1439 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1440 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1441 new_bmcr |= BMCR_FULLDPLX;
1442 }
1443 else {
5b0c76ad 1444 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1445 new_bmcr &= ~BMCR_FULLDPLX;
1446 }
5b0c76ad 1447 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1448 /* Force a link down visible on the other side */
1449 if (bp->link_up) {
ca58c3af 1450 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1451 ~(ADVERTISE_1000XFULL |
1452 ADVERTISE_1000XHALF));
ca58c3af 1453 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1454 BMCR_ANRESTART | BMCR_ANENABLE);
1455
1456 bp->link_up = 0;
1457 netif_carrier_off(bp->dev);
ca58c3af 1458 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1459 bnx2_report_link(bp);
b6016b76 1460 }
ca58c3af
MC		 1461 bnx2_write_phy(bp, bp->mii_adv, adv);
1462 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1463 } else {
1464 bnx2_resolve_flow_ctrl(bp);
1465 bnx2_set_mac_link(bp);
b6016b76
MC		 1466 }
1467 return 0;
1468 }
1469
605a9e20 1470 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1471
b6016b76
MC		 1472 if (bp->advertising & ADVERTISED_1000baseT_Full)
1473 new_adv |= ADVERTISE_1000XFULL;
1474
1475 new_adv |= bnx2_phy_get_pause_adv(bp);
1476
ca58c3af
MC		 1477 bnx2_read_phy(bp, bp->mii_adv, &adv);
1478 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1479
1480 bp->serdes_an_pending = 0;
1481 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1482 /* Force a link down visible on the other side */
1483 if (bp->link_up) {
ca58c3af 1484 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1485 spin_unlock_bh(&bp->phy_lock);
1486 msleep(20);
1487 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1488 }
1489
ca58c3af
MC		 1490 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1491 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1492 BMCR_ANENABLE);
f8dd064e
MC		 1493 /* Speed up link-up time when the link partner
1494 * does not autonegotiate which is very common
1495 * in blade servers. Some blade servers use
1496 * IPMI for kerboard input and it's important
1497 * to minimize link disruptions. Autoneg. involves
1498 * exchanging base pages plus 3 next pages and
1499 * normally completes in about 120 msec.
1500 */
1501 bp->current_interval = SERDES_AN_TIMEOUT;
1502 bp->serdes_an_pending = 1;
1503 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1504 } else {
1505 bnx2_resolve_flow_ctrl(bp);
1506 bnx2_set_mac_link(bp);
b6016b76
MC		 1507 }
1508
1509 return 0;
1510}
1511
1512#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1513 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1514 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1515 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1516
1517#define ETHTOOL_ALL_COPPER_SPEED \
1518 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1519 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1520 ADVERTISED_1000baseT_Full)
1521
1522#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1523 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1524
b6016b76
MC		 1525#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1526
0d8a6571
MC		 1527static void
1528bnx2_set_default_remote_link(struct bnx2 *bp)
1529{
1530 u32 link;
1531
1532 if (bp->phy_port == PORT_TP)
1533 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1534 else
1535 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1536
1537 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1538 bp->req_line_speed = 0;
1539 bp->autoneg |= AUTONEG_SPEED;
1540 bp->advertising = ADVERTISED_Autoneg;
1541 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1542 bp->advertising |= ADVERTISED_10baseT_Half;
1543 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1544 bp->advertising |= ADVERTISED_10baseT_Full;
1545 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1546 bp->advertising |= ADVERTISED_100baseT_Half;
1547 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1548 bp->advertising |= ADVERTISED_100baseT_Full;
1549 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1550 bp->advertising |= ADVERTISED_1000baseT_Full;
1551 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1552 bp->advertising |= ADVERTISED_2500baseX_Full;
1553 } else {
1554 bp->autoneg = 0;
1555 bp->advertising = 0;
1556 bp->req_duplex = DUPLEX_FULL;
1557 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1558 bp->req_line_speed = SPEED_10;
1559 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1560 bp->req_duplex = DUPLEX_HALF;
1561 }
1562 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1563 bp->req_line_speed = SPEED_100;
1564 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1565 bp->req_duplex = DUPLEX_HALF;
1566 }
1567 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1568 bp->req_line_speed = SPEED_1000;
1569 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1570 bp->req_line_speed = SPEED_2500;
1571 }
1572}
1573
deaf391b
MC		 1574static void
1575bnx2_set_default_link(struct bnx2 *bp)
1576{
583c28e5 1577 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1578 return bnx2_set_default_remote_link(bp);
1579
deaf391b
MC		 1580 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1581 bp->req_line_speed = 0;
583c28e5 1582 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1583 u32 reg;
1584
1585 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1586
1587 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1588 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1589 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1590 bp->autoneg = 0;
1591 bp->req_line_speed = bp->line_speed = SPEED_1000;
1592 bp->req_duplex = DUPLEX_FULL;
1593 }
1594 } else
1595 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1596}
1597
df149d70
MC		 1598static void
1599bnx2_send_heart_beat(struct bnx2 *bp)
1600{
1601 u32 msg;
1602 u32 addr;
1603
1604 spin_lock(&bp->indirect_lock);
1605 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1606 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1607 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1608 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1609 spin_unlock(&bp->indirect_lock);
1610}
1611
0d8a6571
MC		 1612static void
1613bnx2_remote_phy_event(struct bnx2 *bp)
1614{
1615 u32 msg;
1616 u8 link_up = bp->link_up;
1617 u8 old_port;
1618
1619 msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1620
df149d70
MC		 1621 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1622 bnx2_send_heart_beat(bp);
1623
1624 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1625
0d8a6571
MC		 1626 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1627 bp->link_up = 0;
1628 else {
1629 u32 speed;
1630
1631 bp->link_up = 1;
1632 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1633 bp->duplex = DUPLEX_FULL;
1634 switch (speed) {
1635 case BNX2_LINK_STATUS_10HALF:
1636 bp->duplex = DUPLEX_HALF;
1637 case BNX2_LINK_STATUS_10FULL:
1638 bp->line_speed = SPEED_10;
1639 break;
1640 case BNX2_LINK_STATUS_100HALF:
1641 bp->duplex = DUPLEX_HALF;
1642 case BNX2_LINK_STATUS_100BASE_T4:
1643 case BNX2_LINK_STATUS_100FULL:
1644 bp->line_speed = SPEED_100;
1645 break;
1646 case BNX2_LINK_STATUS_1000HALF:
1647 bp->duplex = DUPLEX_HALF;
1648 case BNX2_LINK_STATUS_1000FULL:
1649 bp->line_speed = SPEED_1000;
1650 break;
1651 case BNX2_LINK_STATUS_2500HALF:
1652 bp->duplex = DUPLEX_HALF;
1653 case BNX2_LINK_STATUS_2500FULL:
1654 bp->line_speed = SPEED_2500;
1655 break;
1656 default:
1657 bp->line_speed = 0;
1658 break;
1659 }
1660
1661 spin_lock(&bp->phy_lock);
1662 bp->flow_ctrl = 0;
1663 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1664 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1665 if (bp->duplex == DUPLEX_FULL)
1666 bp->flow_ctrl = bp->req_flow_ctrl;
1667 } else {
1668 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1669 bp->flow_ctrl |= FLOW_CTRL_TX;
1670 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1671 bp->flow_ctrl |= FLOW_CTRL_RX;
1672 }
1673
1674 old_port = bp->phy_port;
1675 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1676 bp->phy_port = PORT_FIBRE;
1677 else
1678 bp->phy_port = PORT_TP;
1679
1680 if (old_port != bp->phy_port)
1681 bnx2_set_default_link(bp);
1682
1683 spin_unlock(&bp->phy_lock);
1684 }
1685 if (bp->link_up != link_up)
1686 bnx2_report_link(bp);
1687
1688 bnx2_set_mac_link(bp);
1689}
1690
1691static int
1692bnx2_set_remote_link(struct bnx2 *bp)
1693{
1694 u32 evt_code;
1695
1696 evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1697 switch (evt_code) {
1698 case BNX2_FW_EVT_CODE_LINK_EVENT:
1699 bnx2_remote_phy_event(bp);
1700 break;
1701 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1702 default:
df149d70 1703 bnx2_send_heart_beat(bp);
0d8a6571
MC		 1704 break;
1705 }
1706 return 0;
1707}
1708
b6016b76
MC		 1709static int
1710bnx2_setup_copper_phy(struct bnx2 *bp)
1711{
1712 u32 bmcr;
1713 u32 new_bmcr;
1714
ca58c3af 1715 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1716
1717 if (bp->autoneg & AUTONEG_SPEED) {
1718 u32 adv_reg, adv1000_reg;
1719 u32 new_adv_reg = 0;
1720 u32 new_adv1000_reg = 0;
1721
ca58c3af 1722 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 1723 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1724 ADVERTISE_PAUSE_ASYM);
1725
1726 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1727 adv1000_reg &= PHY_ALL_1000_SPEED;
1728
1729 if (bp->advertising & ADVERTISED_10baseT_Half)
1730 new_adv_reg |= ADVERTISE_10HALF;
1731 if (bp->advertising & ADVERTISED_10baseT_Full)
1732 new_adv_reg |= ADVERTISE_10FULL;
1733 if (bp->advertising & ADVERTISED_100baseT_Half)
1734 new_adv_reg |= ADVERTISE_100HALF;
1735 if (bp->advertising & ADVERTISED_100baseT_Full)
1736 new_adv_reg |= ADVERTISE_100FULL;
1737 if (bp->advertising & ADVERTISED_1000baseT_Full)
1738 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 1739
b6016b76
MC		 1740 new_adv_reg |= ADVERTISE_CSMA;
1741
1742 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1743
1744 if ((adv1000_reg != new_adv1000_reg) ||
1745 (adv_reg != new_adv_reg) ||
1746 ((bmcr & BMCR_ANENABLE) == 0)) {
1747
ca58c3af 1748 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 1749 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 1750 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 1751 BMCR_ANENABLE);
1752 }
1753 else if (bp->link_up) {
1754 /* Flow ctrl may have changed from auto to forced */
1755 /* or vice-versa. */
1756
1757 bnx2_resolve_flow_ctrl(bp);
1758 bnx2_set_mac_link(bp);
1759 }
1760 return 0;
1761 }
1762
1763 new_bmcr = 0;
1764 if (bp->req_line_speed == SPEED_100) {
1765 new_bmcr |= BMCR_SPEED100;
1766 }
1767 if (bp->req_duplex == DUPLEX_FULL) {
1768 new_bmcr |= BMCR_FULLDPLX;
1769 }
1770 if (new_bmcr != bmcr) {
1771 u32 bmsr;
b6016b76 1772
ca58c3af
MC		 1773 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1774 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 1775
b6016b76
MC		 1776 if (bmsr & BMSR_LSTATUS) {
1777 /* Force link down */
ca58c3af 1778 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 1779 spin_unlock_bh(&bp->phy_lock);
1780 msleep(50);
1781 spin_lock_bh(&bp->phy_lock);
1782
ca58c3af
MC		 1783 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1784 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 1785 }
1786
ca58c3af 1787 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 1788
1789 /* Normally, the new speed is setup after the link has
1790 * gone down and up again. In some cases, link will not go
1791 * down so we need to set up the new speed here.
1792 */
1793 if (bmsr & BMSR_LSTATUS) {
1794 bp->line_speed = bp->req_line_speed;
1795 bp->duplex = bp->req_duplex;
1796 bnx2_resolve_flow_ctrl(bp);
1797 bnx2_set_mac_link(bp);
1798 }
27a005b8
MC		 1799 } else {
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
b6016b76
MC		 1802 }
1803 return 0;
1804}
1805
1806static int
0d8a6571 1807bnx2_setup_phy(struct bnx2 *bp, u8 port)
b6016b76
MC		 1808{
1809 if (bp->loopback == MAC_LOOPBACK)
1810 return 0;
1811
583c28e5 1812 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 1813 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 1814 }
1815 else {
1816 return (bnx2_setup_copper_phy(bp));
1817 }
1818}
1819
27a005b8
MC		 1820static int
1821bnx2_init_5709s_phy(struct bnx2 *bp)
1822{
1823 u32 val;
1824
1825 bp->mii_bmcr = MII_BMCR + 0x10;
1826 bp->mii_bmsr = MII_BMSR + 0x10;
1827 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1828 bp->mii_adv = MII_ADVERTISE + 0x10;
1829 bp->mii_lpa = MII_LPA + 0x10;
1830 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1831
1832 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1833 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1834
1835 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1836 bnx2_reset_phy(bp);
1837
1838 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1839
1840 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1841 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1842 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1843 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1844
1845 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1846 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 1847 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 1848 val |= BCM5708S_UP1_2G5;
1849 else
1850 val &= ~BCM5708S_UP1_2G5;
1851 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1852
1853 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1854 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1855 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1856 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1857
1858 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1859
1860 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1861 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1862 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1863
1864 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1865
1866 return 0;
1867}
1868
b6016b76 1869static int
5b0c76ad
MC		 1870bnx2_init_5708s_phy(struct bnx2 *bp)
1871{
1872 u32 val;
1873
27a005b8
MC		 1874 bnx2_reset_phy(bp);
1875
1876 bp->mii_up1 = BCM5708S_UP1;
1877
5b0c76ad
MC		 1878 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1879 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1880 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1881
1882 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1883 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1884 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1885
1886 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1887 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1888 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1889
583c28e5 1890 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 1891 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1892 val |= BCM5708S_UP1_2G5;
1893 bnx2_write_phy(bp, BCM5708S_UP1, val);
1894 }
1895
1896 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1897 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1898 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1899 /* increase tx signal amplitude */
1900 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1901 BCM5708S_BLK_ADDR_TX_MISC);
1902 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1903 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1904 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1905 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1906 }
1907
e3648b3d 1908 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1909 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1910
1911 if (val) {
1912 u32 is_backplane;
1913
e3648b3d 1914 is_backplane = REG_RD_IND(bp, bp->shmem_base +
5b0c76ad
MC		 1915 BNX2_SHARED_HW_CFG_CONFIG);
1916 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1917 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1918 BCM5708S_BLK_ADDR_TX_MISC);
1919 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1920 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1921 BCM5708S_BLK_ADDR_DIG);
1922 }
1923 }
1924 return 0;
1925}
1926
1927static int
1928bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76 1929{
27a005b8
MC		 1930 bnx2_reset_phy(bp);
1931
583c28e5 1932 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 1933
59b47d8a
MC		 1934 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1935 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 1936
1937 if (bp->dev->mtu > 1500) {
1938 u32 val;
1939
1940 /* Set extended packet length bit */
1941 bnx2_write_phy(bp, 0x18, 0x7);
1942 bnx2_read_phy(bp, 0x18, &val);
1943 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1944
1945 bnx2_write_phy(bp, 0x1c, 0x6c00);
1946 bnx2_read_phy(bp, 0x1c, &val);
1947 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1948 }
1949 else {
1950 u32 val;
1951
1952 bnx2_write_phy(bp, 0x18, 0x7);
1953 bnx2_read_phy(bp, 0x18, &val);
1954 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1955
1956 bnx2_write_phy(bp, 0x1c, 0x6c00);
1957 bnx2_read_phy(bp, 0x1c, &val);
1958 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1959 }
1960
1961 return 0;
1962}
1963
1964static int
1965bnx2_init_copper_phy(struct bnx2 *bp)
1966{
5b0c76ad
MC		 1967 u32 val;
1968
27a005b8
MC		 1969 bnx2_reset_phy(bp);
1970
583c28e5 1971 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 1972 bnx2_write_phy(bp, 0x18, 0x0c00);
1973 bnx2_write_phy(bp, 0x17, 0x000a);
1974 bnx2_write_phy(bp, 0x15, 0x310b);
1975 bnx2_write_phy(bp, 0x17, 0x201f);
1976 bnx2_write_phy(bp, 0x15, 0x9506);
1977 bnx2_write_phy(bp, 0x17, 0x401f);
1978 bnx2_write_phy(bp, 0x15, 0x14e2);
1979 bnx2_write_phy(bp, 0x18, 0x0400);
1980 }
1981
583c28e5 1982 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 1983 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1984 MII_BNX2_DSP_EXPAND_REG | 0x8);
1985 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1986 val &= ~(1 << 8);
1987 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1988 }
1989
b6016b76 1990 if (bp->dev->mtu > 1500) {
b6016b76
MC		 1991 /* Set extended packet length bit */
1992 bnx2_write_phy(bp, 0x18, 0x7);
1993 bnx2_read_phy(bp, 0x18, &val);
1994 bnx2_write_phy(bp, 0x18, val | 0x4000);
1995
1996 bnx2_read_phy(bp, 0x10, &val);
1997 bnx2_write_phy(bp, 0x10, val | 0x1);
1998 }
1999 else {
b6016b76
MC		 2000 bnx2_write_phy(bp, 0x18, 0x7);
2001 bnx2_read_phy(bp, 0x18, &val);
2002 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2003
2004 bnx2_read_phy(bp, 0x10, &val);
2005 bnx2_write_phy(bp, 0x10, val & ~0x1);
2006 }
2007
5b0c76ad
MC		 2008 /* ethernet@wirespeed */
2009 bnx2_write_phy(bp, 0x18, 0x7007);
2010 bnx2_read_phy(bp, 0x18, &val);
2011 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2012 return 0;
2013}
2014
2015
2016static int
2017bnx2_init_phy(struct bnx2 *bp)
2018{
2019 u32 val;
2020 int rc = 0;
2021
583c28e5
MC		 2022 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2023 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2024
ca58c3af
MC		 2025 bp->mii_bmcr = MII_BMCR;
2026 bp->mii_bmsr = MII_BMSR;
27a005b8 2027 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2028 bp->mii_adv = MII_ADVERTISE;
2029 bp->mii_lpa = MII_LPA;
2030
b6016b76
MC		 2031 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2032
583c28e5 2033 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2034 goto setup_phy;
2035
b6016b76
MC		 2036 bnx2_read_phy(bp, MII_PHYSID1, &val);
2037 bp->phy_id = val << 16;
2038 bnx2_read_phy(bp, MII_PHYSID2, &val);
2039 bp->phy_id |= val & 0xffff;
2040
583c28e5 2041 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 2042 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2043 rc = bnx2_init_5706s_phy(bp);
2044 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2045 rc = bnx2_init_5708s_phy(bp);
27a005b8
MC		 2046 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2047 rc = bnx2_init_5709s_phy(bp);
b6016b76
MC		 2048 }
2049 else {
2050 rc = bnx2_init_copper_phy(bp);
2051 }
2052
0d8a6571
MC		 2053setup_phy:
2054 if (!rc)
2055 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2056
2057 return rc;
2058}
2059
2060static int
2061bnx2_set_mac_loopback(struct bnx2 *bp)
2062{
2063 u32 mac_mode;
2064
2065 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2066 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2067 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2068 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2069 bp->link_up = 1;
2070 return 0;
2071}
2072
bc5a0690
MC		 2073static int bnx2_test_link(struct bnx2 *);
2074
2075static int
2076bnx2_set_phy_loopback(struct bnx2 *bp)
2077{
2078 u32 mac_mode;
2079 int rc, i;
2080
2081 spin_lock_bh(&bp->phy_lock);
ca58c3af 2082 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2083 BMCR_SPEED1000);
2084 spin_unlock_bh(&bp->phy_lock);
2085 if (rc)
2086 return rc;
2087
2088 for (i = 0; i < 10; i++) {
2089 if (bnx2_test_link(bp) == 0)
2090 break;
80be4434 2091 msleep(100);
bc5a0690
MC		 2092 }
2093
2094 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2095 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2096 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2097 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2098
2099 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2100 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2101 bp->link_up = 1;
2102 return 0;
2103}
2104
b6016b76 2105static int
b090ae2b 2106bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 2107{
2108 int i;
2109 u32 val;
2110
b6016b76
MC		 2111 bp->fw_wr_seq++;
2112 msg_data |= bp->fw_wr_seq;
2113
e3648b3d 2114 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76
MC		 2115
2116 /* wait for an acknowledgement. */
b090ae2b
MC		 2117 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2118 msleep(10);
b6016b76 2119
e3648b3d 2120 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
b6016b76
MC		 2121
2122 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2123 break;
2124 }
b090ae2b
MC		 2125 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2126 return 0;
b6016b76
MC		 2127
2128 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2129 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2130 if (!silent)
2131 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2132 "%x\n", msg_data);
b6016b76
MC		 2133
2134 msg_data &= ~BNX2_DRV_MSG_CODE;
2135 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2136
e3648b3d 2137 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76 2138
b6016b76
MC		 2139 return -EBUSY;
2140 }
2141
b090ae2b
MC		 2142 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2143 return -EIO;
2144
b6016b76
MC		 2145 return 0;
2146}
2147
59b47d8a
MC		 2148static int
2149bnx2_init_5709_context(struct bnx2 *bp)
2150{
2151 int i, ret = 0;
2152 u32 val;
2153
2154 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2155 val |= (BCM_PAGE_BITS - 8) << 16;
2156 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2157 for (i = 0; i < 10; i++) {
2158 val = REG_RD(bp, BNX2_CTX_COMMAND);
2159 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2160 break;
2161 udelay(2);
2162 }
2163 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2164 return -EBUSY;
2165
59b47d8a
MC		 2166 for (i = 0; i < bp->ctx_pages; i++) {
2167 int j;
2168
2169 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2170 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2171 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2172 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2173 (u64) bp->ctx_blk_mapping[i] >> 32);
2174 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2175 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2176 for (j = 0; j < 10; j++) {
2177
2178 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2179 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2180 break;
2181 udelay(5);
2182 }
2183 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2184 ret = -EBUSY;
2185 break;
2186 }
2187 }
2188 return ret;
2189}
2190
b6016b76
MC		 2191static void
2192bnx2_init_context(struct bnx2 *bp)
2193{
2194 u32 vcid;
2195
2196 vcid = 96;
2197 while (vcid) {
2198 u32 vcid_addr, pcid_addr, offset;
7947b20e 2199 int i;
b6016b76
MC		 2200
2201 vcid--;
2202
2203 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2204 u32 new_vcid;
2205
2206 vcid_addr = GET_PCID_ADDR(vcid);
2207 if (vcid & 0x8) {
2208 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2209 }
2210 else {
2211 new_vcid = vcid;
2212 }
2213 pcid_addr = GET_PCID_ADDR(new_vcid);
2214 }
2215 else {
2216 vcid_addr = GET_CID_ADDR(vcid);
2217 pcid_addr = vcid_addr;
2218 }
2219
7947b20e
MC		 2220 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2221 vcid_addr += (i << PHY_CTX_SHIFT);
2222 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2223
5d5d0015 2224 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2225 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2226
7947b20e
MC		 2227 /* Zero out the context. */
2228 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
5d5d0015 2229 CTX_WR(bp, vcid_addr, offset, 0);
7947b20e 2230 }
b6016b76
MC		 2231 }
2232}
2233
2234static int
2235bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2236{
2237 u16 *good_mbuf;
2238 u32 good_mbuf_cnt;
2239 u32 val;
2240
2241 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2242 if (good_mbuf == NULL) {
2243 printk(KERN_ERR PFX "Failed to allocate memory in "
2244 "bnx2_alloc_bad_rbuf\n");
2245 return -ENOMEM;
2246 }
2247
2248 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2249 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2250
2251 good_mbuf_cnt = 0;
2252
2253 /* Allocate a bunch of mbufs and save the good ones in an array. */
2254 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2255 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2256 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2257
2258 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2259
2260 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2261
2262 /* The addresses with Bit 9 set are bad memory blocks. */
2263 if (!(val & (1 << 9))) {
2264 good_mbuf[good_mbuf_cnt] = (u16) val;
2265 good_mbuf_cnt++;
2266 }
2267
2268 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2269 }
2270
2271 /* Free the good ones back to the mbuf pool thus discarding
2272 * all the bad ones. */
2273 while (good_mbuf_cnt) {
2274 good_mbuf_cnt--;
2275
2276 val = good_mbuf[good_mbuf_cnt];
2277 val = (val << 9) | val | 1;
2278
2279 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2280 }
2281 kfree(good_mbuf);
2282 return 0;
2283}
2284
2285static void
6aa20a22 2286bnx2_set_mac_addr(struct bnx2 *bp)
b6016b76
MC		 2287{
2288 u32 val;
2289 u8 *mac_addr = bp->dev->dev_addr;
2290
2291 val = (mac_addr[0] << 8) | mac_addr[1];
2292
2293 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2294
6aa20a22 2295 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2296 (mac_addr[4] << 8) | mac_addr[5];
2297
2298 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2299}
2300
47bf4246
MC		 2301static inline int
2302bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2303{
2304 dma_addr_t mapping;
2305 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2306 struct rx_bd *rxbd =
2307 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2308 struct page *page = alloc_page(GFP_ATOMIC);
2309
2310 if (!page)
2311 return -ENOMEM;
2312 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2313 PCI_DMA_FROMDEVICE);
2314 rx_pg->page = page;
2315 pci_unmap_addr_set(rx_pg, mapping, mapping);
2316 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2317 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2318 return 0;
2319}
2320
2321static void
2322bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2323{
2324 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2325 struct page *page = rx_pg->page;
2326
2327 if (!page)
2328 return;
2329
2330 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2331 PCI_DMA_FROMDEVICE);
2332
2333 __free_page(page);
2334 rx_pg->page = NULL;
2335}
2336
b6016b76 2337static inline int
a1f60190 2338bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
b6016b76
MC		 2339{
2340 struct sk_buff *skb;
2341 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2342 dma_addr_t mapping;
13daffa2 2343 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2344 unsigned long align;
2345
932f3772 2346 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2347 if (skb == NULL) {
2348 return -ENOMEM;
2349 }
2350
59b47d8a
MC		 2351 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2352 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2353
b6016b76
MC		 2354 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2355 PCI_DMA_FROMDEVICE);
2356
2357 rx_buf->skb = skb;
2358 pci_unmap_addr_set(rx_buf, mapping, mapping);
2359
2360 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2361 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2362
a1f60190 2363 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2364
2365 return 0;
2366}
2367
da3e4fbe 2368static int
35efa7c1 2369bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2370{
35efa7c1 2371 struct status_block *sblk = bnapi->status_blk;
b6016b76 2372 u32 new_link_state, old_link_state;
da3e4fbe 2373 int is_set = 1;
b6016b76 2374
da3e4fbe
MC		 2375 new_link_state = sblk->status_attn_bits & event;
2376 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2377 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2378 if (new_link_state)
2379 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2380 else
2381 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2382 } else
2383 is_set = 0;
2384
2385 return is_set;
2386}
2387
2388static void
35efa7c1 2389bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2390{
35efa7c1 2391 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {
da3e4fbe 2392 spin_lock(&bp->phy_lock);
b6016b76 2393 bnx2_set_link(bp);
da3e4fbe 2394 spin_unlock(&bp->phy_lock);
b6016b76 2395 }
35efa7c1 2396 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2397 bnx2_set_remote_link(bp);
2398
b6016b76
MC		 2399}
2400
ead7270b 2401static inline u16
35efa7c1 2402bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2403{
2404 u16 cons;
2405
c76c0475
MC		 2406 if (bnapi->int_num == 0)
2407 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2408 else
2409 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
ead7270b
MC		 2410
2411 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2412 cons++;
2413 return cons;
2414}
2415
57851d84
MC		 2416static int
2417bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2418{
2419 u16 hw_cons, sw_cons, sw_ring_cons;
57851d84 2420 int tx_pkt = 0;
b6016b76 2421
35efa7c1 2422 hw_cons = bnx2_get_hw_tx_cons(bnapi);
a550c99b 2423 sw_cons = bnapi->tx_cons;
b6016b76
MC		 2424
2425 while (sw_cons != hw_cons) {
2426 struct sw_bd *tx_buf;
2427 struct sk_buff *skb;
2428 int i, last;
2429
2430 sw_ring_cons = TX_RING_IDX(sw_cons);
2431
2432 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2433 skb = tx_buf->skb;
1d39ed56 2434
b6016b76 2435 /* partial BD completions possible with TSO packets */
89114afd 2436 if (skb_is_gso(skb)) {
b6016b76
MC		 2437 u16 last_idx, last_ring_idx;
2438
2439 last_idx = sw_cons +
2440 skb_shinfo(skb)->nr_frags + 1;
2441 last_ring_idx = sw_ring_cons +
2442 skb_shinfo(skb)->nr_frags + 1;
2443 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2444 last_idx++;
2445 }
2446 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2447 break;
2448 }
2449 }
1d39ed56 2450
b6016b76
MC		 2451 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2452 skb_headlen(skb), PCI_DMA_TODEVICE);
2453
2454 tx_buf->skb = NULL;
2455 last = skb_shinfo(skb)->nr_frags;
2456
2457 for (i = 0; i < last; i++) {
2458 sw_cons = NEXT_TX_BD(sw_cons);
2459
2460 pci_unmap_page(bp->pdev,
2461 pci_unmap_addr(
2462 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2463 mapping),
2464 skb_shinfo(skb)->frags[i].size,
2465 PCI_DMA_TODEVICE);
2466 }
2467
2468 sw_cons = NEXT_TX_BD(sw_cons);
2469
745720e5 2470 dev_kfree_skb(skb);
57851d84
MC		 2471 tx_pkt++;
2472 if (tx_pkt == budget)
2473 break;
b6016b76 2474
35efa7c1 2475 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2476 }
2477
a550c99b
MC		 2478 bnapi->hw_tx_cons = hw_cons;
2479 bnapi->tx_cons = sw_cons;
2f8af120
MC		 2480 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2481 * before checking for netif_queue_stopped(). Without the
2482 * memory barrier, there is a small possibility that bnx2_start_xmit()
2483 * will miss it and cause the queue to be stopped forever.
2484 */
2485 smp_mb();
b6016b76 2486
2f8af120 2487 if (unlikely(netif_queue_stopped(bp->dev)) &&
a550c99b 2488 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2f8af120 2489 netif_tx_lock(bp->dev);
b6016b76 2490 if ((netif_queue_stopped(bp->dev)) &&
a550c99b 2491 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
b6016b76 2492 netif_wake_queue(bp->dev);
2f8af120 2493 netif_tx_unlock(bp->dev);
b6016b76 2494 }
57851d84 2495 return tx_pkt;
b6016b76
MC		 2496}
2497
1db82f2a 2498static void
a1f60190
MC		 2499bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2500 struct sk_buff *skb, int count)
1db82f2a
MC		 2501{
2502 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2503 struct rx_bd *cons_bd, *prod_bd;
2504 dma_addr_t mapping;
2505 int i;
a1f60190
MC		 2506 u16 hw_prod = bnapi->rx_pg_prod, prod;
2507 u16 cons = bnapi->rx_pg_cons;
1db82f2a
MC		 2508
2509 for (i = 0; i < count; i++) {
2510 prod = RX_PG_RING_IDX(hw_prod);
2511
2512 prod_rx_pg = &bp->rx_pg_ring[prod];
2513 cons_rx_pg = &bp->rx_pg_ring[cons];
2514 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2515 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2516
2517 if (i == 0 && skb) {
2518 struct page *page;
2519 struct skb_shared_info *shinfo;
2520
2521 shinfo = skb_shinfo(skb);
2522 shinfo->nr_frags--;
2523 page = shinfo->frags[shinfo->nr_frags].page;
2524 shinfo->frags[shinfo->nr_frags].page = NULL;
2525 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2526 PCI_DMA_FROMDEVICE);
2527 cons_rx_pg->page = page;
2528 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2529 dev_kfree_skb(skb);
2530 }
2531 if (prod != cons) {
2532 prod_rx_pg->page = cons_rx_pg->page;
2533 cons_rx_pg->page = NULL;
2534 pci_unmap_addr_set(prod_rx_pg, mapping,
2535 pci_unmap_addr(cons_rx_pg, mapping));
2536
2537 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2538 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2539
2540 }
2541 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2542 hw_prod = NEXT_RX_BD(hw_prod);
2543 }
a1f60190
MC		 2544 bnapi->rx_pg_prod = hw_prod;
2545 bnapi->rx_pg_cons = cons;
1db82f2a
MC		 2546}
2547
b6016b76 2548static inline void
a1f60190 2549bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
b6016b76
MC		 2550 u16 cons, u16 prod)
2551{
236b6394
MC		 2552 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2553 struct rx_bd *cons_bd, *prod_bd;
2554
2555 cons_rx_buf = &bp->rx_buf_ring[cons];
2556 prod_rx_buf = &bp->rx_buf_ring[prod];
b6016b76
MC		 2557
2558 pci_dma_sync_single_for_device(bp->pdev,
2559 pci_unmap_addr(cons_rx_buf, mapping),
2560 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2561
a1f60190 2562 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2563
236b6394 2564 prod_rx_buf->skb = skb;
b6016b76 2565
236b6394
MC		 2566 if (cons == prod)
2567 return;
b6016b76 2568
236b6394
MC		 2569 pci_unmap_addr_set(prod_rx_buf, mapping,
2570 pci_unmap_addr(cons_rx_buf, mapping));
2571
3fdfcc2c
MC		 2572 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2573 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2574 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2575 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2576}
2577
85833c62 2578static int
a1f60190
MC		 2579bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2580 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2581 u32 ring_idx)
85833c62
MC		 2582{
2583 int err;
2584 u16 prod = ring_idx & 0xffff;
2585
a1f60190 2586 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
85833c62 2587 if (unlikely(err)) {
a1f60190 2588 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2589 if (hdr_len) {
2590 unsigned int raw_len = len + 4;
2591 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2592
a1f60190 2593 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
1db82f2a 2594 }
85833c62
MC		 2595 return err;
2596 }
2597
2598 skb_reserve(skb, bp->rx_offset);
2599 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2600 PCI_DMA_FROMDEVICE);
2601
1db82f2a
MC		 2602 if (hdr_len == 0) {
2603 skb_put(skb, len);
2604 return 0;
2605 } else {
2606 unsigned int i, frag_len, frag_size, pages;
2607 struct sw_pg *rx_pg;
a1f60190
MC		 2608 u16 pg_cons = bnapi->rx_pg_cons;
2609 u16 pg_prod = bnapi->rx_pg_prod;
1db82f2a
MC		 2610
2611 frag_size = len + 4 - hdr_len;
2612 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2613 skb_put(skb, hdr_len);
2614
2615 for (i = 0; i < pages; i++) {
2616 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2617 if (unlikely(frag_len <= 4)) {
2618 unsigned int tail = 4 - frag_len;
2619
a1f60190
MC		 2620 bnapi->rx_pg_cons = pg_cons;
2621 bnapi->rx_pg_prod = pg_prod;
2622 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2623 pages - i);
1db82f2a
MC		 2624 skb->len -= tail;
2625 if (i == 0) {
2626 skb->tail -= tail;
2627 } else {
2628 skb_frag_t *frag =
2629 &skb_shinfo(skb)->frags[i - 1];
2630 frag->size -= tail;
2631 skb->data_len -= tail;
2632 skb->truesize -= tail;
2633 }
2634 return 0;
2635 }
2636 rx_pg = &bp->rx_pg_ring[pg_cons];
2637
2638 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2639 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2640
2641 if (i == pages - 1)
2642 frag_len -= 4;
2643
2644 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2645 rx_pg->page = NULL;
2646
2647 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2648 if (unlikely(err)) {
a1f60190
MC		 2649 bnapi->rx_pg_cons = pg_cons;
2650 bnapi->rx_pg_prod = pg_prod;
2651 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2652 pages - i);
1db82f2a
MC		 2653 return err;
2654 }
2655
2656 frag_size -= frag_len;
2657 skb->data_len += frag_len;
2658 skb->truesize += frag_len;
2659 skb->len += frag_len;
2660
2661 pg_prod = NEXT_RX_BD(pg_prod);
2662 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2663 }
a1f60190
MC		 2664 bnapi->rx_pg_prod = pg_prod;
2665 bnapi->rx_pg_cons = pg_cons;
1db82f2a 2666 }
85833c62
MC		 2667 return 0;
2668}
2669
c09c2627 2670static inline u16
35efa7c1 2671bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 2672{
35efa7c1 2673 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
c09c2627
MC		 2674
2675 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2676 cons++;
2677 return cons;
2678}
2679
b6016b76 2680static int
35efa7c1 2681bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2682{
2683 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2684 struct l2_fhdr *rx_hdr;
1db82f2a 2685 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 2686
35efa7c1 2687 hw_cons = bnx2_get_hw_rx_cons(bnapi);
a1f60190
MC		 2688 sw_cons = bnapi->rx_cons;
2689 sw_prod = bnapi->rx_prod;
b6016b76
MC		 2690
2691 /* Memory barrier necessary as speculative reads of the rx
2692 * buffer can be ahead of the index in the status block
2693 */
2694 rmb();
2695 while (sw_cons != hw_cons) {
1db82f2a 2696 unsigned int len, hdr_len;
ade2bfe7 2697 u32 status;
b6016b76
MC		 2698 struct sw_bd *rx_buf;
2699 struct sk_buff *skb;
236b6394 2700 dma_addr_t dma_addr;
b6016b76
MC		 2701
2702 sw_ring_cons = RX_RING_IDX(sw_cons);
2703 sw_ring_prod = RX_RING_IDX(sw_prod);
2704
2705 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2706 skb = rx_buf->skb;
236b6394
MC		 2707
2708 rx_buf->skb = NULL;
2709
2710 dma_addr = pci_unmap_addr(rx_buf, mapping);
2711
2712 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
b6016b76
MC		 2713 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2714
2715 rx_hdr = (struct l2_fhdr *) skb->data;
1db82f2a 2716 len = rx_hdr->l2_fhdr_pkt_len;
b6016b76 2717
ade2bfe7 2718 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 2719 (L2_FHDR_ERRORS_BAD_CRC |
2720 L2_FHDR_ERRORS_PHY_DECODE |
2721 L2_FHDR_ERRORS_ALIGNMENT |
2722 L2_FHDR_ERRORS_TOO_SHORT |
2723 L2_FHDR_ERRORS_GIANT_FRAME)) {
2724
a1f60190
MC		 2725 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2726 sw_ring_prod);
85833c62 2727 goto next_rx;
b6016b76 2728 }
1db82f2a
MC		 2729 hdr_len = 0;
2730 if (status & L2_FHDR_STATUS_SPLIT) {
2731 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2732 pg_ring_used = 1;
2733 } else if (len > bp->rx_jumbo_thresh) {
2734 hdr_len = bp->rx_jumbo_thresh;
2735 pg_ring_used = 1;
2736 }
2737
2738 len -= 4;
b6016b76 2739
5d5d0015 2740 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 2741 struct sk_buff *new_skb;
2742
932f3772 2743 new_skb = netdev_alloc_skb(bp->dev, len + 2);
85833c62 2744 if (new_skb == NULL) {
a1f60190 2745 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
85833c62
MC		 2746 sw_ring_prod);
2747 goto next_rx;
2748 }
b6016b76
MC		 2749
2750 /* aligned copy */
d626f62b
ACM		 2751 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2752 new_skb->data, len + 2);
b6016b76
MC		 2753 skb_reserve(new_skb, 2);
2754 skb_put(new_skb, len);
b6016b76 2755
a1f60190 2756 bnx2_reuse_rx_skb(bp, bnapi, skb,
b6016b76
MC		 2757 sw_ring_cons, sw_ring_prod);
2758
2759 skb = new_skb;
a1f60190
MC		 2760 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2761 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 2762 goto next_rx;
b6016b76
MC		 2763
2764 skb->protocol = eth_type_trans(skb, bp->dev);
2765
2766 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 2767 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 2768
745720e5 2769 dev_kfree_skb(skb);
b6016b76
MC		 2770 goto next_rx;
2771
2772 }
2773
b6016b76
MC		 2774 skb->ip_summed = CHECKSUM_NONE;
2775 if (bp->rx_csum &&
2776 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2777 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2778
ade2bfe7
MC		 2779 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2780 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 2781 skb->ip_summed = CHECKSUM_UNNECESSARY;
2782 }
2783
2784#ifdef BCM_VLAN
79ea13ce 2785 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
b6016b76
MC		 2786 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2787 rx_hdr->l2_fhdr_vlan_tag);
2788 }
2789 else
2790#endif
2791 netif_receive_skb(skb);
2792
2793 bp->dev->last_rx = jiffies;
2794 rx_pkt++;
2795
2796next_rx:
b6016b76
MC		 2797 sw_cons = NEXT_RX_BD(sw_cons);
2798 sw_prod = NEXT_RX_BD(sw_prod);
2799
2800 if ((rx_pkt == budget))
2801 break;
f4e418f7
MC		 2802
2803 /* Refresh hw_cons to see if there is new work */
2804 if (sw_cons == hw_cons) {
35efa7c1 2805 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 2806 rmb();
2807 }
b6016b76 2808 }
a1f60190
MC		 2809 bnapi->rx_cons = sw_cons;
2810 bnapi->rx_prod = sw_prod;
b6016b76 2811
1db82f2a
MC		 2812 if (pg_ring_used)
2813 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
a1f60190 2814 bnapi->rx_pg_prod);
1db82f2a 2815
b6016b76
MC		 2816 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2817
a1f60190 2818 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 2819
2820 mmiowb();
2821
2822 return rx_pkt;
2823
2824}
2825
2826/* MSI ISR - The only difference between this and the INTx ISR
2827 * is that the MSI interrupt is always serviced.
2828 */
2829static irqreturn_t
7d12e780 2830bnx2_msi(int irq, void *dev_instance)
b6016b76
MC		 2831{
2832 struct net_device *dev = dev_instance;
972ec0d4 2833 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2834 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
b6016b76 2835
35efa7c1 2836 prefetch(bnapi->status_blk);
b6016b76
MC		 2837 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2838 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2839 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2840
2841 /* Return here if interrupt is disabled. */
73eef4cd
MC		 2842 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2843 return IRQ_HANDLED;
b6016b76 2844
35efa7c1 2845 netif_rx_schedule(dev, &bnapi->napi);
b6016b76 2846
73eef4cd 2847 return IRQ_HANDLED;
b6016b76
MC		 2848}
2849
8e6a72c4
MC		 2850static irqreturn_t
2851bnx2_msi_1shot(int irq, void *dev_instance)
2852{
2853 struct net_device *dev = dev_instance;
2854 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2855 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
8e6a72c4 2856
35efa7c1 2857 prefetch(bnapi->status_blk);
8e6a72c4
MC		 2858
2859 /* Return here if interrupt is disabled. */
2860 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2861 return IRQ_HANDLED;
2862
35efa7c1 2863 netif_rx_schedule(dev, &bnapi->napi);
8e6a72c4
MC		 2864
2865 return IRQ_HANDLED;
2866}
2867
b6016b76 2868static irqreturn_t
7d12e780 2869bnx2_interrupt(int irq, void *dev_instance)
b6016b76
MC		 2870{
2871 struct net_device *dev = dev_instance;
972ec0d4 2872 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2873 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
35efa7c1 2874 struct status_block *sblk = bnapi->status_blk;
b6016b76
MC		 2875
2876 /* When using INTx, it is possible for the interrupt to arrive
2877 * at the CPU before the status block posted prior to the
2878 * interrupt. Reading a register will flush the status block.
2879 * When using MSI, the MSI message will always complete after
2880 * the status block write.
2881 */
35efa7c1 2882 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 2883 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2884 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 2885 return IRQ_NONE;
b6016b76
MC		 2886
2887 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2888 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2889 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2890
b8a7ce7b
MC		 2891 /* Read back to deassert IRQ immediately to avoid too many
2892 * spurious interrupts.
2893 */
2894 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2895
b6016b76 2896 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 2897 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2898 return IRQ_HANDLED;
b6016b76 2899
35efa7c1
MC		 2900 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2901 bnapi->last_status_idx = sblk->status_idx;
2902 __netif_rx_schedule(dev, &bnapi->napi);
b8a7ce7b 2903 }
b6016b76 2904
73eef4cd 2905 return IRQ_HANDLED;
b6016b76
MC		 2906}
2907
57851d84
MC		 2908static irqreturn_t
2909bnx2_tx_msix(int irq, void *dev_instance)
2910{
2911 struct net_device *dev = dev_instance;
2912 struct bnx2 *bp = netdev_priv(dev);
2913 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2914
2915 prefetch(bnapi->status_blk_msix);
2916
2917 /* Return here if interrupt is disabled. */
2918 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2919 return IRQ_HANDLED;
2920
2921 netif_rx_schedule(dev, &bnapi->napi);
2922 return IRQ_HANDLED;
2923}
2924
0d8a6571
MC		 2925#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2926 STATUS_ATTN_BITS_TIMER_ABORT)
da3e4fbe 2927
f4e418f7 2928static inline int
35efa7c1 2929bnx2_has_work(struct bnx2_napi *bnapi)
f4e418f7 2930{
1097f5e9 2931 struct status_block *sblk = bnapi->status_blk;
f4e418f7 2932
a1f60190 2933 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
a550c99b 2934 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
f4e418f7
MC		 2935 return 1;
2936
da3e4fbe
MC		 2937 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2938 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 2939 return 1;
2940
2941 return 0;
2942}
2943
57851d84
MC		 2944static int bnx2_tx_poll(struct napi_struct *napi, int budget)
2945{
2946 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
2947 struct bnx2 *bp = bnapi->bp;
2948 int work_done = 0;
2949 struct status_block_msix *sblk = bnapi->status_blk_msix;
2950
2951 do {
2952 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
2953 if (unlikely(work_done >= budget))
2954 return work_done;
2955
2956 bnapi->last_status_idx = sblk->status_idx;
2957 rmb();
2958 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
2959
2960 netif_rx_complete(bp->dev, napi);
2961 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
2962 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2963 bnapi->last_status_idx);
2964 return work_done;
2965}
2966
35efa7c1
MC		 2967static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
2968 int work_done, int budget)
b6016b76 2969{
35efa7c1 2970 struct status_block *sblk = bnapi->status_blk;
da3e4fbe
MC		 2971 u32 status_attn_bits = sblk->status_attn_bits;
2972 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 2973
da3e4fbe
MC		 2974 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2975 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 2976
35efa7c1 2977 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 2978
2979 /* This is needed to take care of transient status
2980 * during link changes.
2981 */
2982 REG_WR(bp, BNX2_HC_COMMAND,
2983 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2984 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 2985 }
2986
a550c99b 2987 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
57851d84 2988 bnx2_tx_int(bp, bnapi, 0);
b6016b76 2989
a1f60190 2990 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
35efa7c1 2991 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 2992
6f535763
DM		 2993 return work_done;
2994}
2995
2996static int bnx2_poll(struct napi_struct *napi, int budget)
2997{
35efa7c1
MC		 2998 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
2999 struct bnx2 *bp = bnapi->bp;
6f535763 3000 int work_done = 0;
35efa7c1 3001 struct status_block *sblk = bnapi->status_blk;
6f535763
DM		 3002
3003 while (1) {
35efa7c1 3004 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3005
6f535763
DM		 3006 if (unlikely(work_done >= budget))
3007 break;
3008
35efa7c1 3009 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3010 * much work has been processed, so we must read it before
3011 * checking for more work.
3012 */
35efa7c1 3013 bnapi->last_status_idx = sblk->status_idx;
6dee6421 3014 rmb();
35efa7c1 3015 if (likely(!bnx2_has_work(bnapi))) {
6f535763 3016 netif_rx_complete(bp->dev, napi);
f86e82fb 3017 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3018 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3019 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3020 bnapi->last_status_idx);
6dee6421 3021 break;
6f535763 3022 }
1269a8a6
MC		 3023 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3024 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3025 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3026 bnapi->last_status_idx);
1269a8a6 3027
6f535763
DM		 3028 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3029 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3030 bnapi->last_status_idx);
6f535763
DM		 3031 break;
3032 }
b6016b76
MC		 3033 }
3034
bea3348e 3035 return work_done;
b6016b76
MC		 3036}
3037
932ff279 3038/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3039 * from set_multicast.
3040 */
3041static void
3042bnx2_set_rx_mode(struct net_device *dev)
3043{
972ec0d4 3044 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 3045 u32 rx_mode, sort_mode;
3046 int i;
b6016b76 3047
c770a65c 3048 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3049
3050 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3051 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3052 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3053#ifdef BCM_VLAN
f86e82fb 3054 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
b6016b76 3055 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3056#else
f86e82fb 3057 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
e29054f9 3058 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3059#endif
3060 if (dev->flags & IFF_PROMISC) {
3061 /* Promiscuous mode. */
3062 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3063 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3064 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3065 }
3066 else if (dev->flags & IFF_ALLMULTI) {
3067 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3068 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3069 0xffffffff);
3070 }
3071 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3072 }
3073 else {
3074 /* Accept one or more multicast(s). */
3075 struct dev_mc_list *mclist;
3076 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3077 u32 regidx;
3078 u32 bit;
3079 u32 crc;
3080
3081 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3082
3083 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3084 i++, mclist = mclist->next) {
3085
3086 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3087 bit = crc & 0xff;
3088 regidx = (bit & 0xe0) >> 5;
3089 bit &= 0x1f;
3090 mc_filter[regidx] |= (1 << bit);
3091 }
3092
3093 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3094 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3095 mc_filter[i]);
3096 }
3097
3098 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3099 }
3100
3101 if (rx_mode != bp->rx_mode) {
3102 bp->rx_mode = rx_mode;
3103 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3104 }
3105
3106 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3107 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3108 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3109
c770a65c 3110 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3111}
3112
3113static void
3114load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
3115 u32 rv2p_proc)
3116{
3117 int i;
3118 u32 val;
3119
3120
3121 for (i = 0; i < rv2p_code_len; i += 8) {
fba9fe91 3122 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
b6016b76 3123 rv2p_code++;
fba9fe91 3124 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
b6016b76
MC		 3125 rv2p_code++;
3126
3127 if (rv2p_proc == RV2P_PROC1) {
3128 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3129 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3130 }
3131 else {
3132 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3133 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3134 }
3135 }
3136
3137 /* Reset the processor, un-stall is done later. */
3138 if (rv2p_proc == RV2P_PROC1) {
3139 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3140 }
3141 else {
3142 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3143 }
3144}
3145
af3ee519 3146static int
b6016b76
MC		 3147load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3148{
3149 u32 offset;
3150 u32 val;
af3ee519 3151 int rc;
b6016b76
MC		 3152
3153 /* Halt the CPU. */
3154 val = REG_RD_IND(bp, cpu_reg->mode);
3155 val |= cpu_reg->mode_value_halt;
3156 REG_WR_IND(bp, cpu_reg->mode, val);
3157 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
3158
3159 /* Load the Text area. */
3160 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
af3ee519 3161 if (fw->gz_text) {
b6016b76
MC		 3162 int j;
3163
ea1f8d5c
MC		 3164 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3165 fw->gz_text_len);
3166 if (rc < 0)
b3448b0b 3167 return rc;
ea1f8d5c 3168
b6016b76 3169 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
ea1f8d5c 3170 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
b6016b76
MC		 3171 }
3172 }
3173
3174 /* Load the Data area. */
3175 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3176 if (fw->data) {
3177 int j;
3178
3179 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3180 REG_WR_IND(bp, offset, fw->data[j]);
3181 }
3182 }
3183
3184 /* Load the SBSS area. */
3185 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3186 if (fw->sbss_len) {
b6016b76
MC		 3187 int j;
3188
3189 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
ea1f8d5c 3190 REG_WR_IND(bp, offset, 0);
b6016b76
MC		 3191 }
3192 }
3193
3194 /* Load the BSS area. */
3195 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3196 if (fw->bss_len) {
b6016b76
MC		 3197 int j;
3198
3199 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
ea1f8d5c 3200 REG_WR_IND(bp, offset, 0);
b6016b76
MC		 3201 }
3202 }
3203
3204 /* Load the Read-Only area. */
3205 offset = cpu_reg->spad_base +
3206 (fw->rodata_addr - cpu_reg->mips_view_base);
3207 if (fw->rodata) {
3208 int j;
3209
3210 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3211 REG_WR_IND(bp, offset, fw->rodata[j]);
3212 }
3213 }
3214
3215 /* Clear the pre-fetch instruction. */
3216 REG_WR_IND(bp, cpu_reg->inst, 0);
3217 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
3218
3219 /* Start the CPU. */
3220 val = REG_RD_IND(bp, cpu_reg->mode);
3221 val &= ~cpu_reg->mode_value_halt;
3222 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
3223 REG_WR_IND(bp, cpu_reg->mode, val);
af3ee519
MC		 3224
3225 return 0;
b6016b76
MC		 3226}
3227
fba9fe91 3228static int
b6016b76
MC		 3229bnx2_init_cpus(struct bnx2 *bp)
3230{
3231 struct cpu_reg cpu_reg;
af3ee519 3232 struct fw_info *fw;
110d0ef9
MC		 3233 int rc, rv2p_len;
3234 void *text, *rv2p;
b6016b76
MC		 3235
3236 /* Initialize the RV2P processor. */
b3448b0b
DV		 3237 text = vmalloc(FW_BUF_SIZE);
3238 if (!text)
3239 return -ENOMEM;
110d0ef9
MC		 3240 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3241 rv2p = bnx2_xi_rv2p_proc1;
3242 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3243 } else {
3244 rv2p = bnx2_rv2p_proc1;
3245 rv2p_len = sizeof(bnx2_rv2p_proc1);
3246 }
3247 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3248 if (rc < 0)
fba9fe91 3249 goto init_cpu_err;
ea1f8d5c 3250
b3448b0b 3251 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
fba9fe91 3252
110d0ef9
MC		 3253 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3254 rv2p = bnx2_xi_rv2p_proc2;
3255 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3256 } else {
3257 rv2p = bnx2_rv2p_proc2;
3258 rv2p_len = sizeof(bnx2_rv2p_proc2);
3259 }
3260 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3261 if (rc < 0)
fba9fe91 3262 goto init_cpu_err;
ea1f8d5c 3263
b3448b0b 3264 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
b6016b76
MC		 3265
3266 /* Initialize the RX Processor. */
3267 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3268 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3269 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3270 cpu_reg.state = BNX2_RXP_CPU_STATE;
3271 cpu_reg.state_value_clear = 0xffffff;
3272 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3273 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3274 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3275 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3276 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3277 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3278 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3279
d43584c8
MC		 3280 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3281 fw = &bnx2_rxp_fw_09;
3282 else
3283 fw = &bnx2_rxp_fw_06;
fba9fe91 3284
ea1f8d5c 3285 fw->text = text;
af3ee519 3286 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3287 if (rc)
3288 goto init_cpu_err;
3289
b6016b76
MC		 3290 /* Initialize the TX Processor. */
3291 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3292 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3293 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3294 cpu_reg.state = BNX2_TXP_CPU_STATE;
3295 cpu_reg.state_value_clear = 0xffffff;
3296 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3297 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3298 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3299 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3300 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3301 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3302 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3303
d43584c8
MC		 3304 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3305 fw = &bnx2_txp_fw_09;
3306 else
3307 fw = &bnx2_txp_fw_06;
fba9fe91 3308
ea1f8d5c 3309 fw->text = text;
af3ee519 3310 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3311 if (rc)
3312 goto init_cpu_err;
3313
b6016b76
MC		 3314 /* Initialize the TX Patch-up Processor. */
3315 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3316 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3317 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3318 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3319 cpu_reg.state_value_clear = 0xffffff;
3320 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3321 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3322 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3323 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3324 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3325 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3326 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3327
d43584c8
MC		 3328 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3329 fw = &bnx2_tpat_fw_09;
3330 else
3331 fw = &bnx2_tpat_fw_06;
fba9fe91 3332
ea1f8d5c 3333 fw->text = text;
af3ee519 3334 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3335 if (rc)
3336 goto init_cpu_err;
3337
b6016b76
MC		 3338 /* Initialize the Completion Processor. */
3339 cpu_reg.mode = BNX2_COM_CPU_MODE;
3340 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3341 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3342 cpu_reg.state = BNX2_COM_CPU_STATE;
3343 cpu_reg.state_value_clear = 0xffffff;
3344 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3345 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3346 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3347 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3348 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3349 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3350 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3351
d43584c8
MC		 3352 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3353 fw = &bnx2_com_fw_09;
3354 else
3355 fw = &bnx2_com_fw_06;
fba9fe91 3356
ea1f8d5c 3357 fw->text = text;
af3ee519 3358 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3359 if (rc)
3360 goto init_cpu_err;
3361
d43584c8
MC		 3362 /* Initialize the Command Processor. */
3363 cpu_reg.mode = BNX2_CP_CPU_MODE;
3364 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3365 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3366 cpu_reg.state = BNX2_CP_CPU_STATE;
3367 cpu_reg.state_value_clear = 0xffffff;
3368 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3369 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3370 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3371 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3372 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3373 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3374 cpu_reg.mips_view_base = 0x8000000;
b6016b76 3375
110d0ef9 3376 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d43584c8 3377 fw = &bnx2_cp_fw_09;
110d0ef9
MC		 3378 else
3379 fw = &bnx2_cp_fw_06;
3380
3381 fw->text = text;
3382 rc = load_cpu_fw(bp, &cpu_reg, fw);
b6016b76 3383
fba9fe91 3384init_cpu_err:
ea1f8d5c 3385 vfree(text);
fba9fe91 3386 return rc;
b6016b76
MC		 3387}
3388
3389static int
829ca9a3 3390bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3391{
3392 u16 pmcsr;
3393
3394 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3395
3396 switch (state) {
829ca9a3 3397 case PCI_D0: {
b6016b76
MC		 3398 u32 val;
3399
3400 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3401 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3402 PCI_PM_CTRL_PME_STATUS);
3403
3404 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3405 /* delay required during transition out of D3hot */
3406 msleep(20);
3407
3408 val = REG_RD(bp, BNX2_EMAC_MODE);
3409 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3410 val &= ~BNX2_EMAC_MODE_MPKT;
3411 REG_WR(bp, BNX2_EMAC_MODE, val);
3412
3413 val = REG_RD(bp, BNX2_RPM_CONFIG);
3414 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3415 REG_WR(bp, BNX2_RPM_CONFIG, val);
3416 break;
3417 }
829ca9a3 3418 case PCI_D3hot: {
b6016b76
MC		 3419 int i;
3420 u32 val, wol_msg;
3421
3422 if (bp->wol) {
3423 u32 advertising;
3424 u8 autoneg;
3425
3426 autoneg = bp->autoneg;
3427 advertising = bp->advertising;
3428
239cd343
MC		 3429 if (bp->phy_port == PORT_TP) {
3430 bp->autoneg = AUTONEG_SPEED;
3431 bp->advertising = ADVERTISED_10baseT_Half |
3432 ADVERTISED_10baseT_Full |
3433 ADVERTISED_100baseT_Half |
3434 ADVERTISED_100baseT_Full |
3435 ADVERTISED_Autoneg;
3436 }
b6016b76 3437
239cd343
MC		 3438 spin_lock_bh(&bp->phy_lock);
3439 bnx2_setup_phy(bp, bp->phy_port);
3440 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3441
3442 bp->autoneg = autoneg;
3443 bp->advertising = advertising;
3444
3445 bnx2_set_mac_addr(bp);
3446
3447 val = REG_RD(bp, BNX2_EMAC_MODE);
3448
3449 /* Enable port mode. */
3450 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3451 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3452 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3453 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3454 if (bp->phy_port == PORT_TP)
3455 val |= BNX2_EMAC_MODE_PORT_MII;
3456 else {
3457 val |= BNX2_EMAC_MODE_PORT_GMII;
3458 if (bp->line_speed == SPEED_2500)
3459 val |= BNX2_EMAC_MODE_25G_MODE;
3460 }
b6016b76
MC		 3461
3462 REG_WR(bp, BNX2_EMAC_MODE, val);
3463
3464 /* receive all multicast */
3465 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3466 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3467 0xffffffff);
3468 }
3469 REG_WR(bp, BNX2_EMAC_RX_MODE,
3470 BNX2_EMAC_RX_MODE_SORT_MODE);
3471
3472 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3473 BNX2_RPM_SORT_USER0_MC_EN;
3474 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3475 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3476 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3477 BNX2_RPM_SORT_USER0_ENA);
3478
3479 /* Need to enable EMAC and RPM for WOL. */
3480 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3481 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3482 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3483 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3484
3485 val = REG_RD(bp, BNX2_RPM_CONFIG);
3486 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3487 REG_WR(bp, BNX2_RPM_CONFIG, val);
3488
3489 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3490 }
3491 else {
3492 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3493 }
3494
f86e82fb 3495 if (!(bp->flags & BNX2_FLAG_NO_WOL))
dda1e390 3496 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 3497
3498 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3499 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3500 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3501
3502 if (bp->wol)
3503 pmcsr |= 3;
3504 }
3505 else {
3506 pmcsr |= 3;
3507 }
3508 if (bp->wol) {
3509 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3510 }
3511 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3512 pmcsr);
3513
3514 /* No more memory access after this point until
3515 * device is brought back to D0.
3516 */
3517 udelay(50);
3518 break;
3519 }
3520 default:
3521 return -EINVAL;
3522 }
3523 return 0;
3524}
3525
3526static int
3527bnx2_acquire_nvram_lock(struct bnx2 *bp)
3528{
3529 u32 val;
3530 int j;
3531
3532 /* Request access to the flash interface. */
3533 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3534 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3535 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3536 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3537 break;
3538
3539 udelay(5);
3540 }
3541
3542 if (j >= NVRAM_TIMEOUT_COUNT)
3543 return -EBUSY;
3544
3545 return 0;
3546}
3547
3548static int
3549bnx2_release_nvram_lock(struct bnx2 *bp)
3550{
3551 int j;
3552 u32 val;
3553
3554 /* Relinquish nvram interface. */
3555 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3556
3557 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3558 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3559 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3560 break;
3561
3562 udelay(5);
3563 }
3564
3565 if (j >= NVRAM_TIMEOUT_COUNT)
3566 return -EBUSY;
3567
3568 return 0;
3569}
3570
3571
3572static int
3573bnx2_enable_nvram_write(struct bnx2 *bp)
3574{
3575 u32 val;
3576
3577 val = REG_RD(bp, BNX2_MISC_CFG);
3578 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3579
e30372c9 3580 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 3581 int j;
3582
3583 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3584 REG_WR(bp, BNX2_NVM_COMMAND,
3585 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3586
3587 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3588 udelay(5);
3589
3590 val = REG_RD(bp, BNX2_NVM_COMMAND);
3591 if (val & BNX2_NVM_COMMAND_DONE)
3592 break;
3593 }
3594
3595 if (j >= NVRAM_TIMEOUT_COUNT)
3596 return -EBUSY;
3597 }
3598 return 0;
3599}
3600
3601static void
3602bnx2_disable_nvram_write(struct bnx2 *bp)
3603{
3604 u32 val;
3605
3606 val = REG_RD(bp, BNX2_MISC_CFG);
3607 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3608}
3609
3610
3611static void
3612bnx2_enable_nvram_access(struct bnx2 *bp)
3613{
3614 u32 val;
3615
3616 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3617 /* Enable both bits, even on read. */
6aa20a22 3618 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3619 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3620}
3621
3622static void
3623bnx2_disable_nvram_access(struct bnx2 *bp)
3624{
3625 u32 val;
3626
3627 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3628 /* Disable both bits, even after read. */
6aa20a22 3629 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3630 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3631 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3632}
3633
3634static int
3635bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3636{
3637 u32 cmd;
3638 int j;
3639
e30372c9 3640 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 3641 /* Buffered flash, no erase needed */
3642 return 0;
3643
3644 /* Build an erase command */
3645 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3646 BNX2_NVM_COMMAND_DOIT;
3647
3648 /* Need to clear DONE bit separately. */
3649 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3650
3651 /* Address of the NVRAM to read from. */
3652 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3653
3654 /* Issue an erase command. */
3655 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3656
3657 /* Wait for completion. */
3658 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3659 u32 val;
3660
3661 udelay(5);
3662
3663 val = REG_RD(bp, BNX2_NVM_COMMAND);
3664 if (val & BNX2_NVM_COMMAND_DONE)
3665 break;
3666 }
3667
3668 if (j >= NVRAM_TIMEOUT_COUNT)
3669 return -EBUSY;
3670
3671 return 0;
3672}
3673
3674static int
3675bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3676{
3677 u32 cmd;
3678 int j;
3679
3680 /* Build the command word. */
3681 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3682
e30372c9
MC		 3683 /* Calculate an offset of a buffered flash, not needed for 5709. */
3684 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3685 offset = ((offset / bp->flash_info->page_size) <<
3686 bp->flash_info->page_bits) +
3687 (offset % bp->flash_info->page_size);
3688 }
3689
3690 /* Need to clear DONE bit separately. */
3691 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3692
3693 /* Address of the NVRAM to read from. */
3694 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3695
3696 /* Issue a read command. */
3697 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3698
3699 /* Wait for completion. */
3700 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3701 u32 val;
3702
3703 udelay(5);
3704
3705 val = REG_RD(bp, BNX2_NVM_COMMAND);
3706 if (val & BNX2_NVM_COMMAND_DONE) {
3707 val = REG_RD(bp, BNX2_NVM_READ);
3708
3709 val = be32_to_cpu(val);
3710 memcpy(ret_val, &val, 4);
3711 break;
3712 }
3713 }
3714 if (j >= NVRAM_TIMEOUT_COUNT)
3715 return -EBUSY;
3716
3717 return 0;
3718}
3719
3720
3721static int
3722bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3723{
3724 u32 cmd, val32;
3725 int j;
3726
3727 /* Build the command word. */
3728 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3729
e30372c9
MC		 3730 /* Calculate an offset of a buffered flash, not needed for 5709. */
3731 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3732 offset = ((offset / bp->flash_info->page_size) <<
3733 bp->flash_info->page_bits) +
3734 (offset % bp->flash_info->page_size);
3735 }
3736
3737 /* Need to clear DONE bit separately. */
3738 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3739
3740 memcpy(&val32, val, 4);
3741 val32 = cpu_to_be32(val32);
3742
3743 /* Write the data. */
3744 REG_WR(bp, BNX2_NVM_WRITE, val32);
3745
3746 /* Address of the NVRAM to write to. */
3747 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3748
3749 /* Issue the write command. */
3750 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3751
3752 /* Wait for completion. */
3753 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3754 udelay(5);
3755
3756 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3757 break;
3758 }
3759 if (j >= NVRAM_TIMEOUT_COUNT)
3760 return -EBUSY;
3761
3762 return 0;
3763}
3764
3765static int
3766bnx2_init_nvram(struct bnx2 *bp)
3767{
3768 u32 val;
e30372c9 3769 int j, entry_count, rc = 0;
b6016b76
MC		 3770 struct flash_spec *flash;
3771
e30372c9
MC		 3772 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3773 bp->flash_info = &flash_5709;
3774 goto get_flash_size;
3775 }
3776
b6016b76
MC		 3777 /* Determine the selected interface. */
3778 val = REG_RD(bp, BNX2_NVM_CFG1);
3779
ff8ac609 3780 entry_count = ARRAY_SIZE(flash_table);
b6016b76 3781
b6016b76
MC		 3782 if (val & 0x40000000) {
3783
3784 /* Flash interface has been reconfigured */
3785 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 3786 j++, flash++) {
3787 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3788 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 3789 bp->flash_info = flash;
3790 break;
3791 }
3792 }
3793 }
3794 else {
37137709 3795 u32 mask;
b6016b76
MC		 3796 /* Not yet been reconfigured */
3797
37137709
MC		 3798 if (val & (1 << 23))
3799 mask = FLASH_BACKUP_STRAP_MASK;
3800 else
3801 mask = FLASH_STRAP_MASK;
3802
b6016b76
MC		 3803 for (j = 0, flash = &flash_table[0]; j < entry_count;
3804 j++, flash++) {
3805
37137709 3806 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 3807 bp->flash_info = flash;
3808
3809 /* Request access to the flash interface. */
3810 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3811 return rc;
3812
3813 /* Enable access to flash interface */
3814 bnx2_enable_nvram_access(bp);
3815
3816 /* Reconfigure the flash interface */
3817 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3818 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3819 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3820 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3821
3822 /* Disable access to flash interface */
3823 bnx2_disable_nvram_access(bp);
3824 bnx2_release_nvram_lock(bp);
3825
3826 break;
3827 }
3828 }
3829 } /* if (val & 0x40000000) */
3830
3831 if (j == entry_count) {
3832 bp->flash_info = NULL;
2f23c523 3833 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 3834 return -ENODEV;
b6016b76
MC		 3835 }
3836
e30372c9 3837get_flash_size:
1122db71
MC		 3838 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3839 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3840 if (val)
3841 bp->flash_size = val;
3842 else
3843 bp->flash_size = bp->flash_info->total_size;
3844
b6016b76
MC		 3845 return rc;
3846}
3847
3848static int
3849bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3850 int buf_size)
3851{
3852 int rc = 0;
3853 u32 cmd_flags, offset32, len32, extra;
3854
3855 if (buf_size == 0)
3856 return 0;
3857
3858 /* Request access to the flash interface. */
3859 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3860 return rc;
3861
3862 /* Enable access to flash interface */
3863 bnx2_enable_nvram_access(bp);
3864
3865 len32 = buf_size;
3866 offset32 = offset;
3867 extra = 0;
3868
3869 cmd_flags = 0;
3870
3871 if (offset32 & 3) {
3872 u8 buf[4];
3873 u32 pre_len;
3874
3875 offset32 &= ~3;
3876 pre_len = 4 - (offset & 3);
3877
3878 if (pre_len >= len32) {
3879 pre_len = len32;
3880 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3881 BNX2_NVM_COMMAND_LAST;
3882 }
3883 else {
3884 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3885 }
3886
3887 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3888
3889 if (rc)
3890 return rc;
3891
3892 memcpy(ret_buf, buf + (offset & 3), pre_len);
3893
3894 offset32 += 4;
3895 ret_buf += pre_len;
3896 len32 -= pre_len;
3897 }
3898 if (len32 & 3) {
3899 extra = 4 - (len32 & 3);
3900 len32 = (len32 + 4) & ~3;
3901 }
3902
3903 if (len32 == 4) {
3904 u8 buf[4];
3905
3906 if (cmd_flags)
3907 cmd_flags = BNX2_NVM_COMMAND_LAST;
3908 else
3909 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3910 BNX2_NVM_COMMAND_LAST;
3911
3912 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3913
3914 memcpy(ret_buf, buf, 4 - extra);
3915 }
3916 else if (len32 > 0) {
3917 u8 buf[4];
3918
3919 /* Read the first word. */
3920 if (cmd_flags)
3921 cmd_flags = 0;
3922 else
3923 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3924
3925 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3926
3927 /* Advance to the next dword. */
3928 offset32 += 4;
3929 ret_buf += 4;
3930 len32 -= 4;
3931
3932 while (len32 > 4 && rc == 0) {
3933 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3934
3935 /* Advance to the next dword. */
3936 offset32 += 4;
3937 ret_buf += 4;
3938 len32 -= 4;
3939 }
3940
3941 if (rc)
3942 return rc;
3943
3944 cmd_flags = BNX2_NVM_COMMAND_LAST;
3945 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3946
3947 memcpy(ret_buf, buf, 4 - extra);
3948 }
3949
3950 /* Disable access to flash interface */
3951 bnx2_disable_nvram_access(bp);
3952
3953 bnx2_release_nvram_lock(bp);
3954
3955 return rc;
3956}
3957
3958static int
3959bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3960 int buf_size)
3961{
3962 u32 written, offset32, len32;
e6be763f 3963 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 3964 int rc = 0;
3965 int align_start, align_end;
3966
3967 buf = data_buf;
3968 offset32 = offset;
3969 len32 = buf_size;
3970 align_start = align_end = 0;
3971
3972 if ((align_start = (offset32 & 3))) {
3973 offset32 &= ~3;
c873879c
MC		 3974 len32 += align_start;
3975 if (len32 < 4)
3976 len32 = 4;
b6016b76
MC		 3977 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3978 return rc;
3979 }
3980
3981 if (len32 & 3) {
c873879c
MC		 3982 align_end = 4 - (len32 & 3);
3983 len32 += align_end;
3984 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3985 return rc;
b6016b76
MC		 3986 }
3987
3988 if (align_start || align_end) {
e6be763f
MC		 3989 align_buf = kmalloc(len32, GFP_KERNEL);
3990 if (align_buf == NULL)
b6016b76
MC		 3991 return -ENOMEM;
3992 if (align_start) {
e6be763f 3993 memcpy(align_buf, start, 4);
b6016b76
MC		 3994 }
3995 if (align_end) {
e6be763f 3996 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 3997 }
e6be763f
MC		 3998 memcpy(align_buf + align_start, data_buf, buf_size);
3999 buf = align_buf;
b6016b76
MC		 4000 }
4001
e30372c9 4002 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4003 flash_buffer = kmalloc(264, GFP_KERNEL);
4004 if (flash_buffer == NULL) {
4005 rc = -ENOMEM;
4006 goto nvram_write_end;
4007 }
4008 }
4009
b6016b76
MC		 4010 written = 0;
4011 while ((written < len32) && (rc == 0)) {
4012 u32 page_start, page_end, data_start, data_end;
4013 u32 addr, cmd_flags;
4014 int i;
b6016b76
MC		 4015
4016 /* Find the page_start addr */
4017 page_start = offset32 + written;
4018 page_start -= (page_start % bp->flash_info->page_size);
4019 /* Find the page_end addr */
4020 page_end = page_start + bp->flash_info->page_size;
4021 /* Find the data_start addr */
4022 data_start = (written == 0) ? offset32 : page_start;
4023 /* Find the data_end addr */
6aa20a22 4024 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4025 (offset32 + len32) : page_end;
4026
4027 /* Request access to the flash interface. */
4028 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4029 goto nvram_write_end;
4030
4031 /* Enable access to flash interface */
4032 bnx2_enable_nvram_access(bp);
4033
4034 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4035 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4036 int j;
4037
4038 /* Read the whole page into the buffer
4039 * (non-buffer flash only) */
4040 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4041 if (j == (bp->flash_info->page_size - 4)) {
4042 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4043 }
4044 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4045 page_start + j,
4046 &flash_buffer[j],
b6016b76
MC		 4047 cmd_flags);
4048
4049 if (rc)
4050 goto nvram_write_end;
4051
4052 cmd_flags = 0;
4053 }
4054 }
4055
4056 /* Enable writes to flash interface (unlock write-protect) */
4057 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4058 goto nvram_write_end;
4059
b6016b76
MC		 4060 /* Loop to write back the buffer data from page_start to
4061 * data_start */
4062 i = 0;
e30372c9 4063 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4064 /* Erase the page */
4065 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4066 goto nvram_write_end;
4067
4068 /* Re-enable the write again for the actual write */
4069 bnx2_enable_nvram_write(bp);
4070
b6016b76
MC		 4071 for (addr = page_start; addr < data_start;
4072 addr += 4, i += 4) {
6aa20a22 4073
b6016b76
MC		 4074 rc = bnx2_nvram_write_dword(bp, addr,
4075 &flash_buffer[i], cmd_flags);
4076
4077 if (rc != 0)
4078 goto nvram_write_end;
4079
4080 cmd_flags = 0;
4081 }
4082 }
4083
4084 /* Loop to write the new data from data_start to data_end */
bae25761 4085 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4086 if ((addr == page_end - 4) ||
e30372c9 4087 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4088 (addr == data_end - 4))) {
4089
4090 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4091 }
4092 rc = bnx2_nvram_write_dword(bp, addr, buf,
4093 cmd_flags);
4094
4095 if (rc != 0)
4096 goto nvram_write_end;
4097
4098 cmd_flags = 0;
4099 buf += 4;
4100 }
4101
4102 /* Loop to write back the buffer data from data_end
4103 * to page_end */
e30372c9 4104 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4105 for (addr = data_end; addr < page_end;
4106 addr += 4, i += 4) {
6aa20a22 4107
b6016b76
MC		 4108 if (addr == page_end-4) {
4109 cmd_flags = BNX2_NVM_COMMAND_LAST;
4110 }
4111 rc = bnx2_nvram_write_dword(bp, addr,
4112 &flash_buffer[i], cmd_flags);
4113
4114 if (rc != 0)
4115 goto nvram_write_end;
4116
4117 cmd_flags = 0;
4118 }
4119 }
4120
4121 /* Disable writes to flash interface (lock write-protect) */
4122 bnx2_disable_nvram_write(bp);
4123
4124 /* Disable access to flash interface */
4125 bnx2_disable_nvram_access(bp);
4126 bnx2_release_nvram_lock(bp);
4127
4128 /* Increment written */
4129 written += data_end - data_start;
4130 }
4131
4132nvram_write_end:
e6be763f
MC		 4133 kfree(flash_buffer);
4134 kfree(align_buf);
b6016b76
MC		 4135 return rc;
4136}
4137
0d8a6571
MC		 4138static void
4139bnx2_init_remote_phy(struct bnx2 *bp)
4140{
4141 u32 val;
4142
583c28e5
MC		 4143 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4144 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
0d8a6571
MC		 4145 return;
4146
4147 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
4148 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4149 return;
4150
4151 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
583c28e5 4152 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571
MC		 4153
4154 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
4155 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4156 bp->phy_port = PORT_FIBRE;
4157 else
4158 bp->phy_port = PORT_TP;
489310a4
MC		 4159
4160 if (netif_running(bp->dev)) {
4161 u32 sig;
4162
4163 if (val & BNX2_LINK_STATUS_LINK_UP) {
4164 bp->link_up = 1;
4165 netif_carrier_on(bp->dev);
4166 } else {
4167 bp->link_up = 0;
4168 netif_carrier_off(bp->dev);
4169 }
4170 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4171 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4172 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
4173 sig);
4174 }
0d8a6571
MC		 4175 }
4176}
4177
b4b36042
MC		 4178static void
4179bnx2_setup_msix_tbl(struct bnx2 *bp)
4180{
4181 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4182
4183 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4184 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4185}
4186
b6016b76
MC		 4187static int
4188bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4189{
4190 u32 val;
4191 int i, rc = 0;
489310a4 4192 u8 old_port;
b6016b76
MC		 4193
4194 /* Wait for the current PCI transaction to complete before
4195 * issuing a reset. */
4196 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4197 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4198 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4199 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4200 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4201 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4202 udelay(5);
4203
b090ae2b
MC		 4204 /* Wait for the firmware to tell us it is ok to issue a reset. */
4205 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4206
b6016b76
MC		 4207 /* Deposit a driver reset signature so the firmware knows that
4208 * this is a soft reset. */
e3648b3d 4209 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
b6016b76
MC		 4210 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4211
b6016b76
MC		 4212 /* Do a dummy read to force the chip to complete all current transaction
4213 * before we issue a reset. */
4214 val = REG_RD(bp, BNX2_MISC_ID);
4215
234754d5
MC		 4216 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4217 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4218 REG_RD(bp, BNX2_MISC_COMMAND);
4219 udelay(5);
b6016b76 4220
234754d5
MC		 4221 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4222 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4223
234754d5 4224 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4225
234754d5
MC		 4226 } else {
4227 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4228 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4229 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4230
4231 /* Chip reset. */
4232 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4233
594a9dfa
MC		 4234 /* Reading back any register after chip reset will hang the
4235 * bus on 5706 A0 and A1. The msleep below provides plenty
4236 * of margin for write posting.
4237 */
234754d5 4238 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4239 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4240 msleep(20);
b6016b76 4241
234754d5
MC		 4242 /* Reset takes approximate 30 usec */
4243 for (i = 0; i < 10; i++) {
4244 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4245 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4246 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4247 break;
4248 udelay(10);
4249 }
4250
4251 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4252 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4253 printk(KERN_ERR PFX "Chip reset did not complete\n");
4254 return -EBUSY;
4255 }
b6016b76
MC		 4256 }
4257
4258 /* Make sure byte swapping is properly configured. */
4259 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4260 if (val != 0x01020304) {
4261 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4262 return -ENODEV;
4263 }
4264
b6016b76 4265 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 4266 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4267 if (rc)
4268 return rc;
b6016b76 4269
0d8a6571 4270 spin_lock_bh(&bp->phy_lock);
489310a4 4271 old_port = bp->phy_port;
0d8a6571 4272 bnx2_init_remote_phy(bp);
583c28e5
MC		 4273 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4274 old_port != bp->phy_port)
0d8a6571
MC		 4275 bnx2_set_default_remote_link(bp);
4276 spin_unlock_bh(&bp->phy_lock);
4277
b6016b76
MC		 4278 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4279 /* Adjust the voltage regular to two steps lower. The default
4280 * of this register is 0x0000000e. */
4281 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4282
4283 /* Remove bad rbuf memory from the free pool. */
4284 rc = bnx2_alloc_bad_rbuf(bp);
4285 }
4286
f86e82fb 4287 if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 4288 bnx2_setup_msix_tbl(bp);
4289
b6016b76
MC		 4290 return rc;
4291}
4292
4293static int
4294bnx2_init_chip(struct bnx2 *bp)
4295{
4296 u32 val;
b4b36042 4297 int rc, i;
b6016b76
MC		 4298
4299 /* Make sure the interrupt is not active. */
4300 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4301
4302 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4303 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4304#ifdef __BIG_ENDIAN
6aa20a22 4305 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4306#endif
6aa20a22 4307 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4308 DMA_READ_CHANS << 12 |
4309 DMA_WRITE_CHANS << 16;
4310
4311 val |= (0x2 << 20) | (1 << 11);
4312
f86e82fb 4313 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4314 val |= (1 << 23);
4315
4316 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4317 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4318 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4319
4320 REG_WR(bp, BNX2_DMA_CONFIG, val);
4321
4322 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4323 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4324 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4325 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4326 }
4327
f86e82fb 4328 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4329 u16 val16;
4330
4331 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4332 &val16);
4333 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4334 val16 & ~PCI_X_CMD_ERO);
4335 }
4336
4337 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4338 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4339 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4340 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4341
4342 /* Initialize context mapping and zero out the quick contexts. The
4343 * context block must have already been enabled. */
641bdcd5
MC		 4344 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4345 rc = bnx2_init_5709_context(bp);
4346 if (rc)
4347 return rc;
4348 } else
59b47d8a 4349 bnx2_init_context(bp);
b6016b76 4350
fba9fe91
MC		 4351 if ((rc = bnx2_init_cpus(bp)) != 0)
4352 return rc;
4353
b6016b76
MC		 4354 bnx2_init_nvram(bp);
4355
4356 bnx2_set_mac_addr(bp);
4357
4358 val = REG_RD(bp, BNX2_MQ_CONFIG);
4359 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4360 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
68c9f75a
MC		 4361 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4362 val |= BNX2_MQ_CONFIG_HALT_DIS;
4363
b6016b76
MC		 4364 REG_WR(bp, BNX2_MQ_CONFIG, val);
4365
4366 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4367 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4368 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4369
4370 val = (BCM_PAGE_BITS - 8) << 24;
4371 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4372
4373 /* Configure page size. */
4374 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4375 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4376 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4377 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4378
4379 val = bp->mac_addr[0] +
4380 (bp->mac_addr[1] << 8) +
4381 (bp->mac_addr[2] << 16) +
4382 bp->mac_addr[3] +
4383 (bp->mac_addr[4] << 8) +
4384 (bp->mac_addr[5] << 16);
4385 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4386
4387 /* Program the MTU. Also include 4 bytes for CRC32. */
4388 val = bp->dev->mtu + ETH_HLEN + 4;
4389 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4390 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4391 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4392
b4b36042
MC		 4393 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4394 bp->bnx2_napi[i].last_status_idx = 0;
4395
b6016b76
MC		 4396 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4397
4398 /* Set up how to generate a link change interrupt. */
4399 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4400
4401 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4402 (u64) bp->status_blk_mapping & 0xffffffff);
4403 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4404
4405 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4406 (u64) bp->stats_blk_mapping & 0xffffffff);
4407 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4408 (u64) bp->stats_blk_mapping >> 32);
4409
6aa20a22 4410 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4411 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4412
4413 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4414 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4415
4416 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4417 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4418
4419 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4420
4421 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4422
4423 REG_WR(bp, BNX2_HC_COM_TICKS,
4424 (bp->com_ticks_int << 16) | bp->com_ticks);
4425
4426 REG_WR(bp, BNX2_HC_CMD_TICKS,
4427 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4428
02537b06
MC		 4429 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4430 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4431 else
7ea6920e 4432 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4433 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4434
4435 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4436 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4437 else {
8e6a72c4
MC		 4438 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4439 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4440 }
4441
f86e82fb 4442 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4443 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4444 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4445
4446 REG_WR(bp, BNX2_HC_SB_CONFIG_1,
4447 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4448 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4449
4450 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP_1,
4451 (bp->tx_quick_cons_trip_int << 16) |
4452 bp->tx_quick_cons_trip);
4453
4454 REG_WR(bp, BNX2_HC_TX_TICKS_1,
4455 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4456
4457 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4458 }
4459
f86e82fb 4460 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
8e6a72c4
MC		 4461 val |= BNX2_HC_CONFIG_ONE_SHOT;
4462
4463 REG_WR(bp, BNX2_HC_CONFIG, val);
4464
b6016b76
MC		 4465 /* Clear internal stats counters. */
4466 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4467
da3e4fbe 4468 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4469
4470 /* Initialize the receive filter. */
4471 bnx2_set_rx_mode(bp->dev);
4472
0aa38df7
MC		 4473 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4474 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4475 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4476 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4477 }
b090ae2b
MC		 4478 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4479 0);
b6016b76 4480
df149d70 4481 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4482 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4483
4484 udelay(20);
4485
bf5295bb
MC		 4486 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4487
b090ae2b 4488 return rc;
b6016b76
MC		 4489}
4490
c76c0475
MC		 4491static void
4492bnx2_clear_ring_states(struct bnx2 *bp)
4493{
4494 struct bnx2_napi *bnapi;
4495 int i;
4496
4497 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4498 bnapi = &bp->bnx2_napi[i];
4499
4500 bnapi->tx_cons = 0;
4501 bnapi->hw_tx_cons = 0;
4502 bnapi->rx_prod_bseq = 0;
4503 bnapi->rx_prod = 0;
4504 bnapi->rx_cons = 0;
4505 bnapi->rx_pg_prod = 0;
4506 bnapi->rx_pg_cons = 0;
4507 }
4508}
4509
59b47d8a
MC		 4510static void
4511bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4512{
4513 u32 val, offset0, offset1, offset2, offset3;
4514
4515 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4516 offset0 = BNX2_L2CTX_TYPE_XI;
4517 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4518 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4519 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4520 } else {
4521 offset0 = BNX2_L2CTX_TYPE;
4522 offset1 = BNX2_L2CTX_CMD_TYPE;
4523 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4524 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4525 }
4526 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4527 CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
4528
4529 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4530 CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
4531
4532 val = (u64) bp->tx_desc_mapping >> 32;
4533 CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
4534
4535 val = (u64) bp->tx_desc_mapping & 0xffffffff;
4536 CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
4537}
b6016b76
MC		 4538
4539static void
4540bnx2_init_tx_ring(struct bnx2 *bp)
4541{
4542 struct tx_bd *txbd;
c76c0475
MC		 4543 u32 cid = TX_CID;
4544 struct bnx2_napi *bnapi;
4545
4546 bp->tx_vec = 0;
f86e82fb 4547 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4548 cid = TX_TSS_CID;
4549 bp->tx_vec = BNX2_TX_VEC;
4550 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4551 (TX_TSS_CID << 7));
4552 }
4553 bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 4554
2f8af120
MC		 4555 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4556
b6016b76 4557 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 4558
b6016b76
MC		 4559 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4560 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4561
4562 bp->tx_prod = 0;
b6016b76 4563 bp->tx_prod_bseq = 0;
6aa20a22 4564
59b47d8a
MC		 4565 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4566 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 4567
59b47d8a 4568 bnx2_init_tx_context(bp, cid);
b6016b76
MC		 4569}
4570
4571static void
5d5d0015
MC		 4572bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4573 int num_rings)
b6016b76 4574{
b6016b76 4575 int i;
5d5d0015 4576 struct rx_bd *rxbd;
6aa20a22 4577
5d5d0015 4578 for (i = 0; i < num_rings; i++) {
13daffa2 4579 int j;
b6016b76 4580
5d5d0015 4581 rxbd = &rx_ring[i][0];
13daffa2 4582 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 4583 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 4584 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4585 }
5d5d0015 4586 if (i == (num_rings - 1))
13daffa2
MC		 4587 j = 0;
4588 else
4589 j = i + 1;
5d5d0015
MC		 4590 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4591 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 4592 }
5d5d0015
MC		 4593}
4594
4595static void
4596bnx2_init_rx_ring(struct bnx2 *bp)
4597{
4598 int i;
4599 u16 prod, ring_prod;
4600 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
b4b36042 4601 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
5d5d0015 4602
5d5d0015
MC		 4603 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4604 bp->rx_buf_use_size, bp->rx_max_ring);
4605
4606 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246
MC		 4607 if (bp->rx_pg_ring_size) {
4608 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4609 bp->rx_pg_desc_mapping,
4610 PAGE_SIZE, bp->rx_max_pg_ring);
4611 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4612 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4613 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4614 BNX2_L2CTX_RBDC_JUMBO_KEY);
4615
4616 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
4617 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4618
4619 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
4620 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4621
4622 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4623 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4624 }
b6016b76
MC		 4625
4626 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4627 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
4628 val |= 0x02 << 8;
5d5d0015 4629 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
b6016b76 4630
13daffa2 4631 val = (u64) bp->rx_desc_mapping[0] >> 32;
5d5d0015 4632 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 4633
13daffa2 4634 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
5d5d0015 4635 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 4636
a1f60190 4637 ring_prod = prod = bnapi->rx_pg_prod;
47bf4246
MC		 4638 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4639 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4640 break;
4641 prod = NEXT_RX_BD(prod);
4642 ring_prod = RX_PG_RING_IDX(prod);
4643 }
a1f60190 4644 bnapi->rx_pg_prod = prod;
47bf4246 4645
a1f60190 4646 ring_prod = prod = bnapi->rx_prod;
236b6394 4647 for (i = 0; i < bp->rx_ring_size; i++) {
a1f60190 4648 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
b6016b76
MC		 4649 break;
4650 }
4651 prod = NEXT_RX_BD(prod);
4652 ring_prod = RX_RING_IDX(prod);
4653 }
a1f60190 4654 bnapi->rx_prod = prod;
b6016b76 4655
a1f60190
MC		 4656 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4657 bnapi->rx_pg_prod);
b6016b76
MC		 4658 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4659
a1f60190 4660 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 4661}
4662
5d5d0015 4663static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 4664{
5d5d0015 4665 u32 max, num_rings = 1;
13daffa2 4666
5d5d0015
MC		 4667 while (ring_size > MAX_RX_DESC_CNT) {
4668 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 4669 num_rings++;
4670 }
4671 /* round to next power of 2 */
5d5d0015 4672 max = max_size;
13daffa2
MC		 4673 while ((max & num_rings) == 0)
4674 max >>= 1;
4675
4676 if (num_rings != max)
4677 max <<= 1;
4678
5d5d0015
MC		 4679 return max;
4680}
4681
4682static void
4683bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4684{
84eaa187 4685 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 4686
4687 /* 8 for CRC and VLAN */
4688 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4689
84eaa187
MC		 4690 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4691 sizeof(struct skb_shared_info);
4692
5d5d0015 4693 bp->rx_copy_thresh = RX_COPY_THRESH;
47bf4246
MC		 4694 bp->rx_pg_ring_size = 0;
4695 bp->rx_max_pg_ring = 0;
4696 bp->rx_max_pg_ring_idx = 0;
f86e82fb 4697 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 4698 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4699
4700 jumbo_size = size * pages;
4701 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4702 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4703
4704 bp->rx_pg_ring_size = jumbo_size;
4705 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4706 MAX_RX_PG_RINGS);
4707 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4708 rx_size = RX_COPY_THRESH + bp->rx_offset;
4709 bp->rx_copy_thresh = 0;
4710 }
5d5d0015
MC		 4711
4712 bp->rx_buf_use_size = rx_size;
4713 /* hw alignment */
4714 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
1db82f2a 4715 bp->rx_jumbo_thresh = rx_size - bp->rx_offset;
5d5d0015
MC		 4716 bp->rx_ring_size = size;
4717 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 4718 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4719}
4720
b6016b76
MC		 4721static void
4722bnx2_free_tx_skbs(struct bnx2 *bp)
4723{
4724 int i;
4725
4726 if (bp->tx_buf_ring == NULL)
4727 return;
4728
4729 for (i = 0; i < TX_DESC_CNT; ) {
4730 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4731 struct sk_buff *skb = tx_buf->skb;
4732 int j, last;
4733
4734 if (skb == NULL) {
4735 i++;
4736 continue;
4737 }
4738
4739 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4740 skb_headlen(skb), PCI_DMA_TODEVICE);
4741
4742 tx_buf->skb = NULL;
4743
4744 last = skb_shinfo(skb)->nr_frags;
4745 for (j = 0; j < last; j++) {
4746 tx_buf = &bp->tx_buf_ring[i + j + 1];
4747 pci_unmap_page(bp->pdev,
4748 pci_unmap_addr(tx_buf, mapping),
4749 skb_shinfo(skb)->frags[j].size,
4750 PCI_DMA_TODEVICE);
4751 }
745720e5 4752 dev_kfree_skb(skb);
b6016b76
MC		 4753 i += j + 1;
4754 }
4755
4756}
4757
4758static void
4759bnx2_free_rx_skbs(struct bnx2 *bp)
4760{
4761 int i;
4762
4763 if (bp->rx_buf_ring == NULL)
4764 return;
4765
13daffa2 4766 for (i = 0; i < bp->rx_max_ring_idx; i++) {
b6016b76
MC		 4767 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4768 struct sk_buff *skb = rx_buf->skb;
4769
05d0f1cf 4770 if (skb == NULL)
b6016b76
MC		 4771 continue;
4772
4773 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4774 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4775
4776 rx_buf->skb = NULL;
4777
745720e5 4778 dev_kfree_skb(skb);
b6016b76 4779 }
47bf4246
MC		 4780 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4781 bnx2_free_rx_page(bp, i);
b6016b76
MC		 4782}
4783
4784static void
4785bnx2_free_skbs(struct bnx2 *bp)
4786{
4787 bnx2_free_tx_skbs(bp);
4788 bnx2_free_rx_skbs(bp);
4789}
4790
4791static int
4792bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4793{
4794 int rc;
4795
4796 rc = bnx2_reset_chip(bp, reset_code);
4797 bnx2_free_skbs(bp);
4798 if (rc)
4799 return rc;
4800
fba9fe91
MC		 4801 if ((rc = bnx2_init_chip(bp)) != 0)
4802 return rc;
4803
c76c0475 4804 bnx2_clear_ring_states(bp);
b6016b76
MC		 4805 bnx2_init_tx_ring(bp);
4806 bnx2_init_rx_ring(bp);
4807 return 0;
4808}
4809
4810static int
4811bnx2_init_nic(struct bnx2 *bp)
4812{
4813 int rc;
4814
4815 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4816 return rc;
4817
80be4434 4818 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4819 bnx2_init_phy(bp);
4820 bnx2_set_link(bp);
0d8a6571 4821 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4822 return 0;
4823}
4824
4825static int
4826bnx2_test_registers(struct bnx2 *bp)
4827{
4828 int ret;
5bae30c9 4829 int i, is_5709;
f71e1309 4830 static const struct {
b6016b76
MC		 4831 u16 offset;
4832 u16 flags;
5bae30c9 4833#define BNX2_FL_NOT_5709 1
b6016b76
MC		 4834 u32 rw_mask;
4835 u32 ro_mask;
4836 } reg_tbl[] = {
4837 { 0x006c, 0, 0x00000000, 0x0000003f },
4838 { 0x0090, 0, 0xffffffff, 0x00000000 },
4839 { 0x0094, 0, 0x00000000, 0x00000000 },
4840
5bae30c9
MC		 4841 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4842 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4843 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4844 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4845 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4846 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4847 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4848 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4849 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4850
4851 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4852 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4853 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4854 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4855 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4856 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4857
4858 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4859 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4860 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 4861
4862 { 0x1000, 0, 0x00000000, 0x00000001 },
4863 { 0x1004, 0, 0x00000000, 0x000f0001 },
b6016b76
MC		 4864
4865 { 0x1408, 0, 0x01c00800, 0x00000000 },
4866 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4867 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 4868 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 4869 { 0x14b0, 0, 0x00000002, 0x00000001 },
4870 { 0x14b8, 0, 0x00000000, 0x00000000 },
4871 { 0x14c0, 0, 0x00000000, 0x00000009 },
4872 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4873 { 0x14cc, 0, 0x00000000, 0x00000001 },
4874 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 4875
4876 { 0x1800, 0, 0x00000000, 0x00000001 },
4877 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 4878
4879 { 0x2800, 0, 0x00000000, 0x00000001 },
4880 { 0x2804, 0, 0x00000000, 0x00003f01 },
4881 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4882 { 0x2810, 0, 0xffff0000, 0x00000000 },
4883 { 0x2814, 0, 0xffff0000, 0x00000000 },
4884 { 0x2818, 0, 0xffff0000, 0x00000000 },
4885 { 0x281c, 0, 0xffff0000, 0x00000000 },
4886 { 0x2834, 0, 0xffffffff, 0x00000000 },
4887 { 0x2840, 0, 0x00000000, 0xffffffff },
4888 { 0x2844, 0, 0x00000000, 0xffffffff },
4889 { 0x2848, 0, 0xffffffff, 0x00000000 },
4890 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4891
4892 { 0x2c00, 0, 0x00000000, 0x00000011 },
4893 { 0x2c04, 0, 0x00000000, 0x00030007 },
4894
b6016b76
MC		 4895 { 0x3c00, 0, 0x00000000, 0x00000001 },
4896 { 0x3c04, 0, 0x00000000, 0x00070000 },
4897 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4898 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4899 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4900 { 0x3c14, 0, 0x00000000, 0xffffffff },
4901 { 0x3c18, 0, 0x00000000, 0xffffffff },
4902 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4903 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 4904
4905 { 0x5004, 0, 0x00000000, 0x0000007f },
4906 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 4907
b6016b76
MC		 4908 { 0x5c00, 0, 0x00000000, 0x00000001 },
4909 { 0x5c04, 0, 0x00000000, 0x0003000f },
4910 { 0x5c08, 0, 0x00000003, 0x00000000 },
4911 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4912 { 0x5c10, 0, 0x00000000, 0xffffffff },
4913 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4914 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4915 { 0x5c88, 0, 0x00000000, 0x00077373 },
4916 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4917
4918 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4919 { 0x680c, 0, 0xffffffff, 0x00000000 },
4920 { 0x6810, 0, 0xffffffff, 0x00000000 },
4921 { 0x6814, 0, 0xffffffff, 0x00000000 },
4922 { 0x6818, 0, 0xffffffff, 0x00000000 },
4923 { 0x681c, 0, 0xffffffff, 0x00000000 },
4924 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4925 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4926 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4927 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4928 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4929 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4930 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4931 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4932 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4933 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4934 { 0x684c, 0, 0xffffffff, 0x00000000 },
4935 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4936 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4937 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4938 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4939 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4940 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4941
4942 { 0xffff, 0, 0x00000000, 0x00000000 },
4943 };
4944
4945 ret = 0;
5bae30c9
MC		 4946 is_5709 = 0;
4947 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4948 is_5709 = 1;
4949
b6016b76
MC		 4950 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4951 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 4952 u16 flags = reg_tbl[i].flags;
4953
4954 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4955 continue;
b6016b76
MC		 4956
4957 offset = (u32) reg_tbl[i].offset;
4958 rw_mask = reg_tbl[i].rw_mask;
4959 ro_mask = reg_tbl[i].ro_mask;
4960
14ab9b86 4961 save_val = readl(bp->regview + offset);
b6016b76 4962
14ab9b86 4963 writel(0, bp->regview + offset);
b6016b76 4964
14ab9b86 4965 val = readl(bp->regview + offset);
b6016b76
MC		 4966 if ((val & rw_mask) != 0) {
4967 goto reg_test_err;
4968 }
4969
4970 if ((val & ro_mask) != (save_val & ro_mask)) {
4971 goto reg_test_err;
4972 }
4973
14ab9b86 4974 writel(0xffffffff, bp->regview + offset);
b6016b76 4975
14ab9b86 4976 val = readl(bp->regview + offset);
b6016b76
MC		 4977 if ((val & rw_mask) != rw_mask) {
4978 goto reg_test_err;
4979 }
4980
4981 if ((val & ro_mask) != (save_val & ro_mask)) {
4982 goto reg_test_err;
4983 }
4984
14ab9b86 4985 writel(save_val, bp->regview + offset);
b6016b76
MC		 4986 continue;
4987
4988reg_test_err:
14ab9b86 4989 writel(save_val, bp->regview + offset);
b6016b76
MC		 4990 ret = -ENODEV;
4991 break;
4992 }
4993 return ret;
4994}
4995
4996static int
4997bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
4998{
f71e1309 4999 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5000 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5001 int i;
5002
5003 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5004 u32 offset;
5005
5006 for (offset = 0; offset < size; offset += 4) {
5007
5008 REG_WR_IND(bp, start + offset, test_pattern[i]);
5009
5010 if (REG_RD_IND(bp, start + offset) !=
5011 test_pattern[i]) {
5012 return -ENODEV;
5013 }
5014 }
5015 }
5016 return 0;
5017}
5018
5019static int
5020bnx2_test_memory(struct bnx2 *bp)
5021{
5022 int ret = 0;
5023 int i;
5bae30c9 5024 static struct mem_entry {
b6016b76
MC		 5025 u32 offset;
5026 u32 len;
5bae30c9 5027 } mem_tbl_5706[] = {
b6016b76 5028 { 0x60000, 0x4000 },
5b0c76ad 5029 { 0xa0000, 0x3000 },
b6016b76
MC		 5030 { 0xe0000, 0x4000 },
5031 { 0x120000, 0x4000 },
5032 { 0x1a0000, 0x4000 },
5033 { 0x160000, 0x4000 },
5034 { 0xffffffff, 0 },
5bae30c9
MC		 5035 },
5036 mem_tbl_5709[] = {
5037 { 0x60000, 0x4000 },
5038 { 0xa0000, 0x3000 },
5039 { 0xe0000, 0x4000 },
5040 { 0x120000, 0x4000 },
5041 { 0x1a0000, 0x4000 },
5042 { 0xffffffff, 0 },
b6016b76 5043 };
5bae30c9
MC		 5044 struct mem_entry *mem_tbl;
5045
5046 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5047 mem_tbl = mem_tbl_5709;
5048 else
5049 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5050
5051 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5052 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5053 mem_tbl[i].len)) != 0) {
5054 return ret;
5055 }
5056 }
6aa20a22 5057
b6016b76
MC		 5058 return ret;
5059}
5060
bc5a0690
MC		 5061#define BNX2_MAC_LOOPBACK 0
5062#define BNX2_PHY_LOOPBACK 1
5063
b6016b76 5064static int
bc5a0690 5065bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5066{
5067 unsigned int pkt_size, num_pkts, i;
5068 struct sk_buff *skb, *rx_skb;
5069 unsigned char *packet;
bc5a0690 5070 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5071 dma_addr_t map;
5072 struct tx_bd *txbd;
5073 struct sw_bd *rx_buf;
5074 struct l2_fhdr *rx_hdr;
5075 int ret = -ENODEV;
c76c0475
MC		 5076 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5077
5078 tx_napi = bnapi;
f86e82fb 5079 if (bp->flags & BNX2_FLAG_USING_MSIX)
c76c0475 5080 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
b6016b76 5081
bc5a0690
MC		 5082 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5083 bp->loopback = MAC_LOOPBACK;
5084 bnx2_set_mac_loopback(bp);
5085 }
5086 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5087 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5088 return 0;
5089
80be4434 5090 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5091 bnx2_set_phy_loopback(bp);
5092 }
5093 else
5094 return -EINVAL;
b6016b76 5095
84eaa187 5096 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5097 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5098 if (!skb)
5099 return -ENOMEM;
b6016b76 5100 packet = skb_put(skb, pkt_size);
6634292b 5101 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5102 memset(packet + 6, 0x0, 8);
5103 for (i = 14; i < pkt_size; i++)
5104 packet[i] = (unsigned char) (i & 0xff);
5105
5106 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5107 PCI_DMA_TODEVICE);
5108
bf5295bb
MC		 5109 REG_WR(bp, BNX2_HC_COMMAND,
5110 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5111
b6016b76
MC		 5112 REG_RD(bp, BNX2_HC_COMMAND);
5113
5114 udelay(5);
35efa7c1 5115 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5116
b6016b76
MC		 5117 num_pkts = 0;
5118
bc5a0690 5119 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
b6016b76
MC		 5120
5121 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5122 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5123 txbd->tx_bd_mss_nbytes = pkt_size;
5124 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5125
5126 num_pkts++;
bc5a0690
MC		 5127 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5128 bp->tx_prod_bseq += pkt_size;
b6016b76 5129
234754d5
MC		 5130 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5131 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5132
5133 udelay(100);
5134
bf5295bb
MC		 5135 REG_WR(bp, BNX2_HC_COMMAND,
5136 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5137
b6016b76
MC		 5138 REG_RD(bp, BNX2_HC_COMMAND);
5139
5140 udelay(5);
5141
5142 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5143 dev_kfree_skb(skb);
b6016b76 5144
c76c0475 5145 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
b6016b76 5146 goto loopback_test_done;
b6016b76 5147
35efa7c1 5148 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5149 if (rx_idx != rx_start_idx + num_pkts) {
5150 goto loopback_test_done;
5151 }
5152
5153 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5154 rx_skb = rx_buf->skb;
5155
5156 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5157 skb_reserve(rx_skb, bp->rx_offset);
5158
5159 pci_dma_sync_single_for_cpu(bp->pdev,
5160 pci_unmap_addr(rx_buf, mapping),
5161 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5162
ade2bfe7 5163 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5164 (L2_FHDR_ERRORS_BAD_CRC |
5165 L2_FHDR_ERRORS_PHY_DECODE |
5166 L2_FHDR_ERRORS_ALIGNMENT |
5167 L2_FHDR_ERRORS_TOO_SHORT |
5168 L2_FHDR_ERRORS_GIANT_FRAME)) {
5169
5170 goto loopback_test_done;
5171 }
5172
5173 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5174 goto loopback_test_done;
5175 }
5176
5177 for (i = 14; i < pkt_size; i++) {
5178 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5179 goto loopback_test_done;
5180 }
5181 }
5182
5183 ret = 0;
5184
5185loopback_test_done:
5186 bp->loopback = 0;
5187 return ret;
5188}
5189
bc5a0690
MC		 5190#define BNX2_MAC_LOOPBACK_FAILED 1
5191#define BNX2_PHY_LOOPBACK_FAILED 2
5192#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5193 BNX2_PHY_LOOPBACK_FAILED)
5194
5195static int
5196bnx2_test_loopback(struct bnx2 *bp)
5197{
5198 int rc = 0;
5199
5200 if (!netif_running(bp->dev))
5201 return BNX2_LOOPBACK_FAILED;
5202
5203 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5204 spin_lock_bh(&bp->phy_lock);
5205 bnx2_init_phy(bp);
5206 spin_unlock_bh(&bp->phy_lock);
5207 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5208 rc |= BNX2_MAC_LOOPBACK_FAILED;
5209 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5210 rc |= BNX2_PHY_LOOPBACK_FAILED;
5211 return rc;
5212}
5213
b6016b76
MC		 5214#define NVRAM_SIZE 0x200
5215#define CRC32_RESIDUAL 0xdebb20e3
5216
5217static int
5218bnx2_test_nvram(struct bnx2 *bp)
5219{
5220 u32 buf[NVRAM_SIZE / 4];
5221 u8 *data = (u8 *) buf;
5222 int rc = 0;
5223 u32 magic, csum;
5224
5225 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5226 goto test_nvram_done;
5227
5228 magic = be32_to_cpu(buf[0]);
5229 if (magic != 0x669955aa) {
5230 rc = -ENODEV;
5231 goto test_nvram_done;
5232 }
5233
5234 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5235 goto test_nvram_done;
5236
5237 csum = ether_crc_le(0x100, data);
5238 if (csum != CRC32_RESIDUAL) {
5239 rc = -ENODEV;
5240 goto test_nvram_done;
5241 }
5242
5243 csum = ether_crc_le(0x100, data + 0x100);
5244 if (csum != CRC32_RESIDUAL) {
5245 rc = -ENODEV;
5246 }
5247
5248test_nvram_done:
5249 return rc;
5250}
5251
5252static int
5253bnx2_test_link(struct bnx2 *bp)
5254{
5255 u32 bmsr;
5256
583c28e5 5257 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5258 if (bp->link_up)
5259 return 0;
5260 return -ENODEV;
5261 }
c770a65c 5262 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5263 bnx2_enable_bmsr1(bp);
5264 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5265 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5266 bnx2_disable_bmsr1(bp);
c770a65c 5267 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5268
b6016b76
MC		 5269 if (bmsr & BMSR_LSTATUS) {
5270 return 0;
5271 }
5272 return -ENODEV;
5273}
5274
5275static int
5276bnx2_test_intr(struct bnx2 *bp)
5277{
5278 int i;
b6016b76
MC		 5279 u16 status_idx;
5280
5281 if (!netif_running(bp->dev))
5282 return -ENODEV;
5283
5284 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5285
5286 /* This register is not touched during run-time. */
bf5295bb 5287 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5288 REG_RD(bp, BNX2_HC_COMMAND);
5289
5290 for (i = 0; i < 10; i++) {
5291 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5292 status_idx) {
5293
5294 break;
5295 }
5296
5297 msleep_interruptible(10);
5298 }
5299 if (i < 10)
5300 return 0;
5301
5302 return -ENODEV;
5303}
5304
b2fadeae
MC		 5305static int
5306bnx2_5706_serdes_has_link(struct bnx2 *bp)
5307{
5308 u32 mode_ctl, an_dbg, exp;
5309
5310 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5311 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5312
5313 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5314 return 0;
5315
5316 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5317 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5318 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5319
5320 if (an_dbg & MISC_SHDW_AN_DBG_NOSYNC)
5321 return 0;
5322
5323 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5324 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5325 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5326
5327 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5328 return 0;
5329
5330 return 1;
5331}
5332
b6016b76 5333static void
48b01e2d 5334bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5335{
b2fadeae
MC		 5336 int check_link = 1;
5337
48b01e2d 5338 spin_lock(&bp->phy_lock);
583c28e5 5339 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 5340 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 5341 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae
MC		 5342 spin_unlock(&bp->phy_lock);
5343 return;
5344 }
5345
5346 if (bp->serdes_an_pending) {
48b01e2d 5347 bp->serdes_an_pending--;
b2fadeae
MC		 5348 check_link = 0;
5349 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5350 u32 bmcr;
b6016b76 5351
48b01e2d 5352 bp->current_interval = bp->timer_interval;
cd339a0e 5353
ca58c3af 5354 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5355
48b01e2d 5356 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5357 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5358 bmcr &= ~BMCR_ANENABLE;
5359 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5360 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5361 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5362 }
b6016b76 5363 }
48b01e2d
MC		 5364 }
5365 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5366 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5367 u32 phy2;
b6016b76 5368
b2fadeae 5369 check_link = 0;
48b01e2d
MC		 5370 bnx2_write_phy(bp, 0x17, 0x0f01);
5371 bnx2_read_phy(bp, 0x15, &phy2);
5372 if (phy2 & 0x20) {
5373 u32 bmcr;
cd339a0e 5374
ca58c3af 5375 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5376 bmcr |= BMCR_ANENABLE;
ca58c3af 5377 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5378
583c28e5 5379 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5380 }
5381 } else
5382 bp->current_interval = bp->timer_interval;
b6016b76 5383
b2fadeae
MC		 5384 if (bp->link_up && (bp->autoneg & AUTONEG_SPEED) && check_link) {
5385 u32 val;
5386
5387 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5388 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5389 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5390
5391 if (val & MISC_SHDW_AN_DBG_NOSYNC) {
5392 bnx2_5706s_force_link_dn(bp, 1);
583c28e5 5393 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae
MC		 5394 }
5395 }
48b01e2d
MC		 5396 spin_unlock(&bp->phy_lock);
5397}
b6016b76 5398
f8dd064e
MC		 5399static void
5400bnx2_5708_serdes_timer(struct bnx2 *bp)
5401{
583c28e5 5402 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 5403 return;
5404
583c28e5 5405 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 5406 bp->serdes_an_pending = 0;
5407 return;
5408 }
b6016b76 5409
f8dd064e
MC		 5410 spin_lock(&bp->phy_lock);
5411 if (bp->serdes_an_pending)
5412 bp->serdes_an_pending--;
5413 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5414 u32 bmcr;
b6016b76 5415
ca58c3af 5416 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 5417 if (bmcr & BMCR_ANENABLE) {
605a9e20 5418 bnx2_enable_forced_2g5(bp);
f8dd064e
MC		 5419 bp->current_interval = SERDES_FORCED_TIMEOUT;
5420 } else {
605a9e20 5421 bnx2_disable_forced_2g5(bp);
f8dd064e
MC		 5422 bp->serdes_an_pending = 2;
5423 bp->current_interval = bp->timer_interval;
b6016b76 5424 }
b6016b76 5425
f8dd064e
MC		 5426 } else
5427 bp->current_interval = bp->timer_interval;
b6016b76 5428
f8dd064e
MC		 5429 spin_unlock(&bp->phy_lock);
5430}
5431
48b01e2d
MC		 5432static void
5433bnx2_timer(unsigned long data)
5434{
5435 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 5436
48b01e2d
MC		 5437 if (!netif_running(bp->dev))
5438 return;
b6016b76 5439
48b01e2d
MC		 5440 if (atomic_read(&bp->intr_sem) != 0)
5441 goto bnx2_restart_timer;
b6016b76 5442
df149d70 5443 bnx2_send_heart_beat(bp);
b6016b76 5444
48b01e2d 5445 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 5446
02537b06
MC		 5447 /* workaround occasional corrupted counters */
5448 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5449 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5450 BNX2_HC_COMMAND_STATS_NOW);
5451
583c28e5 5452 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 5453 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5454 bnx2_5706_serdes_timer(bp);
27a005b8 5455 else
f8dd064e 5456 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 5457 }
5458
5459bnx2_restart_timer:
cd339a0e 5460 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5461}
5462
8e6a72c4
MC		 5463static int
5464bnx2_request_irq(struct bnx2 *bp)
5465{
5466 struct net_device *dev = bp->dev;
6d866ffc 5467 unsigned long flags;
b4b36042
MC		 5468 struct bnx2_irq *irq;
5469 int rc = 0, i;
8e6a72c4 5470
f86e82fb 5471 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 5472 flags = 0;
5473 else
5474 flags = IRQF_SHARED;
b4b36042
MC		 5475
5476 for (i = 0; i < bp->irq_nvecs; i++) {
5477 irq = &bp->irq_tbl[i];
c76c0475 5478 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
b4b36042
MC		 5479 dev);
5480 if (rc)
5481 break;
5482 irq->requested = 1;
5483 }
8e6a72c4
MC		 5484 return rc;
5485}
5486
5487static void
5488bnx2_free_irq(struct bnx2 *bp)
5489{
5490 struct net_device *dev = bp->dev;
b4b36042
MC		 5491 struct bnx2_irq *irq;
5492 int i;
8e6a72c4 5493
b4b36042
MC		 5494 for (i = 0; i < bp->irq_nvecs; i++) {
5495 irq = &bp->irq_tbl[i];
5496 if (irq->requested)
5497 free_irq(irq->vector, dev);
5498 irq->requested = 0;
6d866ffc 5499 }
f86e82fb 5500 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 5501 pci_disable_msi(bp->pdev);
f86e82fb 5502 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 5503 pci_disable_msix(bp->pdev);
5504
f86e82fb 5505 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 5506}
5507
5508static void
5509bnx2_enable_msix(struct bnx2 *bp)
5510{
57851d84
MC		 5511 int i, rc;
5512 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5513
b4b36042
MC		 5514 bnx2_setup_msix_tbl(bp);
5515 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5516 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5517 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84
MC		 5518
5519 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5520 msix_ent[i].entry = i;
5521 msix_ent[i].vector = 0;
5522 }
5523
5524 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5525 if (rc != 0)
5526 return;
5527
5528 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5529 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5530
5531 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5532 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5533 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5534 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5535
5536 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
f86e82fb 5537 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
57851d84
MC		 5538 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5539 bp->irq_tbl[i].vector = msix_ent[i].vector;
6d866ffc
MC		 5540}
5541
5542static void
5543bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5544{
5545 bp->irq_tbl[0].handler = bnx2_interrupt;
5546 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 5547 bp->irq_nvecs = 1;
5548 bp->irq_tbl[0].vector = bp->pdev->irq;
5549
f86e82fb 5550 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
b4b36042 5551 bnx2_enable_msix(bp);
6d866ffc 5552
f86e82fb
DM		 5553 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5554 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 5555 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 5556 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 5557 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 5558 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 5559 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5560 } else
5561 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 5562
5563 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 5564 }
5565 }
8e6a72c4
MC		 5566}
5567
b6016b76
MC		 5568/* Called with rtnl_lock */
5569static int
5570bnx2_open(struct net_device *dev)
5571{
972ec0d4 5572 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5573 int rc;
5574
1b2f922f
MC		 5575 netif_carrier_off(dev);
5576
829ca9a3 5577 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5578 bnx2_disable_int(bp);
5579
5580 rc = bnx2_alloc_mem(bp);
5581 if (rc)
5582 return rc;
5583
6d866ffc 5584 bnx2_setup_int_mode(bp, disable_msi);
35efa7c1 5585 bnx2_napi_enable(bp);
8e6a72c4
MC		 5586 rc = bnx2_request_irq(bp);
5587
b6016b76 5588 if (rc) {
35efa7c1 5589 bnx2_napi_disable(bp);
b6016b76
MC		 5590 bnx2_free_mem(bp);
5591 return rc;
5592 }
5593
5594 rc = bnx2_init_nic(bp);
5595
5596 if (rc) {
35efa7c1 5597 bnx2_napi_disable(bp);
8e6a72c4 5598 bnx2_free_irq(bp);
b6016b76
MC		 5599 bnx2_free_skbs(bp);
5600 bnx2_free_mem(bp);
5601 return rc;
5602 }
6aa20a22 5603
cd339a0e 5604 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5605
5606 atomic_set(&bp->intr_sem, 0);
5607
5608 bnx2_enable_int(bp);
5609
f86e82fb 5610 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 5611 /* Test MSI to make sure it is working
5612 * If MSI test fails, go back to INTx mode
5613 */
5614 if (bnx2_test_intr(bp) != 0) {
5615 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5616 " using MSI, switching to INTx mode. Please"
5617 " report this failure to the PCI maintainer"
5618 " and include system chipset information.\n",
5619 bp->dev->name);
5620
5621 bnx2_disable_int(bp);
8e6a72c4 5622 bnx2_free_irq(bp);
b6016b76 5623
6d866ffc
MC		 5624 bnx2_setup_int_mode(bp, 1);
5625
b6016b76
MC		 5626 rc = bnx2_init_nic(bp);
5627
8e6a72c4
MC		 5628 if (!rc)
5629 rc = bnx2_request_irq(bp);
5630
b6016b76 5631 if (rc) {
35efa7c1 5632 bnx2_napi_disable(bp);
b6016b76
MC		 5633 bnx2_free_skbs(bp);
5634 bnx2_free_mem(bp);
5635 del_timer_sync(&bp->timer);
5636 return rc;
5637 }
5638 bnx2_enable_int(bp);
5639 }
5640 }
f86e82fb 5641 if (bp->flags & BNX2_FLAG_USING_MSI)
b6016b76 5642 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
f86e82fb 5643 else if (bp->flags & BNX2_FLAG_USING_MSIX)
57851d84 5644 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
b6016b76
MC		 5645
5646 netif_start_queue(dev);
5647
5648 return 0;
5649}
5650
5651static void
c4028958 5652bnx2_reset_task(struct work_struct *work)
b6016b76 5653{
c4028958 5654 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 5655
afdc08b9
MC		 5656 if (!netif_running(bp->dev))
5657 return;
5658
5659 bp->in_reset_task = 1;
b6016b76
MC		 5660 bnx2_netif_stop(bp);
5661
5662 bnx2_init_nic(bp);
5663
5664 atomic_set(&bp->intr_sem, 1);
5665 bnx2_netif_start(bp);
afdc08b9 5666 bp->in_reset_task = 0;
b6016b76
MC		 5667}
5668
5669static void
5670bnx2_tx_timeout(struct net_device *dev)
5671{
972ec0d4 5672 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5673
5674 /* This allows the netif to be shutdown gracefully before resetting */
5675 schedule_work(&bp->reset_task);
5676}
5677
5678#ifdef BCM_VLAN
5679/* Called with rtnl_lock */
5680static void
5681bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5682{
972ec0d4 5683 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5684
5685 bnx2_netif_stop(bp);
5686
5687 bp->vlgrp = vlgrp;
5688 bnx2_set_rx_mode(dev);
5689
5690 bnx2_netif_start(bp);
5691}
b6016b76
MC		 5692#endif
5693
932ff279 5694/* Called with netif_tx_lock.
2f8af120
MC		 5695 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5696 * netif_wake_queue().
b6016b76
MC		 5697 */
5698static int
5699bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5700{
972ec0d4 5701 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5702 dma_addr_t mapping;
5703 struct tx_bd *txbd;
5704 struct sw_bd *tx_buf;
5705 u32 len, vlan_tag_flags, last_frag, mss;
5706 u16 prod, ring_prod;
5707 int i;
57851d84 5708 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 5709
a550c99b
MC		 5710 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5711 (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 5712 netif_stop_queue(dev);
5713 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5714 dev->name);
5715
5716 return NETDEV_TX_BUSY;
5717 }
5718 len = skb_headlen(skb);
5719 prod = bp->tx_prod;
5720 ring_prod = TX_RING_IDX(prod);
5721
5722 vlan_tag_flags = 0;
84fa7933 5723 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 5724 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5725 }
5726
79ea13ce 5727 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 5728 vlan_tag_flags |=
5729 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5730 }
fde82055 5731 if ((mss = skb_shinfo(skb)->gso_size)) {
b6016b76 5732 u32 tcp_opt_len, ip_tcp_len;
eddc9ec5 5733 struct iphdr *iph;
b6016b76 5734
b6016b76
MC		 5735 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5736
4666f87a
MC		 5737 tcp_opt_len = tcp_optlen(skb);
5738
5739 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5740 u32 tcp_off = skb_transport_offset(skb) -
5741 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 5742
4666f87a
MC		 5743 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5744 TX_BD_FLAGS_SW_FLAGS;
5745 if (likely(tcp_off == 0))
5746 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5747 else {
5748 tcp_off >>= 3;
5749 vlan_tag_flags |= ((tcp_off & 0x3) <<
5750 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5751 ((tcp_off & 0x10) <<
5752 TX_BD_FLAGS_TCP6_OFF4_SHL);
5753 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5754 }
5755 } else {
5756 if (skb_header_cloned(skb) &&
5757 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5758 dev_kfree_skb(skb);
5759 return NETDEV_TX_OK;
5760 }
b6016b76 5761
4666f87a
MC		 5762 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5763
5764 iph = ip_hdr(skb);
5765 iph->check = 0;
5766 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5767 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5768 iph->daddr, 0,
5769 IPPROTO_TCP,
5770 0);
5771 if (tcp_opt_len || (iph->ihl > 5)) {
5772 vlan_tag_flags |= ((iph->ihl - 5) +
5773 (tcp_opt_len >> 2)) << 8;
5774 }
b6016b76 5775 }
4666f87a 5776 } else
b6016b76 5777 mss = 0;
b6016b76
MC		 5778
5779 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6aa20a22 5780
b6016b76
MC		 5781 tx_buf = &bp->tx_buf_ring[ring_prod];
5782 tx_buf->skb = skb;
5783 pci_unmap_addr_set(tx_buf, mapping, mapping);
5784
5785 txbd = &bp->tx_desc_ring[ring_prod];
5786
5787 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5788 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5789 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5790 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5791
5792 last_frag = skb_shinfo(skb)->nr_frags;
5793
5794 for (i = 0; i < last_frag; i++) {
5795 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5796
5797 prod = NEXT_TX_BD(prod);
5798 ring_prod = TX_RING_IDX(prod);
5799 txbd = &bp->tx_desc_ring[ring_prod];
5800
5801 len = frag->size;
5802 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5803 len, PCI_DMA_TODEVICE);
5804 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5805 mapping, mapping);
5806
5807 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5808 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5809 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5810 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5811
5812 }
5813 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5814
5815 prod = NEXT_TX_BD(prod);
5816 bp->tx_prod_bseq += skb->len;
5817
234754d5
MC		 5818 REG_WR16(bp, bp->tx_bidx_addr, prod);
5819 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5820
5821 mmiowb();
5822
5823 bp->tx_prod = prod;
5824 dev->trans_start = jiffies;
5825
a550c99b 5826 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
e89bbf10 5827 netif_stop_queue(dev);
a550c99b 5828 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
e89bbf10 5829 netif_wake_queue(dev);
b6016b76
MC		 5830 }
5831
5832 return NETDEV_TX_OK;
5833}
5834
5835/* Called with rtnl_lock */
5836static int
5837bnx2_close(struct net_device *dev)
5838{
972ec0d4 5839 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5840 u32 reset_code;
5841
afdc08b9
MC		 5842 /* Calling flush_scheduled_work() may deadlock because
5843 * linkwatch_event() may be on the workqueue and it will try to get
5844 * the rtnl_lock which we are holding.
5845 */
5846 while (bp->in_reset_task)
5847 msleep(1);
5848
bea3348e 5849 bnx2_disable_int_sync(bp);
35efa7c1 5850 bnx2_napi_disable(bp);
b6016b76 5851 del_timer_sync(&bp->timer);
f86e82fb 5852 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 5853 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 5854 else if (bp->wol)
b6016b76
MC		 5855 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5856 else
5857 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5858 bnx2_reset_chip(bp, reset_code);
8e6a72c4 5859 bnx2_free_irq(bp);
b6016b76
MC		 5860 bnx2_free_skbs(bp);
5861 bnx2_free_mem(bp);
5862 bp->link_up = 0;
5863 netif_carrier_off(bp->dev);
829ca9a3 5864 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 5865 return 0;
5866}
5867
5868#define GET_NET_STATS64(ctr) \
5869 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5870 (unsigned long) (ctr##_lo)
5871
5872#define GET_NET_STATS32(ctr) \
5873 (ctr##_lo)
5874
5875#if (BITS_PER_LONG == 64)
5876#define GET_NET_STATS GET_NET_STATS64
5877#else
5878#define GET_NET_STATS GET_NET_STATS32
5879#endif
5880
5881static struct net_device_stats *
5882bnx2_get_stats(struct net_device *dev)
5883{
972ec0d4 5884 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5885 struct statistics_block *stats_blk = bp->stats_blk;
5886 struct net_device_stats *net_stats = &bp->net_stats;
5887
5888 if (bp->stats_blk == NULL) {
5889 return net_stats;
5890 }
5891 net_stats->rx_packets =
5892 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5893 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5894 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5895
5896 net_stats->tx_packets =
5897 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5898 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5899 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5900
5901 net_stats->rx_bytes =
5902 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5903
5904 net_stats->tx_bytes =
5905 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5906
6aa20a22 5907 net_stats->multicast =
b6016b76
MC		 5908 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5909
6aa20a22 5910 net_stats->collisions =
b6016b76
MC		 5911 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5912
6aa20a22 5913 net_stats->rx_length_errors =
b6016b76
MC		 5914 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5915 stats_blk->stat_EtherStatsOverrsizePkts);
5916
6aa20a22 5917 net_stats->rx_over_errors =
b6016b76
MC		 5918 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5919
6aa20a22 5920 net_stats->rx_frame_errors =
b6016b76
MC		 5921 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5922
6aa20a22 5923 net_stats->rx_crc_errors =
b6016b76
MC		 5924 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5925
5926 net_stats->rx_errors = net_stats->rx_length_errors +
5927 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5928 net_stats->rx_crc_errors;
5929
5930 net_stats->tx_aborted_errors =
5931 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5932 stats_blk->stat_Dot3StatsLateCollisions);
5933
5b0c76ad
MC		 5934 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5935 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 5936 net_stats->tx_carrier_errors = 0;
5937 else {
5938 net_stats->tx_carrier_errors =
5939 (unsigned long)
5940 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5941 }
5942
5943 net_stats->tx_errors =
6aa20a22 5944 (unsigned long)
b6016b76
MC		 5945 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5946 +
5947 net_stats->tx_aborted_errors +
5948 net_stats->tx_carrier_errors;
5949
cea94db9
MC		 5950 net_stats->rx_missed_errors =
5951 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5952 stats_blk->stat_FwRxDrop);
5953
b6016b76
MC		 5954 return net_stats;
5955}
5956
5957/* All ethtool functions called with rtnl_lock */
5958
5959static int
5960bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5961{
972ec0d4 5962 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 5963 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 5964
5965 cmd->supported = SUPPORTED_Autoneg;
583c28e5 5966 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 5967 support_serdes = 1;
5968 support_copper = 1;
5969 } else if (bp->phy_port == PORT_FIBRE)
5970 support_serdes = 1;
5971 else
5972 support_copper = 1;
5973
5974 if (support_serdes) {
b6016b76
MC		 5975 cmd->supported |= SUPPORTED_1000baseT_Full |
5976 SUPPORTED_FIBRE;
583c28e5 5977 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 5978 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 5979
b6016b76 5980 }
7b6b8347 5981 if (support_copper) {
b6016b76
MC		 5982 cmd->supported |= SUPPORTED_10baseT_Half |
5983 SUPPORTED_10baseT_Full |
5984 SUPPORTED_100baseT_Half |
5985 SUPPORTED_100baseT_Full |
5986 SUPPORTED_1000baseT_Full |
5987 SUPPORTED_TP;
5988
b6016b76
MC		 5989 }
5990
7b6b8347
MC		 5991 spin_lock_bh(&bp->phy_lock);
5992 cmd->port = bp->phy_port;
b6016b76
MC		 5993 cmd->advertising = bp->advertising;
5994
5995 if (bp->autoneg & AUTONEG_SPEED) {
5996 cmd->autoneg = AUTONEG_ENABLE;
5997 }
5998 else {
5999 cmd->autoneg = AUTONEG_DISABLE;
6000 }
6001
6002 if (netif_carrier_ok(dev)) {
6003 cmd->speed = bp->line_speed;
6004 cmd->duplex = bp->duplex;
6005 }
6006 else {
6007 cmd->speed = -1;
6008 cmd->duplex = -1;
6009 }
7b6b8347 6010 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6011
6012 cmd->transceiver = XCVR_INTERNAL;
6013 cmd->phy_address = bp->phy_addr;
6014
6015 return 0;
6016}
6aa20a22 6017
b6016b76
MC		 6018static int
6019bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6020{
972ec0d4 6021 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6022 u8 autoneg = bp->autoneg;
6023 u8 req_duplex = bp->req_duplex;
6024 u16 req_line_speed = bp->req_line_speed;
6025 u32 advertising = bp->advertising;
7b6b8347
MC		 6026 int err = -EINVAL;
6027
6028 spin_lock_bh(&bp->phy_lock);
6029
6030 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6031 goto err_out_unlock;
6032
583c28e5
MC		 6033 if (cmd->port != bp->phy_port &&
6034 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6035 goto err_out_unlock;
b6016b76
MC		 6036
6037 if (cmd->autoneg == AUTONEG_ENABLE) {
6038 autoneg |= AUTONEG_SPEED;
6039
6aa20a22 6040 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6041
6042 /* allow advertising 1 speed */
6043 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6044 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6045 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6046 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6047
7b6b8347
MC		 6048 if (cmd->port == PORT_FIBRE)
6049 goto err_out_unlock;
b6016b76
MC		 6050
6051 advertising = cmd->advertising;
6052
27a005b8 6053 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
583c28e5 6054 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
7b6b8347
MC		 6055 (cmd->port == PORT_TP))
6056 goto err_out_unlock;
6057 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
b6016b76 6058 advertising = cmd->advertising;
7b6b8347
MC		 6059 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6060 goto err_out_unlock;
b6016b76 6061 else {
7b6b8347 6062 if (cmd->port == PORT_FIBRE)
b6016b76 6063 advertising = ETHTOOL_ALL_FIBRE_SPEED;
7b6b8347 6064 else
b6016b76 6065 advertising = ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6066 }
6067 advertising |= ADVERTISED_Autoneg;
6068 }
6069 else {
7b6b8347 6070 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6071 if ((cmd->speed != SPEED_1000 &&
6072 cmd->speed != SPEED_2500) ||
6073 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6074 goto err_out_unlock;
80be4434
MC		 6075
6076 if (cmd->speed == SPEED_2500 &&
583c28e5 6077 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6078 goto err_out_unlock;
b6016b76 6079 }
7b6b8347
MC		 6080 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6081 goto err_out_unlock;
6082
b6016b76
MC		 6083 autoneg &= ~AUTONEG_SPEED;
6084 req_line_speed = cmd->speed;
6085 req_duplex = cmd->duplex;
6086 advertising = 0;
6087 }
6088
6089 bp->autoneg = autoneg;
6090 bp->advertising = advertising;
6091 bp->req_line_speed = req_line_speed;
6092 bp->req_duplex = req_duplex;
6093
7b6b8347 6094 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6095
7b6b8347 6096err_out_unlock:
c770a65c 6097 spin_unlock_bh(&bp->phy_lock);
b6016b76 6098
7b6b8347 6099 return err;
b6016b76
MC		 6100}
6101
6102static void
6103bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6104{
972ec0d4 6105 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6106
6107 strcpy(info->driver, DRV_MODULE_NAME);
6108 strcpy(info->version, DRV_MODULE_VERSION);
6109 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6110 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6111}
6112
244ac4f4
MC		 6113#define BNX2_REGDUMP_LEN (32 * 1024)
6114
6115static int
6116bnx2_get_regs_len(struct net_device *dev)
6117{
6118 return BNX2_REGDUMP_LEN;
6119}
6120
6121static void
6122bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6123{
6124 u32 *p = _p, i, offset;
6125 u8 *orig_p = _p;
6126 struct bnx2 *bp = netdev_priv(dev);
6127 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6128 0x0800, 0x0880, 0x0c00, 0x0c10,
6129 0x0c30, 0x0d08, 0x1000, 0x101c,
6130 0x1040, 0x1048, 0x1080, 0x10a4,
6131 0x1400, 0x1490, 0x1498, 0x14f0,
6132 0x1500, 0x155c, 0x1580, 0x15dc,
6133 0x1600, 0x1658, 0x1680, 0x16d8,
6134 0x1800, 0x1820, 0x1840, 0x1854,
6135 0x1880, 0x1894, 0x1900, 0x1984,
6136 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6137 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6138 0x2000, 0x2030, 0x23c0, 0x2400,
6139 0x2800, 0x2820, 0x2830, 0x2850,
6140 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6141 0x3c00, 0x3c94, 0x4000, 0x4010,
6142 0x4080, 0x4090, 0x43c0, 0x4458,
6143 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6144 0x4fc0, 0x5010, 0x53c0, 0x5444,
6145 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6146 0x5fc0, 0x6000, 0x6400, 0x6428,
6147 0x6800, 0x6848, 0x684c, 0x6860,
6148 0x6888, 0x6910, 0x8000 };
6149
6150 regs->version = 0;
6151
6152 memset(p, 0, BNX2_REGDUMP_LEN);
6153
6154 if (!netif_running(bp->dev))
6155 return;
6156
6157 i = 0;
6158 offset = reg_boundaries[0];
6159 p += offset;
6160 while (offset < BNX2_REGDUMP_LEN) {
6161 *p++ = REG_RD(bp, offset);
6162 offset += 4;
6163 if (offset == reg_boundaries[i + 1]) {
6164 offset = reg_boundaries[i + 2];
6165 p = (u32 *) (orig_p + offset);
6166 i += 2;
6167 }
6168 }
6169}
6170
b6016b76
MC		 6171static void
6172bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6173{
972ec0d4 6174 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6175
f86e82fb 6176 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6177 wol->supported = 0;
6178 wol->wolopts = 0;
6179 }
6180 else {
6181 wol->supported = WAKE_MAGIC;
6182 if (bp->wol)
6183 wol->wolopts = WAKE_MAGIC;
6184 else
6185 wol->wolopts = 0;
6186 }
6187 memset(&wol->sopass, 0, sizeof(wol->sopass));
6188}
6189
6190static int
6191bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6192{
972ec0d4 6193 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6194
6195 if (wol->wolopts & ~WAKE_MAGIC)
6196 return -EINVAL;
6197
6198 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6199 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6200 return -EINVAL;
6201
6202 bp->wol = 1;
6203 }
6204 else {
6205 bp->wol = 0;
6206 }
6207 return 0;
6208}
6209
6210static int
6211bnx2_nway_reset(struct net_device *dev)
6212{
972ec0d4 6213 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6214 u32 bmcr;
6215
6216 if (!(bp->autoneg & AUTONEG_SPEED)) {
6217 return -EINVAL;
6218 }
6219
c770a65c 6220 spin_lock_bh(&bp->phy_lock);
b6016b76 6221
583c28e5 6222 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6223 int rc;
6224
6225 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6226 spin_unlock_bh(&bp->phy_lock);
6227 return rc;
6228 }
6229
b6016b76 6230 /* Force a link down visible on the other side */
583c28e5 6231 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6232 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6233 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6234
6235 msleep(20);
6236
c770a65c 6237 spin_lock_bh(&bp->phy_lock);
f8dd064e
MC		 6238
6239 bp->current_interval = SERDES_AN_TIMEOUT;
6240 bp->serdes_an_pending = 1;
6241 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6242 }
6243
ca58c3af 6244 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6245 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6246 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6247
c770a65c 6248 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6249
6250 return 0;
6251}
6252
6253static int
6254bnx2_get_eeprom_len(struct net_device *dev)
6255{
972ec0d4 6256 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6257
1122db71 6258 if (bp->flash_info == NULL)
b6016b76
MC		 6259 return 0;
6260
1122db71 6261 return (int) bp->flash_size;
b6016b76
MC		 6262}
6263
6264static int
6265bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6266 u8 *eebuf)
6267{
972ec0d4 6268 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6269 int rc;
6270
1064e944 6271 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6272
6273 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6274
6275 return rc;
6276}
6277
6278static int
6279bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6280 u8 *eebuf)
6281{
972ec0d4 6282 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6283 int rc;
6284
1064e944 6285 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6286
6287 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6288
6289 return rc;
6290}
6291
6292static int
6293bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6294{
972ec0d4 6295 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6296
6297 memset(coal, 0, sizeof(struct ethtool_coalesce));
6298
6299 coal->rx_coalesce_usecs = bp->rx_ticks;
6300 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6301 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6302 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6303
6304 coal->tx_coalesce_usecs = bp->tx_ticks;
6305 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6306 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6307 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6308
6309 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6310
6311 return 0;
6312}
6313
6314static int
6315bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6316{
972ec0d4 6317 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6318
6319 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6320 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6321
6aa20a22 6322 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 6323 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6324
6325 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6326 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6327
6328 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6329 if (bp->rx_quick_cons_trip_int > 0xff)
6330 bp->rx_quick_cons_trip_int = 0xff;
6331
6332 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6333 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6334
6335 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6336 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6337
6338 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6339 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6340
6341 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6342 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6343 0xff;
6344
6345 bp->stats_ticks = coal->stats_block_coalesce_usecs;
02537b06
MC		 6346 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6347 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6348 bp->stats_ticks = USEC_PER_SEC;
6349 }
7ea6920e
MC		 6350 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6351 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6352 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 6353
6354 if (netif_running(bp->dev)) {
6355 bnx2_netif_stop(bp);
6356 bnx2_init_nic(bp);
6357 bnx2_netif_start(bp);
6358 }
6359
6360 return 0;
6361}
6362
6363static void
6364bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6365{
972ec0d4 6366 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6367
13daffa2 6368 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 6369 ering->rx_mini_max_pending = 0;
47bf4246 6370 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 6371
6372 ering->rx_pending = bp->rx_ring_size;
6373 ering->rx_mini_pending = 0;
47bf4246 6374 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 6375
6376 ering->tx_max_pending = MAX_TX_DESC_CNT;
6377 ering->tx_pending = bp->tx_ring_size;
6378}
6379
6380static int
5d5d0015 6381bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 6382{
13daffa2
MC		 6383 if (netif_running(bp->dev)) {
6384 bnx2_netif_stop(bp);
6385 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6386 bnx2_free_skbs(bp);
6387 bnx2_free_mem(bp);
6388 }
6389
5d5d0015
MC		 6390 bnx2_set_rx_ring_size(bp, rx);
6391 bp->tx_ring_size = tx;
b6016b76
MC		 6392
6393 if (netif_running(bp->dev)) {
13daffa2
MC		 6394 int rc;
6395
6396 rc = bnx2_alloc_mem(bp);
6397 if (rc)
6398 return rc;
b6016b76
MC		 6399 bnx2_init_nic(bp);
6400 bnx2_netif_start(bp);
6401 }
b6016b76
MC		 6402 return 0;
6403}
6404
5d5d0015
MC		 6405static int
6406bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6407{
6408 struct bnx2 *bp = netdev_priv(dev);
6409 int rc;
6410
6411 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6412 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6413 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6414
6415 return -EINVAL;
6416 }
6417 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6418 return rc;
6419}
6420
b6016b76
MC		 6421static void
6422bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6423{
972ec0d4 6424 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6425
6426 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6427 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6428 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6429}
6430
6431static int
6432bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6433{
972ec0d4 6434 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6435
6436 bp->req_flow_ctrl = 0;
6437 if (epause->rx_pause)
6438 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6439 if (epause->tx_pause)
6440 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6441
6442 if (epause->autoneg) {
6443 bp->autoneg |= AUTONEG_FLOW_CTRL;
6444 }
6445 else {
6446 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6447 }
6448
c770a65c 6449 spin_lock_bh(&bp->phy_lock);
b6016b76 6450
0d8a6571 6451 bnx2_setup_phy(bp, bp->phy_port);
b6016b76 6452
c770a65c 6453 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6454
6455 return 0;
6456}
6457
6458static u32
6459bnx2_get_rx_csum(struct net_device *dev)
6460{
972ec0d4 6461 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6462
6463 return bp->rx_csum;
6464}
6465
6466static int
6467bnx2_set_rx_csum(struct net_device *dev, u32 data)
6468{
972ec0d4 6469 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6470
6471 bp->rx_csum = data;
6472 return 0;
6473}
6474
b11d6213
MC		 6475static int
6476bnx2_set_tso(struct net_device *dev, u32 data)
6477{
4666f87a
MC		 6478 struct bnx2 *bp = netdev_priv(dev);
6479
6480 if (data) {
b11d6213 6481 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 6482 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6483 dev->features |= NETIF_F_TSO6;
6484 } else
6485 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6486 NETIF_F_TSO_ECN);
b11d6213
MC		 6487 return 0;
6488}
6489
cea94db9 6490#define BNX2_NUM_STATS 46
b6016b76 6491
14ab9b86 6492static struct {
b6016b76
MC		 6493 char string[ETH_GSTRING_LEN];
6494} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6495 { "rx_bytes" },
6496 { "rx_error_bytes" },
6497 { "tx_bytes" },
6498 { "tx_error_bytes" },
6499 { "rx_ucast_packets" },
6500 { "rx_mcast_packets" },
6501 { "rx_bcast_packets" },
6502 { "tx_ucast_packets" },
6503 { "tx_mcast_packets" },
6504 { "tx_bcast_packets" },
6505 { "tx_mac_errors" },
6506 { "tx_carrier_errors" },
6507 { "rx_crc_errors" },
6508 { "rx_align_errors" },
6509 { "tx_single_collisions" },
6510 { "tx_multi_collisions" },
6511 { "tx_deferred" },
6512 { "tx_excess_collisions" },
6513 { "tx_late_collisions" },
6514 { "tx_total_collisions" },
6515 { "rx_fragments" },
6516 { "rx_jabbers" },
6517 { "rx_undersize_packets" },
6518 { "rx_oversize_packets" },
6519 { "rx_64_byte_packets" },
6520 { "rx_65_to_127_byte_packets" },
6521 { "rx_128_to_255_byte_packets" },
6522 { "rx_256_to_511_byte_packets" },
6523 { "rx_512_to_1023_byte_packets" },
6524 { "rx_1024_to_1522_byte_packets" },
6525 { "rx_1523_to_9022_byte_packets" },
6526 { "tx_64_byte_packets" },
6527 { "tx_65_to_127_byte_packets" },
6528 { "tx_128_to_255_byte_packets" },
6529 { "tx_256_to_511_byte_packets" },
6530 { "tx_512_to_1023_byte_packets" },
6531 { "tx_1024_to_1522_byte_packets" },
6532 { "tx_1523_to_9022_byte_packets" },
6533 { "rx_xon_frames" },
6534 { "rx_xoff_frames" },
6535 { "tx_xon_frames" },
6536 { "tx_xoff_frames" },
6537 { "rx_mac_ctrl_frames" },
6538 { "rx_filtered_packets" },
6539 { "rx_discards" },
cea94db9 6540 { "rx_fw_discards" },
b6016b76
MC		 6541};
6542
6543#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6544
f71e1309 6545static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6546 STATS_OFFSET32(stat_IfHCInOctets_hi),
6547 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6548 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6549 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6550 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6551 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6552 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6553 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6554 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6555 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6556 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 6557 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6558 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6559 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6560 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6561 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6562 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6563 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6564 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6565 STATS_OFFSET32(stat_EtherStatsCollisions),
6566 STATS_OFFSET32(stat_EtherStatsFragments),
6567 STATS_OFFSET32(stat_EtherStatsJabbers),
6568 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6569 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6570 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6571 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6572 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6573 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6574 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6575 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6576 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6577 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6578 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6579 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6580 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6581 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6582 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6583 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6584 STATS_OFFSET32(stat_XonPauseFramesReceived),
6585 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6586 STATS_OFFSET32(stat_OutXonSent),
6587 STATS_OFFSET32(stat_OutXoffSent),
6588 STATS_OFFSET32(stat_MacControlFramesReceived),
6589 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6590 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 6591 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 6592};
6593
6594/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6595 * skipped because of errata.
6aa20a22 6596 */
14ab9b86 6597static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6598 8,0,8,8,8,8,8,8,8,8,
6599 4,0,4,4,4,4,4,4,4,4,
6600 4,4,4,4,4,4,4,4,4,4,
6601 4,4,4,4,4,4,4,4,4,4,
cea94db9 6602 4,4,4,4,4,4,
b6016b76
MC		 6603};
6604
5b0c76ad
MC		 6605static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6606 8,0,8,8,8,8,8,8,8,8,
6607 4,4,4,4,4,4,4,4,4,4,
6608 4,4,4,4,4,4,4,4,4,4,
6609 4,4,4,4,4,4,4,4,4,4,
cea94db9 6610 4,4,4,4,4,4,
5b0c76ad
MC		 6611};
6612
b6016b76
MC		 6613#define BNX2_NUM_TESTS 6
6614
14ab9b86 6615static struct {
b6016b76
MC		 6616 char string[ETH_GSTRING_LEN];
6617} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6618 { "register_test (offline)" },
6619 { "memory_test (offline)" },
6620 { "loopback_test (offline)" },
6621 { "nvram_test (online)" },
6622 { "interrupt_test (online)" },
6623 { "link_test (online)" },
6624};
6625
6626static int
b9f2c044 6627bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 6628{
b9f2c044
JG		 6629 switch (sset) {
6630 case ETH_SS_TEST:
6631 return BNX2_NUM_TESTS;
6632 case ETH_SS_STATS:
6633 return BNX2_NUM_STATS;
6634 default:
6635 return -EOPNOTSUPP;
6636 }
b6016b76
MC		 6637}
6638
6639static void
6640bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6641{
972ec0d4 6642 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6643
6644 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6645 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 6646 int i;
6647
b6016b76
MC		 6648 bnx2_netif_stop(bp);
6649 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6650 bnx2_free_skbs(bp);
6651
6652 if (bnx2_test_registers(bp) != 0) {
6653 buf[0] = 1;
6654 etest->flags |= ETH_TEST_FL_FAILED;
6655 }
6656 if (bnx2_test_memory(bp) != 0) {
6657 buf[1] = 1;
6658 etest->flags |= ETH_TEST_FL_FAILED;
6659 }
bc5a0690 6660 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 6661 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76
MC		 6662
6663 if (!netif_running(bp->dev)) {
6664 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6665 }
6666 else {
6667 bnx2_init_nic(bp);
6668 bnx2_netif_start(bp);
6669 }
6670
6671 /* wait for link up */
80be4434
MC		 6672 for (i = 0; i < 7; i++) {
6673 if (bp->link_up)
6674 break;
6675 msleep_interruptible(1000);
6676 }
b6016b76
MC		 6677 }
6678
6679 if (bnx2_test_nvram(bp) != 0) {
6680 buf[3] = 1;
6681 etest->flags |= ETH_TEST_FL_FAILED;
6682 }
6683 if (bnx2_test_intr(bp) != 0) {
6684 buf[4] = 1;
6685 etest->flags |= ETH_TEST_FL_FAILED;
6686 }
6687
6688 if (bnx2_test_link(bp) != 0) {
6689 buf[5] = 1;
6690 etest->flags |= ETH_TEST_FL_FAILED;
6691
6692 }
6693}
6694
6695static void
6696bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6697{
6698 switch (stringset) {
6699 case ETH_SS_STATS:
6700 memcpy(buf, bnx2_stats_str_arr,
6701 sizeof(bnx2_stats_str_arr));
6702 break;
6703 case ETH_SS_TEST:
6704 memcpy(buf, bnx2_tests_str_arr,
6705 sizeof(bnx2_tests_str_arr));
6706 break;
6707 }
6708}
6709
b6016b76
MC		 6710static void
6711bnx2_get_ethtool_stats(struct net_device *dev,
6712 struct ethtool_stats *stats, u64 *buf)
6713{
972ec0d4 6714 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6715 int i;
6716 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 6717 u8 *stats_len_arr = NULL;
b6016b76
MC		 6718
6719 if (hw_stats == NULL) {
6720 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6721 return;
6722 }
6723
5b0c76ad
MC		 6724 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6725 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6726 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6727 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 6728 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 6729 else
6730 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 6731
6732 for (i = 0; i < BNX2_NUM_STATS; i++) {
6733 if (stats_len_arr[i] == 0) {
6734 /* skip this counter */
6735 buf[i] = 0;
6736 continue;
6737 }
6738 if (stats_len_arr[i] == 4) {
6739 /* 4-byte counter */
6740 buf[i] = (u64)
6741 *(hw_stats + bnx2_stats_offset_arr[i]);
6742 continue;
6743 }
6744 /* 8-byte counter */
6745 buf[i] = (((u64) *(hw_stats +
6746 bnx2_stats_offset_arr[i])) << 32) +
6747 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6748 }
6749}
6750
6751static int
6752bnx2_phys_id(struct net_device *dev, u32 data)
6753{
972ec0d4 6754 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6755 int i;
6756 u32 save;
6757
6758 if (data == 0)
6759 data = 2;
6760
6761 save = REG_RD(bp, BNX2_MISC_CFG);
6762 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6763
6764 for (i = 0; i < (data * 2); i++) {
6765 if ((i % 2) == 0) {
6766 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6767 }
6768 else {
6769 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6770 BNX2_EMAC_LED_1000MB_OVERRIDE |
6771 BNX2_EMAC_LED_100MB_OVERRIDE |
6772 BNX2_EMAC_LED_10MB_OVERRIDE |
6773 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6774 BNX2_EMAC_LED_TRAFFIC);
6775 }
6776 msleep_interruptible(500);
6777 if (signal_pending(current))
6778 break;
6779 }
6780 REG_WR(bp, BNX2_EMAC_LED, 0);
6781 REG_WR(bp, BNX2_MISC_CFG, save);
6782 return 0;
6783}
6784
4666f87a
MC		 6785static int
6786bnx2_set_tx_csum(struct net_device *dev, u32 data)
6787{
6788 struct bnx2 *bp = netdev_priv(dev);
6789
6790 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 6791 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 6792 else
6793 return (ethtool_op_set_tx_csum(dev, data));
6794}
6795
7282d491 6796static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 6797 .get_settings = bnx2_get_settings,
6798 .set_settings = bnx2_set_settings,
6799 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 6800 .get_regs_len = bnx2_get_regs_len,
6801 .get_regs = bnx2_get_regs,
b6016b76
MC		 6802 .get_wol = bnx2_get_wol,
6803 .set_wol = bnx2_set_wol,
6804 .nway_reset = bnx2_nway_reset,
6805 .get_link = ethtool_op_get_link,
6806 .get_eeprom_len = bnx2_get_eeprom_len,
6807 .get_eeprom = bnx2_get_eeprom,
6808 .set_eeprom = bnx2_set_eeprom,
6809 .get_coalesce = bnx2_get_coalesce,
6810 .set_coalesce = bnx2_set_coalesce,
6811 .get_ringparam = bnx2_get_ringparam,
6812 .set_ringparam = bnx2_set_ringparam,
6813 .get_pauseparam = bnx2_get_pauseparam,
6814 .set_pauseparam = bnx2_set_pauseparam,
6815 .get_rx_csum = bnx2_get_rx_csum,
6816 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 6817 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 6818 .set_sg = ethtool_op_set_sg,
b11d6213 6819 .set_tso = bnx2_set_tso,
b6016b76
MC		 6820 .self_test = bnx2_self_test,
6821 .get_strings = bnx2_get_strings,
6822 .phys_id = bnx2_phys_id,
b6016b76 6823 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 6824 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 6825};
6826
6827/* Called with rtnl_lock */
6828static int
6829bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6830{
14ab9b86 6831 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 6832 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6833 int err;
6834
6835 switch(cmd) {
6836 case SIOCGMIIPHY:
6837 data->phy_id = bp->phy_addr;
6838
6839 /* fallthru */
6840 case SIOCGMIIREG: {
6841 u32 mii_regval;
6842
583c28e5 6843 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6844 return -EOPNOTSUPP;
6845
dad3e452
MC		 6846 if (!netif_running(dev))
6847 return -EAGAIN;
6848
c770a65c 6849 spin_lock_bh(&bp->phy_lock);
b6016b76 6850 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 6851 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6852
6853 data->val_out = mii_regval;
6854
6855 return err;
6856 }
6857
6858 case SIOCSMIIREG:
6859 if (!capable(CAP_NET_ADMIN))
6860 return -EPERM;
6861
583c28e5 6862 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6863 return -EOPNOTSUPP;
6864
dad3e452
MC		 6865 if (!netif_running(dev))
6866 return -EAGAIN;
6867
c770a65c 6868 spin_lock_bh(&bp->phy_lock);
b6016b76 6869 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 6870 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6871
6872 return err;
6873
6874 default:
6875 /* do nothing */
6876 break;
6877 }
6878 return -EOPNOTSUPP;
6879}
6880
6881/* Called with rtnl_lock */
6882static int
6883bnx2_change_mac_addr(struct net_device *dev, void *p)
6884{
6885 struct sockaddr *addr = p;
972ec0d4 6886 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6887
73eef4cd
MC		 6888 if (!is_valid_ether_addr(addr->sa_data))
6889 return -EINVAL;
6890
b6016b76
MC		 6891 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6892 if (netif_running(dev))
6893 bnx2_set_mac_addr(bp);
6894
6895 return 0;
6896}
6897
6898/* Called with rtnl_lock */
6899static int
6900bnx2_change_mtu(struct net_device *dev, int new_mtu)
6901{
972ec0d4 6902 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6903
6904 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6905 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6906 return -EINVAL;
6907
6908 dev->mtu = new_mtu;
5d5d0015 6909 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 6910}
6911
6912#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6913static void
6914poll_bnx2(struct net_device *dev)
6915{
972ec0d4 6916 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6917
6918 disable_irq(bp->pdev->irq);
7d12e780 6919 bnx2_interrupt(bp->pdev->irq, dev);
b6016b76
MC		 6920 enable_irq(bp->pdev->irq);
6921}
6922#endif
6923
253c8b75
MC		 6924static void __devinit
6925bnx2_get_5709_media(struct bnx2 *bp)
6926{
6927 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6928 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6929 u32 strap;
6930
6931 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6932 return;
6933 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 6934 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 6935 return;
6936 }
6937
6938 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6939 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6940 else
6941 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6942
6943 if (PCI_FUNC(bp->pdev->devfn) == 0) {
6944 switch (strap) {
6945 case 0x4:
6946 case 0x5:
6947 case 0x6:
583c28e5 6948 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 6949 return;
6950 }
6951 } else {
6952 switch (strap) {
6953 case 0x1:
6954 case 0x2:
6955 case 0x4:
583c28e5 6956 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 6957 return;
6958 }
6959 }
6960}
6961
883e5151
MC		 6962static void __devinit
6963bnx2_get_pci_speed(struct bnx2 *bp)
6964{
6965 u32 reg;
6966
6967 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
6968 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
6969 u32 clkreg;
6970
f86e82fb 6971 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 6972
6973 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
6974
6975 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
6976 switch (clkreg) {
6977 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
6978 bp->bus_speed_mhz = 133;
6979 break;
6980
6981 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
6982 bp->bus_speed_mhz = 100;
6983 break;
6984
6985 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
6986 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
6987 bp->bus_speed_mhz = 66;
6988 break;
6989
6990 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
6991 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
6992 bp->bus_speed_mhz = 50;
6993 break;
6994
6995 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
6996 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
6997 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
6998 bp->bus_speed_mhz = 33;
6999 break;
7000 }
7001 }
7002 else {
7003 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7004 bp->bus_speed_mhz = 66;
7005 else
7006 bp->bus_speed_mhz = 33;
7007 }
7008
7009 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7010 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7011
7012}
7013
b6016b76
MC		 7014static int __devinit
7015bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7016{
7017 struct bnx2 *bp;
7018 unsigned long mem_len;
58fc2ea4 7019 int rc, i, j;
b6016b76 7020 u32 reg;
40453c83 7021 u64 dma_mask, persist_dma_mask;
b6016b76 7022
b6016b76 7023 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7024 bp = netdev_priv(dev);
b6016b76
MC		 7025
7026 bp->flags = 0;
7027 bp->phy_flags = 0;
7028
7029 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7030 rc = pci_enable_device(pdev);
7031 if (rc) {
898eb71c 7032 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
b6016b76
MC		 7033 goto err_out;
7034 }
7035
7036 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7037 dev_err(&pdev->dev,
2e8a538d 7038 "Cannot find PCI device base address, aborting.\n");
b6016b76
MC		 7039 rc = -ENODEV;
7040 goto err_out_disable;
7041 }
7042
7043 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7044 if (rc) {
9b91cf9d 7045 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
b6016b76
MC		 7046 goto err_out_disable;
7047 }
7048
7049 pci_set_master(pdev);
7050
7051 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7052 if (bp->pm_cap == 0) {
9b91cf9d 7053 dev_err(&pdev->dev,
2e8a538d 7054 "Cannot find power management capability, aborting.\n");
b6016b76
MC		 7055 rc = -EIO;
7056 goto err_out_release;
7057 }
7058
b6016b76
MC		 7059 bp->dev = dev;
7060 bp->pdev = pdev;
7061
7062 spin_lock_init(&bp->phy_lock);
1b8227c4 7063 spin_lock_init(&bp->indirect_lock);
c4028958 7064 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7065
7066 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
59b47d8a 7067 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
b6016b76
MC		 7068 dev->mem_end = dev->mem_start + mem_len;
7069 dev->irq = pdev->irq;
7070
7071 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7072
7073 if (!bp->regview) {
9b91cf9d 7074 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
b6016b76
MC		 7075 rc = -ENOMEM;
7076 goto err_out_release;
7077 }
7078
7079 /* Configure byte swap and enable write to the reg_window registers.
7080 * Rely on CPU to do target byte swapping on big endian systems
7081 * The chip's target access swapping will not swap all accesses
7082 */
7083 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7084 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7085 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7086
829ca9a3 7087 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7088
7089 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7090
883e5151
MC		 7091 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7092 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7093 dev_err(&pdev->dev,
7094 "Cannot find PCIE capability, aborting.\n");
7095 rc = -EIO;
7096 goto err_out_unmap;
7097 }
f86e82fb 7098 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7099 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7100 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7101 } else {
59b47d8a
MC		 7102 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7103 if (bp->pcix_cap == 0) {
7104 dev_err(&pdev->dev,
7105 "Cannot find PCIX capability, aborting.\n");
7106 rc = -EIO;
7107 goto err_out_unmap;
7108 }
7109 }
7110
b4b36042
MC		 7111 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7112 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7113 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7114 }
7115
8e6a72c4
MC		 7116 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7117 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7118 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7119 }
7120
40453c83
MC		 7121 /* 5708 cannot support DMA addresses > 40-bit. */
7122 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7123 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7124 else
7125 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7126
7127 /* Configure DMA attributes. */
7128 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7129 dev->features |= NETIF_F_HIGHDMA;
7130 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7131 if (rc) {
7132 dev_err(&pdev->dev,
7133 "pci_set_consistent_dma_mask failed, aborting.\n");
7134 goto err_out_unmap;
7135 }
7136 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7137 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7138 goto err_out_unmap;
7139 }
7140
f86e82fb 7141 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7142 bnx2_get_pci_speed(bp);
b6016b76
MC		 7143
7144 /* 5706A0 may falsely detect SERR and PERR. */
7145 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7146 reg = REG_RD(bp, PCI_COMMAND);
7147 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7148 REG_WR(bp, PCI_COMMAND, reg);
7149 }
7150 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 7151 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 7152
9b91cf9d 7153 dev_err(&pdev->dev,
2e8a538d 7154 "5706 A1 can only be used in a PCIX bus, aborting.\n");
b6016b76
MC		 7155 goto err_out_unmap;
7156 }
7157
7158 bnx2_init_nvram(bp);
7159
e3648b3d
MC		 7160 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
7161
7162 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 7163 BNX2_SHM_HDR_SIGNATURE_SIG) {
7164 u32 off = PCI_FUNC(pdev->devfn) << 2;
7165
7166 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
7167 } else
e3648b3d
MC		 7168 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7169
b6016b76
MC		 7170 /* Get the permanent MAC address. First we need to make sure the
7171 * firmware is actually running.
7172 */
e3648b3d 7173 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 7174
7175 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7176 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
9b91cf9d 7177 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
b6016b76
MC		 7178 rc = -ENODEV;
7179 goto err_out_unmap;
7180 }
7181
58fc2ea4
MC		 7182 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
7183 for (i = 0, j = 0; i < 3; i++) {
7184 u8 num, k, skip0;
7185
7186 num = (u8) (reg >> (24 - (i * 8)));
7187 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7188 if (num >= k || !skip0 || k == 1) {
7189 bp->fw_version[j++] = (num / k) + '0';
7190 skip0 = 0;
7191 }
7192 }
7193 if (i != 2)
7194 bp->fw_version[j++] = '.';
7195 }
846f5c62
MC		 7196 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);
7197 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7198 bp->wol = 1;
7199
7200 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 7201 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 7202
7203 for (i = 0; i < 30; i++) {
7204 reg = REG_RD_IND(bp, bp->shmem_base +
7205 BNX2_BC_STATE_CONDITION);
7206 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7207 break;
7208 msleep(10);
7209 }
7210 }
58fc2ea4
MC		 7211 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);
7212 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7213 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7214 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7215 int i;
7216 u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR);
7217
7218 bp->fw_version[j++] = ' ';
7219 for (i = 0; i < 3; i++) {
7220 reg = REG_RD_IND(bp, addr + i * 4);
7221 reg = swab32(reg);
7222 memcpy(&bp->fw_version[j], &reg, 4);
7223 j += 4;
7224 }
7225 }
b6016b76 7226
e3648b3d 7227 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 7228 bp->mac_addr[0] = (u8) (reg >> 8);
7229 bp->mac_addr[1] = (u8) reg;
7230
e3648b3d 7231 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 7232 bp->mac_addr[2] = (u8) (reg >> 24);
7233 bp->mac_addr[3] = (u8) (reg >> 16);
7234 bp->mac_addr[4] = (u8) (reg >> 8);
7235 bp->mac_addr[5] = (u8) reg;
7236
5d5d0015
MC		 7237 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
7238
b6016b76 7239 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 7240 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 7241
7242 bp->rx_csum = 1;
7243
b6016b76
MC		 7244 bp->tx_quick_cons_trip_int = 20;
7245 bp->tx_quick_cons_trip = 20;
7246 bp->tx_ticks_int = 80;
7247 bp->tx_ticks = 80;
6aa20a22 7248
b6016b76
MC		 7249 bp->rx_quick_cons_trip_int = 6;
7250 bp->rx_quick_cons_trip = 6;
7251 bp->rx_ticks_int = 18;
7252 bp->rx_ticks = 18;
7253
7ea6920e 7254 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7255
7256 bp->timer_interval = HZ;
cd339a0e 7257 bp->current_interval = HZ;
b6016b76 7258
5b0c76ad
MC		 7259 bp->phy_addr = 1;
7260
b6016b76 7261 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 7262 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7263 bnx2_get_5709_media(bp);
7264 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 7265 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 7266
0d8a6571 7267 bp->phy_port = PORT_TP;
583c28e5 7268 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 7269 bp->phy_port = PORT_FIBRE;
846f5c62
MC		 7270 reg = REG_RD_IND(bp, bp->shmem_base +
7271 BNX2_SHARED_HW_CFG_CONFIG);
7272 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 7273 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7274 bp->wol = 0;
7275 }
bac0dff6 7276 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
5b0c76ad 7277 bp->phy_addr = 2;
5b0c76ad 7278 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 7279 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 7280 }
0d8a6571
MC		 7281 bnx2_init_remote_phy(bp);
7282
261dd5ca
MC		 7283 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7284 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 7285 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 7286 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7287 (CHIP_REV(bp) == CHIP_REV_Ax ||
7288 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 7289 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 7290
16088272
MC		 7291 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7292 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
846f5c62 7293 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
f86e82fb 7294 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7295 bp->wol = 0;
7296 }
dda1e390 7297
b6016b76
MC		 7298 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7299 bp->tx_quick_cons_trip_int =
7300 bp->tx_quick_cons_trip;
7301 bp->tx_ticks_int = bp->tx_ticks;
7302 bp->rx_quick_cons_trip_int =
7303 bp->rx_quick_cons_trip;
7304 bp->rx_ticks_int = bp->rx_ticks;
7305 bp->comp_prod_trip_int = bp->comp_prod_trip;
7306 bp->com_ticks_int = bp->com_ticks;
7307 bp->cmd_ticks_int = bp->cmd_ticks;
7308 }
7309
f9317a40
MC		 7310 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7311 *
7312 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7313 * with byte enables disabled on the unused 32-bit word. This is legal
7314 * but causes problems on the AMD 8132 which will eventually stop
7315 * responding after a while.
7316 *
7317 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 7318 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 7319 */
7320 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7321 struct pci_dev *amd_8132 = NULL;
7322
7323 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7324 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7325 amd_8132))) {
f9317a40 7326
44c10138
AK		 7327 if (amd_8132->revision >= 0x10 &&
7328 amd_8132->revision <= 0x13) {
f9317a40
MC		 7329 disable_msi = 1;
7330 pci_dev_put(amd_8132);
7331 break;
7332 }
7333 }
7334 }
7335
deaf391b 7336 bnx2_set_default_link(bp);
b6016b76
MC		 7337 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7338
cd339a0e
MC		 7339 init_timer(&bp->timer);
7340 bp->timer.expires = RUN_AT(bp->timer_interval);
7341 bp->timer.data = (unsigned long) bp;
7342 bp->timer.function = bnx2_timer;
7343
b6016b76
MC		 7344 return 0;
7345
7346err_out_unmap:
7347 if (bp->regview) {
7348 iounmap(bp->regview);
73eef4cd 7349 bp->regview = NULL;
b6016b76
MC		 7350 }
7351
7352err_out_release:
7353 pci_release_regions(pdev);
7354
7355err_out_disable:
7356 pci_disable_device(pdev);
7357 pci_set_drvdata(pdev, NULL);
7358
7359err_out:
7360 return rc;
7361}
7362
883e5151
MC		 7363static char * __devinit
7364bnx2_bus_string(struct bnx2 *bp, char *str)
7365{
7366 char *s = str;
7367
f86e82fb 7368 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 7369 s += sprintf(s, "PCI Express");
7370 } else {
7371 s += sprintf(s, "PCI");
f86e82fb 7372 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 7373 s += sprintf(s, "-X");
f86e82fb 7374 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 7375 s += sprintf(s, " 32-bit");
7376 else
7377 s += sprintf(s, " 64-bit");
7378 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7379 }
7380 return str;
7381}
7382
2ba582b7 7383static void __devinit
35efa7c1
MC		 7384bnx2_init_napi(struct bnx2 *bp)
7385{
b4b36042
MC		 7386 int i;
7387 struct bnx2_napi *bnapi;
35efa7c1 7388
b4b36042
MC		 7389 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7390 bnapi = &bp->bnx2_napi[i];
7391 bnapi->bp = bp;
7392 }
7393 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
57851d84
MC		 7394 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7395 64);
35efa7c1
MC		 7396}
7397
b6016b76
MC		 7398static int __devinit
7399bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7400{
7401 static int version_printed = 0;
7402 struct net_device *dev = NULL;
7403 struct bnx2 *bp;
0795af57 7404 int rc;
883e5151 7405 char str[40];
0795af57 7406 DECLARE_MAC_BUF(mac);
b6016b76
MC		 7407
7408 if (version_printed++ == 0)
7409 printk(KERN_INFO "%s", version);
7410
7411 /* dev zeroed in init_etherdev */
7412 dev = alloc_etherdev(sizeof(*bp));
7413
7414 if (!dev)
7415 return -ENOMEM;
7416
7417 rc = bnx2_init_board(pdev, dev);
7418 if (rc < 0) {
7419 free_netdev(dev);
7420 return rc;
7421 }
7422
7423 dev->open = bnx2_open;
7424 dev->hard_start_xmit = bnx2_start_xmit;
7425 dev->stop = bnx2_close;
7426 dev->get_stats = bnx2_get_stats;
7427 dev->set_multicast_list = bnx2_set_rx_mode;
7428 dev->do_ioctl = bnx2_ioctl;
7429 dev->set_mac_address = bnx2_change_mac_addr;
7430 dev->change_mtu = bnx2_change_mtu;
7431 dev->tx_timeout = bnx2_tx_timeout;
7432 dev->watchdog_timeo = TX_TIMEOUT;
7433#ifdef BCM_VLAN
7434 dev->vlan_rx_register = bnx2_vlan_rx_register;
b6016b76 7435#endif
b6016b76 7436 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 7437
972ec0d4 7438 bp = netdev_priv(dev);
35efa7c1 7439 bnx2_init_napi(bp);
b6016b76
MC		 7440
7441#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7442 dev->poll_controller = poll_bnx2;
7443#endif
7444
1b2f922f
MC		 7445 pci_set_drvdata(pdev, dev);
7446
7447 memcpy(dev->dev_addr, bp->mac_addr, 6);
7448 memcpy(dev->perm_addr, bp->mac_addr, 6);
7449 bp->name = board_info[ent->driver_data].name;
7450
d212f87b 7451 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4666f87a 7452 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d212f87b
SH		 7453 dev->features |= NETIF_F_IPV6_CSUM;
7454
1b2f922f
MC		 7455#ifdef BCM_VLAN
7456 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7457#endif
7458 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7459 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7460 dev->features |= NETIF_F_TSO6;
1b2f922f 7461
b6016b76 7462 if ((rc = register_netdev(dev))) {
9b91cf9d 7463 dev_err(&pdev->dev, "Cannot register net device\n");
b6016b76
MC		 7464 if (bp->regview)
7465 iounmap(bp->regview);
7466 pci_release_regions(pdev);
7467 pci_disable_device(pdev);
7468 pci_set_drvdata(pdev, NULL);
7469 free_netdev(dev);
7470 return rc;
7471 }
7472
883e5151 7473 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
0795af57 7474 "IRQ %d, node addr %s\n",
b6016b76
MC		 7475 dev->name,
7476 bp->name,
7477 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7478 ((CHIP_ID(bp) & 0x0ff0) >> 4),
883e5151 7479 bnx2_bus_string(bp, str),
b6016b76 7480 dev->base_addr,
0795af57 7481 bp->pdev->irq, print_mac(mac, dev->dev_addr));
b6016b76 7482
b6016b76
MC		 7483 return 0;
7484}
7485
7486static void __devexit
7487bnx2_remove_one(struct pci_dev *pdev)
7488{
7489 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7490 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7491
afdc08b9
MC		 7492 flush_scheduled_work();
7493
b6016b76
MC		 7494 unregister_netdev(dev);
7495
7496 if (bp->regview)
7497 iounmap(bp->regview);
7498
7499 free_netdev(dev);
7500 pci_release_regions(pdev);
7501 pci_disable_device(pdev);
7502 pci_set_drvdata(pdev, NULL);
7503}
7504
7505static int
829ca9a3 7506bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 7507{
7508 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7509 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7510 u32 reset_code;
7511
6caebb02
MC		 7512 /* PCI register 4 needs to be saved whether netif_running() or not.
7513 * MSI address and data need to be saved if using MSI and
7514 * netif_running().
7515 */
7516 pci_save_state(pdev);
b6016b76
MC		 7517 if (!netif_running(dev))
7518 return 0;
7519
1d60290f 7520 flush_scheduled_work();
b6016b76
MC		 7521 bnx2_netif_stop(bp);
7522 netif_device_detach(dev);
7523 del_timer_sync(&bp->timer);
f86e82fb 7524 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 7525 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 7526 else if (bp->wol)
b6016b76
MC		 7527 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7528 else
7529 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7530 bnx2_reset_chip(bp, reset_code);
7531 bnx2_free_skbs(bp);
829ca9a3 7532 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 7533 return 0;
7534}
7535
7536static int
7537bnx2_resume(struct pci_dev *pdev)
7538{
7539 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7540 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7541
6caebb02 7542 pci_restore_state(pdev);
b6016b76
MC		 7543 if (!netif_running(dev))
7544 return 0;
7545
829ca9a3 7546 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7547 netif_device_attach(dev);
7548 bnx2_init_nic(bp);
7549 bnx2_netif_start(bp);
7550 return 0;
7551}
7552
7553static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 7554 .name = DRV_MODULE_NAME,
7555 .id_table = bnx2_pci_tbl,
7556 .probe = bnx2_init_one,
7557 .remove = __devexit_p(bnx2_remove_one),
7558 .suspend = bnx2_suspend,
7559 .resume = bnx2_resume,
b6016b76
MC		 7560};
7561
7562static int __init bnx2_init(void)
7563{
29917620 7564 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 7565}
7566
7567static void __exit bnx2_cleanup(void)
7568{
7569 pci_unregister_driver(&bnx2_pci_driver);
7570}
7571
7572module_init(bnx2_init);
7573module_exit(bnx2_cleanup);
7574
7575
7576
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