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a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
ec6ba945 | 16 | #include <linux/netdevice.h> |
b7f080cf | 17 | #include <linux/dma-mapping.h> |
ec6ba945 | 18 | #include <linux/types.h> |
a2fbb9ea | 19 | |
34f80b04 EG |
20 | /* compilation time flags */ |
21 | ||
22 | /* define this to make the driver freeze on error to allow getting debug info | |
23 | * (you will need to reboot afterwards) */ | |
24 | /* #define BNX2X_STOP_ON_ERROR */ | |
25 | ||
b96368e9 VZ |
26 | #define DRV_MODULE_VERSION "1.70.00-0" |
27 | #define DRV_MODULE_RELDATE "2011/06/13" | |
de0c62db DK |
28 | #define BNX2X_BC_VER 0x040200 |
29 | ||
785b9b1a | 30 | #if defined(CONFIG_DCB) |
98507672 | 31 | #define BCM_DCBNL |
785b9b1a | 32 | #endif |
993ac7b5 MC |
33 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
34 | #define BCM_CNIC 1 | |
5d1e859c | 35 | #include "../cnic_if.h" |
993ac7b5 | 36 | #endif |
0c6671b0 | 37 | |
1ac218c8 VZ |
38 | #ifdef BCM_CNIC |
39 | #define BNX2X_MIN_MSIX_VEC_CNT 3 | |
40 | #define BNX2X_MSIX_VEC_FP_START 2 | |
41 | #else | |
42 | #define BNX2X_MIN_MSIX_VEC_CNT 2 | |
43 | #define BNX2X_MSIX_VEC_FP_START 1 | |
44 | #endif | |
01cd4528 EG |
45 | |
46 | #include <linux/mdio.h> | |
619c5cb6 | 47 | |
359d8b15 EG |
48 | #include "bnx2x_reg.h" |
49 | #include "bnx2x_fw_defs.h" | |
50 | #include "bnx2x_hsi.h" | |
51 | #include "bnx2x_link.h" | |
619c5cb6 | 52 | #include "bnx2x_sp.h" |
e4901dde | 53 | #include "bnx2x_dcb.h" |
6c719d00 | 54 | #include "bnx2x_stats.h" |
359d8b15 | 55 | |
a2fbb9ea ET |
56 | /* error/debug prints */ |
57 | ||
34f80b04 | 58 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
59 | |
60 | /* for messages that are currently off */ | |
34f80b04 EG |
61 | #define BNX2X_MSG_OFF 0 |
62 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
63 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
64 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
65 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
66 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
67 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 68 | |
34f80b04 | 69 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
a2fbb9ea ET |
70 | |
71 | /* regular debug print */ | |
7995c64e JP |
72 | #define DP(__mask, __fmt, __args...) \ |
73 | do { \ | |
74 | if (bp->msg_enable & (__mask)) \ | |
75 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \ | |
76 | __func__, __LINE__, \ | |
77 | bp->dev ? (bp->dev->name) : "?", \ | |
78 | ##__args); \ | |
79 | } while (0) | |
a2fbb9ea | 80 | |
619c5cb6 VZ |
81 | #define DP_CONT(__mask, __fmt, __args...) \ |
82 | do { \ | |
83 | if (bp->msg_enable & (__mask)) \ | |
84 | pr_cont(__fmt, ##__args); \ | |
85 | } while (0) | |
86 | ||
34f80b04 | 87 | /* errors debug print */ |
7995c64e JP |
88 | #define BNX2X_DBG_ERR(__fmt, __args...) \ |
89 | do { \ | |
90 | if (netif_msg_probe(bp)) \ | |
91 | pr_err("[%s:%d(%s)]" __fmt, \ | |
92 | __func__, __LINE__, \ | |
93 | bp->dev ? (bp->dev->name) : "?", \ | |
94 | ##__args); \ | |
95 | } while (0) | |
a2fbb9ea | 96 | |
34f80b04 | 97 | /* for errors (never masked) */ |
7995c64e JP |
98 | #define BNX2X_ERR(__fmt, __args...) \ |
99 | do { \ | |
100 | pr_err("[%s:%d(%s)]" __fmt, \ | |
101 | __func__, __LINE__, \ | |
102 | bp->dev ? (bp->dev->name) : "?", \ | |
103 | ##__args); \ | |
cdaa7cb8 VZ |
104 | } while (0) |
105 | ||
106 | #define BNX2X_ERROR(__fmt, __args...) do { \ | |
107 | pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ | |
108 | } while (0) | |
109 | ||
f1410647 | 110 | |
a2fbb9ea | 111 | /* before we have a dev->name use dev_info() */ |
7995c64e JP |
112 | #define BNX2X_DEV_INFO(__fmt, __args...) \ |
113 | do { \ | |
114 | if (netif_msg_probe(bp)) \ | |
115 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
116 | } while (0) | |
a2fbb9ea | 117 | |
619c5cb6 VZ |
118 | #define BNX2X_MAC_FMT "%pM" |
119 | #define BNX2X_MAC_PRN_LIST(mac) (mac) | |
120 | ||
a2fbb9ea ET |
121 | |
122 | #ifdef BNX2X_STOP_ON_ERROR | |
6383c0b3 | 123 | void bnx2x_int_disable(struct bnx2x *bp); |
a2fbb9ea ET |
124 | #define bnx2x_panic() do { \ |
125 | bp->panic = 1; \ | |
126 | BNX2X_ERR("driver assert\n"); \ | |
34f80b04 | 127 | bnx2x_int_disable(bp); \ |
a2fbb9ea ET |
128 | bnx2x_panic_dump(bp); \ |
129 | } while (0) | |
130 | #else | |
131 | #define bnx2x_panic() do { \ | |
e3553b29 | 132 | bp->panic = 1; \ |
a2fbb9ea ET |
133 | BNX2X_ERR("driver assert\n"); \ |
134 | bnx2x_panic_dump(bp); \ | |
135 | } while (0) | |
136 | #endif | |
137 | ||
523224a3 | 138 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
6e30dd4e | 139 | #define bnx2x_uc_addr(ha) ((ha)->addr) |
a2fbb9ea | 140 | |
34f80b04 EG |
141 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
142 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
143 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 144 | |
a2fbb9ea | 145 | |
523224a3 | 146 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
a2fbb9ea | 147 | |
34f80b04 EG |
148 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
149 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
523224a3 | 150 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
34f80b04 EG |
151 | |
152 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 153 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 154 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 155 | |
34f80b04 EG |
156 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
157 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 158 | |
c18487ee YR |
159 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
160 | do { \ | |
161 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 162 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
163 | } while (0) |
164 | ||
34f80b04 | 165 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 166 | do { \ |
573f2035 | 167 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
168 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
169 | offset, len32); \ | |
170 | } while (0) | |
171 | ||
523224a3 DK |
172 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
173 | REG_WR_DMAE(bp, offset, valp, len32) | |
174 | ||
3359fced | 175 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
176 | do { \ |
177 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
178 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
179 | } while (0) | |
180 | ||
34f80b04 EG |
181 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
182 | offsetof(struct shmem_region, field)) | |
183 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
184 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 185 | |
2691d51d EG |
186 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
187 | offsetof(struct shmem2_region, field)) | |
188 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
189 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
523224a3 DK |
190 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
191 | offsetof(struct mf_cfg, field)) | |
f85582f8 | 192 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
f2e0899f | 193 | offsetof(struct mf2_cfg, field)) |
2691d51d | 194 | |
523224a3 DK |
195 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
196 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ | |
197 | MF_CFG_ADDR(bp, field), (val)) | |
f2e0899f | 198 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
f85582f8 | 199 | |
f2e0899f DK |
200 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
201 | (SHMEM2_RD((bp), size) > \ | |
202 | offsetof(struct shmem2_region, field))) | |
72fd0718 | 203 | |
345b5d52 | 204 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 205 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 206 | |
523224a3 DK |
207 | /* SP SB indices */ |
208 | ||
209 | /* General SP events - stats query, cfc delete, etc */ | |
210 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
211 | ||
212 | /* EQ completions */ | |
213 | #define HC_SP_INDEX_EQ_CONS 7 | |
214 | ||
ec6ba945 VZ |
215 | /* FCoE L2 connection completions */ |
216 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 | |
217 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 | |
523224a3 DK |
218 | /* iSCSI L2 */ |
219 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
220 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
221 | ||
ec6ba945 VZ |
222 | /* Special clients parameters */ |
223 | ||
224 | /* SB indices */ | |
225 | /* FCoE L2 */ | |
226 | #define BNX2X_FCOE_L2_RX_INDEX \ | |
227 | (&bp->def_status_blk->sp_sb.\ | |
228 | index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) | |
229 | ||
230 | #define BNX2X_FCOE_L2_TX_INDEX \ | |
231 | (&bp->def_status_blk->sp_sb.\ | |
232 | index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) | |
233 | ||
523224a3 DK |
234 | /** |
235 | * CIDs and CLIDs: | |
236 | * CLIDs below is a CLID for func 0, then the CLID for other | |
237 | * functions will be calculated by the formula: | |
238 | * | |
239 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X | |
240 | * | |
241 | */ | |
242 | /* iSCSI L2 */ | |
619c5cb6 | 243 | #define BNX2X_ISCSI_ETH_CL_ID_IDX 1 |
6383c0b3 | 244 | #define BNX2X_ISCSI_ETH_CID 49 |
523224a3 | 245 | |
ec6ba945 | 246 | /* FCoE L2 */ |
619c5cb6 | 247 | #define BNX2X_FCOE_ETH_CL_ID_IDX 2 |
6383c0b3 | 248 | #define BNX2X_FCOE_ETH_CID 50 |
ec6ba945 | 249 | |
523224a3 DK |
250 | /** Additional rings budgeting */ |
251 | #ifdef BCM_CNIC | |
6383c0b3 AE |
252 | #define CNIC_PRESENT 1 |
253 | #define FCOE_PRESENT 1 | |
523224a3 | 254 | #else |
6383c0b3 AE |
255 | #define CNIC_PRESENT 0 |
256 | #define FCOE_PRESENT 0 | |
523224a3 | 257 | #endif /* BCM_CNIC */ |
6383c0b3 | 258 | #define NON_ETH_CONTEXT_USE (FCOE_PRESENT) |
523224a3 | 259 | |
72fd0718 VZ |
260 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
261 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
262 | ||
523224a3 DK |
263 | #define SM_RX_ID 0 |
264 | #define SM_TX_ID 1 | |
a2fbb9ea | 265 | |
6383c0b3 AE |
266 | /* defines for multiple tx priority indices */ |
267 | #define FIRST_TX_ONLY_COS_INDEX 1 | |
268 | #define FIRST_TX_COS_INDEX 0 | |
269 | ||
270 | /* defines for decodeing the fastpath index and the cos index out of the | |
271 | * transmission queue index | |
272 | */ | |
273 | #define MAX_TXQS_PER_COS FP_SB_MAX_E1x | |
274 | ||
275 | #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) | |
276 | #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) | |
277 | ||
278 | /* rules for calculating the cids of tx-only connections */ | |
279 | #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) | |
280 | #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) | |
281 | ||
282 | /* fp index inside class of service range */ | |
283 | #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) | |
284 | ||
285 | /* | |
286 | * 0..15 eth cos0 | |
287 | * 16..31 eth cos1 if applicable | |
288 | * 32..47 eth cos2 If applicable | |
289 | * fcoe queue follows eth queues (16, 32, 48 depending on cos) | |
290 | */ | |
291 | #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) | |
292 | #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) | |
a2fbb9ea | 293 | |
6383c0b3 | 294 | /* fast path */ |
a2fbb9ea | 295 | struct sw_rx_bd { |
34f80b04 | 296 | struct sk_buff *skb; |
1a983142 | 297 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
298 | }; |
299 | ||
300 | struct sw_tx_bd { | |
34f80b04 EG |
301 | struct sk_buff *skb; |
302 | u16 first_bd; | |
ca00392c EG |
303 | u8 flags; |
304 | /* Set on the first BD descriptor when there is a split BD */ | |
305 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
306 | }; |
307 | ||
7a9b2557 VZ |
308 | struct sw_rx_page { |
309 | struct page *page; | |
1a983142 | 310 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
311 | }; |
312 | ||
ca00392c EG |
313 | union db_prod { |
314 | struct doorbell_set_prod data; | |
315 | u32 raw; | |
316 | }; | |
317 | ||
7a9b2557 VZ |
318 | |
319 | /* MC hsi */ | |
619c5cb6 VZ |
320 | #define BCM_PAGE_SHIFT 12 |
321 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
322 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
7a9b2557 VZ |
323 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
324 | ||
619c5cb6 VZ |
325 | #define PAGES_PER_SGE_SHIFT 0 |
326 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
327 | #define SGE_PAGE_SIZE PAGE_SIZE | |
328 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
329 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) | |
7a9b2557 VZ |
330 | |
331 | /* SGE ring related macros */ | |
619c5cb6 | 332 | #define NUM_RX_SGE_PAGES 2 |
7a9b2557 | 333 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
619c5cb6 | 334 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) |
33471629 | 335 | /* RX_SGE_CNT is promised to be a power of 2 */ |
619c5cb6 VZ |
336 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
337 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
338 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
7a9b2557 VZ |
339 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ |
340 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | |
619c5cb6 VZ |
341 | #define RX_SGE(x) ((x) & MAX_RX_SGE) |
342 | ||
343 | /* Manipulate a bit vector defined as an array of u64 */ | |
7a9b2557 | 344 | |
7a9b2557 | 345 | /* Number of bits in one sge_mask array element */ |
619c5cb6 VZ |
346 | #define BIT_VEC64_ELEM_SZ 64 |
347 | #define BIT_VEC64_ELEM_SHIFT 6 | |
348 | #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) | |
349 | ||
350 | ||
351 | #define __BIT_VEC64_SET_BIT(el, bit) \ | |
352 | do { \ | |
353 | el = ((el) | ((u64)0x1 << (bit))); \ | |
354 | } while (0) | |
355 | ||
356 | #define __BIT_VEC64_CLEAR_BIT(el, bit) \ | |
357 | do { \ | |
358 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
359 | } while (0) | |
360 | ||
361 | ||
362 | #define BIT_VEC64_SET_BIT(vec64, idx) \ | |
363 | __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
364 | (idx) & BIT_VEC64_ELEM_MASK) | |
365 | ||
366 | #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ | |
367 | __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
368 | (idx) & BIT_VEC64_ELEM_MASK) | |
369 | ||
370 | #define BIT_VEC64_TEST_BIT(vec64, idx) \ | |
371 | (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ | |
372 | ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) | |
7a9b2557 VZ |
373 | |
374 | /* Creates a bitmask of all ones in less significant bits. | |
375 | idx - index of the most significant bit in the created mask */ | |
619c5cb6 VZ |
376 | #define BIT_VEC64_ONES_MASK(idx) \ |
377 | (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) | |
378 | #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) | |
379 | ||
380 | /*******************************************************/ | |
381 | ||
382 | ||
7a9b2557 VZ |
383 | |
384 | /* Number of u64 elements in SGE mask array */ | |
385 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ | |
619c5cb6 | 386 | BIT_VEC64_ELEM_SZ) |
7a9b2557 VZ |
387 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
388 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
389 | ||
523224a3 DK |
390 | union host_hc_status_block { |
391 | /* pointer to fp status block e1x */ | |
392 | struct host_hc_status_block_e1x *e1x_sb; | |
f2e0899f DK |
393 | /* pointer to fp status block e2 */ |
394 | struct host_hc_status_block_e2 *e2_sb; | |
523224a3 | 395 | }; |
7a9b2557 | 396 | |
619c5cb6 VZ |
397 | struct bnx2x_agg_info { |
398 | /* | |
399 | * First aggregation buffer is an skb, the following - are pages. | |
400 | * We will preallocate the skbs for each aggregation when | |
401 | * we open the interface and will replace the BD at the consumer | |
402 | * with this one when we receive the TPA_START CQE in order to | |
403 | * keep the Rx BD ring consistent. | |
404 | */ | |
405 | struct sw_rx_bd first_buf; | |
406 | u8 tpa_state; | |
407 | #define BNX2X_TPA_START 1 | |
408 | #define BNX2X_TPA_STOP 2 | |
409 | #define BNX2X_TPA_ERROR 3 | |
410 | u8 placement_offset; | |
411 | u16 parsing_flags; | |
412 | u16 vlan_tag; | |
413 | u16 len_on_bd; | |
414 | }; | |
415 | ||
416 | #define Q_STATS_OFFSET32(stat_name) \ | |
417 | (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) | |
418 | ||
6383c0b3 AE |
419 | struct bnx2x_fp_txdata { |
420 | ||
421 | struct sw_tx_bd *tx_buf_ring; | |
422 | ||
423 | union eth_tx_bd_types *tx_desc_ring; | |
424 | dma_addr_t tx_desc_mapping; | |
425 | ||
426 | u32 cid; | |
427 | ||
428 | union db_prod tx_db; | |
429 | ||
430 | u16 tx_pkt_prod; | |
431 | u16 tx_pkt_cons; | |
432 | u16 tx_bd_prod; | |
433 | u16 tx_bd_cons; | |
434 | ||
435 | unsigned long tx_pkt; | |
436 | ||
437 | __le16 *tx_cons_sb; | |
438 | ||
439 | int txq_index; | |
440 | }; | |
441 | ||
a2fbb9ea | 442 | struct bnx2x_fastpath { |
619c5cb6 | 443 | struct bnx2x *bp; /* parent */ |
a2fbb9ea | 444 | |
d6214d7a | 445 | #define BNX2X_NAPI_WEIGHT 128 |
34f80b04 | 446 | struct napi_struct napi; |
f85582f8 | 447 | union host_hc_status_block status_blk; |
523224a3 DK |
448 | /* chip independed shortcuts into sb structure */ |
449 | __le16 *sb_index_values; | |
450 | __le16 *sb_running_index; | |
451 | /* chip independed shortcut into rx_prods_offset memory */ | |
452 | u32 ustorm_rx_prods_offset; | |
453 | ||
a8c94b91 VZ |
454 | u32 rx_buf_size; |
455 | ||
34f80b04 | 456 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 457 | |
6383c0b3 AE |
458 | u8 max_cos; /* actual number of active tx coses */ |
459 | struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; | |
a2fbb9ea | 460 | |
7a9b2557 VZ |
461 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
462 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
463 | |
464 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 465 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
466 | |
467 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
468 | dma_addr_t rx_comp_mapping; |
469 | ||
7a9b2557 VZ |
470 | /* SGE ring */ |
471 | struct eth_rx_sge *rx_sge_ring; | |
472 | dma_addr_t rx_sge_mapping; | |
473 | ||
474 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
475 | ||
619c5cb6 | 476 | u32 cid; |
34f80b04 | 477 | |
6383c0b3 AE |
478 | __le16 fp_hc_idx; |
479 | ||
f85582f8 DK |
480 | u8 index; /* number in fp array */ |
481 | u8 cl_id; /* eth client id */ | |
523224a3 DK |
482 | u8 cl_qzone_id; |
483 | u8 fw_sb_id; /* status block number in FW */ | |
484 | u8 igu_sb_id; /* status block number in HW */ | |
34f80b04 EG |
485 | |
486 | u16 rx_bd_prod; | |
487 | u16 rx_bd_cons; | |
488 | u16 rx_comp_prod; | |
489 | u16 rx_comp_cons; | |
7a9b2557 VZ |
490 | u16 rx_sge_prod; |
491 | /* The last maximal completed SGE */ | |
492 | u16 last_max_sge; | |
4781bfad | 493 | __le16 *rx_cons_sb; |
6383c0b3 | 494 | unsigned long rx_pkt, |
66e855f3 | 495 | rx_calls; |
ab6ad5a4 | 496 | |
7a9b2557 | 497 | /* TPA related */ |
619c5cb6 | 498 | struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; |
7a9b2557 VZ |
499 | u8 disable_tpa; |
500 | #ifdef BNX2X_STOP_ON_ERROR | |
501 | u64 tpa_queue_used; | |
502 | #endif | |
a2fbb9ea | 503 | |
619c5cb6 VZ |
504 | struct tstorm_per_queue_stats old_tclient; |
505 | struct ustorm_per_queue_stats old_uclient; | |
506 | struct xstorm_per_queue_stats old_xclient; | |
de832a55 EG |
507 | struct bnx2x_eth_q_stats eth_q_stats; |
508 | ||
ca00392c EG |
509 | /* The size is calculated using the following: |
510 | sizeof name field from netdev structure + | |
511 | 4 ('-Xx-' string) + | |
512 | 4 (for the digits and to make it DWORD aligned) */ | |
513 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
514 | char name[FP_NAME_SIZE]; | |
619c5cb6 VZ |
515 | |
516 | /* MACs object */ | |
517 | struct bnx2x_vlan_mac_obj mac_obj; | |
518 | ||
519 | /* Queue State object */ | |
520 | struct bnx2x_queue_sp_obj q_obj; | |
521 | ||
a2fbb9ea ET |
522 | }; |
523 | ||
34f80b04 | 524 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
a8c94b91 VZ |
525 | |
526 | /* Use 2500 as a mini-jumbo MTU for FCoE */ | |
527 | #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 | |
528 | ||
619c5cb6 | 529 | /* FCoE L2 `fastpath' entry is right after the eth entries */ |
ec6ba945 VZ |
530 | #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) |
531 | #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) | |
532 | #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) | |
6383c0b3 AE |
533 | #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ |
534 | txdata[FIRST_TX_COS_INDEX].var) | |
619c5cb6 VZ |
535 | |
536 | ||
6383c0b3 AE |
537 | #define IS_ETH_FP(fp) (fp->index < \ |
538 | BNX2X_NUM_ETH_QUEUES(fp->bp)) | |
619c5cb6 | 539 | #ifdef BCM_CNIC |
ec6ba945 VZ |
540 | #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) |
541 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) | |
542 | #else | |
543 | #define IS_FCOE_FP(fp) false | |
544 | #define IS_FCOE_IDX(idx) false | |
545 | #endif | |
7a9b2557 VZ |
546 | |
547 | ||
548 | /* MC hsi */ | |
619c5cb6 VZ |
549 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ |
550 | #define RX_COPY_THRESH 92 | |
7a9b2557 | 551 | |
619c5cb6 | 552 | #define NUM_TX_RINGS 16 |
ca00392c | 553 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
619c5cb6 VZ |
554 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
555 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
556 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
557 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
7a9b2557 VZ |
558 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
559 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
619c5cb6 VZ |
560 | #define TX_BD(x) ((x) & MAX_TX_BD) |
561 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
7a9b2557 VZ |
562 | |
563 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
619c5cb6 | 564 | #define NUM_RX_RINGS 8 |
7a9b2557 | 565 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
619c5cb6 VZ |
566 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) |
567 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
568 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
569 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
570 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
571 | #define MIN_RX_AVAIL 128 | |
572 | ||
573 | #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ | |
574 | ETH_MIN_RX_CQES_WITH_TPA_E1 : \ | |
575 | ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) | |
576 | #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA | |
577 | #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) | |
578 | #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ | |
579 | MIN_RX_AVAIL)) | |
580 | ||
7a9b2557 VZ |
581 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
582 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
619c5cb6 | 583 | #define RX_BD(x) ((x) & MAX_RX_BD) |
7a9b2557 | 584 | |
619c5cb6 VZ |
585 | /* |
586 | * As long as CQE is X times bigger than BD entry we have to allocate X times | |
587 | * more pages for CQ ring in order to keep it balanced with BD ring | |
588 | */ | |
589 | #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) | |
590 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) | |
7a9b2557 | 591 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
619c5cb6 VZ |
592 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) |
593 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
594 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
595 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
7a9b2557 VZ |
596 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
597 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
619c5cb6 | 598 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
7a9b2557 VZ |
599 | |
600 | ||
33471629 | 601 | /* This is needed for determining of last_max */ |
619c5cb6 VZ |
602 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
603 | #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) | |
7a9b2557 | 604 | |
7a9b2557 | 605 | |
619c5cb6 VZ |
606 | #define BNX2X_SWCID_SHIFT 17 |
607 | #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) | |
7a9b2557 VZ |
608 | |
609 | /* used on a CID received from the HW */ | |
619c5cb6 | 610 | #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) |
7a9b2557 VZ |
611 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ |
612 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
613 | ||
bb2a0f7a YG |
614 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
615 | le32_to_cpu((bd)->addr_lo)) | |
616 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
617 | ||
523224a3 DK |
618 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
619 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ | |
619c5cb6 VZ |
620 | #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) |
621 | #error "Min DB doorbell stride is 8" | |
622 | #endif | |
7a9b2557 VZ |
623 | #define DPM_TRIGER_TYPE 0x40 |
624 | #define DOORBELL(bp, cid, val) \ | |
625 | do { \ | |
523224a3 | 626 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
7a9b2557 VZ |
627 | DPM_TRIGER_TYPE); \ |
628 | } while (0) | |
629 | ||
630 | ||
631 | /* TX CSUM helpers */ | |
632 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
633 | skb->csum_offset) | |
634 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
635 | skb->csum_offset)) | |
636 | ||
637 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
638 | ||
639 | #define XMIT_PLAIN 0 | |
640 | #define XMIT_CSUM_V4 0x1 | |
641 | #define XMIT_CSUM_V6 0x2 | |
642 | #define XMIT_CSUM_TCP 0x4 | |
643 | #define XMIT_GSO_V4 0x8 | |
644 | #define XMIT_GSO_V6 0x10 | |
645 | ||
646 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
647 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
648 | ||
649 | ||
34f80b04 | 650 | /* stuff added to make the code fit 80Col */ |
619c5cb6 VZ |
651 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
652 | #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) | |
653 | #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) | |
654 | #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) | |
655 | #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) | |
7a9b2557 | 656 | |
1adcd8be EG |
657 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
658 | ||
659 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
660 | (!((cqe)->fast_path_cqe.status_flags & \ | |
661 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
662 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
663 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
664 | ||
665 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
666 | (!((cqe)->fast_path_cqe.status_flags & \ | |
667 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
668 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
669 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
670 | ||
671 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
672 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 | 673 | |
052a38e0 EG |
674 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
675 | (((le16_to_cpu(flags) & \ | |
676 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
677 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
678 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 679 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 680 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 681 | |
619c5cb6 VZ |
682 | |
683 | #define FP_USB_FUNC_OFF \ | |
684 | offsetof(struct cstorm_status_block_u, func) | |
685 | #define FP_CSB_FUNC_OFF \ | |
686 | offsetof(struct cstorm_status_block_c, func) | |
687 | ||
688 | #define HC_INDEX_TOE_RX_CQ_CONS 0 /* Formerly Ustorm TOE CQ index */ | |
689 | /* (HC_INDEX_U_TOE_RX_CQ_CONS) */ | |
690 | #define HC_INDEX_ETH_RX_CQ_CONS 1 /* Formerly Ustorm ETH CQ index */ | |
691 | /* (HC_INDEX_U_ETH_RX_CQ_CONS) */ | |
692 | #define HC_INDEX_ETH_RX_BD_CONS 2 /* Formerly Ustorm ETH BD index */ | |
693 | /* (HC_INDEX_U_ETH_RX_BD_CONS) */ | |
694 | ||
695 | #define HC_INDEX_TOE_TX_CQ_CONS 4 /* Formerly Cstorm TOE CQ index */ | |
696 | /* (HC_INDEX_C_TOE_TX_CQ_CONS) */ | |
6383c0b3 AE |
697 | #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 /* Formerly Cstorm ETH CQ index */ |
698 | /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ | |
699 | #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 /* Formerly Cstorm ETH CQ index */ | |
700 | /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ | |
701 | #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 /* Formerly Cstorm ETH CQ index */ | |
619c5cb6 VZ |
702 | /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ |
703 | ||
6383c0b3 AE |
704 | #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 |
705 | ||
a2fbb9ea | 706 | |
34f80b04 | 707 | #define BNX2X_RX_SB_INDEX \ |
619c5cb6 | 708 | (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) |
a2fbb9ea | 709 | |
6383c0b3 AE |
710 | #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 |
711 | ||
712 | #define BNX2X_TX_SB_INDEX_COS0 \ | |
713 | (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) | |
7a9b2557 VZ |
714 | |
715 | /* end of fast path */ | |
716 | ||
34f80b04 | 717 | /* common */ |
a2fbb9ea | 718 | |
34f80b04 | 719 | struct bnx2x_common { |
a2fbb9ea | 720 | |
ad8d3948 | 721 | u32 chip_id; |
a2fbb9ea | 722 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 723 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 724 | |
34f80b04 | 725 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
726 | #define CHIP_NUM_57710 0x164e |
727 | #define CHIP_NUM_57711 0x164f | |
728 | #define CHIP_NUM_57711E 0x1650 | |
f2e0899f | 729 | #define CHIP_NUM_57712 0x1662 |
619c5cb6 VZ |
730 | #define CHIP_NUM_57712_MF 0x1663 |
731 | #define CHIP_NUM_57713 0x1651 | |
732 | #define CHIP_NUM_57713E 0x1652 | |
733 | #define CHIP_NUM_57800 0x168a | |
734 | #define CHIP_NUM_57800_MF 0x16a5 | |
735 | #define CHIP_NUM_57810 0x168e | |
736 | #define CHIP_NUM_57810_MF 0x16ae | |
737 | #define CHIP_NUM_57840 0x168d | |
738 | #define CHIP_NUM_57840_MF 0x16ab | |
ad8d3948 EG |
739 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
740 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
741 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
f2e0899f | 742 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
619c5cb6 VZ |
743 | #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) |
744 | #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) | |
745 | #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) | |
746 | #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) | |
747 | #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) | |
748 | #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) | |
749 | #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) | |
ad8d3948 EG |
750 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
751 | CHIP_IS_57711E(bp)) | |
f2e0899f | 752 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
619c5cb6 VZ |
753 | CHIP_IS_57712_MF(bp)) |
754 | #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ | |
755 | CHIP_IS_57800_MF(bp) || \ | |
756 | CHIP_IS_57810(bp) || \ | |
757 | CHIP_IS_57810_MF(bp) || \ | |
758 | CHIP_IS_57840(bp) || \ | |
759 | CHIP_IS_57840_MF(bp)) | |
f2e0899f | 760 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) |
619c5cb6 VZ |
761 | #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) |
762 | #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) | |
763 | ||
764 | #define CHIP_REV_SHIFT 12 | |
765 | #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) | |
766 | #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) | |
767 | #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) | |
768 | #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) | |
ad8d3948 | 769 | /* assume maximum 5 revisions */ |
619c5cb6 | 770 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) |
ad8d3948 EG |
771 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ |
772 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 773 | !(CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
774 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ |
775 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 776 | (CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
777 | |
778 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
779 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
780 | ||
34f80b04 EG |
781 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
782 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
619c5cb6 VZ |
783 | #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ |
784 | (CHIP_REV_SHIFT + 1)) \ | |
785 | << CHIP_REV_SHIFT) | |
786 | #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ | |
787 | CHIP_REV_SIM(bp) :\ | |
788 | CHIP_REV_VAL(bp)) | |
789 | #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ | |
790 | (CHIP_REV(bp) == CHIP_REV_Bx)) | |
791 | #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ | |
792 | (CHIP_REV(bp) == CHIP_REV_Ax)) | |
a2fbb9ea | 793 | |
34f80b04 | 794 | int flash_size; |
754a2f52 DK |
795 | #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
796 | #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 | |
797 | #define BNX2X_NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 798 | |
34f80b04 | 799 | u32 shmem_base; |
2691d51d | 800 | u32 shmem2_base; |
523224a3 | 801 | u32 mf_cfg_base; |
f2e0899f | 802 | u32 mf2_cfg_base; |
34f80b04 EG |
803 | |
804 | u32 hw_config; | |
c18487ee | 805 | |
34f80b04 | 806 | u32 bc_ver; |
523224a3 DK |
807 | |
808 | u8 int_block; | |
809 | #define INT_BLOCK_HC 0 | |
f2e0899f DK |
810 | #define INT_BLOCK_IGU 1 |
811 | #define INT_BLOCK_MODE_NORMAL 0 | |
812 | #define INT_BLOCK_MODE_BW_COMP 2 | |
813 | #define CHIP_INT_MODE_IS_NBC(bp) \ | |
619c5cb6 | 814 | (!CHIP_IS_E1x(bp) && \ |
f2e0899f DK |
815 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) |
816 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) | |
817 | ||
523224a3 | 818 | u8 chip_port_mode; |
f2e0899f DK |
819 | #define CHIP_4_PORT_MODE 0x0 |
820 | #define CHIP_2_PORT_MODE 0x1 | |
523224a3 | 821 | #define CHIP_PORT_MODE_NONE 0x2 |
f2e0899f DK |
822 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
823 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) | |
34f80b04 | 824 | }; |
c18487ee | 825 | |
f2e0899f DK |
826 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
827 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
828 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
34f80b04 EG |
829 | |
830 | /* end of common */ | |
831 | ||
832 | /* port */ | |
833 | ||
834 | struct bnx2x_port { | |
835 | u32 pmf; | |
c18487ee | 836 | |
a22f0788 | 837 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 838 | |
a22f0788 | 839 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
840 | /* link settings - missing defines */ |
841 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
842 | ||
a22f0788 | 843 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 844 | /* link settings - missing defines */ |
34f80b04 | 845 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 846 | |
34f80b04 | 847 | u32 phy_addr; |
c18487ee YR |
848 | |
849 | /* used to synchronize phy accesses */ | |
850 | struct mutex phy_mutex; | |
46c6a674 | 851 | int need_hw_lock; |
c18487ee | 852 | |
34f80b04 | 853 | u32 port_stx; |
a2fbb9ea | 854 | |
34f80b04 EG |
855 | struct nig_stats old_nig_stats; |
856 | }; | |
a2fbb9ea | 857 | |
34f80b04 EG |
858 | /* end of port */ |
859 | ||
619c5cb6 VZ |
860 | #define STATS_OFFSET32(stat_name) \ |
861 | (offsetof(struct bnx2x_eth_stats, stat_name) / 4) | |
bb2a0f7a | 862 | |
619c5cb6 VZ |
863 | /* slow path */ |
864 | ||
865 | /* slow path work-queue */ | |
866 | extern struct workqueue_struct *bnx2x_wq; | |
867 | ||
868 | #define BNX2X_MAX_NUM_OF_VFS 64 | |
523224a3 | 869 | #define BNX2X_VF_ID_INVALID 0xFF |
34f80b04 | 870 | |
523224a3 DK |
871 | /* |
872 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
873 | * control by the number of fast-path status blocks supported by the | |
874 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
875 | * status block represents an independent interrupts context that can | |
876 | * serve a regular L2 networking queue. However special L2 queues such | |
877 | * as the FCoE queue do not require a FP-SB and other components like | |
878 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
879 | * | |
880 | * If the maximum number of FP-SB available is X then: | |
881 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
882 | * regular L2 queues is Y=X-1 | |
883 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) | |
884 | * c. If the FCoE L2 queue is supported the actual number of L2 queues | |
885 | * is Y+1 | |
886 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
887 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
888 | * FP interrupt context for the CNIC). | |
889 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
890 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. | |
891 | */ | |
892 | ||
619c5cb6 VZ |
893 | /* fast-path interrupt contexts E1x */ |
894 | #define FP_SB_MAX_E1x 16 | |
895 | /* fast-path interrupt contexts E2 */ | |
896 | #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 | |
523224a3 | 897 | |
34f80b04 EG |
898 | union cdu_context { |
899 | struct eth_context eth; | |
900 | char pad[1024]; | |
901 | }; | |
902 | ||
523224a3 DK |
903 | /* CDU host DB constants */ |
904 | #define CDU_ILT_PAGE_SZ_HW 3 | |
6383c0b3 | 905 | #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ |
523224a3 DK |
906 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
907 | ||
908 | #ifdef BCM_CNIC | |
909 | #define CNIC_ISCSI_CID_MAX 256 | |
ec6ba945 VZ |
910 | #define CNIC_FCOE_CID_MAX 2048 |
911 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) | |
523224a3 DK |
912 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
913 | #endif | |
914 | ||
619c5cb6 VZ |
915 | #define QM_ILT_PAGE_SZ_HW 0 |
916 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
917 | #define QM_CID_ROUND 1024 |
918 | ||
919 | #ifdef BCM_CNIC | |
920 | /* TM (timers) host DB constants */ | |
619c5cb6 VZ |
921 | #define TM_ILT_PAGE_SZ_HW 0 |
922 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
923 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ |
924 | #define TM_CONN_NUM 1024 | |
925 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
926 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
927 | ||
928 | /* SRC (Searcher) host DB constants */ | |
619c5cb6 VZ |
929 | #define SRC_ILT_PAGE_SZ_HW 0 |
930 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
931 | #define SRC_HASH_BITS 10 |
932 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
933 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
934 | #define SRC_T2_SZ SRC_ILT_SZ | |
935 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
619c5cb6 | 936 | |
523224a3 DK |
937 | #endif |
938 | ||
619c5cb6 | 939 | #define MAX_DMAE_C 8 |
34f80b04 EG |
940 | |
941 | /* DMA memory not used in fastpath */ | |
942 | struct bnx2x_slowpath { | |
619c5cb6 VZ |
943 | union { |
944 | struct mac_configuration_cmd e1x; | |
945 | struct eth_classify_rules_ramrod_data e2; | |
946 | } mac_rdata; | |
947 | ||
948 | ||
949 | union { | |
950 | struct tstorm_eth_mac_filter_config e1x; | |
951 | struct eth_filter_rules_ramrod_data e2; | |
952 | } rx_mode_rdata; | |
953 | ||
954 | union { | |
955 | struct mac_configuration_cmd e1; | |
956 | struct eth_multicast_rules_ramrod_data e2; | |
957 | } mcast_rdata; | |
958 | ||
959 | struct eth_rss_update_ramrod_data rss_rdata; | |
960 | ||
961 | /* Queue State related ramrods are always sent under rtnl_lock */ | |
962 | union { | |
963 | struct client_init_ramrod_data init_data; | |
964 | struct client_update_ramrod_data update_data; | |
965 | } q_rdata; | |
966 | ||
967 | union { | |
968 | struct function_start_data func_start; | |
6debea87 DK |
969 | /* pfc configuration for DCBX ramrod */ |
970 | struct flow_control_configuration pfc_config; | |
619c5cb6 | 971 | } func_rdata; |
34f80b04 EG |
972 | |
973 | /* used by dmae command executer */ | |
974 | struct dmae_command dmae[MAX_DMAE_C]; | |
975 | ||
bb2a0f7a YG |
976 | u32 stats_comp; |
977 | union mac_stats mac_stats; | |
978 | struct nig_stats nig_stats; | |
979 | struct host_port_stats port_stats; | |
980 | struct host_func_stats func_stats; | |
6fe49bb9 | 981 | struct host_func_stats func_stats_base; |
34f80b04 EG |
982 | |
983 | u32 wb_comp; | |
34f80b04 EG |
984 | u32 wb_data[4]; |
985 | }; | |
986 | ||
987 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
988 | #define bnx2x_sp_mapping(bp, var) \ | |
989 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
990 | ||
991 | ||
992 | /* attn group wiring */ | |
993 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
994 | ||
995 | struct attn_route { | |
619c5cb6 | 996 | u32 sig[5]; |
34f80b04 EG |
997 | }; |
998 | ||
523224a3 DK |
999 | struct iro { |
1000 | u32 base; | |
1001 | u16 m1; | |
1002 | u16 m2; | |
1003 | u16 m3; | |
1004 | u16 size; | |
1005 | }; | |
1006 | ||
1007 | struct hw_context { | |
1008 | union cdu_context *vcxt; | |
1009 | dma_addr_t cxt_mapping; | |
1010 | size_t size; | |
1011 | }; | |
1012 | ||
1013 | /* forward */ | |
1014 | struct bnx2x_ilt; | |
1015 | ||
c9ee9206 VZ |
1016 | |
1017 | enum bnx2x_recovery_state { | |
72fd0718 VZ |
1018 | BNX2X_RECOVERY_DONE, |
1019 | BNX2X_RECOVERY_INIT, | |
1020 | BNX2X_RECOVERY_WAIT, | |
c9ee9206 VZ |
1021 | BNX2X_RECOVERY_FAILED |
1022 | }; | |
72fd0718 | 1023 | |
619c5cb6 | 1024 | /* |
523224a3 DK |
1025 | * Event queue (EQ or event ring) MC hsi |
1026 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 | |
1027 | */ | |
1028 | #define NUM_EQ_PAGES 1 | |
1029 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) | |
1030 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
1031 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
1032 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
1033 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
1034 | ||
1035 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
1036 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ | |
1037 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
1038 | ||
1039 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
1040 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
1041 | ||
1042 | #define BNX2X_EQ_INDEX \ | |
1043 | (&bp->def_status_blk->sp_sb.\ | |
1044 | index_values[HC_SP_INDEX_EQ_CONS]) | |
1045 | ||
2ae17f66 VZ |
1046 | /* This is a data that will be used to create a link report message. |
1047 | * We will keep the data used for the last link report in order | |
1048 | * to prevent reporting the same link parameters twice. | |
1049 | */ | |
1050 | struct bnx2x_link_report_data { | |
1051 | u16 line_speed; /* Effective line speed */ | |
1052 | unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ | |
1053 | }; | |
1054 | ||
1055 | enum { | |
1056 | BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ | |
1057 | BNX2X_LINK_REPORT_LINK_DOWN, | |
1058 | BNX2X_LINK_REPORT_RX_FC_ON, | |
1059 | BNX2X_LINK_REPORT_TX_FC_ON, | |
1060 | }; | |
1061 | ||
619c5cb6 VZ |
1062 | enum { |
1063 | BNX2X_PORT_QUERY_IDX, | |
1064 | BNX2X_PF_QUERY_IDX, | |
1065 | BNX2X_FIRST_QUEUE_QUERY_IDX, | |
1066 | }; | |
1067 | ||
1068 | struct bnx2x_fw_stats_req { | |
1069 | struct stats_query_header hdr; | |
1070 | struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; | |
1071 | }; | |
1072 | ||
1073 | struct bnx2x_fw_stats_data { | |
1074 | struct stats_counter storm_counters; | |
1075 | struct per_port_stats port; | |
1076 | struct per_pf_stats pf; | |
1077 | struct per_queue_stats queue_stats[1]; | |
1078 | }; | |
1079 | ||
7be08a72 AE |
1080 | /* Public slow path states */ |
1081 | enum { | |
6383c0b3 | 1082 | BNX2X_SP_RTNL_SETUP_TC, |
7be08a72 AE |
1083 | BNX2X_SP_RTNL_TX_TIMEOUT, |
1084 | }; | |
1085 | ||
1086 | ||
34f80b04 EG |
1087 | struct bnx2x { |
1088 | /* Fields used in the tx and intr/napi performance paths | |
1089 | * are grouped together in the beginning of the structure | |
1090 | */ | |
523224a3 | 1091 | struct bnx2x_fastpath *fp; |
34f80b04 EG |
1092 | void __iomem *regview; |
1093 | void __iomem *doorbells; | |
523224a3 | 1094 | u16 db_size; |
34f80b04 | 1095 | |
619c5cb6 VZ |
1096 | u8 pf_num; /* absolute PF number */ |
1097 | u8 pfid; /* per-path PF number */ | |
1098 | int base_fw_ndsb; /**/ | |
1099 | #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) | |
1100 | #define BP_PORT(bp) (bp->pfid & 1) | |
1101 | #define BP_FUNC(bp) (bp->pfid) | |
1102 | #define BP_ABS_FUNC(bp) (bp->pf_num) | |
1103 | #define BP_E1HVN(bp) (bp->pfid >> 1) | |
1104 | #define BP_VN(bp) (BP_E1HVN(bp)) /*remove when approved*/ | |
1105 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) | |
1106 | #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ | |
1107 | BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1)) | |
1108 | ||
34f80b04 EG |
1109 | struct net_device *dev; |
1110 | struct pci_dev *pdev; | |
1111 | ||
619c5cb6 | 1112 | const struct iro *iro_arr; |
523224a3 DK |
1113 | #define IRO (bp->iro_arr) |
1114 | ||
c9ee9206 | 1115 | enum bnx2x_recovery_state recovery_state; |
72fd0718 | 1116 | int is_leader; |
523224a3 | 1117 | struct msix_entry *msix_table; |
34f80b04 EG |
1118 | |
1119 | int tx_ring_size; | |
1120 | ||
523224a3 DK |
1121 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
1122 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
34f80b04 EG |
1123 | #define ETH_MIN_PACKET_SIZE 60 |
1124 | #define ETH_MAX_PACKET_SIZE 1500 | |
1125 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 1126 | |
0f00846d EG |
1127 | /* Max supported alignment is 256 (8 shift) */ |
1128 | #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ | |
1129 | L1_CACHE_SHIFT : 8) | |
619c5cb6 VZ |
1130 | /* FW use 2 Cache lines Alignment for start packet and size */ |
1131 | #define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT) | |
523224a3 | 1132 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
0f00846d | 1133 | |
523224a3 DK |
1134 | struct host_sp_status_block *def_status_blk; |
1135 | #define DEF_SB_IGU_ID 16 | |
1136 | #define DEF_SB_ID HC_SP_SB_ID | |
1137 | __le16 def_idx; | |
4781bfad | 1138 | __le16 def_att_idx; |
34f80b04 EG |
1139 | u32 attn_state; |
1140 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
1141 | |
1142 | /* slow path ring */ | |
1143 | struct eth_spe *spq; | |
1144 | dma_addr_t spq_mapping; | |
1145 | u16 spq_prod_idx; | |
1146 | struct eth_spe *spq_prod_bd; | |
1147 | struct eth_spe *spq_last_bd; | |
4781bfad | 1148 | __le16 *dsb_sp_prod; |
6e30dd4e | 1149 | atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ |
34f80b04 EG |
1150 | /* used to synchronize spq accesses */ |
1151 | spinlock_t spq_lock; | |
1152 | ||
523224a3 DK |
1153 | /* event queue */ |
1154 | union event_ring_elem *eq_ring; | |
1155 | dma_addr_t eq_mapping; | |
1156 | u16 eq_prod; | |
1157 | u16 eq_cons; | |
1158 | __le16 *eq_cons_sb; | |
6e30dd4e | 1159 | atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ |
523224a3 | 1160 | |
619c5cb6 VZ |
1161 | |
1162 | ||
1163 | /* Counter for marking that there is a STAT_QUERY ramrod pending */ | |
1164 | u16 stats_pending; | |
1165 | /* Counter for completed statistics ramrods */ | |
1166 | u16 stats_comp; | |
34f80b04 | 1167 | |
33471629 | 1168 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
1169 | |
1170 | int panic; | |
7995c64e | 1171 | int msg_enable; |
34f80b04 EG |
1172 | |
1173 | u32 flags; | |
619c5cb6 VZ |
1174 | #define PCIX_FLAG (1 << 0) |
1175 | #define PCI_32BIT_FLAG (1 << 1) | |
1176 | #define ONE_PORT_FLAG (1 << 2) | |
1177 | #define NO_WOL_FLAG (1 << 3) | |
1178 | #define USING_DAC_FLAG (1 << 4) | |
1179 | #define USING_MSIX_FLAG (1 << 5) | |
1180 | #define USING_MSI_FLAG (1 << 6) | |
1181 | #define DISABLE_MSI_FLAG (1 << 7) | |
1182 | #define TPA_ENABLE_FLAG (1 << 8) | |
1183 | #define NO_MCP_FLAG (1 << 9) | |
1184 | ||
34f80b04 | 1185 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
619c5cb6 VZ |
1186 | #define MF_FUNC_DIS (1 << 11) |
1187 | #define OWN_CNIC_IRQ (1 << 12) | |
1188 | #define NO_ISCSI_OOO_FLAG (1 << 13) | |
1189 | #define NO_ISCSI_FLAG (1 << 14) | |
1190 | #define NO_FCOE_FLAG (1 << 15) | |
ec6ba945 | 1191 | |
2ba45142 VZ |
1192 | #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) |
1193 | #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) | |
619c5cb6 | 1194 | #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) |
37b091ba | 1195 | |
34f80b04 | 1196 | int pm_cap; |
8d5726c4 | 1197 | int mrrs; |
34f80b04 | 1198 | |
1cf167f2 | 1199 | struct delayed_work sp_task; |
7be08a72 | 1200 | struct delayed_work sp_rtnl_task; |
3deb8167 YR |
1201 | |
1202 | struct delayed_work period_task; | |
34f80b04 | 1203 | struct timer_list timer; |
34f80b04 EG |
1204 | int current_interval; |
1205 | ||
1206 | u16 fw_seq; | |
1207 | u16 fw_drv_pulse_wr_seq; | |
1208 | u32 func_stx; | |
1209 | ||
1210 | struct link_params link_params; | |
1211 | struct link_vars link_vars; | |
2ae17f66 VZ |
1212 | u32 link_cnt; |
1213 | struct bnx2x_link_report_data last_reported_link; | |
1214 | ||
01cd4528 | 1215 | struct mdio_if_info mdio; |
a2fbb9ea | 1216 | |
34f80b04 EG |
1217 | struct bnx2x_common common; |
1218 | struct bnx2x_port port; | |
1219 | ||
8a1c38d1 EG |
1220 | struct cmng_struct_per_port cmng; |
1221 | u32 vn_weight_sum; | |
f2e0899f DK |
1222 | u32 mf_config[E1HVN_MAX]; |
1223 | u32 mf2_config[E2_FUNC_MAX]; | |
619c5cb6 | 1224 | u32 path_has_ovlan; /* E3 */ |
fb3bff17 DK |
1225 | u16 mf_ov; |
1226 | u8 mf_mode; | |
f85582f8 | 1227 | #define IS_MF(bp) (bp->mf_mode != 0) |
0793f83f DK |
1228 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
1229 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) | |
a2fbb9ea | 1230 | |
f1410647 ET |
1231 | u8 wol; |
1232 | ||
34f80b04 | 1233 | int rx_ring_size; |
a2fbb9ea | 1234 | |
34f80b04 EG |
1235 | u16 tx_quick_cons_trip_int; |
1236 | u16 tx_quick_cons_trip; | |
1237 | u16 tx_ticks_int; | |
1238 | u16 tx_ticks; | |
a2fbb9ea | 1239 | |
34f80b04 EG |
1240 | u16 rx_quick_cons_trip_int; |
1241 | u16 rx_quick_cons_trip; | |
1242 | u16 rx_ticks_int; | |
1243 | u16 rx_ticks; | |
cdaa7cb8 VZ |
1244 | /* Maximal coalescing timeout in us */ |
1245 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 1246 | |
34f80b04 | 1247 | u32 lin_cnt; |
a2fbb9ea | 1248 | |
619c5cb6 | 1249 | u16 state; |
356e2385 | 1250 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
1251 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
1252 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 1253 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 1254 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea | 1255 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
619c5cb6 | 1256 | |
34f80b04 EG |
1257 | #define BNX2X_STATE_DIAG 0xe000 |
1258 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 1259 | |
555f6c78 | 1260 | int multi_mode; |
6383c0b3 AE |
1261 | #define BNX2X_MAX_PRIORITY 8 |
1262 | #define BNX2X_MAX_ENTRIES_PER_PRI 16 | |
1263 | #define BNX2X_MAX_COS 3 | |
1264 | #define BNX2X_MAX_TX_COS 2 | |
54b9ddaa | 1265 | int num_queues; |
5d7cd496 | 1266 | int disable_tpa; |
523224a3 | 1267 | |
34f80b04 EG |
1268 | u32 rx_mode; |
1269 | #define BNX2X_RX_MODE_NONE 0 | |
1270 | #define BNX2X_RX_MODE_NORMAL 1 | |
1271 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1272 | #define BNX2X_RX_MODE_PROMISC 3 | |
1273 | #define BNX2X_MAX_MULTICAST 64 | |
a2fbb9ea | 1274 | |
523224a3 DK |
1275 | u8 igu_dsb_id; |
1276 | u8 igu_base_sb; | |
1277 | u8 igu_sb_cnt; | |
34f80b04 | 1278 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 1279 | |
34f80b04 EG |
1280 | struct bnx2x_slowpath *slowpath; |
1281 | dma_addr_t slowpath_mapping; | |
619c5cb6 VZ |
1282 | |
1283 | /* Total number of FW statistics requests */ | |
1284 | u8 fw_stats_num; | |
1285 | ||
1286 | /* | |
1287 | * This is a memory buffer that will contain both statistics | |
1288 | * ramrod request and data. | |
1289 | */ | |
1290 | void *fw_stats; | |
1291 | dma_addr_t fw_stats_mapping; | |
1292 | ||
1293 | /* | |
1294 | * FW statistics request shortcut (points at the | |
1295 | * beginning of fw_stats buffer). | |
1296 | */ | |
1297 | struct bnx2x_fw_stats_req *fw_stats_req; | |
1298 | dma_addr_t fw_stats_req_mapping; | |
1299 | int fw_stats_req_sz; | |
1300 | ||
1301 | /* | |
1302 | * FW statistics data shortcut (points at the begining of | |
1303 | * fw_stats buffer + fw_stats_req_sz). | |
1304 | */ | |
1305 | struct bnx2x_fw_stats_data *fw_stats_data; | |
1306 | dma_addr_t fw_stats_data_mapping; | |
1307 | int fw_stats_data_sz; | |
1308 | ||
523224a3 DK |
1309 | struct hw_context context; |
1310 | ||
1311 | struct bnx2x_ilt *ilt; | |
1312 | #define BP_ILT(bp) ((bp)->ilt) | |
619c5cb6 | 1313 | #define ILT_MAX_LINES 256 |
6383c0b3 AE |
1314 | /* |
1315 | * Maximum supported number of RSS queues: number of IGU SBs minus one that goes | |
1316 | * to CNIC. | |
1317 | */ | |
1318 | #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) | |
523224a3 | 1319 | |
6383c0b3 AE |
1320 | /* |
1321 | * Maximum CID count that might be required by the bnx2x: | |
1322 | * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) | |
1323 | */ | |
1324 | #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ | |
1325 | NON_ETH_CONTEXT_USE + CNIC_PRESENT) | |
1326 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ | |
1327 | ILT_PAGE_CIDS)) | |
1328 | #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) | |
523224a3 DK |
1329 | |
1330 | int qm_cid_count; | |
a2fbb9ea | 1331 | |
a18f5128 EG |
1332 | int dropless_fc; |
1333 | ||
37b091ba MC |
1334 | #ifdef BCM_CNIC |
1335 | u32 cnic_flags; | |
1336 | #define BNX2X_CNIC_FLAG_MAC_SET 1 | |
37b091ba MC |
1337 | void *t2; |
1338 | dma_addr_t t2_mapping; | |
13707f9e | 1339 | struct cnic_ops __rcu *cnic_ops; |
37b091ba MC |
1340 | void *cnic_data; |
1341 | u32 cnic_tag; | |
1342 | struct cnic_eth_dev cnic_eth_dev; | |
523224a3 | 1343 | union host_hc_status_block cnic_sb; |
37b091ba | 1344 | dma_addr_t cnic_sb_mapping; |
37b091ba MC |
1345 | struct eth_spe *cnic_kwq; |
1346 | struct eth_spe *cnic_kwq_prod; | |
1347 | struct eth_spe *cnic_kwq_cons; | |
1348 | struct eth_spe *cnic_kwq_last; | |
1349 | u16 cnic_kwq_pending; | |
1350 | u16 cnic_spq_pending; | |
ec6ba945 | 1351 | u8 fip_mac[ETH_ALEN]; |
619c5cb6 VZ |
1352 | struct mutex cnic_mutex; |
1353 | struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; | |
1354 | ||
1355 | /* Start index of the "special" (CNIC related) L2 cleints */ | |
1356 | u8 cnic_base_cl_id; | |
37b091ba MC |
1357 | #endif |
1358 | ||
ad8d3948 EG |
1359 | int dmae_ready; |
1360 | /* used to synchronize dmae accesses */ | |
6e30dd4e | 1361 | spinlock_t dmae_lock; |
ad8d3948 | 1362 | |
c4ff7cbf EG |
1363 | /* used to protect the FW mail box */ |
1364 | struct mutex fw_mb_mutex; | |
1365 | ||
bb2a0f7a YG |
1366 | /* used to synchronize stats collecting */ |
1367 | int stats_state; | |
a13773a5 VZ |
1368 | |
1369 | /* used for synchronization of concurrent threads statistics handling */ | |
1370 | spinlock_t stats_lock; | |
1371 | ||
bb2a0f7a YG |
1372 | /* used by dmae command loader */ |
1373 | struct dmae_command stats_dmae; | |
1374 | int executer_idx; | |
ad8d3948 | 1375 | |
bb2a0f7a | 1376 | u16 stats_counter; |
bb2a0f7a YG |
1377 | struct bnx2x_eth_stats eth_stats; |
1378 | ||
1379 | struct z_stream_s *strm; | |
1380 | void *gunzip_buf; | |
1381 | dma_addr_t gunzip_mapping; | |
1382 | int gunzip_outlen; | |
ad8d3948 | 1383 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
1384 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
1385 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
1386 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 1387 | |
ab6ad5a4 | 1388 | struct raw_op *init_ops; |
94a78b79 | 1389 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 1390 | u16 *init_ops_offsets; |
94a78b79 | 1391 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 1392 | u32 *init_data; |
619c5cb6 VZ |
1393 | u32 init_mode_flags; |
1394 | #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) | |
94a78b79 | 1395 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
1396 | const u8 *tsem_int_table_data; |
1397 | const u8 *tsem_pram_data; | |
1398 | const u8 *usem_int_table_data; | |
1399 | const u8 *usem_pram_data; | |
1400 | const u8 *xsem_int_table_data; | |
1401 | const u8 *xsem_pram_data; | |
1402 | const u8 *csem_int_table_data; | |
1403 | const u8 *csem_pram_data; | |
573f2035 EG |
1404 | #define INIT_OPS(bp) (bp->init_ops) |
1405 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
1406 | #define INIT_DATA(bp) (bp->init_data) | |
1407 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
1408 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
1409 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
1410 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
1411 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
1412 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
1413 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
1414 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
1415 | ||
619c5cb6 | 1416 | #define PHY_FW_VER_LEN 20 |
34f24c7f | 1417 | char fw_ver[32]; |
ab6ad5a4 | 1418 | const struct firmware *firmware; |
619c5cb6 | 1419 | |
785b9b1a SR |
1420 | /* DCB support on/off */ |
1421 | u16 dcb_state; | |
1422 | #define BNX2X_DCB_STATE_OFF 0 | |
1423 | #define BNX2X_DCB_STATE_ON 1 | |
1424 | ||
1425 | /* DCBX engine mode */ | |
1426 | int dcbx_enabled; | |
1427 | #define BNX2X_DCBX_ENABLED_OFF 0 | |
1428 | #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 | |
1429 | #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 | |
1430 | #define BNX2X_DCBX_ENABLED_INVALID (-1) | |
1431 | ||
1432 | bool dcbx_mode_uset; | |
1433 | ||
e4901dde | 1434 | struct bnx2x_config_dcbx_params dcbx_config_params; |
e4901dde VZ |
1435 | struct bnx2x_dcbx_port_params dcbx_port_params; |
1436 | int dcb_version; | |
1437 | ||
619c5cb6 VZ |
1438 | /* CAM credit pools */ |
1439 | struct bnx2x_credit_pool_obj macs_pool; | |
1440 | ||
1441 | /* RX_MODE object */ | |
1442 | struct bnx2x_rx_mode_obj rx_mode_obj; | |
1443 | ||
1444 | /* MCAST object */ | |
1445 | struct bnx2x_mcast_obj mcast_obj; | |
1446 | ||
1447 | /* RSS configuration object */ | |
1448 | struct bnx2x_rss_config_obj rss_conf_obj; | |
1449 | ||
1450 | /* Function State controlling object */ | |
1451 | struct bnx2x_func_sp_obj func_obj; | |
1452 | ||
1453 | unsigned long sp_state; | |
1454 | ||
7be08a72 AE |
1455 | /* operation indication for the sp_rtnl task */ |
1456 | unsigned long sp_rtnl_state; | |
1457 | ||
619c5cb6 | 1458 | /* DCBX Negotation results */ |
e4901dde VZ |
1459 | struct dcbx_features dcbx_local_feat; |
1460 | u32 dcbx_error; | |
619c5cb6 | 1461 | |
0be6bc62 SR |
1462 | #ifdef BCM_DCBNL |
1463 | struct dcbx_features dcbx_remote_feat; | |
1464 | u32 dcbx_remote_flags; | |
1465 | #endif | |
e3835b99 | 1466 | u32 pending_max; |
6383c0b3 AE |
1467 | |
1468 | /* multiple tx classes of service */ | |
1469 | u8 max_cos; | |
1470 | ||
1471 | /* priority to cos mapping */ | |
1472 | u8 prio_to_cos[8]; | |
a2fbb9ea ET |
1473 | }; |
1474 | ||
619c5cb6 VZ |
1475 | /* Tx queues may be less or equal to Rx queues */ |
1476 | extern int num_queues; | |
54b9ddaa | 1477 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
6383c0b3 AE |
1478 | #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) |
1479 | #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) | |
ec6ba945 | 1480 | |
54b9ddaa | 1481 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
3196a88a | 1482 | |
6383c0b3 AE |
1483 | #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) |
1484 | /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ | |
523224a3 DK |
1485 | |
1486 | #define RSS_IPV4_CAP_MASK \ | |
1487 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | |
1488 | ||
1489 | #define RSS_IPV4_TCP_CAP_MASK \ | |
1490 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | |
1491 | ||
1492 | #define RSS_IPV6_CAP_MASK \ | |
1493 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | |
1494 | ||
1495 | #define RSS_IPV6_TCP_CAP_MASK \ | |
1496 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | |
1497 | ||
1498 | /* func init flags */ | |
619c5cb6 VZ |
1499 | #define FUNC_FLG_RSS 0x0001 |
1500 | #define FUNC_FLG_STATS 0x0002 | |
1501 | /* removed FUNC_FLG_UNMATCHED 0x0004 */ | |
1502 | #define FUNC_FLG_TPA 0x0008 | |
1503 | #define FUNC_FLG_SPQ 0x0010 | |
1504 | #define FUNC_FLG_LEADING 0x0020 /* PF only */ | |
523224a3 | 1505 | |
523224a3 DK |
1506 | |
1507 | struct bnx2x_func_init_params { | |
523224a3 DK |
1508 | /* dma */ |
1509 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ | |
1510 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ | |
1511 | ||
1512 | u16 func_flgs; | |
1513 | u16 func_id; /* abs fid */ | |
1514 | u16 pf_id; | |
1515 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ | |
1516 | }; | |
1517 | ||
ec6ba945 | 1518 | #define for_each_eth_queue(bp, var) \ |
6383c0b3 | 1519 | for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 VZ |
1520 | |
1521 | #define for_each_nondefault_eth_queue(bp, var) \ | |
6383c0b3 | 1522 | for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 | 1523 | |
555f6c78 | 1524 | #define for_each_queue(bp, var) \ |
6383c0b3 | 1525 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1526 | if (skip_queue(bp, var)) \ |
1527 | continue; \ | |
1528 | else | |
1529 | ||
6383c0b3 | 1530 | /* Skip forwarding FP */ |
ec6ba945 | 1531 | #define for_each_rx_queue(bp, var) \ |
6383c0b3 | 1532 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1533 | if (skip_rx_queue(bp, var)) \ |
1534 | continue; \ | |
1535 | else | |
1536 | ||
6383c0b3 | 1537 | /* Skip OOO FP */ |
ec6ba945 | 1538 | #define for_each_tx_queue(bp, var) \ |
6383c0b3 | 1539 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1540 | if (skip_tx_queue(bp, var)) \ |
1541 | continue; \ | |
1542 | else | |
1543 | ||
3196a88a | 1544 | #define for_each_nondefault_queue(bp, var) \ |
6383c0b3 | 1545 | for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1546 | if (skip_queue(bp, var)) \ |
1547 | continue; \ | |
1548 | else | |
3196a88a | 1549 | |
6383c0b3 AE |
1550 | #define for_each_cos_in_tx_queue(fp, var) \ |
1551 | for ((var) = 0; (var) < (fp)->max_cos; (var)++) | |
1552 | ||
ec6ba945 | 1553 | /* skip rx queue |
008d23e4 | 1554 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1555 | */ |
1556 | #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1557 | ||
1558 | /* skip tx queue | |
008d23e4 | 1559 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1560 | */ |
1561 | #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1562 | ||
1563 | #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
3196a88a | 1564 | |
f85582f8 | 1565 | |
619c5cb6 VZ |
1566 | |
1567 | ||
1568 | /** | |
1569 | * bnx2x_set_mac_one - configure a single MAC address | |
1570 | * | |
1571 | * @bp: driver handle | |
1572 | * @mac: MAC to configure | |
1573 | * @obj: MAC object handle | |
1574 | * @set: if 'true' add a new MAC, otherwise - delete | |
1575 | * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) | |
1576 | * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) | |
1577 | * | |
1578 | * Configures one MAC according to provided parameters or continues the | |
1579 | * execution of previously scheduled commands if RAMROD_CONT is set in | |
1580 | * ramrod_flags. | |
1581 | * | |
1582 | * Returns zero if operation has successfully completed, a positive value if the | |
1583 | * operation has been successfully scheduled and a negative - if a requested | |
1584 | * operations has failed. | |
1585 | */ | |
1586 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, | |
1587 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
1588 | int mac_type, unsigned long *ramrod_flags); | |
1589 | /** | |
1590 | * Deletes all MACs configured for the specific MAC object. | |
1591 | * | |
1592 | * @param bp Function driver instance | |
1593 | * @param mac_obj MAC object to cleanup | |
1594 | * | |
1595 | * @return zero if all MACs were cleaned | |
1596 | */ | |
1597 | ||
1598 | /** | |
1599 | * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object | |
1600 | * | |
1601 | * @bp: driver handle | |
1602 | * @mac_obj: MAC object handle | |
1603 | * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) | |
1604 | * @wait_for_comp: if 'true' block until completion | |
1605 | * | |
1606 | * Deletes all MACs of the specific type (e.g. ETH, UC list). | |
1607 | * | |
1608 | * Returns zero if operation has successfully completed, a positive value if the | |
1609 | * operation has been successfully scheduled and a negative - if a requested | |
1610 | * operations has failed. | |
1611 | */ | |
1612 | int bnx2x_del_all_macs(struct bnx2x *bp, | |
1613 | struct bnx2x_vlan_mac_obj *mac_obj, | |
1614 | int mac_type, bool wait_for_comp); | |
1615 | ||
1616 | /* Init Function API */ | |
1617 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); | |
1618 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); | |
1619 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
1620 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); | |
1621 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
2ae17f66 VZ |
1622 | void bnx2x_read_mf_cfg(struct bnx2x *bp); |
1623 | ||
619c5cb6 | 1624 | |
f85582f8 | 1625 | /* dmae */ |
c18487ee YR |
1626 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
1627 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
1628 | u32 len32); | |
f85582f8 DK |
1629 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1630 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); | |
1631 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); | |
1632 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |
1633 | bool with_comp, u8 comp_type); | |
1634 | ||
f85582f8 | 1635 | |
de0c62db DK |
1636 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
1637 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
619c5cb6 | 1638 | u32 data_hi, u32 data_lo, int cmd_type); |
de0c62db | 1639 | void bnx2x_update_coalesce(struct bnx2x *bp); |
1ac9e428 | 1640 | int bnx2x_get_cur_phy_idx(struct bnx2x *bp); |
f85582f8 | 1641 | |
34f80b04 EG |
1642 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
1643 | int wait) | |
1644 | { | |
1645 | u32 val; | |
1646 | ||
1647 | do { | |
1648 | val = REG_RD(bp, reg); | |
1649 | if (val == expected) | |
1650 | break; | |
1651 | ms -= wait; | |
1652 | msleep(wait); | |
1653 | ||
1654 | } while (ms > 0); | |
1655 | ||
1656 | return val; | |
1657 | } | |
f85582f8 | 1658 | |
523224a3 DK |
1659 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
1660 | do { \ | |
d245a111 | 1661 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ |
523224a3 DK |
1662 | if (x) \ |
1663 | memset(x, 0, size); \ | |
1664 | } while (0) | |
1665 | ||
1666 | #define BNX2X_ILT_FREE(x, y, size) \ | |
1667 | do { \ | |
1668 | if (x) { \ | |
d245a111 | 1669 | dma_free_coherent(&bp->pdev->dev, size, x, y); \ |
523224a3 DK |
1670 | x = NULL; \ |
1671 | y = 0; \ | |
1672 | } \ | |
1673 | } while (0) | |
1674 | ||
1675 | #define ILOG2(x) (ilog2((x))) | |
1676 | ||
1677 | #define ILT_NUM_PAGE_ENTRIES (3072) | |
1678 | /* In 57710/11 we use whole table since we have 8 func | |
f85582f8 DK |
1679 | * In 57712 we have only 4 func, but use same size per func, then only half of |
1680 | * the table in use | |
523224a3 DK |
1681 | */ |
1682 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) | |
1683 | ||
1684 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
1685 | /* | |
1686 | * the phys address is shifted right 12 bits and has an added | |
1687 | * 1=valid bit added to the 53rd bit | |
1688 | * then since this is a wide register(TM) | |
1689 | * we split it into two 32 bit writes | |
1690 | */ | |
1691 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) | |
1692 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) | |
34f80b04 | 1693 | |
34f80b04 EG |
1694 | /* load/unload mode */ |
1695 | #define LOAD_NORMAL 0 | |
1696 | #define LOAD_OPEN 1 | |
1697 | #define LOAD_DIAG 2 | |
1698 | #define UNLOAD_NORMAL 0 | |
1699 | #define UNLOAD_CLOSE 1 | |
f85582f8 | 1700 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 1701 | |
bb2a0f7a | 1702 | |
ad8d3948 | 1703 | /* DMAE command defines */ |
f2e0899f DK |
1704 | #define DMAE_TIMEOUT -1 |
1705 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1706 | #define DMAE_NOT_RDY -3 | |
1707 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1708 | ||
1709 | #define DMAE_SRC_PCI 0 | |
1710 | #define DMAE_SRC_GRC 1 | |
1711 | ||
1712 | #define DMAE_DST_NONE 0 | |
1713 | #define DMAE_DST_PCI 1 | |
1714 | #define DMAE_DST_GRC 2 | |
1715 | ||
1716 | #define DMAE_COMP_PCI 0 | |
1717 | #define DMAE_COMP_GRC 1 | |
1718 | ||
1719 | /* E2 and onward - PCI error handling in the completion */ | |
1720 | ||
1721 | #define DMAE_COMP_REGULAR 0 | |
1722 | #define DMAE_COM_SET_ERR 1 | |
ad8d3948 | 1723 | |
f2e0899f DK |
1724 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
1725 | DMAE_COMMAND_SRC_SHIFT) | |
1726 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ | |
1727 | DMAE_COMMAND_SRC_SHIFT) | |
ad8d3948 | 1728 | |
f2e0899f DK |
1729 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
1730 | DMAE_COMMAND_DST_SHIFT) | |
1731 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ | |
1732 | DMAE_COMMAND_DST_SHIFT) | |
1733 | ||
1734 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ | |
1735 | DMAE_COMMAND_C_DST_SHIFT) | |
1736 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ | |
1737 | DMAE_COMMAND_C_DST_SHIFT) | |
ad8d3948 EG |
1738 | |
1739 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
1740 | ||
1741 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1742 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1743 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1744 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1745 | ||
1746 | #define DMAE_CMD_PORT_0 0 | |
1747 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
1748 | ||
1749 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
1750 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
1751 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
1752 | ||
f2e0899f DK |
1753 | #define DMAE_SRC_PF 0 |
1754 | #define DMAE_SRC_VF 1 | |
1755 | ||
1756 | #define DMAE_DST_PF 0 | |
1757 | #define DMAE_DST_VF 1 | |
1758 | ||
1759 | #define DMAE_C_SRC 0 | |
1760 | #define DMAE_C_DST 1 | |
1761 | ||
ad8d3948 | 1762 | #define DMAE_LEN32_RD_MAX 0x80 |
02e3c6cb | 1763 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 | 1764 | |
f2e0899f DK |
1765 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
1766 | indicates eror */ | |
ad8d3948 EG |
1767 | |
1768 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 1769 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 | 1770 | BP_E1HVN(bp)) |
ab6ad5a4 | 1771 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
1772 | E1HVN_MAX) |
1773 | ||
25047950 ET |
1774 | /* PCIE link and speed */ |
1775 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1776 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1777 | #define PCICFG_LINK_SPEED 0xf0000 | |
1778 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1779 | |
bb2a0f7a | 1780 | |
d3d4f495 | 1781 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a | 1782 | |
b5bf9068 EG |
1783 | #define BNX2X_PHY_LOOPBACK 0 |
1784 | #define BNX2X_MAC_LOOPBACK 1 | |
1785 | #define BNX2X_PHY_LOOPBACK_FAILED 1 | |
1786 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
bb2a0f7a YG |
1787 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
1788 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1789 | |
7a9b2557 VZ |
1790 | |
1791 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1792 | ||
96fc1784 | 1793 | |
34f80b04 | 1794 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 | 1795 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
619c5cb6 VZ |
1796 | (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \ |
1797 | (x)) | |
7a9b2557 VZ |
1798 | |
1799 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1800 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1801 | ||
1802 | ||
523224a3 | 1803 | #define BNX2X_BTR 4 |
7a9b2557 | 1804 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 1805 | |
ff80ee02 DK |
1806 | /* CMNG constants, as derived from system spec calculations */ |
1807 | /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ | |
1808 | #define DEF_MIN_RATE 100 | |
9b3de1ef DK |
1809 | /* resolution of the rate shaping timer - 400 usec */ |
1810 | #define RS_PERIODIC_TIMEOUT_USEC 400 | |
34f80b04 | 1811 | /* number of bytes in single QM arbitration cycle - |
ff80ee02 DK |
1812 | * coefficient for calculating the fairness timer */ |
1813 | #define QM_ARB_BYTES 160000 | |
1814 | /* resolution of Min algorithm 1:100 */ | |
1815 | #define MIN_RES 100 | |
1816 | /* how many bytes above threshold for the minimal credit of Min algorithm*/ | |
1817 | #define MIN_ABOVE_THRESH 32768 | |
1818 | /* Fairness algorithm integration time coefficient - | |
1819 | * for calculating the actual Tfair */ | |
1820 | #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) | |
1821 | /* Memory of fairness algorithm . 2 cycles */ | |
1822 | #define FAIR_MEM 2 | |
34f80b04 EG |
1823 | |
1824 | ||
1825 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1826 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1827 | #define GPIO_2_FUNC (1L << 10) | |
1828 | #define GPIO_3_FUNC (1L << 11) | |
1829 | #define GPIO_4_FUNC (1L << 12) | |
1830 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1831 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1832 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1833 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1834 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1835 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1836 | ||
1837 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1838 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1839 | |
1840 | ||
34f80b04 EG |
1841 | /* stuff added to make the code fit 80Col */ |
1842 | ||
1843 | #define BNX2X_PMF_LINK_ASSERT \ | |
1844 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1845 | ||
a2fbb9ea ET |
1846 | #define BNX2X_MC_ASSERT_BITS \ |
1847 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1848 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1849 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1850 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1851 | ||
1852 | #define BNX2X_MCP_ASSERT \ | |
1853 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1854 | ||
34f80b04 EG |
1855 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1856 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1857 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1858 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1859 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1860 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1861 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1862 | ||
a2fbb9ea ET |
1863 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1864 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1865 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1866 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
c9ee9206 | 1867 | AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) |
34f80b04 | 1868 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1869 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1870 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1871 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
c9ee9206 VZ |
1872 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ |
1873 | AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ | |
1874 | AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) | |
a2fbb9ea ET |
1875 | #define HW_INTERRUT_ASSERT_SET_1 \ |
1876 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1877 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1878 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1879 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1880 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1881 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1882 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1883 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1884 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1885 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1886 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
c9ee9206 | 1887 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ |
a2fbb9ea | 1888 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
c9ee9206 | 1889 | AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ |
a2fbb9ea | 1890 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
c9ee9206 | 1891 | AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ |
a2fbb9ea | 1892 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
ab6ad5a4 | 1893 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
c9ee9206 | 1894 | AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ |
ab6ad5a4 | 1895 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ |
a2fbb9ea ET |
1896 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
1897 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
c9ee9206 | 1898 | AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ |
a2fbb9ea ET |
1899 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ |
1900 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
c9ee9206 VZ |
1901 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ |
1902 | AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) | |
a2fbb9ea ET |
1903 | #define HW_INTERRUT_ASSERT_SET_2 \ |
1904 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1905 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1906 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1907 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1908 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1909 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1910 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1911 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1912 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1913 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
c9ee9206 | 1914 | AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ |
a2fbb9ea ET |
1915 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ |
1916 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1917 | ||
72fd0718 VZ |
1918 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
1919 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
1920 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
1921 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 1922 | |
c68ed255 | 1923 | #define RSS_FLAGS(bp) \ |
34f80b04 EG |
1924 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
1925 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1926 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1927 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
555f6c78 EG |
1928 | (bp->multi_mode << \ |
1929 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) | |
34f80b04 | 1930 | #define MULTI_MASK 0x7f |
a2fbb9ea | 1931 | |
619c5cb6 VZ |
1932 | |
1933 | #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) | |
1934 | #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) | |
1935 | #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) | |
1936 | #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) | |
1937 | ||
1938 | #define DEF_USB_IGU_INDEX_OFF \ | |
1939 | offsetof(struct cstorm_def_status_block_u, igu_index) | |
1940 | #define DEF_CSB_IGU_INDEX_OFF \ | |
1941 | offsetof(struct cstorm_def_status_block_c, igu_index) | |
1942 | #define DEF_XSB_IGU_INDEX_OFF \ | |
1943 | offsetof(struct xstorm_def_status_block, igu_index) | |
1944 | #define DEF_TSB_IGU_INDEX_OFF \ | |
1945 | offsetof(struct tstorm_def_status_block, igu_index) | |
1946 | ||
1947 | #define DEF_USB_SEGMENT_OFF \ | |
1948 | offsetof(struct cstorm_def_status_block_u, segment) | |
1949 | #define DEF_CSB_SEGMENT_OFF \ | |
1950 | offsetof(struct cstorm_def_status_block_c, segment) | |
1951 | #define DEF_XSB_SEGMENT_OFF \ | |
1952 | offsetof(struct xstorm_def_status_block, segment) | |
1953 | #define DEF_TSB_SEGMENT_OFF \ | |
1954 | offsetof(struct tstorm_def_status_block, segment) | |
1955 | ||
a2fbb9ea | 1956 | #define BNX2X_SP_DSB_INDEX \ |
523224a3 DK |
1957 | (&bp->def_status_blk->sp_sb.\ |
1958 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) | |
f85582f8 | 1959 | |
523224a3 DK |
1960 | #define SET_FLAG(value, mask, flag) \ |
1961 | do {\ | |
1962 | (value) &= ~(mask);\ | |
1963 | (value) |= ((flag) << (mask##_SHIFT));\ | |
1964 | } while (0) | |
a2fbb9ea | 1965 | |
523224a3 | 1966 | #define GET_FLAG(value, mask) \ |
619c5cb6 | 1967 | (((value) & (mask)) >> (mask##_SHIFT)) |
a2fbb9ea | 1968 | |
f2e0899f DK |
1969 | #define GET_FIELD(value, fname) \ |
1970 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) | |
1971 | ||
a2fbb9ea | 1972 | #define CAM_IS_INVALID(x) \ |
523224a3 DK |
1973 | (GET_FLAG(x.flags, \ |
1974 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ | |
1975 | (T_ETH_MAC_COMMAND_INVALIDATE)) | |
a2fbb9ea | 1976 | |
34f80b04 EG |
1977 | /* Number of u32 elements in MC hash array */ |
1978 | #define MC_HASH_SIZE 8 | |
1979 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1980 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
1981 | |
1982 | ||
34f80b04 EG |
1983 | #ifndef PXP2_REG_PXP2_INT_STS |
1984 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1985 | #endif | |
1986 | ||
f2e0899f DK |
1987 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
1988 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
1989 | #endif | |
f85582f8 | 1990 | |
34f24c7f VZ |
1991 | #define BNX2X_VPD_LEN 128 |
1992 | #define VENDOR_ID_LEN 4 | |
1993 | ||
523224a3 DK |
1994 | /* Congestion management fairness mode */ |
1995 | #define CMNG_FNS_NONE 0 | |
1996 | #define CMNG_FNS_MINMAX 1 | |
1997 | ||
1998 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ | |
1999 | #define HC_SEG_ACCESS_ATTN 4 | |
2000 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ | |
2001 | ||
619c5cb6 VZ |
2002 | static const u32 dmae_reg_go_c[] = { |
2003 | DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, | |
2004 | DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, | |
2005 | DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, | |
2006 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 | |
2007 | }; | |
de0c62db | 2008 | |
619c5cb6 | 2009 | void bnx2x_set_ethtool_ops(struct net_device *netdev); |
3deb8167 | 2010 | void bnx2x_notify_link_changed(struct bnx2x *bp); |
a2fbb9ea | 2011 | #endif /* bnx2x.h */ |