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a2fbb9ea ET |
1 | /* bnx2x_hsi.h: Broadcom Everest network driver. |
2 | * | |
3359fced | 3 | * Copyright (c) 2007-2010 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
523224a3 DK |
9 | #ifndef BNX2X_HSI_H |
10 | #define BNX2X_HSI_H | |
11 | ||
12 | #include "bnx2x_fw_defs.h" | |
a2fbb9ea | 13 | |
e2513065 MC |
14 | struct license_key { |
15 | u32 reserved[6]; | |
16 | ||
17 | #if defined(__BIG_ENDIAN) | |
18 | u16 max_iscsi_init_conn; | |
19 | u16 max_iscsi_trgt_conn; | |
20 | #elif defined(__LITTLE_ENDIAN) | |
21 | u16 max_iscsi_trgt_conn; | |
22 | u16 max_iscsi_init_conn; | |
23 | #endif | |
24 | ||
25 | u32 reserved_a[6]; | |
26 | }; | |
27 | ||
a2fbb9ea | 28 | |
f1410647 ET |
29 | #define PORT_0 0 |
30 | #define PORT_1 1 | |
31 | #define PORT_MAX 2 | |
a2fbb9ea ET |
32 | |
33 | /**************************************************************************** | |
34 | * Shared HW configuration * | |
35 | ****************************************************************************/ | |
36 | struct shared_hw_cfg { /* NVRAM Offset */ | |
37 | /* Up to 16 bytes of NULL-terminated string */ | |
38 | u8 part_num[16]; /* 0x104 */ | |
39 | ||
40 | u32 config; /* 0x114 */ | |
41 | #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 | |
42 | #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 | |
43 | #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 | |
44 | #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 | |
45 | #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 | |
46 | ||
47 | #define SHARED_HW_CFG_PORT_SWAP 0x00000004 | |
48 | ||
49 | #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 | |
50 | ||
51 | #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 | |
52 | #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 | |
53 | /* Whatever MFW found in NVM | |
54 | (if multiple found, priority order is: NC-SI, UMP, IPMI) */ | |
55 | #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 | |
56 | #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 | |
57 | #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 | |
58 | #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 | |
59 | /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI | |
60 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
61 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 | |
62 | /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI | |
63 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
64 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 | |
65 | /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP | |
66 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
67 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 | |
68 | ||
69 | #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 | |
70 | #define SHARED_HW_CFG_LED_MODE_SHIFT 16 | |
71 | #define SHARED_HW_CFG_LED_MAC1 0x00000000 | |
72 | #define SHARED_HW_CFG_LED_PHY1 0x00010000 | |
73 | #define SHARED_HW_CFG_LED_PHY2 0x00020000 | |
74 | #define SHARED_HW_CFG_LED_PHY3 0x00030000 | |
75 | #define SHARED_HW_CFG_LED_MAC2 0x00040000 | |
76 | #define SHARED_HW_CFG_LED_PHY4 0x00050000 | |
77 | #define SHARED_HW_CFG_LED_PHY5 0x00060000 | |
78 | #define SHARED_HW_CFG_LED_PHY6 0x00070000 | |
79 | #define SHARED_HW_CFG_LED_MAC3 0x00080000 | |
80 | #define SHARED_HW_CFG_LED_PHY7 0x00090000 | |
81 | #define SHARED_HW_CFG_LED_PHY9 0x000a0000 | |
82 | #define SHARED_HW_CFG_LED_PHY11 0x000b0000 | |
83 | #define SHARED_HW_CFG_LED_MAC4 0x000c0000 | |
84 | #define SHARED_HW_CFG_LED_PHY8 0x000d0000 | |
7f02c4ad YR |
85 | #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 |
86 | ||
a2fbb9ea ET |
87 | |
88 | #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 | |
89 | #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 | |
90 | #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 | |
91 | #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 | |
92 | #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 | |
93 | #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 | |
94 | #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 | |
95 | #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 | |
96 | ||
97 | u32 config2; /* 0x118 */ | |
98 | /* one time auto detect grace period (in sec) */ | |
99 | #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff | |
100 | #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 | |
101 | ||
102 | #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 | |
103 | ||
104 | /* The default value for the core clock is 250MHz and it is | |
105 | achieved by setting the clock change to 4 */ | |
106 | #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 | |
107 | #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 | |
108 | ||
109 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 | |
110 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 | |
111 | ||
f1410647 | 112 | #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
a2fbb9ea | 113 | |
fd4ef40d EG |
114 | /* The fan failure mechanism is usually related to the PHY type |
115 | since the power consumption of the board is determined by the PHY. | |
116 | Currently, fan is required for most designs with SFX7101, BCM8727 | |
117 | and BCM8481. If a fan is not required for a board which uses one | |
118 | of those PHYs, this field should be set to "Disabled". If a fan is | |
119 | required for a different PHY type, this option should be set to | |
120 | "Enabled". | |
121 | The fan failure indication is expected on | |
122 | SPIO5 */ | |
123 | #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 | |
124 | #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 | |
125 | #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 | |
126 | #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 | |
127 | #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 | |
128 | ||
e10bc84d YR |
129 | /* Set the MDC/MDIO access for the first external phy */ |
130 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 | |
131 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 | |
132 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 | |
133 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 | |
134 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 | |
135 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 | |
136 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 | |
137 | ||
138 | /* Set the MDC/MDIO access for the second external phy */ | |
139 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 | |
140 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 | |
141 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 | |
142 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 | |
143 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 | |
144 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 | |
145 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 | |
a2fbb9ea ET |
146 | u32 power_dissipated; /* 0x11c */ |
147 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 | |
148 | #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 | |
149 | ||
150 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 | |
151 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 | |
152 | #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 | |
153 | #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 | |
154 | #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 | |
155 | #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 | |
156 | ||
157 | u32 ump_nc_si_config; /* 0x120 */ | |
158 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 | |
159 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 | |
160 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 | |
161 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 | |
162 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 | |
163 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 | |
164 | ||
165 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 | |
166 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 | |
167 | ||
168 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 | |
169 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 | |
170 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 | |
171 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 | |
172 | ||
173 | u32 board; /* 0x124 */ | |
35b19ba5 | 174 | #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 |
a2fbb9ea ET |
175 | #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 |
176 | ||
35b19ba5 EG |
177 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 |
178 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 | |
179 | ||
180 | #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 | |
181 | #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 | |
182 | ||
a2fbb9ea ET |
183 | u32 reserved; /* 0x128 */ |
184 | ||
185 | }; | |
186 | ||
f1410647 | 187 | |
a2fbb9ea ET |
188 | /**************************************************************************** |
189 | * Port HW configuration * | |
190 | ****************************************************************************/ | |
f1410647 | 191 | struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ |
a2fbb9ea | 192 | |
a2fbb9ea ET |
193 | u32 pci_id; |
194 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 | |
195 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff | |
196 | ||
197 | u32 pci_sub_id; | |
198 | #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 | |
199 | #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff | |
200 | ||
201 | u32 power_dissipated; | |
202 | #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 | |
203 | #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 | |
204 | #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 | |
205 | #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 | |
206 | #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 | |
207 | #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 | |
208 | #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff | |
209 | #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 | |
210 | ||
211 | u32 power_consumed; | |
212 | #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 | |
213 | #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 | |
214 | #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 | |
215 | #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 | |
216 | #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 | |
217 | #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 | |
218 | #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff | |
219 | #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 | |
220 | ||
221 | u32 mac_upper; | |
222 | #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff | |
223 | #define PORT_HW_CFG_UPPERMAC_SHIFT 0 | |
224 | u32 mac_lower; | |
225 | ||
226 | u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ | |
227 | u32 iscsi_mac_lower; | |
228 | ||
229 | u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ | |
230 | u32 rdma_mac_lower; | |
231 | ||
232 | u32 serdes_config; | |
c2c8b03e EG |
233 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF |
234 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 | |
235 | ||
236 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 | |
237 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 | |
238 | ||
239 | ||
240 | u32 Reserved0[16]; /* 0x158 */ | |
241 | ||
242 | /* for external PHY, or forced mode or during AN */ | |
243 | u16 xgxs_config_rx[4]; /* 0x198 */ | |
244 | ||
245 | u16 xgxs_config_tx[4]; /* 0x1A0 */ | |
246 | ||
a22f0788 YR |
247 | u32 Reserved1[57]; /* 0x1A8 */ |
248 | u32 speed_capability_mask2; /* 0x28C */ | |
249 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF | |
250 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 | |
251 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 | |
252 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 | |
253 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 | |
254 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 | |
255 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 | |
256 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 | |
257 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 | |
258 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080 | |
259 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100 | |
260 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200 | |
261 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400 | |
262 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800 | |
263 | ||
264 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 | |
265 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 | |
266 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 | |
267 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 | |
268 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 | |
269 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 | |
270 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 | |
271 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 | |
272 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 | |
273 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000 | |
274 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000 | |
275 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000 | |
276 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000 | |
277 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000 | |
278 | ||
279 | /* In the case where two media types (e.g. copper and fiber) are | |
280 | present and electrically active at the same time, PHY Selection | |
281 | will determine which of the two PHYs will be designated as the | |
282 | Active PHY and used for a connection to the network. */ | |
283 | u32 multi_phy_config; /* 0x290 */ | |
284 | #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 | |
285 | #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 | |
286 | #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 | |
287 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 | |
288 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 | |
289 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 | |
290 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 | |
291 | ||
292 | /* When enabled, all second phy nvram parameters will be swapped | |
293 | with the first phy parameters */ | |
294 | #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 | |
295 | #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 | |
296 | #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 | |
297 | #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 | |
298 | ||
299 | ||
300 | /* Address of the second external phy */ | |
301 | u32 external_phy_config2; /* 0x294 */ | |
302 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF | |
303 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 | |
304 | ||
305 | /* The second XGXS external PHY type */ | |
306 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 | |
307 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 | |
308 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 | |
309 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 | |
310 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 | |
311 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 | |
312 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 | |
313 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 | |
314 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 | |
315 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 | |
316 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 | |
317 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 | |
318 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 | |
319 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 | |
320 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 | |
321 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 | |
322 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 | |
323 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 | |
324 | ||
325 | /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as | |
326 | 8706, 8726 and 8727) not all 4 values are needed. */ | |
327 | u16 xgxs_config2_rx[4]; /* 0x296 */ | |
328 | u16 xgxs_config2_tx[4]; /* 0x2A0 */ | |
a2fbb9ea ET |
329 | |
330 | u32 lane_config; | |
331 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff | |
332 | #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
523224a3 | 333 | |
a2fbb9ea ET |
334 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff |
335 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
336 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 | |
337 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
338 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 | |
339 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 | |
340 | /* AN and forced */ | |
341 | #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b | |
342 | /* forced only */ | |
343 | #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 | |
344 | /* forced only */ | |
345 | #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 | |
346 | /* forced only */ | |
347 | #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 | |
348 | ||
349 | u32 external_phy_config; | |
350 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 | |
351 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 | |
352 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 | |
353 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 | |
354 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 | |
355 | ||
356 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 | |
357 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 | |
358 | ||
359 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 | |
360 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 | |
361 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 | |
362 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 | |
363 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 | |
364 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 | |
365 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 | |
366 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 | |
589abe3a | 367 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 |
a2fbb9ea | 368 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 |
f1410647 | 369 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 |
4d295db0 EG |
370 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 |
371 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 | |
4f60dab1 | 372 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 |
f1410647 | 373 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 |
a2fbb9ea ET |
374 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
375 | ||
376 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff | |
377 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 | |
378 | ||
379 | u32 speed_capability_mask; | |
380 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 | |
381 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 | |
382 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 | |
383 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 | |
384 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 | |
385 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 | |
386 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 | |
387 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 | |
388 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 | |
389 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000 | |
390 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000 | |
391 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000 | |
392 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000 | |
393 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000 | |
394 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 | |
395 | ||
396 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff | |
397 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 | |
398 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 | |
399 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 | |
400 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 | |
401 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 | |
402 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 | |
403 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 | |
404 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 | |
405 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080 | |
406 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100 | |
407 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200 | |
408 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400 | |
409 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800 | |
410 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 | |
411 | ||
412 | u32 reserved[2]; | |
413 | ||
414 | }; | |
415 | ||
f1410647 | 416 | |
a2fbb9ea ET |
417 | /**************************************************************************** |
418 | * Shared Feature configuration * | |
419 | ****************************************************************************/ | |
420 | struct shared_feat_cfg { /* NVRAM Offset */ | |
f1410647 ET |
421 | |
422 | u32 config; /* 0x450 */ | |
a2fbb9ea | 423 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 |
589abe3a EG |
424 | |
425 | /* Use the values from options 47 and 48 instead of the HW default | |
426 | values */ | |
427 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000 | |
428 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002 | |
429 | ||
34f80b04 | 430 | #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100 |
a2fbb9ea ET |
431 | |
432 | }; | |
433 | ||
434 | ||
435 | /**************************************************************************** | |
436 | * Port Feature configuration * | |
437 | ****************************************************************************/ | |
f1410647 ET |
438 | struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ |
439 | ||
a2fbb9ea ET |
440 | u32 config; |
441 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f | |
442 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 | |
443 | #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 | |
444 | #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 | |
445 | #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 | |
446 | #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 | |
447 | #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 | |
448 | #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 | |
449 | #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 | |
450 | #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 | |
451 | #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 | |
452 | #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 | |
453 | #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a | |
454 | #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b | |
455 | #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c | |
456 | #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d | |
457 | #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e | |
458 | #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f | |
459 | #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 | |
460 | #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 | |
461 | #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 | |
462 | #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 | |
463 | #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 | |
464 | #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 | |
465 | #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 | |
466 | #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 | |
467 | #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 | |
468 | #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 | |
469 | #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 | |
470 | #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 | |
471 | #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 | |
472 | #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 | |
473 | #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 | |
474 | #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 | |
475 | #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 | |
476 | #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 | |
477 | #define PORT_FEATURE_EN_SIZE_MASK 0x07000000 | |
478 | #define PORT_FEATURE_EN_SIZE_SHIFT 24 | |
479 | #define PORT_FEATURE_WOL_ENABLED 0x01000000 | |
480 | #define PORT_FEATURE_MBA_ENABLED 0x02000000 | |
481 | #define PORT_FEATURE_MFW_ENABLED 0x04000000 | |
482 | ||
4d295db0 EG |
483 | /* Reserved bits: 28-29 */ |
484 | /* Check the optic vendor via i2c against a list of approved modules | |
485 | in a separate nvram image */ | |
486 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 | |
487 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 | |
488 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000 | |
489 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000 | |
490 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 | |
491 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 | |
492 | ||
589abe3a | 493 | |
a2fbb9ea ET |
494 | u32 wol_config; |
495 | /* Default is used when driver sets to "auto" mode */ | |
496 | #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 | |
497 | #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 | |
498 | #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 | |
499 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 | |
500 | #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 | |
501 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 | |
502 | #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 | |
503 | #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 | |
504 | #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 | |
505 | ||
506 | u32 mba_config; | |
507 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003 | |
508 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 | |
509 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 | |
510 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 | |
511 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 | |
512 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 | |
513 | #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 | |
514 | #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 | |
515 | #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 | |
516 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 | |
517 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 | |
518 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 | |
519 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 | |
520 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 | |
521 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 | |
522 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 | |
523 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 | |
524 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 | |
525 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 | |
526 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 | |
527 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 | |
528 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 | |
529 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 | |
530 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 | |
531 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 | |
532 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 | |
533 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 | |
534 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 | |
535 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 | |
536 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 | |
537 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 | |
538 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 | |
539 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 | |
540 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 | |
541 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 | |
542 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 | |
543 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 | |
544 | #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 | |
545 | #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 | |
546 | #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 | |
547 | #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 | |
548 | #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 | |
549 | #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 | |
550 | #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 | |
551 | #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 | |
552 | #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 | |
553 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 | |
554 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000 | |
555 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000 | |
556 | #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000 | |
557 | #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000 | |
558 | #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000 | |
559 | #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000 | |
560 | #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000 | |
561 | ||
562 | u32 bmc_config; | |
563 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 | |
564 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 | |
565 | ||
566 | u32 mba_vlan_cfg; | |
567 | #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff | |
568 | #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 | |
569 | #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 | |
570 | ||
571 | u32 resource_cfg; | |
572 | #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 | |
573 | #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 | |
574 | #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 | |
575 | #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 | |
576 | #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 | |
577 | ||
578 | u32 smbus_config; | |
579 | /* Obsolete */ | |
580 | #define PORT_FEATURE_SMBUS_EN 0x00000001 | |
581 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe | |
582 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 | |
583 | ||
f1410647 | 584 | u32 reserved1; |
a2fbb9ea ET |
585 | |
586 | u32 link_config; /* Used as HW defaults for the driver */ | |
587 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 | |
588 | #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 | |
589 | /* (forced) low speed switch (< 10G) */ | |
590 | #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 | |
591 | /* (forced) high speed switch (>= 10G) */ | |
592 | #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 | |
593 | #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 | |
594 | #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 | |
595 | ||
596 | #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 | |
597 | #define PORT_FEATURE_LINK_SPEED_SHIFT 16 | |
598 | #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 | |
599 | #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 | |
600 | #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 | |
601 | #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 | |
602 | #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 | |
603 | #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 | |
604 | #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 | |
605 | #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 | |
606 | #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000 | |
607 | #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000 | |
608 | #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000 | |
609 | #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000 | |
610 | #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000 | |
611 | #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000 | |
612 | #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000 | |
613 | ||
614 | #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 | |
615 | #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 | |
616 | #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 | |
617 | #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 | |
618 | #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 | |
619 | #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 | |
620 | #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 | |
621 | ||
622 | /* The default for MCP link configuration, | |
a22f0788 | 623 | uses the same defines as link_config */ |
a2fbb9ea | 624 | u32 mfw_wol_link_cfg; |
a22f0788 YR |
625 | /* The default for the driver of the second external phy, |
626 | uses the same defines as link_config */ | |
627 | u32 link_config2; /* 0x47C */ | |
a2fbb9ea | 628 | |
a22f0788 YR |
629 | /* The default for MCP of the second external phy, |
630 | uses the same defines as link_config */ | |
631 | u32 mfw_wol_link_cfg2; /* 0x480 */ | |
632 | ||
633 | u32 Reserved2[17]; /* 0x484 */ | |
a2fbb9ea ET |
634 | |
635 | }; | |
636 | ||
637 | ||
34f80b04 EG |
638 | /**************************************************************************** |
639 | * Device Information * | |
640 | ****************************************************************************/ | |
5cd65a93 | 641 | struct shm_dev_info { /* size */ |
f1410647 | 642 | |
34f80b04 | 643 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ |
f1410647 | 644 | |
34f80b04 | 645 | struct shared_hw_cfg shared_hw_config; /* 40 */ |
f1410647 | 646 | |
34f80b04 | 647 | struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ |
f1410647 | 648 | |
34f80b04 | 649 | struct shared_feat_cfg shared_feature_config; /* 4 */ |
f1410647 | 650 | |
34f80b04 | 651 | struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ |
f1410647 ET |
652 | |
653 | }; | |
654 | ||
655 | ||
656 | #define FUNC_0 0 | |
657 | #define FUNC_1 1 | |
ad8d3948 EG |
658 | #define FUNC_2 2 |
659 | #define FUNC_3 3 | |
660 | #define FUNC_4 4 | |
661 | #define FUNC_5 5 | |
662 | #define FUNC_6 6 | |
663 | #define FUNC_7 7 | |
f1410647 | 664 | #define E1_FUNC_MAX 2 |
ad8d3948 EG |
665 | #define E1H_FUNC_MAX 8 |
666 | ||
667 | #define VN_0 0 | |
668 | #define VN_1 1 | |
669 | #define VN_2 2 | |
670 | #define VN_3 3 | |
671 | #define E1VN_MAX 1 | |
672 | #define E1HVN_MAX 4 | |
f1410647 ET |
673 | |
674 | ||
675 | /* This value (in milliseconds) determines the frequency of the driver | |
676 | * issuing the PULSE message code. The firmware monitors this periodic | |
677 | * pulse to determine when to switch to an OS-absent mode. */ | |
678 | #define DRV_PULSE_PERIOD_MS 250 | |
679 | ||
680 | /* This value (in milliseconds) determines how long the driver should | |
681 | * wait for an acknowledgement from the firmware before timing out. Once | |
682 | * the firmware has timed out, the driver will assume there is no firmware | |
683 | * running and there won't be any firmware-driver synchronization during a | |
684 | * driver reset. */ | |
685 | #define FW_ACK_TIME_OUT_MS 5000 | |
686 | ||
687 | #define FW_ACK_POLL_TIME_MS 1 | |
688 | ||
689 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) | |
690 | ||
691 | /* LED Blink rate that will achieve ~15.9Hz */ | |
692 | #define LED_BLINK_RATE_VAL 480 | |
693 | ||
a2fbb9ea | 694 | /**************************************************************************** |
f1410647 | 695 | * Driver <-> FW Mailbox * |
a2fbb9ea | 696 | ****************************************************************************/ |
f1410647 | 697 | struct drv_port_mb { |
a2fbb9ea | 698 | |
f1410647 ET |
699 | u32 link_status; |
700 | /* Driver should update this field on any link change event */ | |
a2fbb9ea | 701 | |
f1410647 ET |
702 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 |
703 | #define LINK_STATUS_LINK_UP 0x00000001 | |
704 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E | |
705 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) | |
706 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) | |
707 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) | |
708 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) | |
709 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) | |
710 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) | |
711 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) | |
712 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) | |
713 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) | |
714 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) | |
715 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) | |
716 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) | |
717 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) | |
718 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) | |
719 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1) | |
720 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1) | |
721 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1) | |
722 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1) | |
723 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1) | |
724 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1) | |
725 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1) | |
726 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1) | |
727 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1) | |
728 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1) | |
a2fbb9ea | 729 | |
f1410647 ET |
730 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 |
731 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
a2fbb9ea | 732 | |
f1410647 ET |
733 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 |
734 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 | |
735 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
a2fbb9ea | 736 | |
f1410647 ET |
737 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 |
738 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
739 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 | |
740 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 | |
741 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 | |
742 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 | |
743 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 | |
744 | ||
745 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 | |
746 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 | |
747 | ||
748 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 | |
749 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 | |
750 | ||
751 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | |
752 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) | |
753 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) | |
754 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) | |
755 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) | |
756 | ||
757 | #define LINK_STATUS_SERDES_LINK 0x00100000 | |
758 | ||
759 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 | |
760 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 | |
761 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 | |
762 | #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000 | |
763 | #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000 | |
764 | #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000 | |
765 | #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 | |
766 | #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 | |
767 | ||
34f80b04 EG |
768 | u32 port_stx; |
769 | ||
de832a55 EG |
770 | u32 stat_nig_timer; |
771 | ||
a35da8db EG |
772 | /* MCP firmware does not use this field */ |
773 | u32 ext_phy_fw_version; | |
f1410647 ET |
774 | |
775 | }; | |
776 | ||
777 | ||
778 | struct drv_func_mb { | |
779 | ||
780 | u32 drv_mb_header; | |
781 | #define DRV_MSG_CODE_MASK 0xffff0000 | |
782 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
783 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
784 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 | |
785 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 | |
786 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 | |
787 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
2691d51d EG |
788 | #define DRV_MSG_CODE_DCC_OK 0x30000000 |
789 | #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 | |
f1410647 ET |
790 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 |
791 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 | |
792 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 | |
793 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 | |
794 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 | |
795 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 | |
796 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 | |
4d295db0 | 797 | /* |
f77f13e2 | 798 | * The optic module verification commands require bootcode |
4d295db0 EG |
799 | * v5.0.6 or later |
800 | */ | |
a22f0788 YR |
801 | #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 |
802 | #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 | |
803 | /* | |
804 | * The specific optic module verification command requires bootcode | |
805 | * v5.2.12 or later | |
806 | */ | |
807 | #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 | |
808 | #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 | |
f1410647 | 809 | |
34f80b04 EG |
810 | #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 |
811 | #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 | |
812 | #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
813 | #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
814 | ||
f1410647 ET |
815 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff |
816 | ||
817 | u32 drv_mb_param; | |
818 | ||
819 | u32 fw_mb_header; | |
820 | #define FW_MSG_CODE_MASK 0xffff0000 | |
821 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 | |
822 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
823 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
824 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 | |
825 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 | |
826 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 | |
827 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 | |
828 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 | |
829 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
2691d51d | 830 | #define FW_MSG_CODE_DCC_DONE 0x30100000 |
f1410647 ET |
831 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 |
832 | #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 | |
833 | #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 | |
834 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 | |
835 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 | |
836 | #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 | |
837 | #define FW_MSG_CODE_NO_KEY 0x80f00000 | |
838 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 | |
839 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 | |
840 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 | |
841 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 | |
842 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 | |
843 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 | |
4d295db0 EG |
844 | #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 |
845 | #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 | |
846 | #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 | |
f1410647 | 847 | |
34f80b04 EG |
848 | #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 |
849 | #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 | |
850 | #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
851 | #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
852 | ||
f1410647 ET |
853 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff |
854 | ||
855 | u32 fw_mb_param; | |
856 | ||
857 | u32 drv_pulse_mb; | |
858 | #define DRV_PULSE_SEQ_MASK 0x00007fff | |
859 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
860 | /* The system time is in the format of | |
861 | * (year-2001)*12*32 + month*32 + day. */ | |
862 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
863 | /* Indicate to the firmware not to go into the | |
864 | * OS-absent when it is not getting driver pulse. | |
865 | * This is used for debugging as well for PXE(MBA). */ | |
866 | ||
867 | u32 mcp_pulse_mb; | |
868 | #define MCP_PULSE_SEQ_MASK 0x00007fff | |
869 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
870 | /* Indicates to the driver not to assert due to lack | |
871 | * of MCP response */ | |
872 | #define MCP_EVENT_MASK 0xffff0000 | |
873 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
874 | ||
875 | u32 iscsi_boot_signature; | |
876 | u32 iscsi_boot_block_offset; | |
877 | ||
34f80b04 EG |
878 | u32 drv_status; |
879 | #define DRV_STATUS_PMF 0x00000001 | |
880 | ||
2691d51d EG |
881 | #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 |
882 | #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 | |
883 | #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 | |
884 | #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 | |
885 | #define DRV_STATUS_DCC_RESERVED1 0x00000800 | |
886 | #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 | |
887 | #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 | |
888 | ||
34f80b04 EG |
889 | u32 virt_mac_upper; |
890 | #define VIRT_MAC_SIGN_MASK 0xffff0000 | |
891 | #define VIRT_MAC_SIGNATURE 0x564d0000 | |
892 | u32 virt_mac_lower; | |
a2fbb9ea ET |
893 | |
894 | }; | |
895 | ||
896 | ||
897 | /**************************************************************************** | |
898 | * Management firmware state * | |
899 | ****************************************************************************/ | |
f1410647 ET |
900 | /* Allocate 440 bytes for management firmware */ |
901 | #define MGMTFW_STATE_WORD_SIZE 110 | |
a2fbb9ea ET |
902 | |
903 | struct mgmtfw_state { | |
904 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; | |
905 | }; | |
906 | ||
907 | ||
34f80b04 EG |
908 | /**************************************************************************** |
909 | * Multi-Function configuration * | |
910 | ****************************************************************************/ | |
911 | struct shared_mf_cfg { | |
912 | ||
913 | u32 clp_mb; | |
914 | #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 | |
915 | /* set by CLP */ | |
916 | #define SHARED_MF_CLP_EXIT 0x00000001 | |
917 | /* set by MCP */ | |
918 | #define SHARED_MF_CLP_EXIT_DONE 0x00010000 | |
919 | ||
920 | }; | |
921 | ||
922 | struct port_mf_cfg { | |
923 | ||
924 | u32 dynamic_cfg; /* device control channel */ | |
2691d51d EG |
925 | #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
926 | #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 | |
927 | #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK | |
34f80b04 EG |
928 | |
929 | u32 reserved[3]; | |
930 | ||
931 | }; | |
932 | ||
933 | struct func_mf_cfg { | |
934 | ||
935 | u32 config; | |
936 | /* E/R/I/D */ | |
937 | /* function 0 of each port cannot be hidden */ | |
938 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 | |
939 | ||
940 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007 | |
941 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 | |
942 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 | |
943 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 | |
944 | #define FUNC_MF_CFG_PROTOCOL_DEFAULT\ | |
945 | FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA | |
946 | ||
947 | #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 | |
948 | ||
949 | /* PRI */ | |
950 | /* 0 - low priority, 3 - high priority */ | |
951 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 | |
952 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 | |
953 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 | |
954 | ||
955 | /* MINBW, MAXBW */ | |
956 | /* value range - 0..100, increments in 100Mbps */ | |
957 | #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 | |
958 | #define FUNC_MF_CFG_MIN_BW_SHIFT 16 | |
959 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 | |
960 | #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 | |
961 | #define FUNC_MF_CFG_MAX_BW_SHIFT 24 | |
962 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 | |
963 | ||
964 | u32 mac_upper; /* MAC */ | |
965 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff | |
966 | #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 | |
967 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK | |
968 | u32 mac_lower; | |
969 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff | |
970 | ||
971 | u32 e1hov_tag; /* VNI */ | |
972 | #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff | |
973 | #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 | |
974 | #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK | |
975 | ||
976 | u32 reserved[2]; | |
977 | ||
978 | }; | |
979 | ||
980 | struct mf_cfg { | |
981 | ||
982 | struct shared_mf_cfg shared_mf_config; | |
983 | struct port_mf_cfg port_mf_config[PORT_MAX]; | |
34f80b04 | 984 | struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; |
34f80b04 EG |
985 | |
986 | }; | |
987 | ||
988 | ||
a2fbb9ea ET |
989 | /**************************************************************************** |
990 | * Shared Memory Region * | |
991 | ****************************************************************************/ | |
992 | struct shmem_region { /* SharedMem Offset (size) */ | |
f1410647 ET |
993 | |
994 | u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ | |
995 | #define SHR_MEM_FORMAT_REV_ID ('A'<<24) | |
996 | #define SHR_MEM_FORMAT_REV_MASK 0xff000000 | |
997 | /* validity bits */ | |
998 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 | |
999 | #define SHR_MEM_VALIDITY_MB 0x00200000 | |
1000 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 | |
1001 | #define SHR_MEM_VALIDITY_RESERVED 0x00000007 | |
a2fbb9ea ET |
1002 | /* One licensing bit should be set */ |
1003 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 | |
1004 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 | |
1005 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 | |
1006 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 | |
f1410647 ET |
1007 | /* Active MFW */ |
1008 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 | |
1009 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 | |
1010 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 | |
1011 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 | |
1012 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 | |
1013 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 | |
a2fbb9ea | 1014 | |
5cd65a93 | 1015 | struct shm_dev_info dev_info; /* 0x8 (0x438) */ |
a2fbb9ea | 1016 | |
e2513065 | 1017 | struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ |
a2fbb9ea ET |
1018 | |
1019 | /* FW information (for internal FW use) */ | |
f1410647 ET |
1020 | u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ |
1021 | struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ | |
1022 | ||
1023 | struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ | |
523224a3 DK |
1024 | struct drv_func_mb func_mb[]; /* 0x684 |
1025 | (44*2/4/8=0x58/0xb0/0x160) */ | |
1026 | ||
1027 | }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ | |
34f80b04 | 1028 | |
a2fbb9ea | 1029 | |
a2fbb9ea ET |
1030 | |
1031 | ||
2691d51d EG |
1032 | struct shmem2_region { |
1033 | ||
1034 | u32 size; | |
1035 | ||
1036 | u32 dcc_support; | |
1037 | #define SHMEM_DCC_SUPPORT_NONE 0x00000000 | |
1038 | #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 | |
1039 | #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 | |
1040 | #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 | |
1041 | #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 | |
1042 | #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 | |
1043 | #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE | |
a22f0788 YR |
1044 | u32 ext_phy_fw_version2[PORT_MAX]; |
1045 | /* | |
1046 | * For backwards compatibility, if the mf_cfg_addr does not exist | |
1047 | * (the size filed is smaller than 0xc) the mf_cfg resides at the | |
1048 | * end of struct shmem_region | |
1049 | */ | |
2691d51d EG |
1050 | }; |
1051 | ||
1052 | ||
bb2a0f7a YG |
1053 | struct emac_stats { |
1054 | u32 rx_stat_ifhcinoctets; | |
1055 | u32 rx_stat_ifhcinbadoctets; | |
1056 | u32 rx_stat_etherstatsfragments; | |
1057 | u32 rx_stat_ifhcinucastpkts; | |
1058 | u32 rx_stat_ifhcinmulticastpkts; | |
1059 | u32 rx_stat_ifhcinbroadcastpkts; | |
1060 | u32 rx_stat_dot3statsfcserrors; | |
1061 | u32 rx_stat_dot3statsalignmenterrors; | |
1062 | u32 rx_stat_dot3statscarriersenseerrors; | |
1063 | u32 rx_stat_xonpauseframesreceived; | |
1064 | u32 rx_stat_xoffpauseframesreceived; | |
1065 | u32 rx_stat_maccontrolframesreceived; | |
1066 | u32 rx_stat_xoffstateentered; | |
1067 | u32 rx_stat_dot3statsframestoolong; | |
1068 | u32 rx_stat_etherstatsjabbers; | |
1069 | u32 rx_stat_etherstatsundersizepkts; | |
1070 | u32 rx_stat_etherstatspkts64octets; | |
1071 | u32 rx_stat_etherstatspkts65octetsto127octets; | |
1072 | u32 rx_stat_etherstatspkts128octetsto255octets; | |
1073 | u32 rx_stat_etherstatspkts256octetsto511octets; | |
1074 | u32 rx_stat_etherstatspkts512octetsto1023octets; | |
1075 | u32 rx_stat_etherstatspkts1024octetsto1522octets; | |
1076 | u32 rx_stat_etherstatspktsover1522octets; | |
1077 | ||
1078 | u32 rx_stat_falsecarriererrors; | |
1079 | ||
1080 | u32 tx_stat_ifhcoutoctets; | |
1081 | u32 tx_stat_ifhcoutbadoctets; | |
1082 | u32 tx_stat_etherstatscollisions; | |
1083 | u32 tx_stat_outxonsent; | |
1084 | u32 tx_stat_outxoffsent; | |
1085 | u32 tx_stat_flowcontroldone; | |
1086 | u32 tx_stat_dot3statssinglecollisionframes; | |
1087 | u32 tx_stat_dot3statsmultiplecollisionframes; | |
1088 | u32 tx_stat_dot3statsdeferredtransmissions; | |
1089 | u32 tx_stat_dot3statsexcessivecollisions; | |
1090 | u32 tx_stat_dot3statslatecollisions; | |
1091 | u32 tx_stat_ifhcoutucastpkts; | |
1092 | u32 tx_stat_ifhcoutmulticastpkts; | |
1093 | u32 tx_stat_ifhcoutbroadcastpkts; | |
1094 | u32 tx_stat_etherstatspkts64octets; | |
1095 | u32 tx_stat_etherstatspkts65octetsto127octets; | |
1096 | u32 tx_stat_etherstatspkts128octetsto255octets; | |
1097 | u32 tx_stat_etherstatspkts256octetsto511octets; | |
1098 | u32 tx_stat_etherstatspkts512octetsto1023octets; | |
1099 | u32 tx_stat_etherstatspkts1024octetsto1522octets; | |
1100 | u32 tx_stat_etherstatspktsover1522octets; | |
1101 | u32 tx_stat_dot3statsinternalmactransmiterrors; | |
1102 | }; | |
1103 | ||
1104 | ||
523224a3 | 1105 | struct bmac1_stats { |
bb2a0f7a YG |
1106 | u32 tx_stat_gtpkt_lo; |
1107 | u32 tx_stat_gtpkt_hi; | |
1108 | u32 tx_stat_gtxpf_lo; | |
1109 | u32 tx_stat_gtxpf_hi; | |
1110 | u32 tx_stat_gtfcs_lo; | |
1111 | u32 tx_stat_gtfcs_hi; | |
1112 | u32 tx_stat_gtmca_lo; | |
1113 | u32 tx_stat_gtmca_hi; | |
1114 | u32 tx_stat_gtbca_lo; | |
1115 | u32 tx_stat_gtbca_hi; | |
1116 | u32 tx_stat_gtfrg_lo; | |
1117 | u32 tx_stat_gtfrg_hi; | |
1118 | u32 tx_stat_gtovr_lo; | |
1119 | u32 tx_stat_gtovr_hi; | |
1120 | u32 tx_stat_gt64_lo; | |
1121 | u32 tx_stat_gt64_hi; | |
1122 | u32 tx_stat_gt127_lo; | |
1123 | u32 tx_stat_gt127_hi; | |
1124 | u32 tx_stat_gt255_lo; | |
1125 | u32 tx_stat_gt255_hi; | |
1126 | u32 tx_stat_gt511_lo; | |
1127 | u32 tx_stat_gt511_hi; | |
1128 | u32 tx_stat_gt1023_lo; | |
1129 | u32 tx_stat_gt1023_hi; | |
1130 | u32 tx_stat_gt1518_lo; | |
1131 | u32 tx_stat_gt1518_hi; | |
1132 | u32 tx_stat_gt2047_lo; | |
1133 | u32 tx_stat_gt2047_hi; | |
1134 | u32 tx_stat_gt4095_lo; | |
1135 | u32 tx_stat_gt4095_hi; | |
1136 | u32 tx_stat_gt9216_lo; | |
1137 | u32 tx_stat_gt9216_hi; | |
1138 | u32 tx_stat_gt16383_lo; | |
1139 | u32 tx_stat_gt16383_hi; | |
1140 | u32 tx_stat_gtmax_lo; | |
1141 | u32 tx_stat_gtmax_hi; | |
1142 | u32 tx_stat_gtufl_lo; | |
1143 | u32 tx_stat_gtufl_hi; | |
1144 | u32 tx_stat_gterr_lo; | |
1145 | u32 tx_stat_gterr_hi; | |
1146 | u32 tx_stat_gtbyt_lo; | |
1147 | u32 tx_stat_gtbyt_hi; | |
1148 | ||
1149 | u32 rx_stat_gr64_lo; | |
1150 | u32 rx_stat_gr64_hi; | |
1151 | u32 rx_stat_gr127_lo; | |
1152 | u32 rx_stat_gr127_hi; | |
1153 | u32 rx_stat_gr255_lo; | |
1154 | u32 rx_stat_gr255_hi; | |
1155 | u32 rx_stat_gr511_lo; | |
1156 | u32 rx_stat_gr511_hi; | |
1157 | u32 rx_stat_gr1023_lo; | |
1158 | u32 rx_stat_gr1023_hi; | |
1159 | u32 rx_stat_gr1518_lo; | |
1160 | u32 rx_stat_gr1518_hi; | |
1161 | u32 rx_stat_gr2047_lo; | |
1162 | u32 rx_stat_gr2047_hi; | |
1163 | u32 rx_stat_gr4095_lo; | |
1164 | u32 rx_stat_gr4095_hi; | |
1165 | u32 rx_stat_gr9216_lo; | |
1166 | u32 rx_stat_gr9216_hi; | |
1167 | u32 rx_stat_gr16383_lo; | |
1168 | u32 rx_stat_gr16383_hi; | |
1169 | u32 rx_stat_grmax_lo; | |
1170 | u32 rx_stat_grmax_hi; | |
1171 | u32 rx_stat_grpkt_lo; | |
1172 | u32 rx_stat_grpkt_hi; | |
1173 | u32 rx_stat_grfcs_lo; | |
1174 | u32 rx_stat_grfcs_hi; | |
1175 | u32 rx_stat_grmca_lo; | |
1176 | u32 rx_stat_grmca_hi; | |
1177 | u32 rx_stat_grbca_lo; | |
1178 | u32 rx_stat_grbca_hi; | |
1179 | u32 rx_stat_grxcf_lo; | |
1180 | u32 rx_stat_grxcf_hi; | |
1181 | u32 rx_stat_grxpf_lo; | |
1182 | u32 rx_stat_grxpf_hi; | |
1183 | u32 rx_stat_grxuo_lo; | |
1184 | u32 rx_stat_grxuo_hi; | |
1185 | u32 rx_stat_grjbr_lo; | |
1186 | u32 rx_stat_grjbr_hi; | |
1187 | u32 rx_stat_grovr_lo; | |
1188 | u32 rx_stat_grovr_hi; | |
1189 | u32 rx_stat_grflr_lo; | |
1190 | u32 rx_stat_grflr_hi; | |
1191 | u32 rx_stat_grmeg_lo; | |
1192 | u32 rx_stat_grmeg_hi; | |
1193 | u32 rx_stat_grmeb_lo; | |
1194 | u32 rx_stat_grmeb_hi; | |
1195 | u32 rx_stat_grbyt_lo; | |
1196 | u32 rx_stat_grbyt_hi; | |
1197 | u32 rx_stat_grund_lo; | |
1198 | u32 rx_stat_grund_hi; | |
1199 | u32 rx_stat_grfrg_lo; | |
1200 | u32 rx_stat_grfrg_hi; | |
1201 | u32 rx_stat_grerb_lo; | |
1202 | u32 rx_stat_grerb_hi; | |
1203 | u32 rx_stat_grfre_lo; | |
1204 | u32 rx_stat_grfre_hi; | |
1205 | u32 rx_stat_gripj_lo; | |
1206 | u32 rx_stat_gripj_hi; | |
1207 | }; | |
1208 | ||
1209 | ||
1210 | union mac_stats { | |
523224a3 DK |
1211 | struct emac_stats emac_stats; |
1212 | struct bmac1_stats bmac1_stats; | |
bb2a0f7a YG |
1213 | }; |
1214 | ||
1215 | ||
1216 | struct mac_stx { | |
1217 | /* in_bad_octets */ | |
1218 | u32 rx_stat_ifhcinbadoctets_hi; | |
1219 | u32 rx_stat_ifhcinbadoctets_lo; | |
1220 | ||
1221 | /* out_bad_octets */ | |
1222 | u32 tx_stat_ifhcoutbadoctets_hi; | |
1223 | u32 tx_stat_ifhcoutbadoctets_lo; | |
1224 | ||
1225 | /* crc_receive_errors */ | |
1226 | u32 rx_stat_dot3statsfcserrors_hi; | |
1227 | u32 rx_stat_dot3statsfcserrors_lo; | |
1228 | /* alignment_errors */ | |
1229 | u32 rx_stat_dot3statsalignmenterrors_hi; | |
1230 | u32 rx_stat_dot3statsalignmenterrors_lo; | |
1231 | /* carrier_sense_errors */ | |
1232 | u32 rx_stat_dot3statscarriersenseerrors_hi; | |
1233 | u32 rx_stat_dot3statscarriersenseerrors_lo; | |
1234 | /* false_carrier_detections */ | |
1235 | u32 rx_stat_falsecarriererrors_hi; | |
1236 | u32 rx_stat_falsecarriererrors_lo; | |
1237 | ||
1238 | /* runt_packets_received */ | |
1239 | u32 rx_stat_etherstatsundersizepkts_hi; | |
1240 | u32 rx_stat_etherstatsundersizepkts_lo; | |
1241 | /* jabber_packets_received */ | |
1242 | u32 rx_stat_dot3statsframestoolong_hi; | |
1243 | u32 rx_stat_dot3statsframestoolong_lo; | |
1244 | ||
1245 | /* error_runt_packets_received */ | |
1246 | u32 rx_stat_etherstatsfragments_hi; | |
1247 | u32 rx_stat_etherstatsfragments_lo; | |
1248 | /* error_jabber_packets_received */ | |
1249 | u32 rx_stat_etherstatsjabbers_hi; | |
1250 | u32 rx_stat_etherstatsjabbers_lo; | |
1251 | ||
1252 | /* control_frames_received */ | |
1253 | u32 rx_stat_maccontrolframesreceived_hi; | |
1254 | u32 rx_stat_maccontrolframesreceived_lo; | |
1255 | u32 rx_stat_bmac_xpf_hi; | |
1256 | u32 rx_stat_bmac_xpf_lo; | |
1257 | u32 rx_stat_bmac_xcf_hi; | |
1258 | u32 rx_stat_bmac_xcf_lo; | |
1259 | ||
1260 | /* xoff_state_entered */ | |
1261 | u32 rx_stat_xoffstateentered_hi; | |
1262 | u32 rx_stat_xoffstateentered_lo; | |
1263 | /* pause_xon_frames_received */ | |
1264 | u32 rx_stat_xonpauseframesreceived_hi; | |
1265 | u32 rx_stat_xonpauseframesreceived_lo; | |
1266 | /* pause_xoff_frames_received */ | |
1267 | u32 rx_stat_xoffpauseframesreceived_hi; | |
1268 | u32 rx_stat_xoffpauseframesreceived_lo; | |
1269 | /* pause_xon_frames_transmitted */ | |
1270 | u32 tx_stat_outxonsent_hi; | |
1271 | u32 tx_stat_outxonsent_lo; | |
1272 | /* pause_xoff_frames_transmitted */ | |
1273 | u32 tx_stat_outxoffsent_hi; | |
1274 | u32 tx_stat_outxoffsent_lo; | |
1275 | /* flow_control_done */ | |
1276 | u32 tx_stat_flowcontroldone_hi; | |
1277 | u32 tx_stat_flowcontroldone_lo; | |
1278 | ||
1279 | /* ether_stats_collisions */ | |
1280 | u32 tx_stat_etherstatscollisions_hi; | |
1281 | u32 tx_stat_etherstatscollisions_lo; | |
1282 | /* single_collision_transmit_frames */ | |
1283 | u32 tx_stat_dot3statssinglecollisionframes_hi; | |
1284 | u32 tx_stat_dot3statssinglecollisionframes_lo; | |
1285 | /* multiple_collision_transmit_frames */ | |
1286 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; | |
1287 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; | |
1288 | /* deferred_transmissions */ | |
1289 | u32 tx_stat_dot3statsdeferredtransmissions_hi; | |
1290 | u32 tx_stat_dot3statsdeferredtransmissions_lo; | |
1291 | /* excessive_collision_frames */ | |
1292 | u32 tx_stat_dot3statsexcessivecollisions_hi; | |
1293 | u32 tx_stat_dot3statsexcessivecollisions_lo; | |
1294 | /* late_collision_frames */ | |
1295 | u32 tx_stat_dot3statslatecollisions_hi; | |
1296 | u32 tx_stat_dot3statslatecollisions_lo; | |
1297 | ||
1298 | /* frames_transmitted_64_bytes */ | |
1299 | u32 tx_stat_etherstatspkts64octets_hi; | |
1300 | u32 tx_stat_etherstatspkts64octets_lo; | |
1301 | /* frames_transmitted_65_127_bytes */ | |
1302 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; | |
1303 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; | |
1304 | /* frames_transmitted_128_255_bytes */ | |
1305 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; | |
1306 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; | |
1307 | /* frames_transmitted_256_511_bytes */ | |
1308 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; | |
1309 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; | |
1310 | /* frames_transmitted_512_1023_bytes */ | |
1311 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; | |
1312 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; | |
1313 | /* frames_transmitted_1024_1522_bytes */ | |
1314 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; | |
1315 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; | |
1316 | /* frames_transmitted_1523_9022_bytes */ | |
1317 | u32 tx_stat_etherstatspktsover1522octets_hi; | |
1318 | u32 tx_stat_etherstatspktsover1522octets_lo; | |
1319 | u32 tx_stat_bmac_2047_hi; | |
1320 | u32 tx_stat_bmac_2047_lo; | |
1321 | u32 tx_stat_bmac_4095_hi; | |
1322 | u32 tx_stat_bmac_4095_lo; | |
1323 | u32 tx_stat_bmac_9216_hi; | |
1324 | u32 tx_stat_bmac_9216_lo; | |
1325 | u32 tx_stat_bmac_16383_hi; | |
1326 | u32 tx_stat_bmac_16383_lo; | |
1327 | ||
1328 | /* internal_mac_transmit_errors */ | |
1329 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; | |
1330 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; | |
1331 | ||
1332 | /* if_out_discards */ | |
1333 | u32 tx_stat_bmac_ufl_hi; | |
1334 | u32 tx_stat_bmac_ufl_lo; | |
1335 | }; | |
1336 | ||
1337 | ||
1338 | #define MAC_STX_IDX_MAX 2 | |
1339 | ||
1340 | struct host_port_stats { | |
1341 | u32 host_port_stats_start; | |
1342 | ||
1343 | struct mac_stx mac_stx[MAC_STX_IDX_MAX]; | |
1344 | ||
1345 | u32 brb_drop_hi; | |
1346 | u32 brb_drop_lo; | |
1347 | ||
1348 | u32 host_port_stats_end; | |
1349 | }; | |
1350 | ||
1351 | ||
1352 | struct host_func_stats { | |
1353 | u32 host_func_stats_start; | |
1354 | ||
1355 | u32 total_bytes_received_hi; | |
1356 | u32 total_bytes_received_lo; | |
1357 | ||
1358 | u32 total_bytes_transmitted_hi; | |
1359 | u32 total_bytes_transmitted_lo; | |
1360 | ||
1361 | u32 total_unicast_packets_received_hi; | |
1362 | u32 total_unicast_packets_received_lo; | |
1363 | ||
1364 | u32 total_multicast_packets_received_hi; | |
1365 | u32 total_multicast_packets_received_lo; | |
1366 | ||
1367 | u32 total_broadcast_packets_received_hi; | |
1368 | u32 total_broadcast_packets_received_lo; | |
1369 | ||
1370 | u32 total_unicast_packets_transmitted_hi; | |
1371 | u32 total_unicast_packets_transmitted_lo; | |
1372 | ||
1373 | u32 total_multicast_packets_transmitted_hi; | |
1374 | u32 total_multicast_packets_transmitted_lo; | |
1375 | ||
1376 | u32 total_broadcast_packets_transmitted_hi; | |
1377 | u32 total_broadcast_packets_transmitted_lo; | |
1378 | ||
1379 | u32 valid_bytes_received_hi; | |
1380 | u32 valid_bytes_received_lo; | |
1381 | ||
1382 | u32 host_func_stats_end; | |
1383 | }; | |
34f80b04 EG |
1384 | |
1385 | ||
523224a3 DK |
1386 | #define BCM_5710_FW_MAJOR_VERSION 6 |
1387 | #define BCM_5710_FW_MINOR_VERSION 0 | |
1388 | #define BCM_5710_FW_REVISION_VERSION 34 | |
1389 | #define BCM_5710_FW_ENGINEERING_VERSION 0 | |
a2fbb9ea ET |
1390 | #define BCM_5710_FW_COMPILE_FLAGS 1 |
1391 | ||
1392 | ||
1393 | /* | |
1394 | * attention bits | |
1395 | */ | |
523224a3 | 1396 | struct atten_sp_status_block { |
4781bfad EG |
1397 | __le32 attn_bits; |
1398 | __le32 attn_bits_ack; | |
a2fbb9ea ET |
1399 | u8 status_block_id; |
1400 | u8 reserved0; | |
4781bfad EG |
1401 | __le16 attn_bits_index; |
1402 | __le32 reserved1; | |
a2fbb9ea ET |
1403 | }; |
1404 | ||
1405 | ||
1406 | /* | |
1407 | * common data for all protocols | |
1408 | */ | |
1409 | struct doorbell_hdr { | |
1410 | u8 header; | |
1411 | #define DOORBELL_HDR_RX (0x1<<0) | |
1412 | #define DOORBELL_HDR_RX_SHIFT 0 | |
1413 | #define DOORBELL_HDR_DB_TYPE (0x1<<1) | |
1414 | #define DOORBELL_HDR_DB_TYPE_SHIFT 1 | |
1415 | #define DOORBELL_HDR_DPM_SIZE (0x3<<2) | |
1416 | #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 | |
1417 | #define DOORBELL_HDR_CONN_TYPE (0xF<<4) | |
1418 | #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 | |
1419 | }; | |
1420 | ||
1421 | /* | |
34f80b04 | 1422 | * doorbell message sent to the chip |
a2fbb9ea ET |
1423 | */ |
1424 | struct doorbell { | |
1425 | #if defined(__BIG_ENDIAN) | |
1426 | u16 zero_fill2; | |
1427 | u8 zero_fill1; | |
1428 | struct doorbell_hdr header; | |
1429 | #elif defined(__LITTLE_ENDIAN) | |
1430 | struct doorbell_hdr header; | |
1431 | u8 zero_fill1; | |
1432 | u16 zero_fill2; | |
1433 | #endif | |
1434 | }; | |
1435 | ||
1436 | ||
ca00392c EG |
1437 | /* |
1438 | * doorbell message sent to the chip | |
1439 | */ | |
1440 | struct doorbell_set_prod { | |
1441 | #if defined(__BIG_ENDIAN) | |
1442 | u16 prod; | |
1443 | u8 zero_fill1; | |
1444 | struct doorbell_hdr header; | |
1445 | #elif defined(__LITTLE_ENDIAN) | |
1446 | struct doorbell_hdr header; | |
1447 | u8 zero_fill1; | |
1448 | u16 prod; | |
1449 | #endif | |
1450 | }; | |
1451 | ||
1452 | ||
a2fbb9ea | 1453 | /* |
523224a3 DK |
1454 | * 3 lines. status block |
1455 | */ | |
1456 | struct hc_status_block_e1x { | |
1457 | __le16 index_values[HC_SB_MAX_INDICES_E1X]; | |
1458 | __le16 running_index[HC_SB_MAX_SM]; | |
1459 | u32 rsrv; | |
1460 | }; | |
1461 | ||
1462 | /* | |
1463 | * host status block | |
1464 | */ | |
1465 | struct host_hc_status_block_e1x { | |
1466 | struct hc_status_block_e1x sb; | |
1467 | }; | |
1468 | ||
1469 | ||
1470 | /* | |
1471 | * 3 lines. status block | |
1472 | */ | |
1473 | struct hc_status_block_e2 { | |
1474 | __le16 index_values[HC_SB_MAX_INDICES_E2]; | |
1475 | __le16 running_index[HC_SB_MAX_SM]; | |
1476 | u32 reserved; | |
1477 | }; | |
1478 | ||
1479 | /* | |
1480 | * host status block | |
1481 | */ | |
1482 | struct host_hc_status_block_e2 { | |
1483 | struct hc_status_block_e2 sb; | |
1484 | }; | |
1485 | ||
1486 | ||
1487 | /* | |
1488 | * 5 lines. slow-path status block | |
1489 | */ | |
1490 | struct hc_sp_status_block { | |
1491 | __le16 index_values[HC_SP_SB_MAX_INDICES]; | |
1492 | __le16 running_index; | |
1493 | __le16 rsrv; | |
1494 | u32 rsrv1; | |
1495 | }; | |
1496 | ||
1497 | /* | |
1498 | * host status block | |
1499 | */ | |
1500 | struct host_sp_status_block { | |
1501 | struct atten_sp_status_block atten_status_block; | |
1502 | struct hc_sp_status_block sp_sb; | |
1503 | }; | |
1504 | ||
1505 | ||
1506 | /* | |
1507 | * IGU driver acknowledgment register | |
a2fbb9ea ET |
1508 | */ |
1509 | struct igu_ack_register { | |
1510 | #if defined(__BIG_ENDIAN) | |
1511 | u16 sb_id_and_flags; | |
1512 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
1513 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
1514 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
1515 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
1516 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
1517 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
1518 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
1519 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
1520 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
1521 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
1522 | u16 status_block_index; | |
1523 | #elif defined(__LITTLE_ENDIAN) | |
1524 | u16 status_block_index; | |
1525 | u16 sb_id_and_flags; | |
1526 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
1527 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
1528 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
1529 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
1530 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
1531 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
1532 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
1533 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
1534 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
1535 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
1536 | #endif | |
1537 | }; | |
1538 | ||
1539 | ||
ca00392c EG |
1540 | /* |
1541 | * IGU driver acknowledgement register | |
1542 | */ | |
1543 | struct igu_backward_compatible { | |
1544 | u32 sb_id_and_flags; | |
1545 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) | |
1546 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 | |
1547 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) | |
1548 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 | |
1549 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) | |
1550 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 | |
1551 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) | |
1552 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 | |
1553 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) | |
1554 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 | |
1555 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) | |
1556 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 | |
1557 | u32 reserved_2; | |
1558 | }; | |
1559 | ||
1560 | ||
1561 | /* | |
1562 | * IGU driver acknowledgement register | |
1563 | */ | |
1564 | struct igu_regular { | |
1565 | u32 sb_id_and_flags; | |
1566 | #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) | |
1567 | #define IGU_REGULAR_SB_INDEX_SHIFT 0 | |
1568 | #define IGU_REGULAR_RESERVED0 (0x1<<20) | |
1569 | #define IGU_REGULAR_RESERVED0_SHIFT 20 | |
1570 | #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) | |
1571 | #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 | |
1572 | #define IGU_REGULAR_BUPDATE (0x1<<24) | |
1573 | #define IGU_REGULAR_BUPDATE_SHIFT 24 | |
1574 | #define IGU_REGULAR_ENABLE_INT (0x3<<25) | |
1575 | #define IGU_REGULAR_ENABLE_INT_SHIFT 25 | |
1576 | #define IGU_REGULAR_RESERVED_1 (0x1<<27) | |
1577 | #define IGU_REGULAR_RESERVED_1_SHIFT 27 | |
1578 | #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) | |
1579 | #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 | |
1580 | #define IGU_REGULAR_CLEANUP_SET (0x1<<30) | |
1581 | #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 | |
1582 | #define IGU_REGULAR_BCLEANUP (0x1<<31) | |
1583 | #define IGU_REGULAR_BCLEANUP_SHIFT 31 | |
1584 | u32 reserved_2; | |
1585 | }; | |
1586 | ||
1587 | /* | |
1588 | * IGU driver acknowledgement register | |
1589 | */ | |
1590 | union igu_consprod_reg { | |
1591 | struct igu_regular regular; | |
1592 | struct igu_backward_compatible backward_compatible; | |
1593 | }; | |
1594 | ||
1595 | ||
a2fbb9ea ET |
1596 | /* |
1597 | * Parser parsing flags field | |
1598 | */ | |
1599 | struct parsing_flags { | |
4781bfad | 1600 | __le16 flags; |
a2fbb9ea ET |
1601 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) |
1602 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 | |
34f80b04 EG |
1603 | #define PARSING_FLAGS_VLAN (0x1<<1) |
1604 | #define PARSING_FLAGS_VLAN_SHIFT 1 | |
1605 | #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) | |
1606 | #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 | |
a2fbb9ea ET |
1607 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) |
1608 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 | |
1609 | #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) | |
1610 | #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 | |
1611 | #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) | |
1612 | #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 | |
1613 | #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) | |
1614 | #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 | |
1615 | #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) | |
1616 | #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 | |
1617 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) | |
1618 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 | |
1619 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) | |
1620 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 | |
1621 | #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) | |
1622 | #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 | |
1623 | #define PARSING_FLAGS_LLC_SNAP (0x1<<13) | |
1624 | #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 | |
1625 | #define PARSING_FLAGS_RESERVED0 (0x3<<14) | |
1626 | #define PARSING_FLAGS_RESERVED0_SHIFT 14 | |
1627 | }; | |
1628 | ||
1629 | ||
34f80b04 | 1630 | struct regpair { |
4781bfad EG |
1631 | __le32 lo; |
1632 | __le32 hi; | |
34f80b04 EG |
1633 | }; |
1634 | ||
1635 | ||
a2fbb9ea ET |
1636 | /* |
1637 | * dmae command structure | |
1638 | */ | |
1639 | struct dmae_command { | |
1640 | u32 opcode; | |
1641 | #define DMAE_COMMAND_SRC (0x1<<0) | |
1642 | #define DMAE_COMMAND_SRC_SHIFT 0 | |
1643 | #define DMAE_COMMAND_DST (0x3<<1) | |
1644 | #define DMAE_COMMAND_DST_SHIFT 1 | |
1645 | #define DMAE_COMMAND_C_DST (0x1<<3) | |
1646 | #define DMAE_COMMAND_C_DST_SHIFT 3 | |
1647 | #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) | |
1648 | #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 | |
1649 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) | |
1650 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 | |
1651 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) | |
1652 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 | |
1653 | #define DMAE_COMMAND_ENDIANITY (0x3<<9) | |
1654 | #define DMAE_COMMAND_ENDIANITY_SHIFT 9 | |
1655 | #define DMAE_COMMAND_PORT (0x1<<11) | |
1656 | #define DMAE_COMMAND_PORT_SHIFT 11 | |
1657 | #define DMAE_COMMAND_CRC_RESET (0x1<<12) | |
1658 | #define DMAE_COMMAND_CRC_RESET_SHIFT 12 | |
1659 | #define DMAE_COMMAND_SRC_RESET (0x1<<13) | |
1660 | #define DMAE_COMMAND_SRC_RESET_SHIFT 13 | |
1661 | #define DMAE_COMMAND_DST_RESET (0x1<<14) | |
1662 | #define DMAE_COMMAND_DST_RESET_SHIFT 14 | |
ad8d3948 EG |
1663 | #define DMAE_COMMAND_E1HVN (0x3<<15) |
1664 | #define DMAE_COMMAND_E1HVN_SHIFT 15 | |
523224a3 DK |
1665 | #define DMAE_COMMAND_DST_VN (0x3<<17) |
1666 | #define DMAE_COMMAND_DST_VN_SHIFT 17 | |
1667 | #define DMAE_COMMAND_C_FUNC (0x1<<19) | |
1668 | #define DMAE_COMMAND_C_FUNC_SHIFT 19 | |
1669 | #define DMAE_COMMAND_ERR_POLICY (0x3<<20) | |
1670 | #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 | |
1671 | #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) | |
1672 | #define DMAE_COMMAND_RESERVED0_SHIFT 22 | |
a2fbb9ea ET |
1673 | u32 src_addr_lo; |
1674 | u32 src_addr_hi; | |
1675 | u32 dst_addr_lo; | |
1676 | u32 dst_addr_hi; | |
1677 | #if defined(__BIG_ENDIAN) | |
1678 | u16 reserved1; | |
1679 | u16 len; | |
1680 | #elif defined(__LITTLE_ENDIAN) | |
1681 | u16 len; | |
1682 | u16 reserved1; | |
1683 | #endif | |
1684 | u32 comp_addr_lo; | |
1685 | u32 comp_addr_hi; | |
1686 | u32 comp_val; | |
1687 | u32 crc32; | |
1688 | u32 crc32_c; | |
1689 | #if defined(__BIG_ENDIAN) | |
1690 | u16 crc16_c; | |
1691 | u16 crc16; | |
1692 | #elif defined(__LITTLE_ENDIAN) | |
1693 | u16 crc16; | |
1694 | u16 crc16_c; | |
1695 | #endif | |
1696 | #if defined(__BIG_ENDIAN) | |
523224a3 | 1697 | u16 reserved3; |
a2fbb9ea ET |
1698 | u16 crc_t10; |
1699 | #elif defined(__LITTLE_ENDIAN) | |
1700 | u16 crc_t10; | |
523224a3 | 1701 | u16 reserved3; |
a2fbb9ea ET |
1702 | #endif |
1703 | #if defined(__BIG_ENDIAN) | |
1704 | u16 xsum8; | |
1705 | u16 xsum16; | |
1706 | #elif defined(__LITTLE_ENDIAN) | |
1707 | u16 xsum16; | |
1708 | u16 xsum8; | |
1709 | #endif | |
1710 | }; | |
1711 | ||
1712 | ||
1713 | struct double_regpair { | |
1714 | u32 regpair0_lo; | |
1715 | u32 regpair0_hi; | |
1716 | u32 regpair1_lo; | |
1717 | u32 regpair1_hi; | |
1718 | }; | |
1719 | ||
1720 | ||
1721 | /* | |
523224a3 | 1722 | * SDM operation gen command (generate aggregative interrupt) |
a2fbb9ea | 1723 | */ |
523224a3 DK |
1724 | struct sdm_op_gen { |
1725 | __le32 command; | |
1726 | #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) | |
1727 | #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 | |
1728 | #define SDM_OP_GEN_COMP_TYPE (0x7<<5) | |
1729 | #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 | |
1730 | #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) | |
1731 | #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 | |
1732 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) | |
1733 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 | |
1734 | #define SDM_OP_GEN_RESERVED (0x7FFF<<17) | |
1735 | #define SDM_OP_GEN_RESERVED_SHIFT 17 | |
34f80b04 EG |
1736 | }; |
1737 | ||
1738 | /* | |
1739 | * The eth Rx Buffer Descriptor | |
1740 | */ | |
1741 | struct eth_rx_bd { | |
4781bfad EG |
1742 | __le32 addr_lo; |
1743 | __le32 addr_hi; | |
34f80b04 EG |
1744 | }; |
1745 | ||
1746 | /* | |
1747 | * The eth Rx SGE Descriptor | |
1748 | */ | |
1749 | struct eth_rx_sge { | |
4781bfad EG |
1750 | __le32 addr_lo; |
1751 | __le32 addr_hi; | |
34f80b04 EG |
1752 | }; |
1753 | ||
523224a3 | 1754 | |
34f80b04 EG |
1755 | |
1756 | /* | |
1757 | * The eth storm context of Ustorm | |
1758 | */ | |
1759 | struct ustorm_eth_st_context { | |
523224a3 | 1760 | u32 reserved0[48]; |
a2fbb9ea ET |
1761 | }; |
1762 | ||
1763 | /* | |
1764 | * The eth storm context of Tstorm | |
1765 | */ | |
1766 | struct tstorm_eth_st_context { | |
1767 | u32 __reserved0[28]; | |
1768 | }; | |
1769 | ||
a2fbb9ea ET |
1770 | /* |
1771 | * The eth aggregative context of Xstorm | |
1772 | */ | |
1773 | struct xstorm_eth_ag_context { | |
523224a3 | 1774 | u32 reserved0; |
a2fbb9ea ET |
1775 | #if defined(__BIG_ENDIAN) |
1776 | u8 cdu_reserved; | |
523224a3 DK |
1777 | u8 reserved2; |
1778 | u16 reserved1; | |
a2fbb9ea | 1779 | #elif defined(__LITTLE_ENDIAN) |
523224a3 DK |
1780 | u16 reserved1; |
1781 | u8 reserved2; | |
a2fbb9ea ET |
1782 | u8 cdu_reserved; |
1783 | #endif | |
523224a3 | 1784 | u32 reserved3[30]; |
a2fbb9ea ET |
1785 | }; |
1786 | ||
1787 | /* | |
1788 | * The eth aggregative context of Tstorm | |
1789 | */ | |
1790 | struct tstorm_eth_ag_context { | |
523224a3 | 1791 | u32 __reserved0[14]; |
a2fbb9ea ET |
1792 | }; |
1793 | ||
523224a3 | 1794 | |
a2fbb9ea ET |
1795 | /* |
1796 | * The eth aggregative context of Cstorm | |
1797 | */ | |
1798 | struct cstorm_eth_ag_context { | |
523224a3 | 1799 | u32 __reserved0[10]; |
a2fbb9ea ET |
1800 | }; |
1801 | ||
523224a3 | 1802 | |
a2fbb9ea ET |
1803 | /* |
1804 | * The eth aggregative context of Ustorm | |
1805 | */ | |
1806 | struct ustorm_eth_ag_context { | |
523224a3 | 1807 | u32 __reserved0; |
a2fbb9ea ET |
1808 | #if defined(__BIG_ENDIAN) |
1809 | u8 cdu_usage; | |
523224a3 DK |
1810 | u8 __reserved2; |
1811 | u16 __reserved1; | |
a2fbb9ea | 1812 | #elif defined(__LITTLE_ENDIAN) |
523224a3 DK |
1813 | u16 __reserved1; |
1814 | u8 __reserved2; | |
a2fbb9ea ET |
1815 | u8 cdu_usage; |
1816 | #endif | |
523224a3 | 1817 | u32 __reserved3[6]; |
a2fbb9ea ET |
1818 | }; |
1819 | ||
1820 | /* | |
1821 | * Timers connection context | |
1822 | */ | |
1823 | struct timers_block_context { | |
1824 | u32 __reserved_0; | |
1825 | u32 __reserved_1; | |
1826 | u32 __reserved_2; | |
34f80b04 EG |
1827 | u32 flags; |
1828 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) | |
1829 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 | |
1830 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) | |
1831 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 | |
1832 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) | |
1833 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 | |
a2fbb9ea ET |
1834 | }; |
1835 | ||
1836 | /* | |
33471629 | 1837 | * structure for easy accessibility to assembler |
a2fbb9ea ET |
1838 | */ |
1839 | struct eth_tx_bd_flags { | |
1840 | u8 as_bitfield; | |
523224a3 DK |
1841 | #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) |
1842 | #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 | |
1843 | #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) | |
1844 | #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 | |
1845 | #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) | |
1846 | #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 | |
a2fbb9ea ET |
1847 | #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) |
1848 | #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 | |
523224a3 DK |
1849 | #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) |
1850 | #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 | |
a2fbb9ea ET |
1851 | #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) |
1852 | #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 | |
1853 | #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) | |
1854 | #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 | |
1855 | }; | |
1856 | ||
1857 | /* | |
1858 | * The eth Tx Buffer Descriptor | |
1859 | */ | |
ca00392c | 1860 | struct eth_tx_start_bd { |
4781bfad EG |
1861 | __le32 addr_lo; |
1862 | __le32 addr_hi; | |
1863 | __le16 nbd; | |
1864 | __le16 nbytes; | |
523224a3 | 1865 | __le16 vlan_or_ethertype; |
a2fbb9ea ET |
1866 | struct eth_tx_bd_flags bd_flags; |
1867 | u8 general_data; | |
ca00392c EG |
1868 | #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0) |
1869 | #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 | |
1870 | #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) | |
1871 | #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 | |
1872 | }; | |
1873 | ||
1874 | /* | |
1875 | * Tx regular BD structure | |
1876 | */ | |
1877 | struct eth_tx_bd { | |
523224a3 DK |
1878 | __le32 addr_lo; |
1879 | __le32 addr_hi; | |
1880 | __le16 total_pkt_bytes; | |
1881 | __le16 nbytes; | |
ca00392c | 1882 | u8 reserved[4]; |
a2fbb9ea ET |
1883 | }; |
1884 | ||
1885 | /* | |
523224a3 | 1886 | * Tx parsing BD structure for ETH E1/E1h |
a2fbb9ea | 1887 | */ |
523224a3 | 1888 | struct eth_tx_parse_bd_e1x { |
a2fbb9ea | 1889 | u8 global_data; |
523224a3 DK |
1890 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) |
1891 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 | |
1892 | #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) | |
1893 | #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 | |
1894 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) | |
1895 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 | |
1896 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) | |
1897 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 | |
1898 | #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) | |
1899 | #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 | |
a2fbb9ea | 1900 | u8 tcp_flags; |
523224a3 DK |
1901 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) |
1902 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 | |
1903 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) | |
1904 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 | |
1905 | #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) | |
1906 | #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 | |
1907 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) | |
1908 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 | |
1909 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) | |
1910 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 | |
1911 | #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) | |
1912 | #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 | |
1913 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) | |
1914 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 | |
1915 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) | |
1916 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 | |
1917 | u8 ip_hlen_w; | |
ca00392c | 1918 | s8 reserved; |
523224a3 | 1919 | __le16 total_hlen_w; |
4781bfad | 1920 | __le16 tcp_pseudo_csum; |
ca00392c | 1921 | __le16 lso_mss; |
4781bfad EG |
1922 | __le16 ip_id; |
1923 | __le32 tcp_send_seq; | |
a2fbb9ea ET |
1924 | }; |
1925 | ||
1926 | /* | |
1927 | * The last BD in the BD memory will hold a pointer to the next BD memory | |
1928 | */ | |
1929 | struct eth_tx_next_bd { | |
ca00392c EG |
1930 | __le32 addr_lo; |
1931 | __le32 addr_hi; | |
a2fbb9ea ET |
1932 | u8 reserved[8]; |
1933 | }; | |
1934 | ||
1935 | /* | |
ca00392c | 1936 | * union for 4 Bd types |
a2fbb9ea ET |
1937 | */ |
1938 | union eth_tx_bd_types { | |
ca00392c | 1939 | struct eth_tx_start_bd start_bd; |
a2fbb9ea | 1940 | struct eth_tx_bd reg_bd; |
523224a3 | 1941 | struct eth_tx_parse_bd_e1x parse_bd_e1x; |
a2fbb9ea ET |
1942 | struct eth_tx_next_bd next_bd; |
1943 | }; | |
1944 | ||
523224a3 | 1945 | |
a2fbb9ea ET |
1946 | /* |
1947 | * The eth storm context of Xstorm | |
1948 | */ | |
1949 | struct xstorm_eth_st_context { | |
523224a3 | 1950 | u32 reserved0[60]; |
a2fbb9ea ET |
1951 | }; |
1952 | ||
1953 | /* | |
1954 | * The eth storm context of Cstorm | |
1955 | */ | |
1956 | struct cstorm_eth_st_context { | |
523224a3 | 1957 | u32 __reserved0[4]; |
a2fbb9ea ET |
1958 | }; |
1959 | ||
1960 | /* | |
1961 | * Ethernet connection context | |
1962 | */ | |
1963 | struct eth_context { | |
1964 | struct ustorm_eth_st_context ustorm_st_context; | |
1965 | struct tstorm_eth_st_context tstorm_st_context; | |
1966 | struct xstorm_eth_ag_context xstorm_ag_context; | |
1967 | struct tstorm_eth_ag_context tstorm_ag_context; | |
1968 | struct cstorm_eth_ag_context cstorm_ag_context; | |
1969 | struct ustorm_eth_ag_context ustorm_ag_context; | |
1970 | struct timers_block_context timers_context; | |
1971 | struct xstorm_eth_st_context xstorm_st_context; | |
1972 | struct cstorm_eth_st_context cstorm_st_context; | |
1973 | }; | |
1974 | ||
1975 | ||
1976 | /* | |
33471629 | 1977 | * Ethernet doorbell |
a2fbb9ea ET |
1978 | */ |
1979 | struct eth_tx_doorbell { | |
1980 | #if defined(__BIG_ENDIAN) | |
1981 | u16 npackets; | |
1982 | u8 params; | |
1983 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
1984 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
1985 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
1986 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
1987 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
1988 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
1989 | struct doorbell_hdr hdr; | |
1990 | #elif defined(__LITTLE_ENDIAN) | |
1991 | struct doorbell_hdr hdr; | |
1992 | u8 params; | |
1993 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
1994 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
1995 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
1996 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
1997 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
1998 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
1999 | u16 npackets; | |
2000 | #endif | |
2001 | }; | |
2002 | ||
2003 | ||
2004 | /* | |
523224a3 | 2005 | * client init fc data |
a2fbb9ea | 2006 | */ |
523224a3 DK |
2007 | struct client_init_fc_data { |
2008 | __le16 cqe_pause_thr_low; | |
2009 | __le16 cqe_pause_thr_high; | |
2010 | __le16 bd_pause_thr_low; | |
2011 | __le16 bd_pause_thr_high; | |
2012 | __le16 sge_pause_thr_low; | |
2013 | __le16 sge_pause_thr_high; | |
2014 | __le16 rx_cos_mask; | |
2015 | u8 safc_group_num; | |
2016 | u8 safc_group_en_flg; | |
2017 | u8 traffic_type; | |
2018 | u8 reserved0; | |
2019 | __le16 reserved1; | |
2020 | __le32 reserved2; | |
a2fbb9ea ET |
2021 | }; |
2022 | ||
a2fbb9ea ET |
2023 | |
2024 | /* | |
523224a3 | 2025 | * client init ramrod data |
a2fbb9ea | 2026 | */ |
523224a3 DK |
2027 | struct client_init_general_data { |
2028 | u8 client_id; | |
2029 | u8 statistics_counter_id; | |
2030 | u8 statistics_en_flg; | |
2031 | u8 is_fcoe_flg; | |
2032 | u8 activate_flg; | |
2033 | u8 sp_client_id; | |
2034 | __le16 reserved0; | |
2035 | __le32 reserved1[2]; | |
a2fbb9ea ET |
2036 | }; |
2037 | ||
2038 | ||
2039 | /* | |
523224a3 | 2040 | * client init rx data |
a2fbb9ea | 2041 | */ |
523224a3 DK |
2042 | struct client_init_rx_data { |
2043 | u8 tpa_en_flg; | |
2044 | u8 vmqueue_mode_en_flg; | |
2045 | u8 extra_data_over_sgl_en_flg; | |
2046 | u8 cache_line_alignment_log_size; | |
2047 | u8 enable_dynamic_hc; | |
2048 | u8 max_sges_for_packet; | |
2049 | u8 client_qzone_id; | |
2050 | u8 drop_ip_cs_err_flg; | |
2051 | u8 drop_tcp_cs_err_flg; | |
2052 | u8 drop_ttl0_flg; | |
2053 | u8 drop_udp_cs_err_flg; | |
2054 | u8 inner_vlan_removal_enable_flg; | |
2055 | u8 outer_vlan_removal_enable_flg; | |
a2fbb9ea | 2056 | u8 status_block_id; |
523224a3 DK |
2057 | u8 rx_sb_index_number; |
2058 | u8 reserved0[3]; | |
2059 | __le16 bd_buff_size; | |
2060 | __le16 sge_buff_size; | |
2061 | __le16 mtu; | |
2062 | struct regpair bd_page_base; | |
2063 | struct regpair sge_page_base; | |
2064 | struct regpair cqe_page_base; | |
2065 | u8 is_leading_rss; | |
2066 | u8 is_approx_mcast; | |
2067 | __le16 max_agg_size; | |
2068 | __le32 reserved2[3]; | |
2069 | }; | |
2070 | ||
2071 | /* | |
2072 | * client init tx data | |
2073 | */ | |
2074 | struct client_init_tx_data { | |
2075 | u8 enforce_security_flg; | |
2076 | u8 tx_status_block_id; | |
2077 | u8 tx_sb_index_number; | |
2078 | u8 reserved0; | |
2079 | __le16 mtu; | |
2080 | __le16 reserved1; | |
2081 | struct regpair tx_bd_page_base; | |
2082 | __le32 reserved2[2]; | |
a2fbb9ea ET |
2083 | }; |
2084 | ||
2085 | /* | |
523224a3 | 2086 | * client init ramrod data |
a2fbb9ea | 2087 | */ |
523224a3 DK |
2088 | struct client_init_ramrod_data { |
2089 | struct client_init_general_data general; | |
2090 | struct client_init_rx_data rx; | |
2091 | struct client_init_tx_data tx; | |
2092 | struct client_init_fc_data fc; | |
a2fbb9ea ET |
2093 | }; |
2094 | ||
523224a3 | 2095 | |
a2fbb9ea | 2096 | /* |
523224a3 | 2097 | * The data contain client ID need to the ramrod |
a2fbb9ea | 2098 | */ |
523224a3 DK |
2099 | struct eth_common_ramrod_data { |
2100 | u32 client_id; | |
2101 | u32 reserved1; | |
a2fbb9ea ET |
2102 | }; |
2103 | ||
2104 | ||
2105 | /* | |
523224a3 | 2106 | * union for sgl and raw data. |
a2fbb9ea | 2107 | */ |
523224a3 DK |
2108 | union eth_sgl_or_raw_data { |
2109 | __le16 sgl[8]; | |
2110 | u32 raw_data[4]; | |
a2fbb9ea ET |
2111 | }; |
2112 | ||
a2fbb9ea ET |
2113 | /* |
2114 | * regular eth FP CQE parameters struct | |
2115 | */ | |
2116 | struct eth_fast_path_rx_cqe { | |
34f80b04 EG |
2117 | u8 type_error_flags; |
2118 | #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0) | |
2119 | #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 | |
2120 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1) | |
2121 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1 | |
2122 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2) | |
2123 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2 | |
2124 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3) | |
2125 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3 | |
2126 | #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4) | |
2127 | #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4 | |
2128 | #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5) | |
2129 | #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5 | |
523224a3 DK |
2130 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6) |
2131 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6 | |
a2fbb9ea ET |
2132 | u8 status_flags; |
2133 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) | |
2134 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 | |
2135 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) | |
2136 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 | |
2137 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) | |
2138 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 | |
2139 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) | |
2140 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 | |
2141 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) | |
2142 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 | |
2143 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) | |
2144 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 | |
2145 | u8 placement_offset; | |
34f80b04 | 2146 | u8 queue_index; |
4781bfad EG |
2147 | __le32 rss_hash_result; |
2148 | __le16 vlan_tag; | |
2149 | __le16 pkt_len; | |
2150 | __le16 len_on_bd; | |
a2fbb9ea | 2151 | struct parsing_flags pars_flags; |
523224a3 | 2152 | union eth_sgl_or_raw_data sgl_or_raw_data; |
a2fbb9ea ET |
2153 | }; |
2154 | ||
2155 | ||
2156 | /* | |
2157 | * The data for RSS setup ramrod | |
2158 | */ | |
2159 | struct eth_halt_ramrod_data { | |
8d9c5f34 | 2160 | u32 client_id; |
a2fbb9ea ET |
2161 | u32 reserved0; |
2162 | }; | |
2163 | ||
34f80b04 EG |
2164 | /* |
2165 | * The data for statistics query ramrod | |
2166 | */ | |
523224a3 | 2167 | struct common_query_ramrod_data { |
34f80b04 EG |
2168 | #if defined(__BIG_ENDIAN) |
2169 | u8 reserved0; | |
8d9c5f34 | 2170 | u8 collect_port; |
34f80b04 EG |
2171 | u16 drv_counter; |
2172 | #elif defined(__LITTLE_ENDIAN) | |
2173 | u16 drv_counter; | |
8d9c5f34 | 2174 | u8 collect_port; |
34f80b04 EG |
2175 | u8 reserved0; |
2176 | #endif | |
2177 | u32 ctr_id_vector; | |
2178 | }; | |
2179 | ||
2180 | ||
a2fbb9ea ET |
2181 | /* |
2182 | * Place holder for ramrods protocol specific data | |
2183 | */ | |
2184 | struct ramrod_data { | |
4781bfad EG |
2185 | __le32 data_lo; |
2186 | __le32 data_hi; | |
a2fbb9ea ET |
2187 | }; |
2188 | ||
2189 | /* | |
33471629 | 2190 | * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) |
a2fbb9ea ET |
2191 | */ |
2192 | union eth_ramrod_data { | |
2193 | struct ramrod_data general; | |
2194 | }; | |
2195 | ||
2196 | ||
a2fbb9ea ET |
2197 | /* |
2198 | * Eth Rx Cqe structure- general structure for ramrods | |
2199 | */ | |
2200 | struct common_ramrod_eth_rx_cqe { | |
34f80b04 EG |
2201 | u8 ramrod_type; |
2202 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0) | |
2203 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 | |
3359fced VZ |
2204 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1) |
2205 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1 | |
2206 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2) | |
2207 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2 | |
8d9c5f34 | 2208 | u8 conn_type; |
4781bfad EG |
2209 | __le16 reserved1; |
2210 | __le32 conn_and_cmd_data; | |
a2fbb9ea ET |
2211 | #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) |
2212 | #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 | |
2213 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) | |
2214 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 | |
2215 | struct ramrod_data protocol_data; | |
4781bfad | 2216 | __le32 reserved2[4]; |
a2fbb9ea ET |
2217 | }; |
2218 | ||
2219 | /* | |
2220 | * Rx Last CQE in page (in ETH) | |
2221 | */ | |
2222 | struct eth_rx_cqe_next_page { | |
4781bfad EG |
2223 | __le32 addr_lo; |
2224 | __le32 addr_hi; | |
2225 | __le32 reserved[6]; | |
a2fbb9ea ET |
2226 | }; |
2227 | ||
2228 | /* | |
2229 | * union for all eth rx cqe types (fix their sizes) | |
2230 | */ | |
2231 | union eth_rx_cqe { | |
2232 | struct eth_fast_path_rx_cqe fast_path_cqe; | |
2233 | struct common_ramrod_eth_rx_cqe ramrod_cqe; | |
2234 | struct eth_rx_cqe_next_page next_page_cqe; | |
2235 | }; | |
2236 | ||
2237 | ||
2238 | /* | |
2239 | * common data for all protocols | |
2240 | */ | |
2241 | struct spe_hdr { | |
4781bfad | 2242 | __le32 conn_and_cmd_data; |
a2fbb9ea ET |
2243 | #define SPE_HDR_CID (0xFFFFFF<<0) |
2244 | #define SPE_HDR_CID_SHIFT 0 | |
2245 | #define SPE_HDR_CMD_ID (0xFF<<24) | |
2246 | #define SPE_HDR_CMD_ID_SHIFT 24 | |
4781bfad | 2247 | __le16 type; |
a2fbb9ea ET |
2248 | #define SPE_HDR_CONN_TYPE (0xFF<<0) |
2249 | #define SPE_HDR_CONN_TYPE_SHIFT 0 | |
523224a3 DK |
2250 | #define SPE_HDR_FUNCTION_ID (0xFF<<8) |
2251 | #define SPE_HDR_FUNCTION_ID_SHIFT 8 | |
2252 | __le16 reserved1; | |
a2fbb9ea ET |
2253 | }; |
2254 | ||
a2fbb9ea | 2255 | /* |
33471629 | 2256 | * Ethernet slow path element |
a2fbb9ea ET |
2257 | */ |
2258 | union eth_specific_data { | |
2259 | u8 protocol_data[8]; | |
523224a3 | 2260 | struct regpair client_init_ramrod_init_data; |
a2fbb9ea | 2261 | struct eth_halt_ramrod_data halt_ramrod_data; |
a2fbb9ea | 2262 | struct regpair update_data_addr; |
523224a3 | 2263 | struct eth_common_ramrod_data common_ramrod_data; |
a2fbb9ea ET |
2264 | }; |
2265 | ||
2266 | /* | |
33471629 | 2267 | * Ethernet slow path element |
a2fbb9ea ET |
2268 | */ |
2269 | struct eth_spe { | |
2270 | struct spe_hdr hdr; | |
2271 | union eth_specific_data data; | |
2272 | }; | |
2273 | ||
2274 | ||
2275 | /* | |
ca00392c | 2276 | * array of 13 bds as appears in the eth xstorm context |
a2fbb9ea | 2277 | */ |
ca00392c EG |
2278 | struct eth_tx_bds_array { |
2279 | union eth_tx_bd_types bds[13]; | |
a2fbb9ea ET |
2280 | }; |
2281 | ||
2282 | ||
2283 | /* | |
34f80b04 | 2284 | * Common configuration parameters per function in Tstorm |
a2fbb9ea ET |
2285 | */ |
2286 | struct tstorm_eth_function_common_config { | |
34f80b04 | 2287 | #if defined(__BIG_ENDIAN) |
523224a3 | 2288 | u8 reserved1; |
34f80b04 EG |
2289 | u8 rss_result_mask; |
2290 | u16 config_flags; | |
a2fbb9ea ET |
2291 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) |
2292 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 | |
2293 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) | |
2294 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 | |
2295 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) | |
2296 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 | |
2297 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) | |
2298 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 | |
8d9c5f34 EG |
2299 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) |
2300 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 | |
523224a3 DK |
2301 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7) |
2302 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7 | |
2303 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8) | |
2304 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8 | |
2305 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9) | |
2306 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9 | |
a2fbb9ea | 2307 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
2308 | u16 config_flags; |
2309 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) | |
2310 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 | |
2311 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) | |
2312 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 | |
2313 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) | |
2314 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 | |
2315 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) | |
2316 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 | |
8d9c5f34 EG |
2317 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) |
2318 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 | |
523224a3 DK |
2319 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7) |
2320 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7 | |
2321 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8) | |
2322 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8 | |
2323 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9) | |
2324 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9 | |
a2fbb9ea | 2325 | u8 rss_result_mask; |
523224a3 | 2326 | u8 reserved1; |
a2fbb9ea | 2327 | #endif |
34f80b04 | 2328 | u16 vlan_id[2]; |
a2fbb9ea ET |
2329 | }; |
2330 | ||
ca00392c EG |
2331 | /* |
2332 | * RSS idirection table update configuration | |
2333 | */ | |
2334 | struct rss_update_config { | |
2335 | #if defined(__BIG_ENDIAN) | |
2336 | u16 toe_rss_bitmap; | |
2337 | u16 flags; | |
2338 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) | |
2339 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 | |
2340 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) | |
2341 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 | |
2342 | #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) | |
2343 | #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 | |
2344 | #elif defined(__LITTLE_ENDIAN) | |
2345 | u16 flags; | |
2346 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) | |
2347 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 | |
2348 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) | |
2349 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 | |
2350 | #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) | |
2351 | #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 | |
2352 | u16 toe_rss_bitmap; | |
2353 | #endif | |
2354 | u32 reserved1; | |
2355 | }; | |
2356 | ||
a2fbb9ea ET |
2357 | /* |
2358 | * parameters for eth update ramrod | |
2359 | */ | |
2360 | struct eth_update_ramrod_data { | |
2361 | struct tstorm_eth_function_common_config func_config; | |
2362 | u8 indirectionTable[128]; | |
ca00392c | 2363 | struct rss_update_config rss_config; |
a2fbb9ea ET |
2364 | }; |
2365 | ||
2366 | ||
2367 | /* | |
2368 | * MAC filtering configuration command header | |
2369 | */ | |
2370 | struct mac_configuration_hdr { | |
8d9c5f34 | 2371 | u8 length; |
a2fbb9ea | 2372 | u8 offset; |
34f80b04 | 2373 | u16 client_id; |
523224a3 DK |
2374 | u16 echo; |
2375 | u16 reserved1; | |
a2fbb9ea ET |
2376 | }; |
2377 | ||
2378 | /* | |
2379 | * MAC address in list for ramrod | |
2380 | */ | |
523224a3 | 2381 | struct mac_configuration_entry { |
4781bfad EG |
2382 | __le16 lsb_mac_addr; |
2383 | __le16 middle_mac_addr; | |
2384 | __le16 msb_mac_addr; | |
523224a3 DK |
2385 | __le16 vlan_id; |
2386 | u8 pf_id; | |
a2fbb9ea | 2387 | u8 flags; |
523224a3 DK |
2388 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) |
2389 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 | |
2390 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) | |
2391 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 | |
2392 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) | |
2393 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 | |
2394 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) | |
2395 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 | |
2396 | #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) | |
2397 | #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 | |
2398 | #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) | |
2399 | #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 | |
2400 | u16 reserved0; | |
ca00392c | 2401 | u32 clients_bit_vector; |
a2fbb9ea ET |
2402 | }; |
2403 | ||
2404 | /* | |
523224a3 | 2405 | * MAC filtering configuration command |
a2fbb9ea ET |
2406 | */ |
2407 | struct mac_configuration_cmd { | |
2408 | struct mac_configuration_hdr hdr; | |
2409 | struct mac_configuration_entry config_table[64]; | |
2410 | }; | |
2411 | ||
2412 | ||
34f80b04 EG |
2413 | /* |
2414 | * approximate-match multicast filtering for E1H per function in Tstorm | |
2415 | */ | |
2416 | struct tstorm_eth_approximate_match_multicast_filtering { | |
2417 | u32 mcast_add_hash_bit_array[8]; | |
2418 | }; | |
2419 | ||
2420 | ||
a2fbb9ea ET |
2421 | /* |
2422 | * MAC filtering configuration parameters per port in Tstorm | |
2423 | */ | |
2424 | struct tstorm_eth_mac_filter_config { | |
2425 | u32 ucast_drop_all; | |
2426 | u32 ucast_accept_all; | |
2427 | u32 mcast_drop_all; | |
2428 | u32 mcast_accept_all; | |
2429 | u32 bcast_drop_all; | |
2430 | u32 bcast_accept_all; | |
34f80b04 | 2431 | u32 vlan_filter[2]; |
523224a3 | 2432 | u32 unmatched_unicast; |
34f80b04 | 2433 | u32 reserved; |
a2fbb9ea ET |
2434 | }; |
2435 | ||
2436 | ||
8d9c5f34 EG |
2437 | /* |
2438 | * common flag to indicate existance of TPA. | |
2439 | */ | |
2440 | struct tstorm_eth_tpa_exist { | |
2441 | #if defined(__BIG_ENDIAN) | |
2442 | u16 reserved1; | |
2443 | u8 reserved0; | |
2444 | u8 tpa_exist; | |
2445 | #elif defined(__LITTLE_ENDIAN) | |
2446 | u8 tpa_exist; | |
2447 | u8 reserved0; | |
2448 | u16 reserved1; | |
2449 | #endif | |
2450 | u32 reserved2; | |
2451 | }; | |
2452 | ||
2453 | ||
34f80b04 EG |
2454 | /* |
2455 | * Three RX producers for ETH | |
2456 | */ | |
8d9c5f34 | 2457 | struct ustorm_eth_rx_producers { |
a2fbb9ea | 2458 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
2459 | u16 bd_prod; |
2460 | u16 cqe_prod; | |
a2fbb9ea | 2461 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
2462 | u16 cqe_prod; |
2463 | u16 bd_prod; | |
a2fbb9ea | 2464 | #endif |
a2fbb9ea | 2465 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
2466 | u16 reserved; |
2467 | u16 sge_prod; | |
a2fbb9ea | 2468 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
2469 | u16 sge_prod; |
2470 | u16 reserved; | |
a2fbb9ea | 2471 | #endif |
a2fbb9ea ET |
2472 | }; |
2473 | ||
a2fbb9ea | 2474 | |
523224a3 DK |
2475 | /* |
2476 | * cfc delete event data | |
2477 | */ | |
2478 | struct cfc_del_event_data { | |
2479 | u32 cid; | |
2480 | u8 error; | |
2481 | u8 reserved0; | |
2482 | u16 reserved1; | |
2483 | u32 reserved2; | |
2484 | }; | |
2485 | ||
2486 | ||
34f80b04 EG |
2487 | /* |
2488 | * per-port SAFC demo variables | |
2489 | */ | |
2490 | struct cmng_flags_per_port { | |
a2fbb9ea | 2491 | u8 con_number[NUM_OF_PROTOCOLS]; |
8a1c38d1 EG |
2492 | u32 cmng_enables; |
2493 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) | |
2494 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 | |
2495 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) | |
2496 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 | |
2497 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2) | |
2498 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2 | |
2499 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3) | |
2500 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3 | |
2501 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4) | |
2502 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4 | |
523224a3 DK |
2503 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5) |
2504 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5 | |
2505 | #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6) | |
2506 | #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6 | |
a2fbb9ea ET |
2507 | }; |
2508 | ||
34f80b04 EG |
2509 | |
2510 | /* | |
2511 | * per-port rate shaping variables | |
2512 | */ | |
2513 | struct rate_shaping_vars_per_port { | |
2514 | u32 rs_periodic_timeout; | |
2515 | u32 rs_threshold; | |
2516 | }; | |
2517 | ||
34f80b04 EG |
2518 | /* |
2519 | * per-port fairness variables | |
2520 | */ | |
2521 | struct fairness_vars_per_port { | |
2522 | u32 upper_bound; | |
2523 | u32 fair_threshold; | |
2524 | u32 fairness_timeout; | |
2525 | }; | |
2526 | ||
34f80b04 EG |
2527 | /* |
2528 | * per-port SAFC variables | |
2529 | */ | |
2530 | struct safc_struct_per_port { | |
2531 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
2532 | u16 __reserved1; |
2533 | u8 __reserved0; | |
34f80b04 EG |
2534 | u8 safc_timeout_usec; |
2535 | #elif defined(__LITTLE_ENDIAN) | |
2536 | u8 safc_timeout_usec; | |
8d9c5f34 EG |
2537 | u8 __reserved0; |
2538 | u16 __reserved1; | |
34f80b04 | 2539 | #endif |
523224a3 DK |
2540 | u8 cos_to_traffic_types[MAX_COS_NUMBER]; |
2541 | u32 __reserved2; | |
8d9c5f34 | 2542 | u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; |
a2fbb9ea ET |
2543 | }; |
2544 | ||
523224a3 DK |
2545 | /* |
2546 | * per-port PFC variables | |
2547 | */ | |
2548 | struct pfc_struct_per_port { | |
2549 | u8 priority_to_traffic_types[MAX_PFC_PRIORITIES]; | |
2550 | #if defined(__BIG_ENDIAN) | |
2551 | u16 pfc_pause_quanta_in_nanosec; | |
2552 | u8 __reserved0; | |
2553 | u8 priority_non_pausable_mask; | |
2554 | #elif defined(__LITTLE_ENDIAN) | |
2555 | u8 priority_non_pausable_mask; | |
2556 | u8 __reserved0; | |
2557 | u16 pfc_pause_quanta_in_nanosec; | |
2558 | #endif | |
2559 | }; | |
2560 | ||
2561 | /* | |
2562 | * Priority and cos | |
2563 | */ | |
2564 | struct priority_cos { | |
2565 | #if defined(__BIG_ENDIAN) | |
2566 | u16 reserved1; | |
2567 | u8 cos; | |
2568 | u8 priority; | |
2569 | #elif defined(__LITTLE_ENDIAN) | |
2570 | u8 priority; | |
2571 | u8 cos; | |
2572 | u16 reserved1; | |
2573 | #endif | |
2574 | u32 reserved2; | |
2575 | }; | |
2576 | ||
34f80b04 EG |
2577 | /* |
2578 | * Per-port congestion management variables | |
2579 | */ | |
2580 | struct cmng_struct_per_port { | |
2581 | struct rate_shaping_vars_per_port rs_vars; | |
2582 | struct fairness_vars_per_port fair_vars; | |
2583 | struct safc_struct_per_port safc_vars; | |
523224a3 DK |
2584 | struct pfc_struct_per_port pfc_vars; |
2585 | #if defined(__BIG_ENDIAN) | |
2586 | u16 __reserved1; | |
2587 | u8 dcb_enabled; | |
2588 | u8 llfc_mode; | |
2589 | #elif defined(__LITTLE_ENDIAN) | |
2590 | u8 llfc_mode; | |
2591 | u8 dcb_enabled; | |
2592 | u16 __reserved1; | |
2593 | #endif | |
2594 | struct priority_cos | |
2595 | traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES]; | |
34f80b04 | 2596 | struct cmng_flags_per_port flags; |
a2fbb9ea ET |
2597 | }; |
2598 | ||
2599 | ||
523224a3 DK |
2600 | |
2601 | /* | |
2602 | * Dynamic HC counters set by the driver | |
2603 | */ | |
2604 | struct hc_dynamic_drv_counter { | |
2605 | u32 val[HC_SB_MAX_DYNAMIC_INDICES]; | |
2606 | }; | |
2607 | ||
2608 | /* | |
2609 | * zone A per-queue data | |
2610 | */ | |
2611 | struct cstorm_queue_zone_data { | |
2612 | struct hc_dynamic_drv_counter hc_dyn_drv_cnt; | |
2613 | struct regpair reserved[2]; | |
2614 | }; | |
2615 | ||
ca00392c EG |
2616 | /* |
2617 | * Dynamic host coalescing init parameters | |
2618 | */ | |
2619 | struct dynamic_hc_config { | |
2620 | u32 threshold[3]; | |
523224a3 DK |
2621 | u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; |
2622 | u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; | |
2623 | u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; | |
2624 | u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; | |
2625 | u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; | |
ca00392c EG |
2626 | }; |
2627 | ||
2628 | ||
a2fbb9ea | 2629 | /* |
bb2a0f7a | 2630 | * Protocol-common statistics collected by the Xstorm (per client) |
a2fbb9ea | 2631 | */ |
bb2a0f7a | 2632 | struct xstorm_per_client_stats { |
ca00392c | 2633 | __le32 reserved0; |
4781bfad | 2634 | __le32 unicast_pkts_sent; |
a2fbb9ea ET |
2635 | struct regpair unicast_bytes_sent; |
2636 | struct regpair multicast_bytes_sent; | |
4781bfad EG |
2637 | __le32 multicast_pkts_sent; |
2638 | __le32 broadcast_pkts_sent; | |
a2fbb9ea | 2639 | struct regpair broadcast_bytes_sent; |
4781bfad | 2640 | __le16 stats_counter; |
ca00392c EG |
2641 | __le16 reserved1; |
2642 | __le32 reserved2; | |
a2fbb9ea ET |
2643 | }; |
2644 | ||
bb2a0f7a YG |
2645 | /* |
2646 | * Common statistics collected by the Xstorm (per port) | |
2647 | */ | |
2648 | struct xstorm_common_stats { | |
523224a3 | 2649 | struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID]; |
bb2a0f7a YG |
2650 | }; |
2651 | ||
bb2a0f7a YG |
2652 | /* |
2653 | * Protocol-common statistics collected by the Tstorm (per port) | |
2654 | */ | |
2655 | struct tstorm_per_port_stats { | |
4781bfad EG |
2656 | __le32 mac_filter_discard; |
2657 | __le32 xxoverflow_discard; | |
2658 | __le32 brb_truncate_discard; | |
2659 | __le32 mac_discard; | |
bb2a0f7a YG |
2660 | }; |
2661 | ||
a2fbb9ea ET |
2662 | /* |
2663 | * Protocol-common statistics collected by the Tstorm (per client) | |
2664 | */ | |
2665 | struct tstorm_per_client_stats { | |
a2fbb9ea ET |
2666 | struct regpair rcv_unicast_bytes; |
2667 | struct regpair rcv_broadcast_bytes; | |
2668 | struct regpair rcv_multicast_bytes; | |
2669 | struct regpair rcv_error_bytes; | |
4781bfad EG |
2670 | __le32 checksum_discard; |
2671 | __le32 packets_too_big_discard; | |
4781bfad EG |
2672 | __le32 rcv_unicast_pkts; |
2673 | __le32 rcv_broadcast_pkts; | |
2674 | __le32 rcv_multicast_pkts; | |
2675 | __le32 no_buff_discard; | |
2676 | __le32 ttl0_discard; | |
2677 | __le16 stats_counter; | |
2678 | __le16 reserved0; | |
a2fbb9ea ET |
2679 | }; |
2680 | ||
2681 | /* | |
bb2a0f7a | 2682 | * Protocol-common statistics collected by the Tstorm |
a2fbb9ea ET |
2683 | */ |
2684 | struct tstorm_common_stats { | |
bb2a0f7a | 2685 | struct tstorm_per_port_stats port_statistics; |
523224a3 | 2686 | struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID]; |
a2fbb9ea ET |
2687 | }; |
2688 | ||
de832a55 EG |
2689 | /* |
2690 | * Protocol-common statistics collected by the Ustorm (per client) | |
2691 | */ | |
2692 | struct ustorm_per_client_stats { | |
2693 | struct regpair ucast_no_buff_bytes; | |
2694 | struct regpair mcast_no_buff_bytes; | |
2695 | struct regpair bcast_no_buff_bytes; | |
2696 | __le32 ucast_no_buff_pkts; | |
2697 | __le32 mcast_no_buff_pkts; | |
2698 | __le32 bcast_no_buff_pkts; | |
2699 | __le16 stats_counter; | |
2700 | __le16 reserved0; | |
2701 | }; | |
2702 | ||
2703 | /* | |
2704 | * Protocol-common statistics collected by the Ustorm | |
2705 | */ | |
2706 | struct ustorm_common_stats { | |
523224a3 | 2707 | struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID]; |
de832a55 EG |
2708 | }; |
2709 | ||
a2fbb9ea | 2710 | /* |
33471629 | 2711 | * Eth statistics query structure for the eth_stats_query ramrod |
a2fbb9ea ET |
2712 | */ |
2713 | struct eth_stats_query { | |
2714 | struct xstorm_common_stats xstorm_common; | |
2715 | struct tstorm_common_stats tstorm_common; | |
de832a55 | 2716 | struct ustorm_common_stats ustorm_common; |
a2fbb9ea ET |
2717 | }; |
2718 | ||
2719 | ||
523224a3 DK |
2720 | /* |
2721 | * set mac event data | |
2722 | */ | |
2723 | struct set_mac_event_data { | |
2724 | u16 echo; | |
2725 | u16 reserved0; | |
2726 | u32 reserved1; | |
2727 | u32 reserved2; | |
2728 | }; | |
2729 | ||
2730 | /* | |
2731 | * union for all event ring message types | |
2732 | */ | |
2733 | union event_data { | |
2734 | struct set_mac_event_data set_mac_event; | |
2735 | struct cfc_del_event_data cfc_del_event; | |
2736 | }; | |
2737 | ||
2738 | ||
2739 | /* | |
2740 | * per PF event ring data | |
2741 | */ | |
2742 | struct event_ring_data { | |
2743 | struct regpair base_addr; | |
2744 | #if defined(__BIG_ENDIAN) | |
2745 | u8 index_id; | |
2746 | u8 sb_id; | |
2747 | u16 producer; | |
2748 | #elif defined(__LITTLE_ENDIAN) | |
2749 | u16 producer; | |
2750 | u8 sb_id; | |
2751 | u8 index_id; | |
2752 | #endif | |
2753 | u32 reserved0; | |
2754 | }; | |
2755 | ||
2756 | ||
2757 | /* | |
2758 | * event ring message element (each element is 128 bits) | |
2759 | */ | |
2760 | struct event_ring_msg { | |
2761 | u8 opcode; | |
2762 | u8 reserved0; | |
2763 | u16 reserved1; | |
2764 | union event_data data; | |
2765 | }; | |
2766 | ||
2767 | /* | |
2768 | * event ring next page element (128 bits) | |
2769 | */ | |
2770 | struct event_ring_next { | |
2771 | struct regpair addr; | |
2772 | u32 reserved[2]; | |
2773 | }; | |
2774 | ||
2775 | /* | |
2776 | * union for event ring element types (each element is 128 bits) | |
2777 | */ | |
2778 | union event_ring_elem { | |
2779 | struct event_ring_msg message; | |
2780 | struct event_ring_next next_page; | |
2781 | }; | |
2782 | ||
2783 | ||
34f80b04 EG |
2784 | /* |
2785 | * per-vnic fairness variables | |
2786 | */ | |
2787 | struct fairness_vars_per_vn { | |
8a1c38d1 | 2788 | u32 cos_credit_delta[MAX_COS_NUMBER]; |
34f80b04 EG |
2789 | u32 protocol_credit_delta[NUM_OF_PROTOCOLS]; |
2790 | u32 vn_credit_delta; | |
2791 | u32 __reserved0; | |
2792 | }; | |
2793 | ||
2794 | ||
a2fbb9ea ET |
2795 | /* |
2796 | * FW version stored in the Xstorm RAM | |
2797 | */ | |
2798 | struct fw_version { | |
2799 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
2800 | u8 engineering; |
2801 | u8 revision; | |
2802 | u8 minor; | |
2803 | u8 major; | |
a2fbb9ea | 2804 | #elif defined(__LITTLE_ENDIAN) |
8d9c5f34 EG |
2805 | u8 major; |
2806 | u8 minor; | |
2807 | u8 revision; | |
2808 | u8 engineering; | |
a2fbb9ea ET |
2809 | #endif |
2810 | u32 flags; | |
2811 | #define FW_VERSION_OPTIMIZED (0x1<<0) | |
2812 | #define FW_VERSION_OPTIMIZED_SHIFT 0 | |
2813 | #define FW_VERSION_BIG_ENDIEN (0x1<<1) | |
2814 | #define FW_VERSION_BIG_ENDIEN_SHIFT 1 | |
34f80b04 EG |
2815 | #define FW_VERSION_CHIP_VERSION (0x3<<2) |
2816 | #define FW_VERSION_CHIP_VERSION_SHIFT 2 | |
2817 | #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) | |
2818 | #define __FW_VERSION_RESERVED_SHIFT 4 | |
a2fbb9ea ET |
2819 | }; |
2820 | ||
2821 | ||
523224a3 DK |
2822 | /* |
2823 | * Dynamic Host-Coalescing - Driver(host) counters | |
2824 | */ | |
2825 | struct hc_dynamic_sb_drv_counters { | |
2826 | u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; | |
2827 | }; | |
2828 | ||
2829 | ||
2830 | /* | |
2831 | * 2 bytes. configuration/state parameters for a single protocol index | |
2832 | */ | |
2833 | struct hc_index_data { | |
2834 | #if defined(__BIG_ENDIAN) | |
2835 | u8 flags; | |
2836 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
2837 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
2838 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
2839 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
2840 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
2841 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
2842 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
2843 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
2844 | u8 timeout; | |
2845 | #elif defined(__LITTLE_ENDIAN) | |
2846 | u8 timeout; | |
2847 | u8 flags; | |
2848 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
2849 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
2850 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
2851 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
2852 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
2853 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
2854 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
2855 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
2856 | #endif | |
2857 | }; | |
2858 | ||
2859 | ||
2860 | /* | |
2861 | * HC state-machine | |
2862 | */ | |
2863 | struct hc_status_block_sm { | |
2864 | #if defined(__BIG_ENDIAN) | |
2865 | u8 igu_seg_id; | |
2866 | u8 igu_sb_id; | |
2867 | u8 timer_value; | |
2868 | u8 __flags; | |
2869 | #elif defined(__LITTLE_ENDIAN) | |
2870 | u8 __flags; | |
2871 | u8 timer_value; | |
2872 | u8 igu_sb_id; | |
2873 | u8 igu_seg_id; | |
2874 | #endif | |
2875 | u32 time_to_expire; | |
2876 | }; | |
2877 | ||
2878 | /* | |
2879 | * hold PCI identification variables- used in various places in firmware | |
2880 | */ | |
2881 | struct pci_entity { | |
2882 | #if defined(__BIG_ENDIAN) | |
2883 | u8 vf_valid; | |
2884 | u8 vf_id; | |
2885 | u8 vnic_id; | |
2886 | u8 pf_id; | |
2887 | #elif defined(__LITTLE_ENDIAN) | |
2888 | u8 pf_id; | |
2889 | u8 vnic_id; | |
2890 | u8 vf_id; | |
2891 | u8 vf_valid; | |
2892 | #endif | |
2893 | }; | |
2894 | ||
2895 | /* | |
2896 | * The fast-path status block meta-data, common to all chips | |
2897 | */ | |
2898 | struct hc_sb_data { | |
2899 | struct regpair host_sb_addr; | |
2900 | struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; | |
2901 | struct pci_entity p_func; | |
2902 | #if defined(__BIG_ENDIAN) | |
2903 | u8 rsrv0; | |
2904 | u8 dhc_qzone_id; | |
2905 | u8 __dynamic_hc_level; | |
2906 | u8 same_igu_sb_1b; | |
2907 | #elif defined(__LITTLE_ENDIAN) | |
2908 | u8 same_igu_sb_1b; | |
2909 | u8 __dynamic_hc_level; | |
2910 | u8 dhc_qzone_id; | |
2911 | u8 rsrv0; | |
2912 | #endif | |
2913 | struct regpair rsrv1[2]; | |
2914 | }; | |
2915 | ||
2916 | ||
2917 | /* | |
2918 | * The fast-path status block meta-data | |
2919 | */ | |
2920 | struct hc_sp_status_block_data { | |
2921 | struct regpair host_sb_addr; | |
2922 | #if defined(__BIG_ENDIAN) | |
2923 | u16 rsrv; | |
2924 | u8 igu_seg_id; | |
2925 | u8 igu_sb_id; | |
2926 | #elif defined(__LITTLE_ENDIAN) | |
2927 | u8 igu_sb_id; | |
2928 | u8 igu_seg_id; | |
2929 | u16 rsrv; | |
2930 | #endif | |
2931 | struct pci_entity p_func; | |
2932 | }; | |
2933 | ||
2934 | ||
2935 | /* | |
2936 | * The fast-path status block meta-data | |
2937 | */ | |
2938 | struct hc_status_block_data_e1x { | |
2939 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; | |
2940 | struct hc_sb_data common; | |
2941 | }; | |
2942 | ||
2943 | ||
2944 | /* | |
2945 | * The fast-path status block meta-data | |
2946 | */ | |
2947 | struct hc_status_block_data_e2 { | |
2948 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; | |
2949 | struct hc_sb_data common; | |
2950 | }; | |
2951 | ||
2952 | ||
a2fbb9ea ET |
2953 | /* |
2954 | * FW version stored in first line of pram | |
2955 | */ | |
2956 | struct pram_fw_version { | |
8d9c5f34 EG |
2957 | u8 major; |
2958 | u8 minor; | |
2959 | u8 revision; | |
2960 | u8 engineering; | |
a2fbb9ea ET |
2961 | u8 flags; |
2962 | #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) | |
2963 | #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 | |
2964 | #define PRAM_FW_VERSION_STORM_ID (0x3<<1) | |
2965 | #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 | |
2966 | #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) | |
2967 | #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 | |
34f80b04 EG |
2968 | #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) |
2969 | #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 | |
2970 | #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) | |
2971 | #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 | |
2972 | }; | |
2973 | ||
2974 | ||
523224a3 DK |
2975 | /* |
2976 | * Ethernet slow path element | |
2977 | */ | |
2978 | union protocol_common_specific_data { | |
2979 | u8 protocol_data[8]; | |
2980 | struct regpair phy_address; | |
2981 | struct regpair mac_config_addr; | |
2982 | struct common_query_ramrod_data query_ramrod_data; | |
2983 | }; | |
2984 | ||
ca00392c EG |
2985 | /* |
2986 | * The send queue element | |
2987 | */ | |
2988 | struct protocol_common_spe { | |
2989 | struct spe_hdr hdr; | |
523224a3 | 2990 | union protocol_common_specific_data data; |
ca00392c EG |
2991 | }; |
2992 | ||
2993 | ||
34f80b04 EG |
2994 | /* |
2995 | * a single rate shaping counter. can be used as protocol or vnic counter | |
2996 | */ | |
2997 | struct rate_shaping_counter { | |
2998 | u32 quota; | |
2999 | #if defined(__BIG_ENDIAN) | |
3000 | u16 __reserved0; | |
3001 | u16 rate; | |
3002 | #elif defined(__LITTLE_ENDIAN) | |
3003 | u16 rate; | |
3004 | u16 __reserved0; | |
3005 | #endif | |
3006 | }; | |
3007 | ||
3008 | ||
3009 | /* | |
3010 | * per-vnic rate shaping variables | |
3011 | */ | |
3012 | struct rate_shaping_vars_per_vn { | |
3013 | struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS]; | |
3014 | struct rate_shaping_counter vn_counter; | |
a2fbb9ea ET |
3015 | }; |
3016 | ||
3017 | ||
3018 | /* | |
3019 | * The send queue element | |
3020 | */ | |
3021 | struct slow_path_element { | |
3022 | struct spe_hdr hdr; | |
523224a3 | 3023 | struct regpair protocol_data; |
a2fbb9ea ET |
3024 | }; |
3025 | ||
3026 | ||
3027 | /* | |
3028 | * eth/toe flags that indicate if to query | |
3029 | */ | |
3030 | struct stats_indication_flags { | |
3031 | u32 collect_eth; | |
3032 | u32 collect_toe; | |
3033 | }; | |
3034 | ||
3035 | ||
523224a3 DK |
3036 | /* |
3037 | * per-port PFC variables | |
3038 | */ | |
3039 | struct storm_pfc_struct_per_port { | |
3040 | #if defined(__BIG_ENDIAN) | |
3041 | u16 mid_mac_addr; | |
3042 | u16 msb_mac_addr; | |
3043 | #elif defined(__LITTLE_ENDIAN) | |
3044 | u16 msb_mac_addr; | |
3045 | u16 mid_mac_addr; | |
3046 | #endif | |
3047 | #if defined(__BIG_ENDIAN) | |
3048 | u16 pfc_pause_quanta_in_nanosec; | |
3049 | u16 lsb_mac_addr; | |
3050 | #elif defined(__LITTLE_ENDIAN) | |
3051 | u16 lsb_mac_addr; | |
3052 | u16 pfc_pause_quanta_in_nanosec; | |
3053 | #endif | |
3054 | }; | |
3055 | ||
3056 | /* | |
3057 | * Per-port congestion management variables | |
3058 | */ | |
3059 | struct storm_cmng_struct_per_port { | |
3060 | struct storm_pfc_struct_per_port pfc_vars; | |
3061 | }; | |
3062 | ||
3063 | ||
3064 | /* | |
3065 | * zone A per-queue data | |
3066 | */ | |
3067 | struct tstorm_queue_zone_data { | |
3068 | struct regpair reserved[4]; | |
3069 | }; | |
3070 | ||
3071 | ||
3072 | /* | |
3073 | * zone B per-VF data | |
3074 | */ | |
3075 | struct tstorm_vf_zone_data { | |
3076 | struct regpair reserved; | |
3077 | }; | |
3078 | ||
3079 | ||
3080 | /* | |
3081 | * zone A per-queue data | |
3082 | */ | |
3083 | struct ustorm_queue_zone_data { | |
3084 | struct ustorm_eth_rx_producers eth_rx_producers; | |
3085 | struct regpair reserved[3]; | |
3086 | }; | |
3087 | ||
3088 | ||
3089 | /* | |
3090 | * zone B per-VF data | |
3091 | */ | |
3092 | struct ustorm_vf_zone_data { | |
3093 | struct regpair reserved; | |
3094 | }; | |
3095 | ||
3096 | ||
3097 | /* | |
3098 | * data per VF-PF channel | |
3099 | */ | |
3100 | struct vf_pf_channel_data { | |
3101 | #if defined(__BIG_ENDIAN) | |
3102 | u16 reserved0; | |
3103 | u8 valid; | |
3104 | u8 state; | |
3105 | #elif defined(__LITTLE_ENDIAN) | |
3106 | u8 state; | |
3107 | u8 valid; | |
3108 | u16 reserved0; | |
3109 | #endif | |
3110 | u32 reserved1; | |
3111 | }; | |
3112 | ||
3113 | ||
3114 | /* | |
3115 | * zone A per-queue data | |
3116 | */ | |
3117 | struct xstorm_queue_zone_data { | |
3118 | struct regpair reserved[4]; | |
3119 | }; | |
3120 | ||
3121 | ||
3122 | /* | |
3123 | * zone B per-VF data | |
3124 | */ | |
3125 | struct xstorm_vf_zone_data { | |
3126 | struct regpair reserved; | |
3127 | }; | |
3128 | ||
3129 | #endif /* BNX2X_HSI_H */ |