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[mirror_ubuntu-kernels.git] / drivers / net / bnx2x / bnx2x_link.c
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cd88ccee 1/* Copyright 2008-2011 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
7995c64e
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
ea4e040a
YR		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
ea4e040a 26
ea4e040a
YR		 27#include "bnx2x.h"
28
29/********************************************************/
3196a88a 30#define ETH_HLEN 14
cd88ccee
YR		 31/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
32#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
ea4e040a
YR		 33#define ETH_MIN_PACKET_SIZE 60
34#define ETH_MAX_PACKET_SIZE 1500
35#define ETH_MAX_JUMBO_PACKET_SIZE 9600
36#define MDIO_ACCESS_TIMEOUT 1000
cd88ccee 37#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 38
39/***********************************************************/
3196a88a 40/* Shortcut definitions */
ea4e040a
YR		 41/***********************************************************/
42
2f904460
EG		 43#define NIG_LATCH_BC_ENABLE_MI_INT 0
44
45#define NIG_STATUS_EMAC0_MI_INT \
46 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 47#define NIG_STATUS_XGXS0_LINK10G \
48 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
49#define NIG_STATUS_XGXS0_LINK_STATUS \
50 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
51#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
52 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
53#define NIG_STATUS_SERDES0_LINK_STATUS \
54 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
55#define NIG_MASK_MI_INT \
56 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
57#define NIG_MASK_XGXS0_LINK10G \
58 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
59#define NIG_MASK_XGXS0_LINK_STATUS \
60 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
61#define NIG_MASK_SERDES0_LINK_STATUS \
62 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
63
64#define MDIO_AN_CL73_OR_37_COMPLETE \
65 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
66 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
67
68#define XGXS_RESET_BITS \
69 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
73 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
74
75#define SERDES_RESET_BITS \
76 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
80
81#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
82#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
cd88ccee 83#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
3196a88a 84#define AUTONEG_PARALLEL \
ea4e040a 85 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 86#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 87 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 88#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 89
90#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
91 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
92#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
93 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
94#define GP_STATUS_SPEED_MASK \
95 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
96#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
97#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
98#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
99#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
100#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
101#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
102#define GP_STATUS_10G_HIG \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
104#define GP_STATUS_10G_CX4 \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
106#define GP_STATUS_12G_HIG \
107 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
108#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
109#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
110#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
111#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
112#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
113#define GP_STATUS_10G_KX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
115
cd88ccee
YR		 116#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
117#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
ea4e040a 118#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
cd88ccee 119#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
ea4e040a
YR		 120#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
121#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
122#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
123#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
124#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
125#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
126#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
cd88ccee
YR		 127#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
128#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
129#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
130#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
ea4e040a
YR		 131#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
132#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
cd88ccee
YR		 133#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
134#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
135#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
136#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
137#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
138#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
ea4e040a
YR		 139
140#define PHY_XGXS_FLAG 0x1
141#define PHY_SGMII_FLAG 0x2
142#define PHY_SERDES_FLAG 0x4
143
589abe3a
EG		 144/* */
145#define SFP_EEPROM_CON_TYPE_ADDR 0x2
cd88ccee 146 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
589abe3a
EG		 147 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
148
4d295db0
EG		 149
150#define SFP_EEPROM_COMP_CODE_ADDR 0x3
151 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
152 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
153 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
154
589abe3a
EG		 155#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
cd88ccee 157 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 158
cd88ccee 159#define SFP_EEPROM_OPTIONS_ADDR 0x40
589abe3a 160 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
cd88ccee 161#define SFP_EEPROM_OPTIONS_SIZE 2
589abe3a 162
cd88ccee
YR		 163#define EDC_MODE_LINEAR 0x0022
164#define EDC_MODE_LIMITING 0x0044
165#define EDC_MODE_PASSIVE_DAC 0x0055
4d295db0
EG		 166
167
bcab15c5
VZ		 168#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
169#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
ea4e040a
YR		 170/**********************************************************/
171/* INTERFACE */
172/**********************************************************/
e10bc84d 173
cd2be89b 174#define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 175 bnx2x_cl45_write(_bp, _phy, \
7aa0711f 176 (_phy)->def_md_devad, \
ea4e040a
YR		 177 (_bank + (_addr & 0xf)), \
178 _val)
179
cd2be89b 180#define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 181 bnx2x_cl45_read(_bp, _phy, \
7aa0711f 182 (_phy)->def_md_devad, \
ea4e040a
YR		 183 (_bank + (_addr & 0xf)), \
184 _val)
185
ea4e040a
YR		 186static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
187{
188 u32 val = REG_RD(bp, reg);
189
190 val |= bits;
191 REG_WR(bp, reg, val);
192 return val;
193}
194
195static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
196{
197 u32 val = REG_RD(bp, reg);
198
199 val &= ~bits;
200 REG_WR(bp, reg, val);
201 return val;
202}
203
bcab15c5
VZ		 204/******************************************************************/
205/* ETS section */
206/******************************************************************/
207void bnx2x_ets_disabled(struct link_params *params)
208{
209 /* ETS disabled configuration*/
210 struct bnx2x *bp = params->bp;
211
212 DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
213
2cf7acf9 214 /*
bcab15c5
VZ		 215 * mapping between entry priority to client number (0,1,2 -debug and
216 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
217 * 3bits client num.
218 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
219 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
220 */
221
222 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
2cf7acf9 223 /*
bcab15c5
VZ		 224 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
225 * as strict. Bits 0,1,2 - debug and management entries, 3 -
226 * COS0 entry, 4 - COS1 entry.
227 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
228 * bit4 bit3 bit2 bit1 bit0
229 * MCP and debug are strict
230 */
231
232 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
233 /* defines which entries (clients) are subjected to WFQ arbitration */
234 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
2cf7acf9
YR		 235 /*
236 * For strict priority entries defines the number of consecutive
237 * slots for the highest priority.
238 */
bcab15c5 239 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2cf7acf9 240 /*
bcab15c5
VZ		 241 * mapping between the CREDIT_WEIGHT registers and actual client
242 * numbers
243 */
244 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
246 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
247
248 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
249 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
250 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
251 /* ETS mode disable */
252 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
2cf7acf9 253 /*
bcab15c5
VZ		 254 * If ETS mode is enabled (there is no strict priority) defines a WFQ
255 * weight for COS0/COS1.
256 */
257 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
258 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
259 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
260 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
261 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
262 /* Defines the number of consecutive slots for the strict priority */
263 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
264}
265
65a001ba 266static void bnx2x_ets_bw_limit_common(const struct link_params *params)
bcab15c5
VZ		 267{
268 /* ETS disabled configuration */
269 struct bnx2x *bp = params->bp;
270 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
2cf7acf9
YR		 271 /*
272 * defines which entries (clients) are subjected to WFQ arbitration
273 * COS0 0x8
274 * COS1 0x10
275 */
bcab15c5 276 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
2cf7acf9
YR		 277 /*
278 * mapping between the ARB_CREDIT_WEIGHT registers and actual
279 * client numbers (WEIGHT_0 does not actually have to represent
280 * client 0)
281 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
282 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
283 */
bcab15c5
VZ		 284 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
285
286 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
287 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
288 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
289 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
290
291 /* ETS mode enabled*/
292 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
293
294 /* Defines the number of consecutive slots for the strict priority */
295 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
2cf7acf9
YR		 296 /*
297 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
298 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
299 * entry, 4 - COS1 entry.
300 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
301 * bit4 bit3 bit2 bit1 bit0
302 * MCP and debug are strict
303 */
bcab15c5
VZ		 304 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
305
306 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
307 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
308 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
309 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
310 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
311}
312
313void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
314 const u32 cos1_bw)
315{
316 /* ETS disabled configuration*/
317 struct bnx2x *bp = params->bp;
318 const u32 total_bw = cos0_bw + cos1_bw;
319 u32 cos0_credit_weight = 0;
320 u32 cos1_credit_weight = 0;
321
322 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
323
324 if ((0 == total_bw) ||
325 (0 == cos0_bw) ||
326 (0 == cos1_bw)) {
cd88ccee 327 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
bcab15c5
VZ		 328 return;
329 }
330
331 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
332 total_bw;
333 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
334 total_bw;
335
336 bnx2x_ets_bw_limit_common(params);
337
338 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
339 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
340
341 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
342 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
343}
344
345u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
346{
347 /* ETS disabled configuration*/
348 struct bnx2x *bp = params->bp;
349 u32 val = 0;
350
bcab15c5 351 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
2cf7acf9 352 /*
bcab15c5
VZ		 353 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
354 * as strict. Bits 0,1,2 - debug and management entries,
355 * 3 - COS0 entry, 4 - COS1 entry.
356 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
357 * bit4 bit3 bit2 bit1 bit0
358 * MCP and debug are strict
359 */
360 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2cf7acf9 361 /*
bcab15c5
VZ		 362 * For strict priority entries defines the number of consecutive slots
363 * for the highest priority.
364 */
365 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
366 /* ETS mode disable */
367 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
368 /* Defines the number of consecutive slots for the strict priority */
369 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
370
371 /* Defines the number of consecutive slots for the strict priority */
372 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
373
2cf7acf9
YR		 374 /*
375 * mapping between entry priority to client number (0,1,2 -debug and
376 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
377 * 3bits client num.
378 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
379 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
380 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
381 */
bcab15c5
VZ		 382 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
383 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
384
385 return 0;
386}
387/******************************************************************/
388/* ETS section */
389/******************************************************************/
390
391static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
392 u32 pfc_frames_sent[2],
393 u32 pfc_frames_received[2])
394{
395 /* Read pfc statistic */
396 struct bnx2x *bp = params->bp;
397 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
398 NIG_REG_INGRESS_BMAC0_MEM;
399
400 DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
401
402 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
403 pfc_frames_sent, 2);
404
405 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
406 pfc_frames_received, 2);
407
408}
409static void bnx2x_emac_get_pfc_stat(struct link_params *params,
410 u32 pfc_frames_sent[2],
411 u32 pfc_frames_received[2])
412{
413 /* Read pfc statistic */
414 struct bnx2x *bp = params->bp;
415 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
416 u32 val_xon = 0;
417 u32 val_xoff = 0;
418
419 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
420
421 /* PFC received frames */
422 val_xoff = REG_RD(bp, emac_base +
423 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
424 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
425 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
426 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
427
428 pfc_frames_received[0] = val_xon + val_xoff;
429
430 /* PFC received sent */
431 val_xoff = REG_RD(bp, emac_base +
432 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
433 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
434 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
435 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
436
437 pfc_frames_sent[0] = val_xon + val_xoff;
438}
439
440void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
441 u32 pfc_frames_sent[2],
442 u32 pfc_frames_received[2])
443{
444 /* Read pfc statistic */
445 struct bnx2x *bp = params->bp;
446 u32 val = 0;
447 DP(NETIF_MSG_LINK, "pfc statistic\n");
448
449 if (!vars->link_up)
450 return;
451
452 val = REG_RD(bp, MISC_REG_RESET_REG_2);
453 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
454 == 0) {
455 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
456 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
457 pfc_frames_received);
458 } else {
459 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
460 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
461 pfc_frames_received);
462 }
463}
464/******************************************************************/
465/* MAC/PBF section */
466/******************************************************************/
ea4e040a 467static void bnx2x_emac_init(struct link_params *params,
cd88ccee 468 struct link_vars *vars)
ea4e040a
YR		 469{
470 /* reset and unreset the emac core */
471 struct bnx2x *bp = params->bp;
472 u8 port = params->port;
473 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
474 u32 val;
475 u16 timeout;
476
477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
cd88ccee 478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 479 udelay(5);
480 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 481 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 482
483 /* init emac - use read-modify-write */
484 /* self clear reset */
485 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 486 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 487
488 timeout = 200;
3196a88a 489 do {
ea4e040a
YR		 490 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
491 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
492 if (!timeout) {
493 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
494 return;
495 }
496 timeout--;
3196a88a 497 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 498
499 /* Set mac address */
500 val = ((params->mac_addr[0] << 8) |
501 params->mac_addr[1]);
3196a88a 502 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 503
504 val = ((params->mac_addr[2] << 24) |
505 (params->mac_addr[3] << 16) |
506 (params->mac_addr[4] << 8) |
507 params->mac_addr[5]);
3196a88a 508 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 509}
510
511static u8 bnx2x_emac_enable(struct link_params *params,
cd88ccee 512 struct link_vars *vars, u8 lb)
ea4e040a
YR		 513{
514 struct bnx2x *bp = params->bp;
515 u8 port = params->port;
516 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
517 u32 val;
518
519 DP(NETIF_MSG_LINK, "enabling EMAC\n");
520
521 /* enable emac and not bmac */
522 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
523
ea4e040a
YR		 524 /* ASIC */
525 if (vars->phy_flags & PHY_XGXS_FLAG) {
526 u32 ser_lane = ((params->lane_config &
cd88ccee
YR		 527 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
528 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
ea4e040a
YR		 529
530 DP(NETIF_MSG_LINK, "XGXS\n");
531 /* select the master lanes (out of 0-3) */
cd88ccee 532 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
ea4e040a 533 /* select XGXS */
cd88ccee 534 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
ea4e040a
YR		 535
536 } else { /* SerDes */
537 DP(NETIF_MSG_LINK, "SerDes\n");
538 /* select SerDes */
cd88ccee 539 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
ea4e040a
YR		 540 }
541
811a2f2d 542 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
cd88ccee 543 EMAC_RX_MODE_RESET);
811a2f2d 544 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
cd88ccee 545 EMAC_TX_MODE_RESET);
ea4e040a
YR		 546
547 if (CHIP_REV_IS_SLOW(bp)) {
548 /* config GMII mode */
549 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
cd88ccee 550 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
ea4e040a
YR		 551 } else { /* ASIC */
552 /* pause enable/disable */
553 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
554 EMAC_RX_MODE_FLOW_EN);
ea4e040a
YR		 555
556 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
bcab15c5
VZ		 557 (EMAC_TX_MODE_EXT_PAUSE_EN |
558 EMAC_TX_MODE_FLOW_EN));
559 if (!(params->feature_config_flags &
560 FEATURE_CONFIG_PFC_ENABLED)) {
561 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
562 bnx2x_bits_en(bp, emac_base +
563 EMAC_REG_EMAC_RX_MODE,
564 EMAC_RX_MODE_FLOW_EN);
565
566 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
567 bnx2x_bits_en(bp, emac_base +
568 EMAC_REG_EMAC_TX_MODE,
569 (EMAC_TX_MODE_EXT_PAUSE_EN |
570 EMAC_TX_MODE_FLOW_EN));
571 } else
572 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
573 EMAC_TX_MODE_FLOW_EN);
ea4e040a
YR		 574 }
575
576 /* KEEP_VLAN_TAG, promiscuous */
577 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
578 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
bcab15c5 579
2cf7acf9
YR		 580 /*
581 * Setting this bit causes MAC control frames (except for pause
582 * frames) to be passed on for processing. This setting has no
583 * affect on the operation of the pause frames. This bit effects
584 * all packets regardless of RX Parser packet sorting logic.
585 * Turn the PFC off to make sure we are in Xon state before
586 * enabling it.
587 */
bcab15c5
VZ		 588 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
589 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
590 DP(NETIF_MSG_LINK, "PFC is enabled\n");
591 /* Enable PFC again */
592 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
593 EMAC_REG_RX_PFC_MODE_RX_EN |
594 EMAC_REG_RX_PFC_MODE_TX_EN |
595 EMAC_REG_RX_PFC_MODE_PRIORITIES);
596
597 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
598 ((0x0101 <<
599 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
600 (0x00ff <<
601 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
602 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
603 }
3196a88a 604 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 605
606 /* Set Loopback */
607 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
608 if (lb)
609 val |= 0x810;
610 else
611 val &= ~0x810;
3196a88a 612 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 613
6c55c3cd
EG		 614 /* enable emac */
615 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
616
ea4e040a 617 /* enable emac for jumbo packets */
3196a88a 618 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 619 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
620 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
621
622 /* strip CRC */
623 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
624
625 /* disable the NIG in/out to the bmac */
626 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
627 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
628 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
629
630 /* enable the NIG in/out to the emac */
631 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
632 val = 0;
bcab15c5
VZ		 633 if ((params->feature_config_flags &
634 FEATURE_CONFIG_PFC_ENABLED) ||
635 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 636 val = 1;
637
638 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
639 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
640
02a23165 641 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 642
643 vars->mac_type = MAC_TYPE_EMAC;
644 return 0;
645}
646
bcab15c5
VZ		 647static void bnx2x_update_pfc_bmac1(struct link_params *params,
648 struct link_vars *vars)
649{
650 u32 wb_data[2];
651 struct bnx2x *bp = params->bp;
652 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
653 NIG_REG_INGRESS_BMAC0_MEM;
654
655 u32 val = 0x14;
656 if ((!(params->feature_config_flags &
657 FEATURE_CONFIG_PFC_ENABLED)) &&
658 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
659 /* Enable BigMAC to react on received Pause packets */
660 val |= (1<<5);
661 wb_data[0] = val;
662 wb_data[1] = 0;
663 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
664
665 /* tx control */
666 val = 0xc0;
667 if (!(params->feature_config_flags &
668 FEATURE_CONFIG_PFC_ENABLED) &&
669 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
670 val |= 0x800000;
671 wb_data[0] = val;
672 wb_data[1] = 0;
673 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
674}
675
676static void bnx2x_update_pfc_bmac2(struct link_params *params,
677 struct link_vars *vars,
678 u8 is_lb)
f2e0899f
DK		 679{
680 /*
681 * Set rx control: Strip CRC and enable BigMAC to relay
682 * control packets to the system as well
683 */
684 u32 wb_data[2];
685 struct bnx2x *bp = params->bp;
686 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
687 NIG_REG_INGRESS_BMAC0_MEM;
688 u32 val = 0x14;
ea4e040a 689
bcab15c5
VZ		 690 if ((!(params->feature_config_flags &
691 FEATURE_CONFIG_PFC_ENABLED)) &&
692 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
f2e0899f
DK		 693 /* Enable BigMAC to react on received Pause packets */
694 val |= (1<<5);
695 wb_data[0] = val;
696 wb_data[1] = 0;
cd88ccee 697 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
f2e0899f 698 udelay(30);
ea4e040a 699
f2e0899f
DK		 700 /* Tx control */
701 val = 0xc0;
bcab15c5
VZ		 702 if (!(params->feature_config_flags &
703 FEATURE_CONFIG_PFC_ENABLED) &&
704 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
f2e0899f
DK		 705 val |= 0x800000;
706 wb_data[0] = val;
707 wb_data[1] = 0;
bcab15c5
VZ		 708 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
709
710 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
711 DP(NETIF_MSG_LINK, "PFC is enabled\n");
712 /* Enable PFC RX & TX & STATS and set 8 COS */
713 wb_data[0] = 0x0;
714 wb_data[0] |= (1<<0); /* RX */
715 wb_data[0] |= (1<<1); /* TX */
716 wb_data[0] |= (1<<2); /* Force initial Xon */
717 wb_data[0] |= (1<<3); /* 8 cos */
718 wb_data[0] |= (1<<5); /* STATS */
719 wb_data[1] = 0;
720 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
721 wb_data, 2);
722 /* Clear the force Xon */
723 wb_data[0] &= ~(1<<2);
724 } else {
725 DP(NETIF_MSG_LINK, "PFC is disabled\n");
726 /* disable PFC RX & TX & STATS and set 8 COS */
727 wb_data[0] = 0x8;
728 wb_data[1] = 0;
729 }
730
731 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
f2e0899f 732
2cf7acf9
YR		 733 /*
734 * Set Time (based unit is 512 bit time) between automatic
735 * re-sending of PP packets amd enable automatic re-send of
736 * Per-Priroity Packet as long as pp_gen is asserted and
737 * pp_disable is low.
738 */
f2e0899f 739 val = 0x8000;
bcab15c5
VZ		 740 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
741 val |= (1<<16); /* enable automatic re-send */
742
f2e0899f
DK		 743 wb_data[0] = val;
744 wb_data[1] = 0;
745 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
cd88ccee 746 wb_data, 2);
f2e0899f
DK		 747
748 /* mac control */
749 val = 0x3; /* Enable RX and TX */
750 if (is_lb) {
751 val |= 0x4; /* Local loopback */
752 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
753 }
bcab15c5
VZ		 754 /* When PFC enabled, Pass pause frames towards the NIG. */
755 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
756 val |= ((1<<6)|(1<<5));
f2e0899f
DK		 757
758 wb_data[0] = val;
759 wb_data[1] = 0;
cd88ccee 760 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 761}
762
bcab15c5
VZ		 763static void bnx2x_update_pfc_brb(struct link_params *params,
764 struct link_vars *vars,
765 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
766{
767 struct bnx2x *bp = params->bp;
768 int set_pfc = params->feature_config_flags &
769 FEATURE_CONFIG_PFC_ENABLED;
770
771 /* default - pause configuration */
772 u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
773 u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
774 u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
775 u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
776
777 if (set_pfc && pfc_params)
778 /* First COS */
779 if (!pfc_params->cos0_pauseable) {
780 pause_xoff_th =
781 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
782 pause_xon_th =
783 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
784 full_xoff_th =
785 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
786 full_xon_th =
787 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
788 }
2cf7acf9
YR		 789 /*
790 * The number of free blocks below which the pause signal to class 0
791 * of MAC #n is asserted. n=0,1
792 */
bcab15c5 793 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
2cf7acf9
YR		 794 /*
795 * The number of free blocks above which the pause signal to class 0
796 * of MAC #n is de-asserted. n=0,1
797 */
bcab15c5 798 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
2cf7acf9
YR		 799 /*
800 * The number of free blocks below which the full signal to class 0
801 * of MAC #n is asserted. n=0,1
802 */
bcab15c5 803 REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
2cf7acf9
YR		 804 /*
805 * The number of free blocks above which the full signal to class 0
806 * of MAC #n is de-asserted. n=0,1
807 */
bcab15c5
VZ		 808 REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
809
810 if (set_pfc && pfc_params) {
811 /* Second COS */
812 if (pfc_params->cos1_pauseable) {
813 pause_xoff_th =
814 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
815 pause_xon_th =
816 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
817 full_xoff_th =
818 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
819 full_xon_th =
820 PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
821 } else {
822 pause_xoff_th =
823 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
824 pause_xon_th =
825 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
826 full_xoff_th =
827 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
828 full_xon_th =
829 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
830 }
2cf7acf9 831 /*
bcab15c5
VZ		 832 * The number of free blocks below which the pause signal to
833 * class 1 of MAC #n is asserted. n=0,1
2cf7acf9 834 */
bcab15c5 835 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
2cf7acf9 836 /*
bcab15c5
VZ		 837 * The number of free blocks above which the pause signal to
838 * class 1 of MAC #n is de-asserted. n=0,1
2cf7acf9 839 */
bcab15c5 840 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
2cf7acf9 841 /*
bcab15c5
VZ		 842 * The number of free blocks below which the full signal to
843 * class 1 of MAC #n is asserted. n=0,1
2cf7acf9 844 */
bcab15c5 845 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
2cf7acf9 846 /*
bcab15c5
VZ		 847 * The number of free blocks above which the full signal to
848 * class 1 of MAC #n is de-asserted. n=0,1
2cf7acf9 849 */
bcab15c5
VZ		 850 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
851 }
852}
853
854static void bnx2x_update_pfc_nig(struct link_params *params,
855 struct link_vars *vars,
856 struct bnx2x_nig_brb_pfc_port_params *nig_params)
857{
858 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
859 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
860 u32 pkt_priority_to_cos = 0;
861 u32 val;
862 struct bnx2x *bp = params->bp;
863 int port = params->port;
864 int set_pfc = params->feature_config_flags &
865 FEATURE_CONFIG_PFC_ENABLED;
866 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
867
2cf7acf9 868 /*
bcab15c5
VZ		 869 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
870 * MAC control frames (that are not pause packets)
871 * will be forwarded to the XCM.
872 */
873 xcm_mask = REG_RD(bp,
874 port ? NIG_REG_LLH1_XCM_MASK :
875 NIG_REG_LLH0_XCM_MASK);
2cf7acf9 876 /*
bcab15c5
VZ		 877 * nig params will override non PFC params, since it's possible to
878 * do transition from PFC to SAFC
879 */
880 if (set_pfc) {
881 pause_enable = 0;
882 llfc_out_en = 0;
883 llfc_enable = 0;
884 ppp_enable = 1;
885 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
886 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
887 xcm0_out_en = 0;
888 p0_hwpfc_enable = 1;
889 } else {
890 if (nig_params) {
891 llfc_out_en = nig_params->llfc_out_en;
892 llfc_enable = nig_params->llfc_enable;
893 pause_enable = nig_params->pause_enable;
894 } else /*defaul non PFC mode - PAUSE */
895 pause_enable = 1;
896
897 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
898 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
899 xcm0_out_en = 1;
900 }
901
902 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
903 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
904 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
905 NIG_REG_LLFC_ENABLE_0, llfc_enable);
906 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
907 NIG_REG_PAUSE_ENABLE_0, pause_enable);
908
909 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
910 NIG_REG_PPP_ENABLE_0, ppp_enable);
911
912 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
913 NIG_REG_LLH0_XCM_MASK, xcm_mask);
914
915 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
916
917 /* output enable for RX_XCM # IF */
918 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
919
920 /* HW PFC TX enable */
921 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
922
923 /* 0x2 = BMAC, 0x1= EMAC */
924 switch (vars->mac_type) {
925 case MAC_TYPE_EMAC:
926 val = 1;
927 break;
928 case MAC_TYPE_BMAC:
929 val = 0;
930 break;
931 default:
932 val = 0;
933 break;
934 }
935 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
936
937 if (nig_params) {
938 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
939
940 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
941 NIG_REG_P0_RX_COS0_PRIORITY_MASK,
942 nig_params->rx_cos0_priority_mask);
943
944 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
945 NIG_REG_P0_RX_COS1_PRIORITY_MASK,
946 nig_params->rx_cos1_priority_mask);
947
948 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
949 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
950 nig_params->llfc_high_priority_classes);
951
952 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
953 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
954 nig_params->llfc_low_priority_classes);
955 }
956 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
957 NIG_REG_P0_PKT_PRIORITY_TO_COS,
958 pkt_priority_to_cos);
959}
960
961
962void bnx2x_update_pfc(struct link_params *params,
963 struct link_vars *vars,
964 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
965{
2cf7acf9 966 /*
bcab15c5
VZ		 967 * The PFC and pause are orthogonal to one another, meaning when
968 * PFC is enabled, the pause are disabled, and when PFC is
969 * disabled, pause are set according to the pause result.
970 */
971 u32 val;
972 struct bnx2x *bp = params->bp;
973
974 /* update NIG params */
975 bnx2x_update_pfc_nig(params, vars, pfc_params);
976
977 /* update BRB params */
978 bnx2x_update_pfc_brb(params, vars, pfc_params);
979
980 if (!vars->link_up)
981 return;
982
983 val = REG_RD(bp, MISC_REG_RESET_REG_2);
984 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
985 == 0) {
986 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
987 bnx2x_emac_enable(params, vars, 0);
988 return;
989 }
990
991 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
992 if (CHIP_IS_E2(bp))
993 bnx2x_update_pfc_bmac2(params, vars, 0);
994 else
995 bnx2x_update_pfc_bmac1(params, vars);
996
997 val = 0;
998 if ((params->feature_config_flags &
999 FEATURE_CONFIG_PFC_ENABLED) ||
1000 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1001 val = 1;
1002 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1003}
f2e0899f
DK		 1004
1005static u8 bnx2x_bmac1_enable(struct link_params *params,
1006 struct link_vars *vars,
cd88ccee 1007 u8 is_lb)
ea4e040a
YR		 1008{
1009 struct bnx2x *bp = params->bp;
1010 u8 port = params->port;
1011 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1012 NIG_REG_INGRESS_BMAC0_MEM;
1013 u32 wb_data[2];
1014 u32 val;
1015
f2e0899f 1016 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
ea4e040a
YR		 1017
1018 /* XGXS control */
1019 wb_data[0] = 0x3c;
1020 wb_data[1] = 0;
cd88ccee
YR		 1021 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1022 wb_data, 2);
ea4e040a
YR		 1023
1024 /* tx MAC SA */
1025 wb_data[0] = ((params->mac_addr[2] << 24) |
1026 (params->mac_addr[3] << 16) |
1027 (params->mac_addr[4] << 8) |
1028 params->mac_addr[5]);
1029 wb_data[1] = ((params->mac_addr[0] << 8) |
1030 params->mac_addr[1]);
cd88ccee 1031 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
ea4e040a 1032
ea4e040a
YR		 1033 /* mac control */
1034 val = 0x3;
1035 if (is_lb) {
1036 val |= 0x4;
1037 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1038 }
1039 wb_data[0] = val;
1040 wb_data[1] = 0;
cd88ccee 1041 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
ea4e040a 1042
ea4e040a
YR		 1043 /* set rx mtu */
1044 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1045 wb_data[1] = 0;
cd88ccee 1046 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
ea4e040a 1047
bcab15c5 1048 bnx2x_update_pfc_bmac1(params, vars);
ea4e040a
YR		 1049
1050 /* set tx mtu */
1051 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1052 wb_data[1] = 0;
cd88ccee 1053 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
ea4e040a
YR		 1054
1055 /* set cnt max size */
1056 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1057 wb_data[1] = 0;
cd88ccee 1058 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
ea4e040a
YR		 1059
1060 /* configure safc */
1061 wb_data[0] = 0x1000200;
1062 wb_data[1] = 0;
1063 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1064 wb_data, 2);
f2e0899f
DK		 1065
1066 return 0;
1067}
1068
1069static u8 bnx2x_bmac2_enable(struct link_params *params,
1070 struct link_vars *vars,
1071 u8 is_lb)
1072{
1073 struct bnx2x *bp = params->bp;
1074 u8 port = params->port;
1075 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1076 NIG_REG_INGRESS_BMAC0_MEM;
1077 u32 wb_data[2];
1078
1079 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1080
1081 wb_data[0] = 0;
1082 wb_data[1] = 0;
cd88ccee 1083 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 1084 udelay(30);
1085
1086 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1087 wb_data[0] = 0x3c;
1088 wb_data[1] = 0;
cd88ccee
YR		 1089 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1090 wb_data, 2);
f2e0899f
DK		 1091
1092 udelay(30);
1093
1094 /* tx MAC SA */
1095 wb_data[0] = ((params->mac_addr[2] << 24) |
1096 (params->mac_addr[3] << 16) |
1097 (params->mac_addr[4] << 8) |
1098 params->mac_addr[5]);
1099 wb_data[1] = ((params->mac_addr[0] << 8) |
1100 params->mac_addr[1]);
1101 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
cd88ccee 1102 wb_data, 2);
f2e0899f
DK		 1103
1104 udelay(30);
1105
1106 /* Configure SAFC */
1107 wb_data[0] = 0x1000200;
1108 wb_data[1] = 0;
1109 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
cd88ccee 1110 wb_data, 2);
f2e0899f
DK		 1111 udelay(30);
1112
1113 /* set rx mtu */
1114 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1115 wb_data[1] = 0;
cd88ccee 1116 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
f2e0899f
DK		 1117 udelay(30);
1118
1119 /* set tx mtu */
1120 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1121 wb_data[1] = 0;
cd88ccee 1122 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
f2e0899f
DK		 1123 udelay(30);
1124 /* set cnt max size */
1125 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1126 wb_data[1] = 0;
cd88ccee 1127 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
f2e0899f 1128 udelay(30);
bcab15c5 1129 bnx2x_update_pfc_bmac2(params, vars, is_lb);
f2e0899f
DK		 1130
1131 return 0;
1132}
1133
8d96286a 1134static u8 bnx2x_bmac_enable(struct link_params *params,
f2e0899f
DK		 1135 struct link_vars *vars,
1136 u8 is_lb)
1137{
1138 u8 rc, port = params->port;
1139 struct bnx2x *bp = params->bp;
1140 u32 val;
1141 /* reset and unreset the BigMac */
1142 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
cd88ccee 1143 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1d9c05d4 1144 msleep(1);
f2e0899f
DK		 1145
1146 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 1147 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
f2e0899f
DK		 1148
1149 /* enable access for bmac registers */
1150 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1151
1152 /* Enable BMAC according to BMAC type*/
1153 if (CHIP_IS_E2(bp))
1154 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1155 else
1156 rc = bnx2x_bmac1_enable(params, vars, is_lb);
ea4e040a
YR		 1157 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1158 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1159 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1160 val = 0;
bcab15c5
VZ		 1161 if ((params->feature_config_flags &
1162 FEATURE_CONFIG_PFC_ENABLED) ||
1163 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 1164 val = 1;
1165 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1166 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1167 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1168 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1169 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1170 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1171
1172 vars->mac_type = MAC_TYPE_BMAC;
f2e0899f 1173 return rc;
ea4e040a
YR		 1174}
1175
ea4e040a
YR		 1176
1177static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1178{
1179 struct bnx2x *bp = params->bp;
ab6ad5a4 1180
ea4e040a 1181 REG_WR(bp, params->shmem_base +
cd88ccee
YR		 1182 offsetof(struct shmem_region,
1183 port_mb[params->port].link_status), link_status);
ea4e040a
YR		 1184}
1185
1186static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1187{
1188 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
cd88ccee 1189 NIG_REG_INGRESS_BMAC0_MEM;
ea4e040a 1190 u32 wb_data[2];
3196a88a 1191 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 1192
1193 /* Only if the bmac is out of reset */
1194 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1195 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1196 nig_bmac_enable) {
1197
f2e0899f
DK		 1198 if (CHIP_IS_E2(bp)) {
1199 /* Clear Rx Enable bit in BMAC_CONTROL register */
1200 REG_RD_DMAE(bp, bmac_addr +
cd88ccee
YR		 1201 BIGMAC2_REGISTER_BMAC_CONTROL,
1202 wb_data, 2);
f2e0899f
DK		 1203 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1204 REG_WR_DMAE(bp, bmac_addr +
cd88ccee
YR		 1205 BIGMAC2_REGISTER_BMAC_CONTROL,
1206 wb_data, 2);
f2e0899f
DK		 1207 } else {
1208 /* Clear Rx Enable bit in BMAC_CONTROL register */
1209 REG_RD_DMAE(bp, bmac_addr +
1210 BIGMAC_REGISTER_BMAC_CONTROL,
1211 wb_data, 2);
1212 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1213 REG_WR_DMAE(bp, bmac_addr +
1214 BIGMAC_REGISTER_BMAC_CONTROL,
1215 wb_data, 2);
1216 }
ea4e040a
YR		 1217 msleep(1);
1218 }
1219}
1220
1221static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
cd88ccee 1222 u32 line_speed)
ea4e040a
YR		 1223{
1224 struct bnx2x *bp = params->bp;
1225 u8 port = params->port;
1226 u32 init_crd, crd;
1227 u32 count = 1000;
ea4e040a
YR		 1228
1229 /* disable port */
1230 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1231
1232 /* wait for init credit */
1233 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1234 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1235 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
1236
1237 while ((init_crd != crd) && count) {
1238 msleep(5);
1239
1240 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1241 count--;
1242 }
1243 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1244 if (init_crd != crd) {
1245 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1246 init_crd, crd);
1247 return -EINVAL;
1248 }
1249
c0700f90 1250 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 1251 line_speed == SPEED_10 ||
1252 line_speed == SPEED_100 ||
1253 line_speed == SPEED_1000 ||
1254 line_speed == SPEED_2500) {
1255 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 1256 /* update threshold */
1257 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1258 /* update init credit */
cd88ccee 1259 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 1260
1261 } else {
1262 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1263 ETH_OVREHEAD)/16;
8c99e7b0 1264 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 1265 /* update threshold */
1266 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1267 /* update init credit */
1268 switch (line_speed) {
ea4e040a
YR		 1269 case SPEED_10000:
1270 init_crd = thresh + 553 - 22;
1271 break;
1272
1273 case SPEED_12000:
1274 init_crd = thresh + 664 - 22;
1275 break;
1276
1277 case SPEED_13000:
1278 init_crd = thresh + 742 - 22;
1279 break;
1280
1281 case SPEED_16000:
1282 init_crd = thresh + 778 - 22;
1283 break;
1284 default:
1285 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1286 line_speed);
1287 return -EINVAL;
ea4e040a
YR		 1288 }
1289 }
1290 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1291 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1292 line_speed, init_crd);
1293
1294 /* probe the credit changes */
1295 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1296 msleep(5);
1297 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1298
1299 /* enable port */
1300 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1301 return 0;
1302}
1303
2cf7acf9
YR		 1304/*
1305 * get_emac_base
1306 *
1307 * @param cb
1308 * @param mdc_mdio_access
1309 * @param port
1310 *
1311 * @return u32
1312 *
1313 * This function selects the MDC/MDIO access (through emac0 or
1314 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1315 * phy has a default access mode, which could also be overridden
1316 * by nvram configuration. This parameter, whether this is the
1317 * default phy configuration, or the nvram overrun
1318 * configuration, is passed here as mdc_mdio_access and selects
1319 * the emac_base for the CL45 read/writes operations
1320 */
c18aa15d
YR		 1321static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1322 u32 mdc_mdio_access, u8 port)
ea4e040a 1323{
c18aa15d
YR		 1324 u32 emac_base = 0;
1325 switch (mdc_mdio_access) {
1326 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1327 break;
1328 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1329 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1330 emac_base = GRCBASE_EMAC1;
1331 else
1332 emac_base = GRCBASE_EMAC0;
1333 break;
1334 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
589abe3a
EG		 1335 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1336 emac_base = GRCBASE_EMAC0;
1337 else
1338 emac_base = GRCBASE_EMAC1;
ea4e040a 1339 break;
c18aa15d
YR		 1340 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1341 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1342 break;
1343 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
6378c025 1344 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 1345 break;
1346 default:
ea4e040a
YR		 1347 break;
1348 }
1349 return emac_base;
1350
1351}
1352
2cf7acf9
YR		 1353/******************************************************************/
1354/* CL45 access functions */
1355/******************************************************************/
65a001ba
YR		 1356static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1357 u8 devad, u16 reg, u16 val)
ea4e040a
YR		 1358{
1359 u32 tmp, saved_mode;
1360 u8 i, rc = 0;
2cf7acf9
YR		 1361 /*
1362 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
ea4e040a
YR		 1363 * (a value of 49==0x31) and make sure that the AUTO poll is off
1364 */
589abe3a 1365
e10bc84d 1366 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1367 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1368 EMAC_MDIO_MODE_CLOCK_CNT);
1369 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1370 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 1371 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1372 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1373 udelay(40);
1374
1375 /* address */
1376
e10bc84d 1377 tmp = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 1378 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1379 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1380 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 1381
1382 for (i = 0; i < 50; i++) {
1383 udelay(10);
1384
cd88ccee 1385 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1386 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1387 udelay(5);
1388 break;
1389 }
1390 }
1391 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 1393 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1394 rc = -EFAULT;
1395 } else {
1396 /* data */
e10bc84d 1397 tmp = ((phy->addr << 21) | (devad << 16) | val |
ea4e040a
YR		 1398 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1399 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1400 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 1401
1402 for (i = 0; i < 50; i++) {
1403 udelay(10);
1404
e10bc84d 1405 tmp = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 1406 EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1407 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1408 udelay(5);
1409 break;
1410 }
1411 }
1412 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1413 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 1414 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1415 rc = -EFAULT;
1416 }
1417 }
1418
1419 /* Restore the saved mode */
e10bc84d 1420 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 1421
1422 return rc;
1423}
1424
65a001ba
YR		 1425static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1426 u8 devad, u16 reg, u16 *ret_val)
ea4e040a
YR		 1427{
1428 u32 val, saved_mode;
1429 u16 i;
1430 u8 rc = 0;
2cf7acf9
YR		 1431 /*
1432 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
ea4e040a
YR		 1433 * (a value of 49==0x31) and make sure that the AUTO poll is off
1434 */
589abe3a 1435
e10bc84d
YR		 1436 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1437 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
cd88ccee 1438 EMAC_MDIO_MODE_CLOCK_CNT));
ea4e040a 1439 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
ab6ad5a4 1440 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 1441 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1442 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1443 udelay(40);
1444
1445 /* address */
e10bc84d 1446 val = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 1447 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1448 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1449 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 1450
1451 for (i = 0; i < 50; i++) {
1452 udelay(10);
1453
e10bc84d 1454 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1455 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1456 udelay(5);
1457 break;
1458 }
1459 }
1460 if (val & EMAC_MDIO_COMM_START_BUSY) {
1461 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 1462 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1463 *ret_val = 0;
1464 rc = -EFAULT;
1465
1466 } else {
1467 /* data */
e10bc84d 1468 val = ((phy->addr << 21) | (devad << 16) |
ea4e040a
YR		 1469 EMAC_MDIO_COMM_COMMAND_READ_45 |
1470 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1471 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 1472
1473 for (i = 0; i < 50; i++) {
1474 udelay(10);
1475
e10bc84d 1476 val = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 1477 EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1478 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1479 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1480 break;
1481 }
1482 }
1483 if (val & EMAC_MDIO_COMM_START_BUSY) {
1484 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 1485 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1486 *ret_val = 0;
1487 rc = -EFAULT;
1488 }
1489 }
1490
1491 /* Restore the saved mode */
e10bc84d 1492 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 1493
1494 return rc;
1495}
1496
e10bc84d
YR		 1497u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1498 u8 devad, u16 reg, u16 *ret_val)
1499{
1500 u8 phy_index;
2cf7acf9 1501 /*
e10bc84d
YR		 1502 * Probe for the phy according to the given phy_addr, and execute
1503 * the read request on it
1504 */
1505 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1506 if (params->phy[phy_index].addr == phy_addr) {
1507 return bnx2x_cl45_read(params->bp,
1508 &params->phy[phy_index], devad,
1509 reg, ret_val);
1510 }
1511 }
1512 return -EINVAL;
1513}
1514
1515u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1516 u8 devad, u16 reg, u16 val)
1517{
1518 u8 phy_index;
2cf7acf9 1519 /*
e10bc84d
YR		 1520 * Probe for the phy according to the given phy_addr, and execute
1521 * the write request on it
1522 */
1523 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1524 if (params->phy[phy_index].addr == phy_addr) {
1525 return bnx2x_cl45_write(params->bp,
1526 &params->phy[phy_index], devad,
1527 reg, val);
1528 }
1529 }
1530 return -EINVAL;
1531}
1532
f2e0899f
DK		 1533static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1534 struct bnx2x_phy *phy)
ea4e040a 1535{
ea4e040a 1536 u32 ser_lane;
f2e0899f
DK		 1537 u16 offset, aer_val;
1538 struct bnx2x *bp = params->bp;
ea4e040a
YR		 1539 ser_lane = ((params->lane_config &
1540 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1541 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1542
f2e0899f
DK		 1543 offset = phy->addr + ser_lane;
1544 if (CHIP_IS_E2(bp))
82a0d475 1545 aer_val = 0x3800 + offset - 1;
f2e0899f
DK		 1546 else
1547 aer_val = 0x3800 + offset;
cd2be89b 1548 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
cd88ccee 1549 MDIO_AER_BLOCK_AER_REG, aer_val);
f2e0899f
DK		 1550}
1551static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1552 struct bnx2x_phy *phy)
1553{
cd2be89b 1554 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1555 MDIO_REG_BANK_AER_BLOCK,
1556 MDIO_AER_BLOCK_AER_REG, 0x3800);
ea4e040a
YR		 1557}
1558
de6eae1f
YR		 1559/******************************************************************/
1560/* Internal phy section */
1561/******************************************************************/
ea4e040a 1562
de6eae1f
YR		 1563static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1564{
1565 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a 1566
de6eae1f
YR		 1567 /* Set Clause 22 */
1568 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1569 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1570 udelay(500);
1571 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1572 udelay(500);
1573 /* Set Clause 45 */
1574 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
ea4e040a
YR		 1575}
1576
de6eae1f 1577static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
ea4e040a 1578{
de6eae1f 1579 u32 val;
ea4e040a 1580
de6eae1f 1581 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
ea4e040a 1582
de6eae1f 1583 val = SERDES_RESET_BITS << (port*16);
c1b73990 1584
de6eae1f
YR		 1585 /* reset and unreset the SerDes/XGXS */
1586 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1587 udelay(500);
1588 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
ea4e040a 1589
de6eae1f 1590 bnx2x_set_serdes_access(bp, port);
ea4e040a 1591
cd88ccee
YR		 1592 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1593 DEFAULT_PHY_DEV_ADDR);
de6eae1f
YR		 1594}
1595
1596static void bnx2x_xgxs_deassert(struct link_params *params)
1597{
1598 struct bnx2x *bp = params->bp;
1599 u8 port;
1600 u32 val;
1601 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1602 port = params->port;
1603
1604 val = XGXS_RESET_BITS << (port*16);
1605
1606 /* reset and unreset the SerDes/XGXS */
1607 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1608 udelay(500);
1609 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1610
cd88ccee 1611 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
de6eae1f 1612 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
cd88ccee 1613 params->phy[INT_PHY].def_md_devad);
de6eae1f
YR		 1614}
1615
a22f0788 1616
de6eae1f 1617void bnx2x_link_status_update(struct link_params *params,
cd88ccee 1618 struct link_vars *vars)
de6eae1f
YR		 1619{
1620 struct bnx2x *bp = params->bp;
1621 u8 link_10g;
1622 u8 port = params->port;
1623
de6eae1f 1624 vars->link_status = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 1625 offsetof(struct shmem_region,
1626 port_mb[port].link_status));
de6eae1f
YR		 1627
1628 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1629
1630 if (vars->link_up) {
1631 DP(NETIF_MSG_LINK, "phy link up\n");
1632
1633 vars->phy_link_up = 1;
1634 vars->duplex = DUPLEX_FULL;
1635 switch (vars->link_status &
cd88ccee 1636 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
de6eae1f
YR		 1637 case LINK_10THD:
1638 vars->duplex = DUPLEX_HALF;
1639 /* fall thru */
1640 case LINK_10TFD:
1641 vars->line_speed = SPEED_10;
1642 break;
1643
1644 case LINK_100TXHD:
1645 vars->duplex = DUPLEX_HALF;
1646 /* fall thru */
1647 case LINK_100T4:
1648 case LINK_100TXFD:
1649 vars->line_speed = SPEED_100;
1650 break;
1651
1652 case LINK_1000THD:
1653 vars->duplex = DUPLEX_HALF;
1654 /* fall thru */
1655 case LINK_1000TFD:
1656 vars->line_speed = SPEED_1000;
1657 break;
1658
1659 case LINK_2500THD:
1660 vars->duplex = DUPLEX_HALF;
1661 /* fall thru */
1662 case LINK_2500TFD:
1663 vars->line_speed = SPEED_2500;
1664 break;
1665
1666 case LINK_10GTFD:
1667 vars->line_speed = SPEED_10000;
1668 break;
1669
1670 case LINK_12GTFD:
1671 vars->line_speed = SPEED_12000;
1672 break;
1673
1674 case LINK_12_5GTFD:
1675 vars->line_speed = SPEED_12500;
1676 break;
1677
1678 case LINK_13GTFD:
1679 vars->line_speed = SPEED_13000;
1680 break;
1681
1682 case LINK_15GTFD:
1683 vars->line_speed = SPEED_15000;
1684 break;
1685
1686 case LINK_16GTFD:
1687 vars->line_speed = SPEED_16000;
1688 break;
1689
1690 default:
1691 break;
1692 }
de6eae1f
YR		 1693 vars->flow_ctrl = 0;
1694 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1695 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1696
1697 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1698 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1699
1700 if (!vars->flow_ctrl)
1701 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1702
1703 if (vars->line_speed &&
1704 ((vars->line_speed == SPEED_10) ||
1705 (vars->line_speed == SPEED_100))) {
1706 vars->phy_flags |= PHY_SGMII_FLAG;
1707 } else {
1708 vars->phy_flags &= ~PHY_SGMII_FLAG;
1709 }
1710
1711 /* anything 10 and over uses the bmac */
1712 link_10g = ((vars->line_speed == SPEED_10000) ||
1713 (vars->line_speed == SPEED_12000) ||
1714 (vars->line_speed == SPEED_12500) ||
1715 (vars->line_speed == SPEED_13000) ||
1716 (vars->line_speed == SPEED_15000) ||
1717 (vars->line_speed == SPEED_16000));
1718 if (link_10g)
1719 vars->mac_type = MAC_TYPE_BMAC;
1720 else
1721 vars->mac_type = MAC_TYPE_EMAC;
1722
1723 } else { /* link down */
1724 DP(NETIF_MSG_LINK, "phy link down\n");
1725
1726 vars->phy_link_up = 0;
1727
1728 vars->line_speed = 0;
1729 vars->duplex = DUPLEX_FULL;
1730 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1731
1732 /* indicate no mac active */
1733 vars->mac_type = MAC_TYPE_NONE;
1734 }
1735
1736 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
1737 vars->link_status, vars->phy_link_up);
1738 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
1739 vars->line_speed, vars->duplex, vars->flow_ctrl);
1740}
1741
1742
1743static void bnx2x_set_master_ln(struct link_params *params,
1744 struct bnx2x_phy *phy)
1745{
1746 struct bnx2x *bp = params->bp;
1747 u16 new_master_ln, ser_lane;
cd88ccee 1748 ser_lane = ((params->lane_config &
de6eae1f 1749 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
cd88ccee 1750 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
de6eae1f
YR		 1751
1752 /* set the master_ln for AN */
cd2be89b 1753 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1754 MDIO_REG_BANK_XGXS_BLOCK2,
1755 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1756 &new_master_ln);
de6eae1f 1757
cd2be89b 1758 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1759 MDIO_REG_BANK_XGXS_BLOCK2 ,
1760 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1761 (new_master_ln | ser_lane));
de6eae1f
YR		 1762}
1763
1764static u8 bnx2x_reset_unicore(struct link_params *params,
1765 struct bnx2x_phy *phy,
1766 u8 set_serdes)
1767{
1768 struct bnx2x *bp = params->bp;
1769 u16 mii_control;
1770 u16 i;
cd2be89b 1771 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1772 MDIO_REG_BANK_COMBO_IEEE0,
1773 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
de6eae1f
YR		 1774
1775 /* reset the unicore */
cd2be89b 1776 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1777 MDIO_REG_BANK_COMBO_IEEE0,
1778 MDIO_COMBO_IEEE0_MII_CONTROL,
1779 (mii_control |
1780 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
de6eae1f
YR		 1781 if (set_serdes)
1782 bnx2x_set_serdes_access(bp, params->port);
1783
1784 /* wait for the reset to self clear */
1785 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1786 udelay(5);
1787
1788 /* the reset erased the previous bank value */
cd2be89b 1789 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1790 MDIO_REG_BANK_COMBO_IEEE0,
1791 MDIO_COMBO_IEEE0_MII_CONTROL,
1792 &mii_control);
de6eae1f
YR		 1793
1794 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1795 udelay(5);
1796 return 0;
1797 }
1798 }
ea4e040a 1799
6d870c39
YR		 1800 netdev_err(bp->dev, "Warning: PHY was not initialized,"
1801 " Port %d\n",
1802 params->port);
ea4e040a
YR		 1803 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1804 return -EINVAL;
1805
1806}
1807
e10bc84d
YR		 1808static void bnx2x_set_swap_lanes(struct link_params *params,
1809 struct bnx2x_phy *phy)
ea4e040a
YR		 1810{
1811 struct bnx2x *bp = params->bp;
2cf7acf9
YR		 1812 /*
1813 * Each two bits represents a lane number:
1814 * No swap is 0123 => 0x1b no need to enable the swap
1815 */
ea4e040a
YR		 1816 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1817
1818 ser_lane = ((params->lane_config &
cd88ccee
YR		 1819 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1820 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
ea4e040a 1821 rx_lane_swap = ((params->lane_config &
cd88ccee
YR		 1822 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1823 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
ea4e040a 1824 tx_lane_swap = ((params->lane_config &
cd88ccee
YR		 1825 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1826 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
ea4e040a
YR		 1827
1828 if (rx_lane_swap != 0x1b) {
cd2be89b 1829 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1830 MDIO_REG_BANK_XGXS_BLOCK2,
1831 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1832 (rx_lane_swap |
1833 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1834 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
ea4e040a 1835 } else {
cd2be89b 1836 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1837 MDIO_REG_BANK_XGXS_BLOCK2,
1838 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
ea4e040a
YR		 1839 }
1840
1841 if (tx_lane_swap != 0x1b) {
cd2be89b 1842 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1843 MDIO_REG_BANK_XGXS_BLOCK2,
1844 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1845 (tx_lane_swap |
1846 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
ea4e040a 1847 } else {
cd2be89b 1848 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1849 MDIO_REG_BANK_XGXS_BLOCK2,
1850 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
ea4e040a
YR		 1851 }
1852}
1853
e10bc84d
YR		 1854static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1855 struct link_params *params)
ea4e040a
YR		 1856{
1857 struct bnx2x *bp = params->bp;
1858 u16 control2;
cd2be89b 1859 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1860 MDIO_REG_BANK_SERDES_DIGITAL,
1861 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1862 &control2);
7aa0711f 1863 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
18afb0a6
YR		 1864 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1865 else
1866 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
7aa0711f
YR		 1867 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1868 phy->speed_cap_mask, control2);
cd2be89b 1869 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1870 MDIO_REG_BANK_SERDES_DIGITAL,
1871 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1872 control2);
ea4e040a 1873
e10bc84d 1874 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
c18aa15d 1875 (phy->speed_cap_mask &
18afb0a6 1876 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 1877 DP(NETIF_MSG_LINK, "XGXS\n");
1878
cd2be89b 1879 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1880 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1881 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1882 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
ea4e040a 1883
cd2be89b 1884 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1885 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1886 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1887 &control2);
ea4e040a
YR		 1888
1889
1890 control2 |=
1891 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1892
cd2be89b 1893 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1894 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1895 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1896 control2);
ea4e040a
YR		 1897
1898 /* Disable parallel detection of HiG */
cd2be89b 1899 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1900 MDIO_REG_BANK_XGXS_BLOCK2,
1901 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1902 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1903 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
ea4e040a
YR		 1904 }
1905}
1906
e10bc84d
YR		 1907static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1908 struct link_params *params,
cd88ccee
YR		 1909 struct link_vars *vars,
1910 u8 enable_cl73)
ea4e040a
YR		 1911{
1912 struct bnx2x *bp = params->bp;
1913 u16 reg_val;
1914
1915 /* CL37 Autoneg */
cd2be89b 1916 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1917 MDIO_REG_BANK_COMBO_IEEE0,
1918 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a
YR		 1919
1920 /* CL37 Autoneg Enabled */
8c99e7b0 1921 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1922 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1923 else /* CL37 Autoneg Disabled */
1924 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1925 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1926
cd2be89b 1927 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1928 MDIO_REG_BANK_COMBO_IEEE0,
1929 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a
YR		 1930
1931 /* Enable/Disable Autodetection */
1932
cd2be89b 1933 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1934 MDIO_REG_BANK_SERDES_DIGITAL,
1935 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 1936 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1937 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1938 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 1939 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1940 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1941 else
1942 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1943
cd2be89b 1944 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1945 MDIO_REG_BANK_SERDES_DIGITAL,
1946 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
ea4e040a
YR		 1947
1948 /* Enable TetonII and BAM autoneg */
cd2be89b 1949 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1950 MDIO_REG_BANK_BAM_NEXT_PAGE,
1951 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
ea4e040a 1952 &reg_val);
8c99e7b0 1953 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1954 /* Enable BAM aneg Mode and TetonII aneg Mode */
1955 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1956 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1957 } else {
1958 /* TetonII and BAM Autoneg Disabled */
1959 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1960 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1961 }
cd2be89b 1962 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1963 MDIO_REG_BANK_BAM_NEXT_PAGE,
1964 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1965 reg_val);
ea4e040a 1966
239d686d
EG		 1967 if (enable_cl73) {
1968 /* Enable Cl73 FSM status bits */
cd2be89b 1969 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1970 MDIO_REG_BANK_CL73_USERB0,
1971 MDIO_CL73_USERB0_CL73_UCTRL,
1972 0xe);
239d686d
EG		 1973
1974 /* Enable BAM Station Manager*/
cd2be89b 1975 CL22_WR_OVER_CL45(bp, phy,
239d686d
EG		 1976 MDIO_REG_BANK_CL73_USERB0,
1977 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1978 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1979 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1980 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1981
7846e471 1982 /* Advertise CL73 link speeds */
cd2be89b 1983 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1984 MDIO_REG_BANK_CL73_IEEEB1,
1985 MDIO_CL73_IEEEB1_AN_ADV2,
1986 &reg_val);
7aa0711f 1987 if (phy->speed_cap_mask &
7846e471
YR		 1988 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1989 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
7aa0711f 1990 if (phy->speed_cap_mask &
7846e471
YR		 1991 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1992 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d 1993
cd2be89b 1994 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1995 MDIO_REG_BANK_CL73_IEEEB1,
1996 MDIO_CL73_IEEEB1_AN_ADV2,
1997 reg_val);
239d686d 1998
239d686d
EG		 1999 /* CL73 Autoneg Enabled */
2000 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2001
2002 } else /* CL73 Autoneg Disabled */
2003 reg_val = 0;
ea4e040a 2004
cd2be89b 2005 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2006 MDIO_REG_BANK_CL73_IEEEB0,
2007 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
ea4e040a
YR		 2008}
2009
2010/* program SerDes, forced speed */
e10bc84d
YR		 2011static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2012 struct link_params *params,
cd88ccee 2013 struct link_vars *vars)
ea4e040a
YR		 2014{
2015 struct bnx2x *bp = params->bp;
2016 u16 reg_val;
2017
57937203 2018 /* program duplex, disable autoneg and sgmii*/
cd2be89b 2019 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2020 MDIO_REG_BANK_COMBO_IEEE0,
2021 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a 2022 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 2023 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2024 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
7aa0711f 2025 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a 2026 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 2027 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2028 MDIO_REG_BANK_COMBO_IEEE0,
2029 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a 2030
2cf7acf9
YR		 2031 /*
2032 * program speed
2033 * - needed only if the speed is greater than 1G (2.5G or 10G)
2034 */
cd2be89b 2035 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2036 MDIO_REG_BANK_SERDES_DIGITAL,
2037 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 2038 /* clearing the speed value before setting the right speed */
2039 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2040
2041 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2042 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2043
2044 if (!((vars->line_speed == SPEED_1000) ||
2045 (vars->line_speed == SPEED_100) ||
2046 (vars->line_speed == SPEED_10))) {
2047
ea4e040a
YR		 2048 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2049 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 2050 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 2051 reg_val |=
2052 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 2053 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 2054 reg_val |=
2055 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 2056 }
2057
cd2be89b 2058 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2059 MDIO_REG_BANK_SERDES_DIGITAL,
2060 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 2061
ea4e040a
YR		 2062}
2063
e10bc84d
YR		 2064static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2065 struct link_params *params)
ea4e040a
YR		 2066{
2067 struct bnx2x *bp = params->bp;
2068 u16 val = 0;
2069
2070 /* configure the 48 bits for BAM AN */
2071
2072 /* set extended capabilities */
7aa0711f 2073 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
ea4e040a 2074 val |= MDIO_OVER_1G_UP1_2_5G;
7aa0711f 2075 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
ea4e040a 2076 val |= MDIO_OVER_1G_UP1_10G;
cd2be89b 2077 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2078 MDIO_REG_BANK_OVER_1G,
2079 MDIO_OVER_1G_UP1, val);
ea4e040a 2080
cd2be89b 2081 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2082 MDIO_REG_BANK_OVER_1G,
2083 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 2084}
2085
e10bc84d
YR		 2086static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2087 struct link_params *params, u16 *ieee_fc)
ea4e040a 2088{
d5cb9e99 2089 struct bnx2x *bp = params->bp;
8c99e7b0 2090 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2cf7acf9
YR		 2091 /*
2092 * Resolve pause mode and advertisement.
2093 * Please refer to Table 28B-3 of the 802.3ab-1999 spec
2094 */
ea4e040a 2095
7aa0711f 2096 switch (phy->req_flow_ctrl) {
c0700f90 2097 case BNX2X_FLOW_CTRL_AUTO:
cd88ccee
YR		 2098 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
2099 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2100 else
8c99e7b0 2101 *ieee_fc |=
cd88ccee 2102 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
ea4e040a 2103 break;
c0700f90 2104 case BNX2X_FLOW_CTRL_TX:
cd88ccee 2105 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
ea4e040a
YR		 2106 break;
2107
c0700f90
DM		 2108 case BNX2X_FLOW_CTRL_RX:
2109 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 2110 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 2111 break;
2112
c0700f90 2113 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 2114 default:
8c99e7b0 2115 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 2116 break;
2117 }
d5cb9e99 2118 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
8c99e7b0 2119}
ea4e040a 2120
e10bc84d
YR		 2121static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2122 struct link_params *params,
cd88ccee 2123 u16 ieee_fc)
8c99e7b0
YR		 2124{
2125 struct bnx2x *bp = params->bp;
7846e471 2126 u16 val;
8c99e7b0 2127 /* for AN, we are always publishing full duplex */
ea4e040a 2128
cd2be89b 2129 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2130 MDIO_REG_BANK_COMBO_IEEE0,
2131 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
cd2be89b 2132 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2133 MDIO_REG_BANK_CL73_IEEEB1,
2134 MDIO_CL73_IEEEB1_AN_ADV1, &val);
7846e471
YR		 2135 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2136 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
cd2be89b 2137 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2138 MDIO_REG_BANK_CL73_IEEEB1,
2139 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 2140}
2141
e10bc84d
YR		 2142static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2143 struct link_params *params,
2144 u8 enable_cl73)
ea4e040a
YR		 2145{
2146 struct bnx2x *bp = params->bp;
3a36f2ef 2147 u16 mii_control;
239d686d 2148
ea4e040a 2149 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 2150 /* Enable and restart BAM/CL37 aneg */
ea4e040a 2151
239d686d 2152 if (enable_cl73) {
cd2be89b 2153 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2154 MDIO_REG_BANK_CL73_IEEEB0,
2155 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2156 &mii_control);
239d686d 2157
cd2be89b 2158 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2159 MDIO_REG_BANK_CL73_IEEEB0,
2160 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2161 (mii_control |
2162 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2163 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
239d686d
EG		 2164 } else {
2165
cd2be89b 2166 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2167 MDIO_REG_BANK_COMBO_IEEE0,
2168 MDIO_COMBO_IEEE0_MII_CONTROL,
2169 &mii_control);
239d686d
EG		 2170 DP(NETIF_MSG_LINK,
2171 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2172 mii_control);
cd2be89b 2173 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2174 MDIO_REG_BANK_COMBO_IEEE0,
2175 MDIO_COMBO_IEEE0_MII_CONTROL,
2176 (mii_control |
2177 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2178 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
239d686d 2179 }
ea4e040a
YR		 2180}
2181
e10bc84d
YR		 2182static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2183 struct link_params *params,
cd88ccee 2184 struct link_vars *vars)
ea4e040a
YR		 2185{
2186 struct bnx2x *bp = params->bp;
2187 u16 control1;
2188
2189 /* in SGMII mode, the unicore is always slave */
2190
cd2be89b 2191 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2192 MDIO_REG_BANK_SERDES_DIGITAL,
2193 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2194 &control1);
ea4e040a
YR		 2195 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2196 /* set sgmii mode (and not fiber) */
2197 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2198 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2199 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
cd2be89b 2200 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2201 MDIO_REG_BANK_SERDES_DIGITAL,
2202 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2203 control1);
ea4e040a
YR		 2204
2205 /* if forced speed */
8c99e7b0 2206 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 2207 /* set speed, disable autoneg */
2208 u16 mii_control;
2209
cd2be89b 2210 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2211 MDIO_REG_BANK_COMBO_IEEE0,
2212 MDIO_COMBO_IEEE0_MII_CONTROL,
2213 &mii_control);
ea4e040a
YR		 2214 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2215 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2216 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2217
8c99e7b0 2218 switch (vars->line_speed) {
ea4e040a
YR		 2219 case SPEED_100:
2220 mii_control |=
2221 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2222 break;
2223 case SPEED_1000:
2224 mii_control |=
2225 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2226 break;
2227 case SPEED_10:
2228 /* there is nothing to set for 10M */
2229 break;
2230 default:
2231 /* invalid speed for SGMII */
8c99e7b0
YR		 2232 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2233 vars->line_speed);
ea4e040a
YR		 2234 break;
2235 }
2236
2237 /* setting the full duplex */
7aa0711f 2238 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a
YR		 2239 mii_control |=
2240 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 2241 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2242 MDIO_REG_BANK_COMBO_IEEE0,
2243 MDIO_COMBO_IEEE0_MII_CONTROL,
2244 mii_control);
ea4e040a
YR		 2245
2246 } else { /* AN mode */
2247 /* enable and restart AN */
e10bc84d 2248 bnx2x_restart_autoneg(phy, params, 0);
ea4e040a
YR		 2249 }
2250}
2251
2252
2253/*
2254 * link management
2255 */
2256
2257static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0 2258{ /* LD LP */
cd88ccee
YR		 2259 switch (pause_result) { /* ASYM P ASYM P */
2260 case 0xb: /* 1 0 1 1 */
c0700f90 2261 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 2262 break;
2263
cd88ccee 2264 case 0xe: /* 1 1 1 0 */
c0700f90 2265 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 2266 break;
2267
cd88ccee
YR		 2268 case 0x5: /* 0 1 0 1 */
2269 case 0x7: /* 0 1 1 1 */
2270 case 0xd: /* 1 1 0 1 */
2271 case 0xf: /* 1 1 1 1 */
c0700f90 2272 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 2273 break;
2274
2275 default:
2276 break;
2277 }
7aa0711f
YR		 2278 if (pause_result & (1<<0))
2279 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2280 if (pause_result & (1<<1))
2281 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
ea4e040a
YR		 2282}
2283
e10bc84d
YR		 2284static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2285 struct link_params *params)
15ddd2d0
YR		 2286{
2287 struct bnx2x *bp = params->bp;
2288 u16 pd_10g, status2_1000x;
7aa0711f
YR		 2289 if (phy->req_line_speed != SPEED_AUTO_NEG)
2290 return 0;
cd2be89b 2291 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2292 MDIO_REG_BANK_SERDES_DIGITAL,
2293 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2294 &status2_1000x);
cd2be89b 2295 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2296 MDIO_REG_BANK_SERDES_DIGITAL,
2297 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2298 &status2_1000x);
15ddd2d0
YR		 2299 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2300 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2301 params->port);
2302 return 1;
2303 }
2304
cd2be89b 2305 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2306 MDIO_REG_BANK_10G_PARALLEL_DETECT,
2307 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2308 &pd_10g);
15ddd2d0
YR		 2309
2310 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2311 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2312 params->port);
2313 return 1;
2314 }
2315 return 0;
2316}
ea4e040a 2317
e10bc84d
YR		 2318static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2319 struct link_params *params,
2320 struct link_vars *vars,
2321 u32 gp_status)
ea4e040a
YR		 2322{
2323 struct bnx2x *bp = params->bp;
3196a88a
EG		 2324 u16 ld_pause; /* local driver */
2325 u16 lp_pause; /* link partner */
ea4e040a
YR		 2326 u16 pause_result;
2327
c0700f90 2328 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 2329
2330 /* resolve from gp_status in case of AN complete and not sgmii */
7aa0711f
YR		 2331 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2332 vars->flow_ctrl = phy->req_flow_ctrl;
2333 else if (phy->req_line_speed != SPEED_AUTO_NEG)
2334 vars->flow_ctrl = params->req_fc_auto_adv;
2335 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2336 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
e10bc84d 2337 if (bnx2x_direct_parallel_detect_used(phy, params)) {
15ddd2d0
YR		 2338 vars->flow_ctrl = params->req_fc_auto_adv;
2339 return;
2340 }
7846e471
YR		 2341 if ((gp_status &
2342 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2343 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2344 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2345 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2346
cd2be89b 2347 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2348 MDIO_REG_BANK_CL73_IEEEB1,
2349 MDIO_CL73_IEEEB1_AN_ADV1,
2350 &ld_pause);
cd2be89b 2351 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2352 MDIO_REG_BANK_CL73_IEEEB1,
2353 MDIO_CL73_IEEEB1_AN_LP_ADV1,
2354 &lp_pause);
7846e471
YR		 2355 pause_result = (ld_pause &
2356 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2357 >> 8;
2358 pause_result |= (lp_pause &
2359 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2360 >> 10;
2361 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2362 pause_result);
2363 } else {
cd2be89b 2364 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2365 MDIO_REG_BANK_COMBO_IEEE0,
2366 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2367 &ld_pause);
cd2be89b 2368 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2369 MDIO_REG_BANK_COMBO_IEEE0,
2370 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2371 &lp_pause);
7846e471 2372 pause_result = (ld_pause &
ea4e040a 2373 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
7846e471 2374 pause_result |= (lp_pause &
cd88ccee 2375 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
7846e471
YR		 2376 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2377 pause_result);
2378 }
ea4e040a 2379 bnx2x_pause_resolve(vars, pause_result);
ea4e040a
YR		 2380 }
2381 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2382}
2383
e10bc84d
YR		 2384static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2385 struct link_params *params)
239d686d
EG		 2386{
2387 struct bnx2x *bp = params->bp;
2388 u16 rx_status, ustat_val, cl37_fsm_recieved;
2389 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2390 /* Step 1: Make sure signal is detected */
cd2be89b 2391 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2392 MDIO_REG_BANK_RX0,
2393 MDIO_RX0_RX_STATUS,
2394 &rx_status);
239d686d
EG		 2395 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2396 (MDIO_RX0_RX_STATUS_SIGDET)) {
2397 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2398 "rx_status(0x80b0) = 0x%x\n", rx_status);
cd2be89b 2399 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2400 MDIO_REG_BANK_CL73_IEEEB0,
2401 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2402 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
239d686d
EG		 2403 return;
2404 }
2405 /* Step 2: Check CL73 state machine */
cd2be89b 2406 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2407 MDIO_REG_BANK_CL73_USERB0,
2408 MDIO_CL73_USERB0_CL73_USTAT1,
2409 &ustat_val);
239d686d
EG		 2410 if ((ustat_val &
2411 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2412 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2413 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2414 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2415 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2416 "ustat_val(0x8371) = 0x%x\n", ustat_val);
2417 return;
2418 }
2cf7acf9
YR		 2419 /*
2420 * Step 3: Check CL37 Message Pages received to indicate LP
2421 * supports only CL37
2422 */
cd2be89b 2423 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2424 MDIO_REG_BANK_REMOTE_PHY,
2425 MDIO_REMOTE_PHY_MISC_RX_STATUS,
2426 &cl37_fsm_recieved);
239d686d
EG		 2427 if ((cl37_fsm_recieved &
2428 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2429 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2430 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2431 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2432 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2433 "misc_rx_status(0x8330) = 0x%x\n",
2434 cl37_fsm_recieved);
2435 return;
2436 }
2cf7acf9
YR		 2437 /*
2438 * The combined cl37/cl73 fsm state information indicating that
2439 * we are connected to a device which does not support cl73, but
2440 * does support cl37 BAM. In this case we disable cl73 and
2441 * restart cl37 auto-neg
2442 */
2443
239d686d 2444 /* Disable CL73 */
cd2be89b 2445 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2446 MDIO_REG_BANK_CL73_IEEEB0,
2447 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2448 0);
239d686d 2449 /* Restart CL37 autoneg */
e10bc84d 2450 bnx2x_restart_autoneg(phy, params, 0);
239d686d
EG		 2451 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2452}
7aa0711f
YR		 2453
2454static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2455 struct link_params *params,
2456 struct link_vars *vars,
2457 u32 gp_status)
2458{
2459 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2460 vars->link_status |=
2461 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2462
2463 if (bnx2x_direct_parallel_detect_used(phy, params))
2464 vars->link_status |=
2465 LINK_STATUS_PARALLEL_DETECTION_USED;
2466}
2467
b7737c9b
YR		 2468static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2469 struct link_params *params,
2470 struct link_vars *vars)
ea4e040a
YR		 2471{
2472 struct bnx2x *bp = params->bp;
cd88ccee 2473 u16 new_line_speed, gp_status;
ea4e040a 2474 u8 rc = 0;
c18aa15d 2475
b7737c9b 2476 /* Read gp_status */
cd2be89b 2477 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2478 MDIO_REG_BANK_GP_STATUS,
2479 MDIO_GP_STATUS_TOP_AN_STATUS1,
2480 &gp_status);
7f02c4ad 2481
7aa0711f
YR		 2482 if (phy->req_line_speed == SPEED_AUTO_NEG)
2483 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
ea4e040a
YR		 2484 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2485 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2486 gp_status);
2487
2488 vars->phy_link_up = 1;
2489 vars->link_status |= LINK_STATUS_LINK_UP;
2490
2491 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2492 vars->duplex = DUPLEX_FULL;
2493 else
2494 vars->duplex = DUPLEX_HALF;
2495
7aa0711f
YR		 2496 if (SINGLE_MEDIA_DIRECT(params)) {
2497 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2498 if (phy->req_line_speed == SPEED_AUTO_NEG)
2499 bnx2x_xgxs_an_resolve(phy, params, vars,
2500 gp_status);
2501 }
ea4e040a
YR		 2502
2503 switch (gp_status & GP_STATUS_SPEED_MASK) {
2504 case GP_STATUS_10M:
6c55c3cd 2505 new_line_speed = SPEED_10;
ea4e040a
YR		 2506 if (vars->duplex == DUPLEX_FULL)
2507 vars->link_status |= LINK_10TFD;
2508 else
2509 vars->link_status |= LINK_10THD;
2510 break;
2511
2512 case GP_STATUS_100M:
6c55c3cd 2513 new_line_speed = SPEED_100;
ea4e040a
YR		 2514 if (vars->duplex == DUPLEX_FULL)
2515 vars->link_status |= LINK_100TXFD;
2516 else
2517 vars->link_status |= LINK_100TXHD;
2518 break;
2519
2520 case GP_STATUS_1G:
2521 case GP_STATUS_1G_KX:
6c55c3cd 2522 new_line_speed = SPEED_1000;
ea4e040a
YR		 2523 if (vars->duplex == DUPLEX_FULL)
2524 vars->link_status |= LINK_1000TFD;
2525 else
2526 vars->link_status |= LINK_1000THD;
2527 break;
2528
2529 case GP_STATUS_2_5G:
6c55c3cd 2530 new_line_speed = SPEED_2500;
ea4e040a
YR		 2531 if (vars->duplex == DUPLEX_FULL)
2532 vars->link_status |= LINK_2500TFD;
2533 else
2534 vars->link_status |= LINK_2500THD;
2535 break;
2536
2537 case GP_STATUS_5G:
2538 case GP_STATUS_6G:
2539 DP(NETIF_MSG_LINK,
2540 "link speed unsupported gp_status 0x%x\n",
2541 gp_status);
2542 return -EINVAL;
ab6ad5a4 2543
ea4e040a
YR		 2544 case GP_STATUS_10G_KX4:
2545 case GP_STATUS_10G_HIG:
2546 case GP_STATUS_10G_CX4:
6c55c3cd 2547 new_line_speed = SPEED_10000;
ea4e040a
YR		 2548 vars->link_status |= LINK_10GTFD;
2549 break;
2550
2551 case GP_STATUS_12G_HIG:
6c55c3cd 2552 new_line_speed = SPEED_12000;
ea4e040a
YR		 2553 vars->link_status |= LINK_12GTFD;
2554 break;
2555
2556 case GP_STATUS_12_5G:
6c55c3cd 2557 new_line_speed = SPEED_12500;
ea4e040a
YR		 2558 vars->link_status |= LINK_12_5GTFD;
2559 break;
2560
2561 case GP_STATUS_13G:
6c55c3cd 2562 new_line_speed = SPEED_13000;
ea4e040a
YR		 2563 vars->link_status |= LINK_13GTFD;
2564 break;
2565
2566 case GP_STATUS_15G:
6c55c3cd 2567 new_line_speed = SPEED_15000;
ea4e040a
YR		 2568 vars->link_status |= LINK_15GTFD;
2569 break;
2570
2571 case GP_STATUS_16G:
6c55c3cd 2572 new_line_speed = SPEED_16000;
ea4e040a
YR		 2573 vars->link_status |= LINK_16GTFD;
2574 break;
2575
2576 default:
2577 DP(NETIF_MSG_LINK,
2578 "link speed unsupported gp_status 0x%x\n",
2579 gp_status);
ab6ad5a4 2580 return -EINVAL;
ea4e040a
YR		 2581 }
2582
6c55c3cd 2583 vars->line_speed = new_line_speed;
ea4e040a 2584
ea4e040a
YR		 2585 } else { /* link_down */
2586 DP(NETIF_MSG_LINK, "phy link down\n");
2587
2588 vars->phy_link_up = 0;
57963ed9 2589
ea4e040a 2590 vars->duplex = DUPLEX_FULL;
c0700f90 2591 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 2592 vars->mac_type = MAC_TYPE_NONE;
239d686d 2593
c18aa15d
YR		 2594 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2595 SINGLE_MEDIA_DIRECT(params)) {
239d686d 2596 /* Check signal is detected */
c18aa15d 2597 bnx2x_check_fallback_to_cl37(phy, params);
239d686d 2598 }
ea4e040a
YR		 2599 }
2600
2381a55c 2601 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
ea4e040a 2602 gp_status, vars->phy_link_up, vars->line_speed);
a22f0788
YR		 2603 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
2604 vars->duplex, vars->flow_ctrl, vars->link_status);
ea4e040a
YR		 2605 return rc;
2606}
2607
ed8680a7 2608static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 2609{
2610 struct bnx2x *bp = params->bp;
e10bc84d 2611 struct bnx2x_phy *phy = &params->phy[INT_PHY];
ea4e040a
YR		 2612 u16 lp_up2;
2613 u16 tx_driver;
c2c8b03e 2614 u16 bank;
ea4e040a
YR		 2615
2616 /* read precomp */
cd2be89b 2617 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2618 MDIO_REG_BANK_OVER_1G,
2619 MDIO_OVER_1G_LP_UP2, &lp_up2);
ea4e040a 2620
ea4e040a
YR		 2621 /* bits [10:7] at lp_up2, positioned at [15:12] */
2622 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2623 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2624 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2625
c2c8b03e
EG		 2626 if (lp_up2 == 0)
2627 return;
2628
2629 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2630 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
cd2be89b 2631 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2632 bank,
2633 MDIO_TX0_TX_DRIVER, &tx_driver);
c2c8b03e
EG		 2634
2635 /* replace tx_driver bits [15:12] */
2636 if (lp_up2 !=
2637 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2638 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2639 tx_driver |= lp_up2;
cd2be89b 2640 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2641 bank,
2642 MDIO_TX0_TX_DRIVER, tx_driver);
c2c8b03e 2643 }
ea4e040a
YR		 2644 }
2645}
2646
2647static u8 bnx2x_emac_program(struct link_params *params,
b7737c9b 2648 struct link_vars *vars)
ea4e040a
YR		 2649{
2650 struct bnx2x *bp = params->bp;
2651 u8 port = params->port;
2652 u16 mode = 0;
2653
2654 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2655 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
cd88ccee
YR		 2656 EMAC_REG_EMAC_MODE,
2657 (EMAC_MODE_25G_MODE |
2658 EMAC_MODE_PORT_MII_10M |
2659 EMAC_MODE_HALF_DUPLEX));
b7737c9b 2660 switch (vars->line_speed) {
ea4e040a
YR		 2661 case SPEED_10:
2662 mode |= EMAC_MODE_PORT_MII_10M;
2663 break;
2664
2665 case SPEED_100:
2666 mode |= EMAC_MODE_PORT_MII;
2667 break;
2668
2669 case SPEED_1000:
2670 mode |= EMAC_MODE_PORT_GMII;
2671 break;
2672
2673 case SPEED_2500:
2674 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2675 break;
2676
2677 default:
2678 /* 10G not valid for EMAC */
b7737c9b
YR		 2679 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2680 vars->line_speed);
ea4e040a
YR		 2681 return -EINVAL;
2682 }
2683
b7737c9b 2684 if (vars->duplex == DUPLEX_HALF)
ea4e040a
YR		 2685 mode |= EMAC_MODE_HALF_DUPLEX;
2686 bnx2x_bits_en(bp,
cd88ccee
YR		 2687 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2688 mode);
ea4e040a 2689
7f02c4ad 2690 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 2691 return 0;
2692}
2693
de6eae1f
YR		 2694static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2695 struct link_params *params)
b7737c9b 2696{
de6eae1f
YR		 2697
2698 u16 bank, i = 0;
2699 struct bnx2x *bp = params->bp;
2700
2701 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2702 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
cd2be89b 2703 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 2704 bank,
2705 MDIO_RX0_RX_EQ_BOOST,
2706 phy->rx_preemphasis[i]);
2707 }
2708
2709 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2710 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
cd2be89b 2711 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 2712 bank,
2713 MDIO_TX0_TX_DRIVER,
2714 phy->tx_preemphasis[i]);
2715 }
2716}
2717
2718static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2719 struct link_params *params,
2720 struct link_vars *vars)
2721{
2722 struct bnx2x *bp = params->bp;
2723 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2724 (params->loopback_mode == LOOPBACK_XGXS));
2725 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2726 if (SINGLE_MEDIA_DIRECT(params) &&
2727 (params->feature_config_flags &
2728 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2729 bnx2x_set_preemphasis(phy, params);
2730
2731 /* forced speed requested? */
2732 if (vars->line_speed != SPEED_AUTO_NEG ||
2733 (SINGLE_MEDIA_DIRECT(params) &&
cd88ccee 2734 params->loopback_mode == LOOPBACK_EXT)) {
de6eae1f
YR		 2735 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2736
2737 /* disable autoneg */
2738 bnx2x_set_autoneg(phy, params, vars, 0);
2739
2740 /* program speed and duplex */
2741 bnx2x_program_serdes(phy, params, vars);
2742
2743 } else { /* AN_mode */
2744 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2745
2746 /* AN enabled */
2747 bnx2x_set_brcm_cl37_advertisment(phy, params);
2748
2749 /* program duplex & pause advertisement (for aneg) */
2750 bnx2x_set_ieee_aneg_advertisment(phy, params,
cd88ccee 2751 vars->ieee_fc);
de6eae1f
YR		 2752
2753 /* enable autoneg */
2754 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2755
2756 /* enable and restart AN */
2757 bnx2x_restart_autoneg(phy, params, enable_cl73);
2758 }
2759
2760 } else { /* SGMII mode */
2761 DP(NETIF_MSG_LINK, "SGMII\n");
2762
2763 bnx2x_initialize_sgmii_process(phy, params, vars);
2764 }
2765}
2766
2767static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2768 struct link_params *params,
2769 struct link_vars *vars)
2770{
2771 u8 rc;
2772 vars->phy_flags |= PHY_SGMII_FLAG;
b7737c9b 2773 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
f2e0899f 2774 bnx2x_set_aer_mmd_serdes(params->bp, phy);
b7737c9b
YR		 2775 rc = bnx2x_reset_unicore(params, phy, 1);
2776 /* reset the SerDes and wait for reset bit return low */
2777 if (rc != 0)
2778 return rc;
f2e0899f 2779 bnx2x_set_aer_mmd_serdes(params->bp, phy);
b7737c9b
YR		 2780
2781 return rc;
2782}
2783
2784static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2785 struct link_params *params,
2786 struct link_vars *vars)
2787{
2788 u8 rc;
2789 vars->phy_flags = PHY_XGXS_FLAG;
2790 if ((phy->req_line_speed &&
2791 ((phy->req_line_speed == SPEED_100) ||
2792 (phy->req_line_speed == SPEED_10))) ||
2793 (!phy->req_line_speed &&
2794 (phy->speed_cap_mask >=
2795 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2796 (phy->speed_cap_mask <
2797 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2798 ))
2799 vars->phy_flags |= PHY_SGMII_FLAG;
2800 else
2801 vars->phy_flags &= ~PHY_SGMII_FLAG;
2802
2803 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
f2e0899f 2804 bnx2x_set_aer_mmd_xgxs(params, phy);
b7737c9b
YR		 2805 bnx2x_set_master_ln(params, phy);
2806
2807 rc = bnx2x_reset_unicore(params, phy, 0);
2808 /* reset the SerDes and wait for reset bit return low */
2809 if (rc != 0)
2810 return rc;
2811
f2e0899f 2812 bnx2x_set_aer_mmd_xgxs(params, phy);
e10bc84d 2813
b7737c9b
YR		 2814 /* setting the masterLn_def again after the reset */
2815 bnx2x_set_master_ln(params, phy);
2816 bnx2x_set_swap_lanes(params, phy);
2817
2818 return rc;
2819}
c18aa15d 2820
de6eae1f 2821static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6d870c39
YR		 2822 struct bnx2x_phy *phy,
2823 struct link_params *params)
ea4e040a 2824{
de6eae1f 2825 u16 cnt, ctrl;
25985edc 2826 /* Wait for soft reset to get cleared up to 1 sec */
de6eae1f
YR		 2827 for (cnt = 0; cnt < 1000; cnt++) {
2828 bnx2x_cl45_read(bp, phy,
2829 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2830 if (!(ctrl & (1<<15)))
2831 break;
2832 msleep(1);
2833 }
6d870c39
YR		 2834
2835 if (cnt == 1000)
2836 netdev_err(bp->dev, "Warning: PHY was not initialized,"
2837 " Port %d\n",
2838 params->port);
de6eae1f
YR		 2839 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2840 return cnt;
ea4e040a
YR		 2841}
2842
de6eae1f 2843static void bnx2x_link_int_enable(struct link_params *params)
a35da8db 2844{
de6eae1f
YR		 2845 u8 port = params->port;
2846 u32 mask;
2847 struct bnx2x *bp = params->bp;
c18aa15d 2848
2cf7acf9 2849 /* Setting the status to report on link up for either XGXS or SerDes */
de6eae1f
YR		 2850 if (params->switch_cfg == SWITCH_CFG_10G) {
2851 mask = (NIG_MASK_XGXS0_LINK10G |
2852 NIG_MASK_XGXS0_LINK_STATUS);
2853 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2854 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2855 params->phy[INT_PHY].type !=
2856 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2857 mask |= NIG_MASK_MI_INT;
2858 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2859 }
2860
2861 } else { /* SerDes */
2862 mask = NIG_MASK_SERDES0_LINK_STATUS;
2863 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2864 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2865 params->phy[INT_PHY].type !=
2866 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2867 mask |= NIG_MASK_MI_INT;
2868 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2869 }
2870 }
2871 bnx2x_bits_en(bp,
2872 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2873 mask);
2874
2875 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2876 (params->switch_cfg == SWITCH_CFG_10G),
2877 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2878 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2879 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2880 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2881 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2882 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2883 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2884 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
a35da8db
EG		 2885}
2886
a22f0788
YR		 2887static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2888 u8 exp_mi_int)
a35da8db 2889{
a22f0788
YR		 2890 u32 latch_status = 0;
2891
2cf7acf9 2892 /*
a22f0788
YR		 2893 * Disable the MI INT ( external phy int ) by writing 1 to the
2894 * status register. Link down indication is high-active-signal,
2895 * so in this case we need to write the status to clear the XOR
de6eae1f
YR		 2896 */
2897 /* Read Latched signals */
2898 latch_status = REG_RD(bp,
a22f0788
YR		 2899 NIG_REG_LATCH_STATUS_0 + port*8);
2900 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
de6eae1f 2901 /* Handle only those with latched-signal=up.*/
a22f0788
YR		 2902 if (exp_mi_int)
2903 bnx2x_bits_en(bp,
2904 NIG_REG_STATUS_INTERRUPT_PORT0
2905 + port*4,
2906 NIG_STATUS_EMAC0_MI_INT);
2907 else
2908 bnx2x_bits_dis(bp,
2909 NIG_REG_STATUS_INTERRUPT_PORT0
2910 + port*4,
2911 NIG_STATUS_EMAC0_MI_INT);
2912
de6eae1f 2913 if (latch_status & 1) {
a22f0788 2914
de6eae1f
YR		 2915 /* For all latched-signal=up : Re-Arm Latch signals */
2916 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
cd88ccee 2917 (latch_status & 0xfffe) | (latch_status & 1));
de6eae1f 2918 }
a22f0788 2919 /* For all latched-signal=up,Write original_signal to status */
a35da8db
EG		 2920}
2921
de6eae1f 2922static void bnx2x_link_int_ack(struct link_params *params,
cd88ccee 2923 struct link_vars *vars, u8 is_10g)
b1607af5 2924{
e10bc84d 2925 struct bnx2x *bp = params->bp;
de6eae1f 2926 u8 port = params->port;
e10bc84d 2927
2cf7acf9
YR		 2928 /*
2929 * First reset all status we assume only one line will be
2930 * change at a time
2931 */
de6eae1f 2932 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 2933 (NIG_STATUS_XGXS0_LINK10G |
2934 NIG_STATUS_XGXS0_LINK_STATUS |
2935 NIG_STATUS_SERDES0_LINK_STATUS));
de6eae1f
YR		 2936 if (vars->phy_link_up) {
2937 if (is_10g) {
2cf7acf9
YR		 2938 /*
2939 * Disable the 10G link interrupt by writing 1 to the
2940 * status register
de6eae1f
YR		 2941 */
2942 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2943 bnx2x_bits_en(bp,
2944 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2945 NIG_STATUS_XGXS0_LINK10G);
b1607af5 2946
de6eae1f 2947 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2cf7acf9
YR		 2948 /*
2949 * Disable the link interrupt by writing 1 to the
2950 * relevant lane in the status register
de6eae1f
YR		 2951 */
2952 u32 ser_lane = ((params->lane_config &
2953 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2954 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
b1607af5 2955
de6eae1f
YR		 2956 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2957 vars->line_speed);
2958 bnx2x_bits_en(bp,
2959 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2960 ((1 << ser_lane) <<
2961 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
ea4e040a 2962
de6eae1f
YR		 2963 } else { /* SerDes */
2964 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2cf7acf9
YR		 2965 /*
2966 * Disable the link interrupt by writing 1 to the status
2967 * register
de6eae1f
YR		 2968 */
2969 bnx2x_bits_en(bp,
2970 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2971 NIG_STATUS_SERDES0_LINK_STATUS);
2972 }
ea4e040a 2973
ea4e040a 2974 }
ea4e040a 2975}
ea4e040a 2976
de6eae1f
YR		 2977static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2978{
2979 u8 *str_ptr = str;
2980 u32 mask = 0xf0000000;
2981 u8 shift = 8*4;
2982 u8 digit;
a22f0788 2983 u8 remove_leading_zeros = 1;
de6eae1f
YR		 2984 if (*len < 10) {
2985 /* Need more than 10chars for this format */
2986 *str_ptr = '\0';
a22f0788 2987 (*len)--;
de6eae1f 2988 return -EINVAL;
ea4e040a 2989 }
de6eae1f 2990 while (shift > 0) {
ea4e040a 2991
de6eae1f
YR		 2992 shift -= 4;
2993 digit = ((num & mask) >> shift);
a22f0788
YR		 2994 if (digit == 0 && remove_leading_zeros) {
2995 mask = mask >> 4;
2996 continue;
2997 } else if (digit < 0xa)
de6eae1f
YR		 2998 *str_ptr = digit + '0';
2999 else
3000 *str_ptr = digit - 0xa + 'a';
a22f0788 3001 remove_leading_zeros = 0;
de6eae1f 3002 str_ptr++;
a22f0788 3003 (*len)--;
de6eae1f
YR		 3004 mask = mask >> 4;
3005 if (shift == 4*4) {
a22f0788 3006 *str_ptr = '.';
de6eae1f 3007 str_ptr++;
a22f0788
YR		 3008 (*len)--;
3009 remove_leading_zeros = 1;
ea4e040a 3010 }
ea4e040a 3011 }
de6eae1f 3012 return 0;
ea4e040a
YR		 3013}
3014
a22f0788 3015
de6eae1f 3016static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
ea4e040a 3017{
de6eae1f
YR		 3018 str[0] = '\0';
3019 (*len)--;
3020 return 0;
3021}
ea4e040a 3022
de6eae1f
YR		 3023u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3024 u8 *version, u16 len)
3025{
3026 struct bnx2x *bp;
3027 u32 spirom_ver = 0;
3028 u8 status = 0;
3029 u8 *ver_p = version;
a22f0788 3030 u16 remain_len = len;
de6eae1f
YR		 3031 if (version == NULL || params == NULL)
3032 return -EINVAL;
3033 bp = params->bp;
ea4e040a 3034
de6eae1f
YR		 3035 /* Extract first external phy*/
3036 version[0] = '\0';
3037 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
ea4e040a 3038
a22f0788 3039 if (params->phy[EXT_PHY1].format_fw_ver) {
de6eae1f
YR		 3040 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3041 ver_p,
a22f0788
YR		 3042 &remain_len);
3043 ver_p += (len - remain_len);
3044 }
3045 if ((params->num_phys == MAX_PHYS) &&
3046 (params->phy[EXT_PHY2].ver_addr != 0)) {
cd88ccee 3047 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
a22f0788
YR		 3048 if (params->phy[EXT_PHY2].format_fw_ver) {
3049 *ver_p = '/';
3050 ver_p++;
3051 remain_len--;
3052 status |= params->phy[EXT_PHY2].format_fw_ver(
3053 spirom_ver,
3054 ver_p,
3055 &remain_len);
3056 ver_p = version + (len - remain_len);
3057 }
3058 }
3059 *ver_p = '\0';
de6eae1f 3060 return status;
6bbca910 3061}
ea4e040a 3062
de6eae1f
YR		 3063static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3064 struct link_params *params)
589abe3a 3065{
de6eae1f 3066 u8 port = params->port;
589abe3a 3067 struct bnx2x *bp = params->bp;
589abe3a 3068
de6eae1f
YR		 3069 if (phy->req_line_speed != SPEED_1000) {
3070 u32 md_devad;
589abe3a 3071
de6eae1f 3072 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
589abe3a 3073
de6eae1f
YR		 3074 /* change the uni_phy_addr in the nig */
3075 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
cd88ccee 3076 port*0x18));
cc1cb004 3077
de6eae1f 3078 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
589abe3a 3079
de6eae1f 3080 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3081 5,
3082 (MDIO_REG_BANK_AER_BLOCK +
3083 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3084 0x2800);
589abe3a 3085
de6eae1f 3086 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3087 5,
3088 (MDIO_REG_BANK_CL73_IEEEB0 +
3089 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3090 0x6041);
de6eae1f
YR		 3091 msleep(200);
3092 /* set aer mmd back */
f2e0899f 3093 bnx2x_set_aer_mmd_xgxs(params, phy);
589abe3a 3094
de6eae1f 3095 /* and md_devad */
cd88ccee 3096 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
de6eae1f
YR		 3097 } else {
3098 u16 mii_ctrl;
3099 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3100 bnx2x_cl45_read(bp, phy, 5,
3101 (MDIO_REG_BANK_COMBO_IEEE0 +
3102 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3103 &mii_ctrl);
3104 bnx2x_cl45_write(bp, phy, 5,
3105 (MDIO_REG_BANK_COMBO_IEEE0 +
3106 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3107 mii_ctrl |
3108 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3109 }
589abe3a
EG		 3110}
3111
7f02c4ad
YR		 3112u8 bnx2x_set_led(struct link_params *params,
3113 struct link_vars *vars, u8 mode, u32 speed)
4d295db0 3114{
de6eae1f
YR		 3115 u8 port = params->port;
3116 u16 hw_led_mode = params->hw_led_mode;
7f02c4ad 3117 u8 rc = 0, phy_idx;
de6eae1f
YR		 3118 u32 tmp;
3119 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
589abe3a 3120 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3121 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3122 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3123 speed, hw_led_mode);
7f02c4ad
YR		 3124 /* In case */
3125 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3126 if (params->phy[phy_idx].set_link_led) {
3127 params->phy[phy_idx].set_link_led(
3128 &params->phy[phy_idx], params, mode);
3129 }
3130 }
3131
de6eae1f 3132 switch (mode) {
7f02c4ad 3133 case LED_MODE_FRONT_PANEL_OFF:
de6eae1f
YR		 3134 case LED_MODE_OFF:
3135 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3136 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
cd88ccee 3137 SHARED_HW_CFG_LED_MAC1);
589abe3a 3138
de6eae1f
YR		 3139 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3140 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3141 break;
589abe3a 3142
de6eae1f 3143 case LED_MODE_OPER:
2cf7acf9 3144 /*
7f02c4ad
YR		 3145 * For all other phys, OPER mode is same as ON, so in case
3146 * link is down, do nothing
2cf7acf9 3147 */
7f02c4ad
YR		 3148 if (!vars->link_up)
3149 break;
3150 case LED_MODE_ON:
1f48353a
YR		 3151 if (params->phy[EXT_PHY1].type ==
3152 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 &&
3153 CHIP_IS_E2(bp) && params->num_phys == 2) {
2cf7acf9
YR		 3154 /*
3155 * This is a work-around for E2+8727 Configurations
3156 */
1f48353a
YR		 3157 if (mode == LED_MODE_ON ||
3158 speed == SPEED_10000){
3159 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3160 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3161
3162 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3163 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3164 (tmp | EMAC_LED_OVERRIDE));
3165 return rc;
3166 }
3167 } else if (SINGLE_MEDIA_DIRECT(params)) {
2cf7acf9
YR		 3168 /*
3169 * This is a work-around for HW issue found when link
3170 * is up in CL73
3171 */
de6eae1f
YR		 3172 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3173 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3174 } else {
cd88ccee 3175 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
de6eae1f 3176 }
589abe3a 3177
cd88ccee 3178 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
de6eae1f
YR		 3179 /* Set blinking rate to ~15.9Hz */
3180 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
cd88ccee 3181 LED_BLINK_RATE_VAL);
de6eae1f 3182 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
cd88ccee 3183 port*4, 1);
de6eae1f 3184 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
cd88ccee 3185 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
589abe3a 3186
de6eae1f
YR		 3187 if (CHIP_IS_E1(bp) &&
3188 ((speed == SPEED_2500) ||
3189 (speed == SPEED_1000) ||
3190 (speed == SPEED_100) ||
3191 (speed == SPEED_10))) {
2cf7acf9
YR		 3192 /*
3193 * On Everest 1 Ax chip versions for speeds less than
3194 * 10G LED scheme is different
3195 */
de6eae1f 3196 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
cd88ccee 3197 + port*4, 1);
de6eae1f 3198 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
cd88ccee 3199 port*4, 0);
de6eae1f 3200 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
cd88ccee 3201 port*4, 1);
de6eae1f
YR		 3202 }
3203 break;
589abe3a 3204
de6eae1f
YR		 3205 default:
3206 rc = -EINVAL;
3207 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3208 mode);
3209 break;
589abe3a 3210 }
de6eae1f 3211 return rc;
589abe3a 3212
4d295db0
EG		 3213}
3214
2cf7acf9 3215/*
a22f0788
YR		 3216 * This function comes to reflect the actual link state read DIRECTLY from the
3217 * HW
3218 */
3219u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3220 u8 is_serdes)
4d295db0
EG		 3221{
3222 struct bnx2x *bp = params->bp;
de6eae1f 3223 u16 gp_status = 0, phy_index = 0;
a22f0788
YR		 3224 u8 ext_phy_link_up = 0, serdes_phy_type;
3225 struct link_vars temp_vars;
4d295db0 3226
cd2be89b 3227 CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
cd88ccee
YR		 3228 MDIO_REG_BANK_GP_STATUS,
3229 MDIO_GP_STATUS_TOP_AN_STATUS1,
3230 &gp_status);
de6eae1f 3231 /* link is up only if both local phy and external phy are up */
a22f0788
YR		 3232 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3233 return -ESRCH;
3234
3235 switch (params->num_phys) {
3236 case 1:
3237 /* No external PHY */
3238 return 0;
3239 case 2:
3240 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3241 &params->phy[EXT_PHY1],
3242 params, &temp_vars);
3243 break;
3244 case 3: /* Dual Media */
de6eae1f
YR		 3245 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3246 phy_index++) {
a22f0788
YR		 3247 serdes_phy_type = ((params->phy[phy_index].media_type ==
3248 ETH_PHY_SFP_FIBER) ||
3249 (params->phy[phy_index].media_type ==
3250 ETH_PHY_XFP_FIBER));
3251
3252 if (is_serdes != serdes_phy_type)
3253 continue;
3254 if (params->phy[phy_index].read_status) {
3255 ext_phy_link_up |=
de6eae1f
YR		 3256 params->phy[phy_index].read_status(
3257 &params->phy[phy_index],
3258 params, &temp_vars);
a22f0788 3259 }
de6eae1f 3260 }
a22f0788 3261 break;
4d295db0 3262 }
a22f0788
YR		 3263 if (ext_phy_link_up)
3264 return 0;
de6eae1f
YR		 3265 return -ESRCH;
3266}
4d295db0 3267
de6eae1f
YR		 3268static u8 bnx2x_link_initialize(struct link_params *params,
3269 struct link_vars *vars)
3270{
3271 u8 rc = 0;
3272 u8 phy_index, non_ext_phy;
3273 struct bnx2x *bp = params->bp;
2cf7acf9
YR		 3274 /*
3275 * In case of external phy existence, the line speed would be the
3276 * line speed linked up by the external phy. In case it is direct
3277 * only, then the line_speed during initialization will be
3278 * equal to the req_line_speed
3279 */
de6eae1f 3280 vars->line_speed = params->phy[INT_PHY].req_line_speed;
4d295db0 3281
2cf7acf9 3282 /*
de6eae1f
YR		 3283 * Initialize the internal phy in case this is a direct board
3284 * (no external phys), or this board has external phy which requires
3285 * to first.
3286 */
4d295db0 3287
de6eae1f
YR		 3288 if (params->phy[INT_PHY].config_init)
3289 params->phy[INT_PHY].config_init(
3290 &params->phy[INT_PHY],
3291 params, vars);
4d295db0 3292
de6eae1f
YR		 3293 /* init ext phy and enable link state int */
3294 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3295 (params->loopback_mode == LOOPBACK_XGXS));
4d295db0 3296
de6eae1f
YR		 3297 if (non_ext_phy ||
3298 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3299 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3300 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3301 if (vars->line_speed == SPEED_AUTO_NEG)
3302 bnx2x_set_parallel_detection(phy, params);
3303 bnx2x_init_internal_phy(phy, params, vars);
4d295db0
EG		 3304 }
3305
de6eae1f
YR		 3306 /* Init external phy*/
3307 if (!non_ext_phy)
3308 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3309 phy_index++) {
2cf7acf9 3310 /*
a22f0788
YR		 3311 * No need to initialize second phy in case of first
3312 * phy only selection. In case of second phy, we do
3313 * need to initialize the first phy, since they are
3314 * connected.
2cf7acf9 3315 */
a22f0788
YR		 3316 if (phy_index == EXT_PHY2 &&
3317 (bnx2x_phy_selection(params) ==
3318 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
2cf7acf9 3319 DP(NETIF_MSG_LINK, "Ignoring second phy\n");
a22f0788
YR		 3320 continue;
3321 }
de6eae1f
YR		 3322 params->phy[phy_index].config_init(
3323 &params->phy[phy_index],
3324 params, vars);
3325 }
4d295db0 3326
de6eae1f
YR		 3327 /* Reset the interrupt indication after phy was initialized */
3328 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3329 params->port*4,
3330 (NIG_STATUS_XGXS0_LINK10G |
3331 NIG_STATUS_XGXS0_LINK_STATUS |
3332 NIG_STATUS_SERDES0_LINK_STATUS |
3333 NIG_MASK_MI_INT));
3334 return rc;
3335}
4d295db0 3336
de6eae1f
YR		 3337static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3338 struct link_params *params)
3339{
3340 /* reset the SerDes/XGXS */
cd88ccee
YR		 3341 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3342 (0x1ff << (params->port*16)));
589abe3a
EG		 3343}
3344
de6eae1f
YR		 3345static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3346 struct link_params *params)
4d295db0 3347{
de6eae1f
YR		 3348 struct bnx2x *bp = params->bp;
3349 u8 gpio_port;
3350 /* HW reset */
f2e0899f
DK		 3351 if (CHIP_IS_E2(bp))
3352 gpio_port = BP_PATH(bp);
3353 else
3354 gpio_port = params->port;
de6eae1f 3355 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee
YR		 3356 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3357 gpio_port);
de6eae1f 3358 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 3359 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3360 gpio_port);
de6eae1f 3361 DP(NETIF_MSG_LINK, "reset external PHY\n");
4d295db0 3362}
589abe3a 3363
de6eae1f
YR		 3364static u8 bnx2x_update_link_down(struct link_params *params,
3365 struct link_vars *vars)
589abe3a
EG		 3366{
3367 struct bnx2x *bp = params->bp;
de6eae1f 3368 u8 port = params->port;
589abe3a 3369
de6eae1f 3370 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
7f02c4ad 3371 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
589abe3a 3372
de6eae1f
YR		 3373 /* indicate no mac active */
3374 vars->mac_type = MAC_TYPE_NONE;
ab6ad5a4 3375
de6eae1f
YR		 3376 /* update shared memory */
3377 vars->link_status = 0;
3378 vars->line_speed = 0;
3379 bnx2x_update_mng(params, vars->link_status);
589abe3a 3380
de6eae1f
YR		 3381 /* activate nig drain */
3382 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4d295db0 3383
de6eae1f
YR		 3384 /* disable emac */
3385 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3386
3387 msleep(10);
3388
3389 /* reset BigMac */
3390 bnx2x_bmac_rx_disable(bp, params->port);
cd88ccee
YR		 3391 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3392 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
589abe3a
EG		 3393 return 0;
3394}
de6eae1f
YR		 3395
3396static u8 bnx2x_update_link_up(struct link_params *params,
3397 struct link_vars *vars,
3398 u8 link_10g)
589abe3a
EG		 3399{
3400 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3401 u8 port = params->port;
3402 u8 rc = 0;
4d295db0 3403
de6eae1f 3404 vars->link_status |= LINK_STATUS_LINK_UP;
7f02c4ad 3405
de6eae1f
YR		 3406 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3407 vars->link_status |=
3408 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
589abe3a 3409
de6eae1f
YR		 3410 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3411 vars->link_status |=
3412 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7f02c4ad 3413
de6eae1f
YR		 3414 if (link_10g) {
3415 bnx2x_bmac_enable(params, vars, 0);
7f02c4ad
YR		 3416 bnx2x_set_led(params, vars,
3417 LED_MODE_OPER, SPEED_10000);
de6eae1f
YR		 3418 } else {
3419 rc = bnx2x_emac_program(params, vars);
cc1cb004 3420
de6eae1f 3421 bnx2x_emac_enable(params, vars, 0);
cc1cb004 3422
de6eae1f
YR		 3423 /* AN complete? */
3424 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3425 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3426 SINGLE_MEDIA_DIRECT(params))
3427 bnx2x_set_gmii_tx_driver(params);
3428 }
cc1cb004 3429
de6eae1f 3430 /* PBF - link up */
f2e0899f
DK		 3431 if (!(CHIP_IS_E2(bp)))
3432 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3433 vars->line_speed);
589abe3a 3434
de6eae1f
YR		 3435 /* disable drain */
3436 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
589abe3a 3437
de6eae1f
YR		 3438 /* update shared memory */
3439 bnx2x_update_mng(params, vars->link_status);
3440 msleep(20);
3441 return rc;
589abe3a 3442}
2cf7acf9 3443/*
de6eae1f
YR		 3444 * The bnx2x_link_update function should be called upon link
3445 * interrupt.
3446 * Link is considered up as follows:
3447 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3448 * to be up
3449 * - SINGLE_MEDIA - The link between the 577xx and the external
3450 * phy (XGXS) need to up as well as the external link of the
3451 * phy (PHY_EXT1)
3452 * - DUAL_MEDIA - The link between the 577xx and the first
3453 * external phy needs to be up, and at least one of the 2
3454 * external phy link must be up.
3455 */
3456u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4d295db0 3457{
de6eae1f
YR		 3458 struct bnx2x *bp = params->bp;
3459 struct link_vars phy_vars[MAX_PHYS];
3460 u8 port = params->port;
3461 u8 link_10g, phy_index;
3462 u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
3463 u8 is_mi_int = 0;
3464 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3465 u8 active_external_phy = INT_PHY;
3466 vars->link_status = 0;
3467 for (phy_index = INT_PHY; phy_index < params->num_phys;
3468 phy_index++) {
3469 phy_vars[phy_index].flow_ctrl = 0;
3470 phy_vars[phy_index].link_status = 0;
3471 phy_vars[phy_index].line_speed = 0;
3472 phy_vars[phy_index].duplex = DUPLEX_FULL;
3473 phy_vars[phy_index].phy_link_up = 0;
3474 phy_vars[phy_index].link_up = 0;
3475 }
4d295db0 3476
de6eae1f
YR		 3477 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3478 port, (vars->phy_flags & PHY_XGXS_FLAG),
3479 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4d295db0 3480
de6eae1f 3481 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
cd88ccee 3482 port*0x18) > 0);
de6eae1f
YR		 3483 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3484 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3485 is_mi_int,
cd88ccee 3486 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4d295db0 3487
de6eae1f
YR		 3488 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3489 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3490 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4d295db0 3491
de6eae1f
YR		 3492 /* disable emac */
3493 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4d295db0 3494
2cf7acf9
YR		 3495 /*
3496 * Step 1:
3497 * Check external link change only for external phys, and apply
3498 * priority selection between them in case the link on both phys
3499 * is up. Note that the instead of the common vars, a temporary
3500 * vars argument is used since each phy may have different link/
3501 * speed/duplex result
3502 */
de6eae1f
YR		 3503 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3504 phy_index++) {
3505 struct bnx2x_phy *phy = &params->phy[phy_index];
3506 if (!phy->read_status)
3507 continue;
3508 /* Read link status and params of this ext phy */
3509 cur_link_up = phy->read_status(phy, params,
3510 &phy_vars[phy_index]);
3511 if (cur_link_up) {
3512 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3513 phy_index);
3514 } else {
3515 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3516 phy_index);
3517 continue;
3518 }
e10bc84d 3519
de6eae1f
YR		 3520 if (!ext_phy_link_up) {
3521 ext_phy_link_up = 1;
3522 active_external_phy = phy_index;
a22f0788
YR		 3523 } else {
3524 switch (bnx2x_phy_selection(params)) {
3525 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3526 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
2cf7acf9 3527 /*
a22f0788
YR		 3528 * In this option, the first PHY makes sure to pass the
3529 * traffic through itself only.
3530 * Its not clear how to reset the link on the second phy
2cf7acf9 3531 */
a22f0788
YR		 3532 active_external_phy = EXT_PHY1;
3533 break;
3534 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
2cf7acf9 3535 /*
a22f0788
YR		 3536 * In this option, the first PHY makes sure to pass the
3537 * traffic through the second PHY.
2cf7acf9 3538 */
a22f0788
YR		 3539 active_external_phy = EXT_PHY2;
3540 break;
3541 default:
2cf7acf9 3542 /*
a22f0788
YR		 3543 * Link indication on both PHYs with the following cases
3544 * is invalid:
3545 * - FIRST_PHY means that second phy wasn't initialized,
3546 * hence its link is expected to be down
3547 * - SECOND_PHY means that first phy should not be able
3548 * to link up by itself (using configuration)
3549 * - DEFAULT should be overriden during initialiazation
2cf7acf9 3550 */
a22f0788
YR		 3551 DP(NETIF_MSG_LINK, "Invalid link indication"
3552 "mpc=0x%x. DISABLING LINK !!!\n",
3553 params->multi_phy_config);
3554 ext_phy_link_up = 0;
3555 break;
3556 }
589abe3a 3557 }
589abe3a 3558 }
de6eae1f 3559 prev_line_speed = vars->line_speed;
2cf7acf9
YR		 3560 /*
3561 * Step 2:
3562 * Read the status of the internal phy. In case of
3563 * DIRECT_SINGLE_MEDIA board, this link is the external link,
3564 * otherwise this is the link between the 577xx and the first
3565 * external phy
3566 */
de6eae1f
YR		 3567 if (params->phy[INT_PHY].read_status)
3568 params->phy[INT_PHY].read_status(
3569 &params->phy[INT_PHY],
3570 params, vars);
2cf7acf9 3571 /*
de6eae1f
YR		 3572 * The INT_PHY flow control reside in the vars. This include the
3573 * case where the speed or flow control are not set to AUTO.
3574 * Otherwise, the active external phy flow control result is set
3575 * to the vars. The ext_phy_line_speed is needed to check if the
3576 * speed is different between the internal phy and external phy.
3577 * This case may be result of intermediate link speed change.
4d295db0 3578 */
de6eae1f
YR		 3579 if (active_external_phy > INT_PHY) {
3580 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
2cf7acf9 3581 /*
de6eae1f
YR		 3582 * Link speed is taken from the XGXS. AN and FC result from
3583 * the external phy.
4d295db0 3584 */
de6eae1f 3585 vars->link_status |= phy_vars[active_external_phy].link_status;
a22f0788 3586
2cf7acf9 3587 /*
a22f0788
YR		 3588 * if active_external_phy is first PHY and link is up - disable
3589 * disable TX on second external PHY
3590 */
3591 if (active_external_phy == EXT_PHY1) {
3592 if (params->phy[EXT_PHY2].phy_specific_func) {
3593 DP(NETIF_MSG_LINK, "Disabling TX on"
3594 " EXT_PHY2\n");
3595 params->phy[EXT_PHY2].phy_specific_func(
3596 &params->phy[EXT_PHY2],
3597 params, DISABLE_TX);
3598 }
3599 }
3600
de6eae1f
YR		 3601 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3602 vars->duplex = phy_vars[active_external_phy].duplex;
3603 if (params->phy[active_external_phy].supported &
3604 SUPPORTED_FIBRE)
3605 vars->link_status |= LINK_STATUS_SERDES_LINK;
3606 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3607 active_external_phy);
3608 }
a22f0788
YR		 3609
3610 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3611 phy_index++) {
3612 if (params->phy[phy_index].flags &
3613 FLAGS_REARM_LATCH_SIGNAL) {
3614 bnx2x_rearm_latch_signal(bp, port,
3615 phy_index ==
3616 active_external_phy);
3617 break;
3618 }
3619 }
de6eae1f
YR		 3620 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3621 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3622 vars->link_status, ext_phy_line_speed);
2cf7acf9 3623 /*
de6eae1f
YR		 3624 * Upon link speed change set the NIG into drain mode. Comes to
3625 * deals with possible FIFO glitch due to clk change when speed
3626 * is decreased without link down indicator
3627 */
4d295db0 3628
de6eae1f
YR		 3629 if (vars->phy_link_up) {
3630 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3631 (ext_phy_line_speed != vars->line_speed)) {
3632 DP(NETIF_MSG_LINK, "Internal link speed %d is"
3633 " different than the external"
3634 " link speed %d\n", vars->line_speed,
3635 ext_phy_line_speed);
3636 vars->phy_link_up = 0;
3637 } else if (prev_line_speed != vars->line_speed) {
cd88ccee
YR		 3638 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3639 0);
de6eae1f
YR		 3640 msleep(1);
3641 }
3642 }
e10bc84d 3643
de6eae1f
YR		 3644 /* anything 10 and over uses the bmac */
3645 link_10g = ((vars->line_speed == SPEED_10000) ||
3646 (vars->line_speed == SPEED_12000) ||
3647 (vars->line_speed == SPEED_12500) ||
3648 (vars->line_speed == SPEED_13000) ||
3649 (vars->line_speed == SPEED_15000) ||
3650 (vars->line_speed == SPEED_16000));
589abe3a 3651
a22f0788 3652 bnx2x_link_int_ack(params, vars, link_10g);
589abe3a 3653
2cf7acf9
YR		 3654 /*
3655 * In case external phy link is up, and internal link is down
3656 * (not initialized yet probably after link initialization, it
3657 * needs to be initialized.
3658 * Note that after link down-up as result of cable plug, the xgxs
3659 * link would probably become up again without the need
3660 * initialize it
3661 */
de6eae1f
YR		 3662 if (!(SINGLE_MEDIA_DIRECT(params))) {
3663 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3664 " init_preceding = %d\n", ext_phy_link_up,
3665 vars->phy_link_up,
3666 params->phy[EXT_PHY1].flags &
3667 FLAGS_INIT_XGXS_FIRST);
3668 if (!(params->phy[EXT_PHY1].flags &
3669 FLAGS_INIT_XGXS_FIRST)
3670 && ext_phy_link_up && !vars->phy_link_up) {
3671 vars->line_speed = ext_phy_line_speed;
3672 if (vars->line_speed < SPEED_1000)
3673 vars->phy_flags |= PHY_SGMII_FLAG;
3674 else
3675 vars->phy_flags &= ~PHY_SGMII_FLAG;
3676 bnx2x_init_internal_phy(&params->phy[INT_PHY],
3677 params,
3678 vars);
4d295db0 3679 }
589abe3a 3680 }
2cf7acf9
YR		 3681 /*
3682 * Link is up only if both local phy and external phy (in case of
3683 * non-direct board) are up
4d295db0 3684 */
de6eae1f
YR		 3685 vars->link_up = (vars->phy_link_up &&
3686 (ext_phy_link_up ||
3687 SINGLE_MEDIA_DIRECT(params)));
3688
3689 if (vars->link_up)
3690 rc = bnx2x_update_link_up(params, vars, link_10g);
4d295db0 3691 else
de6eae1f 3692 rc = bnx2x_update_link_down(params, vars);
589abe3a 3693
4d295db0 3694 return rc;
589abe3a
EG		 3695}
3696
589abe3a 3697
de6eae1f
YR		 3698/*****************************************************************************/
3699/* External Phy section */
3700/*****************************************************************************/
3701void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3702{
3703 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 3704 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
de6eae1f
YR		 3705 msleep(1);
3706 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 3707 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
de6eae1f 3708}
589abe3a 3709
de6eae1f
YR		 3710static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3711 u32 spirom_ver, u32 ver_addr)
3712{
3713 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3714 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
4d295db0 3715
de6eae1f
YR		 3716 if (ver_addr)
3717 REG_WR(bp, ver_addr, spirom_ver);
589abe3a
EG		 3718}
3719
de6eae1f
YR		 3720static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3721 struct bnx2x_phy *phy,
3722 u8 port)
6bbca910 3723{
de6eae1f
YR		 3724 u16 fw_ver1, fw_ver2;
3725
3726 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 3727 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
de6eae1f 3728 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 3729 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
de6eae1f
YR		 3730 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3731 phy->ver_addr);
ea4e040a 3732}
ab6ad5a4 3733
de6eae1f
YR		 3734static void bnx2x_ext_phy_set_pause(struct link_params *params,
3735 struct bnx2x_phy *phy,
3736 struct link_vars *vars)
ea4e040a 3737{
ea4e040a 3738 u16 val;
de6eae1f
YR		 3739 struct bnx2x *bp = params->bp;
3740 /* read modify write pause advertizing */
3741 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
ea4e040a 3742
de6eae1f 3743 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
ea4e040a 3744
de6eae1f
YR		 3745 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3746 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3747 if ((vars->ieee_fc &
3748 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3749 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
cd88ccee 3750 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
de6eae1f
YR		 3751 }
3752 if ((vars->ieee_fc &
3753 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3754 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3755 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3756 }
3757 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3758 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3759}
3760
3761static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3762 struct link_params *params,
3763 struct link_vars *vars)
3764{
3765 struct bnx2x *bp = params->bp;
3766 u16 ld_pause; /* local */
3767 u16 lp_pause; /* link partner */
3768 u16 pause_result;
3769 u8 ret = 0;
3770 /* read twice */
3771
3772 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3773
3774 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3775 vars->flow_ctrl = phy->req_flow_ctrl;
3776 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3777 vars->flow_ctrl = params->req_fc_auto_adv;
3778 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3779 ret = 1;
3780 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3781 MDIO_AN_DEVAD,
3782 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
de6eae1f 3783 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3784 MDIO_AN_DEVAD,
3785 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
de6eae1f
YR		 3786 pause_result = (ld_pause &
3787 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3788 pause_result |= (lp_pause &
3789 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3790 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3791 pause_result);
3792 bnx2x_pause_resolve(vars, pause_result);
3793 }
3794 return ret;
3795}
3796
3797static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3798 struct bnx2x_phy *phy,
3799 struct link_vars *vars)
3800{
3801 u16 val;
3802 bnx2x_cl45_read(bp, phy,
3803 MDIO_AN_DEVAD,
3804 MDIO_AN_REG_STATUS, &val);
3805 bnx2x_cl45_read(bp, phy,
3806 MDIO_AN_DEVAD,
3807 MDIO_AN_REG_STATUS, &val);
3808 if (val & (1<<5))
3809 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3810 if ((val & (1<<0)) == 0)
3811 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3812}
3813
3814/******************************************************************/
3815/* common BCM8073/BCM8727 PHY SECTION */
3816/******************************************************************/
3817static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3818 struct link_params *params,
3819 struct link_vars *vars)
3820{
3821 struct bnx2x *bp = params->bp;
3822 if (phy->req_line_speed == SPEED_10 ||
3823 phy->req_line_speed == SPEED_100) {
3824 vars->flow_ctrl = phy->req_flow_ctrl;
3825 return;
3826 }
3827
3828 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3829 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3830 u16 pause_result;
3831 u16 ld_pause; /* local */
3832 u16 lp_pause; /* link partner */
3833 bnx2x_cl45_read(bp, phy,
3834 MDIO_AN_DEVAD,
3835 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3836
3837 bnx2x_cl45_read(bp, phy,
3838 MDIO_AN_DEVAD,
3839 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3840 pause_result = (ld_pause &
3841 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3842 pause_result |= (lp_pause &
3843 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3844
3845 bnx2x_pause_resolve(vars, pause_result);
3846 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3847 pause_result);
3848 }
3849}
5c99274b 3850static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
de6eae1f
YR		 3851 struct bnx2x_phy *phy,
3852 u8 port)
3853{
5c99274b
YR		 3854 u32 count = 0;
3855 u16 fw_ver1, fw_msgout;
3856 u8 rc = 0;
3857
de6eae1f
YR		 3858 /* Boot port from external ROM */
3859 /* EDC grst */
3860 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3861 MDIO_PMA_DEVAD,
3862 MDIO_PMA_REG_GEN_CTRL,
3863 0x0001);
de6eae1f
YR		 3864
3865 /* ucode reboot and rst */
3866 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3867 MDIO_PMA_DEVAD,
3868 MDIO_PMA_REG_GEN_CTRL,
3869 0x008c);
de6eae1f
YR		 3870
3871 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3872 MDIO_PMA_DEVAD,
3873 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
de6eae1f
YR		 3874
3875 /* Reset internal microprocessor */
3876 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3877 MDIO_PMA_DEVAD,
3878 MDIO_PMA_REG_GEN_CTRL,
3879 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
de6eae1f
YR		 3880
3881 /* Release srst bit */
3882 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3883 MDIO_PMA_DEVAD,
3884 MDIO_PMA_REG_GEN_CTRL,
3885 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f 3886
5c99274b
YR		 3887 /* Delay 100ms per the PHY specifications */
3888 msleep(100);
3889
3890 /* 8073 sometimes taking longer to download */
3891 do {
3892 count++;
3893 if (count > 300) {
3894 DP(NETIF_MSG_LINK,
3895 "bnx2x_8073_8727_external_rom_boot port %x:"
3896 "Download failed. fw version = 0x%x\n",
3897 port, fw_ver1);
3898 rc = -EINVAL;
3899 break;
3900 }
3901
3902 bnx2x_cl45_read(bp, phy,
3903 MDIO_PMA_DEVAD,
3904 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3905 bnx2x_cl45_read(bp, phy,
3906 MDIO_PMA_DEVAD,
3907 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3908
3909 msleep(1);
3910 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3911 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3912 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
de6eae1f
YR		 3913
3914 /* Clear ser_boot_ctl bit */
3915 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3916 MDIO_PMA_DEVAD,
3917 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f 3918 bnx2x_save_bcm_spirom_ver(bp, phy, port);
5c99274b
YR		 3919
3920 DP(NETIF_MSG_LINK,
3921 "bnx2x_8073_8727_external_rom_boot port %x:"
3922 "Download complete. fw version = 0x%x\n",
3923 port, fw_ver1);
3924
3925 return rc;
de6eae1f
YR		 3926}
3927
de6eae1f
YR		 3928/******************************************************************/
3929/* BCM8073 PHY SECTION */
3930/******************************************************************/
3931static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3932{
3933 /* This is only required for 8073A1, version 102 only */
3934 u16 val;
3935
3936 /* Read 8073 HW revision*/
3937 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3938 MDIO_PMA_DEVAD,
3939 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 3940
3941 if (val != 1) {
3942 /* No need to workaround in 8073 A1 */
3943 return 0;
3944 }
3945
3946 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3947 MDIO_PMA_DEVAD,
3948 MDIO_PMA_REG_ROM_VER2, &val);
de6eae1f
YR		 3949
3950 /* SNR should be applied only for version 0x102 */
3951 if (val != 0x102)
3952 return 0;
3953
3954 return 1;
3955}
3956
3957static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3958{
3959 u16 val, cnt, cnt1 ;
3960
3961 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3962 MDIO_PMA_DEVAD,
3963 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 3964
3965 if (val > 0) {
3966 /* No need to workaround in 8073 A1 */
3967 return 0;
3968 }
3969 /* XAUI workaround in 8073 A0: */
3970
2cf7acf9
YR		 3971 /*
3972 * After loading the boot ROM and restarting Autoneg, poll
3973 * Dev1, Reg $C820:
3974 */
de6eae1f
YR		 3975
3976 for (cnt = 0; cnt < 1000; cnt++) {
3977 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3978 MDIO_PMA_DEVAD,
3979 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3980 &val);
2cf7acf9
YR		 3981 /*
3982 * If bit [14] = 0 or bit [13] = 0, continue on with
3983 * system initialization (XAUI work-around not required, as
3984 * these bits indicate 2.5G or 1G link up).
3985 */
de6eae1f
YR		 3986 if (!(val & (1<<14)) || !(val & (1<<13))) {
3987 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
3988 return 0;
3989 } else if (!(val & (1<<15))) {
2cf7acf9
YR		 3990 DP(NETIF_MSG_LINK, "bit 15 went off\n");
3991 /*
3992 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
3993 * MSB (bit15) goes to 1 (indicating that the XAUI
3994 * workaround has completed), then continue on with
3995 * system initialization.
3996 */
de6eae1f
YR		 3997 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
3998 bnx2x_cl45_read(bp, phy,
3999 MDIO_PMA_DEVAD,
4000 MDIO_PMA_REG_8073_XAUI_WA, &val);
4001 if (val & (1<<15)) {
4002 DP(NETIF_MSG_LINK,
4003 "XAUI workaround has completed\n");
4004 return 0;
4005 }
4006 msleep(3);
4007 }
4008 break;
4009 }
4010 msleep(3);
4011 }
4012 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4013 return -EINVAL;
4014}
4015
4016static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4017{
4018 /* Force KR or KX */
4019 bnx2x_cl45_write(bp, phy,
4020 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4021 bnx2x_cl45_write(bp, phy,
4022 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4023 bnx2x_cl45_write(bp, phy,
4024 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4025 bnx2x_cl45_write(bp, phy,
4026 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4027}
4028
6bbca910 4029static void bnx2x_8073_set_pause_cl37(struct link_params *params,
e10bc84d
YR		 4030 struct bnx2x_phy *phy,
4031 struct link_vars *vars)
ea4e040a 4032{
6bbca910 4033 u16 cl37_val;
e10bc84d
YR		 4034 struct bnx2x *bp = params->bp;
4035 bnx2x_cl45_read(bp, phy,
62b29a5d 4036 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6bbca910
YR		 4037
4038 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4039 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
e10bc84d 4040 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6bbca910
YR		 4041 if ((vars->ieee_fc &
4042 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4043 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4044 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4045 }
4046 if ((vars->ieee_fc &
4047 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4048 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4049 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4050 }
4051 if ((vars->ieee_fc &
4052 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4053 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4054 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4055 }
4056 DP(NETIF_MSG_LINK,
4057 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4058
e10bc84d 4059 bnx2x_cl45_write(bp, phy,
62b29a5d 4060 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6bbca910 4061 msleep(500);
ea4e040a
YR		 4062}
4063
de6eae1f
YR		 4064static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4065 struct link_params *params,
4066 struct link_vars *vars)
ea4e040a 4067{
e10bc84d 4068 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4069 u16 val = 0, tmp1;
4070 u8 gpio_port;
4071 DP(NETIF_MSG_LINK, "Init 8073\n");
e10bc84d 4072
f2e0899f
DK		 4073 if (CHIP_IS_E2(bp))
4074 gpio_port = BP_PATH(bp);
4075 else
4076 gpio_port = params->port;
de6eae1f
YR		 4077 /* Restore normal power mode*/
4078 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 4079 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
e10bc84d 4080
de6eae1f 4081 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 4082 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
ea4e040a 4083
de6eae1f
YR		 4084 /* enable LASI */
4085 bnx2x_cl45_write(bp, phy,
4086 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4087 bnx2x_cl45_write(bp, phy,
4088 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
c2c8b03e 4089
de6eae1f 4090 bnx2x_8073_set_pause_cl37(params, phy, vars);
57963ed9 4091
e10bc84d 4092 bnx2x_cl45_read(bp, phy,
de6eae1f 4093 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
2f904460 4094
de6eae1f
YR		 4095 bnx2x_cl45_read(bp, phy,
4096 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
2f904460 4097
de6eae1f 4098 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
a1e4be39 4099
74d7a119
YR		 4100 /* Swap polarity if required - Must be done only in non-1G mode */
4101 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4102 /* Configure the 8073 to swap _P and _N of the KR lines */
4103 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4104 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4105 bnx2x_cl45_read(bp, phy,
4106 MDIO_PMA_DEVAD,
4107 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4108 bnx2x_cl45_write(bp, phy,
4109 MDIO_PMA_DEVAD,
4110 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4111 (val | (3<<9)));
4112 }
4113
4114
de6eae1f 4115 /* Enable CL37 BAM */
121839be
YR		 4116 if (REG_RD(bp, params->shmem_base +
4117 offsetof(struct shmem_region, dev_info.
4118 port_hw_config[params->port].default_cfg)) &
4119 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
57963ed9 4120
121839be
YR		 4121 bnx2x_cl45_read(bp, phy,
4122 MDIO_AN_DEVAD,
4123 MDIO_AN_REG_8073_BAM, &val);
4124 bnx2x_cl45_write(bp, phy,
4125 MDIO_AN_DEVAD,
4126 MDIO_AN_REG_8073_BAM, val | 1);
4127 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4128 }
de6eae1f
YR		 4129 if (params->loopback_mode == LOOPBACK_EXT) {
4130 bnx2x_807x_force_10G(bp, phy);
4131 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4132 return 0;
4133 } else {
4134 bnx2x_cl45_write(bp, phy,
4135 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4136 }
4137 if (phy->req_line_speed != SPEED_AUTO_NEG) {
4138 if (phy->req_line_speed == SPEED_10000) {
4139 val = (1<<7);
4140 } else if (phy->req_line_speed == SPEED_2500) {
4141 val = (1<<5);
2cf7acf9
YR		 4142 /*
4143 * Note that 2.5G works only when used with 1G
25985edc 4144 * advertisement
2cf7acf9 4145 */
de6eae1f
YR		 4146 } else
4147 val = (1<<5);
4148 } else {
4149 val = 0;
4150 if (phy->speed_cap_mask &
4151 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4152 val |= (1<<7);
57963ed9 4153
25985edc 4154 /* Note that 2.5G works only when used with 1G advertisement */
de6eae1f
YR		 4155 if (phy->speed_cap_mask &
4156 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4157 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4158 val |= (1<<5);
4159 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4160 }
57963ed9 4161
de6eae1f
YR		 4162 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4163 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
57963ed9 4164
de6eae1f
YR		 4165 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4166 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4167 (phy->req_line_speed == SPEED_2500)) {
4168 u16 phy_ver;
4169 /* Allow 2.5G for A1 and above */
4170 bnx2x_cl45_read(bp, phy,
4171 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4172 &phy_ver);
4173 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4174 if (phy_ver > 0)
4175 tmp1 |= 1;
4176 else
4177 tmp1 &= 0xfffe;
4178 } else {
4179 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4180 tmp1 &= 0xfffe;
4181 }
57963ed9 4182
de6eae1f
YR		 4183 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4184 /* Add support for CL37 (passive mode) II */
57963ed9 4185
de6eae1f
YR		 4186 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4187 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4188 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4189 0x20 : 0x40)));
57963ed9 4190
de6eae1f
YR		 4191 /* Add support for CL37 (passive mode) III */
4192 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
57963ed9 4193
2cf7acf9
YR		 4194 /*
4195 * The SNR will improve about 2db by changing BW and FEE main
4196 * tap. Rest commands are executed after link is up
4197 * Change FFE main cursor to 5 in EDC register
4198 */
de6eae1f
YR		 4199 if (bnx2x_8073_is_snr_needed(bp, phy))
4200 bnx2x_cl45_write(bp, phy,
4201 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4202 0xFB0C);
57963ed9 4203
de6eae1f
YR		 4204 /* Enable FEC (Forware Error Correction) Request in the AN */
4205 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4206 tmp1 |= (1<<15);
4207 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
57963ed9 4208
de6eae1f 4209 bnx2x_ext_phy_set_pause(params, phy, vars);
57963ed9 4210
de6eae1f
YR		 4211 /* Restart autoneg */
4212 msleep(500);
4213 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4214 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4215 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4216 return 0;
b7737c9b 4217}
ea4e040a 4218
de6eae1f 4219static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 4220 struct link_params *params,
4221 struct link_vars *vars)
4222{
4223 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4224 u8 link_up = 0;
4225 u16 val1, val2;
4226 u16 link_status = 0;
4227 u16 an1000_status = 0;
a35da8db 4228
de6eae1f
YR		 4229 bnx2x_cl45_read(bp, phy,
4230 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
b7737c9b 4231
de6eae1f 4232 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
ea4e040a 4233
de6eae1f
YR		 4234 /* clear the interrupt LASI status register */
4235 bnx2x_cl45_read(bp, phy,
4236 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4237 bnx2x_cl45_read(bp, phy,
4238 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4239 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4240 /* Clear MSG-OUT */
4241 bnx2x_cl45_read(bp, phy,
4242 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4243
4244 /* Check the LASI */
4245 bnx2x_cl45_read(bp, phy,
4246 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4247
4248 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4249
4250 /* Check the link status */
4251 bnx2x_cl45_read(bp, phy,
4252 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4253 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4254
4255 bnx2x_cl45_read(bp, phy,
4256 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4257 bnx2x_cl45_read(bp, phy,
4258 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4259 link_up = ((val1 & 4) == 4);
4260 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4261
4262 if (link_up &&
4263 ((phy->req_line_speed != SPEED_10000))) {
4264 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4265 return 0;
62b29a5d 4266 }
de6eae1f
YR		 4267 bnx2x_cl45_read(bp, phy,
4268 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4269 bnx2x_cl45_read(bp, phy,
4270 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
62b29a5d 4271
de6eae1f
YR		 4272 /* Check the link status on 1.1.2 */
4273 bnx2x_cl45_read(bp, phy,
4274 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4275 bnx2x_cl45_read(bp, phy,
4276 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4277 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4278 "an_link_status=0x%x\n", val2, val1, an1000_status);
62b29a5d 4279
de6eae1f
YR		 4280 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4281 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
2cf7acf9
YR		 4282 /*
4283 * The SNR will improve about 2dbby changing the BW and FEE main
4284 * tap. The 1st write to change FFE main tap is set before
4285 * restart AN. Change PLL Bandwidth in EDC register
4286 */
62b29a5d 4287 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4288 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4289 0x26BC);
62b29a5d 4290
de6eae1f 4291 /* Change CDR Bandwidth in EDC register */
62b29a5d 4292 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4293 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4294 0x0333);
4295 }
4296 bnx2x_cl45_read(bp, phy,
4297 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4298 &link_status);
62b29a5d 4299
de6eae1f
YR		 4300 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4301 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4302 link_up = 1;
4303 vars->line_speed = SPEED_10000;
4304 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4305 params->port);
4306 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4307 link_up = 1;
4308 vars->line_speed = SPEED_2500;
4309 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4310 params->port);
4311 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4312 link_up = 1;
4313 vars->line_speed = SPEED_1000;
4314 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4315 params->port);
4316 } else {
4317 link_up = 0;
4318 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4319 params->port);
62b29a5d 4320 }
de6eae1f
YR		 4321
4322 if (link_up) {
74d7a119
YR		 4323 /* Swap polarity if required */
4324 if (params->lane_config &
4325 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4326 /* Configure the 8073 to swap P and N of the KR lines */
4327 bnx2x_cl45_read(bp, phy,
4328 MDIO_XS_DEVAD,
4329 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
2cf7acf9
YR		 4330 /*
4331 * Set bit 3 to invert Rx in 1G mode and clear this bit
4332 * when it`s in 10G mode.
4333 */
74d7a119
YR		 4334 if (vars->line_speed == SPEED_1000) {
4335 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4336 "the 8073\n");
4337 val1 |= (1<<3);
4338 } else
4339 val1 &= ~(1<<3);
4340
4341 bnx2x_cl45_write(bp, phy,
4342 MDIO_XS_DEVAD,
4343 MDIO_XS_REG_8073_RX_CTRL_PCIE,
4344 val1);
4345 }
de6eae1f
YR		 4346 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4347 bnx2x_8073_resolve_fc(phy, params, vars);
791f18c0 4348 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 4349 }
4350 return link_up;
b7737c9b
YR		 4351}
4352
de6eae1f
YR		 4353static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4354 struct link_params *params)
4355{
4356 struct bnx2x *bp = params->bp;
4357 u8 gpio_port;
f2e0899f
DK		 4358 if (CHIP_IS_E2(bp))
4359 gpio_port = BP_PATH(bp);
4360 else
4361 gpio_port = params->port;
de6eae1f
YR		 4362 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4363 gpio_port);
4364 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 4365 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4366 gpio_port);
de6eae1f
YR		 4367}
4368
4369/******************************************************************/
4370/* BCM8705 PHY SECTION */
4371/******************************************************************/
4372static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 4373 struct link_params *params,
4374 struct link_vars *vars)
4375{
4376 struct bnx2x *bp = params->bp;
de6eae1f 4377 DP(NETIF_MSG_LINK, "init 8705\n");
b7737c9b
YR		 4378 /* Restore normal power mode*/
4379 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 4380 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 4381 /* HW reset */
4382 bnx2x_ext_phy_hw_reset(bp, params->port);
4383 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 4384 bnx2x_wait_reset_complete(bp, phy, params);
b7737c9b 4385
de6eae1f
YR		 4386 bnx2x_cl45_write(bp, phy,
4387 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4388 bnx2x_cl45_write(bp, phy,
4389 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4390 bnx2x_cl45_write(bp, phy,
4391 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4392 bnx2x_cl45_write(bp, phy,
4393 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4394 /* BCM8705 doesn't have microcode, hence the 0 */
4395 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4396 return 0;
4397}
4d295db0 4398
de6eae1f
YR		 4399static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4400 struct link_params *params,
4401 struct link_vars *vars)
4402{
4403 u8 link_up = 0;
4404 u16 val1, rx_sd;
4405 struct bnx2x *bp = params->bp;
4406 DP(NETIF_MSG_LINK, "read status 8705\n");
4407 bnx2x_cl45_read(bp, phy,
4408 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4409 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 4410
de6eae1f
YR		 4411 bnx2x_cl45_read(bp, phy,
4412 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4413 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 4414
de6eae1f
YR		 4415 bnx2x_cl45_read(bp, phy,
4416 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
c2c8b03e 4417
de6eae1f
YR		 4418 bnx2x_cl45_read(bp, phy,
4419 MDIO_PMA_DEVAD, 0xc809, &val1);
4420 bnx2x_cl45_read(bp, phy,
4421 MDIO_PMA_DEVAD, 0xc809, &val1);
c2c8b03e 4422
de6eae1f
YR		 4423 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4424 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4425 if (link_up) {
4426 vars->line_speed = SPEED_10000;
4427 bnx2x_ext_phy_resolve_fc(phy, params, vars);
62b29a5d 4428 }
de6eae1f
YR		 4429 return link_up;
4430}
d90d96ba 4431
de6eae1f
YR		 4432/******************************************************************/
4433/* SFP+ module Section */
4434/******************************************************************/
a8db5b4c
YR		 4435static u8 bnx2x_get_gpio_port(struct link_params *params)
4436{
4437 u8 gpio_port;
4438 u32 swap_val, swap_override;
4439 struct bnx2x *bp = params->bp;
4440 if (CHIP_IS_E2(bp))
4441 gpio_port = BP_PATH(bp);
4442 else
4443 gpio_port = params->port;
4444 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4445 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4446 return gpio_port ^ (swap_val && swap_override);
4447}
4448static void bnx2x_sfp_set_transmitter(struct link_params *params,
de6eae1f 4449 struct bnx2x_phy *phy,
de6eae1f
YR		 4450 u8 tx_en)
4451{
4452 u16 val;
a8db5b4c
YR		 4453 u8 port = params->port;
4454 struct bnx2x *bp = params->bp;
4455 u32 tx_en_mode;
d90d96ba 4456
de6eae1f 4457 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
a8db5b4c
YR		 4458 tx_en_mode = REG_RD(bp, params->shmem_base +
4459 offsetof(struct shmem_region,
4460 dev_info.port_hw_config[port].sfp_ctrl)) &
4461 PORT_HW_CFG_TX_LASER_MASK;
4462 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
4463 "mode = %x\n", tx_en, port, tx_en_mode);
4464 switch (tx_en_mode) {
4465 case PORT_HW_CFG_TX_LASER_MDIO:
d90d96ba 4466
a8db5b4c
YR		 4467 bnx2x_cl45_read(bp, phy,
4468 MDIO_PMA_DEVAD,
4469 MDIO_PMA_REG_PHY_IDENTIFIER,
4470 &val);
b7737c9b 4471
a8db5b4c
YR		 4472 if (tx_en)
4473 val &= ~(1<<15);
4474 else
4475 val |= (1<<15);
4476
4477 bnx2x_cl45_write(bp, phy,
4478 MDIO_PMA_DEVAD,
4479 MDIO_PMA_REG_PHY_IDENTIFIER,
4480 val);
4481 break;
4482 case PORT_HW_CFG_TX_LASER_GPIO0:
4483 case PORT_HW_CFG_TX_LASER_GPIO1:
4484 case PORT_HW_CFG_TX_LASER_GPIO2:
4485 case PORT_HW_CFG_TX_LASER_GPIO3:
4486 {
4487 u16 gpio_pin;
4488 u8 gpio_port, gpio_mode;
4489 if (tx_en)
4490 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
4491 else
4492 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
4493
4494 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
4495 gpio_port = bnx2x_get_gpio_port(params);
4496 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
4497 break;
4498 }
4499 default:
4500 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
4501 break;
4502 }
b7737c9b
YR		 4503}
4504
de6eae1f
YR		 4505static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4506 struct link_params *params,
cd88ccee 4507 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b
YR		 4508{
4509 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4510 u16 val = 0;
4511 u16 i;
4512 if (byte_cnt > 16) {
4513 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4514 " is limited to 0xf\n");
4515 return -EINVAL;
4516 }
4517 /* Set the read command byte count */
62b29a5d 4518 bnx2x_cl45_write(bp, phy,
de6eae1f 4519 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
cd88ccee 4520 (byte_cnt | 0xa000));
ea4e040a 4521
de6eae1f
YR		 4522 /* Set the read command address */
4523 bnx2x_cl45_write(bp, phy,
4524 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
cd88ccee 4525 addr);
ea4e040a 4526
de6eae1f 4527 /* Activate read command */
62b29a5d 4528 bnx2x_cl45_write(bp, phy,
de6eae1f 4529 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
cd88ccee 4530 0x2c0f);
ea4e040a 4531
de6eae1f
YR		 4532 /* Wait up to 500us for command complete status */
4533 for (i = 0; i < 100; i++) {
4534 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4535 MDIO_PMA_DEVAD,
4536 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4537 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4538 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4539 break;
4540 udelay(5);
62b29a5d 4541 }
62b29a5d 4542
de6eae1f
YR		 4543 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4544 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4545 DP(NETIF_MSG_LINK,
4546 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4547 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4548 return -EINVAL;
62b29a5d 4549 }
e10bc84d 4550
de6eae1f
YR		 4551 /* Read the buffer */
4552 for (i = 0; i < byte_cnt; i++) {
62b29a5d 4553 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4554 MDIO_PMA_DEVAD,
4555 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f 4556 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
62b29a5d 4557 }
6bbca910 4558
de6eae1f
YR		 4559 for (i = 0; i < 100; i++) {
4560 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4561 MDIO_PMA_DEVAD,
4562 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4563 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4564 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 4565 return 0;
de6eae1f
YR		 4566 msleep(1);
4567 }
4568 return -EINVAL;
b7737c9b 4569}
4d295db0 4570
de6eae1f
YR		 4571static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4572 struct link_params *params,
cd88ccee 4573 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b 4574{
b7737c9b 4575 struct bnx2x *bp = params->bp;
de6eae1f 4576 u16 val, i;
ea4e040a 4577
de6eae1f
YR		 4578 if (byte_cnt > 16) {
4579 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4580 " is limited to 0xf\n");
4581 return -EINVAL;
4582 }
4d295db0 4583
de6eae1f
YR		 4584 /* Need to read from 1.8000 to clear it */
4585 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4586 MDIO_PMA_DEVAD,
4587 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4588 &val);
4d295db0 4589
de6eae1f 4590 /* Set the read command byte count */
62b29a5d 4591 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4592 MDIO_PMA_DEVAD,
4593 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4594 ((byte_cnt < 2) ? 2 : byte_cnt));
ea4e040a 4595
de6eae1f 4596 /* Set the read command address */
62b29a5d 4597 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4598 MDIO_PMA_DEVAD,
4599 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4600 addr);
de6eae1f 4601 /* Set the destination address */
62b29a5d 4602 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4603 MDIO_PMA_DEVAD,
4604 0x8004,
4605 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
62b29a5d 4606
de6eae1f 4607 /* Activate read command */
62b29a5d 4608 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4609 MDIO_PMA_DEVAD,
4610 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4611 0x8002);
2cf7acf9
YR		 4612 /*
4613 * Wait appropriate time for two-wire command to finish before
4614 * polling the status register
4615 */
de6eae1f 4616 msleep(1);
4d295db0 4617
de6eae1f
YR		 4618 /* Wait up to 500us for command complete status */
4619 for (i = 0; i < 100; i++) {
62b29a5d 4620 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4621 MDIO_PMA_DEVAD,
4622 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4623 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4624 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4625 break;
4626 udelay(5);
62b29a5d 4627 }
4d295db0 4628
de6eae1f
YR		 4629 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4630 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4631 DP(NETIF_MSG_LINK,
4632 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4633 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
65a001ba 4634 return -EFAULT;
de6eae1f 4635 }
62b29a5d 4636
de6eae1f
YR		 4637 /* Read the buffer */
4638 for (i = 0; i < byte_cnt; i++) {
4639 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4640 MDIO_PMA_DEVAD,
4641 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f
YR		 4642 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4643 }
4d295db0 4644
de6eae1f
YR		 4645 for (i = 0; i < 100; i++) {
4646 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4647 MDIO_PMA_DEVAD,
4648 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4649 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4650 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 4651 return 0;
de6eae1f 4652 msleep(1);
62b29a5d
YR		 4653 }
4654
de6eae1f 4655 return -EINVAL;
b7737c9b
YR		 4656}
4657
cd88ccee
YR		 4658u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4659 struct link_params *params, u16 addr,
4660 u8 byte_cnt, u8 *o_buf)
b7737c9b 4661{
de6eae1f
YR		 4662 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4663 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
cd88ccee 4664 byte_cnt, o_buf);
de6eae1f
YR		 4665 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4666 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
cd88ccee 4667 byte_cnt, o_buf);
de6eae1f 4668 return -EINVAL;
b7737c9b
YR		 4669}
4670
de6eae1f
YR		 4671static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4672 struct link_params *params,
cd88ccee 4673 u16 *edc_mode)
b7737c9b
YR		 4674{
4675 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4676 u8 val, check_limiting_mode = 0;
4677 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 4678
de6eae1f
YR		 4679 /* First check for copper cable */
4680 if (bnx2x_read_sfp_module_eeprom(phy,
4681 params,
4682 SFP_EEPROM_CON_TYPE_ADDR,
4683 1,
4684 &val) != 0) {
4685 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4686 return -EINVAL;
4687 }
a1e4be39 4688
de6eae1f
YR		 4689 switch (val) {
4690 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4691 {
4692 u8 copper_module_type;
62b29a5d 4693
2cf7acf9
YR		 4694 /*
4695 * Check if its active cable (includes SFP+ module)
4696 * of passive cable
4697 */
de6eae1f
YR		 4698 if (bnx2x_read_sfp_module_eeprom(phy,
4699 params,
4700 SFP_EEPROM_FC_TX_TECH_ADDR,
4701 1,
4702 &copper_module_type) !=
4703 0) {
4704 DP(NETIF_MSG_LINK,
4705 "Failed to read copper-cable-type"
4706 " from SFP+ EEPROM\n");
4707 return -EINVAL;
4708 }
4f60dab1 4709
de6eae1f
YR		 4710 if (copper_module_type &
4711 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4712 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4713 check_limiting_mode = 1;
4714 } else if (copper_module_type &
4715 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4716 DP(NETIF_MSG_LINK, "Passive Copper"
4717 " cable detected\n");
4718 *edc_mode =
4719 EDC_MODE_PASSIVE_DAC;
4720 } else {
4721 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4722 "type 0x%x !!!\n", copper_module_type);
4723 return -EINVAL;
4724 }
4725 break;
62b29a5d 4726 }
de6eae1f
YR		 4727 case SFP_EEPROM_CON_TYPE_VAL_LC:
4728 DP(NETIF_MSG_LINK, "Optic module detected\n");
4729 check_limiting_mode = 1;
4730 break;
4731 default:
4732 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4733 val);
4734 return -EINVAL;
62b29a5d 4735 }
2f904460 4736
de6eae1f
YR		 4737 if (check_limiting_mode) {
4738 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4739 if (bnx2x_read_sfp_module_eeprom(phy,
4740 params,
4741 SFP_EEPROM_OPTIONS_ADDR,
4742 SFP_EEPROM_OPTIONS_SIZE,
4743 options) != 0) {
4744 DP(NETIF_MSG_LINK, "Failed to read Option"
4745 " field from module EEPROM\n");
4746 return -EINVAL;
4747 }
4748 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4749 *edc_mode = EDC_MODE_LINEAR;
4750 else
4751 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 4752 }
de6eae1f 4753 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
62b29a5d 4754 return 0;
b7737c9b 4755}
2cf7acf9
YR		 4756/*
4757 * This function read the relevant field from the module (SFP+), and verify it
4758 * is compliant with this board
4759 */
de6eae1f
YR		 4760static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4761 struct link_params *params)
b7737c9b
YR		 4762{
4763 struct bnx2x *bp = params->bp;
a22f0788
YR		 4764 u32 val, cmd;
4765 u32 fw_resp, fw_cmd_param;
de6eae1f
YR		 4766 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4767 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
a22f0788 4768 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
de6eae1f
YR		 4769 val = REG_RD(bp, params->shmem_base +
4770 offsetof(struct shmem_region, dev_info.
4771 port_feature_config[params->port].config));
4772 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4773 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4774 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4775 return 0;
4776 }
ea4e040a 4777
a22f0788
YR		 4778 if (params->feature_config_flags &
4779 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4780 /* Use specific phy request */
4781 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4782 } else if (params->feature_config_flags &
4783 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4784 /* Use first phy request only in case of non-dual media*/
4785 if (DUAL_MEDIA(params)) {
4786 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4787 "verification\n");
4788 return -EINVAL;
4789 }
4790 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4791 } else {
4792 /* No support in OPT MDL detection */
de6eae1f 4793 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
a22f0788 4794 "verification\n");
de6eae1f
YR		 4795 return -EINVAL;
4796 }
523224a3 4797
a22f0788
YR		 4798 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4799 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
de6eae1f
YR		 4800 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4801 DP(NETIF_MSG_LINK, "Approved module\n");
4802 return 0;
4803 }
b7737c9b 4804
de6eae1f
YR		 4805 /* format the warning message */
4806 if (bnx2x_read_sfp_module_eeprom(phy,
4807 params,
cd88ccee
YR		 4808 SFP_EEPROM_VENDOR_NAME_ADDR,
4809 SFP_EEPROM_VENDOR_NAME_SIZE,
4810 (u8 *)vendor_name))
de6eae1f
YR		 4811 vendor_name[0] = '\0';
4812 else
4813 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4814 if (bnx2x_read_sfp_module_eeprom(phy,
4815 params,
cd88ccee
YR		 4816 SFP_EEPROM_PART_NO_ADDR,
4817 SFP_EEPROM_PART_NO_SIZE,
4818 (u8 *)vendor_pn))
de6eae1f
YR		 4819 vendor_pn[0] = '\0';
4820 else
4821 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4822
6d870c39
YR		 4823 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
4824 " Port %d from %s part number %s\n",
4825 params->port, vendor_name, vendor_pn);
a22f0788 4826 phy->flags |= FLAGS_SFP_NOT_APPROVED;
de6eae1f 4827 return -EINVAL;
b7737c9b 4828}
7aa0711f 4829
de6eae1f
YR		 4830static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4831 struct link_params *params)
7aa0711f 4832
4d295db0 4833{
de6eae1f 4834 u8 val;
4d295db0 4835 struct bnx2x *bp = params->bp;
de6eae1f 4836 u16 timeout;
2cf7acf9
YR		 4837 /*
4838 * Initialization time after hot-plug may take up to 300ms for
4839 * some phys type ( e.g. JDSU )
4840 */
4841
de6eae1f
YR		 4842 for (timeout = 0; timeout < 60; timeout++) {
4843 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4844 == 0) {
4845 DP(NETIF_MSG_LINK, "SFP+ module initialization "
4846 "took %d ms\n", timeout * 5);
4847 return 0;
4848 }
4849 msleep(5);
4850 }
4851 return -EINVAL;
4852}
4d295db0 4853
de6eae1f
YR		 4854static void bnx2x_8727_power_module(struct bnx2x *bp,
4855 struct bnx2x_phy *phy,
4856 u8 is_power_up) {
4857 /* Make sure GPIOs are not using for LED mode */
4858 u16 val;
4859 /*
2cf7acf9 4860 * In the GPIO register, bit 4 is use to determine if the GPIOs are
de6eae1f
YR		 4861 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4862 * output
4863 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4864 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4865 * where the 1st bit is the over-current(only input), and 2nd bit is
4866 * for power( only output )
2cf7acf9 4867 *
de6eae1f
YR		 4868 * In case of NOC feature is disabled and power is up, set GPIO control
4869 * as input to enable listening of over-current indication
4870 */
4871 if (phy->flags & FLAGS_NOC)
4872 return;
4873 if (!(phy->flags &
4874 FLAGS_NOC) && is_power_up)
4875 val = (1<<4);
4876 else
4877 /*
4878 * Set GPIO control to OUTPUT, and set the power bit
4879 * to according to the is_power_up
4880 */
4881 val = ((!(is_power_up)) << 1);
4d295db0 4882
de6eae1f
YR		 4883 bnx2x_cl45_write(bp, phy,
4884 MDIO_PMA_DEVAD,
4885 MDIO_PMA_REG_8727_GPIO_CTRL,
4886 val);
4887}
4d295db0 4888
de6eae1f
YR		 4889static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4890 struct bnx2x_phy *phy,
4891 u16 edc_mode)
4892{
4893 u16 cur_limiting_mode;
4d295db0 4894
de6eae1f 4895 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4896 MDIO_PMA_DEVAD,
4897 MDIO_PMA_REG_ROM_VER2,
4898 &cur_limiting_mode);
de6eae1f
YR		 4899 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4900 cur_limiting_mode);
4901
4902 if (edc_mode == EDC_MODE_LIMITING) {
cd88ccee 4903 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
e10bc84d 4904 bnx2x_cl45_write(bp, phy,
62b29a5d 4905 MDIO_PMA_DEVAD,
de6eae1f
YR		 4906 MDIO_PMA_REG_ROM_VER2,
4907 EDC_MODE_LIMITING);
4908 } else { /* LRM mode ( default )*/
4d295db0 4909
de6eae1f 4910 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4d295db0 4911
2cf7acf9
YR		 4912 /*
4913 * Changing to LRM mode takes quite few seconds. So do it only
4914 * if current mode is limiting (default is LRM)
4915 */
de6eae1f
YR		 4916 if (cur_limiting_mode != EDC_MODE_LIMITING)
4917 return 0;
4d295db0 4918
de6eae1f 4919 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4920 MDIO_PMA_DEVAD,
4921 MDIO_PMA_REG_LRM_MODE,
4922 0);
de6eae1f 4923 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4924 MDIO_PMA_DEVAD,
4925 MDIO_PMA_REG_ROM_VER2,
4926 0x128);
de6eae1f 4927 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4928 MDIO_PMA_DEVAD,
4929 MDIO_PMA_REG_MISC_CTRL0,
4930 0x4008);
de6eae1f 4931 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4932 MDIO_PMA_DEVAD,
4933 MDIO_PMA_REG_LRM_MODE,
4934 0xaaaa);
4d295db0 4935 }
de6eae1f 4936 return 0;
4d295db0
EG		 4937}
4938
de6eae1f
YR		 4939static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4940 struct bnx2x_phy *phy,
cd88ccee 4941 u16 edc_mode)
ea4e040a 4942{
de6eae1f
YR		 4943 u16 phy_identifier;
4944 u16 rom_ver2_val;
62b29a5d 4945 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4946 MDIO_PMA_DEVAD,
4947 MDIO_PMA_REG_PHY_IDENTIFIER,
4948 &phy_identifier);
ea4e040a 4949
de6eae1f 4950 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4951 MDIO_PMA_DEVAD,
4952 MDIO_PMA_REG_PHY_IDENTIFIER,
4953 (phy_identifier & ~(1<<9)));
ea4e040a 4954
62b29a5d 4955 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4956 MDIO_PMA_DEVAD,
4957 MDIO_PMA_REG_ROM_VER2,
4958 &rom_ver2_val);
de6eae1f
YR		 4959 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4960 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4961 MDIO_PMA_DEVAD,
4962 MDIO_PMA_REG_ROM_VER2,
4963 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4d295db0 4964
de6eae1f 4965 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4966 MDIO_PMA_DEVAD,
4967 MDIO_PMA_REG_PHY_IDENTIFIER,
4968 (phy_identifier | (1<<9)));
4d295db0 4969
de6eae1f 4970 return 0;
b7737c9b 4971}
ea4e040a 4972
a22f0788
YR		 4973static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4974 struct link_params *params,
4975 u32 action)
4976{
4977 struct bnx2x *bp = params->bp;
4978
4979 switch (action) {
4980 case DISABLE_TX:
a8db5b4c 4981 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788
YR		 4982 break;
4983 case ENABLE_TX:
4984 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
a8db5b4c 4985 bnx2x_sfp_set_transmitter(params, phy, 1);
a22f0788
YR		 4986 break;
4987 default:
4988 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
4989 action);
4990 return;
4991 }
4992}
4993
a8db5b4c
YR		 4994static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
4995 u8 gpio_mode)
4996{
4997 struct bnx2x *bp = params->bp;
4998
4999 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5000 offsetof(struct shmem_region,
5001 dev_info.port_hw_config[params->port].sfp_ctrl)) &
5002 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5003 switch (fault_led_gpio) {
5004 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5005 return;
5006 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5007 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5008 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5009 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5010 {
5011 u8 gpio_port = bnx2x_get_gpio_port(params);
5012 u16 gpio_pin = fault_led_gpio -
5013 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5014 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5015 "pin %x port %x mode %x\n",
5016 gpio_pin, gpio_port, gpio_mode);
5017 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5018 }
5019 break;
5020 default:
5021 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5022 fault_led_gpio);
5023 }
5024}
5025
de6eae1f
YR		 5026static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5027 struct link_params *params)
b7737c9b 5028{
b7737c9b 5029 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5030 u16 edc_mode;
5031 u8 rc = 0;
ea4e040a 5032
de6eae1f
YR		 5033 u32 val = REG_RD(bp, params->shmem_base +
5034 offsetof(struct shmem_region, dev_info.
5035 port_feature_config[params->port].config));
62b29a5d 5036
de6eae1f
YR		 5037 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5038 params->port);
5039
5040 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5041 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5042 return -EINVAL;
cd88ccee 5043 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
de6eae1f
YR		 5044 /* check SFP+ module compatibility */
5045 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5046 rc = -EINVAL;
5047 /* Turn on fault module-detected led */
a8db5b4c
YR		 5048 bnx2x_set_sfp_module_fault_led(params,
5049 MISC_REGISTERS_GPIO_HIGH);
5050
de6eae1f
YR		 5051 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
5052 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5053 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
5054 /* Shutdown SFP+ module */
5055 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5056 bnx2x_8727_power_module(bp, phy, 0);
5057 return rc;
5058 }
5059 } else {
5060 /* Turn off fault module-detected led */
a8db5b4c 5061 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
62b29a5d 5062 }
b7737c9b 5063
de6eae1f
YR		 5064 /* power up the SFP module */
5065 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
5066 bnx2x_8727_power_module(bp, phy, 1);
c18aa15d 5067
2cf7acf9
YR		 5068 /*
5069 * Check and set limiting mode / LRM mode on 8726. On 8727 it
5070 * is done automatically
5071 */
de6eae1f
YR		 5072 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
5073 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
5074 else
5075 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
5076 /*
5077 * Enable transmit for this module if the module is approved, or
5078 * if unapproved modules should also enable the Tx laser
5079 */
5080 if (rc == 0 ||
5081 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5082 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 5083 bnx2x_sfp_set_transmitter(params, phy, 1);
de6eae1f 5084 else
a8db5b4c 5085 bnx2x_sfp_set_transmitter(params, phy, 0);
b7737c9b 5086
de6eae1f
YR		 5087 return rc;
5088}
5089
5090void bnx2x_handle_module_detect_int(struct link_params *params)
b7737c9b
YR		 5091{
5092 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5093 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5094 u32 gpio_val;
5095 u8 port = params->port;
4d295db0 5096
de6eae1f 5097 /* Set valid module led off */
a8db5b4c 5098 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
4d295db0 5099
2cf7acf9 5100 /* Get current gpio val reflecting module plugged in / out*/
de6eae1f 5101 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
62b29a5d 5102
de6eae1f
YR		 5103 /* Call the handling function in case module is detected */
5104 if (gpio_val == 0) {
4d295db0 5105
de6eae1f
YR		 5106 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5107 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5108 port);
4d295db0 5109
de6eae1f
YR		 5110 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5111 bnx2x_sfp_module_detection(phy, params);
5112 else
5113 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5114 } else {
5115 u32 val = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 5116 offsetof(struct shmem_region, dev_info.
5117 port_feature_config[params->port].
5118 config));
4d295db0 5119
de6eae1f
YR		 5120 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5121 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5122 port);
2cf7acf9
YR		 5123 /*
5124 * Module was plugged out.
5125 * Disable transmit for this module
5126 */
de6eae1f
YR		 5127 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5128 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 5129 bnx2x_sfp_set_transmitter(params, phy, 0);
62b29a5d 5130 }
de6eae1f 5131}
62b29a5d 5132
de6eae1f
YR		 5133/******************************************************************/
5134/* common BCM8706/BCM8726 PHY SECTION */
5135/******************************************************************/
5136static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5137 struct link_params *params,
5138 struct link_vars *vars)
5139{
5140 u8 link_up = 0;
5141 u16 val1, val2, rx_sd, pcs_status;
5142 struct bnx2x *bp = params->bp;
5143 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5144 /* Clear RX Alarm*/
62b29a5d 5145 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5146 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5147 /* clear LASI indication*/
5148 bnx2x_cl45_read(bp, phy,
5149 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5150 bnx2x_cl45_read(bp, phy,
5151 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5152 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
62b29a5d
YR		 5153
5154 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5155 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5156 bnx2x_cl45_read(bp, phy,
5157 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5158 bnx2x_cl45_read(bp, phy,
5159 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5160 bnx2x_cl45_read(bp, phy,
5161 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
62b29a5d 5162
de6eae1f
YR		 5163 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5164 " link_status 0x%x\n", rx_sd, pcs_status, val2);
2cf7acf9
YR		 5165 /*
5166 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5167 * are set, or if the autoneg bit 1 is set
de6eae1f
YR		 5168 */
5169 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5170 if (link_up) {
5171 if (val2 & (1<<1))
5172 vars->line_speed = SPEED_1000;
5173 else
5174 vars->line_speed = SPEED_10000;
62b29a5d 5175 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0 5176 vars->duplex = DUPLEX_FULL;
de6eae1f 5177 }
62b29a5d 5178 return link_up;
b7737c9b 5179}
62b29a5d 5180
de6eae1f
YR		 5181/******************************************************************/
5182/* BCM8706 PHY SECTION */
5183/******************************************************************/
5184static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 5185 struct link_params *params,
5186 struct link_vars *vars)
5187{
a8db5b4c
YR		 5188 u32 tx_en_mode;
5189 u16 cnt, val, tmp1;
b7737c9b 5190 struct bnx2x *bp = params->bp;
de6eae1f 5191 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 5192 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 5193 /* HW reset */
5194 bnx2x_ext_phy_hw_reset(bp, params->port);
5195 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 5196 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 5197
de6eae1f
YR		 5198 /* Wait until fw is loaded */
5199 for (cnt = 0; cnt < 100; cnt++) {
5200 bnx2x_cl45_read(bp, phy,
5201 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5202 if (val)
5203 break;
5204 msleep(10);
5205 }
5206 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5207 if ((params->feature_config_flags &
5208 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5209 u8 i;
5210 u16 reg;
5211 for (i = 0; i < 4; i++) {
5212 reg = MDIO_XS_8706_REG_BANK_RX0 +
5213 i*(MDIO_XS_8706_REG_BANK_RX1 -
5214 MDIO_XS_8706_REG_BANK_RX0);
5215 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5216 /* Clear first 3 bits of the control */
5217 val &= ~0x7;
5218 /* Set control bits according to configuration */
5219 val |= (phy->rx_preemphasis[i] & 0x7);
5220 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5221 " reg 0x%x <-- val 0x%x\n", reg, val);
5222 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5223 }
5224 }
5225 /* Force speed */
5226 if (phy->req_line_speed == SPEED_10000) {
5227 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
ea4e040a 5228
de6eae1f
YR		 5229 bnx2x_cl45_write(bp, phy,
5230 MDIO_PMA_DEVAD,
5231 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5232 bnx2x_cl45_write(bp, phy,
5233 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5234 } else {
25985edc 5235 /* Force 1Gbps using autoneg with 1G advertisement */
6bbca910 5236
de6eae1f
YR		 5237 /* Allow CL37 through CL73 */
5238 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5239 bnx2x_cl45_write(bp, phy,
5240 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6bbca910 5241
25985edc 5242 /* Enable Full-Duplex advertisement on CL37 */
de6eae1f
YR		 5243 bnx2x_cl45_write(bp, phy,
5244 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5245 /* Enable CL37 AN */
5246 bnx2x_cl45_write(bp, phy,
5247 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5248 /* 1G support */
5249 bnx2x_cl45_write(bp, phy,
5250 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
6bbca910 5251
de6eae1f
YR		 5252 /* Enable clause 73 AN */
5253 bnx2x_cl45_write(bp, phy,
5254 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5255 bnx2x_cl45_write(bp, phy,
5256 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5257 0x0400);
5258 bnx2x_cl45_write(bp, phy,
5259 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5260 0x0004);
5261 }
5262 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
a8db5b4c
YR		 5263
5264 /*
5265 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5266 * power mode, if TX Laser is disabled
5267 */
5268
5269 tx_en_mode = REG_RD(bp, params->shmem_base +
5270 offsetof(struct shmem_region,
5271 dev_info.port_hw_config[params->port].sfp_ctrl))
5272 & PORT_HW_CFG_TX_LASER_MASK;
5273
5274 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5275 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5276 bnx2x_cl45_read(bp, phy,
5277 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
5278 tmp1 |= 0x1;
5279 bnx2x_cl45_write(bp, phy,
5280 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
5281 }
5282
de6eae1f
YR		 5283 return 0;
5284}
ea4e040a 5285
de6eae1f
YR		 5286static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5287 struct link_params *params,
5288 struct link_vars *vars)
5289{
5290 return bnx2x_8706_8726_read_status(phy, params, vars);
5291}
6bbca910 5292
de6eae1f
YR		 5293/******************************************************************/
5294/* BCM8726 PHY SECTION */
5295/******************************************************************/
5296static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5297 struct link_params *params)
5298{
5299 struct bnx2x *bp = params->bp;
5300 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5301 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5302}
62b29a5d 5303
de6eae1f
YR		 5304static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5305 struct link_params *params)
5306{
5307 struct bnx2x *bp = params->bp;
5308 /* Need to wait 100ms after reset */
5309 msleep(100);
62b29a5d 5310
de6eae1f
YR		 5311 /* Micro controller re-boot */
5312 bnx2x_cl45_write(bp, phy,
5313 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
62b29a5d 5314
de6eae1f
YR		 5315 /* Set soft reset */
5316 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5317 MDIO_PMA_DEVAD,
5318 MDIO_PMA_REG_GEN_CTRL,
5319 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
62b29a5d 5320
de6eae1f 5321 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5322 MDIO_PMA_DEVAD,
5323 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6bbca910 5324
de6eae1f 5325 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5326 MDIO_PMA_DEVAD,
5327 MDIO_PMA_REG_GEN_CTRL,
5328 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f
YR		 5329
5330 /* wait for 150ms for microcode load */
5331 msleep(150);
5332
5333 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5334 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5335 MDIO_PMA_DEVAD,
5336 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f
YR		 5337
5338 msleep(200);
5339 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
b7737c9b
YR		 5340}
5341
de6eae1f 5342static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 5343 struct link_params *params,
5344 struct link_vars *vars)
5345{
5346 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5347 u16 val1;
5348 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
62b29a5d
YR		 5349 if (link_up) {
5350 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5351 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5352 &val1);
5353 if (val1 & (1<<15)) {
5354 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5355 link_up = 0;
5356 vars->line_speed = 0;
5357 }
62b29a5d
YR		 5358 }
5359 return link_up;
b7737c9b
YR		 5360}
5361
de6eae1f
YR		 5362
5363static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5364 struct link_params *params,
5365 struct link_vars *vars)
b7737c9b
YR		 5366{
5367 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5368 u32 val;
5369 u32 swap_val, swap_override, aeu_gpio_mask, offset;
5370 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
62b29a5d 5371
de6eae1f 5372 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6d870c39 5373 bnx2x_wait_reset_complete(bp, phy, params);
62b29a5d 5374
de6eae1f 5375 bnx2x_8726_external_rom_boot(phy, params);
62b29a5d 5376
2cf7acf9
YR		 5377 /*
5378 * Need to call module detected on initialization since the module
5379 * detection triggered by actual module insertion might occur before
5380 * driver is loaded, and when driver is loaded, it reset all
5381 * registers, including the transmitter
5382 */
de6eae1f 5383 bnx2x_sfp_module_detection(phy, params);
62b29a5d 5384
de6eae1f
YR		 5385 if (phy->req_line_speed == SPEED_1000) {
5386 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5387 bnx2x_cl45_write(bp, phy,
5388 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5389 bnx2x_cl45_write(bp, phy,
5390 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5391 bnx2x_cl45_write(bp, phy,
5392 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5393 bnx2x_cl45_write(bp, phy,
5394 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5395 0x400);
5396 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5397 (phy->speed_cap_mask &
5398 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5399 ((phy->speed_cap_mask &
5400 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5401 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5402 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5403 /* Set Flow control */
5404 bnx2x_ext_phy_set_pause(params, phy, vars);
5405 bnx2x_cl45_write(bp, phy,
5406 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5407 bnx2x_cl45_write(bp, phy,
5408 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5409 bnx2x_cl45_write(bp, phy,
5410 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5411 bnx2x_cl45_write(bp, phy,
5412 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5413 bnx2x_cl45_write(bp, phy,
5414 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
2cf7acf9
YR		 5415 /*
5416 * Enable RX-ALARM control to receive interrupt for 1G speed
5417 * change
5418 */
de6eae1f
YR		 5419 bnx2x_cl45_write(bp, phy,
5420 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5421 bnx2x_cl45_write(bp, phy,
5422 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5423 0x400);
62b29a5d 5424
de6eae1f
YR		 5425 } else { /* Default 10G. Set only LASI control */
5426 bnx2x_cl45_write(bp, phy,
5427 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
7aa0711f
YR		 5428 }
5429
de6eae1f
YR		 5430 /* Set TX PreEmphasis if needed */
5431 if ((params->feature_config_flags &
5432 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5433 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5434 "TX_CTRL2 0x%x\n",
5435 phy->tx_preemphasis[0],
5436 phy->tx_preemphasis[1]);
5437 bnx2x_cl45_write(bp, phy,
5438 MDIO_PMA_DEVAD,
5439 MDIO_PMA_REG_8726_TX_CTRL1,
5440 phy->tx_preemphasis[0]);
c18aa15d 5441
de6eae1f
YR		 5442 bnx2x_cl45_write(bp, phy,
5443 MDIO_PMA_DEVAD,
5444 MDIO_PMA_REG_8726_TX_CTRL2,
5445 phy->tx_preemphasis[1]);
5446 }
ab6ad5a4 5447
de6eae1f
YR		 5448 /* Set GPIO3 to trigger SFP+ module insertion/removal */
5449 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
cd88ccee 5450 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
ea4e040a 5451
de6eae1f
YR		 5452 /* The GPIO should be swapped if the swap register is set and active */
5453 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5454 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
ea4e040a 5455
de6eae1f
YR		 5456 /* Select function upon port-swap configuration */
5457 if (params->port == 0) {
5458 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5459 aeu_gpio_mask = (swap_val && swap_override) ?
5460 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5461 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5462 } else {
5463 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5464 aeu_gpio_mask = (swap_val && swap_override) ?
5465 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5466 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
ea4e040a 5467 }
de6eae1f
YR		 5468 val = REG_RD(bp, offset);
5469 /* add GPIO3 to group */
5470 val |= aeu_gpio_mask;
5471 REG_WR(bp, offset, val);
5472 return 0;
ab6ad5a4 5473
ea4e040a
YR		 5474}
5475
de6eae1f
YR		 5476static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5477 struct link_params *params)
2f904460 5478{
de6eae1f
YR		 5479 struct bnx2x *bp = params->bp;
5480 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5481 /* Set serial boot control for external load */
5482 bnx2x_cl45_write(bp, phy,
5483 MDIO_PMA_DEVAD,
5484 MDIO_PMA_REG_GEN_CTRL, 0x0001);
5485}
5486
5487/******************************************************************/
5488/* BCM8727 PHY SECTION */
5489/******************************************************************/
7f02c4ad
YR		 5490
5491static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5492 struct link_params *params, u8 mode)
5493{
5494 struct bnx2x *bp = params->bp;
5495 u16 led_mode_bitmask = 0;
5496 u16 gpio_pins_bitmask = 0;
5497 u16 val;
5498 /* Only NOC flavor requires to set the LED specifically */
5499 if (!(phy->flags & FLAGS_NOC))
5500 return;
5501 switch (mode) {
5502 case LED_MODE_FRONT_PANEL_OFF:
5503 case LED_MODE_OFF:
5504 led_mode_bitmask = 0;
5505 gpio_pins_bitmask = 0x03;
5506 break;
5507 case LED_MODE_ON:
5508 led_mode_bitmask = 0;
5509 gpio_pins_bitmask = 0x02;
5510 break;
5511 case LED_MODE_OPER:
5512 led_mode_bitmask = 0x60;
5513 gpio_pins_bitmask = 0x11;
5514 break;
5515 }
5516 bnx2x_cl45_read(bp, phy,
5517 MDIO_PMA_DEVAD,
5518 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5519 &val);
5520 val &= 0xff8f;
5521 val |= led_mode_bitmask;
5522 bnx2x_cl45_write(bp, phy,
5523 MDIO_PMA_DEVAD,
5524 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5525 val);
5526 bnx2x_cl45_read(bp, phy,
5527 MDIO_PMA_DEVAD,
5528 MDIO_PMA_REG_8727_GPIO_CTRL,
5529 &val);
5530 val &= 0xffe0;
5531 val |= gpio_pins_bitmask;
5532 bnx2x_cl45_write(bp, phy,
5533 MDIO_PMA_DEVAD,
5534 MDIO_PMA_REG_8727_GPIO_CTRL,
5535 val);
5536}
de6eae1f
YR		 5537static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5538 struct link_params *params) {
5539 u32 swap_val, swap_override;
5540 u8 port;
2cf7acf9 5541 /*
de6eae1f
YR		 5542 * The PHY reset is controlled by GPIO 1. Fake the port number
5543 * to cancel the swap done in set_gpio()
2f904460 5544 */
de6eae1f
YR		 5545 struct bnx2x *bp = params->bp;
5546 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5547 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5548 port = (swap_val && swap_override) ^ 1;
5549 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 5550 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2f904460 5551}
e10bc84d 5552
de6eae1f
YR		 5553static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
5554 struct link_params *params,
5555 struct link_vars *vars)
ea4e040a 5556{
a8db5b4c
YR		 5557 u32 tx_en_mode;
5558 u16 tmp1, val, mod_abs, tmp2;
de6eae1f
YR		 5559 u16 rx_alarm_ctrl_val;
5560 u16 lasi_ctrl_val;
ea4e040a 5561 struct bnx2x *bp = params->bp;
de6eae1f 5562 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
ea4e040a 5563
6d870c39 5564 bnx2x_wait_reset_complete(bp, phy, params);
de6eae1f
YR		 5565 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5566 lasi_ctrl_val = 0x0004;
ea4e040a 5567
de6eae1f
YR		 5568 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5569 /* enable LASI */
5570 bnx2x_cl45_write(bp, phy,
5571 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5572 rx_alarm_ctrl_val);
ea4e040a 5573
de6eae1f
YR		 5574 bnx2x_cl45_write(bp, phy,
5575 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
ea4e040a 5576
2cf7acf9
YR		 5577 /*
5578 * Initially configure MOD_ABS to interrupt when module is
5579 * presence( bit 8)
5580 */
de6eae1f
YR		 5581 bnx2x_cl45_read(bp, phy,
5582 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
2cf7acf9
YR		 5583 /*
5584 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
5585 * When the EDC is off it locks onto a reference clock and avoids
5586 * becoming 'lost'
5587 */
7f02c4ad
YR		 5588 mod_abs &= ~(1<<8);
5589 if (!(phy->flags & FLAGS_NOC))
5590 mod_abs &= ~(1<<9);
de6eae1f
YR		 5591 bnx2x_cl45_write(bp, phy,
5592 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5593
ea4e040a 5594
de6eae1f
YR		 5595 /* Make MOD_ABS give interrupt on change */
5596 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5597 &val);
5598 val |= (1<<12);
7f02c4ad
YR		 5599 if (phy->flags & FLAGS_NOC)
5600 val |= (3<<5);
b7737c9b 5601
2cf7acf9 5602 /*
7f02c4ad
YR		 5603 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5604 * status which reflect SFP+ module over-current
5605 */
5606 if (!(phy->flags & FLAGS_NOC))
5607 val &= 0xff8f; /* Reset bits 4-6 */
de6eae1f
YR		 5608 bnx2x_cl45_write(bp, phy,
5609 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
ea4e040a 5610
de6eae1f
YR		 5611 bnx2x_8727_power_module(bp, phy, 1);
5612
5613 bnx2x_cl45_read(bp, phy,
5614 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5615
5616 bnx2x_cl45_read(bp, phy,
5617 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5618
5619 /* Set option 1G speed */
5620 if (phy->req_line_speed == SPEED_1000) {
5621 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5622 bnx2x_cl45_write(bp, phy,
5623 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5624 bnx2x_cl45_write(bp, phy,
5625 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5626 bnx2x_cl45_read(bp, phy,
5627 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5628 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
2cf7acf9 5629 /*
a22f0788
YR		 5630 * Power down the XAUI until link is up in case of dual-media
5631 * and 1G
5632 */
5633 if (DUAL_MEDIA(params)) {
5634 bnx2x_cl45_read(bp, phy,
5635 MDIO_PMA_DEVAD,
5636 MDIO_PMA_REG_8727_PCS_GP, &val);
5637 val |= (3<<10);
5638 bnx2x_cl45_write(bp, phy,
5639 MDIO_PMA_DEVAD,
5640 MDIO_PMA_REG_8727_PCS_GP, val);
5641 }
de6eae1f
YR		 5642 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5643 ((phy->speed_cap_mask &
5644 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5645 ((phy->speed_cap_mask &
5646 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5647 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5648
5649 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5650 bnx2x_cl45_write(bp, phy,
5651 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5652 bnx2x_cl45_write(bp, phy,
5653 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5654 } else {
2cf7acf9 5655 /*
de6eae1f
YR		 5656 * Since the 8727 has only single reset pin, need to set the 10G
5657 * registers although it is default
5658 */
5659 bnx2x_cl45_write(bp, phy,
5660 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5661 0x0020);
5662 bnx2x_cl45_write(bp, phy,
5663 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5664 bnx2x_cl45_write(bp, phy,
5665 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5666 bnx2x_cl45_write(bp, phy,
5667 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5668 0x0008);
ea4e040a 5669 }
ea4e040a 5670
2cf7acf9
YR		 5671 /*
5672 * Set 2-wire transfer rate of SFP+ module EEPROM
de6eae1f
YR		 5673 * to 100Khz since some DACs(direct attached cables) do
5674 * not work at 400Khz.
5675 */
5676 bnx2x_cl45_write(bp, phy,
5677 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5678 0xa001);
b7737c9b 5679
de6eae1f
YR		 5680 /* Set TX PreEmphasis if needed */
5681 if ((params->feature_config_flags &
5682 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5683 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5684 phy->tx_preemphasis[0],
5685 phy->tx_preemphasis[1]);
5686 bnx2x_cl45_write(bp, phy,
5687 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5688 phy->tx_preemphasis[0]);
ea4e040a 5689
de6eae1f
YR		 5690 bnx2x_cl45_write(bp, phy,
5691 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5692 phy->tx_preemphasis[1]);
5693 }
ea4e040a 5694
a8db5b4c
YR		 5695 /*
5696 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5697 * power mode, if TX Laser is disabled
5698 */
5699 tx_en_mode = REG_RD(bp, params->shmem_base +
5700 offsetof(struct shmem_region,
5701 dev_info.port_hw_config[params->port].sfp_ctrl))
5702 & PORT_HW_CFG_TX_LASER_MASK;
5703
5704 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5705
5706 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5707 bnx2x_cl45_read(bp, phy,
5708 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
5709 tmp2 |= 0x1000;
5710 tmp2 &= 0xFFEF;
5711 bnx2x_cl45_write(bp, phy,
5712 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
5713 }
5714
de6eae1f 5715 return 0;
ea4e040a
YR		 5716}
5717
de6eae1f
YR		 5718static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5719 struct link_params *params)
ea4e040a 5720{
ea4e040a 5721 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5722 u16 mod_abs, rx_alarm_status;
5723 u32 val = REG_RD(bp, params->shmem_base +
5724 offsetof(struct shmem_region, dev_info.
5725 port_feature_config[params->port].
5726 config));
5727 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 5728 MDIO_PMA_DEVAD,
5729 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
de6eae1f 5730 if (mod_abs & (1<<8)) {
ea4e040a 5731
de6eae1f
YR		 5732 /* Module is absent */
5733 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5734 "show module is absent\n");
ea4e040a 5735
2cf7acf9
YR		 5736 /*
5737 * 1. Set mod_abs to detect next module
5738 * presence event
5739 * 2. Set EDC off by setting OPTXLOS signal input to low
5740 * (bit 9).
5741 * When the EDC is off it locks onto a reference clock and
5742 * avoids becoming 'lost'.
5743 */
7f02c4ad
YR		 5744 mod_abs &= ~(1<<8);
5745 if (!(phy->flags & FLAGS_NOC))
5746 mod_abs &= ~(1<<9);
de6eae1f 5747 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5748 MDIO_PMA_DEVAD,
5749 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5750
2cf7acf9
YR		 5751 /*
5752 * Clear RX alarm since it stays up as long as
5753 * the mod_abs wasn't changed
5754 */
de6eae1f 5755 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 5756 MDIO_PMA_DEVAD,
5757 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 5758
de6eae1f
YR		 5759 } else {
5760 /* Module is present */
5761 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5762 "show module is present\n");
2cf7acf9
YR		 5763 /*
5764 * First disable transmitter, and if the module is ok, the
5765 * module_detection will enable it
5766 * 1. Set mod_abs to detect next module absent event ( bit 8)
5767 * 2. Restore the default polarity of the OPRXLOS signal and
5768 * this signal will then correctly indicate the presence or
5769 * absence of the Rx signal. (bit 9)
5770 */
7f02c4ad
YR		 5771 mod_abs |= (1<<8);
5772 if (!(phy->flags & FLAGS_NOC))
5773 mod_abs |= (1<<9);
e10bc84d 5774 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 5775 MDIO_PMA_DEVAD,
5776 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5777
2cf7acf9
YR		 5778 /*
5779 * Clear RX alarm since it stays up as long as the mod_abs
5780 * wasn't changed. This is need to be done before calling the
5781 * module detection, otherwise it will clear* the link update
5782 * alarm
5783 */
de6eae1f
YR		 5784 bnx2x_cl45_read(bp, phy,
5785 MDIO_PMA_DEVAD,
5786 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 5787
ea4e040a 5788
de6eae1f
YR		 5789 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5790 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 5791 bnx2x_sfp_set_transmitter(params, phy, 0);
de6eae1f
YR		 5792
5793 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5794 bnx2x_sfp_module_detection(phy, params);
5795 else
5796 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
ea4e040a 5797 }
de6eae1f
YR		 5798
5799 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
2cf7acf9
YR		 5800 rx_alarm_status);
5801 /* No need to check link status in case of module plugged in/out */
ea4e040a
YR		 5802}
5803
de6eae1f
YR		 5804static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5805 struct link_params *params,
5806 struct link_vars *vars)
5807
ea4e040a
YR		 5808{
5809 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5810 u8 link_up = 0;
5811 u16 link_status = 0;
a22f0788
YR		 5812 u16 rx_alarm_status, lasi_ctrl, val1;
5813
5814 /* If PHY is not initialized, do not check link status */
5815 bnx2x_cl45_read(bp, phy,
5816 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5817 &lasi_ctrl);
5818 if (!lasi_ctrl)
5819 return 0;
5820
de6eae1f
YR		 5821 /* Check the LASI */
5822 bnx2x_cl45_read(bp, phy,
5823 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5824 &rx_alarm_status);
5825 vars->line_speed = 0;
5826 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
5827
5828 bnx2x_cl45_read(bp, phy,
5829 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5830
5831 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5832
5833 /* Clear MSG-OUT */
5834 bnx2x_cl45_read(bp, phy,
5835 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5836
2cf7acf9 5837 /*
de6eae1f
YR		 5838 * If a module is present and there is need to check
5839 * for over current
5840 */
5841 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5842 /* Check over-current using 8727 GPIO0 input*/
5843 bnx2x_cl45_read(bp, phy,
5844 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5845 &val1);
5846
5847 if ((val1 & (1<<8)) == 0) {
5848 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5849 " on port %d\n", params->port);
5850 netdev_err(bp->dev, "Error: Power fault on Port %d has"
5851 " been detected and the power to "
5852 "that SFP+ module has been removed"
5853 " to prevent failure of the card."
5854 " Please remove the SFP+ module and"
5855 " restart the system to clear this"
5856 " error.\n",
2cf7acf9
YR		 5857 params->port);
5858 /* Disable all RX_ALARMs except for mod_abs */
de6eae1f
YR		 5859 bnx2x_cl45_write(bp, phy,
5860 MDIO_PMA_DEVAD,
5861 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5862
5863 bnx2x_cl45_read(bp, phy,
5864 MDIO_PMA_DEVAD,
5865 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5866 /* Wait for module_absent_event */
5867 val1 |= (1<<8);
5868 bnx2x_cl45_write(bp, phy,
5869 MDIO_PMA_DEVAD,
5870 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5871 /* Clear RX alarm */
5872 bnx2x_cl45_read(bp, phy,
5873 MDIO_PMA_DEVAD,
5874 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5875 return 0;
5876 }
5877 } /* Over current check */
5878
5879 /* When module absent bit is set, check module */
5880 if (rx_alarm_status & (1<<5)) {
5881 bnx2x_8727_handle_mod_abs(phy, params);
5882 /* Enable all mod_abs and link detection bits */
5883 bnx2x_cl45_write(bp, phy,
5884 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5885 ((1<<5) | (1<<2)));
5886 }
a22f0788
YR		 5887 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5888 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
de6eae1f
YR		 5889 /* If transmitter is disabled, ignore false link up indication */
5890 bnx2x_cl45_read(bp, phy,
5891 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5892 if (val1 & (1<<15)) {
5893 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5894 return 0;
5895 }
5896
5897 bnx2x_cl45_read(bp, phy,
5898 MDIO_PMA_DEVAD,
5899 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5900
2cf7acf9
YR		 5901 /*
5902 * Bits 0..2 --> speed detected,
5903 * Bits 13..15--> link is down
5904 */
de6eae1f
YR		 5905 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5906 link_up = 1;
5907 vars->line_speed = SPEED_10000;
2cf7acf9
YR		 5908 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
5909 params->port);
de6eae1f
YR		 5910 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5911 link_up = 1;
5912 vars->line_speed = SPEED_1000;
5913 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5914 params->port);
5915 } else {
5916 link_up = 0;
5917 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5918 params->port);
5919 }
791f18c0 5920 if (link_up) {
de6eae1f 5921 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0
YR		 5922 vars->duplex = DUPLEX_FULL;
5923 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
5924 }
a22f0788
YR		 5925
5926 if ((DUAL_MEDIA(params)) &&
5927 (phy->req_line_speed == SPEED_1000)) {
5928 bnx2x_cl45_read(bp, phy,
5929 MDIO_PMA_DEVAD,
5930 MDIO_PMA_REG_8727_PCS_GP, &val1);
2cf7acf9 5931 /*
a22f0788
YR		 5932 * In case of dual-media board and 1G, power up the XAUI side,
5933 * otherwise power it down. For 10G it is done automatically
5934 */
5935 if (link_up)
5936 val1 &= ~(3<<10);
5937 else
5938 val1 |= (3<<10);
5939 bnx2x_cl45_write(bp, phy,
5940 MDIO_PMA_DEVAD,
5941 MDIO_PMA_REG_8727_PCS_GP, val1);
5942 }
de6eae1f 5943 return link_up;
b7737c9b 5944}
ea4e040a 5945
de6eae1f
YR		 5946static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5947 struct link_params *params)
b7737c9b
YR		 5948{
5949 struct bnx2x *bp = params->bp;
de6eae1f 5950 /* Disable Transmitter */
a8db5b4c 5951 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788
YR		 5952 /* Clear LASI */
5953 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5954
ea4e040a 5955}
c18aa15d 5956
de6eae1f
YR		 5957/******************************************************************/
5958/* BCM8481/BCM84823/BCM84833 PHY SECTION */
5959/******************************************************************/
5960static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5961 struct link_params *params)
ea4e040a 5962{
c87bca1e 5963 u16 val, fw_ver1, fw_ver2, cnt, adj;
de6eae1f 5964 struct bnx2x *bp = params->bp;
ea4e040a 5965
c87bca1e
YR		 5966 adj = 0;
5967 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
5968 adj = -1;
5969
de6eae1f
YR		 5970 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
5971 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
c87bca1e
YR		 5972 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0014);
5973 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
5974 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, 0x0000);
5975 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, 0x0300);
5976 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x0009);
ea4e040a 5977
de6eae1f 5978 for (cnt = 0; cnt < 100; cnt++) {
c87bca1e 5979 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
de6eae1f
YR		 5980 if (val & 1)
5981 break;
5982 udelay(5);
5983 }
5984 if (cnt == 100) {
5985 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
5986 bnx2x_save_spirom_version(bp, params->port, 0,
5987 phy->ver_addr);
5988 return;
5989 }
ea4e040a 5990
ea4e040a 5991
de6eae1f 5992 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
c87bca1e
YR		 5993 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0000);
5994 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
5995 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x000A);
de6eae1f 5996 for (cnt = 0; cnt < 100; cnt++) {
c87bca1e 5997 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
de6eae1f
YR		 5998 if (val & 1)
5999 break;
6000 udelay(5);
6001 }
6002 if (cnt == 100) {
6003 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
6004 bnx2x_save_spirom_version(bp, params->port, 0,
6005 phy->ver_addr);
6006 return;
ea4e040a
YR		 6007 }
6008
de6eae1f 6009 /* lower 16 bits of the register SPI_FW_STATUS */
c87bca1e 6010 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, &fw_ver1);
de6eae1f 6011 /* upper 16 bits of register SPI_FW_STATUS */
c87bca1e 6012 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, &fw_ver2);
ea4e040a 6013
de6eae1f
YR		 6014 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
6015 phy->ver_addr);
6016}
ea4e040a 6017
de6eae1f
YR		 6018static void bnx2x_848xx_set_led(struct bnx2x *bp,
6019 struct bnx2x_phy *phy)
ea4e040a 6020{
c87bca1e
YR		 6021 u16 val, adj;
6022
6023 adj = 0;
6024 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6025 adj = -1;
7846e471 6026
de6eae1f
YR		 6027 /* PHYC_CTL_LED_CTL */
6028 bnx2x_cl45_read(bp, phy,
6029 MDIO_PMA_DEVAD,
c87bca1e 6030 MDIO_PMA_REG_8481_LINK_SIGNAL + adj, &val);
de6eae1f
YR		 6031 val &= 0xFE00;
6032 val |= 0x0092;
345b5d52 6033
de6eae1f
YR		 6034 bnx2x_cl45_write(bp, phy,
6035 MDIO_PMA_DEVAD,
c87bca1e 6036 MDIO_PMA_REG_8481_LINK_SIGNAL + adj, val);
ea4e040a 6037
de6eae1f
YR		 6038 bnx2x_cl45_write(bp, phy,
6039 MDIO_PMA_DEVAD,
c87bca1e 6040 MDIO_PMA_REG_8481_LED1_MASK + adj,
de6eae1f 6041 0x80);
ea4e040a 6042
de6eae1f
YR		 6043 bnx2x_cl45_write(bp, phy,
6044 MDIO_PMA_DEVAD,
c87bca1e 6045 MDIO_PMA_REG_8481_LED2_MASK + adj,
de6eae1f 6046 0x18);
ea4e040a 6047
f25b3c8b 6048 /* Select activity source by Tx and Rx, as suggested by PHY AE */
de6eae1f
YR		 6049 bnx2x_cl45_write(bp, phy,
6050 MDIO_PMA_DEVAD,
c87bca1e 6051 MDIO_PMA_REG_8481_LED3_MASK + adj,
f25b3c8b
YR		 6052 0x0006);
6053
6054 /* Select the closest activity blink rate to that in 10/100/1000 */
6055 bnx2x_cl45_write(bp, phy,
6056 MDIO_PMA_DEVAD,
c87bca1e 6057 MDIO_PMA_REG_8481_LED3_BLINK + adj,
f25b3c8b
YR		 6058 0);
6059
6060 bnx2x_cl45_read(bp, phy,
6061 MDIO_PMA_DEVAD,
c87bca1e 6062 MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, &val);
f25b3c8b
YR		 6063 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
6064
6065 bnx2x_cl45_write(bp, phy,
6066 MDIO_PMA_DEVAD,
c87bca1e 6067 MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, val);
ea4e040a 6068
de6eae1f
YR		 6069 /* 'Interrupt Mask' */
6070 bnx2x_cl45_write(bp, phy,
6071 MDIO_AN_DEVAD,
6072 0xFFFB, 0xFFFD);
ea4e040a
YR		 6073}
6074
de6eae1f 6075static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
a22f0788
YR		 6076 struct link_params *params,
6077 struct link_vars *vars)
ea4e040a 6078{
c18aa15d 6079 struct bnx2x *bp = params->bp;
de6eae1f 6080 u16 autoneg_val, an_1000_val, an_10_100_val;
2cf7acf9
YR		 6081 /*
6082 * This phy uses the NIG latch mechanism since link indication
6083 * arrives through its LED4 and not via its LASI signal, so we
6084 * get steady signal instead of clear on read
6085 */
de6eae1f
YR		 6086 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6087 1 << NIG_LATCH_BC_ENABLE_MI_INT);
ea4e040a 6088
de6eae1f
YR		 6089 bnx2x_cl45_write(bp, phy,
6090 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
ea4e040a 6091
de6eae1f 6092 bnx2x_848xx_set_led(bp, phy);
ea4e040a 6093
de6eae1f
YR		 6094 /* set 1000 speed advertisement */
6095 bnx2x_cl45_read(bp, phy,
6096 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6097 &an_1000_val);
57963ed9 6098
de6eae1f
YR		 6099 bnx2x_ext_phy_set_pause(params, phy, vars);
6100 bnx2x_cl45_read(bp, phy,
6101 MDIO_AN_DEVAD,
6102 MDIO_AN_REG_8481_LEGACY_AN_ADV,
6103 &an_10_100_val);
6104 bnx2x_cl45_read(bp, phy,
6105 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6106 &autoneg_val);
6107 /* Disable forced speed */
6108 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6109 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
ea4e040a 6110
de6eae1f
YR		 6111 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6112 (phy->speed_cap_mask &
6113 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6114 (phy->req_line_speed == SPEED_1000)) {
6115 an_1000_val |= (1<<8);
6116 autoneg_val |= (1<<9 | 1<<12);
6117 if (phy->req_duplex == DUPLEX_FULL)
6118 an_1000_val |= (1<<9);
6119 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6120 } else
6121 an_1000_val &= ~((1<<8) | (1<<9));
ea4e040a 6122
de6eae1f
YR		 6123 bnx2x_cl45_write(bp, phy,
6124 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6125 an_1000_val);
ea4e040a 6126
de6eae1f
YR		 6127 /* set 10 speed advertisement */
6128 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6129 (phy->speed_cap_mask &
6130 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6131 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6132 an_10_100_val |= (1<<7);
6133 /* Enable autoneg and restart autoneg for legacy speeds */
6134 autoneg_val |= (1<<9 | 1<<12);
b7737c9b 6135
de6eae1f
YR		 6136 if (phy->req_duplex == DUPLEX_FULL)
6137 an_10_100_val |= (1<<8);
6138 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6139 }
6140 /* set 10 speed advertisement */
6141 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6142 (phy->speed_cap_mask &
6143 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6144 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6145 an_10_100_val |= (1<<5);
6146 autoneg_val |= (1<<9 | 1<<12);
6147 if (phy->req_duplex == DUPLEX_FULL)
6148 an_10_100_val |= (1<<6);
6149 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6150 }
b7737c9b 6151
de6eae1f
YR		 6152 /* Only 10/100 are allowed to work in FORCE mode */
6153 if (phy->req_line_speed == SPEED_100) {
6154 autoneg_val |= (1<<13);
6155 /* Enabled AUTO-MDIX when autoneg is disabled */
6156 bnx2x_cl45_write(bp, phy,
6157 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6158 (1<<15 | 1<<9 | 7<<0));
6159 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6160 }
6161 if (phy->req_line_speed == SPEED_10) {
6162 /* Enabled AUTO-MDIX when autoneg is disabled */
6163 bnx2x_cl45_write(bp, phy,
6164 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6165 (1<<15 | 1<<9 | 7<<0));
6166 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6167 }
b7737c9b 6168
de6eae1f
YR		 6169 bnx2x_cl45_write(bp, phy,
6170 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6171 an_10_100_val);
b7737c9b 6172
de6eae1f
YR		 6173 if (phy->req_duplex == DUPLEX_FULL)
6174 autoneg_val |= (1<<8);
b7737c9b 6175
de6eae1f
YR		 6176 bnx2x_cl45_write(bp, phy,
6177 MDIO_AN_DEVAD,
6178 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
b7737c9b 6179
de6eae1f
YR		 6180 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6181 (phy->speed_cap_mask &
6182 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6183 (phy->req_line_speed == SPEED_10000)) {
6184 DP(NETIF_MSG_LINK, "Advertising 10G\n");
6185 /* Restart autoneg for 10G*/
6186
6187 bnx2x_cl45_write(bp, phy,
6188 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6189 0x3200);
6190 } else if (phy->req_line_speed != SPEED_10 &&
6191 phy->req_line_speed != SPEED_100) {
6192 bnx2x_cl45_write(bp, phy,
6193 MDIO_AN_DEVAD,
6194 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6195 1);
b7737c9b 6196 }
de6eae1f
YR		 6197 /* Save spirom version */
6198 bnx2x_save_848xx_spirom_version(phy, params);
6199
6200 return 0;
b7737c9b
YR		 6201}
6202
de6eae1f
YR		 6203static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6204 struct link_params *params,
6205 struct link_vars *vars)
ea4e040a
YR		 6206{
6207 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6208 /* Restore normal power mode*/
6209 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 6210 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 6211
de6eae1f
YR		 6212 /* HW reset */
6213 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 6214 bnx2x_wait_reset_complete(bp, phy, params);
ab6ad5a4 6215
de6eae1f
YR		 6216 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6217 return bnx2x_848xx_cmn_config_init(phy, params, vars);
6218}
ea4e040a 6219
de6eae1f
YR		 6220static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6221 struct link_params *params,
6222 struct link_vars *vars)
6223{
6224 struct bnx2x *bp = params->bp;
6a71bbe0 6225 u8 port, initialize = 1;
c87bca1e 6226 u16 val, adj;
de6eae1f 6227 u16 temp;
1bef68e3 6228 u32 actual_phy_selection, cms_enable;
a22f0788 6229 u8 rc = 0;
7f02c4ad
YR		 6230
6231 /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
c87bca1e
YR		 6232 adj = 0;
6233 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6234 adj = 3;
7f02c4ad 6235
de6eae1f 6236 msleep(1);
6a71bbe0
YR		 6237 if (CHIP_IS_E2(bp))
6238 port = BP_PATH(bp);
6239 else
6240 port = params->port;
de6eae1f
YR		 6241 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6242 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7f02c4ad 6243 port);
6d870c39 6244 bnx2x_wait_reset_complete(bp, phy, params);
9bffeac1
YR		 6245 /* Wait for GPHY to come out of reset */
6246 msleep(50);
2cf7acf9
YR		 6247 /*
6248 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
6249 */
de6eae1f
YR		 6250 temp = vars->line_speed;
6251 vars->line_speed = SPEED_10000;
a22f0788
YR		 6252 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6253 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
de6eae1f 6254 vars->line_speed = temp;
a22f0788
YR		 6255
6256 /* Set dual-media configuration according to configuration */
6257
6258 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
c87bca1e 6259 MDIO_CTL_REG_84823_MEDIA + adj, &val);
a22f0788
YR		 6260 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6261 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6262 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6263 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6264 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6265 val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6266 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6267
6268 actual_phy_selection = bnx2x_phy_selection(params);
6269
6270 switch (actual_phy_selection) {
6271 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
25985edc 6272 /* Do nothing. Essentially this is like the priority copper */
a22f0788
YR		 6273 break;
6274 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6275 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6276 break;
6277 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6278 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6279 break;
6280 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6281 /* Do nothing here. The first PHY won't be initialized at all */
6282 break;
6283 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6284 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6285 initialize = 0;
6286 break;
6287 }
6288 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6289 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6290
6291 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
c87bca1e 6292 MDIO_CTL_REG_84823_MEDIA + adj, val);
a22f0788
YR		 6293 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6294 params->multi_phy_config, val);
6295
6296 if (initialize)
6297 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6298 else
6299 bnx2x_save_848xx_spirom_version(phy, params);
1bef68e3
YR		 6300 cms_enable = REG_RD(bp, params->shmem_base +
6301 offsetof(struct shmem_region,
6302 dev_info.port_hw_config[params->port].default_cfg)) &
6303 PORT_HW_CFG_ENABLE_CMS_MASK;
6304
6305 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6306 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
6307 if (cms_enable)
6308 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
6309 else
6310 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
6311 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6312 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
6313
6314
a22f0788 6315 return rc;
de6eae1f 6316}
ea4e040a 6317
de6eae1f 6318static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
cd88ccee
YR		 6319 struct link_params *params,
6320 struct link_vars *vars)
de6eae1f
YR		 6321{
6322 struct bnx2x *bp = params->bp;
c87bca1e 6323 u16 val, val1, val2, adj;
de6eae1f 6324 u8 link_up = 0;
ea4e040a 6325
c87bca1e
YR		 6326 /* Reg offset adjustment for 84833 */
6327 adj = 0;
6328 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6329 adj = -1;
6330
de6eae1f
YR		 6331 /* Check 10G-BaseT link status */
6332 /* Check PMD signal ok */
6333 bnx2x_cl45_read(bp, phy,
6334 MDIO_AN_DEVAD, 0xFFFA, &val1);
6335 bnx2x_cl45_read(bp, phy,
c87bca1e 6336 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL + adj,
de6eae1f
YR		 6337 &val2);
6338 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
ea4e040a 6339
de6eae1f
YR		 6340 /* Check link 10G */
6341 if (val2 & (1<<11)) {
ea4e040a 6342 vars->line_speed = SPEED_10000;
791f18c0 6343 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 6344 link_up = 1;
6345 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6346 } else { /* Check Legacy speed link */
6347 u16 legacy_status, legacy_speed;
ea4e040a 6348
de6eae1f
YR		 6349 /* Enable expansion register 0x42 (Operation mode status) */
6350 bnx2x_cl45_write(bp, phy,
6351 MDIO_AN_DEVAD,
6352 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
ea4e040a 6353
de6eae1f
YR		 6354 /* Get legacy speed operation status */
6355 bnx2x_cl45_read(bp, phy,
6356 MDIO_AN_DEVAD,
6357 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6358 &legacy_status);
ea4e040a 6359
de6eae1f
YR		 6360 DP(NETIF_MSG_LINK, "Legacy speed status"
6361 " = 0x%x\n", legacy_status);
6362 link_up = ((legacy_status & (1<<11)) == (1<<11));
6363 if (link_up) {
6364 legacy_speed = (legacy_status & (3<<9));
6365 if (legacy_speed == (0<<9))
6366 vars->line_speed = SPEED_10;
6367 else if (legacy_speed == (1<<9))
6368 vars->line_speed = SPEED_100;
6369 else if (legacy_speed == (2<<9))
6370 vars->line_speed = SPEED_1000;
6371 else /* Should not happen */
6372 vars->line_speed = 0;
ea4e040a 6373
de6eae1f
YR		 6374 if (legacy_status & (1<<8))
6375 vars->duplex = DUPLEX_FULL;
6376 else
6377 vars->duplex = DUPLEX_HALF;
ea4e040a 6378
de6eae1f
YR		 6379 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6380 " is_duplex_full= %d\n", vars->line_speed,
6381 (vars->duplex == DUPLEX_FULL));
6382 /* Check legacy speed AN resolution */
6383 bnx2x_cl45_read(bp, phy,
6384 MDIO_AN_DEVAD,
6385 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6386 &val);
6387 if (val & (1<<5))
6388 vars->link_status |=
6389 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6390 bnx2x_cl45_read(bp, phy,
6391 MDIO_AN_DEVAD,
6392 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6393 &val);
6394 if ((val & (1<<0)) == 0)
6395 vars->link_status |=
6396 LINK_STATUS_PARALLEL_DETECTION_USED;
ea4e040a 6397 }
ea4e040a 6398 }
de6eae1f
YR		 6399 if (link_up) {
6400 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6401 vars->line_speed);
6402 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6403 }
589abe3a 6404
de6eae1f 6405 return link_up;
b7737c9b
YR		 6406}
6407
de6eae1f 6408static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
b7737c9b 6409{
de6eae1f
YR		 6410 u8 status = 0;
6411 u32 spirom_ver;
6412 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6413 status = bnx2x_format_ver(spirom_ver, str, len);
6414 return status;
b7737c9b 6415}
de6eae1f
YR		 6416
6417static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6418 struct link_params *params)
b7737c9b 6419{
de6eae1f 6420 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6421 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
de6eae1f 6422 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6423 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
b7737c9b 6424}
de6eae1f 6425
b7737c9b
YR		 6426static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6427 struct link_params *params)
6428{
6429 bnx2x_cl45_write(params->bp, phy,
6430 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6431 bnx2x_cl45_write(params->bp, phy,
6432 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6433}
6434
6435static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6436 struct link_params *params)
6437{
6438 struct bnx2x *bp = params->bp;
6a71bbe0
YR		 6439 u8 port;
6440 if (CHIP_IS_E2(bp))
6441 port = BP_PATH(bp);
6442 else
6443 port = params->port;
b7737c9b 6444 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
cd88ccee
YR		 6445 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6446 port);
b7737c9b
YR		 6447}
6448
7f02c4ad
YR		 6449static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6450 struct link_params *params, u8 mode)
6451{
6452 struct bnx2x *bp = params->bp;
6453 u16 val;
6454
6455 switch (mode) {
6456 case LED_MODE_OFF:
6457
6458 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6459
6460 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6461 SHARED_HW_CFG_LED_EXTPHY1) {
6462
6463 /* Set LED masks */
6464 bnx2x_cl45_write(bp, phy,
6465 MDIO_PMA_DEVAD,
6466 MDIO_PMA_REG_8481_LED1_MASK,
6467 0x0);
6468
6469 bnx2x_cl45_write(bp, phy,
6470 MDIO_PMA_DEVAD,
6471 MDIO_PMA_REG_8481_LED2_MASK,
6472 0x0);
6473
6474 bnx2x_cl45_write(bp, phy,
6475 MDIO_PMA_DEVAD,
6476 MDIO_PMA_REG_8481_LED3_MASK,
6477 0x0);
6478
6479 bnx2x_cl45_write(bp, phy,
6480 MDIO_PMA_DEVAD,
6481 MDIO_PMA_REG_8481_LED5_MASK,
6482 0x0);
6483
6484 } else {
6485 bnx2x_cl45_write(bp, phy,
6486 MDIO_PMA_DEVAD,
6487 MDIO_PMA_REG_8481_LED1_MASK,
6488 0x0);
6489 }
6490 break;
6491 case LED_MODE_FRONT_PANEL_OFF:
6492
6493 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6494 params->port);
6495
6496 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6497 SHARED_HW_CFG_LED_EXTPHY1) {
6498
6499 /* Set LED masks */
6500 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6501 MDIO_PMA_DEVAD,
6502 MDIO_PMA_REG_8481_LED1_MASK,
6503 0x0);
7f02c4ad
YR		 6504
6505 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6506 MDIO_PMA_DEVAD,
6507 MDIO_PMA_REG_8481_LED2_MASK,
6508 0x0);
7f02c4ad
YR		 6509
6510 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6511 MDIO_PMA_DEVAD,
6512 MDIO_PMA_REG_8481_LED3_MASK,
6513 0x0);
7f02c4ad
YR		 6514
6515 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6516 MDIO_PMA_DEVAD,
6517 MDIO_PMA_REG_8481_LED5_MASK,
6518 0x20);
7f02c4ad
YR		 6519
6520 } else {
6521 bnx2x_cl45_write(bp, phy,
6522 MDIO_PMA_DEVAD,
6523 MDIO_PMA_REG_8481_LED1_MASK,
6524 0x0);
6525 }
6526 break;
6527 case LED_MODE_ON:
6528
6529 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6530
6531 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6532 SHARED_HW_CFG_LED_EXTPHY1) {
6533 /* Set control reg */
6534 bnx2x_cl45_read(bp, phy,
6535 MDIO_PMA_DEVAD,
6536 MDIO_PMA_REG_8481_LINK_SIGNAL,
6537 &val);
6538 val &= 0x8000;
6539 val |= 0x2492;
6540
6541 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6542 MDIO_PMA_DEVAD,
6543 MDIO_PMA_REG_8481_LINK_SIGNAL,
6544 val);
7f02c4ad
YR		 6545
6546 /* Set LED masks */
6547 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6548 MDIO_PMA_DEVAD,
6549 MDIO_PMA_REG_8481_LED1_MASK,
6550 0x0);
7f02c4ad
YR		 6551
6552 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6553 MDIO_PMA_DEVAD,
6554 MDIO_PMA_REG_8481_LED2_MASK,
6555 0x20);
7f02c4ad
YR		 6556
6557 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6558 MDIO_PMA_DEVAD,
6559 MDIO_PMA_REG_8481_LED3_MASK,
6560 0x20);
7f02c4ad
YR		 6561
6562 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6563 MDIO_PMA_DEVAD,
6564 MDIO_PMA_REG_8481_LED5_MASK,
6565 0x0);
7f02c4ad
YR		 6566 } else {
6567 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6568 MDIO_PMA_DEVAD,
6569 MDIO_PMA_REG_8481_LED1_MASK,
6570 0x20);
7f02c4ad
YR		 6571 }
6572 break;
6573
6574 case LED_MODE_OPER:
6575
6576 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6577
6578 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6579 SHARED_HW_CFG_LED_EXTPHY1) {
6580
6581 /* Set control reg */
6582 bnx2x_cl45_read(bp, phy,
6583 MDIO_PMA_DEVAD,
6584 MDIO_PMA_REG_8481_LINK_SIGNAL,
6585 &val);
6586
6587 if (!((val &
cd88ccee
YR		 6588 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6589 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
2cf7acf9 6590 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
7f02c4ad
YR		 6591 bnx2x_cl45_write(bp, phy,
6592 MDIO_PMA_DEVAD,
6593 MDIO_PMA_REG_8481_LINK_SIGNAL,
6594 0xa492);
6595 }
6596
6597 /* Set LED masks */
6598 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6599 MDIO_PMA_DEVAD,
6600 MDIO_PMA_REG_8481_LED1_MASK,
6601 0x10);
7f02c4ad
YR		 6602
6603 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6604 MDIO_PMA_DEVAD,
6605 MDIO_PMA_REG_8481_LED2_MASK,
6606 0x80);
7f02c4ad
YR		 6607
6608 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6609 MDIO_PMA_DEVAD,
6610 MDIO_PMA_REG_8481_LED3_MASK,
6611 0x98);
7f02c4ad
YR		 6612
6613 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6614 MDIO_PMA_DEVAD,
6615 MDIO_PMA_REG_8481_LED5_MASK,
6616 0x40);
7f02c4ad
YR		 6617
6618 } else {
6619 bnx2x_cl45_write(bp, phy,
6620 MDIO_PMA_DEVAD,
6621 MDIO_PMA_REG_8481_LED1_MASK,
6622 0x80);
53eda06d
YR		 6623
6624 /* Tell LED3 to blink on source */
6625 bnx2x_cl45_read(bp, phy,
6626 MDIO_PMA_DEVAD,
6627 MDIO_PMA_REG_8481_LINK_SIGNAL,
6628 &val);
6629 val &= ~(7<<6);
6630 val |= (1<<6); /* A83B[8:6]= 1 */
6631 bnx2x_cl45_write(bp, phy,
6632 MDIO_PMA_DEVAD,
6633 MDIO_PMA_REG_8481_LINK_SIGNAL,
6634 val);
7f02c4ad
YR		 6635 }
6636 break;
6637 }
6638}
de6eae1f
YR		 6639/******************************************************************/
6640/* SFX7101 PHY SECTION */
6641/******************************************************************/
6642static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6643 struct link_params *params)
b7737c9b
YR		 6644{
6645 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6646 /* SFX7101_XGXS_TEST1 */
6647 bnx2x_cl45_write(bp, phy,
6648 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
589abe3a
EG		 6649}
6650
de6eae1f
YR		 6651static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6652 struct link_params *params,
6653 struct link_vars *vars)
ea4e040a 6654{
de6eae1f 6655 u16 fw_ver1, fw_ver2, val;
ea4e040a 6656 struct bnx2x *bp = params->bp;
de6eae1f 6657 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
ea4e040a 6658
de6eae1f
YR		 6659 /* Restore normal power mode*/
6660 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 6661 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 6662 /* HW reset */
6663 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 6664 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 6665
de6eae1f
YR		 6666 bnx2x_cl45_write(bp, phy,
6667 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6668 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6669 bnx2x_cl45_write(bp, phy,
6670 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
ea4e040a 6671
de6eae1f
YR		 6672 bnx2x_ext_phy_set_pause(params, phy, vars);
6673 /* Restart autoneg */
6674 bnx2x_cl45_read(bp, phy,
6675 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6676 val |= 0x200;
6677 bnx2x_cl45_write(bp, phy,
6678 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
ea4e040a 6679
de6eae1f
YR		 6680 /* Save spirom version */
6681 bnx2x_cl45_read(bp, phy,
6682 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
ea4e040a 6683
de6eae1f
YR		 6684 bnx2x_cl45_read(bp, phy,
6685 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6686 bnx2x_save_spirom_version(bp, params->port,
6687 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6688 return 0;
6689}
ea4e040a 6690
de6eae1f
YR		 6691static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6692 struct link_params *params,
6693 struct link_vars *vars)
57963ed9
YR		 6694{
6695 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6696 u8 link_up;
6697 u16 val1, val2;
6698 bnx2x_cl45_read(bp, phy,
6699 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6700 bnx2x_cl45_read(bp, phy,
6701 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6702 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6703 val2, val1);
6704 bnx2x_cl45_read(bp, phy,
6705 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6706 bnx2x_cl45_read(bp, phy,
6707 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6708 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6709 val2, val1);
6710 link_up = ((val1 & 4) == 4);
2cf7acf9 6711 /* if link is up print the AN outcome of the SFX7101 PHY */
de6eae1f
YR		 6712 if (link_up) {
6713 bnx2x_cl45_read(bp, phy,
6714 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6715 &val2);
6716 vars->line_speed = SPEED_10000;
791f18c0 6717 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 6718 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6719 val2, (val2 & (1<<14)));
6720 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6721 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6722 }
6723 return link_up;
6724}
6c55c3cd 6725
6c55c3cd 6726
de6eae1f
YR		 6727static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6728{
6729 if (*len < 5)
6730 return -EINVAL;
6731 str[0] = (spirom_ver & 0xFF);
6732 str[1] = (spirom_ver & 0xFF00) >> 8;
6733 str[2] = (spirom_ver & 0xFF0000) >> 16;
6734 str[3] = (spirom_ver & 0xFF000000) >> 24;
6735 str[4] = '\0';
6736 *len -= 5;
57963ed9
YR		 6737 return 0;
6738}
6739
de6eae1f 6740void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
57963ed9 6741{
de6eae1f 6742 u16 val, cnt;
7aa0711f 6743
de6eae1f 6744 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 6745 MDIO_PMA_DEVAD,
6746 MDIO_PMA_REG_7101_RESET, &val);
57963ed9 6747
de6eae1f
YR		 6748 for (cnt = 0; cnt < 10; cnt++) {
6749 msleep(50);
6750 /* Writes a self-clearing reset */
6751 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6752 MDIO_PMA_DEVAD,
6753 MDIO_PMA_REG_7101_RESET,
6754 (val | (1<<15)));
de6eae1f
YR		 6755 /* Wait for clear */
6756 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 6757 MDIO_PMA_DEVAD,
6758 MDIO_PMA_REG_7101_RESET, &val);
0c786f02 6759
de6eae1f
YR		 6760 if ((val & (1<<15)) == 0)
6761 break;
57963ed9 6762 }
57963ed9 6763}
ea4e040a 6764
de6eae1f
YR		 6765static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6766 struct link_params *params) {
6767 /* Low power mode is controlled by GPIO 2 */
6768 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
cd88ccee 6769 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f
YR		 6770 /* The PHY reset is controlled by GPIO 1 */
6771 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6772 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f 6773}
ea4e040a 6774
7f02c4ad
YR		 6775static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6776 struct link_params *params, u8 mode)
6777{
6778 u16 val = 0;
6779 struct bnx2x *bp = params->bp;
6780 switch (mode) {
6781 case LED_MODE_FRONT_PANEL_OFF:
6782 case LED_MODE_OFF:
6783 val = 2;
6784 break;
6785 case LED_MODE_ON:
6786 val = 1;
6787 break;
6788 case LED_MODE_OPER:
6789 val = 0;
6790 break;
6791 }
6792 bnx2x_cl45_write(bp, phy,
6793 MDIO_PMA_DEVAD,
6794 MDIO_PMA_REG_7107_LINK_LED_CNTL,
6795 val);
6796}
6797
de6eae1f
YR		 6798/******************************************************************/
6799/* STATIC PHY DECLARATION */
6800/******************************************************************/
ea4e040a 6801
de6eae1f
YR		 6802static struct bnx2x_phy phy_null = {
6803 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6804 .addr = 0,
6805 .flags = FLAGS_INIT_XGXS_FIRST,
6806 .def_md_devad = 0,
6807 .reserved = 0,
6808 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6809 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6810 .mdio_ctrl = 0,
6811 .supported = 0,
6812 .media_type = ETH_PHY_NOT_PRESENT,
6813 .ver_addr = 0,
cd88ccee
YR		 6814 .req_flow_ctrl = 0,
6815 .req_line_speed = 0,
6816 .speed_cap_mask = 0,
de6eae1f
YR		 6817 .req_duplex = 0,
6818 .rsrv = 0,
6819 .config_init = (config_init_t)NULL,
6820 .read_status = (read_status_t)NULL,
6821 .link_reset = (link_reset_t)NULL,
6822 .config_loopback = (config_loopback_t)NULL,
6823 .format_fw_ver = (format_fw_ver_t)NULL,
6824 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6825 .set_link_led = (set_link_led_t)NULL,
6826 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 6827};
ea4e040a 6828
de6eae1f
YR		 6829static struct bnx2x_phy phy_serdes = {
6830 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6831 .addr = 0xff,
6832 .flags = 0,
6833 .def_md_devad = 0,
6834 .reserved = 0,
6835 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6836 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6837 .mdio_ctrl = 0,
6838 .supported = (SUPPORTED_10baseT_Half |
6839 SUPPORTED_10baseT_Full |
6840 SUPPORTED_100baseT_Half |
6841 SUPPORTED_100baseT_Full |
6842 SUPPORTED_1000baseT_Full |
6843 SUPPORTED_2500baseX_Full |
6844 SUPPORTED_TP |
6845 SUPPORTED_Autoneg |
6846 SUPPORTED_Pause |
6847 SUPPORTED_Asym_Pause),
6848 .media_type = ETH_PHY_UNSPECIFIED,
6849 .ver_addr = 0,
6850 .req_flow_ctrl = 0,
cd88ccee
YR		 6851 .req_line_speed = 0,
6852 .speed_cap_mask = 0,
de6eae1f
YR		 6853 .req_duplex = 0,
6854 .rsrv = 0,
6855 .config_init = (config_init_t)bnx2x_init_serdes,
6856 .read_status = (read_status_t)bnx2x_link_settings_status,
6857 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6858 .config_loopback = (config_loopback_t)NULL,
6859 .format_fw_ver = (format_fw_ver_t)NULL,
6860 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6861 .set_link_led = (set_link_led_t)NULL,
6862 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 6863};
b7737c9b
YR		 6864
6865static struct bnx2x_phy phy_xgxs = {
6866 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6867 .addr = 0xff,
6868 .flags = 0,
6869 .def_md_devad = 0,
6870 .reserved = 0,
6871 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6872 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6873 .mdio_ctrl = 0,
6874 .supported = (SUPPORTED_10baseT_Half |
6875 SUPPORTED_10baseT_Full |
6876 SUPPORTED_100baseT_Half |
6877 SUPPORTED_100baseT_Full |
6878 SUPPORTED_1000baseT_Full |
6879 SUPPORTED_2500baseX_Full |
6880 SUPPORTED_10000baseT_Full |
6881 SUPPORTED_FIBRE |
6882 SUPPORTED_Autoneg |
6883 SUPPORTED_Pause |
6884 SUPPORTED_Asym_Pause),
6885 .media_type = ETH_PHY_UNSPECIFIED,
6886 .ver_addr = 0,
6887 .req_flow_ctrl = 0,
cd88ccee
YR		 6888 .req_line_speed = 0,
6889 .speed_cap_mask = 0,
b7737c9b
YR		 6890 .req_duplex = 0,
6891 .rsrv = 0,
6892 .config_init = (config_init_t)bnx2x_init_xgxs,
6893 .read_status = (read_status_t)bnx2x_link_settings_status,
6894 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6895 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6896 .format_fw_ver = (format_fw_ver_t)NULL,
6897 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6898 .set_link_led = (set_link_led_t)NULL,
6899 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6900};
6901
6902static struct bnx2x_phy phy_7101 = {
6903 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6904 .addr = 0xff,
6905 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6906 .def_md_devad = 0,
6907 .reserved = 0,
6908 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6909 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6910 .mdio_ctrl = 0,
6911 .supported = (SUPPORTED_10000baseT_Full |
6912 SUPPORTED_TP |
6913 SUPPORTED_Autoneg |
6914 SUPPORTED_Pause |
6915 SUPPORTED_Asym_Pause),
6916 .media_type = ETH_PHY_BASE_T,
6917 .ver_addr = 0,
6918 .req_flow_ctrl = 0,
cd88ccee
YR		 6919 .req_line_speed = 0,
6920 .speed_cap_mask = 0,
b7737c9b
YR		 6921 .req_duplex = 0,
6922 .rsrv = 0,
6923 .config_init = (config_init_t)bnx2x_7101_config_init,
6924 .read_status = (read_status_t)bnx2x_7101_read_status,
6925 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6926 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6927 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
6928 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
7f02c4ad 6929 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
a22f0788 6930 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6931};
6932static struct bnx2x_phy phy_8073 = {
6933 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6934 .addr = 0xff,
6935 .flags = FLAGS_HW_LOCK_REQUIRED,
6936 .def_md_devad = 0,
6937 .reserved = 0,
6938 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6939 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6940 .mdio_ctrl = 0,
6941 .supported = (SUPPORTED_10000baseT_Full |
6942 SUPPORTED_2500baseX_Full |
6943 SUPPORTED_1000baseT_Full |
6944 SUPPORTED_FIBRE |
6945 SUPPORTED_Autoneg |
6946 SUPPORTED_Pause |
6947 SUPPORTED_Asym_Pause),
6948 .media_type = ETH_PHY_UNSPECIFIED,
6949 .ver_addr = 0,
cd88ccee
YR		 6950 .req_flow_ctrl = 0,
6951 .req_line_speed = 0,
6952 .speed_cap_mask = 0,
b7737c9b
YR		 6953 .req_duplex = 0,
6954 .rsrv = 0,
62b29a5d 6955 .config_init = (config_init_t)bnx2x_8073_config_init,
b7737c9b
YR		 6956 .read_status = (read_status_t)bnx2x_8073_read_status,
6957 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
6958 .config_loopback = (config_loopback_t)NULL,
6959 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6960 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6961 .set_link_led = (set_link_led_t)NULL,
6962 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6963};
6964static struct bnx2x_phy phy_8705 = {
6965 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
6966 .addr = 0xff,
6967 .flags = FLAGS_INIT_XGXS_FIRST,
6968 .def_md_devad = 0,
6969 .reserved = 0,
6970 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6971 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6972 .mdio_ctrl = 0,
6973 .supported = (SUPPORTED_10000baseT_Full |
6974 SUPPORTED_FIBRE |
6975 SUPPORTED_Pause |
6976 SUPPORTED_Asym_Pause),
6977 .media_type = ETH_PHY_XFP_FIBER,
6978 .ver_addr = 0,
6979 .req_flow_ctrl = 0,
6980 .req_line_speed = 0,
6981 .speed_cap_mask = 0,
6982 .req_duplex = 0,
6983 .rsrv = 0,
6984 .config_init = (config_init_t)bnx2x_8705_config_init,
6985 .read_status = (read_status_t)bnx2x_8705_read_status,
6986 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6987 .config_loopback = (config_loopback_t)NULL,
6988 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
6989 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6990 .set_link_led = (set_link_led_t)NULL,
6991 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6992};
6993static struct bnx2x_phy phy_8706 = {
6994 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
6995 .addr = 0xff,
6996 .flags = FLAGS_INIT_XGXS_FIRST,
6997 .def_md_devad = 0,
6998 .reserved = 0,
6999 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7000 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7001 .mdio_ctrl = 0,
7002 .supported = (SUPPORTED_10000baseT_Full |
7003 SUPPORTED_1000baseT_Full |
7004 SUPPORTED_FIBRE |
7005 SUPPORTED_Pause |
7006 SUPPORTED_Asym_Pause),
7007 .media_type = ETH_PHY_SFP_FIBER,
7008 .ver_addr = 0,
7009 .req_flow_ctrl = 0,
7010 .req_line_speed = 0,
7011 .speed_cap_mask = 0,
7012 .req_duplex = 0,
7013 .rsrv = 0,
7014 .config_init = (config_init_t)bnx2x_8706_config_init,
7015 .read_status = (read_status_t)bnx2x_8706_read_status,
7016 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
7017 .config_loopback = (config_loopback_t)NULL,
7018 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7019 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 7020 .set_link_led = (set_link_led_t)NULL,
7021 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 7022};
7023
7024static struct bnx2x_phy phy_8726 = {
7025 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
7026 .addr = 0xff,
7027 .flags = (FLAGS_HW_LOCK_REQUIRED |
7028 FLAGS_INIT_XGXS_FIRST),
7029 .def_md_devad = 0,
7030 .reserved = 0,
7031 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7032 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7033 .mdio_ctrl = 0,
7034 .supported = (SUPPORTED_10000baseT_Full |
7035 SUPPORTED_1000baseT_Full |
7036 SUPPORTED_Autoneg |
7037 SUPPORTED_FIBRE |
7038 SUPPORTED_Pause |
7039 SUPPORTED_Asym_Pause),
7040 .media_type = ETH_PHY_SFP_FIBER,
7041 .ver_addr = 0,
7042 .req_flow_ctrl = 0,
7043 .req_line_speed = 0,
7044 .speed_cap_mask = 0,
7045 .req_duplex = 0,
7046 .rsrv = 0,
7047 .config_init = (config_init_t)bnx2x_8726_config_init,
7048 .read_status = (read_status_t)bnx2x_8726_read_status,
7049 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
7050 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
7051 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7052 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 7053 .set_link_led = (set_link_led_t)NULL,
7054 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 7055};
7056
7057static struct bnx2x_phy phy_8727 = {
7058 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
7059 .addr = 0xff,
7060 .flags = FLAGS_FAN_FAILURE_DET_REQ,
7061 .def_md_devad = 0,
7062 .reserved = 0,
7063 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7064 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7065 .mdio_ctrl = 0,
7066 .supported = (SUPPORTED_10000baseT_Full |
7067 SUPPORTED_1000baseT_Full |
b7737c9b
YR		 7068 SUPPORTED_FIBRE |
7069 SUPPORTED_Pause |
7070 SUPPORTED_Asym_Pause),
7071 .media_type = ETH_PHY_SFP_FIBER,
7072 .ver_addr = 0,
7073 .req_flow_ctrl = 0,
7074 .req_line_speed = 0,
7075 .speed_cap_mask = 0,
7076 .req_duplex = 0,
7077 .rsrv = 0,
7078 .config_init = (config_init_t)bnx2x_8727_config_init,
7079 .read_status = (read_status_t)bnx2x_8727_read_status,
7080 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
7081 .config_loopback = (config_loopback_t)NULL,
7082 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7083 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
7f02c4ad 7084 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
a22f0788 7085 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
b7737c9b
YR		 7086};
7087static struct bnx2x_phy phy_8481 = {
7088 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
7089 .addr = 0xff,
a22f0788
YR		 7090 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7091 FLAGS_REARM_LATCH_SIGNAL,
b7737c9b
YR		 7092 .def_md_devad = 0,
7093 .reserved = 0,
7094 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7095 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7096 .mdio_ctrl = 0,
7097 .supported = (SUPPORTED_10baseT_Half |
7098 SUPPORTED_10baseT_Full |
7099 SUPPORTED_100baseT_Half |
7100 SUPPORTED_100baseT_Full |
7101 SUPPORTED_1000baseT_Full |
7102 SUPPORTED_10000baseT_Full |
7103 SUPPORTED_TP |
7104 SUPPORTED_Autoneg |
7105 SUPPORTED_Pause |
7106 SUPPORTED_Asym_Pause),
7107 .media_type = ETH_PHY_BASE_T,
7108 .ver_addr = 0,
7109 .req_flow_ctrl = 0,
7110 .req_line_speed = 0,
7111 .speed_cap_mask = 0,
7112 .req_duplex = 0,
7113 .rsrv = 0,
7114 .config_init = (config_init_t)bnx2x_8481_config_init,
7115 .read_status = (read_status_t)bnx2x_848xx_read_status,
7116 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
7117 .config_loopback = (config_loopback_t)NULL,
7118 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7119 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
7f02c4ad 7120 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 7121 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 7122};
7123
de6eae1f
YR		 7124static struct bnx2x_phy phy_84823 = {
7125 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7126 .addr = 0xff,
a22f0788
YR		 7127 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7128 FLAGS_REARM_LATCH_SIGNAL,
de6eae1f
YR		 7129 .def_md_devad = 0,
7130 .reserved = 0,
7131 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7132 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7133 .mdio_ctrl = 0,
7134 .supported = (SUPPORTED_10baseT_Half |
7135 SUPPORTED_10baseT_Full |
7136 SUPPORTED_100baseT_Half |
7137 SUPPORTED_100baseT_Full |
7138 SUPPORTED_1000baseT_Full |
7139 SUPPORTED_10000baseT_Full |
7140 SUPPORTED_TP |
7141 SUPPORTED_Autoneg |
7142 SUPPORTED_Pause |
7143 SUPPORTED_Asym_Pause),
7144 .media_type = ETH_PHY_BASE_T,
7145 .ver_addr = 0,
7146 .req_flow_ctrl = 0,
7147 .req_line_speed = 0,
7148 .speed_cap_mask = 0,
7149 .req_duplex = 0,
7150 .rsrv = 0,
7151 .config_init = (config_init_t)bnx2x_848x3_config_init,
7152 .read_status = (read_status_t)bnx2x_848xx_read_status,
7153 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7154 .config_loopback = (config_loopback_t)NULL,
7155 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7156 .hw_reset = (hw_reset_t)NULL,
7f02c4ad 7157 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 7158 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f
YR		 7159};
7160
c87bca1e
YR		 7161static struct bnx2x_phy phy_84833 = {
7162 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
7163 .addr = 0xff,
7164 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7165 FLAGS_REARM_LATCH_SIGNAL,
7166 .def_md_devad = 0,
7167 .reserved = 0,
7168 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7169 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7170 .mdio_ctrl = 0,
7171 .supported = (SUPPORTED_10baseT_Half |
7172 SUPPORTED_10baseT_Full |
7173 SUPPORTED_100baseT_Half |
7174 SUPPORTED_100baseT_Full |
7175 SUPPORTED_1000baseT_Full |
7176 SUPPORTED_10000baseT_Full |
7177 SUPPORTED_TP |
7178 SUPPORTED_Autoneg |
7179 SUPPORTED_Pause |
7180 SUPPORTED_Asym_Pause),
7181 .media_type = ETH_PHY_BASE_T,
7182 .ver_addr = 0,
7183 .req_flow_ctrl = 0,
7184 .req_line_speed = 0,
7185 .speed_cap_mask = 0,
7186 .req_duplex = 0,
7187 .rsrv = 0,
7188 .config_init = (config_init_t)bnx2x_848x3_config_init,
7189 .read_status = (read_status_t)bnx2x_848xx_read_status,
7190 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7191 .config_loopback = (config_loopback_t)NULL,
7192 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7193 .hw_reset = (hw_reset_t)NULL,
7194 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
7195 .phy_specific_func = (phy_specific_func_t)NULL
7196};
7197
de6eae1f
YR		 7198/*****************************************************************/
7199/* */
7200/* Populate the phy according. Main function: bnx2x_populate_phy */
7201/* */
7202/*****************************************************************/
7203
7204static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7205 struct bnx2x_phy *phy, u8 port,
7206 u8 phy_index)
7207{
7208 /* Get the 4 lanes xgxs config rx and tx */
7209 u32 rx = 0, tx = 0, i;
7210 for (i = 0; i < 2; i++) {
2cf7acf9 7211 /*
de6eae1f
YR		 7212 * INT_PHY and EXT_PHY1 share the same value location in the
7213 * shmem. When num_phys is greater than 1, than this value
7214 * applies only to EXT_PHY1
7215 */
a22f0788
YR		 7216 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7217 rx = REG_RD(bp, shmem_base +
7218 offsetof(struct shmem_region,
cd88ccee 7219 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
a22f0788
YR		 7220
7221 tx = REG_RD(bp, shmem_base +
7222 offsetof(struct shmem_region,
cd88ccee 7223 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
a22f0788
YR		 7224 } else {
7225 rx = REG_RD(bp, shmem_base +
7226 offsetof(struct shmem_region,
cd88ccee 7227 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
de6eae1f 7228
a22f0788
YR		 7229 tx = REG_RD(bp, shmem_base +
7230 offsetof(struct shmem_region,
cd88ccee 7231 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
a22f0788 7232 }
de6eae1f
YR		 7233
7234 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7235 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7236
7237 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7238 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7239 }
7240}
7241
7242static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7243 u8 phy_index, u8 port)
7244{
7245 u32 ext_phy_config = 0;
7246 switch (phy_index) {
7247 case EXT_PHY1:
7248 ext_phy_config = REG_RD(bp, shmem_base +
7249 offsetof(struct shmem_region,
7250 dev_info.port_hw_config[port].external_phy_config));
7251 break;
a22f0788
YR		 7252 case EXT_PHY2:
7253 ext_phy_config = REG_RD(bp, shmem_base +
7254 offsetof(struct shmem_region,
7255 dev_info.port_hw_config[port].external_phy_config2));
7256 break;
de6eae1f
YR		 7257 default:
7258 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7259 return -EINVAL;
7260 }
7261
7262 return ext_phy_config;
7263}
7264static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7265 struct bnx2x_phy *phy)
7266{
7267 u32 phy_addr;
7268 u32 chip_id;
7269 u32 switch_cfg = (REG_RD(bp, shmem_base +
7270 offsetof(struct shmem_region,
7271 dev_info.port_feature_config[port].link_config)) &
7272 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7273 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7274 switch (switch_cfg) {
7275 case SWITCH_CFG_1G:
7276 phy_addr = REG_RD(bp,
7277 NIG_REG_SERDES0_CTRL_PHY_ADDR +
7278 port * 0x10);
7279 *phy = phy_serdes;
7280 break;
7281 case SWITCH_CFG_10G:
7282 phy_addr = REG_RD(bp,
7283 NIG_REG_XGXS0_CTRL_PHY_ADDR +
7284 port * 0x18);
7285 *phy = phy_xgxs;
7286 break;
7287 default:
7288 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7289 return -EINVAL;
7290 }
7291 phy->addr = (u8)phy_addr;
7292 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7293 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7294 port);
f2e0899f
DK		 7295 if (CHIP_IS_E2(bp))
7296 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7297 else
7298 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
de6eae1f
YR		 7299
7300 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7301 port, phy->addr, phy->mdio_ctrl);
7302
7303 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7304 return 0;
7305}
7306
7307static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7308 u8 phy_index,
7309 u32 shmem_base,
a22f0788 7310 u32 shmem2_base,
de6eae1f
YR		 7311 u8 port,
7312 struct bnx2x_phy *phy)
7313{
7314 u32 ext_phy_config, phy_type, config2;
7315 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7316 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7317 phy_index, port);
7318 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7319 /* Select the phy type */
7320 switch (phy_type) {
7321 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7322 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7323 *phy = phy_8073;
7324 break;
7325 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7326 *phy = phy_8705;
7327 break;
7328 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7329 *phy = phy_8706;
7330 break;
7331 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7332 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7333 *phy = phy_8726;
7334 break;
7335 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7336 /* BCM8727_NOC => BCM8727 no over current */
7337 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7338 *phy = phy_8727;
7339 phy->flags |= FLAGS_NOC;
7340 break;
7341 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7342 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7343 *phy = phy_8727;
7344 break;
7345 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7346 *phy = phy_8481;
7347 break;
7348 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7349 *phy = phy_84823;
7350 break;
c87bca1e
YR		 7351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
7352 *phy = phy_84833;
7353 break;
de6eae1f
YR		 7354 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7355 *phy = phy_7101;
7356 break;
7357 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7358 *phy = phy_null;
7359 return -EINVAL;
7360 default:
7361 *phy = phy_null;
7362 return 0;
7363 }
7364
7365 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7366 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7367
2cf7acf9
YR		 7368 /*
7369 * The shmem address of the phy version is located on different
7370 * structures. In case this structure is too old, do not set
7371 * the address
7372 */
de6eae1f
YR		 7373 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7374 dev_info.shared_hw_config.config2));
a22f0788
YR		 7375 if (phy_index == EXT_PHY1) {
7376 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7377 port_mb[port].ext_phy_fw_version);
de6eae1f 7378
cd88ccee
YR		 7379 /* Check specific mdc mdio settings */
7380 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7381 mdc_mdio_access = config2 &
7382 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
a22f0788
YR		 7383 } else {
7384 u32 size = REG_RD(bp, shmem2_base);
de6eae1f 7385
a22f0788
YR		 7386 if (size >
7387 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7388 phy->ver_addr = shmem2_base +
7389 offsetof(struct shmem2_region,
7390 ext_phy_fw_version2[port]);
7391 }
7392 /* Check specific mdc mdio settings */
7393 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7394 mdc_mdio_access = (config2 &
7395 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7396 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7397 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7398 }
de6eae1f
YR		 7399 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7400
2cf7acf9 7401 /*
de6eae1f
YR		 7402 * In case mdc/mdio_access of the external phy is different than the
7403 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7404 * to prevent one port interfere with another port's CL45 operations.
7405 */
7406 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7407 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7408 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7409 phy_type, port, phy_index);
7410 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
7411 phy->addr, phy->mdio_ctrl);
7412 return 0;
7413}
7414
7415static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
a22f0788 7416 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
de6eae1f
YR		 7417{
7418 u8 status = 0;
7419 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7420 if (phy_index == INT_PHY)
7421 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
a22f0788 7422 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 7423 port, phy);
7424 return status;
7425}
7426
7427static void bnx2x_phy_def_cfg(struct link_params *params,
7428 struct bnx2x_phy *phy,
a22f0788 7429 u8 phy_index)
de6eae1f
YR		 7430{
7431 struct bnx2x *bp = params->bp;
7432 u32 link_config;
7433 /* Populate the default phy configuration for MF mode */
a22f0788
YR		 7434 if (phy_index == EXT_PHY2) {
7435 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 7436 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 7437 port_feature_config[params->port].link_config2));
7438 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 7439 offsetof(struct shmem_region,
7440 dev_info.
a22f0788
YR		 7441 port_hw_config[params->port].speed_capability_mask2));
7442 } else {
7443 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 7444 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 7445 port_feature_config[params->port].link_config));
7446 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 7447 offsetof(struct shmem_region,
7448 dev_info.
7449 port_hw_config[params->port].speed_capability_mask));
a22f0788
YR		 7450 }
7451 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7452 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
de6eae1f
YR		 7453
7454 phy->req_duplex = DUPLEX_FULL;
7455 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7456 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7457 phy->req_duplex = DUPLEX_HALF;
7458 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7459 phy->req_line_speed = SPEED_10;
7460 break;
7461 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7462 phy->req_duplex = DUPLEX_HALF;
7463 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7464 phy->req_line_speed = SPEED_100;
7465 break;
7466 case PORT_FEATURE_LINK_SPEED_1G:
7467 phy->req_line_speed = SPEED_1000;
7468 break;
7469 case PORT_FEATURE_LINK_SPEED_2_5G:
7470 phy->req_line_speed = SPEED_2500;
7471 break;
7472 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7473 phy->req_line_speed = SPEED_10000;
7474 break;
7475 default:
7476 phy->req_line_speed = SPEED_AUTO_NEG;
7477 break;
7478 }
7479
7480 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
7481 case PORT_FEATURE_FLOW_CONTROL_AUTO:
7482 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7483 break;
7484 case PORT_FEATURE_FLOW_CONTROL_TX:
7485 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7486 break;
7487 case PORT_FEATURE_FLOW_CONTROL_RX:
7488 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7489 break;
7490 case PORT_FEATURE_FLOW_CONTROL_BOTH:
7491 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7492 break;
7493 default:
7494 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7495 break;
7496 }
7497}
7498
a22f0788
YR		 7499u32 bnx2x_phy_selection(struct link_params *params)
7500{
7501 u32 phy_config_swapped, prio_cfg;
7502 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7503
7504 phy_config_swapped = params->multi_phy_config &
7505 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7506
7507 prio_cfg = params->multi_phy_config &
7508 PORT_HW_CFG_PHY_SELECTION_MASK;
7509
7510 if (phy_config_swapped) {
7511 switch (prio_cfg) {
7512 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7513 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7514 break;
7515 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7516 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7517 break;
7518 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7519 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7520 break;
7521 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7522 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7523 break;
7524 }
7525 } else
7526 return_cfg = prio_cfg;
7527
7528 return return_cfg;
7529}
7530
7531
de6eae1f
YR		 7532u8 bnx2x_phy_probe(struct link_params *params)
7533{
7534 u8 phy_index, actual_phy_idx, link_cfg_idx;
a22f0788 7535 u32 phy_config_swapped;
de6eae1f
YR		 7536 struct bnx2x *bp = params->bp;
7537 struct bnx2x_phy *phy;
7538 params->num_phys = 0;
7539 DP(NETIF_MSG_LINK, "Begin phy probe\n");
a22f0788
YR		 7540 phy_config_swapped = params->multi_phy_config &
7541 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 7542
7543 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7544 phy_index++) {
7545 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7546 actual_phy_idx = phy_index;
a22f0788
YR		 7547 if (phy_config_swapped) {
7548 if (phy_index == EXT_PHY1)
7549 actual_phy_idx = EXT_PHY2;
7550 else if (phy_index == EXT_PHY2)
7551 actual_phy_idx = EXT_PHY1;
7552 }
7553 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7554 " actual_phy_idx %x\n", phy_config_swapped,
7555 phy_index, actual_phy_idx);
de6eae1f
YR		 7556 phy = &params->phy[actual_phy_idx];
7557 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
a22f0788 7558 params->shmem2_base, params->port,
de6eae1f
YR		 7559 phy) != 0) {
7560 params->num_phys = 0;
7561 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7562 phy_index);
7563 for (phy_index = INT_PHY;
7564 phy_index < MAX_PHYS;
7565 phy_index++)
7566 *phy = phy_null;
7567 return -EINVAL;
7568 }
7569 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7570 break;
7571
a22f0788 7572 bnx2x_phy_def_cfg(params, phy, phy_index);
de6eae1f
YR		 7573 params->num_phys++;
7574 }
7575
7576 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7577 return 0;
7578}
7579
de6eae1f
YR		 7580static void set_phy_vars(struct link_params *params)
7581{
7582 struct bnx2x *bp = params->bp;
a22f0788
YR		 7583 u8 actual_phy_idx, phy_index, link_cfg_idx;
7584 u8 phy_config_swapped = params->multi_phy_config &
7585 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 7586 for (phy_index = INT_PHY; phy_index < params->num_phys;
7587 phy_index++) {
a22f0788 7588 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
de6eae1f 7589 actual_phy_idx = phy_index;
a22f0788
YR		 7590 if (phy_config_swapped) {
7591 if (phy_index == EXT_PHY1)
7592 actual_phy_idx = EXT_PHY2;
7593 else if (phy_index == EXT_PHY2)
7594 actual_phy_idx = EXT_PHY1;
7595 }
cd88ccee 7596 params->phy[actual_phy_idx].req_flow_ctrl =
a22f0788 7597 params->req_flow_ctrl[link_cfg_idx];
de6eae1f
YR		 7598
7599 params->phy[actual_phy_idx].req_line_speed =
a22f0788 7600 params->req_line_speed[link_cfg_idx];
de6eae1f
YR		 7601
7602 params->phy[actual_phy_idx].speed_cap_mask =
a22f0788 7603 params->speed_cap_mask[link_cfg_idx];
de6eae1f
YR		 7604
7605 params->phy[actual_phy_idx].req_duplex =
a22f0788 7606 params->req_duplex[link_cfg_idx];
de6eae1f
YR		 7607
7608 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7609 " speed_cap_mask %x\n",
7610 params->phy[actual_phy_idx].req_flow_ctrl,
7611 params->phy[actual_phy_idx].req_line_speed,
7612 params->phy[actual_phy_idx].speed_cap_mask);
7613 }
7614}
7615
7616u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7617{
7618 struct bnx2x *bp = params->bp;
de6eae1f 7619 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
a22f0788
YR		 7620 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7621 params->req_line_speed[0], params->req_flow_ctrl[0]);
7622 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7623 params->req_line_speed[1], params->req_flow_ctrl[1]);
de6eae1f
YR		 7624 vars->link_status = 0;
7625 vars->phy_link_up = 0;
7626 vars->link_up = 0;
7627 vars->line_speed = 0;
7628 vars->duplex = DUPLEX_FULL;
7629 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7630 vars->mac_type = MAC_TYPE_NONE;
7631 vars->phy_flags = 0;
7632
7633 /* disable attentions */
7634 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7635 (NIG_MASK_XGXS0_LINK_STATUS |
7636 NIG_MASK_XGXS0_LINK10G |
7637 NIG_MASK_SERDES0_LINK_STATUS |
7638 NIG_MASK_MI_INT));
7639
7640 bnx2x_emac_init(params, vars);
7641
7642 if (params->num_phys == 0) {
7643 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7644 return -EINVAL;
7645 }
7646 set_phy_vars(params);
7647
7648 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
de6eae1f
YR		 7649 if (params->loopback_mode == LOOPBACK_BMAC) {
7650
7651 vars->link_up = 1;
7652 vars->line_speed = SPEED_10000;
7653 vars->duplex = DUPLEX_FULL;
7654 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7655 vars->mac_type = MAC_TYPE_BMAC;
b7737c9b 7656
de6eae1f 7657 vars->phy_flags = PHY_XGXS_FLAG;
b7737c9b 7658
de6eae1f 7659 bnx2x_xgxs_deassert(params);
b7737c9b 7660
de6eae1f
YR		 7661 /* set bmac loopback */
7662 bnx2x_bmac_enable(params, vars, 1);
b7737c9b 7663
cd88ccee 7664 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
b7737c9b 7665
de6eae1f 7666 } else if (params->loopback_mode == LOOPBACK_EMAC) {
b7737c9b 7667
de6eae1f
YR		 7668 vars->link_up = 1;
7669 vars->line_speed = SPEED_1000;
7670 vars->duplex = DUPLEX_FULL;
7671 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7672 vars->mac_type = MAC_TYPE_EMAC;
b7737c9b 7673
de6eae1f 7674 vars->phy_flags = PHY_XGXS_FLAG;
e10bc84d 7675
de6eae1f
YR		 7676 bnx2x_xgxs_deassert(params);
7677 /* set bmac loopback */
7678 bnx2x_emac_enable(params, vars, 1);
7679 bnx2x_emac_program(params, vars);
cd88ccee 7680 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
b7737c9b 7681
de6eae1f
YR		 7682 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7683 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
b7737c9b 7684
de6eae1f 7685 vars->link_up = 1;
de6eae1f 7686 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
a22f0788
YR		 7687 vars->duplex = DUPLEX_FULL;
7688 if (params->req_line_speed[0] == SPEED_1000) {
7689 vars->line_speed = SPEED_1000;
7690 vars->mac_type = MAC_TYPE_EMAC;
7691 } else {
7692 vars->line_speed = SPEED_10000;
7693 vars->mac_type = MAC_TYPE_BMAC;
7694 }
62b29a5d 7695
de6eae1f
YR		 7696 bnx2x_xgxs_deassert(params);
7697 bnx2x_link_initialize(params, vars);
c18aa15d 7698
a22f0788
YR		 7699 if (params->req_line_speed[0] == SPEED_1000) {
7700 bnx2x_emac_program(params, vars);
7701 bnx2x_emac_enable(params, vars, 0);
7702 } else
cd88ccee 7703 bnx2x_bmac_enable(params, vars, 0);
de6eae1f
YR		 7704 if (params->loopback_mode == LOOPBACK_XGXS) {
7705 /* set 10G XGXS loopback */
7706 params->phy[INT_PHY].config_loopback(
7707 &params->phy[INT_PHY],
7708 params);
c18aa15d 7709
de6eae1f
YR		 7710 } else {
7711 /* set external phy loopback */
7712 u8 phy_index;
7713 for (phy_index = EXT_PHY1;
7714 phy_index < params->num_phys; phy_index++) {
7715 if (params->phy[phy_index].config_loopback)
7716 params->phy[phy_index].config_loopback(
7717 &params->phy[phy_index],
7718 params);
7719 }
7720 }
cd88ccee 7721 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
de6eae1f 7722
7f02c4ad
YR		 7723 bnx2x_set_led(params, vars,
7724 LED_MODE_OPER, vars->line_speed);
de6eae1f
YR		 7725 } else
7726 /* No loopback */
7727 {
7728 if (params->switch_cfg == SWITCH_CFG_10G)
7729 bnx2x_xgxs_deassert(params);
7730 else
7731 bnx2x_serdes_deassert(bp, params->port);
7f02c4ad 7732
de6eae1f
YR		 7733 bnx2x_link_initialize(params, vars);
7734 msleep(30);
7735 bnx2x_link_int_enable(params);
7736 }
e10bc84d
YR		 7737 return 0;
7738}
de6eae1f 7739u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
cd88ccee 7740 u8 reset_ext_phy)
b7737c9b
YR		 7741{
7742 struct bnx2x *bp = params->bp;
cf1d972c 7743 u8 phy_index, port = params->port, clear_latch_ind = 0;
de6eae1f
YR		 7744 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7745 /* disable attentions */
7746 vars->link_status = 0;
7747 bnx2x_update_mng(params, vars->link_status);
7748 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 7749 (NIG_MASK_XGXS0_LINK_STATUS |
7750 NIG_MASK_XGXS0_LINK10G |
7751 NIG_MASK_SERDES0_LINK_STATUS |
7752 NIG_MASK_MI_INT));
b7737c9b 7753
de6eae1f
YR		 7754 /* activate nig drain */
7755 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
b7737c9b 7756
de6eae1f
YR		 7757 /* disable nig egress interface */
7758 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7759 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
b7737c9b 7760
de6eae1f
YR		 7761 /* Stop BigMac rx */
7762 bnx2x_bmac_rx_disable(bp, port);
b7737c9b 7763
de6eae1f
YR		 7764 /* disable emac */
7765 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
b7737c9b 7766
de6eae1f 7767 msleep(10);
25985edc 7768 /* The PHY reset is controlled by GPIO 1
de6eae1f
YR		 7769 * Hold it as vars low
7770 */
7771 /* clear link led */
7f02c4ad
YR		 7772 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7773
de6eae1f
YR		 7774 if (reset_ext_phy) {
7775 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7776 phy_index++) {
7777 if (params->phy[phy_index].link_reset)
7778 params->phy[phy_index].link_reset(
7779 &params->phy[phy_index],
7780 params);
cf1d972c
YR		 7781 if (params->phy[phy_index].flags &
7782 FLAGS_REARM_LATCH_SIGNAL)
7783 clear_latch_ind = 1;
b7737c9b 7784 }
b7737c9b
YR		 7785 }
7786
cf1d972c
YR		 7787 if (clear_latch_ind) {
7788 /* Clear latching indication */
7789 bnx2x_rearm_latch_signal(bp, port, 0);
7790 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7791 1 << NIG_LATCH_BC_ENABLE_MI_INT);
7792 }
de6eae1f
YR		 7793 if (params->phy[INT_PHY].link_reset)
7794 params->phy[INT_PHY].link_reset(
7795 &params->phy[INT_PHY], params);
7796 /* reset BigMac */
7797 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7798 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
b7737c9b 7799
de6eae1f
YR		 7800 /* disable nig ingress interface */
7801 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7802 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7803 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7804 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7805 vars->link_up = 0;
b7737c9b
YR		 7806 return 0;
7807}
7808
de6eae1f
YR		 7809/****************************************************************************/
7810/* Common function */
7811/****************************************************************************/
f2e0899f
DK		 7812static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7813 u32 shmem_base_path[],
7814 u32 shmem2_base_path[], u8 phy_index,
7815 u32 chip_id)
6bbca910 7816{
e10bc84d
YR		 7817 struct bnx2x_phy phy[PORT_MAX];
7818 struct bnx2x_phy *phy_blk[PORT_MAX];
6bbca910 7819 u16 val;
c8e64df4 7820 s8 port = 0;
f2e0899f 7821 s8 port_of_path = 0;
c8e64df4
YR		 7822 u32 swap_val, swap_override;
7823 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7824 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7825 port ^= (swap_val && swap_override);
7826 bnx2x_ext_phy_hw_reset(bp, port);
6bbca910
YR		 7827 /* PART1 - Reset both phys */
7828 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7829 u32 shmem_base, shmem2_base;
7830 /* In E2, same phy is using for port0 of the two paths */
7831 if (CHIP_IS_E2(bp)) {
7832 shmem_base = shmem_base_path[port];
7833 shmem2_base = shmem2_base_path[port];
7834 port_of_path = 0;
7835 } else {
7836 shmem_base = shmem_base_path[0];
7837 shmem2_base = shmem2_base_path[0];
7838 port_of_path = port;
7839 }
7840
6bbca910 7841 /* Extract the ext phy address for the port */
a22f0788 7842 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 7843 port_of_path, &phy[port]) !=
e10bc84d
YR		 7844 0) {
7845 DP(NETIF_MSG_LINK, "populate_phy failed\n");
7846 return -EINVAL;
7847 }
6bbca910 7848 /* disable attentions */
6a71bbe0
YR		 7849 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7850 port_of_path*4,
cd88ccee
YR		 7851 (NIG_MASK_XGXS0_LINK_STATUS |
7852 NIG_MASK_XGXS0_LINK10G |
7853 NIG_MASK_SERDES0_LINK_STATUS |
7854 NIG_MASK_MI_INT));
6bbca910 7855
6bbca910
YR		 7856 /* Need to take the phy out of low power mode in order
7857 to write to access its registers */
7858 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 7859 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7860 port);
6bbca910
YR		 7861
7862 /* Reset the phy */
e10bc84d 7863 bnx2x_cl45_write(bp, &phy[port],
cd88ccee
YR		 7864 MDIO_PMA_DEVAD,
7865 MDIO_PMA_REG_CTRL,
7866 1<<15);
6bbca910
YR		 7867 }
7868
7869 /* Add delay of 150ms after reset */
7870 msleep(150);
7871
e10bc84d
YR		 7872 if (phy[PORT_0].addr & 0x1) {
7873 phy_blk[PORT_0] = &(phy[PORT_1]);
7874 phy_blk[PORT_1] = &(phy[PORT_0]);
7875 } else {
7876 phy_blk[PORT_0] = &(phy[PORT_0]);
7877 phy_blk[PORT_1] = &(phy[PORT_1]);
7878 }
7879
6bbca910
YR		 7880 /* PART2 - Download firmware to both phys */
7881 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7882 if (CHIP_IS_E2(bp))
7883 port_of_path = 0;
7884 else
7885 port_of_path = port;
6bbca910 7886
f2e0899f
DK		 7887 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7888 phy_blk[port]->addr);
5c99274b
YR		 7889 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7890 port_of_path))
6bbca910 7891 return -EINVAL;
6bbca910
YR		 7892
7893 /* Only set bit 10 = 1 (Tx power down) */
e10bc84d 7894 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 7895 MDIO_PMA_DEVAD,
7896 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910
YR		 7897
7898 /* Phase1 of TX_POWER_DOWN reset */
e10bc84d 7899 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 7900 MDIO_PMA_DEVAD,
7901 MDIO_PMA_REG_TX_POWER_DOWN,
7902 (val | 1<<10));
6bbca910
YR		 7903 }
7904
2cf7acf9
YR		 7905 /*
7906 * Toggle Transmitter: Power down and then up with 600ms delay
7907 * between
7908 */
6bbca910
YR		 7909 msleep(600);
7910
7911 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
7912 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 7913 /* Phase2 of POWER_DOWN_RESET */
6bbca910 7914 /* Release bit 10 (Release Tx power down) */
e10bc84d 7915 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 7916 MDIO_PMA_DEVAD,
7917 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910 7918
e10bc84d 7919 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 7920 MDIO_PMA_DEVAD,
7921 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6bbca910
YR		 7922 msleep(15);
7923
7924 /* Read modify write the SPI-ROM version select register */
e10bc84d 7925 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 7926 MDIO_PMA_DEVAD,
7927 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
e10bc84d 7928 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 7929 MDIO_PMA_DEVAD,
7930 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6bbca910
YR		 7931
7932 /* set GPIO2 back to LOW */
7933 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 7934 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6bbca910
YR		 7935 }
7936 return 0;
6bbca910 7937}
f2e0899f
DK		 7938static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7939 u32 shmem_base_path[],
7940 u32 shmem2_base_path[], u8 phy_index,
7941 u32 chip_id)
de6eae1f
YR		 7942{
7943 u32 val;
7944 s8 port;
7945 struct bnx2x_phy phy;
7946 /* Use port1 because of the static port-swap */
7947 /* Enable the module detection interrupt */
7948 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
7949 val |= ((1<<MISC_REGISTERS_GPIO_3)|
7950 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
7951 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
7952
650154bf 7953 bnx2x_ext_phy_hw_reset(bp, 0);
de6eae1f
YR		 7954 msleep(5);
7955 for (port = 0; port < PORT_MAX; port++) {
f2e0899f
DK		 7956 u32 shmem_base, shmem2_base;
7957
7958 /* In E2, same phy is using for port0 of the two paths */
7959 if (CHIP_IS_E2(bp)) {
7960 shmem_base = shmem_base_path[port];
7961 shmem2_base = shmem2_base_path[port];
7962 } else {
7963 shmem_base = shmem_base_path[0];
7964 shmem2_base = shmem2_base_path[0];
7965 }
de6eae1f 7966 /* Extract the ext phy address for the port */
a22f0788 7967 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 7968 port, &phy) !=
7969 0) {
7970 DP(NETIF_MSG_LINK, "populate phy failed\n");
7971 return -EINVAL;
7972 }
7973
7974 /* Reset phy*/
7975 bnx2x_cl45_write(bp, &phy,
7976 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
7977
7978
7979 /* Set fault module detected LED on */
7980 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
cd88ccee
YR		 7981 MISC_REGISTERS_GPIO_HIGH,
7982 port);
de6eae1f
YR		 7983 }
7984
7985 return 0;
7986}
a8db5b4c
YR		 7987static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
7988 u8 *io_gpio, u8 *io_port)
7989{
7990
7991 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
7992 offsetof(struct shmem_region,
7993 dev_info.port_hw_config[PORT_0].default_cfg));
7994 switch (phy_gpio_reset) {
7995 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
7996 *io_gpio = 0;
7997 *io_port = 0;
7998 break;
7999 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
8000 *io_gpio = 1;
8001 *io_port = 0;
8002 break;
8003 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
8004 *io_gpio = 2;
8005 *io_port = 0;
8006 break;
8007 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
8008 *io_gpio = 3;
8009 *io_port = 0;
8010 break;
8011 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
8012 *io_gpio = 0;
8013 *io_port = 1;
8014 break;
8015 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
8016 *io_gpio = 1;
8017 *io_port = 1;
8018 break;
8019 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
8020 *io_gpio = 2;
8021 *io_port = 1;
8022 break;
8023 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
8024 *io_gpio = 3;
8025 *io_port = 1;
8026 break;
8027 default:
8028 /* Don't override the io_gpio and io_port */
8029 break;
8030 }
8031}
f2e0899f
DK		 8032static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
8033 u32 shmem_base_path[],
8034 u32 shmem2_base_path[], u8 phy_index,
8035 u32 chip_id)
4d295db0 8036{
a8db5b4c 8037 s8 port, reset_gpio;
4d295db0 8038 u32 swap_val, swap_override;
e10bc84d
YR		 8039 struct bnx2x_phy phy[PORT_MAX];
8040 struct bnx2x_phy *phy_blk[PORT_MAX];
f2e0899f 8041 s8 port_of_path;
cd88ccee
YR		 8042 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8043 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4d295db0 8044
a8db5b4c 8045 reset_gpio = MISC_REGISTERS_GPIO_1;
a22f0788 8046 port = 1;
4d295db0 8047
a8db5b4c
YR		 8048 /*
8049 * Retrieve the reset gpio/port which control the reset.
8050 * Default is GPIO1, PORT1
8051 */
8052 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
8053 (u8 *)&reset_gpio, (u8 *)&port);
a22f0788
YR		 8054
8055 /* Calculate the port based on port swap */
8056 port ^= (swap_val && swap_override);
8057
a8db5b4c
YR		 8058 /* Initiate PHY reset*/
8059 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
8060 port);
8061 msleep(1);
8062 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8063 port);
8064
a22f0788 8065 msleep(5);
bc7f0a05 8066
4d295db0 8067 /* PART1 - Reset both phys */
a22f0788 8068 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 8069 u32 shmem_base, shmem2_base;
8070
8071 /* In E2, same phy is using for port0 of the two paths */
8072 if (CHIP_IS_E2(bp)) {
8073 shmem_base = shmem_base_path[port];
8074 shmem2_base = shmem2_base_path[port];
8075 port_of_path = 0;
8076 } else {
8077 shmem_base = shmem_base_path[0];
8078 shmem2_base = shmem2_base_path[0];
8079 port_of_path = port;
8080 }
8081
4d295db0 8082 /* Extract the ext phy address for the port */
a22f0788 8083 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 8084 port_of_path, &phy[port]) !=
e10bc84d
YR		 8085 0) {
8086 DP(NETIF_MSG_LINK, "populate phy failed\n");
8087 return -EINVAL;
8088 }
4d295db0 8089 /* disable attentions */
f2e0899f
DK		 8090 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8091 port_of_path*4,
8092 (NIG_MASK_XGXS0_LINK_STATUS |
8093 NIG_MASK_XGXS0_LINK10G |
8094 NIG_MASK_SERDES0_LINK_STATUS |
8095 NIG_MASK_MI_INT));
4d295db0 8096
4d295db0
EG		 8097
8098 /* Reset the phy */
e10bc84d 8099 bnx2x_cl45_write(bp, &phy[port],
cd88ccee 8100 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
4d295db0
EG		 8101 }
8102
8103 /* Add delay of 150ms after reset */
8104 msleep(150);
e10bc84d
YR		 8105 if (phy[PORT_0].addr & 0x1) {
8106 phy_blk[PORT_0] = &(phy[PORT_1]);
8107 phy_blk[PORT_1] = &(phy[PORT_0]);
8108 } else {
8109 phy_blk[PORT_0] = &(phy[PORT_0]);
8110 phy_blk[PORT_1] = &(phy[PORT_1]);
8111 }
4d295db0 8112 /* PART2 - Download firmware to both phys */
e10bc84d 8113 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
cd88ccee 8114 if (CHIP_IS_E2(bp))
f2e0899f
DK		 8115 port_of_path = 0;
8116 else
8117 port_of_path = port;
8118 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8119 phy_blk[port]->addr);
5c99274b
YR		 8120 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8121 port_of_path))
4d295db0 8122 return -EINVAL;
4d295db0 8123
5c99274b 8124 }
4d295db0
EG		 8125 return 0;
8126}
8127
f2e0899f
DK		 8128static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
8129 u32 shmem2_base_path[], u8 phy_index,
8130 u32 ext_phy_type, u32 chip_id)
6bbca910
YR		 8131{
8132 u8 rc = 0;
6bbca910
YR		 8133
8134 switch (ext_phy_type) {
8135 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
f2e0899f
DK		 8136 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
8137 shmem2_base_path,
8138 phy_index, chip_id);
6bbca910 8139 break;
4d295db0
EG		 8140
8141 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8142 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
f2e0899f
DK		 8143 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
8144 shmem2_base_path,
8145 phy_index, chip_id);
4d295db0
EG		 8146 break;
8147
589abe3a 8148 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
2cf7acf9
YR		 8149 /*
8150 * GPIO1 affects both ports, so there's need to pull
8151 * it for single port alone
8152 */
f2e0899f
DK		 8153 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
8154 shmem2_base_path,
8155 phy_index, chip_id);
a22f0788
YR		 8156 break;
8157 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8158 rc = -EINVAL;
4f60dab1 8159 break;
6bbca910
YR		 8160 default:
8161 DP(NETIF_MSG_LINK,
2cf7acf9
YR		 8162 "ext_phy 0x%x common init not required\n",
8163 ext_phy_type);
6bbca910
YR		 8164 break;
8165 }
8166
6d870c39
YR		 8167 if (rc != 0)
8168 netdev_err(bp->dev, "Warning: PHY was not initialized,"
8169 " Port %d\n",
8170 0);
6bbca910
YR		 8171 return rc;
8172}
8173
f2e0899f
DK		 8174u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
8175 u32 shmem2_base_path[], u32 chip_id)
a22f0788
YR		 8176{
8177 u8 rc = 0;
b21a3424 8178 u32 phy_ver;
a22f0788
YR		 8179 u8 phy_index;
8180 u32 ext_phy_type, ext_phy_config;
8181 DP(NETIF_MSG_LINK, "Begin common phy init\n");
8182
b21a3424
YR		 8183 /* Check if common init was already done */
8184 phy_ver = REG_RD(bp, shmem_base_path[0] +
8185 offsetof(struct shmem_region,
8186 port_mb[PORT_0].ext_phy_fw_version));
8187 if (phy_ver) {
8188 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8189 phy_ver);
8190 return 0;
8191 }
8192
a22f0788
YR		 8193 /* Read the ext_phy_type for arbitrary port(0) */
8194 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8195 phy_index++) {
8196 ext_phy_config = bnx2x_get_ext_phy_config(bp,
f2e0899f 8197 shmem_base_path[0],
a22f0788
YR		 8198 phy_index, 0);
8199 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
f2e0899f
DK		 8200 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8201 shmem2_base_path,
8202 phy_index, ext_phy_type,
8203 chip_id);
a22f0788
YR		 8204 }
8205 return rc;
8206}
d90d96ba 8207
a22f0788 8208u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
d90d96ba
YR		 8209{
8210 u8 phy_index;
8211 struct bnx2x_phy phy;
8212 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8213 phy_index++) {
a22f0788 8214 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 8215 0, &phy) != 0) {
8216 DP(NETIF_MSG_LINK, "populate phy failed\n");
8217 return 0;
8218 }
8219
8220 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8221 return 1;
8222 }
8223 return 0;
8224}
8225
8226u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8227 u32 shmem_base,
a22f0788 8228 u32 shmem2_base,
d90d96ba
YR		 8229 u8 port)
8230{
8231 u8 phy_index, fan_failure_det_req = 0;
8232 struct bnx2x_phy phy;
8233 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8234 phy_index++) {
a22f0788 8235 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 8236 port, &phy)
8237 != 0) {
8238 DP(NETIF_MSG_LINK, "populate phy failed\n");
8239 return 0;
8240 }
8241 fan_failure_det_req |= (phy.flags &
8242 FLAGS_FAN_FAILURE_DET_REQ);
8243 }
8244 return fan_failure_det_req;
8245}
8246
8247void bnx2x_hw_reset_phy(struct link_params *params)
8248{
8249 u8 phy_index;
8250 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8251 phy_index++) {
8252 if (params->phy[phy_index].hw_reset) {
8253 params->phy[phy_index].hw_reset(
8254 &params->phy[phy_index],
8255 params);
8256 params->phy[phy_index] = phy_null;
8257 }
8258 }
8259}
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