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bnx2x: Fix BCM8073/BCM8727 microcode loading
[mirror_ubuntu-kernels.git] / drivers / net / bnx2x / bnx2x_link.c
CommitLineData
d05c26ce 1/* Copyright 2008-2009 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
7995c64e
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
ea4e040a
YR		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
ea4e040a 26
ea4e040a
YR		 27#include "bnx2x.h"
28
29/********************************************************/
3196a88a 30#define ETH_HLEN 14
523224a3 31#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */
ea4e040a
YR		 32#define ETH_MIN_PACKET_SIZE 60
33#define ETH_MAX_PACKET_SIZE 1500
34#define ETH_MAX_JUMBO_PACKET_SIZE 9600
35#define MDIO_ACCESS_TIMEOUT 1000
36#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 37
38/***********************************************************/
3196a88a 39/* Shortcut definitions */
ea4e040a
YR		 40/***********************************************************/
41
2f904460
EG		 42#define NIG_LATCH_BC_ENABLE_MI_INT 0
43
44#define NIG_STATUS_EMAC0_MI_INT \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 46#define NIG_STATUS_XGXS0_LINK10G \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
48#define NIG_STATUS_XGXS0_LINK_STATUS \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
50#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
52#define NIG_STATUS_SERDES0_LINK_STATUS \
53 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
54#define NIG_MASK_MI_INT \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
56#define NIG_MASK_XGXS0_LINK10G \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
58#define NIG_MASK_XGXS0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
60#define NIG_MASK_SERDES0_LINK_STATUS \
61 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
62
63#define MDIO_AN_CL73_OR_37_COMPLETE \
64 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
65 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
66
67#define XGXS_RESET_BITS \
68 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
73
74#define SERDES_RESET_BITS \
75 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
79
80#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
3196a88a
EG		 82#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83#define AUTONEG_PARALLEL \
ea4e040a 84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 85#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 86 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 87#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 88
89#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
91#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
93#define GP_STATUS_SPEED_MASK \
94 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
95#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
96#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
97#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
98#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
99#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
100#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
101#define GP_STATUS_10G_HIG \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
103#define GP_STATUS_10G_CX4 \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
105#define GP_STATUS_12G_HIG \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
107#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
108#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
109#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
110#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
111#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
112#define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
114
115#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
122#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
123#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
138
139#define PHY_XGXS_FLAG 0x1
140#define PHY_SGMII_FLAG 0x2
141#define PHY_SERDES_FLAG 0x4
142
589abe3a
EG		 143/* */
144#define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147
4d295db0
EG		 148
149#define SFP_EEPROM_COMP_CODE_ADDR 0x3
150 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
151 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
152 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
153
589abe3a
EG		 154#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 157
589abe3a
EG		 158#define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160#define SFP_EEPROM_OPTIONS_SIZE 2
161
4d295db0
EG		 162#define EDC_MODE_LINEAR 0x0022
163#define EDC_MODE_LIMITING 0x0044
164#define EDC_MODE_PASSIVE_DAC 0x0055
165
166
bcab15c5
VZ		 167#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
168#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
ea4e040a
YR		 169/**********************************************************/
170/* INTERFACE */
171/**********************************************************/
e10bc84d
YR		 172
173#define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
174 bnx2x_cl45_write(_bp, _phy, \
7aa0711f 175 (_phy)->def_md_devad, \
ea4e040a
YR		 176 (_bank + (_addr & 0xf)), \
177 _val)
178
e10bc84d
YR		 179#define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
180 bnx2x_cl45_read(_bp, _phy, \
7aa0711f 181 (_phy)->def_md_devad, \
ea4e040a
YR		 182 (_bank + (_addr & 0xf)), \
183 _val)
184
8d96286a 185static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
186 u8 devad, u16 reg, u16 *ret_val);
187
188static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
189 u8 devad, u16 reg, u16 val);
190
ea4e040a
YR		 191static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
192{
193 u32 val = REG_RD(bp, reg);
194
195 val |= bits;
196 REG_WR(bp, reg, val);
197 return val;
198}
199
200static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
201{
202 u32 val = REG_RD(bp, reg);
203
204 val &= ~bits;
205 REG_WR(bp, reg, val);
206 return val;
207}
208
bcab15c5
VZ		 209/******************************************************************/
210/* ETS section */
211/******************************************************************/
212void bnx2x_ets_disabled(struct link_params *params)
213{
214 /* ETS disabled configuration*/
215 struct bnx2x *bp = params->bp;
216
217 DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
218
219 /**
220 * mapping between entry priority to client number (0,1,2 -debug and
221 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
222 * 3bits client num.
223 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
224 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
225 */
226
227 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
228 /**
229 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
230 * as strict. Bits 0,1,2 - debug and management entries, 3 -
231 * COS0 entry, 4 - COS1 entry.
232 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
233 * bit4 bit3 bit2 bit1 bit0
234 * MCP and debug are strict
235 */
236
237 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
238 /* defines which entries (clients) are subjected to WFQ arbitration */
239 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
240 /**
241 * For strict priority entries defines the number of consecutive
242 * slots for the highest priority.
243 */
244 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
245 /**
246 * mapping between the CREDIT_WEIGHT registers and actual client
247 * numbers
248 */
249 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
250 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
251 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
252
253 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
254 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
255 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
256 /* ETS mode disable */
257 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
258 /**
259 * If ETS mode is enabled (there is no strict priority) defines a WFQ
260 * weight for COS0/COS1.
261 */
262 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
263 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
264 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
265 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
266 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
267 /* Defines the number of consecutive slots for the strict priority */
268 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
269}
270
271void bnx2x_ets_bw_limit_common(const struct link_params *params)
272{
273 /* ETS disabled configuration */
274 struct bnx2x *bp = params->bp;
275 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
276 /**
277 * defines which entries (clients) are subjected to WFQ arbitration
278 * COS0 0x8
279 * COS1 0x10
280 */
281 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
282 /**
283 * mapping between the ARB_CREDIT_WEIGHT registers and actual
284 * client numbers (WEIGHT_0 does not actually have to represent
285 * client 0)
286 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
287 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
288 */
289 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
290
291 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
292 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
293 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
294 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
295
296 /* ETS mode enabled*/
297 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
298
299 /* Defines the number of consecutive slots for the strict priority */
300 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
301 /**
302 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
303 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
304 * entry, 4 - COS1 entry.
305 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
306 * bit4 bit3 bit2 bit1 bit0
307 * MCP and debug are strict
308 */
309 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
310
311 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
312 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
313 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
314 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
315 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
316}
317
318void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
319 const u32 cos1_bw)
320{
321 /* ETS disabled configuration*/
322 struct bnx2x *bp = params->bp;
323 const u32 total_bw = cos0_bw + cos1_bw;
324 u32 cos0_credit_weight = 0;
325 u32 cos1_credit_weight = 0;
326
327 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
328
329 if ((0 == total_bw) ||
330 (0 == cos0_bw) ||
331 (0 == cos1_bw)) {
332 DP(NETIF_MSG_LINK,
333 "bnx2x_ets_bw_limit: Total BW can't be zero\n");
334 return;
335 }
336
337 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
338 total_bw;
339 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
340 total_bw;
341
342 bnx2x_ets_bw_limit_common(params);
343
344 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
345 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
346
347 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
348 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
349}
350
351u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
352{
353 /* ETS disabled configuration*/
354 struct bnx2x *bp = params->bp;
355 u32 val = 0;
356
bcab15c5
VZ		 357 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
358 /**
359 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
360 * as strict. Bits 0,1,2 - debug and management entries,
361 * 3 - COS0 entry, 4 - COS1 entry.
362 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
363 * bit4 bit3 bit2 bit1 bit0
364 * MCP and debug are strict
365 */
366 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
367 /**
368 * For strict priority entries defines the number of consecutive slots
369 * for the highest priority.
370 */
371 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
372 /* ETS mode disable */
373 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
374 /* Defines the number of consecutive slots for the strict priority */
375 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
376
377 /* Defines the number of consecutive slots for the strict priority */
378 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
379
380 /**
381 * mapping between entry priority to client number (0,1,2 -debug and
382 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
383 * 3bits client num.
384 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
385 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
386 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
387 */
388 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
389 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
390
391 return 0;
392}
393/******************************************************************/
394/* ETS section */
395/******************************************************************/
396
397static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
398 u32 pfc_frames_sent[2],
399 u32 pfc_frames_received[2])
400{
401 /* Read pfc statistic */
402 struct bnx2x *bp = params->bp;
403 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
404 NIG_REG_INGRESS_BMAC0_MEM;
405
406 DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
407
408 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
409 pfc_frames_sent, 2);
410
411 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
412 pfc_frames_received, 2);
413
414}
415static void bnx2x_emac_get_pfc_stat(struct link_params *params,
416 u32 pfc_frames_sent[2],
417 u32 pfc_frames_received[2])
418{
419 /* Read pfc statistic */
420 struct bnx2x *bp = params->bp;
421 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
422 u32 val_xon = 0;
423 u32 val_xoff = 0;
424
425 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
426
427 /* PFC received frames */
428 val_xoff = REG_RD(bp, emac_base +
429 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
430 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
431 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
432 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
433
434 pfc_frames_received[0] = val_xon + val_xoff;
435
436 /* PFC received sent */
437 val_xoff = REG_RD(bp, emac_base +
438 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
439 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
440 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
441 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
442
443 pfc_frames_sent[0] = val_xon + val_xoff;
444}
445
446void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
447 u32 pfc_frames_sent[2],
448 u32 pfc_frames_received[2])
449{
450 /* Read pfc statistic */
451 struct bnx2x *bp = params->bp;
452 u32 val = 0;
453 DP(NETIF_MSG_LINK, "pfc statistic\n");
454
455 if (!vars->link_up)
456 return;
457
458 val = REG_RD(bp, MISC_REG_RESET_REG_2);
459 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
460 == 0) {
461 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
462 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
463 pfc_frames_received);
464 } else {
465 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
466 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
467 pfc_frames_received);
468 }
469}
470/******************************************************************/
471/* MAC/PBF section */
472/******************************************************************/
ea4e040a
YR		 473static void bnx2x_emac_init(struct link_params *params,
474 struct link_vars *vars)
475{
476 /* reset and unreset the emac core */
477 struct bnx2x *bp = params->bp;
478 u8 port = params->port;
479 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
480 u32 val;
481 u16 timeout;
482
483 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
484 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
485 udelay(5);
486 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
487 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
488
489 /* init emac - use read-modify-write */
490 /* self clear reset */
491 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 492 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 493
494 timeout = 200;
3196a88a 495 do {
ea4e040a
YR		 496 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
497 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
498 if (!timeout) {
499 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
500 return;
501 }
502 timeout--;
3196a88a 503 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 504
505 /* Set mac address */
506 val = ((params->mac_addr[0] << 8) |
507 params->mac_addr[1]);
3196a88a 508 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 509
510 val = ((params->mac_addr[2] << 24) |
511 (params->mac_addr[3] << 16) |
512 (params->mac_addr[4] << 8) |
513 params->mac_addr[5]);
3196a88a 514 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 515}
516
517static u8 bnx2x_emac_enable(struct link_params *params,
518 struct link_vars *vars, u8 lb)
519{
520 struct bnx2x *bp = params->bp;
521 u8 port = params->port;
522 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
523 u32 val;
524
525 DP(NETIF_MSG_LINK, "enabling EMAC\n");
526
527 /* enable emac and not bmac */
528 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
529
530 /* for paladium */
531 if (CHIP_REV_IS_EMUL(bp)) {
532 /* Use lane 1 (of lanes 0-3) */
533 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
534 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
535 port*4, 1);
536 }
537 /* for fpga */
538 else
539
540 if (CHIP_REV_IS_FPGA(bp)) {
541 /* Use lane 1 (of lanes 0-3) */
542 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
543
544 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
545 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
546 0);
547 } else
548 /* ASIC */
549 if (vars->phy_flags & PHY_XGXS_FLAG) {
550 u32 ser_lane = ((params->lane_config &
551 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
552 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
553
554 DP(NETIF_MSG_LINK, "XGXS\n");
555 /* select the master lanes (out of 0-3) */
556 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
557 port*4, ser_lane);
558 /* select XGXS */
559 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
560 port*4, 1);
561
562 } else { /* SerDes */
563 DP(NETIF_MSG_LINK, "SerDes\n");
564 /* select SerDes */
565 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
566 port*4, 0);
567 }
568
811a2f2d
EG		 569 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
570 EMAC_RX_MODE_RESET);
571 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
572 EMAC_TX_MODE_RESET);
ea4e040a
YR		 573
574 if (CHIP_REV_IS_SLOW(bp)) {
575 /* config GMII mode */
576 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 577 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
ea4e040a
YR		 578 (val | EMAC_MODE_PORT_GMII));
579 } else { /* ASIC */
580 /* pause enable/disable */
581 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
582 EMAC_RX_MODE_FLOW_EN);
ea4e040a
YR		 583
584 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
bcab15c5
VZ		 585 (EMAC_TX_MODE_EXT_PAUSE_EN |
586 EMAC_TX_MODE_FLOW_EN));
587 if (!(params->feature_config_flags &
588 FEATURE_CONFIG_PFC_ENABLED)) {
589 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
590 bnx2x_bits_en(bp, emac_base +
591 EMAC_REG_EMAC_RX_MODE,
592 EMAC_RX_MODE_FLOW_EN);
593
594 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
595 bnx2x_bits_en(bp, emac_base +
596 EMAC_REG_EMAC_TX_MODE,
597 (EMAC_TX_MODE_EXT_PAUSE_EN |
598 EMAC_TX_MODE_FLOW_EN));
599 } else
600 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
601 EMAC_TX_MODE_FLOW_EN);
ea4e040a
YR		 602 }
603
604 /* KEEP_VLAN_TAG, promiscuous */
605 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
606 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
bcab15c5
VZ		 607
608 /**
609 * Setting this bit causes MAC control frames (except for pause
610 * frames) to be passed on for processing. This setting has no
611 * affect on the operation of the pause frames. This bit effects
612 * all packets regardless of RX Parser packet sorting logic.
613 * Turn the PFC off to make sure we are in Xon state before
614 * enabling it.
615 */
616 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
617 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
618 DP(NETIF_MSG_LINK, "PFC is enabled\n");
619 /* Enable PFC again */
620 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
621 EMAC_REG_RX_PFC_MODE_RX_EN |
622 EMAC_REG_RX_PFC_MODE_TX_EN |
623 EMAC_REG_RX_PFC_MODE_PRIORITIES);
624
625 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
626 ((0x0101 <<
627 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
628 (0x00ff <<
629 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
630 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
631 }
3196a88a 632 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 633
634 /* Set Loopback */
635 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
636 if (lb)
637 val |= 0x810;
638 else
639 val &= ~0x810;
3196a88a 640 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 641
6c55c3cd
EG		 642 /* enable emac */
643 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
644
ea4e040a 645 /* enable emac for jumbo packets */
3196a88a 646 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 647 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
648 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
649
650 /* strip CRC */
651 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
652
653 /* disable the NIG in/out to the bmac */
654 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
655 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
656 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
657
658 /* enable the NIG in/out to the emac */
659 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
660 val = 0;
bcab15c5
VZ		 661 if ((params->feature_config_flags &
662 FEATURE_CONFIG_PFC_ENABLED) ||
663 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 664 val = 1;
665
666 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
667 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
668
669 if (CHIP_REV_IS_EMUL(bp)) {
670 /* take the BigMac out of reset */
671 REG_WR(bp,
672 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
673 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
674
675 /* enable access for bmac registers */
676 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
6f65497b
EG		 677 } else
678 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 679
680 vars->mac_type = MAC_TYPE_EMAC;
681 return 0;
682}
683
bcab15c5
VZ		 684static void bnx2x_update_pfc_bmac1(struct link_params *params,
685 struct link_vars *vars)
686{
687 u32 wb_data[2];
688 struct bnx2x *bp = params->bp;
689 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
690 NIG_REG_INGRESS_BMAC0_MEM;
691
692 u32 val = 0x14;
693 if ((!(params->feature_config_flags &
694 FEATURE_CONFIG_PFC_ENABLED)) &&
695 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
696 /* Enable BigMAC to react on received Pause packets */
697 val |= (1<<5);
698 wb_data[0] = val;
699 wb_data[1] = 0;
700 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
701
702 /* tx control */
703 val = 0xc0;
704 if (!(params->feature_config_flags &
705 FEATURE_CONFIG_PFC_ENABLED) &&
706 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
707 val |= 0x800000;
708 wb_data[0] = val;
709 wb_data[1] = 0;
710 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
711}
712
713static void bnx2x_update_pfc_bmac2(struct link_params *params,
714 struct link_vars *vars,
715 u8 is_lb)
f2e0899f
DK		 716{
717 /*
718 * Set rx control: Strip CRC and enable BigMAC to relay
719 * control packets to the system as well
720 */
721 u32 wb_data[2];
722 struct bnx2x *bp = params->bp;
723 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
724 NIG_REG_INGRESS_BMAC0_MEM;
725 u32 val = 0x14;
ea4e040a 726
bcab15c5
VZ		 727 if ((!(params->feature_config_flags &
728 FEATURE_CONFIG_PFC_ENABLED)) &&
729 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
f2e0899f
DK		 730 /* Enable BigMAC to react on received Pause packets */
731 val |= (1<<5);
732 wb_data[0] = val;
733 wb_data[1] = 0;
734 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL,
735 wb_data, 2);
736 udelay(30);
ea4e040a 737
f2e0899f
DK		 738 /* Tx control */
739 val = 0xc0;
bcab15c5
VZ		 740 if (!(params->feature_config_flags &
741 FEATURE_CONFIG_PFC_ENABLED) &&
742 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
f2e0899f
DK		 743 val |= 0x800000;
744 wb_data[0] = val;
745 wb_data[1] = 0;
bcab15c5
VZ		 746 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
747
748 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
749 DP(NETIF_MSG_LINK, "PFC is enabled\n");
750 /* Enable PFC RX & TX & STATS and set 8 COS */
751 wb_data[0] = 0x0;
752 wb_data[0] |= (1<<0); /* RX */
753 wb_data[0] |= (1<<1); /* TX */
754 wb_data[0] |= (1<<2); /* Force initial Xon */
755 wb_data[0] |= (1<<3); /* 8 cos */
756 wb_data[0] |= (1<<5); /* STATS */
757 wb_data[1] = 0;
758 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
759 wb_data, 2);
760 /* Clear the force Xon */
761 wb_data[0] &= ~(1<<2);
762 } else {
763 DP(NETIF_MSG_LINK, "PFC is disabled\n");
764 /* disable PFC RX & TX & STATS and set 8 COS */
765 wb_data[0] = 0x8;
766 wb_data[1] = 0;
767 }
768
769 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
f2e0899f 770
bcab15c5
VZ		 771 /**
772 * Set Time (based unit is 512 bit time) between automatic
773 * re-sending of PP packets amd enable automatic re-send of
774 * Per-Priroity Packet as long as pp_gen is asserted and
775 * pp_disable is low.
776 */
f2e0899f 777 val = 0x8000;
bcab15c5
VZ		 778 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
779 val |= (1<<16); /* enable automatic re-send */
780
f2e0899f
DK		 781 wb_data[0] = val;
782 wb_data[1] = 0;
783 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
784 wb_data, 2);
785
786 /* mac control */
787 val = 0x3; /* Enable RX and TX */
788 if (is_lb) {
789 val |= 0x4; /* Local loopback */
790 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
791 }
bcab15c5
VZ		 792 /* When PFC enabled, Pass pause frames towards the NIG. */
793 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
794 val |= ((1<<6)|(1<<5));
f2e0899f
DK		 795
796 wb_data[0] = val;
797 wb_data[1] = 0;
798 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
799 wb_data, 2);
800}
801
bcab15c5
VZ		 802static void bnx2x_update_pfc_brb(struct link_params *params,
803 struct link_vars *vars,
804 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
805{
806 struct bnx2x *bp = params->bp;
807 int set_pfc = params->feature_config_flags &
808 FEATURE_CONFIG_PFC_ENABLED;
809
810 /* default - pause configuration */
811 u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
812 u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
813 u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
814 u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
815
816 if (set_pfc && pfc_params)
817 /* First COS */
818 if (!pfc_params->cos0_pauseable) {
819 pause_xoff_th =
820 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
821 pause_xon_th =
822 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
823 full_xoff_th =
824 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
825 full_xon_th =
826 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
827 }
828 /* The number of free blocks below which the pause signal to class 0
829 of MAC #n is asserted. n=0,1 */
830 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
831 /* The number of free blocks above which the pause signal to class 0
832 of MAC #n is de-asserted. n=0,1 */
833 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
834 /* The number of free blocks below which the full signal to class 0
835 of MAC #n is asserted. n=0,1 */
836 REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
837 /* The number of free blocks above which the full signal to class 0
838 of MAC #n is de-asserted. n=0,1 */
839 REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
840
841 if (set_pfc && pfc_params) {
842 /* Second COS */
843 if (pfc_params->cos1_pauseable) {
844 pause_xoff_th =
845 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
846 pause_xon_th =
847 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
848 full_xoff_th =
849 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
850 full_xon_th =
851 PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
852 } else {
853 pause_xoff_th =
854 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
855 pause_xon_th =
856 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
857 full_xoff_th =
858 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
859 full_xon_th =
860 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
861 }
862 /**
863 * The number of free blocks below which the pause signal to
864 * class 1 of MAC #n is asserted. n=0,1
865 **/
866 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
867 /**
868 * The number of free blocks above which the pause signal to
869 * class 1 of MAC #n is de-asserted. n=0,1
870 **/
871 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
872 /**
873 * The number of free blocks below which the full signal to
874 * class 1 of MAC #n is asserted. n=0,1
875 **/
876 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
877 /**
878 * The number of free blocks above which the full signal to
879 * class 1 of MAC #n is de-asserted. n=0,1
880 **/
881 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
882 }
883}
884
885static void bnx2x_update_pfc_nig(struct link_params *params,
886 struct link_vars *vars,
887 struct bnx2x_nig_brb_pfc_port_params *nig_params)
888{
889 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
890 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
891 u32 pkt_priority_to_cos = 0;
892 u32 val;
893 struct bnx2x *bp = params->bp;
894 int port = params->port;
895 int set_pfc = params->feature_config_flags &
896 FEATURE_CONFIG_PFC_ENABLED;
897 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
898
899 /**
900 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
901 * MAC control frames (that are not pause packets)
902 * will be forwarded to the XCM.
903 */
904 xcm_mask = REG_RD(bp,
905 port ? NIG_REG_LLH1_XCM_MASK :
906 NIG_REG_LLH0_XCM_MASK);
907 /**
908 * nig params will override non PFC params, since it's possible to
909 * do transition from PFC to SAFC
910 */
911 if (set_pfc) {
912 pause_enable = 0;
913 llfc_out_en = 0;
914 llfc_enable = 0;
915 ppp_enable = 1;
916 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
917 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
918 xcm0_out_en = 0;
919 p0_hwpfc_enable = 1;
920 } else {
921 if (nig_params) {
922 llfc_out_en = nig_params->llfc_out_en;
923 llfc_enable = nig_params->llfc_enable;
924 pause_enable = nig_params->pause_enable;
925 } else /*defaul non PFC mode - PAUSE */
926 pause_enable = 1;
927
928 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
929 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
930 xcm0_out_en = 1;
931 }
932
933 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
934 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
935 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
936 NIG_REG_LLFC_ENABLE_0, llfc_enable);
937 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
938 NIG_REG_PAUSE_ENABLE_0, pause_enable);
939
940 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
941 NIG_REG_PPP_ENABLE_0, ppp_enable);
942
943 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
944 NIG_REG_LLH0_XCM_MASK, xcm_mask);
945
946 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
947
948 /* output enable for RX_XCM # IF */
949 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
950
951 /* HW PFC TX enable */
952 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
953
954 /* 0x2 = BMAC, 0x1= EMAC */
955 switch (vars->mac_type) {
956 case MAC_TYPE_EMAC:
957 val = 1;
958 break;
959 case MAC_TYPE_BMAC:
960 val = 0;
961 break;
962 default:
963 val = 0;
964 break;
965 }
966 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
967
968 if (nig_params) {
969 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
970
971 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
972 NIG_REG_P0_RX_COS0_PRIORITY_MASK,
973 nig_params->rx_cos0_priority_mask);
974
975 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
976 NIG_REG_P0_RX_COS1_PRIORITY_MASK,
977 nig_params->rx_cos1_priority_mask);
978
979 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
980 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
981 nig_params->llfc_high_priority_classes);
982
983 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
984 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
985 nig_params->llfc_low_priority_classes);
986 }
987 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
988 NIG_REG_P0_PKT_PRIORITY_TO_COS,
989 pkt_priority_to_cos);
990}
991
992
993void bnx2x_update_pfc(struct link_params *params,
994 struct link_vars *vars,
995 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
996{
997 /**
998 * The PFC and pause are orthogonal to one another, meaning when
999 * PFC is enabled, the pause are disabled, and when PFC is
1000 * disabled, pause are set according to the pause result.
1001 */
1002 u32 val;
1003 struct bnx2x *bp = params->bp;
1004
1005 /* update NIG params */
1006 bnx2x_update_pfc_nig(params, vars, pfc_params);
1007
1008 /* update BRB params */
1009 bnx2x_update_pfc_brb(params, vars, pfc_params);
1010
1011 if (!vars->link_up)
1012 return;
1013
1014 val = REG_RD(bp, MISC_REG_RESET_REG_2);
1015 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1016 == 0) {
1017 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
1018 bnx2x_emac_enable(params, vars, 0);
1019 return;
1020 }
1021
1022 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
1023 if (CHIP_IS_E2(bp))
1024 bnx2x_update_pfc_bmac2(params, vars, 0);
1025 else
1026 bnx2x_update_pfc_bmac1(params, vars);
1027
1028 val = 0;
1029 if ((params->feature_config_flags &
1030 FEATURE_CONFIG_PFC_ENABLED) ||
1031 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1032 val = 1;
1033 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1034}
f2e0899f
DK		 1035
1036static u8 bnx2x_bmac1_enable(struct link_params *params,
1037 struct link_vars *vars,
ea4e040a
YR		 1038 u8 is_lb)
1039{
1040 struct bnx2x *bp = params->bp;
1041 u8 port = params->port;
1042 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1043 NIG_REG_INGRESS_BMAC0_MEM;
1044 u32 wb_data[2];
1045 u32 val;
1046
f2e0899f 1047 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
ea4e040a
YR		 1048
1049 /* XGXS control */
1050 wb_data[0] = 0x3c;
1051 wb_data[1] = 0;
1052 REG_WR_DMAE(bp, bmac_addr +
1053 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1054 wb_data, 2);
1055
1056 /* tx MAC SA */
1057 wb_data[0] = ((params->mac_addr[2] << 24) |
1058 (params->mac_addr[3] << 16) |
1059 (params->mac_addr[4] << 8) |
1060 params->mac_addr[5]);
1061 wb_data[1] = ((params->mac_addr[0] << 8) |
1062 params->mac_addr[1]);
1063 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
1064 wb_data, 2);
1065
ea4e040a
YR		 1066 /* mac control */
1067 val = 0x3;
1068 if (is_lb) {
1069 val |= 0x4;
1070 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1071 }
1072 wb_data[0] = val;
1073 wb_data[1] = 0;
1074 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
1075 wb_data, 2);
1076
ea4e040a
YR		 1077 /* set rx mtu */
1078 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1079 wb_data[1] = 0;
1080 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
1081 wb_data, 2);
1082
bcab15c5 1083 bnx2x_update_pfc_bmac1(params, vars);
ea4e040a
YR		 1084
1085 /* set tx mtu */
1086 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1087 wb_data[1] = 0;
1088 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
1089 wb_data, 2);
1090
1091 /* set cnt max size */
1092 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1093 wb_data[1] = 0;
1094 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
1095 wb_data, 2);
1096
1097 /* configure safc */
1098 wb_data[0] = 0x1000200;
1099 wb_data[1] = 0;
1100 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1101 wb_data, 2);
1102 /* fix for emulation */
1103 if (CHIP_REV_IS_EMUL(bp)) {
1104 wb_data[0] = 0xf000;
1105 wb_data[1] = 0;
1106 REG_WR_DMAE(bp,
1107 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
1108 wb_data, 2);
1109 }
1110
f2e0899f
DK		 1111
1112 return 0;
1113}
1114
1115static u8 bnx2x_bmac2_enable(struct link_params *params,
1116 struct link_vars *vars,
1117 u8 is_lb)
1118{
1119 struct bnx2x *bp = params->bp;
1120 u8 port = params->port;
1121 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1122 NIG_REG_INGRESS_BMAC0_MEM;
1123 u32 wb_data[2];
1124
1125 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1126
1127 wb_data[0] = 0;
1128 wb_data[1] = 0;
1129 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
1130 wb_data, 2);
1131 udelay(30);
1132
1133 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1134 wb_data[0] = 0x3c;
1135 wb_data[1] = 0;
1136 REG_WR_DMAE(bp, bmac_addr +
1137 BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1138 wb_data, 2);
1139
1140 udelay(30);
1141
1142 /* tx MAC SA */
1143 wb_data[0] = ((params->mac_addr[2] << 24) |
1144 (params->mac_addr[3] << 16) |
1145 (params->mac_addr[4] << 8) |
1146 params->mac_addr[5]);
1147 wb_data[1] = ((params->mac_addr[0] << 8) |
1148 params->mac_addr[1]);
1149 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1150 wb_data, 2);
1151
1152 udelay(30);
1153
1154 /* Configure SAFC */
1155 wb_data[0] = 0x1000200;
1156 wb_data[1] = 0;
1157 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1158 wb_data, 2);
1159 udelay(30);
1160
1161 /* set rx mtu */
1162 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1163 wb_data[1] = 0;
1164 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE,
1165 wb_data, 2);
1166 udelay(30);
1167
1168 /* set tx mtu */
1169 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1170 wb_data[1] = 0;
1171 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE,
1172 wb_data, 2);
1173 udelay(30);
1174 /* set cnt max size */
1175 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1176 wb_data[1] = 0;
1177 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE,
1178 wb_data, 2);
1179 udelay(30);
bcab15c5 1180 bnx2x_update_pfc_bmac2(params, vars, is_lb);
f2e0899f
DK		 1181
1182 return 0;
1183}
1184
8d96286a 1185static u8 bnx2x_bmac_enable(struct link_params *params,
f2e0899f
DK		 1186 struct link_vars *vars,
1187 u8 is_lb)
1188{
1189 u8 rc, port = params->port;
1190 struct bnx2x *bp = params->bp;
1191 u32 val;
1192 /* reset and unreset the BigMac */
1193 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1194 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1d9c05d4 1195 msleep(1);
f2e0899f
DK		 1196
1197 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1198 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1199
1200 /* enable access for bmac registers */
1201 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1202
1203 /* Enable BMAC according to BMAC type*/
1204 if (CHIP_IS_E2(bp))
1205 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1206 else
1207 rc = bnx2x_bmac1_enable(params, vars, is_lb);
ea4e040a
YR		 1208 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1209 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1210 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1211 val = 0;
bcab15c5
VZ		 1212 if ((params->feature_config_flags &
1213 FEATURE_CONFIG_PFC_ENABLED) ||
1214 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 1215 val = 1;
1216 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1217 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1218 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1219 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1220 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1221 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1222
1223 vars->mac_type = MAC_TYPE_BMAC;
f2e0899f 1224 return rc;
ea4e040a
YR		 1225}
1226
ea4e040a
YR		 1227
1228static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1229{
1230 struct bnx2x *bp = params->bp;
ab6ad5a4 1231
ea4e040a
YR		 1232 REG_WR(bp, params->shmem_base +
1233 offsetof(struct shmem_region,
1234 port_mb[params->port].link_status),
1235 link_status);
1236}
1237
1238static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1239{
1240 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1241 NIG_REG_INGRESS_BMAC0_MEM;
1242 u32 wb_data[2];
3196a88a 1243 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 1244
1245 /* Only if the bmac is out of reset */
1246 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1247 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1248 nig_bmac_enable) {
1249
f2e0899f
DK		 1250 if (CHIP_IS_E2(bp)) {
1251 /* Clear Rx Enable bit in BMAC_CONTROL register */
1252 REG_RD_DMAE(bp, bmac_addr +
1253 BIGMAC2_REGISTER_BMAC_CONTROL,
1254 wb_data, 2);
1255 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1256 REG_WR_DMAE(bp, bmac_addr +
1257 BIGMAC2_REGISTER_BMAC_CONTROL,
1258 wb_data, 2);
1259 } else {
1260 /* Clear Rx Enable bit in BMAC_CONTROL register */
1261 REG_RD_DMAE(bp, bmac_addr +
1262 BIGMAC_REGISTER_BMAC_CONTROL,
1263 wb_data, 2);
1264 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1265 REG_WR_DMAE(bp, bmac_addr +
1266 BIGMAC_REGISTER_BMAC_CONTROL,
1267 wb_data, 2);
1268 }
ea4e040a
YR		 1269 msleep(1);
1270 }
1271}
1272
1273static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1274 u32 line_speed)
1275{
1276 struct bnx2x *bp = params->bp;
1277 u8 port = params->port;
1278 u32 init_crd, crd;
1279 u32 count = 1000;
ea4e040a
YR		 1280
1281 /* disable port */
1282 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1283
1284 /* wait for init credit */
1285 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1286 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1287 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
1288
1289 while ((init_crd != crd) && count) {
1290 msleep(5);
1291
1292 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1293 count--;
1294 }
1295 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1296 if (init_crd != crd) {
1297 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1298 init_crd, crd);
1299 return -EINVAL;
1300 }
1301
c0700f90 1302 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 1303 line_speed == SPEED_10 ||
1304 line_speed == SPEED_100 ||
1305 line_speed == SPEED_1000 ||
1306 line_speed == SPEED_2500) {
1307 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 1308 /* update threshold */
1309 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1310 /* update init credit */
8c99e7b0 1311 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 1312
1313 } else {
1314 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1315 ETH_OVREHEAD)/16;
8c99e7b0 1316 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 1317 /* update threshold */
1318 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1319 /* update init credit */
1320 switch (line_speed) {
ea4e040a
YR		 1321 case SPEED_10000:
1322 init_crd = thresh + 553 - 22;
1323 break;
1324
1325 case SPEED_12000:
1326 init_crd = thresh + 664 - 22;
1327 break;
1328
1329 case SPEED_13000:
1330 init_crd = thresh + 742 - 22;
1331 break;
1332
1333 case SPEED_16000:
1334 init_crd = thresh + 778 - 22;
1335 break;
1336 default:
1337 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1338 line_speed);
1339 return -EINVAL;
ea4e040a
YR		 1340 }
1341 }
1342 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1343 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1344 line_speed, init_crd);
1345
1346 /* probe the credit changes */
1347 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1348 msleep(5);
1349 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1350
1351 /* enable port */
1352 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1353 return 0;
1354}
1355
c18aa15d
YR		 1356static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1357 u32 mdc_mdio_access, u8 port)
ea4e040a 1358{
c18aa15d
YR		 1359 u32 emac_base = 0;
1360 switch (mdc_mdio_access) {
1361 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1362 break;
1363 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1364 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1365 emac_base = GRCBASE_EMAC1;
1366 else
1367 emac_base = GRCBASE_EMAC0;
1368 break;
1369 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
589abe3a
EG		 1370 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1371 emac_base = GRCBASE_EMAC0;
1372 else
1373 emac_base = GRCBASE_EMAC1;
ea4e040a 1374 break;
c18aa15d
YR		 1375 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1376 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1377 break;
1378 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
6378c025 1379 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 1380 break;
1381 default:
ea4e040a
YR		 1382 break;
1383 }
1384 return emac_base;
1385
1386}
1387
e10bc84d
YR		 1388u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1389 u8 devad, u16 reg, u16 val)
ea4e040a
YR		 1390{
1391 u32 tmp, saved_mode;
1392 u8 i, rc = 0;
ea4e040a
YR		 1393
1394 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1395 * (a value of 49==0x31) and make sure that the AUTO poll is off
1396 */
589abe3a 1397
e10bc84d 1398 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1399 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1400 EMAC_MDIO_MODE_CLOCK_CNT);
1401 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1402 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 1403 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1404 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1405 udelay(40);
1406
1407 /* address */
1408
e10bc84d 1409 tmp = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 1410 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1411 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1412 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 1413
1414 for (i = 0; i < 50; i++) {
1415 udelay(10);
1416
e10bc84d
YR		 1417 tmp = REG_RD(bp, phy->mdio_ctrl +
1418 EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1419 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1420 udelay(5);
1421 break;
1422 }
1423 }
1424 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1425 DP(NETIF_MSG_LINK, "write phy register failed\n");
1426 rc = -EFAULT;
1427 } else {
1428 /* data */
e10bc84d 1429 tmp = ((phy->addr << 21) | (devad << 16) | val |
ea4e040a
YR		 1430 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1431 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1432 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 1433
1434 for (i = 0; i < 50; i++) {
1435 udelay(10);
1436
e10bc84d 1437 tmp = REG_RD(bp, phy->mdio_ctrl +
ea4e040a
YR		 1438 EMAC_REG_EMAC_MDIO_COMM);
1439 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1440 udelay(5);
1441 break;
1442 }
1443 }
1444 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1445 DP(NETIF_MSG_LINK, "write phy register failed\n");
1446 rc = -EFAULT;
1447 }
1448 }
1449
1450 /* Restore the saved mode */
e10bc84d 1451 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 1452
1453 return rc;
1454}
1455
e10bc84d
YR		 1456u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1457 u8 devad, u16 reg, u16 *ret_val)
ea4e040a
YR		 1458{
1459 u32 val, saved_mode;
1460 u16 i;
1461 u8 rc = 0;
1462
ea4e040a
YR		 1463 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1464 * (a value of 49==0x31) and make sure that the AUTO poll is off
1465 */
589abe3a 1466
e10bc84d
YR		 1467 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1468 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
ea4e040a
YR		 1469 EMAC_MDIO_MODE_CLOCK_CNT));
1470 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
ab6ad5a4 1471 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 1472 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1473 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1474 udelay(40);
1475
1476 /* address */
e10bc84d 1477 val = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 1478 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1479 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1480 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 1481
1482 for (i = 0; i < 50; i++) {
1483 udelay(10);
1484
e10bc84d 1485 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1486 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1487 udelay(5);
1488 break;
1489 }
1490 }
1491 if (val & EMAC_MDIO_COMM_START_BUSY) {
1492 DP(NETIF_MSG_LINK, "read phy register failed\n");
1493
1494 *ret_val = 0;
1495 rc = -EFAULT;
1496
1497 } else {
1498 /* data */
e10bc84d 1499 val = ((phy->addr << 21) | (devad << 16) |
ea4e040a
YR		 1500 EMAC_MDIO_COMM_COMMAND_READ_45 |
1501 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1502 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 1503
1504 for (i = 0; i < 50; i++) {
1505 udelay(10);
1506
e10bc84d 1507 val = REG_RD(bp, phy->mdio_ctrl +
ea4e040a
YR		 1508 EMAC_REG_EMAC_MDIO_COMM);
1509 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1510 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1511 break;
1512 }
1513 }
1514 if (val & EMAC_MDIO_COMM_START_BUSY) {
1515 DP(NETIF_MSG_LINK, "read phy register failed\n");
1516
1517 *ret_val = 0;
1518 rc = -EFAULT;
1519 }
1520 }
1521
1522 /* Restore the saved mode */
e10bc84d 1523 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 1524
1525 return rc;
1526}
1527
e10bc84d
YR		 1528u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1529 u8 devad, u16 reg, u16 *ret_val)
1530{
1531 u8 phy_index;
1532 /**
1533 * Probe for the phy according to the given phy_addr, and execute
1534 * the read request on it
1535 */
1536 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1537 if (params->phy[phy_index].addr == phy_addr) {
1538 return bnx2x_cl45_read(params->bp,
1539 &params->phy[phy_index], devad,
1540 reg, ret_val);
1541 }
1542 }
1543 return -EINVAL;
1544}
1545
1546u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1547 u8 devad, u16 reg, u16 val)
1548{
1549 u8 phy_index;
1550 /**
1551 * Probe for the phy according to the given phy_addr, and execute
1552 * the write request on it
1553 */
1554 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1555 if (params->phy[phy_index].addr == phy_addr) {
1556 return bnx2x_cl45_write(params->bp,
1557 &params->phy[phy_index], devad,
1558 reg, val);
1559 }
1560 }
1561 return -EINVAL;
1562}
1563
f2e0899f
DK		 1564static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1565 struct bnx2x_phy *phy)
ea4e040a 1566{
ea4e040a 1567 u32 ser_lane;
f2e0899f
DK		 1568 u16 offset, aer_val;
1569 struct bnx2x *bp = params->bp;
ea4e040a
YR		 1570 ser_lane = ((params->lane_config &
1571 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1572 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1573
f2e0899f
DK		 1574 offset = phy->addr + ser_lane;
1575 if (CHIP_IS_E2(bp))
1576 aer_val = 0x2800 + offset - 1;
1577 else
1578 aer_val = 0x3800 + offset;
e10bc84d 1579 CL45_WR_OVER_CL22(bp, phy,
f2e0899f
DK		 1580 MDIO_REG_BANK_AER_BLOCK,
1581 MDIO_AER_BLOCK_AER_REG, aer_val);
1582}
1583static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1584 struct bnx2x_phy *phy)
1585{
1586 CL45_WR_OVER_CL22(bp, phy,
1587 MDIO_REG_BANK_AER_BLOCK,
1588 MDIO_AER_BLOCK_AER_REG, 0x3800);
ea4e040a
YR		 1589}
1590
de6eae1f
YR		 1591/******************************************************************/
1592/* Internal phy section */
1593/******************************************************************/
ea4e040a 1594
de6eae1f
YR		 1595static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1596{
1597 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a 1598
de6eae1f
YR		 1599 /* Set Clause 22 */
1600 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1601 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1602 udelay(500);
1603 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1604 udelay(500);
1605 /* Set Clause 45 */
1606 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
ea4e040a
YR		 1607}
1608
de6eae1f 1609static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
ea4e040a 1610{
de6eae1f 1611 u32 val;
ea4e040a 1612
de6eae1f 1613 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
ea4e040a 1614
de6eae1f 1615 val = SERDES_RESET_BITS << (port*16);
c1b73990 1616
de6eae1f
YR		 1617 /* reset and unreset the SerDes/XGXS */
1618 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1619 udelay(500);
1620 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
ea4e040a 1621
de6eae1f 1622 bnx2x_set_serdes_access(bp, port);
ea4e040a 1623
de6eae1f
YR		 1624 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
1625 port*0x10,
1626 DEFAULT_PHY_DEV_ADDR);
1627}
1628
1629static void bnx2x_xgxs_deassert(struct link_params *params)
1630{
1631 struct bnx2x *bp = params->bp;
1632 u8 port;
1633 u32 val;
1634 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1635 port = params->port;
1636
1637 val = XGXS_RESET_BITS << (port*16);
1638
1639 /* reset and unreset the SerDes/XGXS */
1640 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1641 udelay(500);
1642 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1643
1644 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
1645 port*0x18, 0);
1646 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1647 params->phy[INT_PHY].def_md_devad);
1648}
1649
a22f0788 1650
de6eae1f
YR		 1651void bnx2x_link_status_update(struct link_params *params,
1652 struct link_vars *vars)
1653{
1654 struct bnx2x *bp = params->bp;
1655 u8 link_10g;
1656 u8 port = params->port;
1657
de6eae1f
YR		 1658 vars->link_status = REG_RD(bp, params->shmem_base +
1659 offsetof(struct shmem_region,
1660 port_mb[port].link_status));
1661
1662 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1663
1664 if (vars->link_up) {
1665 DP(NETIF_MSG_LINK, "phy link up\n");
1666
1667 vars->phy_link_up = 1;
1668 vars->duplex = DUPLEX_FULL;
1669 switch (vars->link_status &
1670 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1671 case LINK_10THD:
1672 vars->duplex = DUPLEX_HALF;
1673 /* fall thru */
1674 case LINK_10TFD:
1675 vars->line_speed = SPEED_10;
1676 break;
1677
1678 case LINK_100TXHD:
1679 vars->duplex = DUPLEX_HALF;
1680 /* fall thru */
1681 case LINK_100T4:
1682 case LINK_100TXFD:
1683 vars->line_speed = SPEED_100;
1684 break;
1685
1686 case LINK_1000THD:
1687 vars->duplex = DUPLEX_HALF;
1688 /* fall thru */
1689 case LINK_1000TFD:
1690 vars->line_speed = SPEED_1000;
1691 break;
1692
1693 case LINK_2500THD:
1694 vars->duplex = DUPLEX_HALF;
1695 /* fall thru */
1696 case LINK_2500TFD:
1697 vars->line_speed = SPEED_2500;
1698 break;
1699
1700 case LINK_10GTFD:
1701 vars->line_speed = SPEED_10000;
1702 break;
1703
1704 case LINK_12GTFD:
1705 vars->line_speed = SPEED_12000;
1706 break;
1707
1708 case LINK_12_5GTFD:
1709 vars->line_speed = SPEED_12500;
1710 break;
1711
1712 case LINK_13GTFD:
1713 vars->line_speed = SPEED_13000;
1714 break;
1715
1716 case LINK_15GTFD:
1717 vars->line_speed = SPEED_15000;
1718 break;
1719
1720 case LINK_16GTFD:
1721 vars->line_speed = SPEED_16000;
1722 break;
1723
1724 default:
1725 break;
1726 }
de6eae1f
YR		 1727 vars->flow_ctrl = 0;
1728 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1729 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1730
1731 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1732 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1733
1734 if (!vars->flow_ctrl)
1735 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1736
1737 if (vars->line_speed &&
1738 ((vars->line_speed == SPEED_10) ||
1739 (vars->line_speed == SPEED_100))) {
1740 vars->phy_flags |= PHY_SGMII_FLAG;
1741 } else {
1742 vars->phy_flags &= ~PHY_SGMII_FLAG;
1743 }
1744
1745 /* anything 10 and over uses the bmac */
1746 link_10g = ((vars->line_speed == SPEED_10000) ||
1747 (vars->line_speed == SPEED_12000) ||
1748 (vars->line_speed == SPEED_12500) ||
1749 (vars->line_speed == SPEED_13000) ||
1750 (vars->line_speed == SPEED_15000) ||
1751 (vars->line_speed == SPEED_16000));
1752 if (link_10g)
1753 vars->mac_type = MAC_TYPE_BMAC;
1754 else
1755 vars->mac_type = MAC_TYPE_EMAC;
1756
1757 } else { /* link down */
1758 DP(NETIF_MSG_LINK, "phy link down\n");
1759
1760 vars->phy_link_up = 0;
1761
1762 vars->line_speed = 0;
1763 vars->duplex = DUPLEX_FULL;
1764 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1765
1766 /* indicate no mac active */
1767 vars->mac_type = MAC_TYPE_NONE;
1768 }
1769
1770 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
1771 vars->link_status, vars->phy_link_up);
1772 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
1773 vars->line_speed, vars->duplex, vars->flow_ctrl);
1774}
1775
1776
1777static void bnx2x_set_master_ln(struct link_params *params,
1778 struct bnx2x_phy *phy)
1779{
1780 struct bnx2x *bp = params->bp;
1781 u16 new_master_ln, ser_lane;
1782 ser_lane = ((params->lane_config &
1783 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1784 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1785
1786 /* set the master_ln for AN */
1787 CL45_RD_OVER_CL22(bp, phy,
1788 MDIO_REG_BANK_XGXS_BLOCK2,
1789 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1790 &new_master_ln);
1791
1792 CL45_WR_OVER_CL22(bp, phy,
1793 MDIO_REG_BANK_XGXS_BLOCK2 ,
1794 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1795 (new_master_ln | ser_lane));
1796}
1797
1798static u8 bnx2x_reset_unicore(struct link_params *params,
1799 struct bnx2x_phy *phy,
1800 u8 set_serdes)
1801{
1802 struct bnx2x *bp = params->bp;
1803 u16 mii_control;
1804 u16 i;
1805
1806 CL45_RD_OVER_CL22(bp, phy,
1807 MDIO_REG_BANK_COMBO_IEEE0,
1808 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1809
1810 /* reset the unicore */
1811 CL45_WR_OVER_CL22(bp, phy,
1812 MDIO_REG_BANK_COMBO_IEEE0,
1813 MDIO_COMBO_IEEE0_MII_CONTROL,
1814 (mii_control |
1815 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1816 if (set_serdes)
1817 bnx2x_set_serdes_access(bp, params->port);
1818
1819 /* wait for the reset to self clear */
1820 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1821 udelay(5);
1822
1823 /* the reset erased the previous bank value */
1824 CL45_RD_OVER_CL22(bp, phy,
1825 MDIO_REG_BANK_COMBO_IEEE0,
1826 MDIO_COMBO_IEEE0_MII_CONTROL,
1827 &mii_control);
1828
1829 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1830 udelay(5);
1831 return 0;
1832 }
1833 }
ea4e040a
YR		 1834
1835 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1836 return -EINVAL;
1837
1838}
1839
e10bc84d
YR		 1840static void bnx2x_set_swap_lanes(struct link_params *params,
1841 struct bnx2x_phy *phy)
ea4e040a
YR		 1842{
1843 struct bnx2x *bp = params->bp;
1844 /* Each two bits represents a lane number:
1845 No swap is 0123 => 0x1b no need to enable the swap */
1846 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1847
1848 ser_lane = ((params->lane_config &
1849 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1850 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1851 rx_lane_swap = ((params->lane_config &
1852 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1853 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1854 tx_lane_swap = ((params->lane_config &
1855 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1856 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1857
1858 if (rx_lane_swap != 0x1b) {
e10bc84d 1859 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1860 MDIO_REG_BANK_XGXS_BLOCK2,
1861 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1862 (rx_lane_swap |
1863 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1864 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1865 } else {
e10bc84d 1866 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1867 MDIO_REG_BANK_XGXS_BLOCK2,
1868 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1869 }
1870
1871 if (tx_lane_swap != 0x1b) {
e10bc84d 1872 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1873 MDIO_REG_BANK_XGXS_BLOCK2,
1874 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1875 (tx_lane_swap |
1876 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1877 } else {
e10bc84d 1878 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1879 MDIO_REG_BANK_XGXS_BLOCK2,
1880 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1881 }
1882}
1883
e10bc84d
YR		 1884static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1885 struct link_params *params)
ea4e040a
YR		 1886{
1887 struct bnx2x *bp = params->bp;
1888 u16 control2;
e10bc84d 1889 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1890 MDIO_REG_BANK_SERDES_DIGITAL,
1891 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1892 &control2);
7aa0711f 1893 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
18afb0a6
YR		 1894 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1895 else
1896 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
7aa0711f
YR		 1897 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1898 phy->speed_cap_mask, control2);
e10bc84d 1899 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1900 MDIO_REG_BANK_SERDES_DIGITAL,
1901 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1902 control2);
1903
e10bc84d 1904 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
c18aa15d 1905 (phy->speed_cap_mask &
18afb0a6 1906 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 1907 DP(NETIF_MSG_LINK, "XGXS\n");
1908
e10bc84d 1909 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1910 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1911 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1912 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1913
e10bc84d 1914 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1915 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1916 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1917 &control2);
1918
1919
1920 control2 |=
1921 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1922
e10bc84d 1923 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1924 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1925 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1926 control2);
1927
1928 /* Disable parallel detection of HiG */
e10bc84d 1929 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1930 MDIO_REG_BANK_XGXS_BLOCK2,
1931 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1932 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1933 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1934 }
1935}
1936
e10bc84d
YR		 1937static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1938 struct link_params *params,
239d686d
EG		 1939 struct link_vars *vars,
1940 u8 enable_cl73)
ea4e040a
YR		 1941{
1942 struct bnx2x *bp = params->bp;
1943 u16 reg_val;
1944
1945 /* CL37 Autoneg */
e10bc84d 1946 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1947 MDIO_REG_BANK_COMBO_IEEE0,
1948 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1949
1950 /* CL37 Autoneg Enabled */
8c99e7b0 1951 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1952 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1953 else /* CL37 Autoneg Disabled */
1954 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1955 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1956
e10bc84d 1957 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1958 MDIO_REG_BANK_COMBO_IEEE0,
1959 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1960
1961 /* Enable/Disable Autodetection */
1962
e10bc84d 1963 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1964 MDIO_REG_BANK_SERDES_DIGITAL,
1965 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 1966 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1967 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1968 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 1969 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1970 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1971 else
1972 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1973
e10bc84d 1974 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1975 MDIO_REG_BANK_SERDES_DIGITAL,
1976 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1977
1978 /* Enable TetonII and BAM autoneg */
e10bc84d 1979 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1980 MDIO_REG_BANK_BAM_NEXT_PAGE,
1981 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1982 &reg_val);
8c99e7b0 1983 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1984 /* Enable BAM aneg Mode and TetonII aneg Mode */
1985 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1986 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1987 } else {
1988 /* TetonII and BAM Autoneg Disabled */
1989 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1990 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1991 }
e10bc84d 1992 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1993 MDIO_REG_BANK_BAM_NEXT_PAGE,
1994 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1995 reg_val);
1996
239d686d
EG		 1997 if (enable_cl73) {
1998 /* Enable Cl73 FSM status bits */
e10bc84d 1999 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 2000 MDIO_REG_BANK_CL73_USERB0,
2001 MDIO_CL73_USERB0_CL73_UCTRL,
7846e471 2002 0xe);
239d686d
EG		 2003
2004 /* Enable BAM Station Manager*/
e10bc84d 2005 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 2006 MDIO_REG_BANK_CL73_USERB0,
2007 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2008 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2009 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2010 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
2011
7846e471 2012 /* Advertise CL73 link speeds */
e10bc84d 2013 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 2014 MDIO_REG_BANK_CL73_IEEEB1,
2015 MDIO_CL73_IEEEB1_AN_ADV2,
2016 &reg_val);
7aa0711f 2017 if (phy->speed_cap_mask &
7846e471
YR		 2018 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2019 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
7aa0711f 2020 if (phy->speed_cap_mask &
7846e471
YR		 2021 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2022 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d 2023
e10bc84d 2024 CL45_WR_OVER_CL22(bp, phy,
de6eae1f
YR		 2025 MDIO_REG_BANK_CL73_IEEEB1,
2026 MDIO_CL73_IEEEB1_AN_ADV2,
2027 reg_val);
239d686d 2028
239d686d
EG		 2029 /* CL73 Autoneg Enabled */
2030 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2031
2032 } else /* CL73 Autoneg Disabled */
2033 reg_val = 0;
ea4e040a 2034
e10bc84d 2035 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 2036 MDIO_REG_BANK_CL73_IEEEB0,
2037 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2038}
2039
2040/* program SerDes, forced speed */
e10bc84d
YR		 2041static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2042 struct link_params *params,
8c99e7b0 2043 struct link_vars *vars)
ea4e040a
YR		 2044{
2045 struct bnx2x *bp = params->bp;
2046 u16 reg_val;
2047
57937203 2048 /* program duplex, disable autoneg and sgmii*/
e10bc84d 2049 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 2050 MDIO_REG_BANK_COMBO_IEEE0,
2051 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2052 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 2053 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2054 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
7aa0711f 2055 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a 2056 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
e10bc84d 2057 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 2058 MDIO_REG_BANK_COMBO_IEEE0,
2059 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2060
2061 /* program speed
2062 - needed only if the speed is greater than 1G (2.5G or 10G) */
e10bc84d 2063 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 2064 MDIO_REG_BANK_SERDES_DIGITAL,
2065 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 2066 /* clearing the speed value before setting the right speed */
2067 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2068
2069 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2070 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2071
2072 if (!((vars->line_speed == SPEED_1000) ||
2073 (vars->line_speed == SPEED_100) ||
2074 (vars->line_speed == SPEED_10))) {
2075
ea4e040a
YR		 2076 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2077 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 2078 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 2079 reg_val |=
2080 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 2081 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 2082 reg_val |=
2083 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 2084 }
2085
e10bc84d 2086 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 2087 MDIO_REG_BANK_SERDES_DIGITAL,
2088 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 2089
ea4e040a
YR		 2090}
2091
e10bc84d
YR		 2092static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2093 struct link_params *params)
ea4e040a
YR		 2094{
2095 struct bnx2x *bp = params->bp;
2096 u16 val = 0;
2097
2098 /* configure the 48 bits for BAM AN */
2099
2100 /* set extended capabilities */
7aa0711f 2101 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
ea4e040a 2102 val |= MDIO_OVER_1G_UP1_2_5G;
7aa0711f 2103 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
ea4e040a 2104 val |= MDIO_OVER_1G_UP1_10G;
e10bc84d 2105 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 2106 MDIO_REG_BANK_OVER_1G,
2107 MDIO_OVER_1G_UP1, val);
2108
e10bc84d 2109 CL45_WR_OVER_CL22(bp, phy,
ea4e040a 2110 MDIO_REG_BANK_OVER_1G,
239d686d 2111 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 2112}
2113
e10bc84d
YR		 2114static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2115 struct link_params *params, u16 *ieee_fc)
ea4e040a 2116{
d5cb9e99 2117 struct bnx2x *bp = params->bp;
8c99e7b0 2118 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
ea4e040a
YR		 2119 /* resolve pause mode and advertisement
2120 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
2121
7aa0711f 2122 switch (phy->req_flow_ctrl) {
c0700f90
DM		 2123 case BNX2X_FLOW_CTRL_AUTO:
2124 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
8c99e7b0 2125 *ieee_fc |=
ea4e040a
YR		 2126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2127 } else {
8c99e7b0 2128 *ieee_fc |=
ea4e040a
YR		 2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2130 }
2131 break;
c0700f90 2132 case BNX2X_FLOW_CTRL_TX:
8c99e7b0 2133 *ieee_fc |=
ea4e040a
YR		 2134 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2135 break;
2136
c0700f90
DM		 2137 case BNX2X_FLOW_CTRL_RX:
2138 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 2139 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 2140 break;
2141
c0700f90 2142 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 2143 default:
8c99e7b0 2144 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 2145 break;
2146 }
d5cb9e99 2147 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
8c99e7b0 2148}
ea4e040a 2149
e10bc84d
YR		 2150static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2151 struct link_params *params,
1ef70b9c 2152 u16 ieee_fc)
8c99e7b0
YR		 2153{
2154 struct bnx2x *bp = params->bp;
7846e471 2155 u16 val;
8c99e7b0 2156 /* for AN, we are always publishing full duplex */
ea4e040a 2157
e10bc84d 2158 CL45_WR_OVER_CL22(bp, phy,
ea4e040a 2159 MDIO_REG_BANK_COMBO_IEEE0,
1ef70b9c 2160 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
e10bc84d 2161 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 2162 MDIO_REG_BANK_CL73_IEEEB1,
2163 MDIO_CL73_IEEEB1_AN_ADV1, &val);
2164 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2165 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
e10bc84d 2166 CL45_WR_OVER_CL22(bp, phy,
7846e471
YR		 2167 MDIO_REG_BANK_CL73_IEEEB1,
2168 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 2169}
2170
e10bc84d
YR		 2171static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2172 struct link_params *params,
2173 u8 enable_cl73)
ea4e040a
YR		 2174{
2175 struct bnx2x *bp = params->bp;
3a36f2ef 2176 u16 mii_control;
239d686d 2177
ea4e040a 2178 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 2179 /* Enable and restart BAM/CL37 aneg */
ea4e040a 2180
239d686d 2181 if (enable_cl73) {
e10bc84d 2182 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 2183 MDIO_REG_BANK_CL73_IEEEB0,
2184 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2185 &mii_control);
2186
e10bc84d 2187 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 2188 MDIO_REG_BANK_CL73_IEEEB0,
2189 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2190 (mii_control |
2191 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2192 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2193 } else {
2194
e10bc84d 2195 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 2196 MDIO_REG_BANK_COMBO_IEEE0,
2197 MDIO_COMBO_IEEE0_MII_CONTROL,
2198 &mii_control);
2199 DP(NETIF_MSG_LINK,
2200 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2201 mii_control);
e10bc84d 2202 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 2203 MDIO_REG_BANK_COMBO_IEEE0,
2204 MDIO_COMBO_IEEE0_MII_CONTROL,
2205 (mii_control |
2206 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2207 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2208 }
ea4e040a
YR		 2209}
2210
e10bc84d
YR		 2211static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2212 struct link_params *params,
8c99e7b0 2213 struct link_vars *vars)
ea4e040a
YR		 2214{
2215 struct bnx2x *bp = params->bp;
2216 u16 control1;
2217
2218 /* in SGMII mode, the unicore is always slave */
2219
e10bc84d 2220 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 2221 MDIO_REG_BANK_SERDES_DIGITAL,
2222 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2223 &control1);
2224 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2225 /* set sgmii mode (and not fiber) */
2226 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2227 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2228 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
e10bc84d 2229 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 2230 MDIO_REG_BANK_SERDES_DIGITAL,
2231 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2232 control1);
2233
2234 /* if forced speed */
8c99e7b0 2235 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 2236 /* set speed, disable autoneg */
2237 u16 mii_control;
2238
e10bc84d 2239 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 2240 MDIO_REG_BANK_COMBO_IEEE0,
2241 MDIO_COMBO_IEEE0_MII_CONTROL,
2242 &mii_control);
2243 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2244 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2245 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2246
8c99e7b0 2247 switch (vars->line_speed) {
ea4e040a
YR		 2248 case SPEED_100:
2249 mii_control |=
2250 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2251 break;
2252 case SPEED_1000:
2253 mii_control |=
2254 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2255 break;
2256 case SPEED_10:
2257 /* there is nothing to set for 10M */
2258 break;
2259 default:
2260 /* invalid speed for SGMII */
8c99e7b0
YR		 2261 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2262 vars->line_speed);
ea4e040a
YR		 2263 break;
2264 }
2265
2266 /* setting the full duplex */
7aa0711f 2267 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a
YR		 2268 mii_control |=
2269 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
e10bc84d 2270 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 2271 MDIO_REG_BANK_COMBO_IEEE0,
2272 MDIO_COMBO_IEEE0_MII_CONTROL,
2273 mii_control);
2274
2275 } else { /* AN mode */
2276 /* enable and restart AN */
e10bc84d 2277 bnx2x_restart_autoneg(phy, params, 0);
ea4e040a
YR		 2278 }
2279}
2280
2281
2282/*
2283 * link management
2284 */
2285
2286static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0
YR		 2287{ /* LD LP */
2288 switch (pause_result) { /* ASYM P ASYM P */
2289 case 0xb: /* 1 0 1 1 */
c0700f90 2290 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 2291 break;
2292
8c99e7b0 2293 case 0xe: /* 1 1 1 0 */
c0700f90 2294 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 2295 break;
2296
8c99e7b0
YR		 2297 case 0x5: /* 0 1 0 1 */
2298 case 0x7: /* 0 1 1 1 */
2299 case 0xd: /* 1 1 0 1 */
2300 case 0xf: /* 1 1 1 1 */
c0700f90 2301 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 2302 break;
2303
2304 default:
2305 break;
2306 }
7aa0711f
YR		 2307 if (pause_result & (1<<0))
2308 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2309 if (pause_result & (1<<1))
2310 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
ea4e040a
YR		 2311}
2312
e10bc84d
YR		 2313static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2314 struct link_params *params)
15ddd2d0
YR		 2315{
2316 struct bnx2x *bp = params->bp;
2317 u16 pd_10g, status2_1000x;
7aa0711f
YR		 2318 if (phy->req_line_speed != SPEED_AUTO_NEG)
2319 return 0;
e10bc84d 2320 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 2321 MDIO_REG_BANK_SERDES_DIGITAL,
2322 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2323 &status2_1000x);
e10bc84d 2324 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 2325 MDIO_REG_BANK_SERDES_DIGITAL,
2326 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2327 &status2_1000x);
2328 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2329 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2330 params->port);
2331 return 1;
2332 }
2333
e10bc84d 2334 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 2335 MDIO_REG_BANK_10G_PARALLEL_DETECT,
2336 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2337 &pd_10g);
2338
2339 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2340 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2341 params->port);
2342 return 1;
2343 }
2344 return 0;
2345}
ea4e040a 2346
e10bc84d
YR		 2347static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2348 struct link_params *params,
2349 struct link_vars *vars,
2350 u32 gp_status)
ea4e040a
YR		 2351{
2352 struct bnx2x *bp = params->bp;
3196a88a
EG		 2353 u16 ld_pause; /* local driver */
2354 u16 lp_pause; /* link partner */
ea4e040a
YR		 2355 u16 pause_result;
2356
c0700f90 2357 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 2358
2359 /* resolve from gp_status in case of AN complete and not sgmii */
7aa0711f
YR		 2360 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2361 vars->flow_ctrl = phy->req_flow_ctrl;
2362 else if (phy->req_line_speed != SPEED_AUTO_NEG)
2363 vars->flow_ctrl = params->req_fc_auto_adv;
2364 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2365 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
e10bc84d 2366 if (bnx2x_direct_parallel_detect_used(phy, params)) {
15ddd2d0
YR		 2367 vars->flow_ctrl = params->req_fc_auto_adv;
2368 return;
2369 }
7846e471
YR		 2370 if ((gp_status &
2371 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2372 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2373 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2374 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2375
e10bc84d 2376 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 2377 MDIO_REG_BANK_CL73_IEEEB1,
2378 MDIO_CL73_IEEEB1_AN_ADV1,
2379 &ld_pause);
e10bc84d 2380 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 2381 MDIO_REG_BANK_CL73_IEEEB1,
2382 MDIO_CL73_IEEEB1_AN_LP_ADV1,
2383 &lp_pause);
2384 pause_result = (ld_pause &
2385 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2386 >> 8;
2387 pause_result |= (lp_pause &
2388 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2389 >> 10;
2390 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2391 pause_result);
2392 } else {
e10bc84d 2393 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 2394 MDIO_REG_BANK_COMBO_IEEE0,
2395 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2396 &ld_pause);
e10bc84d 2397 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 2398 MDIO_REG_BANK_COMBO_IEEE0,
2399 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2400 &lp_pause);
2401 pause_result = (ld_pause &
ea4e040a 2402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
7846e471 2403 pause_result |= (lp_pause &
ea4e040a 2404 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
7846e471
YR		 2405 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2406 pause_result);
2407 }
ea4e040a 2408 bnx2x_pause_resolve(vars, pause_result);
ea4e040a
YR		 2409 }
2410 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2411}
2412
e10bc84d
YR		 2413static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2414 struct link_params *params)
239d686d
EG		 2415{
2416 struct bnx2x *bp = params->bp;
2417 u16 rx_status, ustat_val, cl37_fsm_recieved;
2418 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2419 /* Step 1: Make sure signal is detected */
e10bc84d 2420 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 2421 MDIO_REG_BANK_RX0,
2422 MDIO_RX0_RX_STATUS,
2423 &rx_status);
2424 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2425 (MDIO_RX0_RX_STATUS_SIGDET)) {
2426 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2427 "rx_status(0x80b0) = 0x%x\n", rx_status);
e10bc84d 2428 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 2429 MDIO_REG_BANK_CL73_IEEEB0,
2430 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2431 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2432 return;
2433 }
2434 /* Step 2: Check CL73 state machine */
e10bc84d 2435 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 2436 MDIO_REG_BANK_CL73_USERB0,
2437 MDIO_CL73_USERB0_CL73_USTAT1,
2438 &ustat_val);
2439 if ((ustat_val &
2440 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2441 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2442 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2443 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2444 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2445 "ustat_val(0x8371) = 0x%x\n", ustat_val);
2446 return;
2447 }
2448 /* Step 3: Check CL37 Message Pages received to indicate LP
2449 supports only CL37 */
e10bc84d 2450 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 2451 MDIO_REG_BANK_REMOTE_PHY,
2452 MDIO_REMOTE_PHY_MISC_RX_STATUS,
2453 &cl37_fsm_recieved);
2454 if ((cl37_fsm_recieved &
2455 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2456 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2457 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2458 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2459 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2460 "misc_rx_status(0x8330) = 0x%x\n",
2461 cl37_fsm_recieved);
2462 return;
2463 }
2464 /* The combined cl37/cl73 fsm state information indicating that we are
2465 connected to a device which does not support cl73, but does support
2466 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
2467 /* Disable CL73 */
e10bc84d 2468 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 2469 MDIO_REG_BANK_CL73_IEEEB0,
2470 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2471 0);
2472 /* Restart CL37 autoneg */
e10bc84d 2473 bnx2x_restart_autoneg(phy, params, 0);
239d686d
EG		 2474 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2475}
7aa0711f
YR		 2476
2477static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2478 struct link_params *params,
2479 struct link_vars *vars,
2480 u32 gp_status)
2481{
2482 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2483 vars->link_status |=
2484 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2485
2486 if (bnx2x_direct_parallel_detect_used(phy, params))
2487 vars->link_status |=
2488 LINK_STATUS_PARALLEL_DETECTION_USED;
2489}
2490
b7737c9b
YR		 2491static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2492 struct link_params *params,
2493 struct link_vars *vars)
ea4e040a
YR		 2494{
2495 struct bnx2x *bp = params->bp;
b7737c9b 2496 u16 new_line_speed , gp_status;
ea4e040a 2497 u8 rc = 0;
c18aa15d 2498
b7737c9b
YR		 2499 /* Read gp_status */
2500 CL45_RD_OVER_CL22(bp, phy,
2501 MDIO_REG_BANK_GP_STATUS,
2502 MDIO_GP_STATUS_TOP_AN_STATUS1,
2503 &gp_status);
7f02c4ad 2504
7aa0711f
YR		 2505 if (phy->req_line_speed == SPEED_AUTO_NEG)
2506 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
ea4e040a
YR		 2507 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2508 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2509 gp_status);
2510
2511 vars->phy_link_up = 1;
2512 vars->link_status |= LINK_STATUS_LINK_UP;
2513
2514 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2515 vars->duplex = DUPLEX_FULL;
2516 else
2517 vars->duplex = DUPLEX_HALF;
2518
7aa0711f
YR		 2519 if (SINGLE_MEDIA_DIRECT(params)) {
2520 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2521 if (phy->req_line_speed == SPEED_AUTO_NEG)
2522 bnx2x_xgxs_an_resolve(phy, params, vars,
2523 gp_status);
2524 }
ea4e040a
YR		 2525
2526 switch (gp_status & GP_STATUS_SPEED_MASK) {
2527 case GP_STATUS_10M:
6c55c3cd 2528 new_line_speed = SPEED_10;
ea4e040a
YR		 2529 if (vars->duplex == DUPLEX_FULL)
2530 vars->link_status |= LINK_10TFD;
2531 else
2532 vars->link_status |= LINK_10THD;
2533 break;
2534
2535 case GP_STATUS_100M:
6c55c3cd 2536 new_line_speed = SPEED_100;
ea4e040a
YR		 2537 if (vars->duplex == DUPLEX_FULL)
2538 vars->link_status |= LINK_100TXFD;
2539 else
2540 vars->link_status |= LINK_100TXHD;
2541 break;
2542
2543 case GP_STATUS_1G:
2544 case GP_STATUS_1G_KX:
6c55c3cd 2545 new_line_speed = SPEED_1000;
ea4e040a
YR		 2546 if (vars->duplex == DUPLEX_FULL)
2547 vars->link_status |= LINK_1000TFD;
2548 else
2549 vars->link_status |= LINK_1000THD;
2550 break;
2551
2552 case GP_STATUS_2_5G:
6c55c3cd 2553 new_line_speed = SPEED_2500;
ea4e040a
YR		 2554 if (vars->duplex == DUPLEX_FULL)
2555 vars->link_status |= LINK_2500TFD;
2556 else
2557 vars->link_status |= LINK_2500THD;
2558 break;
2559
2560 case GP_STATUS_5G:
2561 case GP_STATUS_6G:
2562 DP(NETIF_MSG_LINK,
2563 "link speed unsupported gp_status 0x%x\n",
2564 gp_status);
2565 return -EINVAL;
ab6ad5a4 2566
ea4e040a
YR		 2567 case GP_STATUS_10G_KX4:
2568 case GP_STATUS_10G_HIG:
2569 case GP_STATUS_10G_CX4:
6c55c3cd 2570 new_line_speed = SPEED_10000;
ea4e040a
YR		 2571 vars->link_status |= LINK_10GTFD;
2572 break;
2573
2574 case GP_STATUS_12G_HIG:
6c55c3cd 2575 new_line_speed = SPEED_12000;
ea4e040a
YR		 2576 vars->link_status |= LINK_12GTFD;
2577 break;
2578
2579 case GP_STATUS_12_5G:
6c55c3cd 2580 new_line_speed = SPEED_12500;
ea4e040a
YR		 2581 vars->link_status |= LINK_12_5GTFD;
2582 break;
2583
2584 case GP_STATUS_13G:
6c55c3cd 2585 new_line_speed = SPEED_13000;
ea4e040a
YR		 2586 vars->link_status |= LINK_13GTFD;
2587 break;
2588
2589 case GP_STATUS_15G:
6c55c3cd 2590 new_line_speed = SPEED_15000;
ea4e040a
YR		 2591 vars->link_status |= LINK_15GTFD;
2592 break;
2593
2594 case GP_STATUS_16G:
6c55c3cd 2595 new_line_speed = SPEED_16000;
ea4e040a
YR		 2596 vars->link_status |= LINK_16GTFD;
2597 break;
2598
2599 default:
2600 DP(NETIF_MSG_LINK,
2601 "link speed unsupported gp_status 0x%x\n",
2602 gp_status);
ab6ad5a4 2603 return -EINVAL;
ea4e040a
YR		 2604 }
2605
6c55c3cd 2606 vars->line_speed = new_line_speed;
ea4e040a 2607
ea4e040a
YR		 2608 } else { /* link_down */
2609 DP(NETIF_MSG_LINK, "phy link down\n");
2610
2611 vars->phy_link_up = 0;
57963ed9 2612
ea4e040a 2613 vars->duplex = DUPLEX_FULL;
c0700f90 2614 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 2615 vars->mac_type = MAC_TYPE_NONE;
239d686d 2616
c18aa15d
YR		 2617 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2618 SINGLE_MEDIA_DIRECT(params)) {
239d686d 2619 /* Check signal is detected */
c18aa15d 2620 bnx2x_check_fallback_to_cl37(phy, params);
239d686d 2621 }
ea4e040a
YR		 2622 }
2623
2381a55c 2624 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
ea4e040a 2625 gp_status, vars->phy_link_up, vars->line_speed);
a22f0788
YR		 2626 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
2627 vars->duplex, vars->flow_ctrl, vars->link_status);
ea4e040a
YR		 2628 return rc;
2629}
2630
ed8680a7 2631static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 2632{
2633 struct bnx2x *bp = params->bp;
e10bc84d 2634 struct bnx2x_phy *phy = &params->phy[INT_PHY];
ea4e040a
YR		 2635 u16 lp_up2;
2636 u16 tx_driver;
c2c8b03e 2637 u16 bank;
ea4e040a
YR		 2638
2639 /* read precomp */
e10bc84d 2640 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 2641 MDIO_REG_BANK_OVER_1G,
2642 MDIO_OVER_1G_LP_UP2, &lp_up2);
2643
ea4e040a
YR		 2644 /* bits [10:7] at lp_up2, positioned at [15:12] */
2645 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2646 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2647 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2648
c2c8b03e
EG		 2649 if (lp_up2 == 0)
2650 return;
2651
2652 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2653 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
e10bc84d 2654 CL45_RD_OVER_CL22(bp, phy,
c2c8b03e
EG		 2655 bank,
2656 MDIO_TX0_TX_DRIVER, &tx_driver);
2657
2658 /* replace tx_driver bits [15:12] */
2659 if (lp_up2 !=
2660 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2661 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2662 tx_driver |= lp_up2;
e10bc84d 2663 CL45_WR_OVER_CL22(bp, phy,
c2c8b03e
EG		 2664 bank,
2665 MDIO_TX0_TX_DRIVER, tx_driver);
2666 }
ea4e040a
YR		 2667 }
2668}
2669
2670static u8 bnx2x_emac_program(struct link_params *params,
b7737c9b 2671 struct link_vars *vars)
ea4e040a
YR		 2672{
2673 struct bnx2x *bp = params->bp;
2674 u8 port = params->port;
2675 u16 mode = 0;
2676
2677 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2678 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2679 EMAC_REG_EMAC_MODE,
2680 (EMAC_MODE_25G_MODE |
2681 EMAC_MODE_PORT_MII_10M |
2682 EMAC_MODE_HALF_DUPLEX));
b7737c9b 2683 switch (vars->line_speed) {
ea4e040a
YR		 2684 case SPEED_10:
2685 mode |= EMAC_MODE_PORT_MII_10M;
2686 break;
2687
2688 case SPEED_100:
2689 mode |= EMAC_MODE_PORT_MII;
2690 break;
2691
2692 case SPEED_1000:
2693 mode |= EMAC_MODE_PORT_GMII;
2694 break;
2695
2696 case SPEED_2500:
2697 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2698 break;
2699
2700 default:
2701 /* 10G not valid for EMAC */
b7737c9b
YR		 2702 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2703 vars->line_speed);
ea4e040a
YR		 2704 return -EINVAL;
2705 }
2706
b7737c9b 2707 if (vars->duplex == DUPLEX_HALF)
ea4e040a
YR		 2708 mode |= EMAC_MODE_HALF_DUPLEX;
2709 bnx2x_bits_en(bp,
2710 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2711 mode);
2712
7f02c4ad 2713 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 2714 return 0;
2715}
2716
de6eae1f
YR		 2717static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2718 struct link_params *params)
b7737c9b 2719{
de6eae1f
YR		 2720
2721 u16 bank, i = 0;
2722 struct bnx2x *bp = params->bp;
2723
2724 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2725 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2726 CL45_WR_OVER_CL22(bp, phy,
2727 bank,
2728 MDIO_RX0_RX_EQ_BOOST,
2729 phy->rx_preemphasis[i]);
2730 }
2731
2732 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2733 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2734 CL45_WR_OVER_CL22(bp, phy,
2735 bank,
2736 MDIO_TX0_TX_DRIVER,
2737 phy->tx_preemphasis[i]);
2738 }
2739}
2740
2741static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2742 struct link_params *params,
2743 struct link_vars *vars)
2744{
2745 struct bnx2x *bp = params->bp;
2746 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2747 (params->loopback_mode == LOOPBACK_XGXS));
2748 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2749 if (SINGLE_MEDIA_DIRECT(params) &&
2750 (params->feature_config_flags &
2751 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2752 bnx2x_set_preemphasis(phy, params);
2753
2754 /* forced speed requested? */
2755 if (vars->line_speed != SPEED_AUTO_NEG ||
2756 (SINGLE_MEDIA_DIRECT(params) &&
2757 params->loopback_mode == LOOPBACK_EXT)) {
2758 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2759
2760 /* disable autoneg */
2761 bnx2x_set_autoneg(phy, params, vars, 0);
2762
2763 /* program speed and duplex */
2764 bnx2x_program_serdes(phy, params, vars);
2765
2766 } else { /* AN_mode */
2767 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2768
2769 /* AN enabled */
2770 bnx2x_set_brcm_cl37_advertisment(phy, params);
2771
2772 /* program duplex & pause advertisement (for aneg) */
2773 bnx2x_set_ieee_aneg_advertisment(phy, params,
2774 vars->ieee_fc);
2775
2776 /* enable autoneg */
2777 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2778
2779 /* enable and restart AN */
2780 bnx2x_restart_autoneg(phy, params, enable_cl73);
2781 }
2782
2783 } else { /* SGMII mode */
2784 DP(NETIF_MSG_LINK, "SGMII\n");
2785
2786 bnx2x_initialize_sgmii_process(phy, params, vars);
2787 }
2788}
2789
2790static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2791 struct link_params *params,
2792 struct link_vars *vars)
2793{
2794 u8 rc;
2795 vars->phy_flags |= PHY_SGMII_FLAG;
b7737c9b 2796 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
f2e0899f 2797 bnx2x_set_aer_mmd_serdes(params->bp, phy);
b7737c9b
YR		 2798 rc = bnx2x_reset_unicore(params, phy, 1);
2799 /* reset the SerDes and wait for reset bit return low */
2800 if (rc != 0)
2801 return rc;
f2e0899f 2802 bnx2x_set_aer_mmd_serdes(params->bp, phy);
b7737c9b
YR		 2803
2804 return rc;
2805}
2806
2807static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2808 struct link_params *params,
2809 struct link_vars *vars)
2810{
2811 u8 rc;
2812 vars->phy_flags = PHY_XGXS_FLAG;
2813 if ((phy->req_line_speed &&
2814 ((phy->req_line_speed == SPEED_100) ||
2815 (phy->req_line_speed == SPEED_10))) ||
2816 (!phy->req_line_speed &&
2817 (phy->speed_cap_mask >=
2818 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2819 (phy->speed_cap_mask <
2820 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2821 ))
2822 vars->phy_flags |= PHY_SGMII_FLAG;
2823 else
2824 vars->phy_flags &= ~PHY_SGMII_FLAG;
2825
2826 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
f2e0899f 2827 bnx2x_set_aer_mmd_xgxs(params, phy);
b7737c9b
YR		 2828 bnx2x_set_master_ln(params, phy);
2829
2830 rc = bnx2x_reset_unicore(params, phy, 0);
2831 /* reset the SerDes and wait for reset bit return low */
2832 if (rc != 0)
2833 return rc;
2834
f2e0899f 2835 bnx2x_set_aer_mmd_xgxs(params, phy);
e10bc84d 2836
b7737c9b
YR		 2837 /* setting the masterLn_def again after the reset */
2838 bnx2x_set_master_ln(params, phy);
2839 bnx2x_set_swap_lanes(params, phy);
2840
2841 return rc;
2842}
c18aa15d 2843
de6eae1f
YR		 2844static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2845 struct bnx2x_phy *phy)
ea4e040a 2846{
de6eae1f
YR		 2847 u16 cnt, ctrl;
2848 /* Wait for soft reset to get cleared upto 1 sec */
2849 for (cnt = 0; cnt < 1000; cnt++) {
2850 bnx2x_cl45_read(bp, phy,
2851 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2852 if (!(ctrl & (1<<15)))
2853 break;
2854 msleep(1);
2855 }
2856 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2857 return cnt;
ea4e040a
YR		 2858}
2859
de6eae1f 2860static void bnx2x_link_int_enable(struct link_params *params)
a35da8db 2861{
de6eae1f
YR		 2862 u8 port = params->port;
2863 u32 mask;
2864 struct bnx2x *bp = params->bp;
c18aa15d 2865
de6eae1f
YR		 2866 /* setting the status to report on link up
2867 for either XGXS or SerDes */
2868
2869 if (params->switch_cfg == SWITCH_CFG_10G) {
2870 mask = (NIG_MASK_XGXS0_LINK10G |
2871 NIG_MASK_XGXS0_LINK_STATUS);
2872 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2873 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2874 params->phy[INT_PHY].type !=
2875 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2876 mask |= NIG_MASK_MI_INT;
2877 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2878 }
2879
2880 } else { /* SerDes */
2881 mask = NIG_MASK_SERDES0_LINK_STATUS;
2882 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2883 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2884 params->phy[INT_PHY].type !=
2885 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2886 mask |= NIG_MASK_MI_INT;
2887 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2888 }
2889 }
2890 bnx2x_bits_en(bp,
2891 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2892 mask);
2893
2894 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2895 (params->switch_cfg == SWITCH_CFG_10G),
2896 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2897 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2898 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2899 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2900 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2901 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2902 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2903 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
a35da8db
EG		 2904}
2905
a22f0788
YR		 2906static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2907 u8 exp_mi_int)
a35da8db 2908{
a22f0788
YR		 2909 u32 latch_status = 0;
2910
2911 /**
2912 * Disable the MI INT ( external phy int ) by writing 1 to the
2913 * status register. Link down indication is high-active-signal,
2914 * so in this case we need to write the status to clear the XOR
de6eae1f
YR		 2915 */
2916 /* Read Latched signals */
2917 latch_status = REG_RD(bp,
a22f0788
YR		 2918 NIG_REG_LATCH_STATUS_0 + port*8);
2919 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
de6eae1f 2920 /* Handle only those with latched-signal=up.*/
a22f0788
YR		 2921 if (exp_mi_int)
2922 bnx2x_bits_en(bp,
2923 NIG_REG_STATUS_INTERRUPT_PORT0
2924 + port*4,
2925 NIG_STATUS_EMAC0_MI_INT);
2926 else
2927 bnx2x_bits_dis(bp,
2928 NIG_REG_STATUS_INTERRUPT_PORT0
2929 + port*4,
2930 NIG_STATUS_EMAC0_MI_INT);
2931
de6eae1f 2932 if (latch_status & 1) {
a22f0788 2933
de6eae1f
YR		 2934 /* For all latched-signal=up : Re-Arm Latch signals */
2935 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
7f02c4ad 2936 (latch_status & 0xfffe) | (latch_status & 1));
de6eae1f 2937 }
a22f0788 2938 /* For all latched-signal=up,Write original_signal to status */
a35da8db
EG		 2939}
2940
de6eae1f 2941static void bnx2x_link_int_ack(struct link_params *params,
a22f0788 2942 struct link_vars *vars, u8 is_10g)
b1607af5 2943{
e10bc84d 2944 struct bnx2x *bp = params->bp;
de6eae1f 2945 u8 port = params->port;
e10bc84d 2946
de6eae1f
YR		 2947 /* first reset all status
2948 * we assume only one line will be change at a time */
2949 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2950 (NIG_STATUS_XGXS0_LINK10G |
2951 NIG_STATUS_XGXS0_LINK_STATUS |
2952 NIG_STATUS_SERDES0_LINK_STATUS));
de6eae1f
YR		 2953 if (vars->phy_link_up) {
2954 if (is_10g) {
2955 /* Disable the 10G link interrupt
2956 * by writing 1 to the status register
2957 */
2958 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2959 bnx2x_bits_en(bp,
2960 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2961 NIG_STATUS_XGXS0_LINK10G);
b1607af5 2962
de6eae1f
YR		 2963 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2964 /* Disable the link interrupt
2965 * by writing 1 to the relevant lane
2966 * in the status register
2967 */
2968 u32 ser_lane = ((params->lane_config &
2969 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2970 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
b1607af5 2971
de6eae1f
YR		 2972 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2973 vars->line_speed);
2974 bnx2x_bits_en(bp,
2975 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2976 ((1 << ser_lane) <<
2977 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
ea4e040a 2978
de6eae1f
YR		 2979 } else { /* SerDes */
2980 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2981 /* Disable the link interrupt
2982 * by writing 1 to the status register
2983 */
2984 bnx2x_bits_en(bp,
2985 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2986 NIG_STATUS_SERDES0_LINK_STATUS);
2987 }
ea4e040a 2988
ea4e040a 2989 }
ea4e040a 2990}
ea4e040a 2991
de6eae1f
YR		 2992static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2993{
2994 u8 *str_ptr = str;
2995 u32 mask = 0xf0000000;
2996 u8 shift = 8*4;
2997 u8 digit;
a22f0788 2998 u8 remove_leading_zeros = 1;
de6eae1f
YR		 2999 if (*len < 10) {
3000 /* Need more than 10chars for this format */
3001 *str_ptr = '\0';
a22f0788 3002 (*len)--;
de6eae1f 3003 return -EINVAL;
ea4e040a 3004 }
de6eae1f 3005 while (shift > 0) {
ea4e040a 3006
de6eae1f
YR		 3007 shift -= 4;
3008 digit = ((num & mask) >> shift);
a22f0788
YR		 3009 if (digit == 0 && remove_leading_zeros) {
3010 mask = mask >> 4;
3011 continue;
3012 } else if (digit < 0xa)
de6eae1f
YR		 3013 *str_ptr = digit + '0';
3014 else
3015 *str_ptr = digit - 0xa + 'a';
a22f0788 3016 remove_leading_zeros = 0;
de6eae1f 3017 str_ptr++;
a22f0788 3018 (*len)--;
de6eae1f
YR		 3019 mask = mask >> 4;
3020 if (shift == 4*4) {
a22f0788 3021 *str_ptr = '.';
de6eae1f 3022 str_ptr++;
a22f0788
YR		 3023 (*len)--;
3024 remove_leading_zeros = 1;
ea4e040a 3025 }
ea4e040a 3026 }
de6eae1f 3027 return 0;
ea4e040a
YR		 3028}
3029
a22f0788 3030
de6eae1f 3031static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
ea4e040a 3032{
de6eae1f
YR		 3033 str[0] = '\0';
3034 (*len)--;
3035 return 0;
3036}
ea4e040a 3037
de6eae1f
YR		 3038u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3039 u8 *version, u16 len)
3040{
3041 struct bnx2x *bp;
3042 u32 spirom_ver = 0;
3043 u8 status = 0;
3044 u8 *ver_p = version;
a22f0788 3045 u16 remain_len = len;
de6eae1f
YR		 3046 if (version == NULL || params == NULL)
3047 return -EINVAL;
3048 bp = params->bp;
ea4e040a 3049
de6eae1f
YR		 3050 /* Extract first external phy*/
3051 version[0] = '\0';
3052 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
ea4e040a 3053
a22f0788 3054 if (params->phy[EXT_PHY1].format_fw_ver) {
de6eae1f
YR		 3055 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3056 ver_p,
a22f0788
YR		 3057 &remain_len);
3058 ver_p += (len - remain_len);
3059 }
3060 if ((params->num_phys == MAX_PHYS) &&
3061 (params->phy[EXT_PHY2].ver_addr != 0)) {
3062 spirom_ver = REG_RD(bp,
3063 params->phy[EXT_PHY2].ver_addr);
3064 if (params->phy[EXT_PHY2].format_fw_ver) {
3065 *ver_p = '/';
3066 ver_p++;
3067 remain_len--;
3068 status |= params->phy[EXT_PHY2].format_fw_ver(
3069 spirom_ver,
3070 ver_p,
3071 &remain_len);
3072 ver_p = version + (len - remain_len);
3073 }
3074 }
3075 *ver_p = '\0';
de6eae1f 3076 return status;
6bbca910 3077}
ea4e040a 3078
de6eae1f
YR		 3079static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3080 struct link_params *params)
589abe3a 3081{
de6eae1f 3082 u8 port = params->port;
589abe3a 3083 struct bnx2x *bp = params->bp;
589abe3a 3084
de6eae1f
YR		 3085 if (phy->req_line_speed != SPEED_1000) {
3086 u32 md_devad;
589abe3a 3087
de6eae1f 3088 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
589abe3a 3089
de6eae1f
YR		 3090 /* change the uni_phy_addr in the nig */
3091 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3092 port*0x18));
cc1cb004 3093
de6eae1f 3094 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
589abe3a 3095
de6eae1f
YR		 3096 bnx2x_cl45_write(bp, phy,
3097 5,
3098 (MDIO_REG_BANK_AER_BLOCK +
3099 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3100 0x2800);
589abe3a 3101
de6eae1f
YR		 3102 bnx2x_cl45_write(bp, phy,
3103 5,
3104 (MDIO_REG_BANK_CL73_IEEEB0 +
3105 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3106 0x6041);
3107 msleep(200);
3108 /* set aer mmd back */
f2e0899f 3109 bnx2x_set_aer_mmd_xgxs(params, phy);
589abe3a 3110
de6eae1f
YR		 3111 /* and md_devad */
3112 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3113 md_devad);
3114
3115 } else {
3116 u16 mii_ctrl;
3117 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3118 bnx2x_cl45_read(bp, phy, 5,
3119 (MDIO_REG_BANK_COMBO_IEEE0 +
3120 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3121 &mii_ctrl);
3122 bnx2x_cl45_write(bp, phy, 5,
3123 (MDIO_REG_BANK_COMBO_IEEE0 +
3124 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3125 mii_ctrl |
3126 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3127 }
589abe3a
EG		 3128}
3129
7f02c4ad
YR		 3130u8 bnx2x_set_led(struct link_params *params,
3131 struct link_vars *vars, u8 mode, u32 speed)
4d295db0 3132{
de6eae1f
YR		 3133 u8 port = params->port;
3134 u16 hw_led_mode = params->hw_led_mode;
7f02c4ad 3135 u8 rc = 0, phy_idx;
de6eae1f
YR		 3136 u32 tmp;
3137 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
589abe3a 3138 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3139 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3140 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3141 speed, hw_led_mode);
7f02c4ad
YR		 3142 /* In case */
3143 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3144 if (params->phy[phy_idx].set_link_led) {
3145 params->phy[phy_idx].set_link_led(
3146 &params->phy[phy_idx], params, mode);
3147 }
3148 }
3149
de6eae1f 3150 switch (mode) {
7f02c4ad 3151 case LED_MODE_FRONT_PANEL_OFF:
de6eae1f
YR		 3152 case LED_MODE_OFF:
3153 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3154 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3155 SHARED_HW_CFG_LED_MAC1);
589abe3a 3156
de6eae1f
YR		 3157 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3158 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3159 break;
589abe3a 3160
de6eae1f 3161 case LED_MODE_OPER:
7f02c4ad
YR		 3162 /**
3163 * For all other phys, OPER mode is same as ON, so in case
3164 * link is down, do nothing
3165 **/
3166 if (!vars->link_up)
3167 break;
3168 case LED_MODE_ON:
1f48353a
YR		 3169 if (params->phy[EXT_PHY1].type ==
3170 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 &&
3171 CHIP_IS_E2(bp) && params->num_phys == 2) {
3172 /**
3173 * This is a work-around for E2+8727 Configurations
3174 */
3175 if (mode == LED_MODE_ON ||
3176 speed == SPEED_10000){
3177 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3178 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3179
3180 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3181 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3182 (tmp | EMAC_LED_OVERRIDE));
3183 return rc;
3184 }
3185 } else if (SINGLE_MEDIA_DIRECT(params)) {
7f02c4ad
YR		 3186 /**
3187 * This is a work-around for HW issue found when link
3188 * is up in CL73
3189 */
de6eae1f
YR		 3190 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3191 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3192 } else {
3193 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3194 hw_led_mode);
3195 }
589abe3a 3196
de6eae1f
YR		 3197 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
3198 port*4, 0);
3199 /* Set blinking rate to ~15.9Hz */
3200 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3201 LED_BLINK_RATE_VAL);
3202 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3203 port*4, 1);
3204 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3205 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3206 (tmp & (~EMAC_LED_OVERRIDE)));
589abe3a 3207
de6eae1f
YR		 3208 if (CHIP_IS_E1(bp) &&
3209 ((speed == SPEED_2500) ||
3210 (speed == SPEED_1000) ||
3211 (speed == SPEED_100) ||
3212 (speed == SPEED_10))) {
3213 /* On Everest 1 Ax chip versions for speeds less than
3214 10G LED scheme is different */
3215 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3216 + port*4, 1);
3217 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3218 port*4, 0);
3219 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3220 port*4, 1);
3221 }
3222 break;
589abe3a 3223
de6eae1f
YR		 3224 default:
3225 rc = -EINVAL;
3226 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3227 mode);
3228 break;
589abe3a 3229 }
de6eae1f 3230 return rc;
589abe3a 3231
4d295db0
EG		 3232}
3233
a22f0788
YR		 3234/**
3235 * This function comes to reflect the actual link state read DIRECTLY from the
3236 * HW
3237 */
3238u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3239 u8 is_serdes)
4d295db0
EG		 3240{
3241 struct bnx2x *bp = params->bp;
de6eae1f 3242 u16 gp_status = 0, phy_index = 0;
a22f0788
YR		 3243 u8 ext_phy_link_up = 0, serdes_phy_type;
3244 struct link_vars temp_vars;
4d295db0 3245
de6eae1f
YR		 3246 CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
3247 MDIO_REG_BANK_GP_STATUS,
3248 MDIO_GP_STATUS_TOP_AN_STATUS1,
3249 &gp_status);
3250 /* link is up only if both local phy and external phy are up */
a22f0788
YR		 3251 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3252 return -ESRCH;
3253
3254 switch (params->num_phys) {
3255 case 1:
3256 /* No external PHY */
3257 return 0;
3258 case 2:
3259 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3260 &params->phy[EXT_PHY1],
3261 params, &temp_vars);
3262 break;
3263 case 3: /* Dual Media */
de6eae1f
YR		 3264 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3265 phy_index++) {
a22f0788
YR		 3266 serdes_phy_type = ((params->phy[phy_index].media_type ==
3267 ETH_PHY_SFP_FIBER) ||
3268 (params->phy[phy_index].media_type ==
3269 ETH_PHY_XFP_FIBER));
3270
3271 if (is_serdes != serdes_phy_type)
3272 continue;
3273 if (params->phy[phy_index].read_status) {
3274 ext_phy_link_up |=
de6eae1f
YR		 3275 params->phy[phy_index].read_status(
3276 &params->phy[phy_index],
3277 params, &temp_vars);
a22f0788 3278 }
de6eae1f 3279 }
a22f0788 3280 break;
4d295db0 3281 }
a22f0788
YR		 3282 if (ext_phy_link_up)
3283 return 0;
de6eae1f
YR		 3284 return -ESRCH;
3285}
4d295db0 3286
de6eae1f
YR		 3287static u8 bnx2x_link_initialize(struct link_params *params,
3288 struct link_vars *vars)
3289{
3290 u8 rc = 0;
3291 u8 phy_index, non_ext_phy;
3292 struct bnx2x *bp = params->bp;
3293 /**
3294 * In case of external phy existence, the line speed would be the
3295 * line speed linked up by the external phy. In case it is direct
3296 * only, then the line_speed during initialization will be
3297 * equal to the req_line_speed
3298 */
3299 vars->line_speed = params->phy[INT_PHY].req_line_speed;
4d295db0 3300
de6eae1f
YR		 3301 /**
3302 * Initialize the internal phy in case this is a direct board
3303 * (no external phys), or this board has external phy which requires
3304 * to first.
3305 */
4d295db0 3306
de6eae1f
YR		 3307 if (params->phy[INT_PHY].config_init)
3308 params->phy[INT_PHY].config_init(
3309 &params->phy[INT_PHY],
3310 params, vars);
4d295db0 3311
de6eae1f
YR		 3312 /* init ext phy and enable link state int */
3313 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3314 (params->loopback_mode == LOOPBACK_XGXS));
4d295db0 3315
de6eae1f
YR		 3316 if (non_ext_phy ||
3317 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3318 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3319 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3320 if (vars->line_speed == SPEED_AUTO_NEG)
3321 bnx2x_set_parallel_detection(phy, params);
3322 bnx2x_init_internal_phy(phy, params, vars);
4d295db0
EG		 3323 }
3324
de6eae1f
YR		 3325 /* Init external phy*/
3326 if (!non_ext_phy)
3327 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3328 phy_index++) {
a22f0788
YR		 3329 /**
3330 * No need to initialize second phy in case of first
3331 * phy only selection. In case of second phy, we do
3332 * need to initialize the first phy, since they are
3333 * connected.
3334 **/
3335 if (phy_index == EXT_PHY2 &&
3336 (bnx2x_phy_selection(params) ==
3337 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3338 DP(NETIF_MSG_LINK, "Not initializing"
3339 "second phy\n");
3340 continue;
3341 }
de6eae1f
YR		 3342 params->phy[phy_index].config_init(
3343 &params->phy[phy_index],
3344 params, vars);
3345 }
4d295db0 3346
de6eae1f
YR		 3347 /* Reset the interrupt indication after phy was initialized */
3348 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3349 params->port*4,
3350 (NIG_STATUS_XGXS0_LINK10G |
3351 NIG_STATUS_XGXS0_LINK_STATUS |
3352 NIG_STATUS_SERDES0_LINK_STATUS |
3353 NIG_MASK_MI_INT));
3354 return rc;
3355}
4d295db0 3356
de6eae1f
YR		 3357static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3358 struct link_params *params)
3359{
3360 /* reset the SerDes/XGXS */
3361 REG_WR(params->bp, GRCBASE_MISC +
3362 MISC_REGISTERS_RESET_REG_3_CLEAR,
3363 (0x1ff << (params->port*16)));
589abe3a
EG		 3364}
3365
de6eae1f
YR		 3366static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3367 struct link_params *params)
4d295db0 3368{
de6eae1f
YR		 3369 struct bnx2x *bp = params->bp;
3370 u8 gpio_port;
3371 /* HW reset */
f2e0899f
DK		 3372 if (CHIP_IS_E2(bp))
3373 gpio_port = BP_PATH(bp);
3374 else
3375 gpio_port = params->port;
de6eae1f
YR		 3376 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3377 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3378 gpio_port);
3379 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3380 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3381 gpio_port);
3382 DP(NETIF_MSG_LINK, "reset external PHY\n");
4d295db0 3383}
589abe3a 3384
de6eae1f
YR		 3385static u8 bnx2x_update_link_down(struct link_params *params,
3386 struct link_vars *vars)
589abe3a
EG		 3387{
3388 struct bnx2x *bp = params->bp;
de6eae1f 3389 u8 port = params->port;
589abe3a 3390
de6eae1f 3391 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
7f02c4ad 3392 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
589abe3a 3393
de6eae1f
YR		 3394 /* indicate no mac active */
3395 vars->mac_type = MAC_TYPE_NONE;
ab6ad5a4 3396
de6eae1f
YR		 3397 /* update shared memory */
3398 vars->link_status = 0;
3399 vars->line_speed = 0;
3400 bnx2x_update_mng(params, vars->link_status);
589abe3a 3401
de6eae1f
YR		 3402 /* activate nig drain */
3403 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4d295db0 3404
de6eae1f
YR		 3405 /* disable emac */
3406 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3407
3408 msleep(10);
3409
3410 /* reset BigMac */
3411 bnx2x_bmac_rx_disable(bp, params->port);
3412 REG_WR(bp, GRCBASE_MISC +
3413 MISC_REGISTERS_RESET_REG_2_CLEAR,
3414 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
589abe3a
EG		 3415 return 0;
3416}
de6eae1f
YR		 3417
3418static u8 bnx2x_update_link_up(struct link_params *params,
3419 struct link_vars *vars,
3420 u8 link_10g)
589abe3a
EG		 3421{
3422 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3423 u8 port = params->port;
3424 u8 rc = 0;
4d295db0 3425
de6eae1f 3426 vars->link_status |= LINK_STATUS_LINK_UP;
7f02c4ad 3427
de6eae1f
YR		 3428 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3429 vars->link_status |=
3430 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
589abe3a 3431
de6eae1f
YR		 3432 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3433 vars->link_status |=
3434 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7f02c4ad 3435
de6eae1f
YR		 3436 if (link_10g) {
3437 bnx2x_bmac_enable(params, vars, 0);
7f02c4ad
YR		 3438 bnx2x_set_led(params, vars,
3439 LED_MODE_OPER, SPEED_10000);
de6eae1f
YR		 3440 } else {
3441 rc = bnx2x_emac_program(params, vars);
cc1cb004 3442
de6eae1f 3443 bnx2x_emac_enable(params, vars, 0);
cc1cb004 3444
de6eae1f
YR		 3445 /* AN complete? */
3446 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3447 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3448 SINGLE_MEDIA_DIRECT(params))
3449 bnx2x_set_gmii_tx_driver(params);
3450 }
cc1cb004 3451
de6eae1f 3452 /* PBF - link up */
f2e0899f
DK		 3453 if (!(CHIP_IS_E2(bp)))
3454 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3455 vars->line_speed);
589abe3a 3456
de6eae1f
YR		 3457 /* disable drain */
3458 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
589abe3a 3459
de6eae1f
YR		 3460 /* update shared memory */
3461 bnx2x_update_mng(params, vars->link_status);
3462 msleep(20);
3463 return rc;
589abe3a 3464}
de6eae1f
YR		 3465/**
3466 * The bnx2x_link_update function should be called upon link
3467 * interrupt.
3468 * Link is considered up as follows:
3469 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3470 * to be up
3471 * - SINGLE_MEDIA - The link between the 577xx and the external
3472 * phy (XGXS) need to up as well as the external link of the
3473 * phy (PHY_EXT1)
3474 * - DUAL_MEDIA - The link between the 577xx and the first
3475 * external phy needs to be up, and at least one of the 2
3476 * external phy link must be up.
3477 */
3478u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4d295db0 3479{
de6eae1f
YR		 3480 struct bnx2x *bp = params->bp;
3481 struct link_vars phy_vars[MAX_PHYS];
3482 u8 port = params->port;
3483 u8 link_10g, phy_index;
3484 u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
3485 u8 is_mi_int = 0;
3486 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3487 u8 active_external_phy = INT_PHY;
3488 vars->link_status = 0;
3489 for (phy_index = INT_PHY; phy_index < params->num_phys;
3490 phy_index++) {
3491 phy_vars[phy_index].flow_ctrl = 0;
3492 phy_vars[phy_index].link_status = 0;
3493 phy_vars[phy_index].line_speed = 0;
3494 phy_vars[phy_index].duplex = DUPLEX_FULL;
3495 phy_vars[phy_index].phy_link_up = 0;
3496 phy_vars[phy_index].link_up = 0;
3497 }
4d295db0 3498
de6eae1f
YR		 3499 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3500 port, (vars->phy_flags & PHY_XGXS_FLAG),
3501 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4d295db0 3502
de6eae1f
YR		 3503 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3504 port*0x18) > 0);
3505 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3506 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3507 is_mi_int,
3508 REG_RD(bp,
3509 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4d295db0 3510
de6eae1f
YR		 3511 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3512 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3513 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4d295db0 3514
de6eae1f
YR		 3515 /* disable emac */
3516 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4d295db0 3517
de6eae1f
YR		 3518 /**
3519 * Step 1:
3520 * Check external link change only for external phys, and apply
3521 * priority selection between them in case the link on both phys
3522 * is up. Note that the instead of the common vars, a temporary
3523 * vars argument is used since each phy may have different link/
3524 * speed/duplex result
3525 */
3526 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3527 phy_index++) {
3528 struct bnx2x_phy *phy = &params->phy[phy_index];
3529 if (!phy->read_status)
3530 continue;
3531 /* Read link status and params of this ext phy */
3532 cur_link_up = phy->read_status(phy, params,
3533 &phy_vars[phy_index]);
3534 if (cur_link_up) {
3535 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3536 phy_index);
3537 } else {
3538 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3539 phy_index);
3540 continue;
3541 }
e10bc84d 3542
de6eae1f
YR		 3543 if (!ext_phy_link_up) {
3544 ext_phy_link_up = 1;
3545 active_external_phy = phy_index;
a22f0788
YR		 3546 } else {
3547 switch (bnx2x_phy_selection(params)) {
3548 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3549 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3550 /**
3551 * In this option, the first PHY makes sure to pass the
3552 * traffic through itself only.
3553 * Its not clear how to reset the link on the second phy
3554 **/
3555 active_external_phy = EXT_PHY1;
3556 break;
3557 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3558 /**
3559 * In this option, the first PHY makes sure to pass the
3560 * traffic through the second PHY.
3561 **/
3562 active_external_phy = EXT_PHY2;
3563 break;
3564 default:
3565 /**
3566 * Link indication on both PHYs with the following cases
3567 * is invalid:
3568 * - FIRST_PHY means that second phy wasn't initialized,
3569 * hence its link is expected to be down
3570 * - SECOND_PHY means that first phy should not be able
3571 * to link up by itself (using configuration)
3572 * - DEFAULT should be overriden during initialiazation
3573 **/
3574 DP(NETIF_MSG_LINK, "Invalid link indication"
3575 "mpc=0x%x. DISABLING LINK !!!\n",
3576 params->multi_phy_config);
3577 ext_phy_link_up = 0;
3578 break;
3579 }
589abe3a 3580 }
589abe3a 3581 }
de6eae1f
YR		 3582 prev_line_speed = vars->line_speed;
3583 /**
3584 * Step 2:
3585 * Read the status of the internal phy. In case of
3586 * DIRECT_SINGLE_MEDIA board, this link is the external link,
3587 * otherwise this is the link between the 577xx and the first
3588 * external phy
4d295db0 3589 */
de6eae1f
YR		 3590 if (params->phy[INT_PHY].read_status)
3591 params->phy[INT_PHY].read_status(
3592 &params->phy[INT_PHY],
3593 params, vars);
3594 /**
3595 * The INT_PHY flow control reside in the vars. This include the
3596 * case where the speed or flow control are not set to AUTO.
3597 * Otherwise, the active external phy flow control result is set
3598 * to the vars. The ext_phy_line_speed is needed to check if the
3599 * speed is different between the internal phy and external phy.
3600 * This case may be result of intermediate link speed change.
4d295db0 3601 */
de6eae1f
YR		 3602 if (active_external_phy > INT_PHY) {
3603 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3604 /**
3605 * Link speed is taken from the XGXS. AN and FC result from
3606 * the external phy.
4d295db0 3607 */
de6eae1f 3608 vars->link_status |= phy_vars[active_external_phy].link_status;
a22f0788
YR		 3609
3610 /**
3611 * if active_external_phy is first PHY and link is up - disable
3612 * disable TX on second external PHY
3613 */
3614 if (active_external_phy == EXT_PHY1) {
3615 if (params->phy[EXT_PHY2].phy_specific_func) {
3616 DP(NETIF_MSG_LINK, "Disabling TX on"
3617 " EXT_PHY2\n");
3618 params->phy[EXT_PHY2].phy_specific_func(
3619 &params->phy[EXT_PHY2],
3620 params, DISABLE_TX);
3621 }
3622 }
3623
de6eae1f
YR		 3624 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3625 vars->duplex = phy_vars[active_external_phy].duplex;
3626 if (params->phy[active_external_phy].supported &
3627 SUPPORTED_FIBRE)
3628 vars->link_status |= LINK_STATUS_SERDES_LINK;
3629 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3630 active_external_phy);
3631 }
a22f0788
YR		 3632
3633 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3634 phy_index++) {
3635 if (params->phy[phy_index].flags &
3636 FLAGS_REARM_LATCH_SIGNAL) {
3637 bnx2x_rearm_latch_signal(bp, port,
3638 phy_index ==
3639 active_external_phy);
3640 break;
3641 }
3642 }
de6eae1f
YR		 3643 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3644 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3645 vars->link_status, ext_phy_line_speed);
3646 /**
3647 * Upon link speed change set the NIG into drain mode. Comes to
3648 * deals with possible FIFO glitch due to clk change when speed
3649 * is decreased without link down indicator
3650 */
4d295db0 3651
de6eae1f
YR		 3652 if (vars->phy_link_up) {
3653 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3654 (ext_phy_line_speed != vars->line_speed)) {
3655 DP(NETIF_MSG_LINK, "Internal link speed %d is"
3656 " different than the external"
3657 " link speed %d\n", vars->line_speed,
3658 ext_phy_line_speed);
3659 vars->phy_link_up = 0;
3660 } else if (prev_line_speed != vars->line_speed) {
3661 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3662 + params->port*4, 0);
3663 msleep(1);
3664 }
3665 }
e10bc84d 3666
de6eae1f
YR		 3667 /* anything 10 and over uses the bmac */
3668 link_10g = ((vars->line_speed == SPEED_10000) ||
3669 (vars->line_speed == SPEED_12000) ||
3670 (vars->line_speed == SPEED_12500) ||
3671 (vars->line_speed == SPEED_13000) ||
3672 (vars->line_speed == SPEED_15000) ||
3673 (vars->line_speed == SPEED_16000));
589abe3a 3674
a22f0788 3675 bnx2x_link_int_ack(params, vars, link_10g);
589abe3a 3676
de6eae1f
YR		 3677 /**
3678 * In case external phy link is up, and internal link is down
3679 * (not initialized yet probably after link initialization, it
3680 * needs to be initialized.
3681 * Note that after link down-up as result of cable plug, the xgxs
3682 * link would probably become up again without the need
3683 * initialize it
3684 */
3685 if (!(SINGLE_MEDIA_DIRECT(params))) {
3686 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3687 " init_preceding = %d\n", ext_phy_link_up,
3688 vars->phy_link_up,
3689 params->phy[EXT_PHY1].flags &
3690 FLAGS_INIT_XGXS_FIRST);
3691 if (!(params->phy[EXT_PHY1].flags &
3692 FLAGS_INIT_XGXS_FIRST)
3693 && ext_phy_link_up && !vars->phy_link_up) {
3694 vars->line_speed = ext_phy_line_speed;
3695 if (vars->line_speed < SPEED_1000)
3696 vars->phy_flags |= PHY_SGMII_FLAG;
3697 else
3698 vars->phy_flags &= ~PHY_SGMII_FLAG;
3699 bnx2x_init_internal_phy(&params->phy[INT_PHY],
3700 params,
3701 vars);
4d295db0 3702 }
589abe3a 3703 }
de6eae1f
YR		 3704 /**
3705 * Link is up only if both local phy and external phy (in case of
3706 * non-direct board) are up
4d295db0 3707 */
de6eae1f
YR		 3708 vars->link_up = (vars->phy_link_up &&
3709 (ext_phy_link_up ||
3710 SINGLE_MEDIA_DIRECT(params)));
3711
3712 if (vars->link_up)
3713 rc = bnx2x_update_link_up(params, vars, link_10g);
4d295db0 3714 else
de6eae1f 3715 rc = bnx2x_update_link_down(params, vars);
589abe3a 3716
4d295db0 3717 return rc;
589abe3a
EG		 3718}
3719
589abe3a 3720
de6eae1f
YR		 3721/*****************************************************************************/
3722/* External Phy section */
3723/*****************************************************************************/
3724void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3725{
3726 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3727 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3728 msleep(1);
3729 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3730 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3731}
589abe3a 3732
de6eae1f
YR		 3733static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3734 u32 spirom_ver, u32 ver_addr)
3735{
3736 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3737 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
4d295db0 3738
de6eae1f
YR		 3739 if (ver_addr)
3740 REG_WR(bp, ver_addr, spirom_ver);
589abe3a
EG		 3741}
3742
de6eae1f
YR		 3743static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3744 struct bnx2x_phy *phy,
3745 u8 port)
6bbca910 3746{
de6eae1f
YR		 3747 u16 fw_ver1, fw_ver2;
3748
3749 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3750 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3751 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3752 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3753 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3754 phy->ver_addr);
ea4e040a 3755}
ab6ad5a4 3756
de6eae1f
YR		 3757static void bnx2x_ext_phy_set_pause(struct link_params *params,
3758 struct bnx2x_phy *phy,
3759 struct link_vars *vars)
ea4e040a 3760{
ea4e040a 3761 u16 val;
de6eae1f
YR		 3762 struct bnx2x *bp = params->bp;
3763 /* read modify write pause advertizing */
3764 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
ea4e040a 3765
de6eae1f 3766 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
ea4e040a 3767
de6eae1f
YR		 3768 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3769 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3770 if ((vars->ieee_fc &
3771 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3772 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3773 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3774 }
3775 if ((vars->ieee_fc &
3776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3777 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3778 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3779 }
3780 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3781 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3782}
3783
3784static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3785 struct link_params *params,
3786 struct link_vars *vars)
3787{
3788 struct bnx2x *bp = params->bp;
3789 u16 ld_pause; /* local */
3790 u16 lp_pause; /* link partner */
3791 u16 pause_result;
3792 u8 ret = 0;
3793 /* read twice */
3794
3795 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3796
3797 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3798 vars->flow_ctrl = phy->req_flow_ctrl;
3799 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3800 vars->flow_ctrl = params->req_fc_auto_adv;
3801 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3802 ret = 1;
3803 bnx2x_cl45_read(bp, phy,
3804 MDIO_AN_DEVAD,
3805 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3806 bnx2x_cl45_read(bp, phy,
3807 MDIO_AN_DEVAD,
3808 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3809 pause_result = (ld_pause &
3810 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3811 pause_result |= (lp_pause &
3812 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3813 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3814 pause_result);
3815 bnx2x_pause_resolve(vars, pause_result);
3816 }
3817 return ret;
3818}
3819
3820static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3821 struct bnx2x_phy *phy,
3822 struct link_vars *vars)
3823{
3824 u16 val;
3825 bnx2x_cl45_read(bp, phy,
3826 MDIO_AN_DEVAD,
3827 MDIO_AN_REG_STATUS, &val);
3828 bnx2x_cl45_read(bp, phy,
3829 MDIO_AN_DEVAD,
3830 MDIO_AN_REG_STATUS, &val);
3831 if (val & (1<<5))
3832 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3833 if ((val & (1<<0)) == 0)
3834 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3835}
3836
3837/******************************************************************/
3838/* common BCM8073/BCM8727 PHY SECTION */
3839/******************************************************************/
3840static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3841 struct link_params *params,
3842 struct link_vars *vars)
3843{
3844 struct bnx2x *bp = params->bp;
3845 if (phy->req_line_speed == SPEED_10 ||
3846 phy->req_line_speed == SPEED_100) {
3847 vars->flow_ctrl = phy->req_flow_ctrl;
3848 return;
3849 }
3850
3851 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3852 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3853 u16 pause_result;
3854 u16 ld_pause; /* local */
3855 u16 lp_pause; /* link partner */
3856 bnx2x_cl45_read(bp, phy,
3857 MDIO_AN_DEVAD,
3858 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3859
3860 bnx2x_cl45_read(bp, phy,
3861 MDIO_AN_DEVAD,
3862 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3863 pause_result = (ld_pause &
3864 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3865 pause_result |= (lp_pause &
3866 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3867
3868 bnx2x_pause_resolve(vars, pause_result);
3869 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3870 pause_result);
3871 }
3872}
5c99274b 3873static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
de6eae1f
YR		 3874 struct bnx2x_phy *phy,
3875 u8 port)
3876{
5c99274b
YR		 3877 u32 count = 0;
3878 u16 fw_ver1, fw_msgout;
3879 u8 rc = 0;
3880
de6eae1f
YR		 3881 /* Boot port from external ROM */
3882 /* EDC grst */
3883 bnx2x_cl45_write(bp, phy,
3884 MDIO_PMA_DEVAD,
3885 MDIO_PMA_REG_GEN_CTRL,
3886 0x0001);
3887
3888 /* ucode reboot and rst */
3889 bnx2x_cl45_write(bp, phy,
3890 MDIO_PMA_DEVAD,
3891 MDIO_PMA_REG_GEN_CTRL,
3892 0x008c);
3893
3894 bnx2x_cl45_write(bp, phy,
3895 MDIO_PMA_DEVAD,
3896 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3897
3898 /* Reset internal microprocessor */
3899 bnx2x_cl45_write(bp, phy,
3900 MDIO_PMA_DEVAD,
3901 MDIO_PMA_REG_GEN_CTRL,
3902 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3903
3904 /* Release srst bit */
3905 bnx2x_cl45_write(bp, phy,
3906 MDIO_PMA_DEVAD,
3907 MDIO_PMA_REG_GEN_CTRL,
3908 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3909
5c99274b
YR		 3910 /* Delay 100ms per the PHY specifications */
3911 msleep(100);
3912
3913 /* 8073 sometimes taking longer to download */
3914 do {
3915 count++;
3916 if (count > 300) {
3917 DP(NETIF_MSG_LINK,
3918 "bnx2x_8073_8727_external_rom_boot port %x:"
3919 "Download failed. fw version = 0x%x\n",
3920 port, fw_ver1);
3921 rc = -EINVAL;
3922 break;
3923 }
3924
3925 bnx2x_cl45_read(bp, phy,
3926 MDIO_PMA_DEVAD,
3927 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3928 bnx2x_cl45_read(bp, phy,
3929 MDIO_PMA_DEVAD,
3930 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3931
3932 msleep(1);
3933 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3934 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
de6eae1f
YR		 3936
3937 /* Clear ser_boot_ctl bit */
3938 bnx2x_cl45_write(bp, phy,
3939 MDIO_PMA_DEVAD,
3940 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3941 bnx2x_save_bcm_spirom_ver(bp, phy, port);
5c99274b
YR		 3942
3943 DP(NETIF_MSG_LINK,
3944 "bnx2x_8073_8727_external_rom_boot port %x:"
3945 "Download complete. fw version = 0x%x\n",
3946 port, fw_ver1);
3947
3948 return rc;
de6eae1f
YR		 3949}
3950
3951static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3952 struct bnx2x_phy *phy)
3953{
3954 u16 val;
3955 bnx2x_cl45_read(bp, phy,
3956 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
3957
3958 if (val == 0) {
3959 /* Mustn't set low power mode in 8073 A0 */
3960 return;
3961 }
3962
3963 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3964 bnx2x_cl45_read(bp, phy,
62b29a5d 3965 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
ea4e040a 3966 val &= ~(1<<13);
e10bc84d 3967 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 3968 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3969
3970 /* PLL controls */
62b29a5d
YR		 3971 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
3972 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
3973 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
3974 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
3975 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
ea4e040a
YR		 3976
3977 /* Tx Controls */
62b29a5d
YR		 3978 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3979 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
3980 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
ea4e040a
YR		 3981
3982 /* Rx Controls */
62b29a5d
YR		 3983 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3984 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
3985 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
ea4e040a
YR		 3986
3987 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
62b29a5d 3988 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
ea4e040a 3989 val |= (1<<13);
62b29a5d 3990 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
ea4e040a 3991}
6bbca910 3992
de6eae1f
YR		 3993/******************************************************************/
3994/* BCM8073 PHY SECTION */
3995/******************************************************************/
3996static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3997{
3998 /* This is only required for 8073A1, version 102 only */
3999 u16 val;
4000
4001 /* Read 8073 HW revision*/
4002 bnx2x_cl45_read(bp, phy,
4003 MDIO_PMA_DEVAD,
4004 MDIO_PMA_REG_8073_CHIP_REV, &val);
4005
4006 if (val != 1) {
4007 /* No need to workaround in 8073 A1 */
4008 return 0;
4009 }
4010
4011 bnx2x_cl45_read(bp, phy,
4012 MDIO_PMA_DEVAD,
4013 MDIO_PMA_REG_ROM_VER2, &val);
4014
4015 /* SNR should be applied only for version 0x102 */
4016 if (val != 0x102)
4017 return 0;
4018
4019 return 1;
4020}
4021
4022static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
4023{
4024 u16 val, cnt, cnt1 ;
4025
4026 bnx2x_cl45_read(bp, phy,
4027 MDIO_PMA_DEVAD,
4028 MDIO_PMA_REG_8073_CHIP_REV, &val);
4029
4030 if (val > 0) {
4031 /* No need to workaround in 8073 A1 */
4032 return 0;
4033 }
4034 /* XAUI workaround in 8073 A0: */
4035
4036 /* After loading the boot ROM and restarting Autoneg,
4037 poll Dev1, Reg $C820: */
4038
4039 for (cnt = 0; cnt < 1000; cnt++) {
4040 bnx2x_cl45_read(bp, phy,
4041 MDIO_PMA_DEVAD,
4042 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4043 &val);
4044 /* If bit [14] = 0 or bit [13] = 0, continue on with
4045 system initialization (XAUI work-around not required,
4046 as these bits indicate 2.5G or 1G link up). */
4047 if (!(val & (1<<14)) || !(val & (1<<13))) {
4048 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
4049 return 0;
4050 } else if (!(val & (1<<15))) {
4051 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
4052 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
4053 it's MSB (bit 15) goes to 1 (indicating that the
4054 XAUI workaround has completed),
4055 then continue on with system initialization.*/
4056 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4057 bnx2x_cl45_read(bp, phy,
4058 MDIO_PMA_DEVAD,
4059 MDIO_PMA_REG_8073_XAUI_WA, &val);
4060 if (val & (1<<15)) {
4061 DP(NETIF_MSG_LINK,
4062 "XAUI workaround has completed\n");
4063 return 0;
4064 }
4065 msleep(3);
4066 }
4067 break;
4068 }
4069 msleep(3);
4070 }
4071 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4072 return -EINVAL;
4073}
4074
4075static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4076{
4077 /* Force KR or KX */
4078 bnx2x_cl45_write(bp, phy,
4079 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4080 bnx2x_cl45_write(bp, phy,
4081 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4082 bnx2x_cl45_write(bp, phy,
4083 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4084 bnx2x_cl45_write(bp, phy,
4085 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4086}
4087
6bbca910 4088static void bnx2x_8073_set_pause_cl37(struct link_params *params,
e10bc84d
YR		 4089 struct bnx2x_phy *phy,
4090 struct link_vars *vars)
ea4e040a 4091{
6bbca910 4092 u16 cl37_val;
e10bc84d
YR		 4093 struct bnx2x *bp = params->bp;
4094 bnx2x_cl45_read(bp, phy,
62b29a5d 4095 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6bbca910
YR		 4096
4097 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4098 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
e10bc84d 4099 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6bbca910
YR		 4100 if ((vars->ieee_fc &
4101 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4102 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4103 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4104 }
4105 if ((vars->ieee_fc &
4106 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4107 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4108 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4109 }
4110 if ((vars->ieee_fc &
4111 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4112 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4113 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4114 }
4115 DP(NETIF_MSG_LINK,
4116 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4117
e10bc84d 4118 bnx2x_cl45_write(bp, phy,
62b29a5d 4119 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6bbca910 4120 msleep(500);
ea4e040a
YR		 4121}
4122
de6eae1f
YR		 4123static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4124 struct link_params *params,
4125 struct link_vars *vars)
ea4e040a 4126{
e10bc84d 4127 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4128 u16 val = 0, tmp1;
4129 u8 gpio_port;
4130 DP(NETIF_MSG_LINK, "Init 8073\n");
e10bc84d 4131
f2e0899f
DK		 4132 if (CHIP_IS_E2(bp))
4133 gpio_port = BP_PATH(bp);
4134 else
4135 gpio_port = params->port;
de6eae1f
YR		 4136 /* Restore normal power mode*/
4137 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4138 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
e10bc84d 4139
de6eae1f
YR		 4140 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4141 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
ea4e040a 4142
de6eae1f
YR		 4143 /* enable LASI */
4144 bnx2x_cl45_write(bp, phy,
4145 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4146 bnx2x_cl45_write(bp, phy,
4147 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
c2c8b03e 4148
de6eae1f 4149 bnx2x_8073_set_pause_cl37(params, phy, vars);
57963ed9 4150
de6eae1f 4151 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
e10bc84d 4152
e10bc84d 4153 bnx2x_cl45_read(bp, phy,
de6eae1f 4154 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
2f904460 4155
de6eae1f
YR		 4156 bnx2x_cl45_read(bp, phy,
4157 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
2f904460 4158
de6eae1f 4159 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
a1e4be39 4160
74d7a119
YR		 4161 /**
4162 * If this is forced speed, set to KR or KX (all other are not
4163 * supported)
4164 */
4165 /* Swap polarity if required - Must be done only in non-1G mode */
4166 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4167 /* Configure the 8073 to swap _P and _N of the KR lines */
4168 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4169 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4170 bnx2x_cl45_read(bp, phy,
4171 MDIO_PMA_DEVAD,
4172 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4173 bnx2x_cl45_write(bp, phy,
4174 MDIO_PMA_DEVAD,
4175 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4176 (val | (3<<9)));
4177 }
4178
4179
de6eae1f 4180 /* Enable CL37 BAM */
121839be
YR		 4181 if (REG_RD(bp, params->shmem_base +
4182 offsetof(struct shmem_region, dev_info.
4183 port_hw_config[params->port].default_cfg)) &
4184 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
57963ed9 4185
121839be
YR		 4186 bnx2x_cl45_read(bp, phy,
4187 MDIO_AN_DEVAD,
4188 MDIO_AN_REG_8073_BAM, &val);
4189 bnx2x_cl45_write(bp, phy,
4190 MDIO_AN_DEVAD,
4191 MDIO_AN_REG_8073_BAM, val | 1);
4192 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4193 }
de6eae1f
YR		 4194 if (params->loopback_mode == LOOPBACK_EXT) {
4195 bnx2x_807x_force_10G(bp, phy);
4196 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4197 return 0;
4198 } else {
4199 bnx2x_cl45_write(bp, phy,
4200 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4201 }
4202 if (phy->req_line_speed != SPEED_AUTO_NEG) {
4203 if (phy->req_line_speed == SPEED_10000) {
4204 val = (1<<7);
4205 } else if (phy->req_line_speed == SPEED_2500) {
4206 val = (1<<5);
4207 /* Note that 2.5G works only
4208 when used with 1G advertisment */
4209 } else
4210 val = (1<<5);
4211 } else {
4212 val = 0;
4213 if (phy->speed_cap_mask &
4214 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4215 val |= (1<<7);
57963ed9 4216
de6eae1f
YR		 4217 /* Note that 2.5G works only when
4218 used with 1G advertisment */
4219 if (phy->speed_cap_mask &
4220 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4221 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4222 val |= (1<<5);
4223 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4224 }
57963ed9 4225
de6eae1f
YR		 4226 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4227 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
57963ed9 4228
de6eae1f
YR		 4229 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4230 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4231 (phy->req_line_speed == SPEED_2500)) {
4232 u16 phy_ver;
4233 /* Allow 2.5G for A1 and above */
4234 bnx2x_cl45_read(bp, phy,
4235 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4236 &phy_ver);
4237 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4238 if (phy_ver > 0)
4239 tmp1 |= 1;
4240 else
4241 tmp1 &= 0xfffe;
4242 } else {
4243 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4244 tmp1 &= 0xfffe;
4245 }
57963ed9 4246
de6eae1f
YR		 4247 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4248 /* Add support for CL37 (passive mode) II */
57963ed9 4249
de6eae1f
YR		 4250 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4251 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4252 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4253 0x20 : 0x40)));
57963ed9 4254
de6eae1f
YR		 4255 /* Add support for CL37 (passive mode) III */
4256 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
57963ed9 4257
de6eae1f
YR		 4258 /* The SNR will improve about 2db by changing
4259 BW and FEE main tap. Rest commands are executed
4260 after link is up*/
4261 if (bnx2x_8073_is_snr_needed(bp, phy))
4262 bnx2x_cl45_write(bp, phy,
4263 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4264 0xFB0C);
57963ed9 4265
de6eae1f
YR		 4266 /* Enable FEC (Forware Error Correction) Request in the AN */
4267 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4268 tmp1 |= (1<<15);
4269 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
57963ed9 4270
de6eae1f 4271 bnx2x_ext_phy_set_pause(params, phy, vars);
57963ed9 4272
de6eae1f
YR		 4273 /* Restart autoneg */
4274 msleep(500);
4275 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4276 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4277 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4278 return 0;
b7737c9b 4279}
ea4e040a 4280
de6eae1f 4281static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 4282 struct link_params *params,
4283 struct link_vars *vars)
4284{
4285 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4286 u8 link_up = 0;
4287 u16 val1, val2;
4288 u16 link_status = 0;
4289 u16 an1000_status = 0;
a35da8db 4290
de6eae1f
YR		 4291 bnx2x_cl45_read(bp, phy,
4292 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
b7737c9b 4293
de6eae1f 4294 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
ea4e040a 4295
de6eae1f
YR		 4296 /* clear the interrupt LASI status register */
4297 bnx2x_cl45_read(bp, phy,
4298 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4299 bnx2x_cl45_read(bp, phy,
4300 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4301 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4302 /* Clear MSG-OUT */
4303 bnx2x_cl45_read(bp, phy,
4304 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4305
4306 /* Check the LASI */
4307 bnx2x_cl45_read(bp, phy,
4308 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4309
4310 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4311
4312 /* Check the link status */
4313 bnx2x_cl45_read(bp, phy,
4314 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4315 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4316
4317 bnx2x_cl45_read(bp, phy,
4318 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4319 bnx2x_cl45_read(bp, phy,
4320 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4321 link_up = ((val1 & 4) == 4);
4322 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4323
4324 if (link_up &&
4325 ((phy->req_line_speed != SPEED_10000))) {
4326 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4327 return 0;
62b29a5d 4328 }
de6eae1f
YR		 4329 bnx2x_cl45_read(bp, phy,
4330 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4331 bnx2x_cl45_read(bp, phy,
4332 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
62b29a5d 4333
de6eae1f
YR		 4334 /* Check the link status on 1.1.2 */
4335 bnx2x_cl45_read(bp, phy,
4336 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4337 bnx2x_cl45_read(bp, phy,
4338 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4339 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4340 "an_link_status=0x%x\n", val2, val1, an1000_status);
62b29a5d 4341
de6eae1f
YR		 4342 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4343 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4344 /* The SNR will improve about 2dbby
4345 changing the BW and FEE main tap.*/
4346 /* The 1st write to change FFE main
4347 tap is set before restart AN */
4348 /* Change PLL Bandwidth in EDC
4349 register */
62b29a5d 4350 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4351 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4352 0x26BC);
62b29a5d 4353
de6eae1f 4354 /* Change CDR Bandwidth in EDC register */
62b29a5d 4355 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4356 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4357 0x0333);
4358 }
4359 bnx2x_cl45_read(bp, phy,
4360 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4361 &link_status);
62b29a5d 4362
de6eae1f
YR		 4363 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4364 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4365 link_up = 1;
4366 vars->line_speed = SPEED_10000;
4367 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4368 params->port);
4369 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4370 link_up = 1;
4371 vars->line_speed = SPEED_2500;
4372 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4373 params->port);
4374 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4375 link_up = 1;
4376 vars->line_speed = SPEED_1000;
4377 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4378 params->port);
4379 } else {
4380 link_up = 0;
4381 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4382 params->port);
62b29a5d 4383 }
de6eae1f
YR		 4384
4385 if (link_up) {
74d7a119
YR		 4386 /* Swap polarity if required */
4387 if (params->lane_config &
4388 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4389 /* Configure the 8073 to swap P and N of the KR lines */
4390 bnx2x_cl45_read(bp, phy,
4391 MDIO_XS_DEVAD,
4392 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4393 /**
4394 * Set bit 3 to invert Rx in 1G mode and clear this bit
4395 * when it`s in 10G mode.
4396 */
4397 if (vars->line_speed == SPEED_1000) {
4398 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4399 "the 8073\n");
4400 val1 |= (1<<3);
4401 } else
4402 val1 &= ~(1<<3);
4403
4404 bnx2x_cl45_write(bp, phy,
4405 MDIO_XS_DEVAD,
4406 MDIO_XS_REG_8073_RX_CTRL_PCIE,
4407 val1);
4408 }
de6eae1f
YR		 4409 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4410 bnx2x_8073_resolve_fc(phy, params, vars);
4411 }
4412 return link_up;
b7737c9b
YR		 4413}
4414
de6eae1f
YR		 4415static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4416 struct link_params *params)
4417{
4418 struct bnx2x *bp = params->bp;
4419 u8 gpio_port;
f2e0899f
DK		 4420 if (CHIP_IS_E2(bp))
4421 gpio_port = BP_PATH(bp);
4422 else
4423 gpio_port = params->port;
de6eae1f
YR		 4424 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4425 gpio_port);
4426 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4427 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4428 gpio_port);
4429}
4430
4431/******************************************************************/
4432/* BCM8705 PHY SECTION */
4433/******************************************************************/
4434static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 4435 struct link_params *params,
4436 struct link_vars *vars)
4437{
4438 struct bnx2x *bp = params->bp;
de6eae1f 4439 DP(NETIF_MSG_LINK, "init 8705\n");
b7737c9b
YR		 4440 /* Restore normal power mode*/
4441 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4442 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 4443 /* HW reset */
4444 bnx2x_ext_phy_hw_reset(bp, params->port);
4445 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
b7737c9b
YR		 4446 bnx2x_wait_reset_complete(bp, phy);
4447
de6eae1f
YR		 4448 bnx2x_cl45_write(bp, phy,
4449 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4450 bnx2x_cl45_write(bp, phy,
4451 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4452 bnx2x_cl45_write(bp, phy,
4453 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4454 bnx2x_cl45_write(bp, phy,
4455 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4456 /* BCM8705 doesn't have microcode, hence the 0 */
4457 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4458 return 0;
4459}
4d295db0 4460
de6eae1f
YR		 4461static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4462 struct link_params *params,
4463 struct link_vars *vars)
4464{
4465 u8 link_up = 0;
4466 u16 val1, rx_sd;
4467 struct bnx2x *bp = params->bp;
4468 DP(NETIF_MSG_LINK, "read status 8705\n");
4469 bnx2x_cl45_read(bp, phy,
4470 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4471 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 4472
de6eae1f
YR		 4473 bnx2x_cl45_read(bp, phy,
4474 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4475 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 4476
de6eae1f
YR		 4477 bnx2x_cl45_read(bp, phy,
4478 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
c2c8b03e 4479
de6eae1f
YR		 4480 bnx2x_cl45_read(bp, phy,
4481 MDIO_PMA_DEVAD, 0xc809, &val1);
4482 bnx2x_cl45_read(bp, phy,
4483 MDIO_PMA_DEVAD, 0xc809, &val1);
c2c8b03e 4484
de6eae1f
YR		 4485 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4486 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4487 if (link_up) {
4488 vars->line_speed = SPEED_10000;
4489 bnx2x_ext_phy_resolve_fc(phy, params, vars);
62b29a5d 4490 }
de6eae1f
YR		 4491 return link_up;
4492}
d90d96ba 4493
de6eae1f
YR		 4494/******************************************************************/
4495/* SFP+ module Section */
4496/******************************************************************/
4497static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
4498 struct bnx2x_phy *phy,
4499 u8 port,
4500 u8 tx_en)
4501{
4502 u16 val;
d90d96ba 4503
de6eae1f
YR		 4504 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
4505 tx_en, port);
4506 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4507 bnx2x_cl45_read(bp, phy,
4508 MDIO_PMA_DEVAD,
4509 MDIO_PMA_REG_PHY_IDENTIFIER,
4510 &val);
d90d96ba 4511
de6eae1f
YR		 4512 if (tx_en)
4513 val &= ~(1<<15);
4514 else
4515 val |= (1<<15);
b7737c9b 4516
de6eae1f
YR		 4517 bnx2x_cl45_write(bp, phy,
4518 MDIO_PMA_DEVAD,
4519 MDIO_PMA_REG_PHY_IDENTIFIER,
4520 val);
b7737c9b
YR		 4521}
4522
de6eae1f
YR		 4523static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4524 struct link_params *params,
4525 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b
YR		 4526{
4527 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4528 u16 val = 0;
4529 u16 i;
4530 if (byte_cnt > 16) {
4531 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4532 " is limited to 0xf\n");
4533 return -EINVAL;
4534 }
4535 /* Set the read command byte count */
62b29a5d 4536 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4537 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4538 (byte_cnt | 0xa000));
ea4e040a 4539
de6eae1f
YR		 4540 /* Set the read command address */
4541 bnx2x_cl45_write(bp, phy,
4542 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4543 addr);
ea4e040a 4544
de6eae1f 4545 /* Activate read command */
62b29a5d 4546 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4547 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4548 0x2c0f);
ea4e040a 4549
de6eae1f
YR		 4550 /* Wait up to 500us for command complete status */
4551 for (i = 0; i < 100; i++) {
4552 bnx2x_cl45_read(bp, phy,
4553 MDIO_PMA_DEVAD,
4554 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4555 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4556 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4557 break;
4558 udelay(5);
62b29a5d 4559 }
62b29a5d 4560
de6eae1f
YR		 4561 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4562 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4563 DP(NETIF_MSG_LINK,
4564 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4565 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4566 return -EINVAL;
62b29a5d 4567 }
e10bc84d 4568
de6eae1f
YR		 4569 /* Read the buffer */
4570 for (i = 0; i < byte_cnt; i++) {
62b29a5d 4571 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4572 MDIO_PMA_DEVAD,
4573 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4574 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
62b29a5d 4575 }
6bbca910 4576
de6eae1f
YR		 4577 for (i = 0; i < 100; i++) {
4578 bnx2x_cl45_read(bp, phy,
4579 MDIO_PMA_DEVAD,
4580 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4581 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4582 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 4583 return 0;
de6eae1f
YR		 4584 msleep(1);
4585 }
4586 return -EINVAL;
b7737c9b 4587}
4d295db0 4588
de6eae1f
YR		 4589static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4590 struct link_params *params,
4591 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b 4592{
b7737c9b 4593 struct bnx2x *bp = params->bp;
de6eae1f 4594 u16 val, i;
ea4e040a 4595
de6eae1f
YR		 4596 if (byte_cnt > 16) {
4597 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4598 " is limited to 0xf\n");
4599 return -EINVAL;
4600 }
4d295db0 4601
de6eae1f
YR		 4602 /* Need to read from 1.8000 to clear it */
4603 bnx2x_cl45_read(bp, phy,
4604 MDIO_PMA_DEVAD,
4605 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4606 &val);
4d295db0 4607
de6eae1f 4608 /* Set the read command byte count */
62b29a5d 4609 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4610 MDIO_PMA_DEVAD,
4611 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4612 ((byte_cnt < 2) ? 2 : byte_cnt));
ea4e040a 4613
de6eae1f 4614 /* Set the read command address */
62b29a5d 4615 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4616 MDIO_PMA_DEVAD,
4617 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4618 addr);
4619 /* Set the destination address */
62b29a5d 4620 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4621 MDIO_PMA_DEVAD,
4622 0x8004,
4623 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
62b29a5d 4624
de6eae1f 4625 /* Activate read command */
62b29a5d 4626 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4627 MDIO_PMA_DEVAD,
4628 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4629 0x8002);
4630 /* Wait appropriate time for two-wire command to finish before
4631 polling the status register */
4632 msleep(1);
4d295db0 4633
de6eae1f
YR		 4634 /* Wait up to 500us for command complete status */
4635 for (i = 0; i < 100; i++) {
62b29a5d 4636 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4637 MDIO_PMA_DEVAD,
4638 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4639 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4640 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4641 break;
4642 udelay(5);
62b29a5d 4643 }
4d295db0 4644
de6eae1f
YR		 4645 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4646 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4647 DP(NETIF_MSG_LINK,
4648 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4649 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4650 return -EINVAL;
4651 }
62b29a5d 4652
de6eae1f
YR		 4653 /* Read the buffer */
4654 for (i = 0; i < byte_cnt; i++) {
4655 bnx2x_cl45_read(bp, phy,
4656 MDIO_PMA_DEVAD,
4657 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4658 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4659 }
4d295db0 4660
de6eae1f
YR		 4661 for (i = 0; i < 100; i++) {
4662 bnx2x_cl45_read(bp, phy,
4663 MDIO_PMA_DEVAD,
4664 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4665 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4666 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 4667 return 0;
de6eae1f 4668 msleep(1);
62b29a5d
YR		 4669 }
4670
de6eae1f 4671 return -EINVAL;
b7737c9b
YR		 4672}
4673
8d96286a 4674static u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4675 struct link_params *params, u16 addr,
4676 u8 byte_cnt, u8 *o_buf)
b7737c9b 4677{
de6eae1f
YR		 4678 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4679 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4680 byte_cnt, o_buf);
4681 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4682 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4683 byte_cnt, o_buf);
4684 return -EINVAL;
b7737c9b
YR		 4685}
4686
de6eae1f
YR		 4687static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4688 struct link_params *params,
4689 u16 *edc_mode)
b7737c9b
YR		 4690{
4691 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4692 u8 val, check_limiting_mode = 0;
4693 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 4694
de6eae1f
YR		 4695 /* First check for copper cable */
4696 if (bnx2x_read_sfp_module_eeprom(phy,
4697 params,
4698 SFP_EEPROM_CON_TYPE_ADDR,
4699 1,
4700 &val) != 0) {
4701 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4702 return -EINVAL;
4703 }
a1e4be39 4704
de6eae1f
YR		 4705 switch (val) {
4706 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4707 {
4708 u8 copper_module_type;
62b29a5d 4709
de6eae1f
YR		 4710 /* Check if its active cable( includes SFP+ module)
4711 of passive cable*/
4712 if (bnx2x_read_sfp_module_eeprom(phy,
4713 params,
4714 SFP_EEPROM_FC_TX_TECH_ADDR,
4715 1,
4716 &copper_module_type) !=
4717 0) {
4718 DP(NETIF_MSG_LINK,
4719 "Failed to read copper-cable-type"
4720 " from SFP+ EEPROM\n");
4721 return -EINVAL;
4722 }
4f60dab1 4723
de6eae1f
YR		 4724 if (copper_module_type &
4725 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4726 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4727 check_limiting_mode = 1;
4728 } else if (copper_module_type &
4729 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4730 DP(NETIF_MSG_LINK, "Passive Copper"
4731 " cable detected\n");
4732 *edc_mode =
4733 EDC_MODE_PASSIVE_DAC;
4734 } else {
4735 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4736 "type 0x%x !!!\n", copper_module_type);
4737 return -EINVAL;
4738 }
4739 break;
62b29a5d 4740 }
de6eae1f
YR		 4741 case SFP_EEPROM_CON_TYPE_VAL_LC:
4742 DP(NETIF_MSG_LINK, "Optic module detected\n");
4743 check_limiting_mode = 1;
4744 break;
4745 default:
4746 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4747 val);
4748 return -EINVAL;
62b29a5d 4749 }
2f904460 4750
de6eae1f
YR		 4751 if (check_limiting_mode) {
4752 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4753 if (bnx2x_read_sfp_module_eeprom(phy,
4754 params,
4755 SFP_EEPROM_OPTIONS_ADDR,
4756 SFP_EEPROM_OPTIONS_SIZE,
4757 options) != 0) {
4758 DP(NETIF_MSG_LINK, "Failed to read Option"
4759 " field from module EEPROM\n");
4760 return -EINVAL;
4761 }
4762 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4763 *edc_mode = EDC_MODE_LINEAR;
4764 else
4765 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 4766 }
de6eae1f 4767 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
62b29a5d 4768 return 0;
b7737c9b 4769}
de6eae1f
YR		 4770/* This function read the relevant field from the module ( SFP+ ),
4771 and verify it is compliant with this board */
4772static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4773 struct link_params *params)
b7737c9b
YR		 4774{
4775 struct bnx2x *bp = params->bp;
a22f0788
YR		 4776 u32 val, cmd;
4777 u32 fw_resp, fw_cmd_param;
de6eae1f
YR		 4778 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4779 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
a22f0788 4780 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
de6eae1f
YR		 4781 val = REG_RD(bp, params->shmem_base +
4782 offsetof(struct shmem_region, dev_info.
4783 port_feature_config[params->port].config));
4784 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4785 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4786 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4787 return 0;
4788 }
ea4e040a 4789
a22f0788
YR		 4790 if (params->feature_config_flags &
4791 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4792 /* Use specific phy request */
4793 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4794 } else if (params->feature_config_flags &
4795 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4796 /* Use first phy request only in case of non-dual media*/
4797 if (DUAL_MEDIA(params)) {
4798 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4799 "verification\n");
4800 return -EINVAL;
4801 }
4802 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4803 } else {
4804 /* No support in OPT MDL detection */
de6eae1f 4805 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
a22f0788 4806 "verification\n");
de6eae1f
YR		 4807 return -EINVAL;
4808 }
523224a3 4809
a22f0788
YR		 4810 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4811 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
de6eae1f
YR		 4812 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4813 DP(NETIF_MSG_LINK, "Approved module\n");
4814 return 0;
4815 }
b7737c9b 4816
de6eae1f
YR		 4817 /* format the warning message */
4818 if (bnx2x_read_sfp_module_eeprom(phy,
4819 params,
4820 SFP_EEPROM_VENDOR_NAME_ADDR,
4821 SFP_EEPROM_VENDOR_NAME_SIZE,
4822 (u8 *)vendor_name))
4823 vendor_name[0] = '\0';
4824 else
4825 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4826 if (bnx2x_read_sfp_module_eeprom(phy,
4827 params,
4828 SFP_EEPROM_PART_NO_ADDR,
4829 SFP_EEPROM_PART_NO_SIZE,
4830 (u8 *)vendor_pn))
4831 vendor_pn[0] = '\0';
4832 else
4833 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4834
4835 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
4836 " Port %d from %s part number %s\n",
4837 params->port, vendor_name, vendor_pn);
a22f0788 4838 phy->flags |= FLAGS_SFP_NOT_APPROVED;
de6eae1f 4839 return -EINVAL;
b7737c9b 4840}
7aa0711f 4841
de6eae1f
YR		 4842static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4843 struct link_params *params)
7aa0711f 4844
4d295db0 4845{
de6eae1f 4846 u8 val;
4d295db0 4847 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4848 u16 timeout;
4849 /* Initialization time after hot-plug may take up to 300ms for some
4850 phys type ( e.g. JDSU ) */
4851 for (timeout = 0; timeout < 60; timeout++) {
4852 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4853 == 0) {
4854 DP(NETIF_MSG_LINK, "SFP+ module initialization "
4855 "took %d ms\n", timeout * 5);
4856 return 0;
4857 }
4858 msleep(5);
4859 }
4860 return -EINVAL;
4861}
4d295db0 4862
de6eae1f
YR		 4863static void bnx2x_8727_power_module(struct bnx2x *bp,
4864 struct bnx2x_phy *phy,
4865 u8 is_power_up) {
4866 /* Make sure GPIOs are not using for LED mode */
4867 u16 val;
4868 /*
4869 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
4870 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4871 * output
4872 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4873 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4874 * where the 1st bit is the over-current(only input), and 2nd bit is
4875 * for power( only output )
4876 */
4d295db0 4877
de6eae1f
YR		 4878 /*
4879 * In case of NOC feature is disabled and power is up, set GPIO control
4880 * as input to enable listening of over-current indication
4881 */
4882 if (phy->flags & FLAGS_NOC)
4883 return;
4884 if (!(phy->flags &
4885 FLAGS_NOC) && is_power_up)
4886 val = (1<<4);
4887 else
4888 /*
4889 * Set GPIO control to OUTPUT, and set the power bit
4890 * to according to the is_power_up
4891 */
4892 val = ((!(is_power_up)) << 1);
4d295db0 4893
de6eae1f
YR		 4894 bnx2x_cl45_write(bp, phy,
4895 MDIO_PMA_DEVAD,
4896 MDIO_PMA_REG_8727_GPIO_CTRL,
4897 val);
4898}
4d295db0 4899
de6eae1f
YR		 4900static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4901 struct bnx2x_phy *phy,
4902 u16 edc_mode)
4903{
4904 u16 cur_limiting_mode;
4d295db0 4905
de6eae1f
YR		 4906 bnx2x_cl45_read(bp, phy,
4907 MDIO_PMA_DEVAD,
4908 MDIO_PMA_REG_ROM_VER2,
4909 &cur_limiting_mode);
4910 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4911 cur_limiting_mode);
4912
4913 if (edc_mode == EDC_MODE_LIMITING) {
4914 DP(NETIF_MSG_LINK,
4915 "Setting LIMITING MODE\n");
e10bc84d 4916 bnx2x_cl45_write(bp, phy,
62b29a5d 4917 MDIO_PMA_DEVAD,
de6eae1f
YR		 4918 MDIO_PMA_REG_ROM_VER2,
4919 EDC_MODE_LIMITING);
4920 } else { /* LRM mode ( default )*/
4d295db0 4921
de6eae1f 4922 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4d295db0 4923
de6eae1f
YR		 4924 /* Changing to LRM mode takes quite few seconds.
4925 So do it only if current mode is limiting
4926 ( default is LRM )*/
4927 if (cur_limiting_mode != EDC_MODE_LIMITING)
4928 return 0;
4d295db0 4929
de6eae1f
YR		 4930 bnx2x_cl45_write(bp, phy,
4931 MDIO_PMA_DEVAD,
4932 MDIO_PMA_REG_LRM_MODE,
4933 0);
4934 bnx2x_cl45_write(bp, phy,
4935 MDIO_PMA_DEVAD,
4936 MDIO_PMA_REG_ROM_VER2,
4937 0x128);
4938 bnx2x_cl45_write(bp, phy,
4939 MDIO_PMA_DEVAD,
4940 MDIO_PMA_REG_MISC_CTRL0,
4941 0x4008);
4942 bnx2x_cl45_write(bp, phy,
4943 MDIO_PMA_DEVAD,
4944 MDIO_PMA_REG_LRM_MODE,
4945 0xaaaa);
4d295db0 4946 }
de6eae1f 4947 return 0;
4d295db0
EG		 4948}
4949
de6eae1f
YR		 4950static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4951 struct bnx2x_phy *phy,
4952 u16 edc_mode)
ea4e040a 4953{
de6eae1f
YR		 4954 u16 phy_identifier;
4955 u16 rom_ver2_val;
62b29a5d 4956 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4957 MDIO_PMA_DEVAD,
4958 MDIO_PMA_REG_PHY_IDENTIFIER,
4959 &phy_identifier);
ea4e040a 4960
de6eae1f
YR		 4961 bnx2x_cl45_write(bp, phy,
4962 MDIO_PMA_DEVAD,
4963 MDIO_PMA_REG_PHY_IDENTIFIER,
4964 (phy_identifier & ~(1<<9)));
ea4e040a 4965
62b29a5d 4966 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4967 MDIO_PMA_DEVAD,
4968 MDIO_PMA_REG_ROM_VER2,
4969 &rom_ver2_val);
4970 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4971 bnx2x_cl45_write(bp, phy,
4972 MDIO_PMA_DEVAD,
4973 MDIO_PMA_REG_ROM_VER2,
4974 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4d295db0 4975
de6eae1f
YR		 4976 bnx2x_cl45_write(bp, phy,
4977 MDIO_PMA_DEVAD,
4978 MDIO_PMA_REG_PHY_IDENTIFIER,
4979 (phy_identifier | (1<<9)));
4d295db0 4980
de6eae1f 4981 return 0;
b7737c9b 4982}
ea4e040a 4983
a22f0788
YR		 4984static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4985 struct link_params *params,
4986 u32 action)
4987{
4988 struct bnx2x *bp = params->bp;
4989
4990 switch (action) {
4991 case DISABLE_TX:
4992 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4993 break;
4994 case ENABLE_TX:
4995 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
4996 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4997 break;
4998 default:
4999 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
5000 action);
5001 return;
5002 }
5003}
5004
de6eae1f
YR		 5005static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5006 struct link_params *params)
b7737c9b 5007{
b7737c9b 5008 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5009 u16 edc_mode;
5010 u8 rc = 0;
ea4e040a 5011
de6eae1f
YR		 5012 u32 val = REG_RD(bp, params->shmem_base +
5013 offsetof(struct shmem_region, dev_info.
5014 port_feature_config[params->port].config));
62b29a5d 5015
de6eae1f
YR		 5016 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5017 params->port);
5018
5019 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5020 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5021 return -EINVAL;
5022 } else if (bnx2x_verify_sfp_module(phy, params) !=
5023 0) {
5024 /* check SFP+ module compatibility */
5025 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5026 rc = -EINVAL;
5027 /* Turn on fault module-detected led */
5028 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
5029 MISC_REGISTERS_GPIO_HIGH,
5030 params->port);
5031 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
5032 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5033 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
5034 /* Shutdown SFP+ module */
5035 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5036 bnx2x_8727_power_module(bp, phy, 0);
5037 return rc;
5038 }
5039 } else {
5040 /* Turn off fault module-detected led */
5041 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
5042 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
5043 MISC_REGISTERS_GPIO_LOW,
5044 params->port);
62b29a5d 5045 }
b7737c9b 5046
de6eae1f
YR		 5047 /* power up the SFP module */
5048 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
5049 bnx2x_8727_power_module(bp, phy, 1);
c18aa15d 5050
de6eae1f
YR		 5051 /* Check and set limiting mode / LRM mode on 8726.
5052 On 8727 it is done automatically */
5053 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
5054 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
5055 else
5056 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
5057 /*
5058 * Enable transmit for this module if the module is approved, or
5059 * if unapproved modules should also enable the Tx laser
5060 */
5061 if (rc == 0 ||
5062 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5063 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5064 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
5065 else
5066 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
b7737c9b 5067
de6eae1f
YR		 5068 return rc;
5069}
5070
5071void bnx2x_handle_module_detect_int(struct link_params *params)
b7737c9b
YR		 5072{
5073 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5074 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5075 u32 gpio_val;
5076 u8 port = params->port;
4d295db0 5077
de6eae1f
YR		 5078 /* Set valid module led off */
5079 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
5080 MISC_REGISTERS_GPIO_HIGH,
5081 params->port);
4d295db0 5082
de6eae1f
YR		 5083 /* Get current gpio val refelecting module plugged in / out*/
5084 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
62b29a5d 5085
de6eae1f
YR		 5086 /* Call the handling function in case module is detected */
5087 if (gpio_val == 0) {
4d295db0 5088
de6eae1f
YR		 5089 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5090 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5091 port);
4d295db0 5092
de6eae1f
YR		 5093 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5094 bnx2x_sfp_module_detection(phy, params);
5095 else
5096 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5097 } else {
5098 u32 val = REG_RD(bp, params->shmem_base +
5099 offsetof(struct shmem_region, dev_info.
5100 port_feature_config[params->port].
5101 config));
4d295db0 5102
de6eae1f
YR		 5103 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5104 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5105 port);
5106 /* Module was plugged out. */
5107 /* Disable transmit for this module */
5108 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5109 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5110 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
62b29a5d 5111 }
de6eae1f 5112}
62b29a5d 5113
de6eae1f
YR		 5114/******************************************************************/
5115/* common BCM8706/BCM8726 PHY SECTION */
5116/******************************************************************/
5117static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5118 struct link_params *params,
5119 struct link_vars *vars)
5120{
5121 u8 link_up = 0;
5122 u16 val1, val2, rx_sd, pcs_status;
5123 struct bnx2x *bp = params->bp;
5124 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5125 /* Clear RX Alarm*/
62b29a5d 5126 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5127 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5128 /* clear LASI indication*/
5129 bnx2x_cl45_read(bp, phy,
5130 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5131 bnx2x_cl45_read(bp, phy,
5132 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5133 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
62b29a5d
YR		 5134
5135 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5136 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5137 bnx2x_cl45_read(bp, phy,
5138 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5139 bnx2x_cl45_read(bp, phy,
5140 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5141 bnx2x_cl45_read(bp, phy,
5142 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
62b29a5d 5143
de6eae1f
YR		 5144 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5145 " link_status 0x%x\n", rx_sd, pcs_status, val2);
5146 /* link is up if both bit 0 of pmd_rx_sd and
5147 * bit 0 of pcs_status are set, or if the autoneg bit
5148 * 1 is set
5149 */
5150 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5151 if (link_up) {
5152 if (val2 & (1<<1))
5153 vars->line_speed = SPEED_1000;
5154 else
5155 vars->line_speed = SPEED_10000;
62b29a5d 5156 bnx2x_ext_phy_resolve_fc(phy, params, vars);
de6eae1f 5157 }
62b29a5d 5158 return link_up;
b7737c9b 5159}
62b29a5d 5160
de6eae1f
YR		 5161/******************************************************************/
5162/* BCM8706 PHY SECTION */
5163/******************************************************************/
5164static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 5165 struct link_params *params,
5166 struct link_vars *vars)
5167{
de6eae1f 5168 u16 cnt, val;
b7737c9b 5169 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5170 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5171 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5172 /* HW reset */
5173 bnx2x_ext_phy_hw_reset(bp, params->port);
5174 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5175 bnx2x_wait_reset_complete(bp, phy);
ea4e040a 5176
de6eae1f
YR		 5177 /* Wait until fw is loaded */
5178 for (cnt = 0; cnt < 100; cnt++) {
5179 bnx2x_cl45_read(bp, phy,
5180 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5181 if (val)
5182 break;
5183 msleep(10);
5184 }
5185 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5186 if ((params->feature_config_flags &
5187 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5188 u8 i;
5189 u16 reg;
5190 for (i = 0; i < 4; i++) {
5191 reg = MDIO_XS_8706_REG_BANK_RX0 +
5192 i*(MDIO_XS_8706_REG_BANK_RX1 -
5193 MDIO_XS_8706_REG_BANK_RX0);
5194 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5195 /* Clear first 3 bits of the control */
5196 val &= ~0x7;
5197 /* Set control bits according to configuration */
5198 val |= (phy->rx_preemphasis[i] & 0x7);
5199 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5200 " reg 0x%x <-- val 0x%x\n", reg, val);
5201 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5202 }
5203 }
5204 /* Force speed */
5205 if (phy->req_line_speed == SPEED_10000) {
5206 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
ea4e040a 5207
de6eae1f
YR		 5208 bnx2x_cl45_write(bp, phy,
5209 MDIO_PMA_DEVAD,
5210 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5211 bnx2x_cl45_write(bp, phy,
5212 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5213 } else {
5214 /* Force 1Gbps using autoneg with 1G advertisment */
6bbca910 5215
de6eae1f
YR		 5216 /* Allow CL37 through CL73 */
5217 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5218 bnx2x_cl45_write(bp, phy,
5219 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6bbca910 5220
de6eae1f
YR		 5221 /* Enable Full-Duplex advertisment on CL37 */
5222 bnx2x_cl45_write(bp, phy,
5223 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5224 /* Enable CL37 AN */
5225 bnx2x_cl45_write(bp, phy,
5226 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5227 /* 1G support */
5228 bnx2x_cl45_write(bp, phy,
5229 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
6bbca910 5230
de6eae1f
YR		 5231 /* Enable clause 73 AN */
5232 bnx2x_cl45_write(bp, phy,
5233 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5234 bnx2x_cl45_write(bp, phy,
5235 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5236 0x0400);
5237 bnx2x_cl45_write(bp, phy,
5238 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5239 0x0004);
5240 }
5241 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5242 return 0;
5243}
ea4e040a 5244
de6eae1f
YR		 5245static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5246 struct link_params *params,
5247 struct link_vars *vars)
5248{
5249 return bnx2x_8706_8726_read_status(phy, params, vars);
5250}
6bbca910 5251
de6eae1f
YR		 5252/******************************************************************/
5253/* BCM8726 PHY SECTION */
5254/******************************************************************/
5255static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5256 struct link_params *params)
5257{
5258 struct bnx2x *bp = params->bp;
5259 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5260 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5261}
62b29a5d 5262
de6eae1f
YR		 5263static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5264 struct link_params *params)
5265{
5266 struct bnx2x *bp = params->bp;
5267 /* Need to wait 100ms after reset */
5268 msleep(100);
62b29a5d 5269
de6eae1f
YR		 5270 /* Micro controller re-boot */
5271 bnx2x_cl45_write(bp, phy,
5272 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
62b29a5d 5273
de6eae1f
YR		 5274 /* Set soft reset */
5275 bnx2x_cl45_write(bp, phy,
5276 MDIO_PMA_DEVAD,
5277 MDIO_PMA_REG_GEN_CTRL,
5278 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
62b29a5d 5279
de6eae1f
YR		 5280 bnx2x_cl45_write(bp, phy,
5281 MDIO_PMA_DEVAD,
5282 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6bbca910 5283
de6eae1f
YR		 5284 bnx2x_cl45_write(bp, phy,
5285 MDIO_PMA_DEVAD,
5286 MDIO_PMA_REG_GEN_CTRL,
5287 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5288
5289 /* wait for 150ms for microcode load */
5290 msleep(150);
5291
5292 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5293 bnx2x_cl45_write(bp, phy,
5294 MDIO_PMA_DEVAD,
5295 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5296
5297 msleep(200);
5298 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
b7737c9b
YR		 5299}
5300
de6eae1f 5301static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 5302 struct link_params *params,
5303 struct link_vars *vars)
5304{
5305 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5306 u16 val1;
5307 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
62b29a5d
YR		 5308 if (link_up) {
5309 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5310 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5311 &val1);
5312 if (val1 & (1<<15)) {
5313 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5314 link_up = 0;
5315 vars->line_speed = 0;
5316 }
62b29a5d
YR		 5317 }
5318 return link_up;
b7737c9b
YR		 5319}
5320
de6eae1f
YR		 5321
5322static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5323 struct link_params *params,
5324 struct link_vars *vars)
b7737c9b
YR		 5325{
5326 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5327 u32 val;
5328 u32 swap_val, swap_override, aeu_gpio_mask, offset;
5329 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5330 /* Restore normal power mode*/
5331 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5332 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 5333
de6eae1f
YR		 5334 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5335 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
62b29a5d 5336
de6eae1f
YR		 5337 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5338 bnx2x_wait_reset_complete(bp, phy);
62b29a5d 5339
de6eae1f 5340 bnx2x_8726_external_rom_boot(phy, params);
62b29a5d 5341
de6eae1f
YR		 5342 /* Need to call module detected on initialization since
5343 the module detection triggered by actual module
5344 insertion might occur before driver is loaded, and when
5345 driver is loaded, it reset all registers, including the
5346 transmitter */
5347 bnx2x_sfp_module_detection(phy, params);
62b29a5d 5348
de6eae1f
YR		 5349 if (phy->req_line_speed == SPEED_1000) {
5350 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5351 bnx2x_cl45_write(bp, phy,
5352 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5353 bnx2x_cl45_write(bp, phy,
5354 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5355 bnx2x_cl45_write(bp, phy,
5356 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5357 bnx2x_cl45_write(bp, phy,
5358 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5359 0x400);
5360 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5361 (phy->speed_cap_mask &
5362 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5363 ((phy->speed_cap_mask &
5364 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5365 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5366 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5367 /* Set Flow control */
5368 bnx2x_ext_phy_set_pause(params, phy, vars);
5369 bnx2x_cl45_write(bp, phy,
5370 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5371 bnx2x_cl45_write(bp, phy,
5372 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5373 bnx2x_cl45_write(bp, phy,
5374 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5375 bnx2x_cl45_write(bp, phy,
5376 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5377 bnx2x_cl45_write(bp, phy,
5378 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5379 /* Enable RX-ALARM control to receive
5380 interrupt for 1G speed change */
5381 bnx2x_cl45_write(bp, phy,
5382 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5383 bnx2x_cl45_write(bp, phy,
5384 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5385 0x400);
62b29a5d 5386
de6eae1f
YR		 5387 } else { /* Default 10G. Set only LASI control */
5388 bnx2x_cl45_write(bp, phy,
5389 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
7aa0711f
YR		 5390 }
5391
de6eae1f
YR		 5392 /* Set TX PreEmphasis if needed */
5393 if ((params->feature_config_flags &
5394 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5395 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5396 "TX_CTRL2 0x%x\n",
5397 phy->tx_preemphasis[0],
5398 phy->tx_preemphasis[1]);
5399 bnx2x_cl45_write(bp, phy,
5400 MDIO_PMA_DEVAD,
5401 MDIO_PMA_REG_8726_TX_CTRL1,
5402 phy->tx_preemphasis[0]);
c18aa15d 5403
de6eae1f
YR		 5404 bnx2x_cl45_write(bp, phy,
5405 MDIO_PMA_DEVAD,
5406 MDIO_PMA_REG_8726_TX_CTRL2,
5407 phy->tx_preemphasis[1]);
5408 }
ab6ad5a4 5409
de6eae1f
YR		 5410 /* Set GPIO3 to trigger SFP+ module insertion/removal */
5411 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5412 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
ea4e040a 5413
de6eae1f
YR		 5414 /* The GPIO should be swapped if the swap register is set and active */
5415 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5416 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
ea4e040a 5417
de6eae1f
YR		 5418 /* Select function upon port-swap configuration */
5419 if (params->port == 0) {
5420 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5421 aeu_gpio_mask = (swap_val && swap_override) ?
5422 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5423 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5424 } else {
5425 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5426 aeu_gpio_mask = (swap_val && swap_override) ?
5427 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5428 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
ea4e040a 5429 }
de6eae1f
YR		 5430 val = REG_RD(bp, offset);
5431 /* add GPIO3 to group */
5432 val |= aeu_gpio_mask;
5433 REG_WR(bp, offset, val);
5434 return 0;
ab6ad5a4 5435
ea4e040a
YR		 5436}
5437
de6eae1f
YR		 5438static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5439 struct link_params *params)
2f904460 5440{
de6eae1f
YR		 5441 struct bnx2x *bp = params->bp;
5442 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5443 /* Set serial boot control for external load */
5444 bnx2x_cl45_write(bp, phy,
5445 MDIO_PMA_DEVAD,
5446 MDIO_PMA_REG_GEN_CTRL, 0x0001);
5447}
5448
5449/******************************************************************/
5450/* BCM8727 PHY SECTION */
5451/******************************************************************/
7f02c4ad
YR		 5452
5453static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5454 struct link_params *params, u8 mode)
5455{
5456 struct bnx2x *bp = params->bp;
5457 u16 led_mode_bitmask = 0;
5458 u16 gpio_pins_bitmask = 0;
5459 u16 val;
5460 /* Only NOC flavor requires to set the LED specifically */
5461 if (!(phy->flags & FLAGS_NOC))
5462 return;
5463 switch (mode) {
5464 case LED_MODE_FRONT_PANEL_OFF:
5465 case LED_MODE_OFF:
5466 led_mode_bitmask = 0;
5467 gpio_pins_bitmask = 0x03;
5468 break;
5469 case LED_MODE_ON:
5470 led_mode_bitmask = 0;
5471 gpio_pins_bitmask = 0x02;
5472 break;
5473 case LED_MODE_OPER:
5474 led_mode_bitmask = 0x60;
5475 gpio_pins_bitmask = 0x11;
5476 break;
5477 }
5478 bnx2x_cl45_read(bp, phy,
5479 MDIO_PMA_DEVAD,
5480 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5481 &val);
5482 val &= 0xff8f;
5483 val |= led_mode_bitmask;
5484 bnx2x_cl45_write(bp, phy,
5485 MDIO_PMA_DEVAD,
5486 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5487 val);
5488 bnx2x_cl45_read(bp, phy,
5489 MDIO_PMA_DEVAD,
5490 MDIO_PMA_REG_8727_GPIO_CTRL,
5491 &val);
5492 val &= 0xffe0;
5493 val |= gpio_pins_bitmask;
5494 bnx2x_cl45_write(bp, phy,
5495 MDIO_PMA_DEVAD,
5496 MDIO_PMA_REG_8727_GPIO_CTRL,
5497 val);
5498}
de6eae1f
YR		 5499static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5500 struct link_params *params) {
5501 u32 swap_val, swap_override;
5502 u8 port;
5503 /**
5504 * The PHY reset is controlled by GPIO 1. Fake the port number
5505 * to cancel the swap done in set_gpio()
2f904460 5506 */
de6eae1f
YR		 5507 struct bnx2x *bp = params->bp;
5508 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5509 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5510 port = (swap_val && swap_override) ^ 1;
5511 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5512 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2f904460 5513}
e10bc84d 5514
de6eae1f
YR		 5515static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
5516 struct link_params *params,
5517 struct link_vars *vars)
ea4e040a 5518{
de6eae1f
YR		 5519 u16 tmp1, val, mod_abs;
5520 u16 rx_alarm_ctrl_val;
5521 u16 lasi_ctrl_val;
ea4e040a 5522 struct bnx2x *bp = params->bp;
de6eae1f 5523 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
ea4e040a 5524
de6eae1f
YR		 5525 bnx2x_wait_reset_complete(bp, phy);
5526 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5527 lasi_ctrl_val = 0x0004;
ea4e040a 5528
de6eae1f
YR		 5529 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5530 /* enable LASI */
5531 bnx2x_cl45_write(bp, phy,
5532 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5533 rx_alarm_ctrl_val);
ea4e040a 5534
de6eae1f
YR		 5535 bnx2x_cl45_write(bp, phy,
5536 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
ea4e040a 5537
de6eae1f
YR		 5538 /* Initially configure MOD_ABS to interrupt when
5539 module is presence( bit 8) */
5540 bnx2x_cl45_read(bp, phy,
5541 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5542 /* Set EDC off by setting OPTXLOS signal input to low
5543 (bit 9).
5544 When the EDC is off it locks onto a reference clock and
5545 avoids becoming 'lost'.*/
7f02c4ad
YR		 5546 mod_abs &= ~(1<<8);
5547 if (!(phy->flags & FLAGS_NOC))
5548 mod_abs &= ~(1<<9);
de6eae1f
YR		 5549 bnx2x_cl45_write(bp, phy,
5550 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5551
ea4e040a 5552
de6eae1f
YR		 5553 /* Make MOD_ABS give interrupt on change */
5554 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5555 &val);
5556 val |= (1<<12);
7f02c4ad
YR		 5557 if (phy->flags & FLAGS_NOC)
5558 val |= (3<<5);
b7737c9b 5559
7f02c4ad
YR		 5560 /**
5561 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5562 * status which reflect SFP+ module over-current
5563 */
5564 if (!(phy->flags & FLAGS_NOC))
5565 val &= 0xff8f; /* Reset bits 4-6 */
de6eae1f
YR		 5566 bnx2x_cl45_write(bp, phy,
5567 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
ea4e040a 5568
de6eae1f
YR		 5569 bnx2x_8727_power_module(bp, phy, 1);
5570
5571 bnx2x_cl45_read(bp, phy,
5572 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5573
5574 bnx2x_cl45_read(bp, phy,
5575 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5576
5577 /* Set option 1G speed */
5578 if (phy->req_line_speed == SPEED_1000) {
5579 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5580 bnx2x_cl45_write(bp, phy,
5581 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5582 bnx2x_cl45_write(bp, phy,
5583 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5584 bnx2x_cl45_read(bp, phy,
5585 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5586 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
a22f0788
YR		 5587 /**
5588 * Power down the XAUI until link is up in case of dual-media
5589 * and 1G
5590 */
5591 if (DUAL_MEDIA(params)) {
5592 bnx2x_cl45_read(bp, phy,
5593 MDIO_PMA_DEVAD,
5594 MDIO_PMA_REG_8727_PCS_GP, &val);
5595 val |= (3<<10);
5596 bnx2x_cl45_write(bp, phy,
5597 MDIO_PMA_DEVAD,
5598 MDIO_PMA_REG_8727_PCS_GP, val);
5599 }
de6eae1f
YR		 5600 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5601 ((phy->speed_cap_mask &
5602 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5603 ((phy->speed_cap_mask &
5604 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5605 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5606
5607 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5608 bnx2x_cl45_write(bp, phy,
5609 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5610 bnx2x_cl45_write(bp, phy,
5611 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5612 } else {
5613 /**
5614 * Since the 8727 has only single reset pin, need to set the 10G
5615 * registers although it is default
5616 */
5617 bnx2x_cl45_write(bp, phy,
5618 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5619 0x0020);
5620 bnx2x_cl45_write(bp, phy,
5621 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5622 bnx2x_cl45_write(bp, phy,
5623 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5624 bnx2x_cl45_write(bp, phy,
5625 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5626 0x0008);
ea4e040a 5627 }
ea4e040a 5628
de6eae1f
YR		 5629 /* Set 2-wire transfer rate of SFP+ module EEPROM
5630 * to 100Khz since some DACs(direct attached cables) do
5631 * not work at 400Khz.
5632 */
5633 bnx2x_cl45_write(bp, phy,
5634 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5635 0xa001);
b7737c9b 5636
de6eae1f
YR		 5637 /* Set TX PreEmphasis if needed */
5638 if ((params->feature_config_flags &
5639 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5640 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5641 phy->tx_preemphasis[0],
5642 phy->tx_preemphasis[1]);
5643 bnx2x_cl45_write(bp, phy,
5644 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5645 phy->tx_preemphasis[0]);
ea4e040a 5646
de6eae1f
YR		 5647 bnx2x_cl45_write(bp, phy,
5648 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5649 phy->tx_preemphasis[1]);
5650 }
ea4e040a 5651
de6eae1f 5652 return 0;
ea4e040a
YR		 5653}
5654
de6eae1f
YR		 5655static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5656 struct link_params *params)
ea4e040a 5657{
ea4e040a 5658 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5659 u16 mod_abs, rx_alarm_status;
5660 u32 val = REG_RD(bp, params->shmem_base +
5661 offsetof(struct shmem_region, dev_info.
5662 port_feature_config[params->port].
5663 config));
5664 bnx2x_cl45_read(bp, phy,
5665 MDIO_PMA_DEVAD,
5666 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5667 if (mod_abs & (1<<8)) {
ea4e040a 5668
de6eae1f
YR		 5669 /* Module is absent */
5670 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5671 "show module is absent\n");
ea4e040a 5672
de6eae1f
YR		 5673 /* 1. Set mod_abs to detect next module
5674 presence event
5675 2. Set EDC off by setting OPTXLOS signal input to low
5676 (bit 9).
5677 When the EDC is off it locks onto a reference clock and
5678 avoids becoming 'lost'.*/
7f02c4ad
YR		 5679 mod_abs &= ~(1<<8);
5680 if (!(phy->flags & FLAGS_NOC))
5681 mod_abs &= ~(1<<9);
de6eae1f
YR		 5682 bnx2x_cl45_write(bp, phy,
5683 MDIO_PMA_DEVAD,
5684 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5685
de6eae1f
YR		 5686 /* Clear RX alarm since it stays up as long as
5687 the mod_abs wasn't changed */
5688 bnx2x_cl45_read(bp, phy,
5689 MDIO_PMA_DEVAD,
5690 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 5691
de6eae1f
YR		 5692 } else {
5693 /* Module is present */
5694 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5695 "show module is present\n");
5696 /* First thing, disable transmitter,
5697 and if the module is ok, the
5698 module_detection will enable it*/
ea4e040a 5699
de6eae1f
YR		 5700 /* 1. Set mod_abs to detect next module
5701 absent event ( bit 8)
5702 2. Restore the default polarity of the OPRXLOS signal and
5703 this signal will then correctly indicate the presence or
5704 absence of the Rx signal. (bit 9) */
7f02c4ad
YR		 5705 mod_abs |= (1<<8);
5706 if (!(phy->flags & FLAGS_NOC))
5707 mod_abs |= (1<<9);
e10bc84d 5708 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 5709 MDIO_PMA_DEVAD,
5710 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5711
de6eae1f
YR		 5712 /* Clear RX alarm since it stays up as long as
5713 the mod_abs wasn't changed. This is need to be done
5714 before calling the module detection, otherwise it will clear
5715 the link update alarm */
5716 bnx2x_cl45_read(bp, phy,
5717 MDIO_PMA_DEVAD,
5718 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 5719
ea4e040a 5720
de6eae1f
YR		 5721 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5722 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5723 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5724
5725 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5726 bnx2x_sfp_module_detection(phy, params);
5727 else
5728 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
ea4e040a 5729 }
de6eae1f
YR		 5730
5731 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5732 rx_alarm_status);
5733 /* No need to check link status in case of
5734 module plugged in/out */
ea4e040a
YR		 5735}
5736
de6eae1f
YR		 5737static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5738 struct link_params *params,
5739 struct link_vars *vars)
5740
ea4e040a
YR		 5741{
5742 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5743 u8 link_up = 0;
5744 u16 link_status = 0;
a22f0788
YR		 5745 u16 rx_alarm_status, lasi_ctrl, val1;
5746
5747 /* If PHY is not initialized, do not check link status */
5748 bnx2x_cl45_read(bp, phy,
5749 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5750 &lasi_ctrl);
5751 if (!lasi_ctrl)
5752 return 0;
5753
de6eae1f
YR		 5754 /* Check the LASI */
5755 bnx2x_cl45_read(bp, phy,
5756 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5757 &rx_alarm_status);
5758 vars->line_speed = 0;
5759 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
5760
5761 bnx2x_cl45_read(bp, phy,
5762 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5763
5764 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5765
5766 /* Clear MSG-OUT */
5767 bnx2x_cl45_read(bp, phy,
5768 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5769
5770 /**
5771 * If a module is present and there is need to check
5772 * for over current
5773 */
5774 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5775 /* Check over-current using 8727 GPIO0 input*/
5776 bnx2x_cl45_read(bp, phy,
5777 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5778 &val1);
5779
5780 if ((val1 & (1<<8)) == 0) {
5781 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5782 " on port %d\n", params->port);
5783 netdev_err(bp->dev, "Error: Power fault on Port %d has"
5784 " been detected and the power to "
5785 "that SFP+ module has been removed"
5786 " to prevent failure of the card."
5787 " Please remove the SFP+ module and"
5788 " restart the system to clear this"
5789 " error.\n",
5790 params->port);
5791
5792 /*
5793 * Disable all RX_ALARMs except for
5794 * mod_abs
5795 */
5796 bnx2x_cl45_write(bp, phy,
5797 MDIO_PMA_DEVAD,
5798 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5799
5800 bnx2x_cl45_read(bp, phy,
5801 MDIO_PMA_DEVAD,
5802 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5803 /* Wait for module_absent_event */
5804 val1 |= (1<<8);
5805 bnx2x_cl45_write(bp, phy,
5806 MDIO_PMA_DEVAD,
5807 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5808 /* Clear RX alarm */
5809 bnx2x_cl45_read(bp, phy,
5810 MDIO_PMA_DEVAD,
5811 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5812 return 0;
5813 }
5814 } /* Over current check */
5815
5816 /* When module absent bit is set, check module */
5817 if (rx_alarm_status & (1<<5)) {
5818 bnx2x_8727_handle_mod_abs(phy, params);
5819 /* Enable all mod_abs and link detection bits */
5820 bnx2x_cl45_write(bp, phy,
5821 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5822 ((1<<5) | (1<<2)));
5823 }
a22f0788
YR		 5824 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5825 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
de6eae1f
YR		 5826 /* If transmitter is disabled, ignore false link up indication */
5827 bnx2x_cl45_read(bp, phy,
5828 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5829 if (val1 & (1<<15)) {
5830 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5831 return 0;
5832 }
5833
5834 bnx2x_cl45_read(bp, phy,
5835 MDIO_PMA_DEVAD,
5836 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5837
5838 /* Bits 0..2 --> speed detected,
5839 bits 13..15--> link is down */
5840 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5841 link_up = 1;
5842 vars->line_speed = SPEED_10000;
5843 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5844 link_up = 1;
5845 vars->line_speed = SPEED_1000;
5846 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5847 params->port);
5848 } else {
5849 link_up = 0;
5850 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5851 params->port);
5852 }
5853 if (link_up)
5854 bnx2x_ext_phy_resolve_fc(phy, params, vars);
a22f0788
YR		 5855
5856 if ((DUAL_MEDIA(params)) &&
5857 (phy->req_line_speed == SPEED_1000)) {
5858 bnx2x_cl45_read(bp, phy,
5859 MDIO_PMA_DEVAD,
5860 MDIO_PMA_REG_8727_PCS_GP, &val1);
5861 /**
5862 * In case of dual-media board and 1G, power up the XAUI side,
5863 * otherwise power it down. For 10G it is done automatically
5864 */
5865 if (link_up)
5866 val1 &= ~(3<<10);
5867 else
5868 val1 |= (3<<10);
5869 bnx2x_cl45_write(bp, phy,
5870 MDIO_PMA_DEVAD,
5871 MDIO_PMA_REG_8727_PCS_GP, val1);
5872 }
de6eae1f 5873 return link_up;
b7737c9b 5874}
ea4e040a 5875
de6eae1f
YR		 5876static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5877 struct link_params *params)
b7737c9b
YR		 5878{
5879 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5880 /* Disable Transmitter */
5881 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
a22f0788
YR		 5882 /* Clear LASI */
5883 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5884
ea4e040a 5885}
c18aa15d 5886
de6eae1f
YR		 5887/******************************************************************/
5888/* BCM8481/BCM84823/BCM84833 PHY SECTION */
5889/******************************************************************/
5890static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5891 struct link_params *params)
ea4e040a 5892{
de6eae1f
YR		 5893 u16 val, fw_ver1, fw_ver2, cnt;
5894 struct bnx2x *bp = params->bp;
ea4e040a 5895
de6eae1f
YR		 5896 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
5897 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
5898 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
5899 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5900 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
5901 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
5902 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
ea4e040a 5903
de6eae1f
YR		 5904 for (cnt = 0; cnt < 100; cnt++) {
5905 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5906 if (val & 1)
5907 break;
5908 udelay(5);
5909 }
5910 if (cnt == 100) {
5911 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
5912 bnx2x_save_spirom_version(bp, params->port, 0,
5913 phy->ver_addr);
5914 return;
5915 }
ea4e040a 5916
ea4e040a 5917
de6eae1f
YR		 5918 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
5919 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
5920 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5921 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
5922 for (cnt = 0; cnt < 100; cnt++) {
5923 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5924 if (val & 1)
5925 break;
5926 udelay(5);
5927 }
5928 if (cnt == 100) {
5929 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
5930 bnx2x_save_spirom_version(bp, params->port, 0,
5931 phy->ver_addr);
5932 return;
ea4e040a
YR		 5933 }
5934
de6eae1f
YR		 5935 /* lower 16 bits of the register SPI_FW_STATUS */
5936 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
5937 /* upper 16 bits of register SPI_FW_STATUS */
5938 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
ea4e040a 5939
de6eae1f
YR		 5940 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
5941 phy->ver_addr);
5942}
ea4e040a 5943
de6eae1f
YR		 5944static void bnx2x_848xx_set_led(struct bnx2x *bp,
5945 struct bnx2x_phy *phy)
ea4e040a 5946{
de6eae1f 5947 u16 val;
7846e471 5948
de6eae1f
YR		 5949 /* PHYC_CTL_LED_CTL */
5950 bnx2x_cl45_read(bp, phy,
5951 MDIO_PMA_DEVAD,
5952 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
5953 val &= 0xFE00;
5954 val |= 0x0092;
345b5d52 5955
de6eae1f
YR		 5956 bnx2x_cl45_write(bp, phy,
5957 MDIO_PMA_DEVAD,
5958 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
ea4e040a 5959
de6eae1f
YR		 5960 bnx2x_cl45_write(bp, phy,
5961 MDIO_PMA_DEVAD,
5962 MDIO_PMA_REG_8481_LED1_MASK,
5963 0x80);
ea4e040a 5964
de6eae1f
YR		 5965 bnx2x_cl45_write(bp, phy,
5966 MDIO_PMA_DEVAD,
5967 MDIO_PMA_REG_8481_LED2_MASK,
5968 0x18);
ea4e040a 5969
de6eae1f
YR		 5970 bnx2x_cl45_write(bp, phy,
5971 MDIO_PMA_DEVAD,
5972 MDIO_PMA_REG_8481_LED3_MASK,
5973 0x0040);
ea4e040a 5974
de6eae1f
YR		 5975 /* 'Interrupt Mask' */
5976 bnx2x_cl45_write(bp, phy,
5977 MDIO_AN_DEVAD,
5978 0xFFFB, 0xFFFD);
ea4e040a
YR		 5979}
5980
de6eae1f 5981static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
a22f0788
YR		 5982 struct link_params *params,
5983 struct link_vars *vars)
ea4e040a 5984{
c18aa15d 5985 struct bnx2x *bp = params->bp;
de6eae1f 5986 u16 autoneg_val, an_1000_val, an_10_100_val;
9bffeac1 5987
de6eae1f
YR		 5988 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
5989 1 << NIG_LATCH_BC_ENABLE_MI_INT);
ea4e040a 5990
de6eae1f
YR		 5991 bnx2x_cl45_write(bp, phy,
5992 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
ea4e040a 5993
de6eae1f 5994 bnx2x_848xx_set_led(bp, phy);
ea4e040a 5995
de6eae1f
YR		 5996 /* set 1000 speed advertisement */
5997 bnx2x_cl45_read(bp, phy,
5998 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5999 &an_1000_val);
57963ed9 6000
de6eae1f
YR		 6001 bnx2x_ext_phy_set_pause(params, phy, vars);
6002 bnx2x_cl45_read(bp, phy,
6003 MDIO_AN_DEVAD,
6004 MDIO_AN_REG_8481_LEGACY_AN_ADV,
6005 &an_10_100_val);
6006 bnx2x_cl45_read(bp, phy,
6007 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6008 &autoneg_val);
6009 /* Disable forced speed */
6010 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6011 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
ea4e040a 6012
de6eae1f
YR		 6013 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6014 (phy->speed_cap_mask &
6015 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6016 (phy->req_line_speed == SPEED_1000)) {
6017 an_1000_val |= (1<<8);
6018 autoneg_val |= (1<<9 | 1<<12);
6019 if (phy->req_duplex == DUPLEX_FULL)
6020 an_1000_val |= (1<<9);
6021 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6022 } else
6023 an_1000_val &= ~((1<<8) | (1<<9));
ea4e040a 6024
de6eae1f
YR		 6025 bnx2x_cl45_write(bp, phy,
6026 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6027 an_1000_val);
ea4e040a 6028
de6eae1f
YR		 6029 /* set 10 speed advertisement */
6030 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6031 (phy->speed_cap_mask &
6032 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6033 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6034 an_10_100_val |= (1<<7);
6035 /* Enable autoneg and restart autoneg for legacy speeds */
6036 autoneg_val |= (1<<9 | 1<<12);
b7737c9b 6037
de6eae1f
YR		 6038 if (phy->req_duplex == DUPLEX_FULL)
6039 an_10_100_val |= (1<<8);
6040 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6041 }
6042 /* set 10 speed advertisement */
6043 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6044 (phy->speed_cap_mask &
6045 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6046 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6047 an_10_100_val |= (1<<5);
6048 autoneg_val |= (1<<9 | 1<<12);
6049 if (phy->req_duplex == DUPLEX_FULL)
6050 an_10_100_val |= (1<<6);
6051 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6052 }
b7737c9b 6053
de6eae1f
YR		 6054 /* Only 10/100 are allowed to work in FORCE mode */
6055 if (phy->req_line_speed == SPEED_100) {
6056 autoneg_val |= (1<<13);
6057 /* Enabled AUTO-MDIX when autoneg is disabled */
6058 bnx2x_cl45_write(bp, phy,
6059 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6060 (1<<15 | 1<<9 | 7<<0));
6061 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6062 }
6063 if (phy->req_line_speed == SPEED_10) {
6064 /* Enabled AUTO-MDIX when autoneg is disabled */
6065 bnx2x_cl45_write(bp, phy,
6066 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6067 (1<<15 | 1<<9 | 7<<0));
6068 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6069 }
b7737c9b 6070
de6eae1f
YR		 6071 bnx2x_cl45_write(bp, phy,
6072 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6073 an_10_100_val);
b7737c9b 6074
de6eae1f
YR		 6075 if (phy->req_duplex == DUPLEX_FULL)
6076 autoneg_val |= (1<<8);
b7737c9b 6077
de6eae1f
YR		 6078 bnx2x_cl45_write(bp, phy,
6079 MDIO_AN_DEVAD,
6080 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
b7737c9b 6081
de6eae1f
YR		 6082 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6083 (phy->speed_cap_mask &
6084 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6085 (phy->req_line_speed == SPEED_10000)) {
6086 DP(NETIF_MSG_LINK, "Advertising 10G\n");
6087 /* Restart autoneg for 10G*/
6088
6089 bnx2x_cl45_write(bp, phy,
6090 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6091 0x3200);
6092 } else if (phy->req_line_speed != SPEED_10 &&
6093 phy->req_line_speed != SPEED_100) {
6094 bnx2x_cl45_write(bp, phy,
6095 MDIO_AN_DEVAD,
6096 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6097 1);
b7737c9b 6098 }
de6eae1f
YR		 6099 /* Save spirom version */
6100 bnx2x_save_848xx_spirom_version(phy, params);
6101
6102 return 0;
b7737c9b
YR		 6103}
6104
de6eae1f
YR		 6105static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6106 struct link_params *params,
6107 struct link_vars *vars)
ea4e040a
YR		 6108{
6109 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6110 /* Restore normal power mode*/
6111 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6112 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 6113
de6eae1f
YR		 6114 /* HW reset */
6115 bnx2x_ext_phy_hw_reset(bp, params->port);
9bffeac1 6116 bnx2x_wait_reset_complete(bp, phy);
ab6ad5a4 6117
de6eae1f
YR		 6118 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6119 return bnx2x_848xx_cmn_config_init(phy, params, vars);
6120}
ea4e040a 6121
de6eae1f
YR		 6122static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6123 struct link_params *params,
6124 struct link_vars *vars)
6125{
6126 struct bnx2x *bp = params->bp;
6a71bbe0 6127 u8 port, initialize = 1;
a22f0788 6128 u16 val;
de6eae1f 6129 u16 temp;
a22f0788
YR		 6130 u32 actual_phy_selection;
6131 u8 rc = 0;
7f02c4ad
YR		 6132
6133 /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
6134
de6eae1f 6135 msleep(1);
6a71bbe0
YR		 6136 if (CHIP_IS_E2(bp))
6137 port = BP_PATH(bp);
6138 else
6139 port = params->port;
de6eae1f
YR		 6140 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6141 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7f02c4ad 6142 port);
9bffeac1
YR		 6143 bnx2x_wait_reset_complete(bp, phy);
6144 /* Wait for GPHY to come out of reset */
6145 msleep(50);
7f02c4ad
YR		 6146 /* BCM84823 requires that XGXS links up first @ 10G for normal
6147 behavior */
de6eae1f
YR		 6148 temp = vars->line_speed;
6149 vars->line_speed = SPEED_10000;
a22f0788
YR		 6150 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6151 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
de6eae1f 6152 vars->line_speed = temp;
a22f0788
YR		 6153
6154 /* Set dual-media configuration according to configuration */
6155
6156 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6157 MDIO_CTL_REG_84823_MEDIA, &val);
6158 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6159 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6160 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6161 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6162 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6163 val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6164 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6165
6166 actual_phy_selection = bnx2x_phy_selection(params);
6167
6168 switch (actual_phy_selection) {
6169 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6170 /* Do nothing. Essentialy this is like the priority copper */
6171 break;
6172 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6173 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6174 break;
6175 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6176 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6177 break;
6178 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6179 /* Do nothing here. The first PHY won't be initialized at all */
6180 break;
6181 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6182 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6183 initialize = 0;
6184 break;
6185 }
6186 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6187 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6188
6189 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6190 MDIO_CTL_REG_84823_MEDIA, val);
6191 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6192 params->multi_phy_config, val);
6193
6194 if (initialize)
6195 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6196 else
6197 bnx2x_save_848xx_spirom_version(phy, params);
6198 return rc;
de6eae1f 6199}
ea4e040a 6200
de6eae1f
YR		 6201static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6202 struct link_params *params,
6203 struct link_vars *vars)
6204{
6205 struct bnx2x *bp = params->bp;
6206 u16 val, val1, val2;
6207 u8 link_up = 0;
ea4e040a 6208
de6eae1f
YR		 6209 /* Check 10G-BaseT link status */
6210 /* Check PMD signal ok */
6211 bnx2x_cl45_read(bp, phy,
6212 MDIO_AN_DEVAD, 0xFFFA, &val1);
6213 bnx2x_cl45_read(bp, phy,
6214 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
6215 &val2);
6216 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
ea4e040a 6217
de6eae1f
YR		 6218 /* Check link 10G */
6219 if (val2 & (1<<11)) {
ea4e040a 6220 vars->line_speed = SPEED_10000;
de6eae1f
YR		 6221 link_up = 1;
6222 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6223 } else { /* Check Legacy speed link */
6224 u16 legacy_status, legacy_speed;
ea4e040a 6225
de6eae1f
YR		 6226 /* Enable expansion register 0x42 (Operation mode status) */
6227 bnx2x_cl45_write(bp, phy,
6228 MDIO_AN_DEVAD,
6229 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
ea4e040a 6230
de6eae1f
YR		 6231 /* Get legacy speed operation status */
6232 bnx2x_cl45_read(bp, phy,
6233 MDIO_AN_DEVAD,
6234 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6235 &legacy_status);
ea4e040a 6236
de6eae1f
YR		 6237 DP(NETIF_MSG_LINK, "Legacy speed status"
6238 " = 0x%x\n", legacy_status);
6239 link_up = ((legacy_status & (1<<11)) == (1<<11));
6240 if (link_up) {
6241 legacy_speed = (legacy_status & (3<<9));
6242 if (legacy_speed == (0<<9))
6243 vars->line_speed = SPEED_10;
6244 else if (legacy_speed == (1<<9))
6245 vars->line_speed = SPEED_100;
6246 else if (legacy_speed == (2<<9))
6247 vars->line_speed = SPEED_1000;
6248 else /* Should not happen */
6249 vars->line_speed = 0;
ea4e040a 6250
de6eae1f
YR		 6251 if (legacy_status & (1<<8))
6252 vars->duplex = DUPLEX_FULL;
6253 else
6254 vars->duplex = DUPLEX_HALF;
ea4e040a 6255
de6eae1f
YR		 6256 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6257 " is_duplex_full= %d\n", vars->line_speed,
6258 (vars->duplex == DUPLEX_FULL));
6259 /* Check legacy speed AN resolution */
6260 bnx2x_cl45_read(bp, phy,
6261 MDIO_AN_DEVAD,
6262 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6263 &val);
6264 if (val & (1<<5))
6265 vars->link_status |=
6266 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6267 bnx2x_cl45_read(bp, phy,
6268 MDIO_AN_DEVAD,
6269 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6270 &val);
6271 if ((val & (1<<0)) == 0)
6272 vars->link_status |=
6273 LINK_STATUS_PARALLEL_DETECTION_USED;
ea4e040a 6274 }
ea4e040a 6275 }
de6eae1f
YR		 6276 if (link_up) {
6277 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6278 vars->line_speed);
6279 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6280 }
589abe3a 6281
de6eae1f 6282 return link_up;
b7737c9b
YR		 6283}
6284
de6eae1f 6285static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
b7737c9b 6286{
de6eae1f
YR		 6287 u8 status = 0;
6288 u32 spirom_ver;
6289 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6290 status = bnx2x_format_ver(spirom_ver, str, len);
6291 return status;
b7737c9b 6292}
de6eae1f
YR		 6293
6294static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6295 struct link_params *params)
b7737c9b 6296{
de6eae1f
YR		 6297 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6298 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6299 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6300 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
b7737c9b 6301}
de6eae1f 6302
b7737c9b
YR		 6303static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6304 struct link_params *params)
6305{
6306 bnx2x_cl45_write(params->bp, phy,
6307 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6308 bnx2x_cl45_write(params->bp, phy,
6309 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6310}
6311
6312static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6313 struct link_params *params)
6314{
6315 struct bnx2x *bp = params->bp;
6a71bbe0
YR		 6316 u8 port;
6317 if (CHIP_IS_E2(bp))
6318 port = BP_PATH(bp);
6319 else
6320 port = params->port;
b7737c9b
YR		 6321 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6322 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6323 port);
6324}
6325
7f02c4ad
YR		 6326static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6327 struct link_params *params, u8 mode)
6328{
6329 struct bnx2x *bp = params->bp;
6330 u16 val;
6331
6332 switch (mode) {
6333 case LED_MODE_OFF:
6334
6335 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6336
6337 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6338 SHARED_HW_CFG_LED_EXTPHY1) {
6339
6340 /* Set LED masks */
6341 bnx2x_cl45_write(bp, phy,
6342 MDIO_PMA_DEVAD,
6343 MDIO_PMA_REG_8481_LED1_MASK,
6344 0x0);
6345
6346 bnx2x_cl45_write(bp, phy,
6347 MDIO_PMA_DEVAD,
6348 MDIO_PMA_REG_8481_LED2_MASK,
6349 0x0);
6350
6351 bnx2x_cl45_write(bp, phy,
6352 MDIO_PMA_DEVAD,
6353 MDIO_PMA_REG_8481_LED3_MASK,
6354 0x0);
6355
6356 bnx2x_cl45_write(bp, phy,
6357 MDIO_PMA_DEVAD,
6358 MDIO_PMA_REG_8481_LED5_MASK,
6359 0x0);
6360
6361 } else {
6362 bnx2x_cl45_write(bp, phy,
6363 MDIO_PMA_DEVAD,
6364 MDIO_PMA_REG_8481_LED1_MASK,
6365 0x0);
6366 }
6367 break;
6368 case LED_MODE_FRONT_PANEL_OFF:
6369
6370 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6371 params->port);
6372
6373 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6374 SHARED_HW_CFG_LED_EXTPHY1) {
6375
6376 /* Set LED masks */
6377 bnx2x_cl45_write(bp, phy,
6378 MDIO_PMA_DEVAD,
6379 MDIO_PMA_REG_8481_LED1_MASK,
6380 0x0);
6381
6382 bnx2x_cl45_write(bp, phy,
6383 MDIO_PMA_DEVAD,
6384 MDIO_PMA_REG_8481_LED2_MASK,
6385 0x0);
6386
6387 bnx2x_cl45_write(bp, phy,
6388 MDIO_PMA_DEVAD,
6389 MDIO_PMA_REG_8481_LED3_MASK,
6390 0x0);
6391
6392 bnx2x_cl45_write(bp, phy,
6393 MDIO_PMA_DEVAD,
6394 MDIO_PMA_REG_8481_LED5_MASK,
6395 0x20);
6396
6397 } else {
6398 bnx2x_cl45_write(bp, phy,
6399 MDIO_PMA_DEVAD,
6400 MDIO_PMA_REG_8481_LED1_MASK,
6401 0x0);
6402 }
6403 break;
6404 case LED_MODE_ON:
6405
6406 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6407
6408 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6409 SHARED_HW_CFG_LED_EXTPHY1) {
6410 /* Set control reg */
6411 bnx2x_cl45_read(bp, phy,
6412 MDIO_PMA_DEVAD,
6413 MDIO_PMA_REG_8481_LINK_SIGNAL,
6414 &val);
6415 val &= 0x8000;
6416 val |= 0x2492;
6417
6418 bnx2x_cl45_write(bp, phy,
6419 MDIO_PMA_DEVAD,
6420 MDIO_PMA_REG_8481_LINK_SIGNAL,
6421 val);
6422
6423 /* Set LED masks */
6424 bnx2x_cl45_write(bp, phy,
6425 MDIO_PMA_DEVAD,
6426 MDIO_PMA_REG_8481_LED1_MASK,
6427 0x0);
6428
6429 bnx2x_cl45_write(bp, phy,
6430 MDIO_PMA_DEVAD,
6431 MDIO_PMA_REG_8481_LED2_MASK,
6432 0x20);
6433
6434 bnx2x_cl45_write(bp, phy,
6435 MDIO_PMA_DEVAD,
6436 MDIO_PMA_REG_8481_LED3_MASK,
6437 0x20);
6438
6439 bnx2x_cl45_write(bp, phy,
6440 MDIO_PMA_DEVAD,
6441 MDIO_PMA_REG_8481_LED5_MASK,
6442 0x0);
6443 } else {
6444 bnx2x_cl45_write(bp, phy,
6445 MDIO_PMA_DEVAD,
6446 MDIO_PMA_REG_8481_LED1_MASK,
6447 0x20);
6448 }
6449 break;
6450
6451 case LED_MODE_OPER:
6452
6453 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6454
6455 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6456 SHARED_HW_CFG_LED_EXTPHY1) {
6457
6458 /* Set control reg */
6459 bnx2x_cl45_read(bp, phy,
6460 MDIO_PMA_DEVAD,
6461 MDIO_PMA_REG_8481_LINK_SIGNAL,
6462 &val);
6463
6464 if (!((val &
6465 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6466 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){
6467 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n");
6468 bnx2x_cl45_write(bp, phy,
6469 MDIO_PMA_DEVAD,
6470 MDIO_PMA_REG_8481_LINK_SIGNAL,
6471 0xa492);
6472 }
6473
6474 /* Set LED masks */
6475 bnx2x_cl45_write(bp, phy,
6476 MDIO_PMA_DEVAD,
6477 MDIO_PMA_REG_8481_LED1_MASK,
6478 0x10);
6479
6480 bnx2x_cl45_write(bp, phy,
6481 MDIO_PMA_DEVAD,
6482 MDIO_PMA_REG_8481_LED2_MASK,
6483 0x80);
6484
6485 bnx2x_cl45_write(bp, phy,
6486 MDIO_PMA_DEVAD,
6487 MDIO_PMA_REG_8481_LED3_MASK,
6488 0x98);
6489
6490 bnx2x_cl45_write(bp, phy,
6491 MDIO_PMA_DEVAD,
6492 MDIO_PMA_REG_8481_LED5_MASK,
6493 0x40);
6494
6495 } else {
6496 bnx2x_cl45_write(bp, phy,
6497 MDIO_PMA_DEVAD,
6498 MDIO_PMA_REG_8481_LED1_MASK,
6499 0x80);
6500 }
6501 break;
6502 }
6503}
de6eae1f
YR		 6504/******************************************************************/
6505/* SFX7101 PHY SECTION */
6506/******************************************************************/
6507static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6508 struct link_params *params)
b7737c9b
YR		 6509{
6510 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6511 /* SFX7101_XGXS_TEST1 */
6512 bnx2x_cl45_write(bp, phy,
6513 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
589abe3a
EG		 6514}
6515
de6eae1f
YR		 6516static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6517 struct link_params *params,
6518 struct link_vars *vars)
ea4e040a 6519{
de6eae1f 6520 u16 fw_ver1, fw_ver2, val;
ea4e040a 6521 struct bnx2x *bp = params->bp;
de6eae1f 6522 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
ea4e040a 6523
de6eae1f
YR		 6524 /* Restore normal power mode*/
6525 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6526 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6527 /* HW reset */
6528 bnx2x_ext_phy_hw_reset(bp, params->port);
6529 bnx2x_wait_reset_complete(bp, phy);
ea4e040a 6530
de6eae1f
YR		 6531 bnx2x_cl45_write(bp, phy,
6532 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6533 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6534 bnx2x_cl45_write(bp, phy,
6535 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
ea4e040a 6536
de6eae1f
YR		 6537 bnx2x_ext_phy_set_pause(params, phy, vars);
6538 /* Restart autoneg */
6539 bnx2x_cl45_read(bp, phy,
6540 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6541 val |= 0x200;
6542 bnx2x_cl45_write(bp, phy,
6543 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
ea4e040a 6544
de6eae1f
YR		 6545 /* Save spirom version */
6546 bnx2x_cl45_read(bp, phy,
6547 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
ea4e040a 6548
de6eae1f
YR		 6549 bnx2x_cl45_read(bp, phy,
6550 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6551 bnx2x_save_spirom_version(bp, params->port,
6552 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6553 return 0;
6554}
ea4e040a 6555
de6eae1f
YR		 6556static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6557 struct link_params *params,
6558 struct link_vars *vars)
57963ed9
YR		 6559{
6560 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6561 u8 link_up;
6562 u16 val1, val2;
6563 bnx2x_cl45_read(bp, phy,
6564 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6565 bnx2x_cl45_read(bp, phy,
6566 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6567 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6568 val2, val1);
6569 bnx2x_cl45_read(bp, phy,
6570 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6571 bnx2x_cl45_read(bp, phy,
6572 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6573 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6574 val2, val1);
6575 link_up = ((val1 & 4) == 4);
6576 /* if link is up
6577 * print the AN outcome of the SFX7101 PHY
6578 */
6579 if (link_up) {
6580 bnx2x_cl45_read(bp, phy,
6581 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6582 &val2);
6583 vars->line_speed = SPEED_10000;
6584 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6585 val2, (val2 & (1<<14)));
6586 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6587 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6588 }
6589 return link_up;
6590}
6c55c3cd 6591
6c55c3cd 6592
de6eae1f
YR		 6593static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6594{
6595 if (*len < 5)
6596 return -EINVAL;
6597 str[0] = (spirom_ver & 0xFF);
6598 str[1] = (spirom_ver & 0xFF00) >> 8;
6599 str[2] = (spirom_ver & 0xFF0000) >> 16;
6600 str[3] = (spirom_ver & 0xFF000000) >> 24;
6601 str[4] = '\0';
6602 *len -= 5;
57963ed9
YR		 6603 return 0;
6604}
6605
de6eae1f 6606void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
57963ed9 6607{
de6eae1f 6608 u16 val, cnt;
7aa0711f 6609
de6eae1f
YR		 6610 bnx2x_cl45_read(bp, phy,
6611 MDIO_PMA_DEVAD,
6612 MDIO_PMA_REG_7101_RESET, &val);
57963ed9 6613
de6eae1f
YR		 6614 for (cnt = 0; cnt < 10; cnt++) {
6615 msleep(50);
6616 /* Writes a self-clearing reset */
6617 bnx2x_cl45_write(bp, phy,
6618 MDIO_PMA_DEVAD,
6619 MDIO_PMA_REG_7101_RESET,
6620 (val | (1<<15)));
6621 /* Wait for clear */
6622 bnx2x_cl45_read(bp, phy,
6623 MDIO_PMA_DEVAD,
6624 MDIO_PMA_REG_7101_RESET, &val);
0c786f02 6625
de6eae1f
YR		 6626 if ((val & (1<<15)) == 0)
6627 break;
57963ed9 6628 }
57963ed9 6629}
ea4e040a 6630
de6eae1f
YR		 6631static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6632 struct link_params *params) {
6633 /* Low power mode is controlled by GPIO 2 */
6634 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6635 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6636 /* The PHY reset is controlled by GPIO 1 */
6637 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6638 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6639}
ea4e040a 6640
7f02c4ad
YR		 6641static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6642 struct link_params *params, u8 mode)
6643{
6644 u16 val = 0;
6645 struct bnx2x *bp = params->bp;
6646 switch (mode) {
6647 case LED_MODE_FRONT_PANEL_OFF:
6648 case LED_MODE_OFF:
6649 val = 2;
6650 break;
6651 case LED_MODE_ON:
6652 val = 1;
6653 break;
6654 case LED_MODE_OPER:
6655 val = 0;
6656 break;
6657 }
6658 bnx2x_cl45_write(bp, phy,
6659 MDIO_PMA_DEVAD,
6660 MDIO_PMA_REG_7107_LINK_LED_CNTL,
6661 val);
6662}
6663
de6eae1f
YR		 6664/******************************************************************/
6665/* STATIC PHY DECLARATION */
6666/******************************************************************/
ea4e040a 6667
de6eae1f
YR		 6668static struct bnx2x_phy phy_null = {
6669 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6670 .addr = 0,
6671 .flags = FLAGS_INIT_XGXS_FIRST,
6672 .def_md_devad = 0,
6673 .reserved = 0,
6674 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6675 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6676 .mdio_ctrl = 0,
6677 .supported = 0,
6678 .media_type = ETH_PHY_NOT_PRESENT,
6679 .ver_addr = 0,
6680 .req_flow_ctrl = 0,
6681 .req_line_speed = 0,
6682 .speed_cap_mask = 0,
6683 .req_duplex = 0,
6684 .rsrv = 0,
6685 .config_init = (config_init_t)NULL,
6686 .read_status = (read_status_t)NULL,
6687 .link_reset = (link_reset_t)NULL,
6688 .config_loopback = (config_loopback_t)NULL,
6689 .format_fw_ver = (format_fw_ver_t)NULL,
6690 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6691 .set_link_led = (set_link_led_t)NULL,
6692 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 6693};
ea4e040a 6694
de6eae1f
YR		 6695static struct bnx2x_phy phy_serdes = {
6696 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6697 .addr = 0xff,
6698 .flags = 0,
6699 .def_md_devad = 0,
6700 .reserved = 0,
6701 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6702 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6703 .mdio_ctrl = 0,
6704 .supported = (SUPPORTED_10baseT_Half |
6705 SUPPORTED_10baseT_Full |
6706 SUPPORTED_100baseT_Half |
6707 SUPPORTED_100baseT_Full |
6708 SUPPORTED_1000baseT_Full |
6709 SUPPORTED_2500baseX_Full |
6710 SUPPORTED_TP |
6711 SUPPORTED_Autoneg |
6712 SUPPORTED_Pause |
6713 SUPPORTED_Asym_Pause),
6714 .media_type = ETH_PHY_UNSPECIFIED,
6715 .ver_addr = 0,
6716 .req_flow_ctrl = 0,
6717 .req_line_speed = 0,
6718 .speed_cap_mask = 0,
6719 .req_duplex = 0,
6720 .rsrv = 0,
6721 .config_init = (config_init_t)bnx2x_init_serdes,
6722 .read_status = (read_status_t)bnx2x_link_settings_status,
6723 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6724 .config_loopback = (config_loopback_t)NULL,
6725 .format_fw_ver = (format_fw_ver_t)NULL,
6726 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6727 .set_link_led = (set_link_led_t)NULL,
6728 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 6729};
b7737c9b
YR		 6730
6731static struct bnx2x_phy phy_xgxs = {
6732 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6733 .addr = 0xff,
6734 .flags = 0,
6735 .def_md_devad = 0,
6736 .reserved = 0,
6737 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6738 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6739 .mdio_ctrl = 0,
6740 .supported = (SUPPORTED_10baseT_Half |
6741 SUPPORTED_10baseT_Full |
6742 SUPPORTED_100baseT_Half |
6743 SUPPORTED_100baseT_Full |
6744 SUPPORTED_1000baseT_Full |
6745 SUPPORTED_2500baseX_Full |
6746 SUPPORTED_10000baseT_Full |
6747 SUPPORTED_FIBRE |
6748 SUPPORTED_Autoneg |
6749 SUPPORTED_Pause |
6750 SUPPORTED_Asym_Pause),
6751 .media_type = ETH_PHY_UNSPECIFIED,
6752 .ver_addr = 0,
6753 .req_flow_ctrl = 0,
6754 .req_line_speed = 0,
6755 .speed_cap_mask = 0,
6756 .req_duplex = 0,
6757 .rsrv = 0,
6758 .config_init = (config_init_t)bnx2x_init_xgxs,
6759 .read_status = (read_status_t)bnx2x_link_settings_status,
6760 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6761 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6762 .format_fw_ver = (format_fw_ver_t)NULL,
6763 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6764 .set_link_led = (set_link_led_t)NULL,
6765 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6766};
6767
6768static struct bnx2x_phy phy_7101 = {
6769 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6770 .addr = 0xff,
6771 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6772 .def_md_devad = 0,
6773 .reserved = 0,
6774 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6775 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6776 .mdio_ctrl = 0,
6777 .supported = (SUPPORTED_10000baseT_Full |
6778 SUPPORTED_TP |
6779 SUPPORTED_Autoneg |
6780 SUPPORTED_Pause |
6781 SUPPORTED_Asym_Pause),
6782 .media_type = ETH_PHY_BASE_T,
6783 .ver_addr = 0,
6784 .req_flow_ctrl = 0,
6785 .req_line_speed = 0,
6786 .speed_cap_mask = 0,
6787 .req_duplex = 0,
6788 .rsrv = 0,
6789 .config_init = (config_init_t)bnx2x_7101_config_init,
6790 .read_status = (read_status_t)bnx2x_7101_read_status,
6791 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6792 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6793 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
6794 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
7f02c4ad 6795 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
a22f0788 6796 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6797};
6798static struct bnx2x_phy phy_8073 = {
6799 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6800 .addr = 0xff,
6801 .flags = FLAGS_HW_LOCK_REQUIRED,
6802 .def_md_devad = 0,
6803 .reserved = 0,
6804 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6805 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6806 .mdio_ctrl = 0,
6807 .supported = (SUPPORTED_10000baseT_Full |
6808 SUPPORTED_2500baseX_Full |
6809 SUPPORTED_1000baseT_Full |
6810 SUPPORTED_FIBRE |
6811 SUPPORTED_Autoneg |
6812 SUPPORTED_Pause |
6813 SUPPORTED_Asym_Pause),
6814 .media_type = ETH_PHY_UNSPECIFIED,
6815 .ver_addr = 0,
6816 .req_flow_ctrl = 0,
6817 .req_line_speed = 0,
6818 .speed_cap_mask = 0,
6819 .req_duplex = 0,
6820 .rsrv = 0,
62b29a5d 6821 .config_init = (config_init_t)bnx2x_8073_config_init,
b7737c9b
YR		 6822 .read_status = (read_status_t)bnx2x_8073_read_status,
6823 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
6824 .config_loopback = (config_loopback_t)NULL,
6825 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6826 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6827 .set_link_led = (set_link_led_t)NULL,
6828 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6829};
6830static struct bnx2x_phy phy_8705 = {
6831 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
6832 .addr = 0xff,
6833 .flags = FLAGS_INIT_XGXS_FIRST,
6834 .def_md_devad = 0,
6835 .reserved = 0,
6836 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6837 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6838 .mdio_ctrl = 0,
6839 .supported = (SUPPORTED_10000baseT_Full |
6840 SUPPORTED_FIBRE |
6841 SUPPORTED_Pause |
6842 SUPPORTED_Asym_Pause),
6843 .media_type = ETH_PHY_XFP_FIBER,
6844 .ver_addr = 0,
6845 .req_flow_ctrl = 0,
6846 .req_line_speed = 0,
6847 .speed_cap_mask = 0,
6848 .req_duplex = 0,
6849 .rsrv = 0,
6850 .config_init = (config_init_t)bnx2x_8705_config_init,
6851 .read_status = (read_status_t)bnx2x_8705_read_status,
6852 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6853 .config_loopback = (config_loopback_t)NULL,
6854 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
6855 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6856 .set_link_led = (set_link_led_t)NULL,
6857 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6858};
6859static struct bnx2x_phy phy_8706 = {
6860 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
6861 .addr = 0xff,
6862 .flags = FLAGS_INIT_XGXS_FIRST,
6863 .def_md_devad = 0,
6864 .reserved = 0,
6865 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6866 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6867 .mdio_ctrl = 0,
6868 .supported = (SUPPORTED_10000baseT_Full |
6869 SUPPORTED_1000baseT_Full |
6870 SUPPORTED_FIBRE |
6871 SUPPORTED_Pause |
6872 SUPPORTED_Asym_Pause),
6873 .media_type = ETH_PHY_SFP_FIBER,
6874 .ver_addr = 0,
6875 .req_flow_ctrl = 0,
6876 .req_line_speed = 0,
6877 .speed_cap_mask = 0,
6878 .req_duplex = 0,
6879 .rsrv = 0,
6880 .config_init = (config_init_t)bnx2x_8706_config_init,
6881 .read_status = (read_status_t)bnx2x_8706_read_status,
6882 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6883 .config_loopback = (config_loopback_t)NULL,
6884 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6885 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6886 .set_link_led = (set_link_led_t)NULL,
6887 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6888};
6889
6890static struct bnx2x_phy phy_8726 = {
6891 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
6892 .addr = 0xff,
6893 .flags = (FLAGS_HW_LOCK_REQUIRED |
6894 FLAGS_INIT_XGXS_FIRST),
6895 .def_md_devad = 0,
6896 .reserved = 0,
6897 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6898 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6899 .mdio_ctrl = 0,
6900 .supported = (SUPPORTED_10000baseT_Full |
6901 SUPPORTED_1000baseT_Full |
6902 SUPPORTED_Autoneg |
6903 SUPPORTED_FIBRE |
6904 SUPPORTED_Pause |
6905 SUPPORTED_Asym_Pause),
6906 .media_type = ETH_PHY_SFP_FIBER,
6907 .ver_addr = 0,
6908 .req_flow_ctrl = 0,
6909 .req_line_speed = 0,
6910 .speed_cap_mask = 0,
6911 .req_duplex = 0,
6912 .rsrv = 0,
6913 .config_init = (config_init_t)bnx2x_8726_config_init,
6914 .read_status = (read_status_t)bnx2x_8726_read_status,
6915 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
6916 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
6917 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6918 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6919 .set_link_led = (set_link_led_t)NULL,
6920 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6921};
6922
6923static struct bnx2x_phy phy_8727 = {
6924 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6925 .addr = 0xff,
6926 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6927 .def_md_devad = 0,
6928 .reserved = 0,
6929 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6930 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6931 .mdio_ctrl = 0,
6932 .supported = (SUPPORTED_10000baseT_Full |
6933 SUPPORTED_1000baseT_Full |
b7737c9b
YR		 6934 SUPPORTED_FIBRE |
6935 SUPPORTED_Pause |
6936 SUPPORTED_Asym_Pause),
6937 .media_type = ETH_PHY_SFP_FIBER,
6938 .ver_addr = 0,
6939 .req_flow_ctrl = 0,
6940 .req_line_speed = 0,
6941 .speed_cap_mask = 0,
6942 .req_duplex = 0,
6943 .rsrv = 0,
6944 .config_init = (config_init_t)bnx2x_8727_config_init,
6945 .read_status = (read_status_t)bnx2x_8727_read_status,
6946 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
6947 .config_loopback = (config_loopback_t)NULL,
6948 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6949 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
7f02c4ad 6950 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
a22f0788 6951 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
b7737c9b
YR		 6952};
6953static struct bnx2x_phy phy_8481 = {
6954 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6955 .addr = 0xff,
a22f0788
YR		 6956 .flags = FLAGS_FAN_FAILURE_DET_REQ |
6957 FLAGS_REARM_LATCH_SIGNAL,
b7737c9b
YR		 6958 .def_md_devad = 0,
6959 .reserved = 0,
6960 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6961 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6962 .mdio_ctrl = 0,
6963 .supported = (SUPPORTED_10baseT_Half |
6964 SUPPORTED_10baseT_Full |
6965 SUPPORTED_100baseT_Half |
6966 SUPPORTED_100baseT_Full |
6967 SUPPORTED_1000baseT_Full |
6968 SUPPORTED_10000baseT_Full |
6969 SUPPORTED_TP |
6970 SUPPORTED_Autoneg |
6971 SUPPORTED_Pause |
6972 SUPPORTED_Asym_Pause),
6973 .media_type = ETH_PHY_BASE_T,
6974 .ver_addr = 0,
6975 .req_flow_ctrl = 0,
6976 .req_line_speed = 0,
6977 .speed_cap_mask = 0,
6978 .req_duplex = 0,
6979 .rsrv = 0,
6980 .config_init = (config_init_t)bnx2x_8481_config_init,
6981 .read_status = (read_status_t)bnx2x_848xx_read_status,
6982 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
6983 .config_loopback = (config_loopback_t)NULL,
6984 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
6985 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
7f02c4ad 6986 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 6987 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6988};
6989
de6eae1f
YR		 6990static struct bnx2x_phy phy_84823 = {
6991 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
6992 .addr = 0xff,
a22f0788
YR		 6993 .flags = FLAGS_FAN_FAILURE_DET_REQ |
6994 FLAGS_REARM_LATCH_SIGNAL,
de6eae1f
YR		 6995 .def_md_devad = 0,
6996 .reserved = 0,
6997 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6998 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6999 .mdio_ctrl = 0,
7000 .supported = (SUPPORTED_10baseT_Half |
7001 SUPPORTED_10baseT_Full |
7002 SUPPORTED_100baseT_Half |
7003 SUPPORTED_100baseT_Full |
7004 SUPPORTED_1000baseT_Full |
7005 SUPPORTED_10000baseT_Full |
7006 SUPPORTED_TP |
7007 SUPPORTED_Autoneg |
7008 SUPPORTED_Pause |
7009 SUPPORTED_Asym_Pause),
7010 .media_type = ETH_PHY_BASE_T,
7011 .ver_addr = 0,
7012 .req_flow_ctrl = 0,
7013 .req_line_speed = 0,
7014 .speed_cap_mask = 0,
7015 .req_duplex = 0,
7016 .rsrv = 0,
7017 .config_init = (config_init_t)bnx2x_848x3_config_init,
7018 .read_status = (read_status_t)bnx2x_848xx_read_status,
7019 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7020 .config_loopback = (config_loopback_t)NULL,
7021 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7022 .hw_reset = (hw_reset_t)NULL,
7f02c4ad 7023 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 7024 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f
YR		 7025};
7026
7027/*****************************************************************/
7028/* */
7029/* Populate the phy according. Main function: bnx2x_populate_phy */
7030/* */
7031/*****************************************************************/
7032
7033static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7034 struct bnx2x_phy *phy, u8 port,
7035 u8 phy_index)
7036{
7037 /* Get the 4 lanes xgxs config rx and tx */
7038 u32 rx = 0, tx = 0, i;
7039 for (i = 0; i < 2; i++) {
7040 /**
7041 * INT_PHY and EXT_PHY1 share the same value location in the
7042 * shmem. When num_phys is greater than 1, than this value
7043 * applies only to EXT_PHY1
7044 */
a22f0788
YR		 7045 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7046 rx = REG_RD(bp, shmem_base +
7047 offsetof(struct shmem_region,
7048 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
7049
7050 tx = REG_RD(bp, shmem_base +
7051 offsetof(struct shmem_region,
7052 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7053 } else {
7054 rx = REG_RD(bp, shmem_base +
7055 offsetof(struct shmem_region,
7056 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
de6eae1f 7057
a22f0788
YR		 7058 tx = REG_RD(bp, shmem_base +
7059 offsetof(struct shmem_region,
7060 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7061 }
de6eae1f
YR		 7062
7063 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7064 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7065
7066 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7067 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7068 }
7069}
7070
7071static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7072 u8 phy_index, u8 port)
7073{
7074 u32 ext_phy_config = 0;
7075 switch (phy_index) {
7076 case EXT_PHY1:
7077 ext_phy_config = REG_RD(bp, shmem_base +
7078 offsetof(struct shmem_region,
7079 dev_info.port_hw_config[port].external_phy_config));
7080 break;
a22f0788
YR		 7081 case EXT_PHY2:
7082 ext_phy_config = REG_RD(bp, shmem_base +
7083 offsetof(struct shmem_region,
7084 dev_info.port_hw_config[port].external_phy_config2));
7085 break;
de6eae1f
YR		 7086 default:
7087 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7088 return -EINVAL;
7089 }
7090
7091 return ext_phy_config;
7092}
7093static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7094 struct bnx2x_phy *phy)
7095{
7096 u32 phy_addr;
7097 u32 chip_id;
7098 u32 switch_cfg = (REG_RD(bp, shmem_base +
7099 offsetof(struct shmem_region,
7100 dev_info.port_feature_config[port].link_config)) &
7101 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7102 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7103 switch (switch_cfg) {
7104 case SWITCH_CFG_1G:
7105 phy_addr = REG_RD(bp,
7106 NIG_REG_SERDES0_CTRL_PHY_ADDR +
7107 port * 0x10);
7108 *phy = phy_serdes;
7109 break;
7110 case SWITCH_CFG_10G:
7111 phy_addr = REG_RD(bp,
7112 NIG_REG_XGXS0_CTRL_PHY_ADDR +
7113 port * 0x18);
7114 *phy = phy_xgxs;
7115 break;
7116 default:
7117 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7118 return -EINVAL;
7119 }
7120 phy->addr = (u8)phy_addr;
7121 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7122 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7123 port);
f2e0899f
DK		 7124 if (CHIP_IS_E2(bp))
7125 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7126 else
7127 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
de6eae1f
YR		 7128
7129 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7130 port, phy->addr, phy->mdio_ctrl);
7131
7132 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7133 return 0;
7134}
7135
7136static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7137 u8 phy_index,
7138 u32 shmem_base,
a22f0788 7139 u32 shmem2_base,
de6eae1f
YR		 7140 u8 port,
7141 struct bnx2x_phy *phy)
7142{
7143 u32 ext_phy_config, phy_type, config2;
7144 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7145 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7146 phy_index, port);
7147 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7148 /* Select the phy type */
7149 switch (phy_type) {
7150 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7151 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7152 *phy = phy_8073;
7153 break;
7154 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7155 *phy = phy_8705;
7156 break;
7157 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7158 *phy = phy_8706;
7159 break;
7160 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7161 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7162 *phy = phy_8726;
7163 break;
7164 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7165 /* BCM8727_NOC => BCM8727 no over current */
7166 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7167 *phy = phy_8727;
7168 phy->flags |= FLAGS_NOC;
7169 break;
7170 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7171 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7172 *phy = phy_8727;
7173 break;
7174 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7175 *phy = phy_8481;
7176 break;
7177 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7178 *phy = phy_84823;
7179 break;
7180 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7181 *phy = phy_7101;
7182 break;
7183 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7184 *phy = phy_null;
7185 return -EINVAL;
7186 default:
7187 *phy = phy_null;
7188 return 0;
7189 }
7190
7191 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7192 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7193
7194 /**
7195 * The shmem address of the phy version is located on different
7196 * structures. In case this structure is too old, do not set
7197 * the address
7198 */
7199 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7200 dev_info.shared_hw_config.config2));
a22f0788
YR		 7201 if (phy_index == EXT_PHY1) {
7202 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7203 port_mb[port].ext_phy_fw_version);
de6eae1f
YR		 7204
7205 /* Check specific mdc mdio settings */
7206 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7207 mdc_mdio_access = config2 &
7208 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
a22f0788
YR		 7209 } else {
7210 u32 size = REG_RD(bp, shmem2_base);
de6eae1f 7211
a22f0788
YR		 7212 if (size >
7213 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7214 phy->ver_addr = shmem2_base +
7215 offsetof(struct shmem2_region,
7216 ext_phy_fw_version2[port]);
7217 }
7218 /* Check specific mdc mdio settings */
7219 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7220 mdc_mdio_access = (config2 &
7221 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7222 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7223 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7224 }
de6eae1f
YR		 7225 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7226
7227 /**
7228 * In case mdc/mdio_access of the external phy is different than the
7229 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7230 * to prevent one port interfere with another port's CL45 operations.
7231 */
7232 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7233 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7234 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7235 phy_type, port, phy_index);
7236 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
7237 phy->addr, phy->mdio_ctrl);
7238 return 0;
7239}
7240
7241static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
a22f0788 7242 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
de6eae1f
YR		 7243{
7244 u8 status = 0;
7245 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7246 if (phy_index == INT_PHY)
7247 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
a22f0788 7248 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 7249 port, phy);
7250 return status;
7251}
7252
7253static void bnx2x_phy_def_cfg(struct link_params *params,
7254 struct bnx2x_phy *phy,
a22f0788 7255 u8 phy_index)
de6eae1f
YR		 7256{
7257 struct bnx2x *bp = params->bp;
7258 u32 link_config;
7259 /* Populate the default phy configuration for MF mode */
a22f0788
YR		 7260 if (phy_index == EXT_PHY2) {
7261 link_config = REG_RD(bp, params->shmem_base +
7262 offsetof(struct shmem_region, dev_info.
7263 port_feature_config[params->port].link_config2));
7264 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7265 offsetof(struct shmem_region, dev_info.
7266 port_hw_config[params->port].speed_capability_mask2));
7267 } else {
7268 link_config = REG_RD(bp, params->shmem_base +
7269 offsetof(struct shmem_region, dev_info.
7270 port_feature_config[params->port].link_config));
7271 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
de6eae1f 7272 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 7273 port_hw_config[params->port].speed_capability_mask));
7274 }
7275 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7276 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
de6eae1f
YR		 7277
7278 phy->req_duplex = DUPLEX_FULL;
7279 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7280 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7281 phy->req_duplex = DUPLEX_HALF;
7282 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7283 phy->req_line_speed = SPEED_10;
7284 break;
7285 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7286 phy->req_duplex = DUPLEX_HALF;
7287 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7288 phy->req_line_speed = SPEED_100;
7289 break;
7290 case PORT_FEATURE_LINK_SPEED_1G:
7291 phy->req_line_speed = SPEED_1000;
7292 break;
7293 case PORT_FEATURE_LINK_SPEED_2_5G:
7294 phy->req_line_speed = SPEED_2500;
7295 break;
7296 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7297 phy->req_line_speed = SPEED_10000;
7298 break;
7299 default:
7300 phy->req_line_speed = SPEED_AUTO_NEG;
7301 break;
7302 }
7303
7304 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
7305 case PORT_FEATURE_FLOW_CONTROL_AUTO:
7306 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7307 break;
7308 case PORT_FEATURE_FLOW_CONTROL_TX:
7309 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7310 break;
7311 case PORT_FEATURE_FLOW_CONTROL_RX:
7312 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7313 break;
7314 case PORT_FEATURE_FLOW_CONTROL_BOTH:
7315 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7316 break;
7317 default:
7318 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7319 break;
7320 }
7321}
7322
a22f0788
YR		 7323u32 bnx2x_phy_selection(struct link_params *params)
7324{
7325 u32 phy_config_swapped, prio_cfg;
7326 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7327
7328 phy_config_swapped = params->multi_phy_config &
7329 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7330
7331 prio_cfg = params->multi_phy_config &
7332 PORT_HW_CFG_PHY_SELECTION_MASK;
7333
7334 if (phy_config_swapped) {
7335 switch (prio_cfg) {
7336 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7337 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7338 break;
7339 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7340 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7341 break;
7342 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7343 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7344 break;
7345 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7346 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7347 break;
7348 }
7349 } else
7350 return_cfg = prio_cfg;
7351
7352 return return_cfg;
7353}
7354
7355
de6eae1f
YR		 7356u8 bnx2x_phy_probe(struct link_params *params)
7357{
7358 u8 phy_index, actual_phy_idx, link_cfg_idx;
a22f0788 7359 u32 phy_config_swapped;
de6eae1f
YR		 7360 struct bnx2x *bp = params->bp;
7361 struct bnx2x_phy *phy;
7362 params->num_phys = 0;
7363 DP(NETIF_MSG_LINK, "Begin phy probe\n");
a22f0788
YR		 7364 phy_config_swapped = params->multi_phy_config &
7365 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 7366
7367 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7368 phy_index++) {
7369 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7370 actual_phy_idx = phy_index;
a22f0788
YR		 7371 if (phy_config_swapped) {
7372 if (phy_index == EXT_PHY1)
7373 actual_phy_idx = EXT_PHY2;
7374 else if (phy_index == EXT_PHY2)
7375 actual_phy_idx = EXT_PHY1;
7376 }
7377 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7378 " actual_phy_idx %x\n", phy_config_swapped,
7379 phy_index, actual_phy_idx);
de6eae1f
YR		 7380 phy = &params->phy[actual_phy_idx];
7381 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
a22f0788 7382 params->shmem2_base, params->port,
de6eae1f
YR		 7383 phy) != 0) {
7384 params->num_phys = 0;
7385 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7386 phy_index);
7387 for (phy_index = INT_PHY;
7388 phy_index < MAX_PHYS;
7389 phy_index++)
7390 *phy = phy_null;
7391 return -EINVAL;
7392 }
7393 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7394 break;
7395
a22f0788 7396 bnx2x_phy_def_cfg(params, phy, phy_index);
de6eae1f
YR		 7397 params->num_phys++;
7398 }
7399
7400 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7401 return 0;
7402}
7403
de6eae1f
YR		 7404static void set_phy_vars(struct link_params *params)
7405{
7406 struct bnx2x *bp = params->bp;
a22f0788
YR		 7407 u8 actual_phy_idx, phy_index, link_cfg_idx;
7408 u8 phy_config_swapped = params->multi_phy_config &
7409 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 7410 for (phy_index = INT_PHY; phy_index < params->num_phys;
7411 phy_index++) {
a22f0788 7412 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
de6eae1f 7413 actual_phy_idx = phy_index;
a22f0788
YR		 7414 if (phy_config_swapped) {
7415 if (phy_index == EXT_PHY1)
7416 actual_phy_idx = EXT_PHY2;
7417 else if (phy_index == EXT_PHY2)
7418 actual_phy_idx = EXT_PHY1;
7419 }
de6eae1f 7420 params->phy[actual_phy_idx].req_flow_ctrl =
a22f0788 7421 params->req_flow_ctrl[link_cfg_idx];
de6eae1f
YR		 7422
7423 params->phy[actual_phy_idx].req_line_speed =
a22f0788 7424 params->req_line_speed[link_cfg_idx];
de6eae1f
YR		 7425
7426 params->phy[actual_phy_idx].speed_cap_mask =
a22f0788 7427 params->speed_cap_mask[link_cfg_idx];
de6eae1f
YR		 7428
7429 params->phy[actual_phy_idx].req_duplex =
a22f0788 7430 params->req_duplex[link_cfg_idx];
de6eae1f
YR		 7431
7432 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7433 " speed_cap_mask %x\n",
7434 params->phy[actual_phy_idx].req_flow_ctrl,
7435 params->phy[actual_phy_idx].req_line_speed,
7436 params->phy[actual_phy_idx].speed_cap_mask);
7437 }
7438}
7439
7440u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7441{
7442 struct bnx2x *bp = params->bp;
de6eae1f 7443 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
a22f0788
YR		 7444 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7445 params->req_line_speed[0], params->req_flow_ctrl[0]);
7446 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7447 params->req_line_speed[1], params->req_flow_ctrl[1]);
de6eae1f
YR		 7448 vars->link_status = 0;
7449 vars->phy_link_up = 0;
7450 vars->link_up = 0;
7451 vars->line_speed = 0;
7452 vars->duplex = DUPLEX_FULL;
7453 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7454 vars->mac_type = MAC_TYPE_NONE;
7455 vars->phy_flags = 0;
7456
7457 /* disable attentions */
7458 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7459 (NIG_MASK_XGXS0_LINK_STATUS |
7460 NIG_MASK_XGXS0_LINK10G |
7461 NIG_MASK_SERDES0_LINK_STATUS |
7462 NIG_MASK_MI_INT));
7463
7464 bnx2x_emac_init(params, vars);
7465
7466 if (params->num_phys == 0) {
7467 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7468 return -EINVAL;
7469 }
7470 set_phy_vars(params);
7471
7472 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7473 if (CHIP_REV_IS_FPGA(bp)) {
7474
7475 vars->link_up = 1;
7476 vars->line_speed = SPEED_10000;
7477 vars->duplex = DUPLEX_FULL;
7478 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7479 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7480 /* enable on E1.5 FPGA */
7481 if (CHIP_IS_E1H(bp)) {
7482 vars->flow_ctrl |=
7483 (BNX2X_FLOW_CTRL_TX |
7484 BNX2X_FLOW_CTRL_RX);
7485 vars->link_status |=
7486 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
7487 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
7488 }
7489
7490 bnx2x_emac_enable(params, vars, 0);
f2e0899f
DK		 7491 if (!(CHIP_IS_E2(bp)))
7492 bnx2x_pbf_update(params, vars->flow_ctrl,
7493 vars->line_speed);
de6eae1f
YR		 7494 /* disable drain */
7495 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7496
7497 /* update shared memory */
7498 bnx2x_update_mng(params, vars->link_status);
7499
7500 return 0;
7501
7502 } else
7503 if (CHIP_REV_IS_EMUL(bp)) {
7504
7505 vars->link_up = 1;
7506 vars->line_speed = SPEED_10000;
7507 vars->duplex = DUPLEX_FULL;
7508 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7509 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7510
7511 bnx2x_bmac_enable(params, vars, 0);
7512
7513 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
7514 /* Disable drain */
7515 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
7516 + params->port*4, 0);
7517
7518 /* update shared memory */
7519 bnx2x_update_mng(params, vars->link_status);
7520
7521 return 0;
7522
7523 } else
7524 if (params->loopback_mode == LOOPBACK_BMAC) {
7525
7526 vars->link_up = 1;
7527 vars->line_speed = SPEED_10000;
7528 vars->duplex = DUPLEX_FULL;
7529 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7530 vars->mac_type = MAC_TYPE_BMAC;
b7737c9b 7531
de6eae1f 7532 vars->phy_flags = PHY_XGXS_FLAG;
b7737c9b 7533
de6eae1f 7534 bnx2x_xgxs_deassert(params);
b7737c9b 7535
de6eae1f
YR		 7536 /* set bmac loopback */
7537 bnx2x_bmac_enable(params, vars, 1);
b7737c9b 7538
de6eae1f
YR		 7539 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7540 params->port*4, 0);
b7737c9b 7541
de6eae1f 7542 } else if (params->loopback_mode == LOOPBACK_EMAC) {
b7737c9b 7543
de6eae1f
YR		 7544 vars->link_up = 1;
7545 vars->line_speed = SPEED_1000;
7546 vars->duplex = DUPLEX_FULL;
7547 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7548 vars->mac_type = MAC_TYPE_EMAC;
b7737c9b 7549
de6eae1f 7550 vars->phy_flags = PHY_XGXS_FLAG;
e10bc84d 7551
de6eae1f
YR		 7552 bnx2x_xgxs_deassert(params);
7553 /* set bmac loopback */
7554 bnx2x_emac_enable(params, vars, 1);
7555 bnx2x_emac_program(params, vars);
7556 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7557 params->port*4, 0);
b7737c9b 7558
de6eae1f
YR		 7559 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7560 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
b7737c9b 7561
de6eae1f 7562 vars->link_up = 1;
de6eae1f 7563 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
a22f0788
YR		 7564 vars->duplex = DUPLEX_FULL;
7565 if (params->req_line_speed[0] == SPEED_1000) {
7566 vars->line_speed = SPEED_1000;
7567 vars->mac_type = MAC_TYPE_EMAC;
7568 } else {
7569 vars->line_speed = SPEED_10000;
7570 vars->mac_type = MAC_TYPE_BMAC;
7571 }
62b29a5d 7572
de6eae1f
YR		 7573 bnx2x_xgxs_deassert(params);
7574 bnx2x_link_initialize(params, vars);
c18aa15d 7575
a22f0788
YR		 7576 if (params->req_line_speed[0] == SPEED_1000) {
7577 bnx2x_emac_program(params, vars);
7578 bnx2x_emac_enable(params, vars, 0);
7579 } else
de6eae1f 7580 bnx2x_bmac_enable(params, vars, 0);
c18aa15d 7581
de6eae1f
YR		 7582 if (params->loopback_mode == LOOPBACK_XGXS) {
7583 /* set 10G XGXS loopback */
7584 params->phy[INT_PHY].config_loopback(
7585 &params->phy[INT_PHY],
7586 params);
c18aa15d 7587
de6eae1f
YR		 7588 } else {
7589 /* set external phy loopback */
7590 u8 phy_index;
7591 for (phy_index = EXT_PHY1;
7592 phy_index < params->num_phys; phy_index++) {
7593 if (params->phy[phy_index].config_loopback)
7594 params->phy[phy_index].config_loopback(
7595 &params->phy[phy_index],
7596 params);
7597 }
7598 }
7599
7600 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7601 params->port*4, 0);
7602
7f02c4ad
YR		 7603 bnx2x_set_led(params, vars,
7604 LED_MODE_OPER, vars->line_speed);
de6eae1f
YR		 7605 } else
7606 /* No loopback */
7607 {
7608 if (params->switch_cfg == SWITCH_CFG_10G)
7609 bnx2x_xgxs_deassert(params);
7610 else
7611 bnx2x_serdes_deassert(bp, params->port);
7f02c4ad 7612
de6eae1f
YR		 7613 bnx2x_link_initialize(params, vars);
7614 msleep(30);
7615 bnx2x_link_int_enable(params);
7616 }
e10bc84d
YR		 7617 return 0;
7618}
de6eae1f
YR		 7619u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7620 u8 reset_ext_phy)
b7737c9b
YR		 7621{
7622 struct bnx2x *bp = params->bp;
cf1d972c 7623 u8 phy_index, port = params->port, clear_latch_ind = 0;
de6eae1f
YR		 7624 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7625 /* disable attentions */
7626 vars->link_status = 0;
7627 bnx2x_update_mng(params, vars->link_status);
7628 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7629 (NIG_MASK_XGXS0_LINK_STATUS |
7630 NIG_MASK_XGXS0_LINK10G |
7631 NIG_MASK_SERDES0_LINK_STATUS |
7632 NIG_MASK_MI_INT));
b7737c9b 7633
de6eae1f
YR		 7634 /* activate nig drain */
7635 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
b7737c9b 7636
de6eae1f
YR		 7637 /* disable nig egress interface */
7638 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7639 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
b7737c9b 7640
de6eae1f
YR		 7641 /* Stop BigMac rx */
7642 bnx2x_bmac_rx_disable(bp, port);
b7737c9b 7643
de6eae1f
YR		 7644 /* disable emac */
7645 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
b7737c9b 7646
de6eae1f
YR		 7647 msleep(10);
7648 /* The PHY reset is controled by GPIO 1
7649 * Hold it as vars low
7650 */
7651 /* clear link led */
7f02c4ad
YR		 7652 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7653
de6eae1f
YR		 7654 if (reset_ext_phy) {
7655 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7656 phy_index++) {
7657 if (params->phy[phy_index].link_reset)
7658 params->phy[phy_index].link_reset(
7659 &params->phy[phy_index],
7660 params);
cf1d972c
YR		 7661 if (params->phy[phy_index].flags &
7662 FLAGS_REARM_LATCH_SIGNAL)
7663 clear_latch_ind = 1;
b7737c9b 7664 }
b7737c9b
YR		 7665 }
7666
cf1d972c
YR		 7667 if (clear_latch_ind) {
7668 /* Clear latching indication */
7669 bnx2x_rearm_latch_signal(bp, port, 0);
7670 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7671 1 << NIG_LATCH_BC_ENABLE_MI_INT);
7672 }
de6eae1f
YR		 7673 if (params->phy[INT_PHY].link_reset)
7674 params->phy[INT_PHY].link_reset(
7675 &params->phy[INT_PHY], params);
7676 /* reset BigMac */
7677 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7678 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
b7737c9b 7679
de6eae1f
YR		 7680 /* disable nig ingress interface */
7681 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7682 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7683 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7684 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7685 vars->link_up = 0;
b7737c9b
YR		 7686 return 0;
7687}
7688
de6eae1f
YR		 7689/****************************************************************************/
7690/* Common function */
7691/****************************************************************************/
f2e0899f
DK		 7692static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7693 u32 shmem_base_path[],
7694 u32 shmem2_base_path[], u8 phy_index,
7695 u32 chip_id)
6bbca910 7696{
e10bc84d
YR		 7697 struct bnx2x_phy phy[PORT_MAX];
7698 struct bnx2x_phy *phy_blk[PORT_MAX];
6bbca910
YR		 7699 u16 val;
7700 s8 port;
f2e0899f 7701 s8 port_of_path = 0;
6bbca910 7702
1d03f069 7703 bnx2x_ext_phy_hw_reset(bp, 0);
6bbca910
YR		 7704 /* PART1 - Reset both phys */
7705 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7706 u32 shmem_base, shmem2_base;
7707 /* In E2, same phy is using for port0 of the two paths */
7708 if (CHIP_IS_E2(bp)) {
7709 shmem_base = shmem_base_path[port];
7710 shmem2_base = shmem2_base_path[port];
7711 port_of_path = 0;
7712 } else {
7713 shmem_base = shmem_base_path[0];
7714 shmem2_base = shmem2_base_path[0];
7715 port_of_path = port;
7716 }
7717
6bbca910 7718 /* Extract the ext phy address for the port */
a22f0788 7719 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 7720 port_of_path, &phy[port]) !=
e10bc84d
YR		 7721 0) {
7722 DP(NETIF_MSG_LINK, "populate_phy failed\n");
7723 return -EINVAL;
7724 }
6bbca910 7725 /* disable attentions */
6a71bbe0
YR		 7726 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7727 port_of_path*4,
6bbca910
YR		 7728 (NIG_MASK_XGXS0_LINK_STATUS |
7729 NIG_MASK_XGXS0_LINK10G |
7730 NIG_MASK_SERDES0_LINK_STATUS |
7731 NIG_MASK_MI_INT));
7732
6bbca910
YR		 7733 /* Need to take the phy out of low power mode in order
7734 to write to access its registers */
7735 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7736 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7737
7738 /* Reset the phy */
e10bc84d 7739 bnx2x_cl45_write(bp, &phy[port],
6bbca910
YR		 7740 MDIO_PMA_DEVAD,
7741 MDIO_PMA_REG_CTRL,
7742 1<<15);
7743 }
7744
7745 /* Add delay of 150ms after reset */
7746 msleep(150);
7747
e10bc84d
YR		 7748 if (phy[PORT_0].addr & 0x1) {
7749 phy_blk[PORT_0] = &(phy[PORT_1]);
7750 phy_blk[PORT_1] = &(phy[PORT_0]);
7751 } else {
7752 phy_blk[PORT_0] = &(phy[PORT_0]);
7753 phy_blk[PORT_1] = &(phy[PORT_1]);
7754 }
7755
6bbca910
YR		 7756 /* PART2 - Download firmware to both phys */
7757 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7758 if (CHIP_IS_E2(bp))
7759 port_of_path = 0;
7760 else
7761 port_of_path = port;
6bbca910 7762
f2e0899f
DK		 7763 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7764 phy_blk[port]->addr);
5c99274b
YR		 7765 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7766 port_of_path))
6bbca910 7767 return -EINVAL;
6bbca910
YR		 7768
7769 /* Only set bit 10 = 1 (Tx power down) */
e10bc84d 7770 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 7771 MDIO_PMA_DEVAD,
7772 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7773
7774 /* Phase1 of TX_POWER_DOWN reset */
e10bc84d 7775 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 7776 MDIO_PMA_DEVAD,
7777 MDIO_PMA_REG_TX_POWER_DOWN,
7778 (val | 1<<10));
7779 }
7780
7781 /* Toggle Transmitter: Power down and then up with 600ms
7782 delay between */
7783 msleep(600);
7784
7785 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
7786 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 7787 /* Phase2 of POWER_DOWN_RESET */
6bbca910 7788 /* Release bit 10 (Release Tx power down) */
e10bc84d 7789 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 7790 MDIO_PMA_DEVAD,
7791 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7792
e10bc84d 7793 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 7794 MDIO_PMA_DEVAD,
7795 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
7796 msleep(15);
7797
7798 /* Read modify write the SPI-ROM version select register */
e10bc84d 7799 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 7800 MDIO_PMA_DEVAD,
7801 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
e10bc84d 7802 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 7803 MDIO_PMA_DEVAD,
7804 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
7805
7806 /* set GPIO2 back to LOW */
7807 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7808 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7809 }
7810 return 0;
6bbca910 7811}
f2e0899f
DK		 7812static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7813 u32 shmem_base_path[],
7814 u32 shmem2_base_path[], u8 phy_index,
7815 u32 chip_id)
de6eae1f
YR		 7816{
7817 u32 val;
7818 s8 port;
7819 struct bnx2x_phy phy;
7820 /* Use port1 because of the static port-swap */
7821 /* Enable the module detection interrupt */
7822 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
7823 val |= ((1<<MISC_REGISTERS_GPIO_3)|
7824 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
7825 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
7826
650154bf 7827 bnx2x_ext_phy_hw_reset(bp, 0);
de6eae1f
YR		 7828 msleep(5);
7829 for (port = 0; port < PORT_MAX; port++) {
f2e0899f
DK		 7830 u32 shmem_base, shmem2_base;
7831
7832 /* In E2, same phy is using for port0 of the two paths */
7833 if (CHIP_IS_E2(bp)) {
7834 shmem_base = shmem_base_path[port];
7835 shmem2_base = shmem2_base_path[port];
7836 } else {
7837 shmem_base = shmem_base_path[0];
7838 shmem2_base = shmem2_base_path[0];
7839 }
de6eae1f 7840 /* Extract the ext phy address for the port */
a22f0788 7841 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 7842 port, &phy) !=
7843 0) {
7844 DP(NETIF_MSG_LINK, "populate phy failed\n");
7845 return -EINVAL;
7846 }
7847
7848 /* Reset phy*/
7849 bnx2x_cl45_write(bp, &phy,
7850 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
7851
7852
7853 /* Set fault module detected LED on */
7854 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
7855 MISC_REGISTERS_GPIO_HIGH,
7856 port);
7857 }
7858
7859 return 0;
7860}
f2e0899f
DK		 7861static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7862 u32 shmem_base_path[],
7863 u32 shmem2_base_path[], u8 phy_index,
7864 u32 chip_id)
4d295db0 7865{
a22f0788 7866 s8 port;
4d295db0 7867 u32 swap_val, swap_override;
e10bc84d
YR		 7868 struct bnx2x_phy phy[PORT_MAX];
7869 struct bnx2x_phy *phy_blk[PORT_MAX];
f2e0899f 7870 s8 port_of_path;
4d295db0
EG		 7871 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7872 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7873
a22f0788 7874 port = 1;
4d295db0 7875
a22f0788
YR		 7876 bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override));
7877
7878 /* Calculate the port based on port swap */
7879 port ^= (swap_val && swap_override);
7880
7881 msleep(5);
bc7f0a05 7882
4d295db0 7883 /* PART1 - Reset both phys */
a22f0788 7884 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7885 u32 shmem_base, shmem2_base;
7886
7887 /* In E2, same phy is using for port0 of the two paths */
7888 if (CHIP_IS_E2(bp)) {
7889 shmem_base = shmem_base_path[port];
7890 shmem2_base = shmem2_base_path[port];
7891 port_of_path = 0;
7892 } else {
7893 shmem_base = shmem_base_path[0];
7894 shmem2_base = shmem2_base_path[0];
7895 port_of_path = port;
7896 }
7897
4d295db0 7898 /* Extract the ext phy address for the port */
a22f0788 7899 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 7900 port_of_path, &phy[port]) !=
e10bc84d
YR		 7901 0) {
7902 DP(NETIF_MSG_LINK, "populate phy failed\n");
7903 return -EINVAL;
7904 }
4d295db0 7905 /* disable attentions */
f2e0899f
DK		 7906 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7907 port_of_path*4,
7908 (NIG_MASK_XGXS0_LINK_STATUS |
7909 NIG_MASK_XGXS0_LINK10G |
7910 NIG_MASK_SERDES0_LINK_STATUS |
7911 NIG_MASK_MI_INT));
4d295db0 7912
4d295db0
EG		 7913
7914 /* Reset the phy */
e10bc84d 7915 bnx2x_cl45_write(bp, &phy[port],
4d295db0
EG		 7916 MDIO_PMA_DEVAD,
7917 MDIO_PMA_REG_CTRL,
7918 1<<15);
7919 }
7920
7921 /* Add delay of 150ms after reset */
7922 msleep(150);
e10bc84d
YR		 7923 if (phy[PORT_0].addr & 0x1) {
7924 phy_blk[PORT_0] = &(phy[PORT_1]);
7925 phy_blk[PORT_1] = &(phy[PORT_0]);
7926 } else {
7927 phy_blk[PORT_0] = &(phy[PORT_0]);
7928 phy_blk[PORT_1] = &(phy[PORT_1]);
7929 }
4d295db0 7930 /* PART2 - Download firmware to both phys */
e10bc84d 7931 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7932 if (CHIP_IS_E2(bp))
7933 port_of_path = 0;
7934 else
7935 port_of_path = port;
7936 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7937 phy_blk[port]->addr);
5c99274b
YR		 7938 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7939 port_of_path))
4d295db0 7940 return -EINVAL;
4d295db0 7941
5c99274b 7942 }
4d295db0
EG		 7943 return 0;
7944}
7945
f2e0899f
DK		 7946static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
7947 u32 shmem2_base_path[], u8 phy_index,
7948 u32 ext_phy_type, u32 chip_id)
6bbca910
YR		 7949{
7950 u8 rc = 0;
6bbca910
YR		 7951
7952 switch (ext_phy_type) {
7953 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
f2e0899f
DK		 7954 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
7955 shmem2_base_path,
7956 phy_index, chip_id);
6bbca910 7957 break;
4d295db0
EG		 7958
7959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7960 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
f2e0899f
DK		 7961 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
7962 shmem2_base_path,
7963 phy_index, chip_id);
4d295db0
EG		 7964 break;
7965
589abe3a
EG		 7966 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7967 /* GPIO1 affects both ports, so there's need to pull
7968 it for single port alone */
f2e0899f
DK		 7969 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
7970 shmem2_base_path,
7971 phy_index, chip_id);
a22f0788
YR		 7972 break;
7973 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7974 rc = -EINVAL;
4f60dab1 7975 break;
6bbca910
YR		 7976 default:
7977 DP(NETIF_MSG_LINK,
7978 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
7979 ext_phy_type);
7980 break;
7981 }
7982
7983 return rc;
7984}
7985
f2e0899f
DK		 7986u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
7987 u32 shmem2_base_path[], u32 chip_id)
a22f0788
YR		 7988{
7989 u8 rc = 0;
b21a3424 7990 u32 phy_ver;
a22f0788
YR		 7991 u8 phy_index;
7992 u32 ext_phy_type, ext_phy_config;
7993 DP(NETIF_MSG_LINK, "Begin common phy init\n");
7994
7995 if (CHIP_REV_IS_EMUL(bp))
7996 return 0;
7997
b21a3424
YR		 7998 /* Check if common init was already done */
7999 phy_ver = REG_RD(bp, shmem_base_path[0] +
8000 offsetof(struct shmem_region,
8001 port_mb[PORT_0].ext_phy_fw_version));
8002 if (phy_ver) {
8003 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8004 phy_ver);
8005 return 0;
8006 }
8007
a22f0788
YR		 8008 /* Read the ext_phy_type for arbitrary port(0) */
8009 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8010 phy_index++) {
8011 ext_phy_config = bnx2x_get_ext_phy_config(bp,
f2e0899f 8012 shmem_base_path[0],
a22f0788
YR		 8013 phy_index, 0);
8014 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
f2e0899f
DK		 8015 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8016 shmem2_base_path,
8017 phy_index, ext_phy_type,
8018 chip_id);
a22f0788
YR		 8019 }
8020 return rc;
8021}
d90d96ba 8022
a22f0788 8023u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
d90d96ba
YR		 8024{
8025 u8 phy_index;
8026 struct bnx2x_phy phy;
8027 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8028 phy_index++) {
a22f0788 8029 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 8030 0, &phy) != 0) {
8031 DP(NETIF_MSG_LINK, "populate phy failed\n");
8032 return 0;
8033 }
8034
8035 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8036 return 1;
8037 }
8038 return 0;
8039}
8040
8041u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8042 u32 shmem_base,
a22f0788 8043 u32 shmem2_base,
d90d96ba
YR		 8044 u8 port)
8045{
8046 u8 phy_index, fan_failure_det_req = 0;
8047 struct bnx2x_phy phy;
8048 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8049 phy_index++) {
a22f0788 8050 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 8051 port, &phy)
8052 != 0) {
8053 DP(NETIF_MSG_LINK, "populate phy failed\n");
8054 return 0;
8055 }
8056 fan_failure_det_req |= (phy.flags &
8057 FLAGS_FAN_FAILURE_DET_REQ);
8058 }
8059 return fan_failure_det_req;
8060}
8061
8062void bnx2x_hw_reset_phy(struct link_params *params)
8063{
8064 u8 phy_index;
8065 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8066 phy_index++) {
8067 if (params->phy[phy_index].hw_reset) {
8068 params->phy[phy_index].hw_reset(
8069 &params->phy[phy_index],
8070 params);
8071 params->phy[phy_index] = phy_null;
8072 }
8073 }
8074}
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