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bnx2x: Add dual-media changes
[mirror_ubuntu-kernels.git] / drivers / net / bnx2x / bnx2x_link.c
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d05c26ce 1/* Copyright 2008-2009 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
7995c64e
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
ea4e040a
YR		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
ea4e040a 26
ea4e040a
YR		 27#include "bnx2x.h"
28
29/********************************************************/
3196a88a 30#define ETH_HLEN 14
ea4e040a
YR		 31#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
32#define ETH_MIN_PACKET_SIZE 60
33#define ETH_MAX_PACKET_SIZE 1500
34#define ETH_MAX_JUMBO_PACKET_SIZE 9600
35#define MDIO_ACCESS_TIMEOUT 1000
36#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 37
38/***********************************************************/
3196a88a 39/* Shortcut definitions */
ea4e040a
YR		 40/***********************************************************/
41
2f904460
EG		 42#define NIG_LATCH_BC_ENABLE_MI_INT 0
43
44#define NIG_STATUS_EMAC0_MI_INT \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 46#define NIG_STATUS_XGXS0_LINK10G \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
48#define NIG_STATUS_XGXS0_LINK_STATUS \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
50#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
52#define NIG_STATUS_SERDES0_LINK_STATUS \
53 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
54#define NIG_MASK_MI_INT \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
56#define NIG_MASK_XGXS0_LINK10G \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
58#define NIG_MASK_XGXS0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
60#define NIG_MASK_SERDES0_LINK_STATUS \
61 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
62
63#define MDIO_AN_CL73_OR_37_COMPLETE \
64 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
65 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
66
67#define XGXS_RESET_BITS \
68 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
73
74#define SERDES_RESET_BITS \
75 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
79
80#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
3196a88a
EG		 82#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83#define AUTONEG_PARALLEL \
ea4e040a 84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 85#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 86 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 87#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 88
89#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
91#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
93#define GP_STATUS_SPEED_MASK \
94 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
95#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
96#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
97#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
98#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
99#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
100#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
101#define GP_STATUS_10G_HIG \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
103#define GP_STATUS_10G_CX4 \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
105#define GP_STATUS_12G_HIG \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
107#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
108#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
109#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
110#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
111#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
112#define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
114
115#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
122#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
123#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
138
139#define PHY_XGXS_FLAG 0x1
140#define PHY_SGMII_FLAG 0x2
141#define PHY_SERDES_FLAG 0x4
142
589abe3a
EG		 143/* */
144#define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147
4d295db0
EG		 148
149#define SFP_EEPROM_COMP_CODE_ADDR 0x3
150 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
151 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
152 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
153
589abe3a
EG		 154#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 157
589abe3a
EG		 158#define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160#define SFP_EEPROM_OPTIONS_SIZE 2
161
4d295db0
EG		 162#define EDC_MODE_LINEAR 0x0022
163#define EDC_MODE_LIMITING 0x0044
164#define EDC_MODE_PASSIVE_DAC 0x0055
165
166
589abe3a 167
ea4e040a
YR		 168/**********************************************************/
169/* INTERFACE */
170/**********************************************************/
e10bc84d
YR		 171
172#define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
173 bnx2x_cl45_write(_bp, _phy, \
7aa0711f 174 (_phy)->def_md_devad, \
ea4e040a
YR		 175 (_bank + (_addr & 0xf)), \
176 _val)
177
e10bc84d
YR		 178#define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
179 bnx2x_cl45_read(_bp, _phy, \
7aa0711f 180 (_phy)->def_md_devad, \
ea4e040a
YR		 181 (_bank + (_addr & 0xf)), \
182 _val)
183
ea4e040a
YR		 184static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
185{
186 u32 val = REG_RD(bp, reg);
187
188 val |= bits;
189 REG_WR(bp, reg, val);
190 return val;
191}
192
193static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
194{
195 u32 val = REG_RD(bp, reg);
196
197 val &= ~bits;
198 REG_WR(bp, reg, val);
199 return val;
200}
201
202static void bnx2x_emac_init(struct link_params *params,
203 struct link_vars *vars)
204{
205 /* reset and unreset the emac core */
206 struct bnx2x *bp = params->bp;
207 u8 port = params->port;
208 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
209 u32 val;
210 u16 timeout;
211
212 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
213 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
214 udelay(5);
215 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
216 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
217
218 /* init emac - use read-modify-write */
219 /* self clear reset */
220 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 221 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 222
223 timeout = 200;
3196a88a 224 do {
ea4e040a
YR		 225 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
226 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
227 if (!timeout) {
228 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
229 return;
230 }
231 timeout--;
3196a88a 232 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 233
234 /* Set mac address */
235 val = ((params->mac_addr[0] << 8) |
236 params->mac_addr[1]);
3196a88a 237 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 238
239 val = ((params->mac_addr[2] << 24) |
240 (params->mac_addr[3] << 16) |
241 (params->mac_addr[4] << 8) |
242 params->mac_addr[5]);
3196a88a 243 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 244}
245
246static u8 bnx2x_emac_enable(struct link_params *params,
247 struct link_vars *vars, u8 lb)
248{
249 struct bnx2x *bp = params->bp;
250 u8 port = params->port;
251 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
252 u32 val;
253
254 DP(NETIF_MSG_LINK, "enabling EMAC\n");
255
256 /* enable emac and not bmac */
257 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
258
259 /* for paladium */
260 if (CHIP_REV_IS_EMUL(bp)) {
261 /* Use lane 1 (of lanes 0-3) */
262 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
263 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
264 port*4, 1);
265 }
266 /* for fpga */
267 else
268
269 if (CHIP_REV_IS_FPGA(bp)) {
270 /* Use lane 1 (of lanes 0-3) */
271 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
272
273 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
274 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
275 0);
276 } else
277 /* ASIC */
278 if (vars->phy_flags & PHY_XGXS_FLAG) {
279 u32 ser_lane = ((params->lane_config &
280 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
281 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
282
283 DP(NETIF_MSG_LINK, "XGXS\n");
284 /* select the master lanes (out of 0-3) */
285 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
286 port*4, ser_lane);
287 /* select XGXS */
288 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
289 port*4, 1);
290
291 } else { /* SerDes */
292 DP(NETIF_MSG_LINK, "SerDes\n");
293 /* select SerDes */
294 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
295 port*4, 0);
296 }
297
811a2f2d
EG		 298 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
299 EMAC_RX_MODE_RESET);
300 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
301 EMAC_TX_MODE_RESET);
ea4e040a
YR		 302
303 if (CHIP_REV_IS_SLOW(bp)) {
304 /* config GMII mode */
305 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 306 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
ea4e040a
YR		 307 (val | EMAC_MODE_PORT_GMII));
308 } else { /* ASIC */
309 /* pause enable/disable */
310 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
311 EMAC_RX_MODE_FLOW_EN);
c0700f90 312 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 313 bnx2x_bits_en(bp, emac_base +
314 EMAC_REG_EMAC_RX_MODE,
315 EMAC_RX_MODE_FLOW_EN);
316
317 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 318 (EMAC_TX_MODE_EXT_PAUSE_EN |
319 EMAC_TX_MODE_FLOW_EN));
c0700f90 320 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 321 bnx2x_bits_en(bp, emac_base +
322 EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 323 (EMAC_TX_MODE_EXT_PAUSE_EN |
324 EMAC_TX_MODE_FLOW_EN));
ea4e040a
YR		 325 }
326
327 /* KEEP_VLAN_TAG, promiscuous */
328 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
329 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
3196a88a 330 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 331
332 /* Set Loopback */
333 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
334 if (lb)
335 val |= 0x810;
336 else
337 val &= ~0x810;
3196a88a 338 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 339
6c55c3cd
EG		 340 /* enable emac */
341 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
342
ea4e040a 343 /* enable emac for jumbo packets */
3196a88a 344 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 345 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
346 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
347
348 /* strip CRC */
349 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
350
351 /* disable the NIG in/out to the bmac */
352 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
353 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
354 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
355
356 /* enable the NIG in/out to the emac */
357 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
358 val = 0;
c0700f90 359 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 360 val = 1;
361
362 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
363 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
364
365 if (CHIP_REV_IS_EMUL(bp)) {
366 /* take the BigMac out of reset */
367 REG_WR(bp,
368 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
369 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
370
371 /* enable access for bmac registers */
372 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
6f65497b
EG		 373 } else
374 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 375
376 vars->mac_type = MAC_TYPE_EMAC;
377 return 0;
378}
379
380
381
382static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
383 u8 is_lb)
384{
385 struct bnx2x *bp = params->bp;
386 u8 port = params->port;
387 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
388 NIG_REG_INGRESS_BMAC0_MEM;
389 u32 wb_data[2];
390 u32 val;
391
392 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
393 /* reset and unreset the BigMac */
394 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
395 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
396 msleep(1);
397
398 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
399 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
400
401 /* enable access for bmac registers */
402 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
403
404 /* XGXS control */
405 wb_data[0] = 0x3c;
406 wb_data[1] = 0;
407 REG_WR_DMAE(bp, bmac_addr +
408 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
409 wb_data, 2);
410
411 /* tx MAC SA */
412 wb_data[0] = ((params->mac_addr[2] << 24) |
413 (params->mac_addr[3] << 16) |
414 (params->mac_addr[4] << 8) |
415 params->mac_addr[5]);
416 wb_data[1] = ((params->mac_addr[0] << 8) |
417 params->mac_addr[1]);
418 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
419 wb_data, 2);
420
421 /* tx control */
422 val = 0xc0;
c0700f90 423 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 424 val |= 0x800000;
425 wb_data[0] = val;
426 wb_data[1] = 0;
427 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
428 wb_data, 2);
429
430 /* mac control */
431 val = 0x3;
432 if (is_lb) {
433 val |= 0x4;
434 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
435 }
436 wb_data[0] = val;
437 wb_data[1] = 0;
438 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
439 wb_data, 2);
440
ea4e040a
YR		 441 /* set rx mtu */
442 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
443 wb_data[1] = 0;
444 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
445 wb_data, 2);
446
447 /* rx control set to don't strip crc */
448 val = 0x14;
c0700f90 449 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 450 val |= 0x20;
451 wb_data[0] = val;
452 wb_data[1] = 0;
453 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
454 wb_data, 2);
455
456 /* set tx mtu */
457 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
458 wb_data[1] = 0;
459 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
460 wb_data, 2);
461
462 /* set cnt max size */
463 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
464 wb_data[1] = 0;
465 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
466 wb_data, 2);
467
468 /* configure safc */
469 wb_data[0] = 0x1000200;
470 wb_data[1] = 0;
471 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
472 wb_data, 2);
473 /* fix for emulation */
474 if (CHIP_REV_IS_EMUL(bp)) {
475 wb_data[0] = 0xf000;
476 wb_data[1] = 0;
477 REG_WR_DMAE(bp,
478 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
479 wb_data, 2);
480 }
481
482 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
483 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
484 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
485 val = 0;
c0700f90 486 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 487 val = 1;
488 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
489 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
490 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
491 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
492 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
493 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
494
495 vars->mac_type = MAC_TYPE_BMAC;
496 return 0;
497}
498
ea4e040a
YR		 499
500static void bnx2x_update_mng(struct link_params *params, u32 link_status)
501{
502 struct bnx2x *bp = params->bp;
ab6ad5a4 503
ea4e040a
YR		 504 REG_WR(bp, params->shmem_base +
505 offsetof(struct shmem_region,
506 port_mb[params->port].link_status),
507 link_status);
508}
509
510static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
511{
512 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
513 NIG_REG_INGRESS_BMAC0_MEM;
514 u32 wb_data[2];
3196a88a 515 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 516
517 /* Only if the bmac is out of reset */
518 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
519 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
520 nig_bmac_enable) {
521
522 /* Clear Rx Enable bit in BMAC_CONTROL register */
523 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
524 wb_data, 2);
525 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
526 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
527 wb_data, 2);
528
529 msleep(1);
530 }
531}
532
533static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
534 u32 line_speed)
535{
536 struct bnx2x *bp = params->bp;
537 u8 port = params->port;
538 u32 init_crd, crd;
539 u32 count = 1000;
ea4e040a
YR		 540
541 /* disable port */
542 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
543
544 /* wait for init credit */
545 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
546 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
547 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
548
549 while ((init_crd != crd) && count) {
550 msleep(5);
551
552 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
553 count--;
554 }
555 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
556 if (init_crd != crd) {
557 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
558 init_crd, crd);
559 return -EINVAL;
560 }
561
c0700f90 562 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 563 line_speed == SPEED_10 ||
564 line_speed == SPEED_100 ||
565 line_speed == SPEED_1000 ||
566 line_speed == SPEED_2500) {
567 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 568 /* update threshold */
569 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
570 /* update init credit */
8c99e7b0 571 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 572
573 } else {
574 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
575 ETH_OVREHEAD)/16;
8c99e7b0 576 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 577 /* update threshold */
578 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
579 /* update init credit */
580 switch (line_speed) {
ea4e040a
YR		 581 case SPEED_10000:
582 init_crd = thresh + 553 - 22;
583 break;
584
585 case SPEED_12000:
586 init_crd = thresh + 664 - 22;
587 break;
588
589 case SPEED_13000:
590 init_crd = thresh + 742 - 22;
591 break;
592
593 case SPEED_16000:
594 init_crd = thresh + 778 - 22;
595 break;
596 default:
597 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
598 line_speed);
599 return -EINVAL;
ea4e040a
YR		 600 }
601 }
602 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
603 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
604 line_speed, init_crd);
605
606 /* probe the credit changes */
607 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
608 msleep(5);
609 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
610
611 /* enable port */
612 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
613 return 0;
614}
615
c18aa15d
YR		 616static u32 bnx2x_get_emac_base(struct bnx2x *bp,
617 u32 mdc_mdio_access, u8 port)
ea4e040a 618{
c18aa15d
YR		 619 u32 emac_base = 0;
620 switch (mdc_mdio_access) {
621 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
622 break;
623 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
624 if (REG_RD(bp, NIG_REG_PORT_SWAP))
625 emac_base = GRCBASE_EMAC1;
626 else
627 emac_base = GRCBASE_EMAC0;
628 break;
629 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
589abe3a
EG		 630 if (REG_RD(bp, NIG_REG_PORT_SWAP))
631 emac_base = GRCBASE_EMAC0;
632 else
633 emac_base = GRCBASE_EMAC1;
ea4e040a 634 break;
c18aa15d
YR		 635 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
636 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
637 break;
638 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
6378c025 639 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 640 break;
641 default:
ea4e040a
YR		 642 break;
643 }
644 return emac_base;
645
646}
647
e10bc84d
YR		 648u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
649 u8 devad, u16 reg, u16 val)
ea4e040a
YR		 650{
651 u32 tmp, saved_mode;
652 u8 i, rc = 0;
ea4e040a
YR		 653
654 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
655 * (a value of 49==0x31) and make sure that the AUTO poll is off
656 */
589abe3a 657
e10bc84d 658 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 659 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
660 EMAC_MDIO_MODE_CLOCK_CNT);
661 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
662 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 663 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
664 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 665 udelay(40);
666
667 /* address */
668
e10bc84d 669 tmp = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 670 EMAC_MDIO_COMM_COMMAND_ADDRESS |
671 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 672 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 673
674 for (i = 0; i < 50; i++) {
675 udelay(10);
676
e10bc84d
YR		 677 tmp = REG_RD(bp, phy->mdio_ctrl +
678 EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 679 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
680 udelay(5);
681 break;
682 }
683 }
684 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
685 DP(NETIF_MSG_LINK, "write phy register failed\n");
686 rc = -EFAULT;
687 } else {
688 /* data */
e10bc84d 689 tmp = ((phy->addr << 21) | (devad << 16) | val |
ea4e040a
YR		 690 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
691 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 692 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 693
694 for (i = 0; i < 50; i++) {
695 udelay(10);
696
e10bc84d 697 tmp = REG_RD(bp, phy->mdio_ctrl +
ea4e040a
YR		 698 EMAC_REG_EMAC_MDIO_COMM);
699 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
700 udelay(5);
701 break;
702 }
703 }
704 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
705 DP(NETIF_MSG_LINK, "write phy register failed\n");
706 rc = -EFAULT;
707 }
708 }
709
710 /* Restore the saved mode */
e10bc84d 711 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 712
713 return rc;
714}
715
e10bc84d
YR		 716u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
717 u8 devad, u16 reg, u16 *ret_val)
ea4e040a
YR		 718{
719 u32 val, saved_mode;
720 u16 i;
721 u8 rc = 0;
722
ea4e040a
YR		 723 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
724 * (a value of 49==0x31) and make sure that the AUTO poll is off
725 */
589abe3a 726
e10bc84d
YR		 727 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
728 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
ea4e040a
YR		 729 EMAC_MDIO_MODE_CLOCK_CNT));
730 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
ab6ad5a4 731 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 732 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
733 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 734 udelay(40);
735
736 /* address */
e10bc84d 737 val = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 738 EMAC_MDIO_COMM_COMMAND_ADDRESS |
739 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 740 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 741
742 for (i = 0; i < 50; i++) {
743 udelay(10);
744
e10bc84d 745 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 746 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
747 udelay(5);
748 break;
749 }
750 }
751 if (val & EMAC_MDIO_COMM_START_BUSY) {
752 DP(NETIF_MSG_LINK, "read phy register failed\n");
753
754 *ret_val = 0;
755 rc = -EFAULT;
756
757 } else {
758 /* data */
e10bc84d 759 val = ((phy->addr << 21) | (devad << 16) |
ea4e040a
YR		 760 EMAC_MDIO_COMM_COMMAND_READ_45 |
761 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 762 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 763
764 for (i = 0; i < 50; i++) {
765 udelay(10);
766
e10bc84d 767 val = REG_RD(bp, phy->mdio_ctrl +
ea4e040a
YR		 768 EMAC_REG_EMAC_MDIO_COMM);
769 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
770 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
771 break;
772 }
773 }
774 if (val & EMAC_MDIO_COMM_START_BUSY) {
775 DP(NETIF_MSG_LINK, "read phy register failed\n");
776
777 *ret_val = 0;
778 rc = -EFAULT;
779 }
780 }
781
782 /* Restore the saved mode */
e10bc84d 783 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 784
785 return rc;
786}
787
e10bc84d
YR		 788u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
789 u8 devad, u16 reg, u16 *ret_val)
790{
791 u8 phy_index;
792 /**
793 * Probe for the phy according to the given phy_addr, and execute
794 * the read request on it
795 */
796 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
797 if (params->phy[phy_index].addr == phy_addr) {
798 return bnx2x_cl45_read(params->bp,
799 &params->phy[phy_index], devad,
800 reg, ret_val);
801 }
802 }
803 return -EINVAL;
804}
805
806u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
807 u8 devad, u16 reg, u16 val)
808{
809 u8 phy_index;
810 /**
811 * Probe for the phy according to the given phy_addr, and execute
812 * the write request on it
813 */
814 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
815 if (params->phy[phy_index].addr == phy_addr) {
816 return bnx2x_cl45_write(params->bp,
817 &params->phy[phy_index], devad,
818 reg, val);
819 }
820 }
821 return -EINVAL;
822}
823
ea4e040a 824static void bnx2x_set_aer_mmd(struct link_params *params,
e10bc84d 825 struct bnx2x_phy *phy)
ea4e040a
YR		 826{
827 struct bnx2x *bp = params->bp;
828 u32 ser_lane;
829 u16 offset;
830
831 ser_lane = ((params->lane_config &
832 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
833 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
834
e10bc84d
YR		 835 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
836 (phy->addr + ser_lane) : 0;
ea4e040a 837
e10bc84d 838 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 839 MDIO_REG_BANK_AER_BLOCK,
840 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
841}
842
de6eae1f
YR		 843/******************************************************************/
844/* Internal phy section */
845/******************************************************************/
ea4e040a 846
de6eae1f
YR		 847static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
848{
849 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a 850
de6eae1f
YR		 851 /* Set Clause 22 */
852 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
853 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
854 udelay(500);
855 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
856 udelay(500);
857 /* Set Clause 45 */
858 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
ea4e040a
YR		 859}
860
de6eae1f 861static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
ea4e040a 862{
de6eae1f 863 u32 val;
ea4e040a 864
de6eae1f 865 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
ea4e040a 866
de6eae1f 867 val = SERDES_RESET_BITS << (port*16);
c1b73990 868
de6eae1f
YR		 869 /* reset and unreset the SerDes/XGXS */
870 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
871 udelay(500);
872 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
ea4e040a 873
de6eae1f 874 bnx2x_set_serdes_access(bp, port);
ea4e040a 875
de6eae1f
YR		 876 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
877 port*0x10,
878 DEFAULT_PHY_DEV_ADDR);
879}
880
881static void bnx2x_xgxs_deassert(struct link_params *params)
882{
883 struct bnx2x *bp = params->bp;
884 u8 port;
885 u32 val;
886 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
887 port = params->port;
888
889 val = XGXS_RESET_BITS << (port*16);
890
891 /* reset and unreset the SerDes/XGXS */
892 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
893 udelay(500);
894 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
895
896 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
897 port*0x18, 0);
898 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
899 params->phy[INT_PHY].def_md_devad);
900}
901
a22f0788 902
de6eae1f
YR		 903void bnx2x_link_status_update(struct link_params *params,
904 struct link_vars *vars)
905{
906 struct bnx2x *bp = params->bp;
907 u8 link_10g;
908 u8 port = params->port;
909
de6eae1f
YR		 910 vars->link_status = REG_RD(bp, params->shmem_base +
911 offsetof(struct shmem_region,
912 port_mb[port].link_status));
913
914 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
915
916 if (vars->link_up) {
917 DP(NETIF_MSG_LINK, "phy link up\n");
918
919 vars->phy_link_up = 1;
920 vars->duplex = DUPLEX_FULL;
921 switch (vars->link_status &
922 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
923 case LINK_10THD:
924 vars->duplex = DUPLEX_HALF;
925 /* fall thru */
926 case LINK_10TFD:
927 vars->line_speed = SPEED_10;
928 break;
929
930 case LINK_100TXHD:
931 vars->duplex = DUPLEX_HALF;
932 /* fall thru */
933 case LINK_100T4:
934 case LINK_100TXFD:
935 vars->line_speed = SPEED_100;
936 break;
937
938 case LINK_1000THD:
939 vars->duplex = DUPLEX_HALF;
940 /* fall thru */
941 case LINK_1000TFD:
942 vars->line_speed = SPEED_1000;
943 break;
944
945 case LINK_2500THD:
946 vars->duplex = DUPLEX_HALF;
947 /* fall thru */
948 case LINK_2500TFD:
949 vars->line_speed = SPEED_2500;
950 break;
951
952 case LINK_10GTFD:
953 vars->line_speed = SPEED_10000;
954 break;
955
956 case LINK_12GTFD:
957 vars->line_speed = SPEED_12000;
958 break;
959
960 case LINK_12_5GTFD:
961 vars->line_speed = SPEED_12500;
962 break;
963
964 case LINK_13GTFD:
965 vars->line_speed = SPEED_13000;
966 break;
967
968 case LINK_15GTFD:
969 vars->line_speed = SPEED_15000;
970 break;
971
972 case LINK_16GTFD:
973 vars->line_speed = SPEED_16000;
974 break;
975
976 default:
977 break;
978 }
979
980 vars->flow_ctrl = 0;
981 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
982 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
983
984 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
985 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
986
987 if (!vars->flow_ctrl)
988 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
989
990 if (vars->line_speed &&
991 ((vars->line_speed == SPEED_10) ||
992 (vars->line_speed == SPEED_100))) {
993 vars->phy_flags |= PHY_SGMII_FLAG;
994 } else {
995 vars->phy_flags &= ~PHY_SGMII_FLAG;
996 }
997
998 /* anything 10 and over uses the bmac */
999 link_10g = ((vars->line_speed == SPEED_10000) ||
1000 (vars->line_speed == SPEED_12000) ||
1001 (vars->line_speed == SPEED_12500) ||
1002 (vars->line_speed == SPEED_13000) ||
1003 (vars->line_speed == SPEED_15000) ||
1004 (vars->line_speed == SPEED_16000));
1005 if (link_10g)
1006 vars->mac_type = MAC_TYPE_BMAC;
1007 else
1008 vars->mac_type = MAC_TYPE_EMAC;
1009
1010 } else { /* link down */
1011 DP(NETIF_MSG_LINK, "phy link down\n");
1012
1013 vars->phy_link_up = 0;
1014
1015 vars->line_speed = 0;
1016 vars->duplex = DUPLEX_FULL;
1017 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1018
1019 /* indicate no mac active */
1020 vars->mac_type = MAC_TYPE_NONE;
1021 }
1022
1023 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
1024 vars->link_status, vars->phy_link_up);
1025 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
1026 vars->line_speed, vars->duplex, vars->flow_ctrl);
1027}
1028
1029
1030static void bnx2x_set_master_ln(struct link_params *params,
1031 struct bnx2x_phy *phy)
1032{
1033 struct bnx2x *bp = params->bp;
1034 u16 new_master_ln, ser_lane;
1035 ser_lane = ((params->lane_config &
1036 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1037 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1038
1039 /* set the master_ln for AN */
1040 CL45_RD_OVER_CL22(bp, phy,
1041 MDIO_REG_BANK_XGXS_BLOCK2,
1042 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1043 &new_master_ln);
1044
1045 CL45_WR_OVER_CL22(bp, phy,
1046 MDIO_REG_BANK_XGXS_BLOCK2 ,
1047 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1048 (new_master_ln | ser_lane));
1049}
1050
1051static u8 bnx2x_reset_unicore(struct link_params *params,
1052 struct bnx2x_phy *phy,
1053 u8 set_serdes)
1054{
1055 struct bnx2x *bp = params->bp;
1056 u16 mii_control;
1057 u16 i;
1058
1059 CL45_RD_OVER_CL22(bp, phy,
1060 MDIO_REG_BANK_COMBO_IEEE0,
1061 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1062
1063 /* reset the unicore */
1064 CL45_WR_OVER_CL22(bp, phy,
1065 MDIO_REG_BANK_COMBO_IEEE0,
1066 MDIO_COMBO_IEEE0_MII_CONTROL,
1067 (mii_control |
1068 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1069 if (set_serdes)
1070 bnx2x_set_serdes_access(bp, params->port);
1071
1072 /* wait for the reset to self clear */
1073 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1074 udelay(5);
1075
1076 /* the reset erased the previous bank value */
1077 CL45_RD_OVER_CL22(bp, phy,
1078 MDIO_REG_BANK_COMBO_IEEE0,
1079 MDIO_COMBO_IEEE0_MII_CONTROL,
1080 &mii_control);
1081
1082 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1083 udelay(5);
1084 return 0;
1085 }
1086 }
ea4e040a
YR		 1087
1088 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1089 return -EINVAL;
1090
1091}
1092
e10bc84d
YR		 1093static void bnx2x_set_swap_lanes(struct link_params *params,
1094 struct bnx2x_phy *phy)
ea4e040a
YR		 1095{
1096 struct bnx2x *bp = params->bp;
1097 /* Each two bits represents a lane number:
1098 No swap is 0123 => 0x1b no need to enable the swap */
1099 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1100
1101 ser_lane = ((params->lane_config &
1102 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1103 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1104 rx_lane_swap = ((params->lane_config &
1105 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1106 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1107 tx_lane_swap = ((params->lane_config &
1108 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1109 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1110
1111 if (rx_lane_swap != 0x1b) {
e10bc84d 1112 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1113 MDIO_REG_BANK_XGXS_BLOCK2,
1114 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1115 (rx_lane_swap |
1116 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1117 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1118 } else {
e10bc84d 1119 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1120 MDIO_REG_BANK_XGXS_BLOCK2,
1121 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1122 }
1123
1124 if (tx_lane_swap != 0x1b) {
e10bc84d 1125 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1126 MDIO_REG_BANK_XGXS_BLOCK2,
1127 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1128 (tx_lane_swap |
1129 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1130 } else {
e10bc84d 1131 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1132 MDIO_REG_BANK_XGXS_BLOCK2,
1133 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1134 }
1135}
1136
e10bc84d
YR		 1137static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1138 struct link_params *params)
ea4e040a
YR		 1139{
1140 struct bnx2x *bp = params->bp;
1141 u16 control2;
e10bc84d 1142 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1143 MDIO_REG_BANK_SERDES_DIGITAL,
1144 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1145 &control2);
7aa0711f 1146 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
18afb0a6
YR		 1147 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1148 else
1149 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
7aa0711f
YR		 1150 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1151 phy->speed_cap_mask, control2);
e10bc84d 1152 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1153 MDIO_REG_BANK_SERDES_DIGITAL,
1154 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1155 control2);
1156
e10bc84d 1157 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
c18aa15d 1158 (phy->speed_cap_mask &
18afb0a6 1159 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 1160 DP(NETIF_MSG_LINK, "XGXS\n");
1161
e10bc84d 1162 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1163 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1164 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1165 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1166
e10bc84d 1167 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1168 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1169 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1170 &control2);
1171
1172
1173 control2 |=
1174 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1175
e10bc84d 1176 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1177 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1178 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1179 control2);
1180
1181 /* Disable parallel detection of HiG */
e10bc84d 1182 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1183 MDIO_REG_BANK_XGXS_BLOCK2,
1184 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1185 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1186 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1187 }
1188}
1189
e10bc84d
YR		 1190static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1191 struct link_params *params,
239d686d
EG		 1192 struct link_vars *vars,
1193 u8 enable_cl73)
ea4e040a
YR		 1194{
1195 struct bnx2x *bp = params->bp;
1196 u16 reg_val;
1197
1198 /* CL37 Autoneg */
e10bc84d 1199 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1200 MDIO_REG_BANK_COMBO_IEEE0,
1201 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1202
1203 /* CL37 Autoneg Enabled */
8c99e7b0 1204 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1205 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1206 else /* CL37 Autoneg Disabled */
1207 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1208 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1209
e10bc84d 1210 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1211 MDIO_REG_BANK_COMBO_IEEE0,
1212 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1213
1214 /* Enable/Disable Autodetection */
1215
e10bc84d 1216 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1217 MDIO_REG_BANK_SERDES_DIGITAL,
1218 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 1219 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1220 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1221 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 1222 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1223 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1224 else
1225 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1226
e10bc84d 1227 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1228 MDIO_REG_BANK_SERDES_DIGITAL,
1229 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1230
1231 /* Enable TetonII and BAM autoneg */
e10bc84d 1232 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1233 MDIO_REG_BANK_BAM_NEXT_PAGE,
1234 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1235 &reg_val);
8c99e7b0 1236 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1237 /* Enable BAM aneg Mode and TetonII aneg Mode */
1238 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1239 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1240 } else {
1241 /* TetonII and BAM Autoneg Disabled */
1242 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1243 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1244 }
e10bc84d 1245 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1246 MDIO_REG_BANK_BAM_NEXT_PAGE,
1247 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1248 reg_val);
1249
239d686d
EG		 1250 if (enable_cl73) {
1251 /* Enable Cl73 FSM status bits */
e10bc84d 1252 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1253 MDIO_REG_BANK_CL73_USERB0,
1254 MDIO_CL73_USERB0_CL73_UCTRL,
7846e471 1255 0xe);
239d686d
EG		 1256
1257 /* Enable BAM Station Manager*/
e10bc84d 1258 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1259 MDIO_REG_BANK_CL73_USERB0,
1260 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1261 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1262 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1263 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1264
7846e471 1265 /* Advertise CL73 link speeds */
e10bc84d 1266 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1267 MDIO_REG_BANK_CL73_IEEEB1,
1268 MDIO_CL73_IEEEB1_AN_ADV2,
1269 &reg_val);
7aa0711f 1270 if (phy->speed_cap_mask &
7846e471
YR		 1271 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1272 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
7aa0711f 1273 if (phy->speed_cap_mask &
7846e471
YR		 1274 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1275 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d 1276
e10bc84d 1277 CL45_WR_OVER_CL22(bp, phy,
de6eae1f
YR		 1278 MDIO_REG_BANK_CL73_IEEEB1,
1279 MDIO_CL73_IEEEB1_AN_ADV2,
1280 reg_val);
239d686d 1281
239d686d
EG		 1282 /* CL73 Autoneg Enabled */
1283 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1284
1285 } else /* CL73 Autoneg Disabled */
1286 reg_val = 0;
ea4e040a 1287
e10bc84d 1288 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1289 MDIO_REG_BANK_CL73_IEEEB0,
1290 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1291}
1292
1293/* program SerDes, forced speed */
e10bc84d
YR		 1294static void bnx2x_program_serdes(struct bnx2x_phy *phy,
1295 struct link_params *params,
8c99e7b0 1296 struct link_vars *vars)
ea4e040a
YR		 1297{
1298 struct bnx2x *bp = params->bp;
1299 u16 reg_val;
1300
57937203 1301 /* program duplex, disable autoneg and sgmii*/
e10bc84d 1302 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1303 MDIO_REG_BANK_COMBO_IEEE0,
1304 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1305 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 1306 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1307 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
7aa0711f 1308 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a 1309 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
e10bc84d 1310 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1311 MDIO_REG_BANK_COMBO_IEEE0,
1312 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1313
1314 /* program speed
1315 - needed only if the speed is greater than 1G (2.5G or 10G) */
e10bc84d 1316 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1317 MDIO_REG_BANK_SERDES_DIGITAL,
1318 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 1319 /* clearing the speed value before setting the right speed */
1320 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1321
1322 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1323 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1324
1325 if (!((vars->line_speed == SPEED_1000) ||
1326 (vars->line_speed == SPEED_100) ||
1327 (vars->line_speed == SPEED_10))) {
1328
ea4e040a
YR		 1329 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1330 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 1331 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 1332 reg_val |=
1333 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 1334 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 1335 reg_val |=
1336 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 1337 }
1338
e10bc84d 1339 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1340 MDIO_REG_BANK_SERDES_DIGITAL,
1341 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 1342
ea4e040a
YR		 1343}
1344
e10bc84d
YR		 1345static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
1346 struct link_params *params)
ea4e040a
YR		 1347{
1348 struct bnx2x *bp = params->bp;
1349 u16 val = 0;
1350
1351 /* configure the 48 bits for BAM AN */
1352
1353 /* set extended capabilities */
7aa0711f 1354 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
ea4e040a 1355 val |= MDIO_OVER_1G_UP1_2_5G;
7aa0711f 1356 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
ea4e040a 1357 val |= MDIO_OVER_1G_UP1_10G;
e10bc84d 1358 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1359 MDIO_REG_BANK_OVER_1G,
1360 MDIO_OVER_1G_UP1, val);
1361
e10bc84d 1362 CL45_WR_OVER_CL22(bp, phy,
ea4e040a 1363 MDIO_REG_BANK_OVER_1G,
239d686d 1364 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 1365}
1366
e10bc84d
YR		 1367static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
1368 struct link_params *params, u16 *ieee_fc)
ea4e040a 1369{
d5cb9e99 1370 struct bnx2x *bp = params->bp;
8c99e7b0 1371 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
ea4e040a
YR		 1372 /* resolve pause mode and advertisement
1373 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1374
7aa0711f 1375 switch (phy->req_flow_ctrl) {
c0700f90
DM		 1376 case BNX2X_FLOW_CTRL_AUTO:
1377 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
8c99e7b0 1378 *ieee_fc |=
ea4e040a
YR		 1379 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1380 } else {
8c99e7b0 1381 *ieee_fc |=
ea4e040a
YR		 1382 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1383 }
1384 break;
c0700f90 1385 case BNX2X_FLOW_CTRL_TX:
8c99e7b0 1386 *ieee_fc |=
ea4e040a
YR		 1387 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1388 break;
1389
c0700f90
DM		 1390 case BNX2X_FLOW_CTRL_RX:
1391 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 1392 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 1393 break;
1394
c0700f90 1395 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 1396 default:
8c99e7b0 1397 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 1398 break;
1399 }
d5cb9e99 1400 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
8c99e7b0 1401}
ea4e040a 1402
e10bc84d
YR		 1403static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
1404 struct link_params *params,
1ef70b9c 1405 u16 ieee_fc)
8c99e7b0
YR		 1406{
1407 struct bnx2x *bp = params->bp;
7846e471 1408 u16 val;
8c99e7b0 1409 /* for AN, we are always publishing full duplex */
ea4e040a 1410
e10bc84d 1411 CL45_WR_OVER_CL22(bp, phy,
ea4e040a 1412 MDIO_REG_BANK_COMBO_IEEE0,
1ef70b9c 1413 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
e10bc84d 1414 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1415 MDIO_REG_BANK_CL73_IEEEB1,
1416 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1417 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1418 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
e10bc84d 1419 CL45_WR_OVER_CL22(bp, phy,
7846e471
YR		 1420 MDIO_REG_BANK_CL73_IEEEB1,
1421 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 1422}
1423
e10bc84d
YR		 1424static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
1425 struct link_params *params,
1426 u8 enable_cl73)
ea4e040a
YR		 1427{
1428 struct bnx2x *bp = params->bp;
3a36f2ef 1429 u16 mii_control;
239d686d 1430
ea4e040a 1431 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 1432 /* Enable and restart BAM/CL37 aneg */
ea4e040a 1433
239d686d 1434 if (enable_cl73) {
e10bc84d 1435 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1436 MDIO_REG_BANK_CL73_IEEEB0,
1437 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1438 &mii_control);
1439
e10bc84d 1440 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1441 MDIO_REG_BANK_CL73_IEEEB0,
1442 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1443 (mii_control |
1444 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1445 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1446 } else {
1447
e10bc84d 1448 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1449 MDIO_REG_BANK_COMBO_IEEE0,
1450 MDIO_COMBO_IEEE0_MII_CONTROL,
1451 &mii_control);
1452 DP(NETIF_MSG_LINK,
1453 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1454 mii_control);
e10bc84d 1455 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1456 MDIO_REG_BANK_COMBO_IEEE0,
1457 MDIO_COMBO_IEEE0_MII_CONTROL,
1458 (mii_control |
1459 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1460 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1461 }
ea4e040a
YR		 1462}
1463
e10bc84d
YR		 1464static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
1465 struct link_params *params,
8c99e7b0 1466 struct link_vars *vars)
ea4e040a
YR		 1467{
1468 struct bnx2x *bp = params->bp;
1469 u16 control1;
1470
1471 /* in SGMII mode, the unicore is always slave */
1472
e10bc84d 1473 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1474 MDIO_REG_BANK_SERDES_DIGITAL,
1475 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1476 &control1);
1477 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1478 /* set sgmii mode (and not fiber) */
1479 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1480 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1481 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
e10bc84d 1482 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1483 MDIO_REG_BANK_SERDES_DIGITAL,
1484 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1485 control1);
1486
1487 /* if forced speed */
8c99e7b0 1488 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 1489 /* set speed, disable autoneg */
1490 u16 mii_control;
1491
e10bc84d 1492 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1493 MDIO_REG_BANK_COMBO_IEEE0,
1494 MDIO_COMBO_IEEE0_MII_CONTROL,
1495 &mii_control);
1496 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1497 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1498 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1499
8c99e7b0 1500 switch (vars->line_speed) {
ea4e040a
YR		 1501 case SPEED_100:
1502 mii_control |=
1503 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1504 break;
1505 case SPEED_1000:
1506 mii_control |=
1507 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1508 break;
1509 case SPEED_10:
1510 /* there is nothing to set for 10M */
1511 break;
1512 default:
1513 /* invalid speed for SGMII */
8c99e7b0
YR		 1514 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1515 vars->line_speed);
ea4e040a
YR		 1516 break;
1517 }
1518
1519 /* setting the full duplex */
7aa0711f 1520 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a
YR		 1521 mii_control |=
1522 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
e10bc84d 1523 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1524 MDIO_REG_BANK_COMBO_IEEE0,
1525 MDIO_COMBO_IEEE0_MII_CONTROL,
1526 mii_control);
1527
1528 } else { /* AN mode */
1529 /* enable and restart AN */
e10bc84d 1530 bnx2x_restart_autoneg(phy, params, 0);
ea4e040a
YR		 1531 }
1532}
1533
1534
1535/*
1536 * link management
1537 */
1538
1539static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0
YR		 1540{ /* LD LP */
1541 switch (pause_result) { /* ASYM P ASYM P */
1542 case 0xb: /* 1 0 1 1 */
c0700f90 1543 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 1544 break;
1545
8c99e7b0 1546 case 0xe: /* 1 1 1 0 */
c0700f90 1547 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 1548 break;
1549
8c99e7b0
YR		 1550 case 0x5: /* 0 1 0 1 */
1551 case 0x7: /* 0 1 1 1 */
1552 case 0xd: /* 1 1 0 1 */
1553 case 0xf: /* 1 1 1 1 */
c0700f90 1554 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 1555 break;
1556
1557 default:
1558 break;
1559 }
7aa0711f
YR		 1560 if (pause_result & (1<<0))
1561 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
1562 if (pause_result & (1<<1))
1563 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
1564
ea4e040a
YR		 1565}
1566
e10bc84d
YR		 1567static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
1568 struct link_params *params)
15ddd2d0
YR		 1569{
1570 struct bnx2x *bp = params->bp;
1571 u16 pd_10g, status2_1000x;
7aa0711f
YR		 1572 if (phy->req_line_speed != SPEED_AUTO_NEG)
1573 return 0;
e10bc84d 1574 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 1575 MDIO_REG_BANK_SERDES_DIGITAL,
1576 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1577 &status2_1000x);
e10bc84d 1578 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 1579 MDIO_REG_BANK_SERDES_DIGITAL,
1580 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1581 &status2_1000x);
1582 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
1583 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
1584 params->port);
1585 return 1;
1586 }
1587
e10bc84d 1588 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 1589 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1590 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1591 &pd_10g);
1592
1593 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
1594 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
1595 params->port);
1596 return 1;
1597 }
1598 return 0;
1599}
ea4e040a 1600
e10bc84d
YR		 1601static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
1602 struct link_params *params,
1603 struct link_vars *vars,
1604 u32 gp_status)
ea4e040a
YR		 1605{
1606 struct bnx2x *bp = params->bp;
3196a88a
EG		 1607 u16 ld_pause; /* local driver */
1608 u16 lp_pause; /* link partner */
ea4e040a
YR		 1609 u16 pause_result;
1610
c0700f90 1611 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1612
1613 /* resolve from gp_status in case of AN complete and not sgmii */
7aa0711f
YR		 1614 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
1615 vars->flow_ctrl = phy->req_flow_ctrl;
1616 else if (phy->req_line_speed != SPEED_AUTO_NEG)
1617 vars->flow_ctrl = params->req_fc_auto_adv;
1618 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1619 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
e10bc84d 1620 if (bnx2x_direct_parallel_detect_used(phy, params)) {
15ddd2d0
YR		 1621 vars->flow_ctrl = params->req_fc_auto_adv;
1622 return;
1623 }
7846e471
YR		 1624 if ((gp_status &
1625 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1626 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
1627 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1628 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1629
e10bc84d 1630 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1631 MDIO_REG_BANK_CL73_IEEEB1,
1632 MDIO_CL73_IEEEB1_AN_ADV1,
1633 &ld_pause);
e10bc84d 1634 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1635 MDIO_REG_BANK_CL73_IEEEB1,
1636 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1637 &lp_pause);
1638 pause_result = (ld_pause &
1639 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
1640 >> 8;
1641 pause_result |= (lp_pause &
1642 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
1643 >> 10;
1644 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1645 pause_result);
1646 } else {
e10bc84d 1647 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1648 MDIO_REG_BANK_COMBO_IEEE0,
1649 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1650 &ld_pause);
e10bc84d 1651 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1652 MDIO_REG_BANK_COMBO_IEEE0,
1653 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1654 &lp_pause);
1655 pause_result = (ld_pause &
ea4e040a 1656 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
7846e471 1657 pause_result |= (lp_pause &
ea4e040a 1658 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
7846e471
YR		 1659 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
1660 pause_result);
1661 }
ea4e040a 1662 bnx2x_pause_resolve(vars, pause_result);
ea4e040a
YR		 1663 }
1664 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1665}
1666
e10bc84d
YR		 1667static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
1668 struct link_params *params)
239d686d
EG		 1669{
1670 struct bnx2x *bp = params->bp;
1671 u16 rx_status, ustat_val, cl37_fsm_recieved;
1672 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1673 /* Step 1: Make sure signal is detected */
e10bc84d 1674 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1675 MDIO_REG_BANK_RX0,
1676 MDIO_RX0_RX_STATUS,
1677 &rx_status);
1678 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
1679 (MDIO_RX0_RX_STATUS_SIGDET)) {
1680 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1681 "rx_status(0x80b0) = 0x%x\n", rx_status);
e10bc84d 1682 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1683 MDIO_REG_BANK_CL73_IEEEB0,
1684 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1685 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1686 return;
1687 }
1688 /* Step 2: Check CL73 state machine */
e10bc84d 1689 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1690 MDIO_REG_BANK_CL73_USERB0,
1691 MDIO_CL73_USERB0_CL73_USTAT1,
1692 &ustat_val);
1693 if ((ustat_val &
1694 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1695 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
1696 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1697 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
1698 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
1699 "ustat_val(0x8371) = 0x%x\n", ustat_val);
1700 return;
1701 }
1702 /* Step 3: Check CL37 Message Pages received to indicate LP
1703 supports only CL37 */
e10bc84d 1704 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1705 MDIO_REG_BANK_REMOTE_PHY,
1706 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1707 &cl37_fsm_recieved);
1708 if ((cl37_fsm_recieved &
1709 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1710 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
1711 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1712 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
1713 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
1714 "misc_rx_status(0x8330) = 0x%x\n",
1715 cl37_fsm_recieved);
1716 return;
1717 }
1718 /* The combined cl37/cl73 fsm state information indicating that we are
1719 connected to a device which does not support cl73, but does support
1720 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1721 /* Disable CL73 */
e10bc84d 1722 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1723 MDIO_REG_BANK_CL73_IEEEB0,
1724 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1725 0);
1726 /* Restart CL37 autoneg */
e10bc84d 1727 bnx2x_restart_autoneg(phy, params, 0);
239d686d
EG		 1728 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1729}
7aa0711f
YR		 1730
1731static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
1732 struct link_params *params,
1733 struct link_vars *vars,
1734 u32 gp_status)
1735{
1736 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1737 vars->link_status |=
1738 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1739
1740 if (bnx2x_direct_parallel_detect_used(phy, params))
1741 vars->link_status |=
1742 LINK_STATUS_PARALLEL_DETECTION_USED;
1743}
1744
b7737c9b
YR		 1745static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
1746 struct link_params *params,
1747 struct link_vars *vars)
ea4e040a
YR		 1748{
1749 struct bnx2x *bp = params->bp;
b7737c9b 1750 u16 new_line_speed , gp_status;
ea4e040a 1751 u8 rc = 0;
c18aa15d 1752
b7737c9b
YR		 1753 /* Read gp_status */
1754 CL45_RD_OVER_CL22(bp, phy,
1755 MDIO_REG_BANK_GP_STATUS,
1756 MDIO_GP_STATUS_TOP_AN_STATUS1,
1757 &gp_status);
7aa0711f
YR		 1758 if (phy->req_line_speed == SPEED_AUTO_NEG)
1759 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
ea4e040a
YR		 1760 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1761 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1762 gp_status);
1763
1764 vars->phy_link_up = 1;
1765 vars->link_status |= LINK_STATUS_LINK_UP;
1766
1767 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1768 vars->duplex = DUPLEX_FULL;
1769 else
1770 vars->duplex = DUPLEX_HALF;
1771
7aa0711f
YR		 1772 if (SINGLE_MEDIA_DIRECT(params)) {
1773 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
1774 if (phy->req_line_speed == SPEED_AUTO_NEG)
1775 bnx2x_xgxs_an_resolve(phy, params, vars,
1776 gp_status);
1777 }
ea4e040a
YR		 1778
1779 switch (gp_status & GP_STATUS_SPEED_MASK) {
1780 case GP_STATUS_10M:
6c55c3cd 1781 new_line_speed = SPEED_10;
ea4e040a
YR		 1782 if (vars->duplex == DUPLEX_FULL)
1783 vars->link_status |= LINK_10TFD;
1784 else
1785 vars->link_status |= LINK_10THD;
1786 break;
1787
1788 case GP_STATUS_100M:
6c55c3cd 1789 new_line_speed = SPEED_100;
ea4e040a
YR		 1790 if (vars->duplex == DUPLEX_FULL)
1791 vars->link_status |= LINK_100TXFD;
1792 else
1793 vars->link_status |= LINK_100TXHD;
1794 break;
1795
1796 case GP_STATUS_1G:
1797 case GP_STATUS_1G_KX:
6c55c3cd 1798 new_line_speed = SPEED_1000;
ea4e040a
YR		 1799 if (vars->duplex == DUPLEX_FULL)
1800 vars->link_status |= LINK_1000TFD;
1801 else
1802 vars->link_status |= LINK_1000THD;
1803 break;
1804
1805 case GP_STATUS_2_5G:
6c55c3cd 1806 new_line_speed = SPEED_2500;
ea4e040a
YR		 1807 if (vars->duplex == DUPLEX_FULL)
1808 vars->link_status |= LINK_2500TFD;
1809 else
1810 vars->link_status |= LINK_2500THD;
1811 break;
1812
1813 case GP_STATUS_5G:
1814 case GP_STATUS_6G:
1815 DP(NETIF_MSG_LINK,
1816 "link speed unsupported gp_status 0x%x\n",
1817 gp_status);
1818 return -EINVAL;
ab6ad5a4 1819
ea4e040a
YR		 1820 case GP_STATUS_10G_KX4:
1821 case GP_STATUS_10G_HIG:
1822 case GP_STATUS_10G_CX4:
6c55c3cd 1823 new_line_speed = SPEED_10000;
ea4e040a
YR		 1824 vars->link_status |= LINK_10GTFD;
1825 break;
1826
1827 case GP_STATUS_12G_HIG:
6c55c3cd 1828 new_line_speed = SPEED_12000;
ea4e040a
YR		 1829 vars->link_status |= LINK_12GTFD;
1830 break;
1831
1832 case GP_STATUS_12_5G:
6c55c3cd 1833 new_line_speed = SPEED_12500;
ea4e040a
YR		 1834 vars->link_status |= LINK_12_5GTFD;
1835 break;
1836
1837 case GP_STATUS_13G:
6c55c3cd 1838 new_line_speed = SPEED_13000;
ea4e040a
YR		 1839 vars->link_status |= LINK_13GTFD;
1840 break;
1841
1842 case GP_STATUS_15G:
6c55c3cd 1843 new_line_speed = SPEED_15000;
ea4e040a
YR		 1844 vars->link_status |= LINK_15GTFD;
1845 break;
1846
1847 case GP_STATUS_16G:
6c55c3cd 1848 new_line_speed = SPEED_16000;
ea4e040a
YR		 1849 vars->link_status |= LINK_16GTFD;
1850 break;
1851
1852 default:
1853 DP(NETIF_MSG_LINK,
1854 "link speed unsupported gp_status 0x%x\n",
1855 gp_status);
ab6ad5a4 1856 return -EINVAL;
ea4e040a
YR		 1857 }
1858
6c55c3cd 1859 vars->line_speed = new_line_speed;
ea4e040a 1860
e10bc84d 1861
ea4e040a
YR		 1862 } else { /* link_down */
1863 DP(NETIF_MSG_LINK, "phy link down\n");
1864
1865 vars->phy_link_up = 0;
57963ed9 1866
ea4e040a 1867 vars->duplex = DUPLEX_FULL;
c0700f90 1868 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 1869 vars->mac_type = MAC_TYPE_NONE;
239d686d 1870
c18aa15d
YR		 1871 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
1872 SINGLE_MEDIA_DIRECT(params)) {
239d686d 1873 /* Check signal is detected */
c18aa15d 1874 bnx2x_check_fallback_to_cl37(phy, params);
239d686d 1875 }
ea4e040a
YR		 1876 }
1877
2381a55c 1878 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
ea4e040a 1879 gp_status, vars->phy_link_up, vars->line_speed);
a22f0788
YR		 1880 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
1881 vars->duplex, vars->flow_ctrl, vars->link_status);
ea4e040a
YR		 1882 return rc;
1883}
1884
ed8680a7 1885static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 1886{
1887 struct bnx2x *bp = params->bp;
e10bc84d 1888 struct bnx2x_phy *phy = &params->phy[INT_PHY];
ea4e040a
YR		 1889 u16 lp_up2;
1890 u16 tx_driver;
c2c8b03e 1891 u16 bank;
ea4e040a
YR		 1892
1893 /* read precomp */
e10bc84d 1894 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1895 MDIO_REG_BANK_OVER_1G,
1896 MDIO_OVER_1G_LP_UP2, &lp_up2);
1897
ea4e040a
YR		 1898 /* bits [10:7] at lp_up2, positioned at [15:12] */
1899 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1900 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1901 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1902
c2c8b03e
EG		 1903 if (lp_up2 == 0)
1904 return;
1905
1906 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
1907 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
e10bc84d 1908 CL45_RD_OVER_CL22(bp, phy,
c2c8b03e
EG		 1909 bank,
1910 MDIO_TX0_TX_DRIVER, &tx_driver);
1911
1912 /* replace tx_driver bits [15:12] */
1913 if (lp_up2 !=
1914 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
1915 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1916 tx_driver |= lp_up2;
e10bc84d 1917 CL45_WR_OVER_CL22(bp, phy,
c2c8b03e
EG		 1918 bank,
1919 MDIO_TX0_TX_DRIVER, tx_driver);
1920 }
ea4e040a
YR		 1921 }
1922}
1923
1924static u8 bnx2x_emac_program(struct link_params *params,
b7737c9b 1925 struct link_vars *vars)
ea4e040a
YR		 1926{
1927 struct bnx2x *bp = params->bp;
1928 u8 port = params->port;
1929 u16 mode = 0;
1930
1931 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1932 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1933 EMAC_REG_EMAC_MODE,
1934 (EMAC_MODE_25G_MODE |
1935 EMAC_MODE_PORT_MII_10M |
1936 EMAC_MODE_HALF_DUPLEX));
b7737c9b 1937 switch (vars->line_speed) {
ea4e040a
YR		 1938 case SPEED_10:
1939 mode |= EMAC_MODE_PORT_MII_10M;
1940 break;
1941
1942 case SPEED_100:
1943 mode |= EMAC_MODE_PORT_MII;
1944 break;
1945
1946 case SPEED_1000:
1947 mode |= EMAC_MODE_PORT_GMII;
1948 break;
1949
1950 case SPEED_2500:
1951 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1952 break;
1953
1954 default:
1955 /* 10G not valid for EMAC */
b7737c9b
YR		 1956 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1957 vars->line_speed);
ea4e040a
YR		 1958 return -EINVAL;
1959 }
1960
b7737c9b 1961 if (vars->duplex == DUPLEX_HALF)
ea4e040a
YR		 1962 mode |= EMAC_MODE_HALF_DUPLEX;
1963 bnx2x_bits_en(bp,
1964 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1965 mode);
1966
b7737c9b 1967 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 1968 return 0;
1969}
1970
de6eae1f
YR		 1971static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
1972 struct link_params *params)
b7737c9b 1973{
de6eae1f
YR		 1974
1975 u16 bank, i = 0;
1976 struct bnx2x *bp = params->bp;
1977
1978 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
1979 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
1980 CL45_WR_OVER_CL22(bp, phy,
1981 bank,
1982 MDIO_RX0_RX_EQ_BOOST,
1983 phy->rx_preemphasis[i]);
1984 }
1985
1986 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
1987 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
1988 CL45_WR_OVER_CL22(bp, phy,
1989 bank,
1990 MDIO_TX0_TX_DRIVER,
1991 phy->tx_preemphasis[i]);
1992 }
1993}
1994
1995static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
1996 struct link_params *params,
1997 struct link_vars *vars)
1998{
1999 struct bnx2x *bp = params->bp;
2000 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2001 (params->loopback_mode == LOOPBACK_XGXS));
2002 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2003 if (SINGLE_MEDIA_DIRECT(params) &&
2004 (params->feature_config_flags &
2005 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2006 bnx2x_set_preemphasis(phy, params);
2007
2008 /* forced speed requested? */
2009 if (vars->line_speed != SPEED_AUTO_NEG ||
2010 (SINGLE_MEDIA_DIRECT(params) &&
2011 params->loopback_mode == LOOPBACK_EXT)) {
2012 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2013
2014 /* disable autoneg */
2015 bnx2x_set_autoneg(phy, params, vars, 0);
2016
2017 /* program speed and duplex */
2018 bnx2x_program_serdes(phy, params, vars);
2019
2020 } else { /* AN_mode */
2021 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2022
2023 /* AN enabled */
2024 bnx2x_set_brcm_cl37_advertisment(phy, params);
2025
2026 /* program duplex & pause advertisement (for aneg) */
2027 bnx2x_set_ieee_aneg_advertisment(phy, params,
2028 vars->ieee_fc);
2029
2030 /* enable autoneg */
2031 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2032
2033 /* enable and restart AN */
2034 bnx2x_restart_autoneg(phy, params, enable_cl73);
2035 }
2036
2037 } else { /* SGMII mode */
2038 DP(NETIF_MSG_LINK, "SGMII\n");
2039
2040 bnx2x_initialize_sgmii_process(phy, params, vars);
2041 }
2042}
2043
2044static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2045 struct link_params *params,
2046 struct link_vars *vars)
2047{
2048 u8 rc;
2049 vars->phy_flags |= PHY_SGMII_FLAG;
b7737c9b
YR		 2050 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2051 bnx2x_set_aer_mmd(params, phy);
2052 rc = bnx2x_reset_unicore(params, phy, 1);
2053 /* reset the SerDes and wait for reset bit return low */
2054 if (rc != 0)
2055 return rc;
2056 bnx2x_set_aer_mmd(params, phy);
2057
2058 return rc;
2059}
2060
2061static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2062 struct link_params *params,
2063 struct link_vars *vars)
2064{
2065 u8 rc;
2066 vars->phy_flags = PHY_XGXS_FLAG;
2067 if ((phy->req_line_speed &&
2068 ((phy->req_line_speed == SPEED_100) ||
2069 (phy->req_line_speed == SPEED_10))) ||
2070 (!phy->req_line_speed &&
2071 (phy->speed_cap_mask >=
2072 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2073 (phy->speed_cap_mask <
2074 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2075 ))
2076 vars->phy_flags |= PHY_SGMII_FLAG;
2077 else
2078 vars->phy_flags &= ~PHY_SGMII_FLAG;
2079
2080 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2081 bnx2x_set_aer_mmd(params, phy);
2082 bnx2x_set_master_ln(params, phy);
2083
2084 rc = bnx2x_reset_unicore(params, phy, 0);
2085 /* reset the SerDes and wait for reset bit return low */
2086 if (rc != 0)
2087 return rc;
2088
2089 bnx2x_set_aer_mmd(params, phy);
e10bc84d 2090
b7737c9b
YR		 2091 /* setting the masterLn_def again after the reset */
2092 bnx2x_set_master_ln(params, phy);
2093 bnx2x_set_swap_lanes(params, phy);
2094
2095 return rc;
2096}
c18aa15d 2097
de6eae1f
YR		 2098static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2099 struct bnx2x_phy *phy)
ea4e040a 2100{
de6eae1f
YR		 2101 u16 cnt, ctrl;
2102 /* Wait for soft reset to get cleared upto 1 sec */
2103 for (cnt = 0; cnt < 1000; cnt++) {
2104 bnx2x_cl45_read(bp, phy,
2105 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2106 if (!(ctrl & (1<<15)))
2107 break;
2108 msleep(1);
2109 }
2110 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2111 return cnt;
ea4e040a
YR		 2112}
2113
de6eae1f 2114static void bnx2x_link_int_enable(struct link_params *params)
a35da8db 2115{
de6eae1f
YR		 2116 u8 port = params->port;
2117 u32 mask;
2118 struct bnx2x *bp = params->bp;
c18aa15d 2119
de6eae1f
YR		 2120 /* setting the status to report on link up
2121 for either XGXS or SerDes */
2122
2123 if (params->switch_cfg == SWITCH_CFG_10G) {
2124 mask = (NIG_MASK_XGXS0_LINK10G |
2125 NIG_MASK_XGXS0_LINK_STATUS);
2126 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2127 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2128 params->phy[INT_PHY].type !=
2129 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2130 mask |= NIG_MASK_MI_INT;
2131 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2132 }
2133
2134 } else { /* SerDes */
2135 mask = NIG_MASK_SERDES0_LINK_STATUS;
2136 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2137 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2138 params->phy[INT_PHY].type !=
2139 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2140 mask |= NIG_MASK_MI_INT;
2141 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2142 }
2143 }
2144 bnx2x_bits_en(bp,
2145 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2146 mask);
2147
2148 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2149 (params->switch_cfg == SWITCH_CFG_10G),
2150 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2151 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2152 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2153 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2154 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2155 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2156 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2157 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
a35da8db
EG		 2158}
2159
a22f0788
YR		 2160static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2161 u8 exp_mi_int)
a35da8db 2162{
a22f0788
YR		 2163 u32 latch_status = 0;
2164
2165 /**
2166 * Disable the MI INT ( external phy int ) by writing 1 to the
2167 * status register. Link down indication is high-active-signal,
2168 * so in this case we need to write the status to clear the XOR
de6eae1f
YR		 2169 */
2170 /* Read Latched signals */
2171 latch_status = REG_RD(bp,
a22f0788
YR		 2172 NIG_REG_LATCH_STATUS_0 + port*8);
2173 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
de6eae1f 2174 /* Handle only those with latched-signal=up.*/
a22f0788
YR		 2175 if (exp_mi_int)
2176 bnx2x_bits_en(bp,
2177 NIG_REG_STATUS_INTERRUPT_PORT0
2178 + port*4,
2179 NIG_STATUS_EMAC0_MI_INT);
2180 else
2181 bnx2x_bits_dis(bp,
2182 NIG_REG_STATUS_INTERRUPT_PORT0
2183 + port*4,
2184 NIG_STATUS_EMAC0_MI_INT);
2185
de6eae1f 2186 if (latch_status & 1) {
a22f0788 2187
de6eae1f
YR		 2188 /* For all latched-signal=up : Re-Arm Latch signals */
2189 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2190 (latch_status & 0xfffe) | (latch_status & 1));
2191 }
a22f0788 2192 /* For all latched-signal=up,Write original_signal to status */
a35da8db
EG		 2193}
2194
de6eae1f 2195static void bnx2x_link_int_ack(struct link_params *params,
a22f0788 2196 struct link_vars *vars, u8 is_10g)
b1607af5 2197{
e10bc84d 2198 struct bnx2x *bp = params->bp;
de6eae1f 2199 u8 port = params->port;
e10bc84d 2200
de6eae1f
YR		 2201 /* first reset all status
2202 * we assume only one line will be change at a time */
2203 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2204 (NIG_STATUS_XGXS0_LINK10G |
2205 NIG_STATUS_XGXS0_LINK_STATUS |
2206 NIG_STATUS_SERDES0_LINK_STATUS));
de6eae1f
YR		 2207 if (vars->phy_link_up) {
2208 if (is_10g) {
2209 /* Disable the 10G link interrupt
2210 * by writing 1 to the status register
2211 */
2212 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2213 bnx2x_bits_en(bp,
2214 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2215 NIG_STATUS_XGXS0_LINK10G);
b1607af5 2216
de6eae1f
YR		 2217 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2218 /* Disable the link interrupt
2219 * by writing 1 to the relevant lane
2220 * in the status register
2221 */
2222 u32 ser_lane = ((params->lane_config &
2223 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2224 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
b1607af5 2225
de6eae1f
YR		 2226 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2227 vars->line_speed);
2228 bnx2x_bits_en(bp,
2229 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2230 ((1 << ser_lane) <<
2231 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
ea4e040a 2232
de6eae1f
YR		 2233 } else { /* SerDes */
2234 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2235 /* Disable the link interrupt
2236 * by writing 1 to the status register
2237 */
2238 bnx2x_bits_en(bp,
2239 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2240 NIG_STATUS_SERDES0_LINK_STATUS);
2241 }
ea4e040a 2242
ea4e040a 2243 }
ea4e040a 2244}
ea4e040a 2245
de6eae1f
YR		 2246static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2247{
2248 u8 *str_ptr = str;
2249 u32 mask = 0xf0000000;
2250 u8 shift = 8*4;
2251 u8 digit;
a22f0788 2252 u8 remove_leading_zeros = 1;
de6eae1f
YR		 2253 if (*len < 10) {
2254 /* Need more than 10chars for this format */
2255 *str_ptr = '\0';
a22f0788 2256 (*len)--;
de6eae1f 2257 return -EINVAL;
ea4e040a 2258 }
de6eae1f 2259 while (shift > 0) {
ea4e040a 2260
de6eae1f
YR		 2261 shift -= 4;
2262 digit = ((num & mask) >> shift);
a22f0788
YR		 2263 if (digit == 0 && remove_leading_zeros) {
2264 mask = mask >> 4;
2265 continue;
2266 } else if (digit < 0xa)
de6eae1f
YR		 2267 *str_ptr = digit + '0';
2268 else
2269 *str_ptr = digit - 0xa + 'a';
a22f0788 2270 remove_leading_zeros = 0;
de6eae1f 2271 str_ptr++;
a22f0788 2272 (*len)--;
de6eae1f
YR		 2273 mask = mask >> 4;
2274 if (shift == 4*4) {
a22f0788 2275 *str_ptr = '.';
de6eae1f 2276 str_ptr++;
a22f0788
YR		 2277 (*len)--;
2278 remove_leading_zeros = 1;
ea4e040a 2279 }
ea4e040a 2280 }
de6eae1f 2281 return 0;
ea4e040a
YR		 2282}
2283
a22f0788 2284
de6eae1f 2285static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
ea4e040a 2286{
de6eae1f
YR		 2287 str[0] = '\0';
2288 (*len)--;
2289 return 0;
2290}
ea4e040a 2291
de6eae1f
YR		 2292u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
2293 u8 *version, u16 len)
2294{
2295 struct bnx2x *bp;
2296 u32 spirom_ver = 0;
2297 u8 status = 0;
2298 u8 *ver_p = version;
a22f0788 2299 u16 remain_len = len;
de6eae1f
YR		 2300 if (version == NULL || params == NULL)
2301 return -EINVAL;
2302 bp = params->bp;
ea4e040a 2303
de6eae1f
YR		 2304 /* Extract first external phy*/
2305 version[0] = '\0';
2306 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
ea4e040a 2307
a22f0788 2308 if (params->phy[EXT_PHY1].format_fw_ver) {
de6eae1f
YR		 2309 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
2310 ver_p,
a22f0788
YR		 2311 &remain_len);
2312 ver_p += (len - remain_len);
2313 }
2314 if ((params->num_phys == MAX_PHYS) &&
2315 (params->phy[EXT_PHY2].ver_addr != 0)) {
2316 spirom_ver = REG_RD(bp,
2317 params->phy[EXT_PHY2].ver_addr);
2318 if (params->phy[EXT_PHY2].format_fw_ver) {
2319 *ver_p = '/';
2320 ver_p++;
2321 remain_len--;
2322 status |= params->phy[EXT_PHY2].format_fw_ver(
2323 spirom_ver,
2324 ver_p,
2325 &remain_len);
2326 ver_p = version + (len - remain_len);
2327 }
2328 }
2329 *ver_p = '\0';
de6eae1f 2330 return status;
6bbca910 2331}
ea4e040a 2332
de6eae1f
YR		 2333static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
2334 struct link_params *params)
589abe3a 2335{
de6eae1f 2336 u8 port = params->port;
589abe3a 2337 struct bnx2x *bp = params->bp;
589abe3a 2338
de6eae1f
YR		 2339 if (phy->req_line_speed != SPEED_1000) {
2340 u32 md_devad;
589abe3a 2341
de6eae1f 2342 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
589abe3a 2343
de6eae1f
YR		 2344 /* change the uni_phy_addr in the nig */
2345 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
2346 port*0x18));
cc1cb004 2347
de6eae1f 2348 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
589abe3a 2349
de6eae1f
YR		 2350 bnx2x_cl45_write(bp, phy,
2351 5,
2352 (MDIO_REG_BANK_AER_BLOCK +
2353 (MDIO_AER_BLOCK_AER_REG & 0xf)),
2354 0x2800);
589abe3a 2355
de6eae1f
YR		 2356 bnx2x_cl45_write(bp, phy,
2357 5,
2358 (MDIO_REG_BANK_CL73_IEEEB0 +
2359 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
2360 0x6041);
2361 msleep(200);
2362 /* set aer mmd back */
2363 bnx2x_set_aer_mmd(params, phy);
589abe3a 2364
de6eae1f
YR		 2365 /* and md_devad */
2366 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
2367 md_devad);
2368
2369 } else {
2370 u16 mii_ctrl;
2371 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
2372 bnx2x_cl45_read(bp, phy, 5,
2373 (MDIO_REG_BANK_COMBO_IEEE0 +
2374 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
2375 &mii_ctrl);
2376 bnx2x_cl45_write(bp, phy, 5,
2377 (MDIO_REG_BANK_COMBO_IEEE0 +
2378 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
2379 mii_ctrl |
2380 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
2381 }
589abe3a
EG		 2382}
2383
de6eae1f
YR		 2384/*
2385 *------------------------------------------------------------------------
2386 * bnx2x_override_led_value -
2387 *
2388 * Override the led value of the requested led
2389 *
2390 *------------------------------------------------------------------------
2391 */
2392u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
2393 u32 led_idx, u32 value)
589abe3a 2394{
de6eae1f 2395 u32 reg_val;
ab6ad5a4 2396
de6eae1f
YR		 2397 /* If port 0 then use EMAC0, else use EMAC1*/
2398 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
589abe3a 2399
de6eae1f
YR		 2400 DP(NETIF_MSG_LINK,
2401 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
2402 port, led_idx, value);
589abe3a 2403
de6eae1f
YR		 2404 switch (led_idx) {
2405 case 0: /* 10MB led */
2406 /* Read the current value of the LED register in
2407 the EMAC block */
2408 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2409 /* Set the OVERRIDE bit to 1 */
2410 reg_val |= EMAC_LED_OVERRIDE;
2411 /* If value is 1, set the 10M_OVERRIDE bit,
2412 otherwise reset it.*/
2413 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
2414 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
2415 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2416 break;
2417 case 1: /*100MB led */
2418 /*Read the current value of the LED register in
2419 the EMAC block */
2420 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2421 /* Set the OVERRIDE bit to 1 */
2422 reg_val |= EMAC_LED_OVERRIDE;
2423 /* If value is 1, set the 100M_OVERRIDE bit,
2424 otherwise reset it.*/
2425 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
2426 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
2427 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2428 break;
2429 case 2: /* 1000MB led */
2430 /* Read the current value of the LED register in the
2431 EMAC block */
2432 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2433 /* Set the OVERRIDE bit to 1 */
2434 reg_val |= EMAC_LED_OVERRIDE;
2435 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
2436 reset it. */
2437 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
2438 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
2439 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2440 break;
2441 case 3: /* 2500MB led */
2442 /* Read the current value of the LED register in the
2443 EMAC block*/
2444 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2445 /* Set the OVERRIDE bit to 1 */
2446 reg_val |= EMAC_LED_OVERRIDE;
2447 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
2448 reset it.*/
2449 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
2450 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
2451 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2452 break;
2453 case 4: /*10G led */
2454 if (port == 0) {
2455 REG_WR(bp, NIG_REG_LED_10G_P0,
2456 value);
2457 } else {
2458 REG_WR(bp, NIG_REG_LED_10G_P1,
2459 value);
2460 }
2461 break;
2462 case 5: /* TRAFFIC led */
2463 /* Find if the traffic control is via BMAC or EMAC */
2464 if (port == 0)
2465 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
2466 else
2467 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
2468
2469 /* Override the traffic led in the EMAC:*/
2470 if (reg_val == 1) {
2471 /* Read the current value of the LED register in
2472 the EMAC block */
2473 reg_val = REG_RD(bp, emac_base +
2474 EMAC_REG_EMAC_LED);
2475 /* Set the TRAFFIC_OVERRIDE bit to 1 */
2476 reg_val |= EMAC_LED_OVERRIDE;
2477 /* If value is 1, set the TRAFFIC bit, otherwise
2478 reset it.*/
2479 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
2480 (reg_val & ~EMAC_LED_TRAFFIC);
2481 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2482 } else { /* Override the traffic led in the BMAC: */
2483 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
2484 + port*4, 1);
2485 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
2486 value);
2487 }
2488 break;
2489 default:
2490 DP(NETIF_MSG_LINK,
2491 "bnx2x_override_led_value() unknown led index %d "
2492 "(should be 0-5)\n", led_idx);
2493 return -EINVAL;
2494 }
2495
2496 return 0;
589abe3a
EG		 2497}
2498
de6eae1f 2499u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
4d295db0 2500{
de6eae1f
YR		 2501 u8 port = params->port;
2502 u16 hw_led_mode = params->hw_led_mode;
2503 u8 rc = 0;
2504 u32 tmp;
2505 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
589abe3a 2506 struct bnx2x *bp = params->bp;
de6eae1f
YR		 2507 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
2508 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
2509 speed, hw_led_mode);
2510 switch (mode) {
2511 case LED_MODE_OFF:
2512 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
2513 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
2514 SHARED_HW_CFG_LED_MAC1);
589abe3a 2515
de6eae1f
YR		 2516 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
2517 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
2518 break;
589abe3a 2519
de6eae1f
YR		 2520 case LED_MODE_OPER:
2521 if (SINGLE_MEDIA_DIRECT(params)) {
2522 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
2523 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
2524 } else {
2525 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
2526 hw_led_mode);
2527 }
589abe3a 2528
de6eae1f
YR		 2529 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
2530 port*4, 0);
2531 /* Set blinking rate to ~15.9Hz */
2532 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
2533 LED_BLINK_RATE_VAL);
2534 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
2535 port*4, 1);
2536 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
2537 EMAC_WR(bp, EMAC_REG_EMAC_LED,
2538 (tmp & (~EMAC_LED_OVERRIDE)));
589abe3a 2539
de6eae1f
YR		 2540 if (CHIP_IS_E1(bp) &&
2541 ((speed == SPEED_2500) ||
2542 (speed == SPEED_1000) ||
2543 (speed == SPEED_100) ||
2544 (speed == SPEED_10))) {
2545 /* On Everest 1 Ax chip versions for speeds less than
2546 10G LED scheme is different */
2547 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
2548 + port*4, 1);
2549 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
2550 port*4, 0);
2551 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
2552 port*4, 1);
2553 }
2554 break;
589abe3a 2555
de6eae1f
YR		 2556 default:
2557 rc = -EINVAL;
2558 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
2559 mode);
2560 break;
589abe3a 2561 }
de6eae1f 2562 return rc;
589abe3a 2563
4d295db0
EG		 2564}
2565
a22f0788
YR		 2566/**
2567 * This function comes to reflect the actual link state read DIRECTLY from the
2568 * HW
2569 */
2570u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
2571 u8 is_serdes)
4d295db0
EG		 2572{
2573 struct bnx2x *bp = params->bp;
de6eae1f 2574 u16 gp_status = 0, phy_index = 0;
a22f0788
YR		 2575 u8 ext_phy_link_up = 0, serdes_phy_type;
2576 struct link_vars temp_vars;
4d295db0 2577
de6eae1f
YR		 2578 CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
2579 MDIO_REG_BANK_GP_STATUS,
2580 MDIO_GP_STATUS_TOP_AN_STATUS1,
2581 &gp_status);
2582 /* link is up only if both local phy and external phy are up */
a22f0788
YR		 2583 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
2584 return -ESRCH;
2585
2586 switch (params->num_phys) {
2587 case 1:
2588 /* No external PHY */
2589 return 0;
2590 case 2:
2591 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
2592 &params->phy[EXT_PHY1],
2593 params, &temp_vars);
2594 break;
2595 case 3: /* Dual Media */
de6eae1f
YR		 2596 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
2597 phy_index++) {
a22f0788
YR		 2598 serdes_phy_type = ((params->phy[phy_index].media_type ==
2599 ETH_PHY_SFP_FIBER) ||
2600 (params->phy[phy_index].media_type ==
2601 ETH_PHY_XFP_FIBER));
2602
2603 if (is_serdes != serdes_phy_type)
2604 continue;
2605 if (params->phy[phy_index].read_status) {
2606 ext_phy_link_up |=
de6eae1f
YR		 2607 params->phy[phy_index].read_status(
2608 &params->phy[phy_index],
2609 params, &temp_vars);
a22f0788 2610 }
de6eae1f 2611 }
a22f0788 2612 break;
4d295db0 2613 }
a22f0788
YR		 2614 if (ext_phy_link_up)
2615 return 0;
de6eae1f
YR		 2616 return -ESRCH;
2617}
4d295db0 2618
de6eae1f
YR		 2619static u8 bnx2x_link_initialize(struct link_params *params,
2620 struct link_vars *vars)
2621{
2622 u8 rc = 0;
2623 u8 phy_index, non_ext_phy;
2624 struct bnx2x *bp = params->bp;
2625 /**
2626 * In case of external phy existence, the line speed would be the
2627 * line speed linked up by the external phy. In case it is direct
2628 * only, then the line_speed during initialization will be
2629 * equal to the req_line_speed
2630 */
2631 vars->line_speed = params->phy[INT_PHY].req_line_speed;
4d295db0 2632
de6eae1f
YR		 2633 /**
2634 * Initialize the internal phy in case this is a direct board
2635 * (no external phys), or this board has external phy which requires
2636 * to first.
2637 */
4d295db0 2638
de6eae1f
YR		 2639 if (params->phy[INT_PHY].config_init)
2640 params->phy[INT_PHY].config_init(
2641 &params->phy[INT_PHY],
2642 params, vars);
4d295db0 2643
de6eae1f
YR		 2644 /* init ext phy and enable link state int */
2645 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
2646 (params->loopback_mode == LOOPBACK_XGXS));
4d295db0 2647
de6eae1f
YR		 2648 if (non_ext_phy ||
2649 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
2650 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
2651 struct bnx2x_phy *phy = &params->phy[INT_PHY];
2652 if (vars->line_speed == SPEED_AUTO_NEG)
2653 bnx2x_set_parallel_detection(phy, params);
2654 bnx2x_init_internal_phy(phy, params, vars);
4d295db0
EG		 2655 }
2656
de6eae1f
YR		 2657 /* Init external phy*/
2658 if (!non_ext_phy)
2659 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
2660 phy_index++) {
a22f0788
YR		 2661 /**
2662 * No need to initialize second phy in case of first
2663 * phy only selection. In case of second phy, we do
2664 * need to initialize the first phy, since they are
2665 * connected.
2666 **/
2667 if (phy_index == EXT_PHY2 &&
2668 (bnx2x_phy_selection(params) ==
2669 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
2670 DP(NETIF_MSG_LINK, "Not initializing"
2671 "second phy\n");
2672 continue;
2673 }
de6eae1f
YR		 2674 params->phy[phy_index].config_init(
2675 &params->phy[phy_index],
2676 params, vars);
2677 }
4d295db0 2678
de6eae1f
YR		 2679 /* Reset the interrupt indication after phy was initialized */
2680 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
2681 params->port*4,
2682 (NIG_STATUS_XGXS0_LINK10G |
2683 NIG_STATUS_XGXS0_LINK_STATUS |
2684 NIG_STATUS_SERDES0_LINK_STATUS |
2685 NIG_MASK_MI_INT));
2686 return rc;
2687}
4d295db0 2688
de6eae1f
YR		 2689static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
2690 struct link_params *params)
2691{
2692 /* reset the SerDes/XGXS */
2693 REG_WR(params->bp, GRCBASE_MISC +
2694 MISC_REGISTERS_RESET_REG_3_CLEAR,
2695 (0x1ff << (params->port*16)));
589abe3a
EG		 2696}
2697
de6eae1f
YR		 2698static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
2699 struct link_params *params)
4d295db0 2700{
de6eae1f
YR		 2701 struct bnx2x *bp = params->bp;
2702 u8 gpio_port;
2703 /* HW reset */
2704 gpio_port = params->port;
2705 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2706 MISC_REGISTERS_GPIO_OUTPUT_LOW,
2707 gpio_port);
2708 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2709 MISC_REGISTERS_GPIO_OUTPUT_LOW,
2710 gpio_port);
2711 DP(NETIF_MSG_LINK, "reset external PHY\n");
4d295db0 2712}
589abe3a 2713
de6eae1f
YR		 2714static u8 bnx2x_update_link_down(struct link_params *params,
2715 struct link_vars *vars)
589abe3a
EG		 2716{
2717 struct bnx2x *bp = params->bp;
de6eae1f 2718 u8 port = params->port;
589abe3a 2719
de6eae1f
YR		 2720 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
2721 bnx2x_set_led(params, LED_MODE_OFF, 0);
589abe3a 2722
de6eae1f
YR		 2723 /* indicate no mac active */
2724 vars->mac_type = MAC_TYPE_NONE;
ab6ad5a4 2725
de6eae1f
YR		 2726 /* update shared memory */
2727 vars->link_status = 0;
2728 vars->line_speed = 0;
2729 bnx2x_update_mng(params, vars->link_status);
589abe3a 2730
de6eae1f
YR		 2731 /* activate nig drain */
2732 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4d295db0 2733
de6eae1f
YR		 2734 /* disable emac */
2735 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
2736
2737 msleep(10);
2738
2739 /* reset BigMac */
2740 bnx2x_bmac_rx_disable(bp, params->port);
2741 REG_WR(bp, GRCBASE_MISC +
2742 MISC_REGISTERS_RESET_REG_2_CLEAR,
2743 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
589abe3a
EG		 2744 return 0;
2745}
de6eae1f
YR		 2746
2747static u8 bnx2x_update_link_up(struct link_params *params,
2748 struct link_vars *vars,
2749 u8 link_10g)
589abe3a
EG		 2750{
2751 struct bnx2x *bp = params->bp;
de6eae1f
YR		 2752 u8 port = params->port;
2753 u8 rc = 0;
4d295db0 2754
de6eae1f
YR		 2755 vars->link_status |= LINK_STATUS_LINK_UP;
2756 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
2757 vars->link_status |=
2758 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
589abe3a 2759
de6eae1f
YR		 2760 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
2761 vars->link_status |=
2762 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
2763 if (link_10g) {
2764 bnx2x_bmac_enable(params, vars, 0);
2765 bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000);
2766 } else {
2767 rc = bnx2x_emac_program(params, vars);
cc1cb004 2768
de6eae1f 2769 bnx2x_emac_enable(params, vars, 0);
cc1cb004 2770
de6eae1f
YR		 2771 /* AN complete? */
2772 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
2773 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
2774 SINGLE_MEDIA_DIRECT(params))
2775 bnx2x_set_gmii_tx_driver(params);
2776 }
cc1cb004 2777
de6eae1f
YR		 2778 /* PBF - link up */
2779 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
2780 vars->line_speed);
589abe3a 2781
de6eae1f
YR		 2782 /* disable drain */
2783 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
589abe3a 2784
de6eae1f
YR		 2785 /* update shared memory */
2786 bnx2x_update_mng(params, vars->link_status);
2787 msleep(20);
2788 return rc;
589abe3a 2789}
de6eae1f
YR		 2790/**
2791 * The bnx2x_link_update function should be called upon link
2792 * interrupt.
2793 * Link is considered up as follows:
2794 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
2795 * to be up
2796 * - SINGLE_MEDIA - The link between the 577xx and the external
2797 * phy (XGXS) need to up as well as the external link of the
2798 * phy (PHY_EXT1)
2799 * - DUAL_MEDIA - The link between the 577xx and the first
2800 * external phy needs to be up, and at least one of the 2
2801 * external phy link must be up.
2802 */
2803u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4d295db0 2804{
de6eae1f
YR		 2805 struct bnx2x *bp = params->bp;
2806 struct link_vars phy_vars[MAX_PHYS];
2807 u8 port = params->port;
2808 u8 link_10g, phy_index;
2809 u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
2810 u8 is_mi_int = 0;
2811 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
2812 u8 active_external_phy = INT_PHY;
2813 vars->link_status = 0;
2814 for (phy_index = INT_PHY; phy_index < params->num_phys;
2815 phy_index++) {
2816 phy_vars[phy_index].flow_ctrl = 0;
2817 phy_vars[phy_index].link_status = 0;
2818 phy_vars[phy_index].line_speed = 0;
2819 phy_vars[phy_index].duplex = DUPLEX_FULL;
2820 phy_vars[phy_index].phy_link_up = 0;
2821 phy_vars[phy_index].link_up = 0;
2822 }
4d295db0 2823
de6eae1f
YR		 2824 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
2825 port, (vars->phy_flags & PHY_XGXS_FLAG),
2826 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4d295db0 2827
de6eae1f
YR		 2828 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
2829 port*0x18) > 0);
2830 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
2831 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2832 is_mi_int,
2833 REG_RD(bp,
2834 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4d295db0 2835
de6eae1f
YR		 2836 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2837 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2838 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4d295db0 2839
de6eae1f
YR		 2840 /* disable emac */
2841 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4d295db0 2842
de6eae1f
YR		 2843 /**
2844 * Step 1:
2845 * Check external link change only for external phys, and apply
2846 * priority selection between them in case the link on both phys
2847 * is up. Note that the instead of the common vars, a temporary
2848 * vars argument is used since each phy may have different link/
2849 * speed/duplex result
2850 */
2851 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
2852 phy_index++) {
2853 struct bnx2x_phy *phy = &params->phy[phy_index];
2854 if (!phy->read_status)
2855 continue;
2856 /* Read link status and params of this ext phy */
2857 cur_link_up = phy->read_status(phy, params,
2858 &phy_vars[phy_index]);
2859 if (cur_link_up) {
2860 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
2861 phy_index);
2862 } else {
2863 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
2864 phy_index);
2865 continue;
2866 }
e10bc84d 2867
de6eae1f
YR		 2868 if (!ext_phy_link_up) {
2869 ext_phy_link_up = 1;
2870 active_external_phy = phy_index;
a22f0788
YR		 2871 } else {
2872 switch (bnx2x_phy_selection(params)) {
2873 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
2874 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
2875 /**
2876 * In this option, the first PHY makes sure to pass the
2877 * traffic through itself only.
2878 * Its not clear how to reset the link on the second phy
2879 **/
2880 active_external_phy = EXT_PHY1;
2881 break;
2882 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
2883 /**
2884 * In this option, the first PHY makes sure to pass the
2885 * traffic through the second PHY.
2886 **/
2887 active_external_phy = EXT_PHY2;
2888 break;
2889 default:
2890 /**
2891 * Link indication on both PHYs with the following cases
2892 * is invalid:
2893 * - FIRST_PHY means that second phy wasn't initialized,
2894 * hence its link is expected to be down
2895 * - SECOND_PHY means that first phy should not be able
2896 * to link up by itself (using configuration)
2897 * - DEFAULT should be overriden during initialiazation
2898 **/
2899 DP(NETIF_MSG_LINK, "Invalid link indication"
2900 "mpc=0x%x. DISABLING LINK !!!\n",
2901 params->multi_phy_config);
2902 ext_phy_link_up = 0;
2903 break;
2904 }
589abe3a 2905 }
589abe3a 2906 }
de6eae1f
YR		 2907 prev_line_speed = vars->line_speed;
2908 /**
2909 * Step 2:
2910 * Read the status of the internal phy. In case of
2911 * DIRECT_SINGLE_MEDIA board, this link is the external link,
2912 * otherwise this is the link between the 577xx and the first
2913 * external phy
4d295db0 2914 */
de6eae1f
YR		 2915 if (params->phy[INT_PHY].read_status)
2916 params->phy[INT_PHY].read_status(
2917 &params->phy[INT_PHY],
2918 params, vars);
2919 /**
2920 * The INT_PHY flow control reside in the vars. This include the
2921 * case where the speed or flow control are not set to AUTO.
2922 * Otherwise, the active external phy flow control result is set
2923 * to the vars. The ext_phy_line_speed is needed to check if the
2924 * speed is different between the internal phy and external phy.
2925 * This case may be result of intermediate link speed change.
4d295db0 2926 */
de6eae1f
YR		 2927 if (active_external_phy > INT_PHY) {
2928 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
2929 /**
2930 * Link speed is taken from the XGXS. AN and FC result from
2931 * the external phy.
4d295db0 2932 */
de6eae1f 2933 vars->link_status |= phy_vars[active_external_phy].link_status;
a22f0788
YR		 2934
2935 /**
2936 * if active_external_phy is first PHY and link is up - disable
2937 * disable TX on second external PHY
2938 */
2939 if (active_external_phy == EXT_PHY1) {
2940 if (params->phy[EXT_PHY2].phy_specific_func) {
2941 DP(NETIF_MSG_LINK, "Disabling TX on"
2942 " EXT_PHY2\n");
2943 params->phy[EXT_PHY2].phy_specific_func(
2944 &params->phy[EXT_PHY2],
2945 params, DISABLE_TX);
2946 }
2947 }
2948
de6eae1f
YR		 2949 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
2950 vars->duplex = phy_vars[active_external_phy].duplex;
2951 if (params->phy[active_external_phy].supported &
2952 SUPPORTED_FIBRE)
2953 vars->link_status |= LINK_STATUS_SERDES_LINK;
2954 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
2955 active_external_phy);
2956 }
a22f0788
YR		 2957
2958 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
2959 phy_index++) {
2960 if (params->phy[phy_index].flags &
2961 FLAGS_REARM_LATCH_SIGNAL) {
2962 bnx2x_rearm_latch_signal(bp, port,
2963 phy_index ==
2964 active_external_phy);
2965 break;
2966 }
2967 }
de6eae1f
YR		 2968 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
2969 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
2970 vars->link_status, ext_phy_line_speed);
2971 /**
2972 * Upon link speed change set the NIG into drain mode. Comes to
2973 * deals with possible FIFO glitch due to clk change when speed
2974 * is decreased without link down indicator
2975 */
4d295db0 2976
de6eae1f
YR		 2977 if (vars->phy_link_up) {
2978 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
2979 (ext_phy_line_speed != vars->line_speed)) {
2980 DP(NETIF_MSG_LINK, "Internal link speed %d is"
2981 " different than the external"
2982 " link speed %d\n", vars->line_speed,
2983 ext_phy_line_speed);
2984 vars->phy_link_up = 0;
2985 } else if (prev_line_speed != vars->line_speed) {
2986 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
2987 + params->port*4, 0);
2988 msleep(1);
2989 }
2990 }
e10bc84d 2991
de6eae1f
YR		 2992 /* anything 10 and over uses the bmac */
2993 link_10g = ((vars->line_speed == SPEED_10000) ||
2994 (vars->line_speed == SPEED_12000) ||
2995 (vars->line_speed == SPEED_12500) ||
2996 (vars->line_speed == SPEED_13000) ||
2997 (vars->line_speed == SPEED_15000) ||
2998 (vars->line_speed == SPEED_16000));
589abe3a 2999
a22f0788 3000 bnx2x_link_int_ack(params, vars, link_10g);
589abe3a 3001
de6eae1f
YR		 3002 /**
3003 * In case external phy link is up, and internal link is down
3004 * (not initialized yet probably after link initialization, it
3005 * needs to be initialized.
3006 * Note that after link down-up as result of cable plug, the xgxs
3007 * link would probably become up again without the need
3008 * initialize it
3009 */
3010 if (!(SINGLE_MEDIA_DIRECT(params))) {
3011 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3012 " init_preceding = %d\n", ext_phy_link_up,
3013 vars->phy_link_up,
3014 params->phy[EXT_PHY1].flags &
3015 FLAGS_INIT_XGXS_FIRST);
3016 if (!(params->phy[EXT_PHY1].flags &
3017 FLAGS_INIT_XGXS_FIRST)
3018 && ext_phy_link_up && !vars->phy_link_up) {
3019 vars->line_speed = ext_phy_line_speed;
3020 if (vars->line_speed < SPEED_1000)
3021 vars->phy_flags |= PHY_SGMII_FLAG;
3022 else
3023 vars->phy_flags &= ~PHY_SGMII_FLAG;
3024 bnx2x_init_internal_phy(&params->phy[INT_PHY],
3025 params,
3026 vars);
4d295db0 3027 }
589abe3a 3028 }
de6eae1f
YR		 3029 /**
3030 * Link is up only if both local phy and external phy (in case of
3031 * non-direct board) are up
4d295db0 3032 */
de6eae1f
YR		 3033 vars->link_up = (vars->phy_link_up &&
3034 (ext_phy_link_up ||
3035 SINGLE_MEDIA_DIRECT(params)));
3036
3037 if (vars->link_up)
3038 rc = bnx2x_update_link_up(params, vars, link_10g);
4d295db0 3039 else
de6eae1f 3040 rc = bnx2x_update_link_down(params, vars);
589abe3a 3041
4d295db0 3042 return rc;
589abe3a
EG		 3043}
3044
589abe3a 3045
de6eae1f
YR		 3046/*****************************************************************************/
3047/* External Phy section */
3048/*****************************************************************************/
3049void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3050{
3051 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3052 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3053 msleep(1);
3054 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3055 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3056}
589abe3a 3057
de6eae1f
YR		 3058static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3059 u32 spirom_ver, u32 ver_addr)
3060{
3061 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3062 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
4d295db0 3063
de6eae1f
YR		 3064 if (ver_addr)
3065 REG_WR(bp, ver_addr, spirom_ver);
589abe3a
EG		 3066}
3067
de6eae1f
YR		 3068static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3069 struct bnx2x_phy *phy,
3070 u8 port)
6bbca910 3071{
de6eae1f
YR		 3072 u16 fw_ver1, fw_ver2;
3073
3074 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3075 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3076 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3077 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3078 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3079 phy->ver_addr);
ea4e040a 3080}
ab6ad5a4 3081
de6eae1f
YR		 3082static void bnx2x_ext_phy_set_pause(struct link_params *params,
3083 struct bnx2x_phy *phy,
3084 struct link_vars *vars)
ea4e040a 3085{
ea4e040a 3086 u16 val;
de6eae1f
YR		 3087 struct bnx2x *bp = params->bp;
3088 /* read modify write pause advertizing */
3089 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
ea4e040a 3090
de6eae1f 3091 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
ea4e040a 3092
de6eae1f
YR		 3093 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3094 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3095 if ((vars->ieee_fc &
3096 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3097 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3098 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3099 }
3100 if ((vars->ieee_fc &
3101 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3102 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3103 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3104 }
3105 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3106 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3107}
3108
3109static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3110 struct link_params *params,
3111 struct link_vars *vars)
3112{
3113 struct bnx2x *bp = params->bp;
3114 u16 ld_pause; /* local */
3115 u16 lp_pause; /* link partner */
3116 u16 pause_result;
3117 u8 ret = 0;
3118 /* read twice */
3119
3120 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3121
3122 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3123 vars->flow_ctrl = phy->req_flow_ctrl;
3124 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3125 vars->flow_ctrl = params->req_fc_auto_adv;
3126 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3127 ret = 1;
3128 bnx2x_cl45_read(bp, phy,
3129 MDIO_AN_DEVAD,
3130 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3131 bnx2x_cl45_read(bp, phy,
3132 MDIO_AN_DEVAD,
3133 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3134 pause_result = (ld_pause &
3135 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3136 pause_result |= (lp_pause &
3137 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3138 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3139 pause_result);
3140 bnx2x_pause_resolve(vars, pause_result);
3141 }
3142 return ret;
3143}
3144
3145static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3146 struct bnx2x_phy *phy,
3147 struct link_vars *vars)
3148{
3149 u16 val;
3150 bnx2x_cl45_read(bp, phy,
3151 MDIO_AN_DEVAD,
3152 MDIO_AN_REG_STATUS, &val);
3153 bnx2x_cl45_read(bp, phy,
3154 MDIO_AN_DEVAD,
3155 MDIO_AN_REG_STATUS, &val);
3156 if (val & (1<<5))
3157 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3158 if ((val & (1<<0)) == 0)
3159 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3160}
3161
3162/******************************************************************/
3163/* common BCM8073/BCM8727 PHY SECTION */
3164/******************************************************************/
3165static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3166 struct link_params *params,
3167 struct link_vars *vars)
3168{
3169 struct bnx2x *bp = params->bp;
3170 if (phy->req_line_speed == SPEED_10 ||
3171 phy->req_line_speed == SPEED_100) {
3172 vars->flow_ctrl = phy->req_flow_ctrl;
3173 return;
3174 }
3175
3176 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3177 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3178 u16 pause_result;
3179 u16 ld_pause; /* local */
3180 u16 lp_pause; /* link partner */
3181 bnx2x_cl45_read(bp, phy,
3182 MDIO_AN_DEVAD,
3183 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3184
3185 bnx2x_cl45_read(bp, phy,
3186 MDIO_AN_DEVAD,
3187 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3188 pause_result = (ld_pause &
3189 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3190 pause_result |= (lp_pause &
3191 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3192
3193 bnx2x_pause_resolve(vars, pause_result);
3194 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3195 pause_result);
3196 }
3197}
3198
3199static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3200 struct bnx2x_phy *phy,
3201 u8 port)
3202{
3203 /* Boot port from external ROM */
3204 /* EDC grst */
3205 bnx2x_cl45_write(bp, phy,
3206 MDIO_PMA_DEVAD,
3207 MDIO_PMA_REG_GEN_CTRL,
3208 0x0001);
3209
3210 /* ucode reboot and rst */
3211 bnx2x_cl45_write(bp, phy,
3212 MDIO_PMA_DEVAD,
3213 MDIO_PMA_REG_GEN_CTRL,
3214 0x008c);
3215
3216 bnx2x_cl45_write(bp, phy,
3217 MDIO_PMA_DEVAD,
3218 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3219
3220 /* Reset internal microprocessor */
3221 bnx2x_cl45_write(bp, phy,
3222 MDIO_PMA_DEVAD,
3223 MDIO_PMA_REG_GEN_CTRL,
3224 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3225
3226 /* Release srst bit */
3227 bnx2x_cl45_write(bp, phy,
3228 MDIO_PMA_DEVAD,
3229 MDIO_PMA_REG_GEN_CTRL,
3230 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3231
3232 /* wait for 120ms for code download via SPI port */
3233 msleep(120);
3234
3235 /* Clear ser_boot_ctl bit */
3236 bnx2x_cl45_write(bp, phy,
3237 MDIO_PMA_DEVAD,
3238 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3239 bnx2x_save_bcm_spirom_ver(bp, phy, port);
3240}
3241
3242static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3243 struct bnx2x_phy *phy)
3244{
3245 u16 val;
3246 bnx2x_cl45_read(bp, phy,
3247 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
3248
3249 if (val == 0) {
3250 /* Mustn't set low power mode in 8073 A0 */
3251 return;
3252 }
3253
3254 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3255 bnx2x_cl45_read(bp, phy,
62b29a5d 3256 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
ea4e040a 3257 val &= ~(1<<13);
e10bc84d 3258 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 3259 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3260
3261 /* PLL controls */
62b29a5d
YR		 3262 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
3263 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
3264 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
3265 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
3266 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
ea4e040a
YR		 3267
3268 /* Tx Controls */
62b29a5d
YR		 3269 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3270 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
3271 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
ea4e040a
YR		 3272
3273 /* Rx Controls */
62b29a5d
YR		 3274 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3275 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
3276 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
ea4e040a
YR		 3277
3278 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
62b29a5d 3279 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
ea4e040a 3280 val |= (1<<13);
62b29a5d 3281 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
ea4e040a 3282}
6bbca910 3283
de6eae1f
YR		 3284/******************************************************************/
3285/* BCM8073 PHY SECTION */
3286/******************************************************************/
3287static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3288{
3289 /* This is only required for 8073A1, version 102 only */
3290 u16 val;
3291
3292 /* Read 8073 HW revision*/
3293 bnx2x_cl45_read(bp, phy,
3294 MDIO_PMA_DEVAD,
3295 MDIO_PMA_REG_8073_CHIP_REV, &val);
3296
3297 if (val != 1) {
3298 /* No need to workaround in 8073 A1 */
3299 return 0;
3300 }
3301
3302 bnx2x_cl45_read(bp, phy,
3303 MDIO_PMA_DEVAD,
3304 MDIO_PMA_REG_ROM_VER2, &val);
3305
3306 /* SNR should be applied only for version 0x102 */
3307 if (val != 0x102)
3308 return 0;
3309
3310 return 1;
3311}
3312
3313static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3314{
3315 u16 val, cnt, cnt1 ;
3316
3317 bnx2x_cl45_read(bp, phy,
3318 MDIO_PMA_DEVAD,
3319 MDIO_PMA_REG_8073_CHIP_REV, &val);
3320
3321 if (val > 0) {
3322 /* No need to workaround in 8073 A1 */
3323 return 0;
3324 }
3325 /* XAUI workaround in 8073 A0: */
3326
3327 /* After loading the boot ROM and restarting Autoneg,
3328 poll Dev1, Reg $C820: */
3329
3330 for (cnt = 0; cnt < 1000; cnt++) {
3331 bnx2x_cl45_read(bp, phy,
3332 MDIO_PMA_DEVAD,
3333 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3334 &val);
3335 /* If bit [14] = 0 or bit [13] = 0, continue on with
3336 system initialization (XAUI work-around not required,
3337 as these bits indicate 2.5G or 1G link up). */
3338 if (!(val & (1<<14)) || !(val & (1<<13))) {
3339 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
3340 return 0;
3341 } else if (!(val & (1<<15))) {
3342 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
3343 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
3344 it's MSB (bit 15) goes to 1 (indicating that the
3345 XAUI workaround has completed),
3346 then continue on with system initialization.*/
3347 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
3348 bnx2x_cl45_read(bp, phy,
3349 MDIO_PMA_DEVAD,
3350 MDIO_PMA_REG_8073_XAUI_WA, &val);
3351 if (val & (1<<15)) {
3352 DP(NETIF_MSG_LINK,
3353 "XAUI workaround has completed\n");
3354 return 0;
3355 }
3356 msleep(3);
3357 }
3358 break;
3359 }
3360 msleep(3);
3361 }
3362 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
3363 return -EINVAL;
3364}
3365
3366static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
3367{
3368 /* Force KR or KX */
3369 bnx2x_cl45_write(bp, phy,
3370 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
3371 bnx2x_cl45_write(bp, phy,
3372 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
3373 bnx2x_cl45_write(bp, phy,
3374 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
3375 bnx2x_cl45_write(bp, phy,
3376 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
3377}
3378
6bbca910 3379static void bnx2x_8073_set_pause_cl37(struct link_params *params,
e10bc84d
YR		 3380 struct bnx2x_phy *phy,
3381 struct link_vars *vars)
ea4e040a 3382{
6bbca910 3383 u16 cl37_val;
e10bc84d
YR		 3384 struct bnx2x *bp = params->bp;
3385 bnx2x_cl45_read(bp, phy,
62b29a5d 3386 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6bbca910
YR		 3387
3388 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3389 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
e10bc84d 3390 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6bbca910
YR		 3391 if ((vars->ieee_fc &
3392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3393 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3394 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3395 }
3396 if ((vars->ieee_fc &
3397 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3399 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3400 }
3401 if ((vars->ieee_fc &
3402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3403 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3404 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3405 }
3406 DP(NETIF_MSG_LINK,
3407 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3408
e10bc84d 3409 bnx2x_cl45_write(bp, phy,
62b29a5d 3410 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6bbca910 3411 msleep(500);
ea4e040a
YR		 3412}
3413
de6eae1f
YR		 3414static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
3415 struct link_params *params,
3416 struct link_vars *vars)
ea4e040a 3417{
e10bc84d 3418 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3419 u16 val = 0, tmp1;
3420 u8 gpio_port;
3421 DP(NETIF_MSG_LINK, "Init 8073\n");
e10bc84d 3422
de6eae1f
YR		 3423 gpio_port = params->port;
3424 /* Restore normal power mode*/
3425 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3426 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
e10bc84d 3427
de6eae1f
YR		 3428 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3429 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
ea4e040a 3430
de6eae1f
YR		 3431 /* enable LASI */
3432 bnx2x_cl45_write(bp, phy,
3433 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
3434 bnx2x_cl45_write(bp, phy,
3435 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
c2c8b03e 3436
de6eae1f 3437 bnx2x_8073_set_pause_cl37(params, phy, vars);
57963ed9 3438
de6eae1f 3439 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
e10bc84d 3440
e10bc84d 3441 bnx2x_cl45_read(bp, phy,
de6eae1f 3442 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
2f904460 3443
de6eae1f
YR		 3444 bnx2x_cl45_read(bp, phy,
3445 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
2f904460 3446
de6eae1f 3447 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
a1e4be39 3448
de6eae1f
YR		 3449 /* Enable CL37 BAM */
3450 bnx2x_cl45_read(bp, phy,
3451 MDIO_AN_DEVAD,
3452 MDIO_AN_REG_8073_BAM, &val);
e10bc84d 3453 bnx2x_cl45_write(bp, phy,
a1e4be39 3454 MDIO_AN_DEVAD,
de6eae1f 3455 MDIO_AN_REG_8073_BAM, val | 1);
57963ed9 3456
de6eae1f
YR		 3457 if (params->loopback_mode == LOOPBACK_EXT) {
3458 bnx2x_807x_force_10G(bp, phy);
3459 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
3460 return 0;
3461 } else {
3462 bnx2x_cl45_write(bp, phy,
3463 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
3464 }
3465 if (phy->req_line_speed != SPEED_AUTO_NEG) {
3466 if (phy->req_line_speed == SPEED_10000) {
3467 val = (1<<7);
3468 } else if (phy->req_line_speed == SPEED_2500) {
3469 val = (1<<5);
3470 /* Note that 2.5G works only
3471 when used with 1G advertisment */
3472 } else
3473 val = (1<<5);
3474 } else {
3475 val = 0;
3476 if (phy->speed_cap_mask &
3477 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3478 val |= (1<<7);
57963ed9 3479
de6eae1f
YR		 3480 /* Note that 2.5G works only when
3481 used with 1G advertisment */
3482 if (phy->speed_cap_mask &
3483 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3484 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
3485 val |= (1<<5);
3486 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
3487 }
57963ed9 3488
de6eae1f
YR		 3489 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
3490 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
57963ed9 3491
de6eae1f
YR		 3492 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
3493 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
3494 (phy->req_line_speed == SPEED_2500)) {
3495 u16 phy_ver;
3496 /* Allow 2.5G for A1 and above */
3497 bnx2x_cl45_read(bp, phy,
3498 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
3499 &phy_ver);
3500 DP(NETIF_MSG_LINK, "Add 2.5G\n");
3501 if (phy_ver > 0)
3502 tmp1 |= 1;
3503 else
3504 tmp1 &= 0xfffe;
3505 } else {
3506 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
3507 tmp1 &= 0xfffe;
3508 }
57963ed9 3509
de6eae1f
YR		 3510 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
3511 /* Add support for CL37 (passive mode) II */
57963ed9 3512
de6eae1f
YR		 3513 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
3514 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
3515 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
3516 0x20 : 0x40)));
57963ed9 3517
de6eae1f
YR		 3518 /* Add support for CL37 (passive mode) III */
3519 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
57963ed9 3520
de6eae1f
YR		 3521 /* The SNR will improve about 2db by changing
3522 BW and FEE main tap. Rest commands are executed
3523 after link is up*/
3524 if (bnx2x_8073_is_snr_needed(bp, phy))
3525 bnx2x_cl45_write(bp, phy,
3526 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
3527 0xFB0C);
57963ed9 3528
de6eae1f
YR		 3529 /* Enable FEC (Forware Error Correction) Request in the AN */
3530 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
3531 tmp1 |= (1<<15);
3532 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
57963ed9 3533
de6eae1f 3534 bnx2x_ext_phy_set_pause(params, phy, vars);
57963ed9 3535
de6eae1f
YR		 3536 /* Restart autoneg */
3537 msleep(500);
3538 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3539 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
3540 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
3541 return 0;
b7737c9b 3542}
ea4e040a 3543
de6eae1f 3544static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 3545 struct link_params *params,
3546 struct link_vars *vars)
3547{
3548 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3549 u8 link_up = 0;
3550 u16 val1, val2;
3551 u16 link_status = 0;
3552 u16 an1000_status = 0;
a35da8db 3553
de6eae1f
YR		 3554 bnx2x_cl45_read(bp, phy,
3555 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
b7737c9b 3556
de6eae1f 3557 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
ea4e040a 3558
de6eae1f
YR		 3559 /* clear the interrupt LASI status register */
3560 bnx2x_cl45_read(bp, phy,
3561 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
3562 bnx2x_cl45_read(bp, phy,
3563 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
3564 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
3565 /* Clear MSG-OUT */
3566 bnx2x_cl45_read(bp, phy,
3567 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
3568
3569 /* Check the LASI */
3570 bnx2x_cl45_read(bp, phy,
3571 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
3572
3573 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
3574
3575 /* Check the link status */
3576 bnx2x_cl45_read(bp, phy,
3577 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
3578 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
3579
3580 bnx2x_cl45_read(bp, phy,
3581 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
3582 bnx2x_cl45_read(bp, phy,
3583 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
3584 link_up = ((val1 & 4) == 4);
3585 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
3586
3587 if (link_up &&
3588 ((phy->req_line_speed != SPEED_10000))) {
3589 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
3590 return 0;
62b29a5d 3591 }
de6eae1f
YR		 3592 bnx2x_cl45_read(bp, phy,
3593 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
3594 bnx2x_cl45_read(bp, phy,
3595 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
62b29a5d 3596
de6eae1f
YR		 3597 /* Check the link status on 1.1.2 */
3598 bnx2x_cl45_read(bp, phy,
3599 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
3600 bnx2x_cl45_read(bp, phy,
3601 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
3602 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
3603 "an_link_status=0x%x\n", val2, val1, an1000_status);
62b29a5d 3604
de6eae1f
YR		 3605 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
3606 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
3607 /* The SNR will improve about 2dbby
3608 changing the BW and FEE main tap.*/
3609 /* The 1st write to change FFE main
3610 tap is set before restart AN */
3611 /* Change PLL Bandwidth in EDC
3612 register */
62b29a5d 3613 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3614 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
3615 0x26BC);
62b29a5d 3616
de6eae1f 3617 /* Change CDR Bandwidth in EDC register */
62b29a5d 3618 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3619 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
3620 0x0333);
3621 }
3622 bnx2x_cl45_read(bp, phy,
3623 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3624 &link_status);
62b29a5d 3625
de6eae1f
YR		 3626 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
3627 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
3628 link_up = 1;
3629 vars->line_speed = SPEED_10000;
3630 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
3631 params->port);
3632 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
3633 link_up = 1;
3634 vars->line_speed = SPEED_2500;
3635 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
3636 params->port);
3637 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
3638 link_up = 1;
3639 vars->line_speed = SPEED_1000;
3640 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
3641 params->port);
3642 } else {
3643 link_up = 0;
3644 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
3645 params->port);
62b29a5d 3646 }
de6eae1f
YR		 3647
3648 if (link_up) {
3649 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
3650 bnx2x_8073_resolve_fc(phy, params, vars);
3651 }
3652 return link_up;
b7737c9b
YR		 3653}
3654
de6eae1f
YR		 3655static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
3656 struct link_params *params)
3657{
3658 struct bnx2x *bp = params->bp;
3659 u8 gpio_port;
3660 gpio_port = params->port;
3661 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
3662 gpio_port);
3663 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3664 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3665 gpio_port);
3666}
3667
3668/******************************************************************/
3669/* BCM8705 PHY SECTION */
3670/******************************************************************/
3671static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 3672 struct link_params *params,
3673 struct link_vars *vars)
3674{
3675 struct bnx2x *bp = params->bp;
de6eae1f 3676 DP(NETIF_MSG_LINK, "init 8705\n");
b7737c9b
YR		 3677 /* Restore normal power mode*/
3678 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3679 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 3680 /* HW reset */
3681 bnx2x_ext_phy_hw_reset(bp, params->port);
3682 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
b7737c9b
YR		 3683 bnx2x_wait_reset_complete(bp, phy);
3684
de6eae1f
YR		 3685 bnx2x_cl45_write(bp, phy,
3686 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
3687 bnx2x_cl45_write(bp, phy,
3688 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
3689 bnx2x_cl45_write(bp, phy,
3690 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
3691 bnx2x_cl45_write(bp, phy,
3692 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
3693 /* BCM8705 doesn't have microcode, hence the 0 */
3694 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
3695 return 0;
3696}
4d295db0 3697
de6eae1f
YR		 3698static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
3699 struct link_params *params,
3700 struct link_vars *vars)
3701{
3702 u8 link_up = 0;
3703 u16 val1, rx_sd;
3704 struct bnx2x *bp = params->bp;
3705 DP(NETIF_MSG_LINK, "read status 8705\n");
3706 bnx2x_cl45_read(bp, phy,
3707 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
3708 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 3709
de6eae1f
YR		 3710 bnx2x_cl45_read(bp, phy,
3711 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
3712 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 3713
de6eae1f
YR		 3714 bnx2x_cl45_read(bp, phy,
3715 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
c2c8b03e 3716
de6eae1f
YR		 3717 bnx2x_cl45_read(bp, phy,
3718 MDIO_PMA_DEVAD, 0xc809, &val1);
3719 bnx2x_cl45_read(bp, phy,
3720 MDIO_PMA_DEVAD, 0xc809, &val1);
c2c8b03e 3721
de6eae1f
YR		 3722 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
3723 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
3724 if (link_up) {
3725 vars->line_speed = SPEED_10000;
3726 bnx2x_ext_phy_resolve_fc(phy, params, vars);
62b29a5d 3727 }
de6eae1f
YR		 3728 return link_up;
3729}
d90d96ba 3730
de6eae1f
YR		 3731/******************************************************************/
3732/* SFP+ module Section */
3733/******************************************************************/
3734static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
3735 struct bnx2x_phy *phy,
3736 u8 port,
3737 u8 tx_en)
3738{
3739 u16 val;
d90d96ba 3740
de6eae1f
YR		 3741 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
3742 tx_en, port);
3743 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
3744 bnx2x_cl45_read(bp, phy,
3745 MDIO_PMA_DEVAD,
3746 MDIO_PMA_REG_PHY_IDENTIFIER,
3747 &val);
d90d96ba 3748
de6eae1f
YR		 3749 if (tx_en)
3750 val &= ~(1<<15);
3751 else
3752 val |= (1<<15);
b7737c9b 3753
de6eae1f
YR		 3754 bnx2x_cl45_write(bp, phy,
3755 MDIO_PMA_DEVAD,
3756 MDIO_PMA_REG_PHY_IDENTIFIER,
3757 val);
b7737c9b
YR		 3758}
3759
de6eae1f
YR		 3760static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
3761 struct link_params *params,
3762 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b
YR		 3763{
3764 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3765 u16 val = 0;
3766 u16 i;
3767 if (byte_cnt > 16) {
3768 DP(NETIF_MSG_LINK, "Reading from eeprom is"
3769 " is limited to 0xf\n");
3770 return -EINVAL;
3771 }
3772 /* Set the read command byte count */
62b29a5d 3773 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3774 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
3775 (byte_cnt | 0xa000));
ea4e040a 3776
de6eae1f
YR		 3777 /* Set the read command address */
3778 bnx2x_cl45_write(bp, phy,
3779 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
3780 addr);
ea4e040a 3781
de6eae1f 3782 /* Activate read command */
62b29a5d 3783 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3784 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
3785 0x2c0f);
ea4e040a 3786
de6eae1f
YR		 3787 /* Wait up to 500us for command complete status */
3788 for (i = 0; i < 100; i++) {
3789 bnx2x_cl45_read(bp, phy,
3790 MDIO_PMA_DEVAD,
3791 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
3792 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
3793 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
3794 break;
3795 udelay(5);
62b29a5d 3796 }
62b29a5d 3797
de6eae1f
YR		 3798 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
3799 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
3800 DP(NETIF_MSG_LINK,
3801 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
3802 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
3803 return -EINVAL;
62b29a5d 3804 }
e10bc84d 3805
de6eae1f
YR		 3806 /* Read the buffer */
3807 for (i = 0; i < byte_cnt; i++) {
62b29a5d 3808 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 3809 MDIO_PMA_DEVAD,
3810 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
3811 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
62b29a5d 3812 }
6bbca910 3813
de6eae1f
YR		 3814 for (i = 0; i < 100; i++) {
3815 bnx2x_cl45_read(bp, phy,
3816 MDIO_PMA_DEVAD,
3817 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
3818 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
3819 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
3820 return 0;;
3821 msleep(1);
3822 }
3823 return -EINVAL;
b7737c9b 3824}
4d295db0 3825
de6eae1f
YR		 3826static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
3827 struct link_params *params,
3828 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b 3829{
b7737c9b 3830 struct bnx2x *bp = params->bp;
de6eae1f 3831 u16 val, i;
ea4e040a 3832
de6eae1f
YR		 3833 if (byte_cnt > 16) {
3834 DP(NETIF_MSG_LINK, "Reading from eeprom is"
3835 " is limited to 0xf\n");
3836 return -EINVAL;
3837 }
4d295db0 3838
de6eae1f
YR		 3839 /* Need to read from 1.8000 to clear it */
3840 bnx2x_cl45_read(bp, phy,
3841 MDIO_PMA_DEVAD,
3842 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
3843 &val);
4d295db0 3844
de6eae1f 3845 /* Set the read command byte count */
62b29a5d 3846 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3847 MDIO_PMA_DEVAD,
3848 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
3849 ((byte_cnt < 2) ? 2 : byte_cnt));
ea4e040a 3850
de6eae1f 3851 /* Set the read command address */
62b29a5d 3852 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3853 MDIO_PMA_DEVAD,
3854 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
3855 addr);
3856 /* Set the destination address */
62b29a5d 3857 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3858 MDIO_PMA_DEVAD,
3859 0x8004,
3860 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
62b29a5d 3861
de6eae1f 3862 /* Activate read command */
62b29a5d 3863 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 3864 MDIO_PMA_DEVAD,
3865 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
3866 0x8002);
3867 /* Wait appropriate time for two-wire command to finish before
3868 polling the status register */
3869 msleep(1);
4d295db0 3870
de6eae1f
YR		 3871 /* Wait up to 500us for command complete status */
3872 for (i = 0; i < 100; i++) {
62b29a5d 3873 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 3874 MDIO_PMA_DEVAD,
3875 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
3876 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
3877 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
3878 break;
3879 udelay(5);
62b29a5d 3880 }
4d295db0 3881
de6eae1f
YR		 3882 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
3883 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
3884 DP(NETIF_MSG_LINK,
3885 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
3886 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
3887 return -EINVAL;
3888 }
62b29a5d 3889
de6eae1f
YR		 3890 /* Read the buffer */
3891 for (i = 0; i < byte_cnt; i++) {
3892 bnx2x_cl45_read(bp, phy,
3893 MDIO_PMA_DEVAD,
3894 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
3895 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
3896 }
4d295db0 3897
de6eae1f
YR		 3898 for (i = 0; i < 100; i++) {
3899 bnx2x_cl45_read(bp, phy,
3900 MDIO_PMA_DEVAD,
3901 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
3902 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
3903 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
3904 return 0;;
3905 msleep(1);
62b29a5d
YR		 3906 }
3907
de6eae1f 3908 return -EINVAL;
b7737c9b
YR		 3909}
3910
de6eae1f
YR		 3911u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
3912 struct link_params *params, u16 addr,
3913 u8 byte_cnt, u8 *o_buf)
b7737c9b 3914{
de6eae1f
YR		 3915 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3916 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
3917 byte_cnt, o_buf);
3918 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3919 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
3920 byte_cnt, o_buf);
3921 return -EINVAL;
b7737c9b
YR		 3922}
3923
de6eae1f
YR		 3924static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
3925 struct link_params *params,
3926 u16 *edc_mode)
b7737c9b
YR		 3927{
3928 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3929 u8 val, check_limiting_mode = 0;
3930 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 3931
de6eae1f
YR		 3932 /* First check for copper cable */
3933 if (bnx2x_read_sfp_module_eeprom(phy,
3934 params,
3935 SFP_EEPROM_CON_TYPE_ADDR,
3936 1,
3937 &val) != 0) {
3938 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
3939 return -EINVAL;
3940 }
a1e4be39 3941
de6eae1f
YR		 3942 switch (val) {
3943 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
3944 {
3945 u8 copper_module_type;
62b29a5d 3946
de6eae1f
YR		 3947 /* Check if its active cable( includes SFP+ module)
3948 of passive cable*/
3949 if (bnx2x_read_sfp_module_eeprom(phy,
3950 params,
3951 SFP_EEPROM_FC_TX_TECH_ADDR,
3952 1,
3953 &copper_module_type) !=
3954 0) {
3955 DP(NETIF_MSG_LINK,
3956 "Failed to read copper-cable-type"
3957 " from SFP+ EEPROM\n");
3958 return -EINVAL;
3959 }
4f60dab1 3960
de6eae1f
YR		 3961 if (copper_module_type &
3962 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
3963 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
3964 check_limiting_mode = 1;
3965 } else if (copper_module_type &
3966 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
3967 DP(NETIF_MSG_LINK, "Passive Copper"
3968 " cable detected\n");
3969 *edc_mode =
3970 EDC_MODE_PASSIVE_DAC;
3971 } else {
3972 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
3973 "type 0x%x !!!\n", copper_module_type);
3974 return -EINVAL;
3975 }
3976 break;
62b29a5d 3977 }
de6eae1f
YR		 3978 case SFP_EEPROM_CON_TYPE_VAL_LC:
3979 DP(NETIF_MSG_LINK, "Optic module detected\n");
3980 check_limiting_mode = 1;
3981 break;
3982 default:
3983 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
3984 val);
3985 return -EINVAL;
62b29a5d 3986 }
2f904460 3987
de6eae1f
YR		 3988 if (check_limiting_mode) {
3989 u8 options[SFP_EEPROM_OPTIONS_SIZE];
3990 if (bnx2x_read_sfp_module_eeprom(phy,
3991 params,
3992 SFP_EEPROM_OPTIONS_ADDR,
3993 SFP_EEPROM_OPTIONS_SIZE,
3994 options) != 0) {
3995 DP(NETIF_MSG_LINK, "Failed to read Option"
3996 " field from module EEPROM\n");
3997 return -EINVAL;
3998 }
3999 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4000 *edc_mode = EDC_MODE_LINEAR;
4001 else
4002 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 4003 }
de6eae1f 4004 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
62b29a5d 4005 return 0;
b7737c9b 4006}
de6eae1f
YR		 4007/* This function read the relevant field from the module ( SFP+ ),
4008 and verify it is compliant with this board */
4009static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4010 struct link_params *params)
b7737c9b
YR		 4011{
4012 struct bnx2x *bp = params->bp;
a22f0788
YR		 4013 u32 val, cmd;
4014 u32 fw_resp, fw_cmd_param;
de6eae1f
YR		 4015 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4016 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
a22f0788 4017 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
de6eae1f
YR		 4018 val = REG_RD(bp, params->shmem_base +
4019 offsetof(struct shmem_region, dev_info.
4020 port_feature_config[params->port].config));
4021 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4022 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4023 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4024 return 0;
4025 }
ea4e040a 4026
a22f0788
YR		 4027 if (params->feature_config_flags &
4028 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4029 /* Use specific phy request */
4030 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4031 } else if (params->feature_config_flags &
4032 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4033 /* Use first phy request only in case of non-dual media*/
4034 if (DUAL_MEDIA(params)) {
4035 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4036 "verification\n");
4037 return -EINVAL;
4038 }
4039 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4040 } else {
4041 /* No support in OPT MDL detection */
de6eae1f 4042 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
a22f0788 4043 "verification\n");
de6eae1f
YR		 4044 return -EINVAL;
4045 }
a22f0788
YR		 4046 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4047 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
de6eae1f
YR		 4048 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4049 DP(NETIF_MSG_LINK, "Approved module\n");
4050 return 0;
4051 }
b7737c9b 4052
de6eae1f
YR		 4053 /* format the warning message */
4054 if (bnx2x_read_sfp_module_eeprom(phy,
4055 params,
4056 SFP_EEPROM_VENDOR_NAME_ADDR,
4057 SFP_EEPROM_VENDOR_NAME_SIZE,
4058 (u8 *)vendor_name))
4059 vendor_name[0] = '\0';
4060 else
4061 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4062 if (bnx2x_read_sfp_module_eeprom(phy,
4063 params,
4064 SFP_EEPROM_PART_NO_ADDR,
4065 SFP_EEPROM_PART_NO_SIZE,
4066 (u8 *)vendor_pn))
4067 vendor_pn[0] = '\0';
4068 else
4069 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4070
4071 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
4072 " Port %d from %s part number %s\n",
4073 params->port, vendor_name, vendor_pn);
a22f0788 4074 phy->flags |= FLAGS_SFP_NOT_APPROVED;
de6eae1f 4075 return -EINVAL;
b7737c9b 4076}
7aa0711f 4077
de6eae1f
YR		 4078static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4079 struct link_params *params)
7aa0711f 4080
4d295db0 4081{
de6eae1f 4082 u8 val;
4d295db0 4083 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4084 u16 timeout;
4085 /* Initialization time after hot-plug may take up to 300ms for some
4086 phys type ( e.g. JDSU ) */
4087 for (timeout = 0; timeout < 60; timeout++) {
4088 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4089 == 0) {
4090 DP(NETIF_MSG_LINK, "SFP+ module initialization "
4091 "took %d ms\n", timeout * 5);
4092 return 0;
4093 }
4094 msleep(5);
4095 }
4096 return -EINVAL;
4097}
4d295db0 4098
de6eae1f
YR		 4099static void bnx2x_8727_power_module(struct bnx2x *bp,
4100 struct bnx2x_phy *phy,
4101 u8 is_power_up) {
4102 /* Make sure GPIOs are not using for LED mode */
4103 u16 val;
4104 /*
4105 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
4106 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4107 * output
4108 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4109 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4110 * where the 1st bit is the over-current(only input), and 2nd bit is
4111 * for power( only output )
4112 */
4d295db0 4113
de6eae1f
YR		 4114 /*
4115 * In case of NOC feature is disabled and power is up, set GPIO control
4116 * as input to enable listening of over-current indication
4117 */
4118 if (phy->flags & FLAGS_NOC)
4119 return;
4120 if (!(phy->flags &
4121 FLAGS_NOC) && is_power_up)
4122 val = (1<<4);
4123 else
4124 /*
4125 * Set GPIO control to OUTPUT, and set the power bit
4126 * to according to the is_power_up
4127 */
4128 val = ((!(is_power_up)) << 1);
4d295db0 4129
de6eae1f
YR		 4130 bnx2x_cl45_write(bp, phy,
4131 MDIO_PMA_DEVAD,
4132 MDIO_PMA_REG_8727_GPIO_CTRL,
4133 val);
4134}
4d295db0 4135
de6eae1f
YR		 4136static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4137 struct bnx2x_phy *phy,
4138 u16 edc_mode)
4139{
4140 u16 cur_limiting_mode;
4d295db0 4141
de6eae1f
YR		 4142 bnx2x_cl45_read(bp, phy,
4143 MDIO_PMA_DEVAD,
4144 MDIO_PMA_REG_ROM_VER2,
4145 &cur_limiting_mode);
4146 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4147 cur_limiting_mode);
4148
4149 if (edc_mode == EDC_MODE_LIMITING) {
4150 DP(NETIF_MSG_LINK,
4151 "Setting LIMITING MODE\n");
e10bc84d 4152 bnx2x_cl45_write(bp, phy,
62b29a5d 4153 MDIO_PMA_DEVAD,
de6eae1f
YR		 4154 MDIO_PMA_REG_ROM_VER2,
4155 EDC_MODE_LIMITING);
4156 } else { /* LRM mode ( default )*/
4d295db0 4157
de6eae1f 4158 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4d295db0 4159
de6eae1f
YR		 4160 /* Changing to LRM mode takes quite few seconds.
4161 So do it only if current mode is limiting
4162 ( default is LRM )*/
4163 if (cur_limiting_mode != EDC_MODE_LIMITING)
4164 return 0;
4d295db0 4165
de6eae1f
YR		 4166 bnx2x_cl45_write(bp, phy,
4167 MDIO_PMA_DEVAD,
4168 MDIO_PMA_REG_LRM_MODE,
4169 0);
4170 bnx2x_cl45_write(bp, phy,
4171 MDIO_PMA_DEVAD,
4172 MDIO_PMA_REG_ROM_VER2,
4173 0x128);
4174 bnx2x_cl45_write(bp, phy,
4175 MDIO_PMA_DEVAD,
4176 MDIO_PMA_REG_MISC_CTRL0,
4177 0x4008);
4178 bnx2x_cl45_write(bp, phy,
4179 MDIO_PMA_DEVAD,
4180 MDIO_PMA_REG_LRM_MODE,
4181 0xaaaa);
4d295db0 4182 }
de6eae1f 4183 return 0;
4d295db0
EG		 4184}
4185
de6eae1f
YR		 4186static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4187 struct bnx2x_phy *phy,
4188 u16 edc_mode)
ea4e040a 4189{
de6eae1f
YR		 4190 u16 phy_identifier;
4191 u16 rom_ver2_val;
62b29a5d 4192 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4193 MDIO_PMA_DEVAD,
4194 MDIO_PMA_REG_PHY_IDENTIFIER,
4195 &phy_identifier);
ea4e040a 4196
de6eae1f
YR		 4197 bnx2x_cl45_write(bp, phy,
4198 MDIO_PMA_DEVAD,
4199 MDIO_PMA_REG_PHY_IDENTIFIER,
4200 (phy_identifier & ~(1<<9)));
ea4e040a 4201
62b29a5d 4202 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4203 MDIO_PMA_DEVAD,
4204 MDIO_PMA_REG_ROM_VER2,
4205 &rom_ver2_val);
4206 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4207 bnx2x_cl45_write(bp, phy,
4208 MDIO_PMA_DEVAD,
4209 MDIO_PMA_REG_ROM_VER2,
4210 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4d295db0 4211
de6eae1f
YR		 4212 bnx2x_cl45_write(bp, phy,
4213 MDIO_PMA_DEVAD,
4214 MDIO_PMA_REG_PHY_IDENTIFIER,
4215 (phy_identifier | (1<<9)));
4d295db0 4216
de6eae1f 4217 return 0;
b7737c9b 4218}
ea4e040a 4219
a22f0788
YR		 4220static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4221 struct link_params *params,
4222 u32 action)
4223{
4224 struct bnx2x *bp = params->bp;
4225
4226 switch (action) {
4227 case DISABLE_TX:
4228 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4229 break;
4230 case ENABLE_TX:
4231 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
4232 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4233 break;
4234 default:
4235 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
4236 action);
4237 return;
4238 }
4239}
4240
de6eae1f
YR		 4241static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
4242 struct link_params *params)
b7737c9b 4243{
b7737c9b 4244 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4245 u16 edc_mode;
4246 u8 rc = 0;
ea4e040a 4247
de6eae1f
YR		 4248 u32 val = REG_RD(bp, params->shmem_base +
4249 offsetof(struct shmem_region, dev_info.
4250 port_feature_config[params->port].config));
62b29a5d 4251
de6eae1f
YR		 4252 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
4253 params->port);
4254
4255 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
4256 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4257 return -EINVAL;
4258 } else if (bnx2x_verify_sfp_module(phy, params) !=
4259 0) {
4260 /* check SFP+ module compatibility */
4261 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4262 rc = -EINVAL;
4263 /* Turn on fault module-detected led */
4264 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4265 MISC_REGISTERS_GPIO_HIGH,
4266 params->port);
4267 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
4268 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4269 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
4270 /* Shutdown SFP+ module */
4271 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
4272 bnx2x_8727_power_module(bp, phy, 0);
4273 return rc;
4274 }
4275 } else {
4276 /* Turn off fault module-detected led */
4277 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
4278 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4279 MISC_REGISTERS_GPIO_LOW,
4280 params->port);
62b29a5d 4281 }
b7737c9b 4282
de6eae1f
YR		 4283 /* power up the SFP module */
4284 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4285 bnx2x_8727_power_module(bp, phy, 1);
c18aa15d 4286
de6eae1f
YR		 4287 /* Check and set limiting mode / LRM mode on 8726.
4288 On 8727 it is done automatically */
4289 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4290 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
4291 else
4292 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
4293 /*
4294 * Enable transmit for this module if the module is approved, or
4295 * if unapproved modules should also enable the Tx laser
4296 */
4297 if (rc == 0 ||
4298 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
4299 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4300 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4301 else
4302 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
b7737c9b 4303
de6eae1f
YR		 4304 return rc;
4305}
4306
4307void bnx2x_handle_module_detect_int(struct link_params *params)
b7737c9b
YR		 4308{
4309 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4310 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
4311 u32 gpio_val;
4312 u8 port = params->port;
4d295db0 4313
de6eae1f
YR		 4314 /* Set valid module led off */
4315 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4316 MISC_REGISTERS_GPIO_HIGH,
4317 params->port);
4d295db0 4318
de6eae1f
YR		 4319 /* Get current gpio val refelecting module plugged in / out*/
4320 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
62b29a5d 4321
de6eae1f
YR		 4322 /* Call the handling function in case module is detected */
4323 if (gpio_val == 0) {
4d295db0 4324
de6eae1f
YR		 4325 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
4326 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
4327 port);
4d295db0 4328
de6eae1f
YR		 4329 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
4330 bnx2x_sfp_module_detection(phy, params);
4331 else
4332 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4333 } else {
4334 u32 val = REG_RD(bp, params->shmem_base +
4335 offsetof(struct shmem_region, dev_info.
4336 port_feature_config[params->port].
4337 config));
4d295db0 4338
de6eae1f
YR		 4339 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
4340 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
4341 port);
4342 /* Module was plugged out. */
4343 /* Disable transmit for this module */
4344 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4345 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4346 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
62b29a5d 4347 }
de6eae1f 4348}
62b29a5d 4349
de6eae1f
YR		 4350/******************************************************************/
4351/* common BCM8706/BCM8726 PHY SECTION */
4352/******************************************************************/
4353static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
4354 struct link_params *params,
4355 struct link_vars *vars)
4356{
4357 u8 link_up = 0;
4358 u16 val1, val2, rx_sd, pcs_status;
4359 struct bnx2x *bp = params->bp;
4360 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4361 /* Clear RX Alarm*/
62b29a5d 4362 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4363 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4364 /* clear LASI indication*/
4365 bnx2x_cl45_read(bp, phy,
4366 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4367 bnx2x_cl45_read(bp, phy,
4368 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
4369 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
62b29a5d
YR		 4370
4371 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4372 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4373 bnx2x_cl45_read(bp, phy,
4374 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
4375 bnx2x_cl45_read(bp, phy,
4376 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
4377 bnx2x_cl45_read(bp, phy,
4378 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
62b29a5d 4379
de6eae1f
YR		 4380 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
4381 " link_status 0x%x\n", rx_sd, pcs_status, val2);
4382 /* link is up if both bit 0 of pmd_rx_sd and
4383 * bit 0 of pcs_status are set, or if the autoneg bit
4384 * 1 is set
4385 */
4386 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
4387 if (link_up) {
4388 if (val2 & (1<<1))
4389 vars->line_speed = SPEED_1000;
4390 else
4391 vars->line_speed = SPEED_10000;
62b29a5d 4392 bnx2x_ext_phy_resolve_fc(phy, params, vars);
de6eae1f 4393 }
62b29a5d 4394 return link_up;
b7737c9b 4395}
62b29a5d 4396
de6eae1f
YR		 4397/******************************************************************/
4398/* BCM8706 PHY SECTION */
4399/******************************************************************/
4400static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 4401 struct link_params *params,
4402 struct link_vars *vars)
4403{
de6eae1f 4404 u16 cnt, val;
b7737c9b 4405 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4406 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4407 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4408 /* HW reset */
4409 bnx2x_ext_phy_hw_reset(bp, params->port);
4410 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4411 bnx2x_wait_reset_complete(bp, phy);
ea4e040a 4412
de6eae1f
YR		 4413 /* Wait until fw is loaded */
4414 for (cnt = 0; cnt < 100; cnt++) {
4415 bnx2x_cl45_read(bp, phy,
4416 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
4417 if (val)
4418 break;
4419 msleep(10);
4420 }
4421 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
4422 if ((params->feature_config_flags &
4423 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4424 u8 i;
4425 u16 reg;
4426 for (i = 0; i < 4; i++) {
4427 reg = MDIO_XS_8706_REG_BANK_RX0 +
4428 i*(MDIO_XS_8706_REG_BANK_RX1 -
4429 MDIO_XS_8706_REG_BANK_RX0);
4430 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
4431 /* Clear first 3 bits of the control */
4432 val &= ~0x7;
4433 /* Set control bits according to configuration */
4434 val |= (phy->rx_preemphasis[i] & 0x7);
4435 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
4436 " reg 0x%x <-- val 0x%x\n", reg, val);
4437 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
4438 }
4439 }
4440 /* Force speed */
4441 if (phy->req_line_speed == SPEED_10000) {
4442 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
ea4e040a 4443
de6eae1f
YR		 4444 bnx2x_cl45_write(bp, phy,
4445 MDIO_PMA_DEVAD,
4446 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
4447 bnx2x_cl45_write(bp, phy,
4448 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
4449 } else {
4450 /* Force 1Gbps using autoneg with 1G advertisment */
6bbca910 4451
de6eae1f
YR		 4452 /* Allow CL37 through CL73 */
4453 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
4454 bnx2x_cl45_write(bp, phy,
4455 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6bbca910 4456
de6eae1f
YR		 4457 /* Enable Full-Duplex advertisment on CL37 */
4458 bnx2x_cl45_write(bp, phy,
4459 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
4460 /* Enable CL37 AN */
4461 bnx2x_cl45_write(bp, phy,
4462 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4463 /* 1G support */
4464 bnx2x_cl45_write(bp, phy,
4465 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
6bbca910 4466
de6eae1f
YR		 4467 /* Enable clause 73 AN */
4468 bnx2x_cl45_write(bp, phy,
4469 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4470 bnx2x_cl45_write(bp, phy,
4471 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4472 0x0400);
4473 bnx2x_cl45_write(bp, phy,
4474 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
4475 0x0004);
4476 }
4477 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
4478 return 0;
4479}
ea4e040a 4480
de6eae1f
YR		 4481static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
4482 struct link_params *params,
4483 struct link_vars *vars)
4484{
4485 return bnx2x_8706_8726_read_status(phy, params, vars);
4486}
6bbca910 4487
de6eae1f
YR		 4488/******************************************************************/
4489/* BCM8726 PHY SECTION */
4490/******************************************************************/
4491static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
4492 struct link_params *params)
4493{
4494 struct bnx2x *bp = params->bp;
4495 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
4496 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
4497}
62b29a5d 4498
de6eae1f
YR		 4499static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
4500 struct link_params *params)
4501{
4502 struct bnx2x *bp = params->bp;
4503 /* Need to wait 100ms after reset */
4504 msleep(100);
62b29a5d 4505
de6eae1f
YR		 4506 /* Micro controller re-boot */
4507 bnx2x_cl45_write(bp, phy,
4508 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
62b29a5d 4509
de6eae1f
YR		 4510 /* Set soft reset */
4511 bnx2x_cl45_write(bp, phy,
4512 MDIO_PMA_DEVAD,
4513 MDIO_PMA_REG_GEN_CTRL,
4514 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
62b29a5d 4515
de6eae1f
YR		 4516 bnx2x_cl45_write(bp, phy,
4517 MDIO_PMA_DEVAD,
4518 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6bbca910 4519
de6eae1f
YR		 4520 bnx2x_cl45_write(bp, phy,
4521 MDIO_PMA_DEVAD,
4522 MDIO_PMA_REG_GEN_CTRL,
4523 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
4524
4525 /* wait for 150ms for microcode load */
4526 msleep(150);
4527
4528 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
4529 bnx2x_cl45_write(bp, phy,
4530 MDIO_PMA_DEVAD,
4531 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
4532
4533 msleep(200);
4534 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
b7737c9b
YR		 4535}
4536
de6eae1f 4537static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 4538 struct link_params *params,
4539 struct link_vars *vars)
4540{
4541 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4542 u16 val1;
4543 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
62b29a5d
YR		 4544 if (link_up) {
4545 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 4546 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
4547 &val1);
4548 if (val1 & (1<<15)) {
4549 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4550 link_up = 0;
4551 vars->line_speed = 0;
4552 }
62b29a5d
YR		 4553 }
4554 return link_up;
b7737c9b
YR		 4555}
4556
de6eae1f
YR		 4557
4558static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
4559 struct link_params *params,
4560 struct link_vars *vars)
b7737c9b
YR		 4561{
4562 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4563 u32 val;
4564 u32 swap_val, swap_override, aeu_gpio_mask, offset;
4565 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
4566 /* Restore normal power mode*/
4567 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4568 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 4569
de6eae1f
YR		 4570 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4571 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
62b29a5d 4572
de6eae1f
YR		 4573 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
4574 bnx2x_wait_reset_complete(bp, phy);
62b29a5d 4575
de6eae1f 4576 bnx2x_8726_external_rom_boot(phy, params);
62b29a5d 4577
de6eae1f
YR		 4578 /* Need to call module detected on initialization since
4579 the module detection triggered by actual module
4580 insertion might occur before driver is loaded, and when
4581 driver is loaded, it reset all registers, including the
4582 transmitter */
4583 bnx2x_sfp_module_detection(phy, params);
62b29a5d 4584
de6eae1f
YR		 4585 if (phy->req_line_speed == SPEED_1000) {
4586 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4587 bnx2x_cl45_write(bp, phy,
4588 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
4589 bnx2x_cl45_write(bp, phy,
4590 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
4591 bnx2x_cl45_write(bp, phy,
4592 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
4593 bnx2x_cl45_write(bp, phy,
4594 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4595 0x400);
4596 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
4597 (phy->speed_cap_mask &
4598 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
4599 ((phy->speed_cap_mask &
4600 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
4601 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4602 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
4603 /* Set Flow control */
4604 bnx2x_ext_phy_set_pause(params, phy, vars);
4605 bnx2x_cl45_write(bp, phy,
4606 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
4607 bnx2x_cl45_write(bp, phy,
4608 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
4609 bnx2x_cl45_write(bp, phy,
4610 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
4611 bnx2x_cl45_write(bp, phy,
4612 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4613 bnx2x_cl45_write(bp, phy,
4614 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4615 /* Enable RX-ALARM control to receive
4616 interrupt for 1G speed change */
4617 bnx2x_cl45_write(bp, phy,
4618 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
4619 bnx2x_cl45_write(bp, phy,
4620 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4621 0x400);
62b29a5d 4622
de6eae1f
YR		 4623 } else { /* Default 10G. Set only LASI control */
4624 bnx2x_cl45_write(bp, phy,
4625 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
7aa0711f
YR		 4626 }
4627
de6eae1f
YR		 4628 /* Set TX PreEmphasis if needed */
4629 if ((params->feature_config_flags &
4630 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4631 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4632 "TX_CTRL2 0x%x\n",
4633 phy->tx_preemphasis[0],
4634 phy->tx_preemphasis[1]);
4635 bnx2x_cl45_write(bp, phy,
4636 MDIO_PMA_DEVAD,
4637 MDIO_PMA_REG_8726_TX_CTRL1,
4638 phy->tx_preemphasis[0]);
c18aa15d 4639
de6eae1f
YR		 4640 bnx2x_cl45_write(bp, phy,
4641 MDIO_PMA_DEVAD,
4642 MDIO_PMA_REG_8726_TX_CTRL2,
4643 phy->tx_preemphasis[1]);
4644 }
ab6ad5a4 4645
de6eae1f
YR		 4646 /* Set GPIO3 to trigger SFP+ module insertion/removal */
4647 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
4648 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
ea4e040a 4649
de6eae1f
YR		 4650 /* The GPIO should be swapped if the swap register is set and active */
4651 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4652 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
ea4e040a 4653
de6eae1f
YR		 4654 /* Select function upon port-swap configuration */
4655 if (params->port == 0) {
4656 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4657 aeu_gpio_mask = (swap_val && swap_override) ?
4658 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
4659 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
4660 } else {
4661 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
4662 aeu_gpio_mask = (swap_val && swap_override) ?
4663 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
4664 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
ea4e040a 4665 }
de6eae1f
YR		 4666 val = REG_RD(bp, offset);
4667 /* add GPIO3 to group */
4668 val |= aeu_gpio_mask;
4669 REG_WR(bp, offset, val);
4670 return 0;
ab6ad5a4 4671
ea4e040a
YR		 4672}
4673
de6eae1f
YR		 4674static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
4675 struct link_params *params)
2f904460 4676{
de6eae1f
YR		 4677 struct bnx2x *bp = params->bp;
4678 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
4679 /* Set serial boot control for external load */
4680 bnx2x_cl45_write(bp, phy,
4681 MDIO_PMA_DEVAD,
4682 MDIO_PMA_REG_GEN_CTRL, 0x0001);
4683}
4684
4685/******************************************************************/
4686/* BCM8727 PHY SECTION */
4687/******************************************************************/
4688static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
4689 struct link_params *params) {
4690 u32 swap_val, swap_override;
4691 u8 port;
4692 /**
4693 * The PHY reset is controlled by GPIO 1. Fake the port number
4694 * to cancel the swap done in set_gpio()
2f904460 4695 */
de6eae1f
YR		 4696 struct bnx2x *bp = params->bp;
4697 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4698 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4699 port = (swap_val && swap_override) ^ 1;
4700 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4701 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2f904460 4702}
e10bc84d 4703
de6eae1f
YR		 4704static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
4705 struct link_params *params,
4706 struct link_vars *vars)
ea4e040a 4707{
de6eae1f
YR		 4708 u16 tmp1, val, mod_abs;
4709 u16 rx_alarm_ctrl_val;
4710 u16 lasi_ctrl_val;
ea4e040a 4711 struct bnx2x *bp = params->bp;
de6eae1f 4712 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
ea4e040a 4713
de6eae1f
YR		 4714 bnx2x_wait_reset_complete(bp, phy);
4715 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
4716 lasi_ctrl_val = 0x0004;
ea4e040a 4717
de6eae1f
YR		 4718 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
4719 /* enable LASI */
4720 bnx2x_cl45_write(bp, phy,
4721 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4722 rx_alarm_ctrl_val);
ea4e040a 4723
de6eae1f
YR		 4724 bnx2x_cl45_write(bp, phy,
4725 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
ea4e040a 4726
de6eae1f
YR		 4727 /* Initially configure MOD_ABS to interrupt when
4728 module is presence( bit 8) */
4729 bnx2x_cl45_read(bp, phy,
4730 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4731 /* Set EDC off by setting OPTXLOS signal input to low
4732 (bit 9).
4733 When the EDC is off it locks onto a reference clock and
4734 avoids becoming 'lost'.*/
4735 mod_abs &= ~((1<<8) | (1<<9));
4736 bnx2x_cl45_write(bp, phy,
4737 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 4738
ea4e040a 4739
de6eae1f
YR		 4740 /* Make MOD_ABS give interrupt on change */
4741 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4742 &val);
4743 val |= (1<<12);
4744 bnx2x_cl45_write(bp, phy,
4745 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
4746 /* Set 8727 GPIOs to input to allow reading from the
4747 8727 GPIO0 status which reflect SFP+ module
4748 over-current */
b7737c9b 4749
de6eae1f
YR		 4750 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4751 &val);
4752 val &= 0xff8f; /* Reset bits 4-6 */
4753 bnx2x_cl45_write(bp, phy,
4754 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
ea4e040a 4755
de6eae1f
YR		 4756 bnx2x_8727_power_module(bp, phy, 1);
4757
4758 bnx2x_cl45_read(bp, phy,
4759 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4760
4761 bnx2x_cl45_read(bp, phy,
4762 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4763
4764 /* Set option 1G speed */
4765 if (phy->req_line_speed == SPEED_1000) {
4766 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4767 bnx2x_cl45_write(bp, phy,
4768 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
4769 bnx2x_cl45_write(bp, phy,
4770 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
4771 bnx2x_cl45_read(bp, phy,
4772 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
4773 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
a22f0788
YR		 4774 /**
4775 * Power down the XAUI until link is up in case of dual-media
4776 * and 1G
4777 */
4778 if (DUAL_MEDIA(params)) {
4779 bnx2x_cl45_read(bp, phy,
4780 MDIO_PMA_DEVAD,
4781 MDIO_PMA_REG_8727_PCS_GP, &val);
4782 val |= (3<<10);
4783 bnx2x_cl45_write(bp, phy,
4784 MDIO_PMA_DEVAD,
4785 MDIO_PMA_REG_8727_PCS_GP, val);
4786 }
de6eae1f
YR		 4787 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
4788 ((phy->speed_cap_mask &
4789 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
4790 ((phy->speed_cap_mask &
4791 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
4792 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4793
4794 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
4795 bnx2x_cl45_write(bp, phy,
4796 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
4797 bnx2x_cl45_write(bp, phy,
4798 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
4799 } else {
4800 /**
4801 * Since the 8727 has only single reset pin, need to set the 10G
4802 * registers although it is default
4803 */
4804 bnx2x_cl45_write(bp, phy,
4805 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
4806 0x0020);
4807 bnx2x_cl45_write(bp, phy,
4808 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
4809 bnx2x_cl45_write(bp, phy,
4810 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4811 bnx2x_cl45_write(bp, phy,
4812 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
4813 0x0008);
ea4e040a 4814 }
ea4e040a 4815
de6eae1f
YR		 4816 /* Set 2-wire transfer rate of SFP+ module EEPROM
4817 * to 100Khz since some DACs(direct attached cables) do
4818 * not work at 400Khz.
4819 */
4820 bnx2x_cl45_write(bp, phy,
4821 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4822 0xa001);
b7737c9b 4823
de6eae1f
YR		 4824 /* Set TX PreEmphasis if needed */
4825 if ((params->feature_config_flags &
4826 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4827 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
4828 phy->tx_preemphasis[0],
4829 phy->tx_preemphasis[1]);
4830 bnx2x_cl45_write(bp, phy,
4831 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
4832 phy->tx_preemphasis[0]);
ea4e040a 4833
de6eae1f
YR		 4834 bnx2x_cl45_write(bp, phy,
4835 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
4836 phy->tx_preemphasis[1]);
4837 }
ea4e040a 4838
de6eae1f 4839 return 0;
ea4e040a
YR		 4840}
4841
de6eae1f
YR		 4842static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
4843 struct link_params *params)
ea4e040a 4844{
ea4e040a 4845 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4846 u16 mod_abs, rx_alarm_status;
4847 u32 val = REG_RD(bp, params->shmem_base +
4848 offsetof(struct shmem_region, dev_info.
4849 port_feature_config[params->port].
4850 config));
4851 bnx2x_cl45_read(bp, phy,
4852 MDIO_PMA_DEVAD,
4853 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4854 if (mod_abs & (1<<8)) {
ea4e040a 4855
de6eae1f
YR		 4856 /* Module is absent */
4857 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4858 "show module is absent\n");
ea4e040a 4859
de6eae1f
YR		 4860 /* 1. Set mod_abs to detect next module
4861 presence event
4862 2. Set EDC off by setting OPTXLOS signal input to low
4863 (bit 9).
4864 When the EDC is off it locks onto a reference clock and
4865 avoids becoming 'lost'.*/
4866 mod_abs &= ~((1<<8)|(1<<9));
4867 bnx2x_cl45_write(bp, phy,
4868 MDIO_PMA_DEVAD,
4869 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 4870
de6eae1f
YR		 4871 /* Clear RX alarm since it stays up as long as
4872 the mod_abs wasn't changed */
4873 bnx2x_cl45_read(bp, phy,
4874 MDIO_PMA_DEVAD,
4875 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 4876
de6eae1f
YR		 4877 } else {
4878 /* Module is present */
4879 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4880 "show module is present\n");
4881 /* First thing, disable transmitter,
4882 and if the module is ok, the
4883 module_detection will enable it*/
ea4e040a 4884
de6eae1f
YR		 4885 /* 1. Set mod_abs to detect next module
4886 absent event ( bit 8)
4887 2. Restore the default polarity of the OPRXLOS signal and
4888 this signal will then correctly indicate the presence or
4889 absence of the Rx signal. (bit 9) */
4890 mod_abs |= ((1<<8)|(1<<9));
e10bc84d 4891 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4892 MDIO_PMA_DEVAD,
4893 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 4894
de6eae1f
YR		 4895 /* Clear RX alarm since it stays up as long as
4896 the mod_abs wasn't changed. This is need to be done
4897 before calling the module detection, otherwise it will clear
4898 the link update alarm */
4899 bnx2x_cl45_read(bp, phy,
4900 MDIO_PMA_DEVAD,
4901 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 4902
ea4e040a 4903
de6eae1f
YR		 4904 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4905 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4906 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4907
4908 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
4909 bnx2x_sfp_module_detection(phy, params);
4910 else
4911 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
ea4e040a 4912 }
de6eae1f
YR		 4913
4914 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4915 rx_alarm_status);
4916 /* No need to check link status in case of
4917 module plugged in/out */
ea4e040a
YR		 4918}
4919
de6eae1f
YR		 4920static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
4921 struct link_params *params,
4922 struct link_vars *vars)
4923
ea4e040a
YR		 4924{
4925 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4926 u8 link_up = 0;
4927 u16 link_status = 0;
a22f0788
YR		 4928 u16 rx_alarm_status, lasi_ctrl, val1;
4929
4930 /* If PHY is not initialized, do not check link status */
4931 bnx2x_cl45_read(bp, phy,
4932 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
4933 &lasi_ctrl);
4934 if (!lasi_ctrl)
4935 return 0;
4936
de6eae1f
YR		 4937 /* Check the LASI */
4938 bnx2x_cl45_read(bp, phy,
4939 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4940 &rx_alarm_status);
4941 vars->line_speed = 0;
4942 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
4943
4944 bnx2x_cl45_read(bp, phy,
4945 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4946
4947 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
4948
4949 /* Clear MSG-OUT */
4950 bnx2x_cl45_read(bp, phy,
4951 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4952
4953 /**
4954 * If a module is present and there is need to check
4955 * for over current
4956 */
4957 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
4958 /* Check over-current using 8727 GPIO0 input*/
4959 bnx2x_cl45_read(bp, phy,
4960 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
4961 &val1);
4962
4963 if ((val1 & (1<<8)) == 0) {
4964 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
4965 " on port %d\n", params->port);
4966 netdev_err(bp->dev, "Error: Power fault on Port %d has"
4967 " been detected and the power to "
4968 "that SFP+ module has been removed"
4969 " to prevent failure of the card."
4970 " Please remove the SFP+ module and"
4971 " restart the system to clear this"
4972 " error.\n",
4973 params->port);
4974
4975 /*
4976 * Disable all RX_ALARMs except for
4977 * mod_abs
4978 */
4979 bnx2x_cl45_write(bp, phy,
4980 MDIO_PMA_DEVAD,
4981 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
4982
4983 bnx2x_cl45_read(bp, phy,
4984 MDIO_PMA_DEVAD,
4985 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
4986 /* Wait for module_absent_event */
4987 val1 |= (1<<8);
4988 bnx2x_cl45_write(bp, phy,
4989 MDIO_PMA_DEVAD,
4990 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
4991 /* Clear RX alarm */
4992 bnx2x_cl45_read(bp, phy,
4993 MDIO_PMA_DEVAD,
4994 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4995 return 0;
4996 }
4997 } /* Over current check */
4998
4999 /* When module absent bit is set, check module */
5000 if (rx_alarm_status & (1<<5)) {
5001 bnx2x_8727_handle_mod_abs(phy, params);
5002 /* Enable all mod_abs and link detection bits */
5003 bnx2x_cl45_write(bp, phy,
5004 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5005 ((1<<5) | (1<<2)));
5006 }
a22f0788
YR		 5007 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5008 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
de6eae1f
YR		 5009 /* If transmitter is disabled, ignore false link up indication */
5010 bnx2x_cl45_read(bp, phy,
5011 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5012 if (val1 & (1<<15)) {
5013 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5014 return 0;
5015 }
5016
5017 bnx2x_cl45_read(bp, phy,
5018 MDIO_PMA_DEVAD,
5019 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5020
5021 /* Bits 0..2 --> speed detected,
5022 bits 13..15--> link is down */
5023 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5024 link_up = 1;
5025 vars->line_speed = SPEED_10000;
5026 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5027 link_up = 1;
5028 vars->line_speed = SPEED_1000;
5029 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5030 params->port);
5031 } else {
5032 link_up = 0;
5033 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5034 params->port);
5035 }
5036 if (link_up)
5037 bnx2x_ext_phy_resolve_fc(phy, params, vars);
a22f0788
YR		 5038
5039 if ((DUAL_MEDIA(params)) &&
5040 (phy->req_line_speed == SPEED_1000)) {
5041 bnx2x_cl45_read(bp, phy,
5042 MDIO_PMA_DEVAD,
5043 MDIO_PMA_REG_8727_PCS_GP, &val1);
5044 /**
5045 * In case of dual-media board and 1G, power up the XAUI side,
5046 * otherwise power it down. For 10G it is done automatically
5047 */
5048 if (link_up)
5049 val1 &= ~(3<<10);
5050 else
5051 val1 |= (3<<10);
5052 bnx2x_cl45_write(bp, phy,
5053 MDIO_PMA_DEVAD,
5054 MDIO_PMA_REG_8727_PCS_GP, val1);
5055 }
de6eae1f 5056 return link_up;
b7737c9b 5057}
ea4e040a 5058
de6eae1f
YR		 5059static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5060 struct link_params *params)
b7737c9b
YR		 5061{
5062 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5063 /* Disable Transmitter */
5064 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
a22f0788
YR		 5065 /* Clear LASI */
5066 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5067
ea4e040a 5068}
c18aa15d 5069
de6eae1f
YR		 5070/******************************************************************/
5071/* BCM8481/BCM84823/BCM84833 PHY SECTION */
5072/******************************************************************/
5073static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5074 struct link_params *params)
ea4e040a 5075{
de6eae1f
YR		 5076 u16 val, fw_ver1, fw_ver2, cnt;
5077 struct bnx2x *bp = params->bp;
ea4e040a 5078
de6eae1f
YR		 5079 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
5080 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
5081 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
5082 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5083 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
5084 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
5085 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
ea4e040a 5086
de6eae1f
YR		 5087 for (cnt = 0; cnt < 100; cnt++) {
5088 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5089 if (val & 1)
5090 break;
5091 udelay(5);
5092 }
5093 if (cnt == 100) {
5094 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
5095 bnx2x_save_spirom_version(bp, params->port, 0,
5096 phy->ver_addr);
5097 return;
5098 }
ea4e040a 5099
ea4e040a 5100
de6eae1f
YR		 5101 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
5102 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
5103 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5104 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
5105 for (cnt = 0; cnt < 100; cnt++) {
5106 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5107 if (val & 1)
5108 break;
5109 udelay(5);
5110 }
5111 if (cnt == 100) {
5112 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
5113 bnx2x_save_spirom_version(bp, params->port, 0,
5114 phy->ver_addr);
5115 return;
ea4e040a
YR		 5116 }
5117
de6eae1f
YR		 5118 /* lower 16 bits of the register SPI_FW_STATUS */
5119 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
5120 /* upper 16 bits of register SPI_FW_STATUS */
5121 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
ea4e040a 5122
de6eae1f
YR		 5123 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
5124 phy->ver_addr);
5125}
ea4e040a 5126
de6eae1f
YR		 5127static void bnx2x_848xx_set_led(struct bnx2x *bp,
5128 struct bnx2x_phy *phy)
ea4e040a 5129{
de6eae1f 5130 u16 val;
7846e471 5131
de6eae1f
YR		 5132 /* PHYC_CTL_LED_CTL */
5133 bnx2x_cl45_read(bp, phy,
5134 MDIO_PMA_DEVAD,
5135 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
5136 val &= 0xFE00;
5137 val |= 0x0092;
345b5d52 5138
de6eae1f
YR		 5139 bnx2x_cl45_write(bp, phy,
5140 MDIO_PMA_DEVAD,
5141 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
ea4e040a 5142
de6eae1f
YR		 5143 bnx2x_cl45_write(bp, phy,
5144 MDIO_PMA_DEVAD,
5145 MDIO_PMA_REG_8481_LED1_MASK,
5146 0x80);
ea4e040a 5147
de6eae1f
YR		 5148 bnx2x_cl45_write(bp, phy,
5149 MDIO_PMA_DEVAD,
5150 MDIO_PMA_REG_8481_LED2_MASK,
5151 0x18);
ea4e040a 5152
de6eae1f
YR		 5153 bnx2x_cl45_write(bp, phy,
5154 MDIO_PMA_DEVAD,
5155 MDIO_PMA_REG_8481_LED3_MASK,
5156 0x0040);
ea4e040a 5157
de6eae1f
YR		 5158 /* 'Interrupt Mask' */
5159 bnx2x_cl45_write(bp, phy,
5160 MDIO_AN_DEVAD,
5161 0xFFFB, 0xFFFD);
ea4e040a
YR		 5162}
5163
de6eae1f 5164static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
a22f0788
YR		 5165 struct link_params *params,
5166 struct link_vars *vars)
ea4e040a 5167{
c18aa15d 5168 struct bnx2x *bp = params->bp;
de6eae1f 5169 u16 autoneg_val, an_1000_val, an_10_100_val;
de6eae1f
YR		 5170 bnx2x_wait_reset_complete(bp, phy);
5171 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
5172 1 << NIG_LATCH_BC_ENABLE_MI_INT);
ea4e040a 5173
de6eae1f
YR		 5174 bnx2x_cl45_write(bp, phy,
5175 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
ea4e040a 5176
de6eae1f 5177 bnx2x_848xx_set_led(bp, phy);
ea4e040a 5178
de6eae1f
YR		 5179 /* set 1000 speed advertisement */
5180 bnx2x_cl45_read(bp, phy,
5181 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5182 &an_1000_val);
57963ed9 5183
de6eae1f
YR		 5184 bnx2x_ext_phy_set_pause(params, phy, vars);
5185 bnx2x_cl45_read(bp, phy,
5186 MDIO_AN_DEVAD,
5187 MDIO_AN_REG_8481_LEGACY_AN_ADV,
5188 &an_10_100_val);
5189 bnx2x_cl45_read(bp, phy,
5190 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
5191 &autoneg_val);
5192 /* Disable forced speed */
5193 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
5194 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
ea4e040a 5195
de6eae1f
YR		 5196 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5197 (phy->speed_cap_mask &
5198 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5199 (phy->req_line_speed == SPEED_1000)) {
5200 an_1000_val |= (1<<8);
5201 autoneg_val |= (1<<9 | 1<<12);
5202 if (phy->req_duplex == DUPLEX_FULL)
5203 an_1000_val |= (1<<9);
5204 DP(NETIF_MSG_LINK, "Advertising 1G\n");
5205 } else
5206 an_1000_val &= ~((1<<8) | (1<<9));
ea4e040a 5207
de6eae1f
YR		 5208 bnx2x_cl45_write(bp, phy,
5209 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5210 an_1000_val);
ea4e040a 5211
de6eae1f
YR		 5212 /* set 10 speed advertisement */
5213 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5214 (phy->speed_cap_mask &
5215 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
5216 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
5217 an_10_100_val |= (1<<7);
5218 /* Enable autoneg and restart autoneg for legacy speeds */
5219 autoneg_val |= (1<<9 | 1<<12);
b7737c9b 5220
de6eae1f
YR		 5221 if (phy->req_duplex == DUPLEX_FULL)
5222 an_10_100_val |= (1<<8);
5223 DP(NETIF_MSG_LINK, "Advertising 100M\n");
5224 }
5225 /* set 10 speed advertisement */
5226 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5227 (phy->speed_cap_mask &
5228 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
5229 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
5230 an_10_100_val |= (1<<5);
5231 autoneg_val |= (1<<9 | 1<<12);
5232 if (phy->req_duplex == DUPLEX_FULL)
5233 an_10_100_val |= (1<<6);
5234 DP(NETIF_MSG_LINK, "Advertising 10M\n");
5235 }
b7737c9b 5236
de6eae1f
YR		 5237 /* Only 10/100 are allowed to work in FORCE mode */
5238 if (phy->req_line_speed == SPEED_100) {
5239 autoneg_val |= (1<<13);
5240 /* Enabled AUTO-MDIX when autoneg is disabled */
5241 bnx2x_cl45_write(bp, phy,
5242 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
5243 (1<<15 | 1<<9 | 7<<0));
5244 DP(NETIF_MSG_LINK, "Setting 100M force\n");
5245 }
5246 if (phy->req_line_speed == SPEED_10) {
5247 /* Enabled AUTO-MDIX when autoneg is disabled */
5248 bnx2x_cl45_write(bp, phy,
5249 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
5250 (1<<15 | 1<<9 | 7<<0));
5251 DP(NETIF_MSG_LINK, "Setting 10M force\n");
5252 }
b7737c9b 5253
de6eae1f
YR		 5254 bnx2x_cl45_write(bp, phy,
5255 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
5256 an_10_100_val);
b7737c9b 5257
de6eae1f
YR		 5258 if (phy->req_duplex == DUPLEX_FULL)
5259 autoneg_val |= (1<<8);
b7737c9b 5260
de6eae1f
YR		 5261 bnx2x_cl45_write(bp, phy,
5262 MDIO_AN_DEVAD,
5263 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
b7737c9b 5264
de6eae1f
YR		 5265 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5266 (phy->speed_cap_mask &
5267 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
5268 (phy->req_line_speed == SPEED_10000)) {
5269 DP(NETIF_MSG_LINK, "Advertising 10G\n");
5270 /* Restart autoneg for 10G*/
5271
5272 bnx2x_cl45_write(bp, phy,
5273 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
5274 0x3200);
5275 } else if (phy->req_line_speed != SPEED_10 &&
5276 phy->req_line_speed != SPEED_100) {
5277 bnx2x_cl45_write(bp, phy,
5278 MDIO_AN_DEVAD,
5279 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
5280 1);
b7737c9b 5281 }
de6eae1f
YR		 5282 /* Save spirom version */
5283 bnx2x_save_848xx_spirom_version(phy, params);
5284
5285 return 0;
b7737c9b
YR		 5286}
5287
de6eae1f
YR		 5288static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
5289 struct link_params *params,
5290 struct link_vars *vars)
ea4e040a
YR		 5291{
5292 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5293 /* Restore normal power mode*/
5294 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5295 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 5296
de6eae1f
YR		 5297 /* HW reset */
5298 bnx2x_ext_phy_hw_reset(bp, params->port);
ab6ad5a4 5299
de6eae1f
YR		 5300 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5301 return bnx2x_848xx_cmn_config_init(phy, params, vars);
5302}
ea4e040a 5303
de6eae1f
YR		 5304static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
5305 struct link_params *params,
5306 struct link_vars *vars)
5307{
5308 struct bnx2x *bp = params->bp;
a22f0788
YR		 5309 u8 initialize = 1;
5310 u16 val;
de6eae1f 5311 u16 temp;
a22f0788
YR		 5312 u32 actual_phy_selection;
5313 u8 rc = 0;
de6eae1f
YR		 5314 msleep(1);
5315 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5316 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
5317 params->port);
5318 msleep(200); /* 100 is not enough */
ea4e040a 5319
de6eae1f
YR		 5320 /**
5321 * BCM84823 requires that XGXS links up first @ 10G for normal
5322 * behavior
5323 */
5324 temp = vars->line_speed;
5325 vars->line_speed = SPEED_10000;
a22f0788
YR		 5326 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
5327 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
de6eae1f 5328 vars->line_speed = temp;
a22f0788
YR		 5329
5330 /* Set dual-media configuration according to configuration */
5331
5332 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
5333 MDIO_CTL_REG_84823_MEDIA, &val);
5334 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
5335 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
5336 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
5337 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
5338 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
5339 val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
5340 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
5341
5342 actual_phy_selection = bnx2x_phy_selection(params);
5343
5344 switch (actual_phy_selection) {
5345 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
5346 /* Do nothing. Essentialy this is like the priority copper */
5347 break;
5348 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
5349 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
5350 break;
5351 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
5352 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
5353 break;
5354 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
5355 /* Do nothing here. The first PHY won't be initialized at all */
5356 break;
5357 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
5358 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
5359 initialize = 0;
5360 break;
5361 }
5362 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
5363 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
5364
5365 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
5366 MDIO_CTL_REG_84823_MEDIA, val);
5367 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
5368 params->multi_phy_config, val);
5369
5370 if (initialize)
5371 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
5372 else
5373 bnx2x_save_848xx_spirom_version(phy, params);
5374 return rc;
de6eae1f 5375}
ea4e040a 5376
de6eae1f
YR		 5377static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
5378 struct link_params *params,
5379 struct link_vars *vars)
5380{
5381 struct bnx2x *bp = params->bp;
5382 u16 val, val1, val2;
5383 u8 link_up = 0;
ea4e040a 5384
de6eae1f
YR		 5385 /* Check 10G-BaseT link status */
5386 /* Check PMD signal ok */
5387 bnx2x_cl45_read(bp, phy,
5388 MDIO_AN_DEVAD, 0xFFFA, &val1);
5389 bnx2x_cl45_read(bp, phy,
5390 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
5391 &val2);
5392 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
ea4e040a 5393
de6eae1f
YR		 5394 /* Check link 10G */
5395 if (val2 & (1<<11)) {
ea4e040a 5396 vars->line_speed = SPEED_10000;
de6eae1f
YR		 5397 link_up = 1;
5398 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
5399 } else { /* Check Legacy speed link */
5400 u16 legacy_status, legacy_speed;
ea4e040a 5401
de6eae1f
YR		 5402 /* Enable expansion register 0x42 (Operation mode status) */
5403 bnx2x_cl45_write(bp, phy,
5404 MDIO_AN_DEVAD,
5405 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
ea4e040a 5406
de6eae1f
YR		 5407 /* Get legacy speed operation status */
5408 bnx2x_cl45_read(bp, phy,
5409 MDIO_AN_DEVAD,
5410 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5411 &legacy_status);
ea4e040a 5412
de6eae1f
YR		 5413 DP(NETIF_MSG_LINK, "Legacy speed status"
5414 " = 0x%x\n", legacy_status);
5415 link_up = ((legacy_status & (1<<11)) == (1<<11));
5416 if (link_up) {
5417 legacy_speed = (legacy_status & (3<<9));
5418 if (legacy_speed == (0<<9))
5419 vars->line_speed = SPEED_10;
5420 else if (legacy_speed == (1<<9))
5421 vars->line_speed = SPEED_100;
5422 else if (legacy_speed == (2<<9))
5423 vars->line_speed = SPEED_1000;
5424 else /* Should not happen */
5425 vars->line_speed = 0;
ea4e040a 5426
de6eae1f
YR		 5427 if (legacy_status & (1<<8))
5428 vars->duplex = DUPLEX_FULL;
5429 else
5430 vars->duplex = DUPLEX_HALF;
ea4e040a 5431
de6eae1f
YR		 5432 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
5433 " is_duplex_full= %d\n", vars->line_speed,
5434 (vars->duplex == DUPLEX_FULL));
5435 /* Check legacy speed AN resolution */
5436 bnx2x_cl45_read(bp, phy,
5437 MDIO_AN_DEVAD,
5438 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
5439 &val);
5440 if (val & (1<<5))
5441 vars->link_status |=
5442 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5443 bnx2x_cl45_read(bp, phy,
5444 MDIO_AN_DEVAD,
5445 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
5446 &val);
5447 if ((val & (1<<0)) == 0)
5448 vars->link_status |=
5449 LINK_STATUS_PARALLEL_DETECTION_USED;
ea4e040a 5450 }
ea4e040a 5451 }
de6eae1f
YR		 5452 if (link_up) {
5453 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
5454 vars->line_speed);
5455 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5456 }
589abe3a 5457
de6eae1f 5458 return link_up;
b7737c9b
YR		 5459}
5460
de6eae1f 5461static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
b7737c9b 5462{
de6eae1f
YR		 5463 u8 status = 0;
5464 u32 spirom_ver;
5465 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
5466 status = bnx2x_format_ver(spirom_ver, str, len);
5467 return status;
b7737c9b 5468}
de6eae1f
YR		 5469
5470static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
5471 struct link_params *params)
b7737c9b 5472{
de6eae1f
YR		 5473 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5474 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
5475 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5476 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
b7737c9b 5477}
de6eae1f 5478
b7737c9b
YR		 5479static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
5480 struct link_params *params)
5481{
5482 bnx2x_cl45_write(params->bp, phy,
5483 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
5484 bnx2x_cl45_write(params->bp, phy,
5485 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
5486}
5487
5488static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
5489 struct link_params *params)
5490{
5491 struct bnx2x *bp = params->bp;
5492 u8 port = params->port;
5493 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5494 MISC_REGISTERS_GPIO_OUTPUT_LOW,
5495 port);
5496}
5497
de6eae1f
YR		 5498/******************************************************************/
5499/* SFX7101 PHY SECTION */
5500/******************************************************************/
5501static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
5502 struct link_params *params)
b7737c9b
YR		 5503{
5504 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5505 /* SFX7101_XGXS_TEST1 */
5506 bnx2x_cl45_write(bp, phy,
5507 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
589abe3a
EG		 5508}
5509
de6eae1f
YR		 5510static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
5511 struct link_params *params,
5512 struct link_vars *vars)
ea4e040a 5513{
de6eae1f 5514 u16 fw_ver1, fw_ver2, val;
ea4e040a 5515 struct bnx2x *bp = params->bp;
de6eae1f 5516 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
ea4e040a 5517
de6eae1f
YR		 5518 /* Restore normal power mode*/
5519 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5520 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5521 /* HW reset */
5522 bnx2x_ext_phy_hw_reset(bp, params->port);
5523 bnx2x_wait_reset_complete(bp, phy);
ea4e040a 5524
de6eae1f
YR		 5525 bnx2x_cl45_write(bp, phy,
5526 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
5527 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
5528 bnx2x_cl45_write(bp, phy,
5529 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
ea4e040a 5530
de6eae1f
YR		 5531 bnx2x_ext_phy_set_pause(params, phy, vars);
5532 /* Restart autoneg */
5533 bnx2x_cl45_read(bp, phy,
5534 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
5535 val |= 0x200;
5536 bnx2x_cl45_write(bp, phy,
5537 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
ea4e040a 5538
de6eae1f
YR		 5539 /* Save spirom version */
5540 bnx2x_cl45_read(bp, phy,
5541 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
ea4e040a 5542
de6eae1f
YR		 5543 bnx2x_cl45_read(bp, phy,
5544 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
5545 bnx2x_save_spirom_version(bp, params->port,
5546 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
5547 return 0;
5548}
ea4e040a 5549
de6eae1f
YR		 5550static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
5551 struct link_params *params,
5552 struct link_vars *vars)
57963ed9
YR		 5553{
5554 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5555 u8 link_up;
5556 u16 val1, val2;
5557 bnx2x_cl45_read(bp, phy,
5558 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5559 bnx2x_cl45_read(bp, phy,
5560 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5561 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
5562 val2, val1);
5563 bnx2x_cl45_read(bp, phy,
5564 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
5565 bnx2x_cl45_read(bp, phy,
5566 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
5567 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
5568 val2, val1);
5569 link_up = ((val1 & 4) == 4);
5570 /* if link is up
5571 * print the AN outcome of the SFX7101 PHY
5572 */
5573 if (link_up) {
5574 bnx2x_cl45_read(bp, phy,
5575 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
5576 &val2);
5577 vars->line_speed = SPEED_10000;
5578 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
5579 val2, (val2 & (1<<14)));
5580 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
5581 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5582 }
5583 return link_up;
5584}
6c55c3cd 5585
6c55c3cd 5586
de6eae1f
YR		 5587static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5588{
5589 if (*len < 5)
5590 return -EINVAL;
5591 str[0] = (spirom_ver & 0xFF);
5592 str[1] = (spirom_ver & 0xFF00) >> 8;
5593 str[2] = (spirom_ver & 0xFF0000) >> 16;
5594 str[3] = (spirom_ver & 0xFF000000) >> 24;
5595 str[4] = '\0';
5596 *len -= 5;
57963ed9
YR		 5597 return 0;
5598}
5599
de6eae1f 5600void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
57963ed9 5601{
de6eae1f 5602 u16 val, cnt;
7aa0711f 5603
de6eae1f
YR		 5604 bnx2x_cl45_read(bp, phy,
5605 MDIO_PMA_DEVAD,
5606 MDIO_PMA_REG_7101_RESET, &val);
57963ed9 5607
de6eae1f
YR		 5608 for (cnt = 0; cnt < 10; cnt++) {
5609 msleep(50);
5610 /* Writes a self-clearing reset */
5611 bnx2x_cl45_write(bp, phy,
5612 MDIO_PMA_DEVAD,
5613 MDIO_PMA_REG_7101_RESET,
5614 (val | (1<<15)));
5615 /* Wait for clear */
5616 bnx2x_cl45_read(bp, phy,
5617 MDIO_PMA_DEVAD,
5618 MDIO_PMA_REG_7101_RESET, &val);
0c786f02 5619
de6eae1f
YR		 5620 if ((val & (1<<15)) == 0)
5621 break;
57963ed9 5622 }
57963ed9 5623}
ea4e040a 5624
de6eae1f
YR		 5625static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
5626 struct link_params *params) {
5627 /* Low power mode is controlled by GPIO 2 */
5628 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
5629 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
5630 /* The PHY reset is controlled by GPIO 1 */
5631 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5632 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
5633}
ea4e040a 5634
de6eae1f
YR		 5635/******************************************************************/
5636/* STATIC PHY DECLARATION */
5637/******************************************************************/
ea4e040a 5638
de6eae1f
YR		 5639static struct bnx2x_phy phy_null = {
5640 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
5641 .addr = 0,
5642 .flags = FLAGS_INIT_XGXS_FIRST,
5643 .def_md_devad = 0,
5644 .reserved = 0,
5645 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5646 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5647 .mdio_ctrl = 0,
5648 .supported = 0,
5649 .media_type = ETH_PHY_NOT_PRESENT,
5650 .ver_addr = 0,
5651 .req_flow_ctrl = 0,
5652 .req_line_speed = 0,
5653 .speed_cap_mask = 0,
5654 .req_duplex = 0,
5655 .rsrv = 0,
5656 .config_init = (config_init_t)NULL,
5657 .read_status = (read_status_t)NULL,
5658 .link_reset = (link_reset_t)NULL,
5659 .config_loopback = (config_loopback_t)NULL,
5660 .format_fw_ver = (format_fw_ver_t)NULL,
5661 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5662 .set_link_led = (set_link_led_t)NULL,
5663 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 5664};
ea4e040a 5665
de6eae1f
YR		 5666static struct bnx2x_phy phy_serdes = {
5667 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
5668 .addr = 0xff,
5669 .flags = 0,
5670 .def_md_devad = 0,
5671 .reserved = 0,
5672 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5673 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5674 .mdio_ctrl = 0,
5675 .supported = (SUPPORTED_10baseT_Half |
5676 SUPPORTED_10baseT_Full |
5677 SUPPORTED_100baseT_Half |
5678 SUPPORTED_100baseT_Full |
5679 SUPPORTED_1000baseT_Full |
5680 SUPPORTED_2500baseX_Full |
5681 SUPPORTED_TP |
5682 SUPPORTED_Autoneg |
5683 SUPPORTED_Pause |
5684 SUPPORTED_Asym_Pause),
5685 .media_type = ETH_PHY_UNSPECIFIED,
5686 .ver_addr = 0,
5687 .req_flow_ctrl = 0,
5688 .req_line_speed = 0,
5689 .speed_cap_mask = 0,
5690 .req_duplex = 0,
5691 .rsrv = 0,
5692 .config_init = (config_init_t)bnx2x_init_serdes,
5693 .read_status = (read_status_t)bnx2x_link_settings_status,
5694 .link_reset = (link_reset_t)bnx2x_int_link_reset,
5695 .config_loopback = (config_loopback_t)NULL,
5696 .format_fw_ver = (format_fw_ver_t)NULL,
5697 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5698 .set_link_led = (set_link_led_t)NULL,
5699 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 5700};
b7737c9b
YR		 5701
5702static struct bnx2x_phy phy_xgxs = {
5703 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
5704 .addr = 0xff,
5705 .flags = 0,
5706 .def_md_devad = 0,
5707 .reserved = 0,
5708 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5709 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5710 .mdio_ctrl = 0,
5711 .supported = (SUPPORTED_10baseT_Half |
5712 SUPPORTED_10baseT_Full |
5713 SUPPORTED_100baseT_Half |
5714 SUPPORTED_100baseT_Full |
5715 SUPPORTED_1000baseT_Full |
5716 SUPPORTED_2500baseX_Full |
5717 SUPPORTED_10000baseT_Full |
5718 SUPPORTED_FIBRE |
5719 SUPPORTED_Autoneg |
5720 SUPPORTED_Pause |
5721 SUPPORTED_Asym_Pause),
5722 .media_type = ETH_PHY_UNSPECIFIED,
5723 .ver_addr = 0,
5724 .req_flow_ctrl = 0,
5725 .req_line_speed = 0,
5726 .speed_cap_mask = 0,
5727 .req_duplex = 0,
5728 .rsrv = 0,
5729 .config_init = (config_init_t)bnx2x_init_xgxs,
5730 .read_status = (read_status_t)bnx2x_link_settings_status,
5731 .link_reset = (link_reset_t)bnx2x_int_link_reset,
5732 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
5733 .format_fw_ver = (format_fw_ver_t)NULL,
5734 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5735 .set_link_led = (set_link_led_t)NULL,
5736 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 5737};
5738
5739static struct bnx2x_phy phy_7101 = {
5740 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
5741 .addr = 0xff,
5742 .flags = FLAGS_FAN_FAILURE_DET_REQ,
5743 .def_md_devad = 0,
5744 .reserved = 0,
5745 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5746 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5747 .mdio_ctrl = 0,
5748 .supported = (SUPPORTED_10000baseT_Full |
5749 SUPPORTED_TP |
5750 SUPPORTED_Autoneg |
5751 SUPPORTED_Pause |
5752 SUPPORTED_Asym_Pause),
5753 .media_type = ETH_PHY_BASE_T,
5754 .ver_addr = 0,
5755 .req_flow_ctrl = 0,
5756 .req_line_speed = 0,
5757 .speed_cap_mask = 0,
5758 .req_duplex = 0,
5759 .rsrv = 0,
5760 .config_init = (config_init_t)bnx2x_7101_config_init,
5761 .read_status = (read_status_t)bnx2x_7101_read_status,
5762 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
5763 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
5764 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
5765 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
a22f0788
YR		 5766 .set_link_led = (set_link_led_t)NULL,
5767 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 5768};
5769static struct bnx2x_phy phy_8073 = {
5770 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
5771 .addr = 0xff,
5772 .flags = FLAGS_HW_LOCK_REQUIRED,
5773 .def_md_devad = 0,
5774 .reserved = 0,
5775 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5776 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5777 .mdio_ctrl = 0,
5778 .supported = (SUPPORTED_10000baseT_Full |
5779 SUPPORTED_2500baseX_Full |
5780 SUPPORTED_1000baseT_Full |
5781 SUPPORTED_FIBRE |
5782 SUPPORTED_Autoneg |
5783 SUPPORTED_Pause |
5784 SUPPORTED_Asym_Pause),
5785 .media_type = ETH_PHY_UNSPECIFIED,
5786 .ver_addr = 0,
5787 .req_flow_ctrl = 0,
5788 .req_line_speed = 0,
5789 .speed_cap_mask = 0,
5790 .req_duplex = 0,
5791 .rsrv = 0,
62b29a5d 5792 .config_init = (config_init_t)bnx2x_8073_config_init,
b7737c9b
YR		 5793 .read_status = (read_status_t)bnx2x_8073_read_status,
5794 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
5795 .config_loopback = (config_loopback_t)NULL,
5796 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5797 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5798 .set_link_led = (set_link_led_t)NULL,
5799 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 5800};
5801static struct bnx2x_phy phy_8705 = {
5802 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
5803 .addr = 0xff,
5804 .flags = FLAGS_INIT_XGXS_FIRST,
5805 .def_md_devad = 0,
5806 .reserved = 0,
5807 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5808 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5809 .mdio_ctrl = 0,
5810 .supported = (SUPPORTED_10000baseT_Full |
5811 SUPPORTED_FIBRE |
5812 SUPPORTED_Pause |
5813 SUPPORTED_Asym_Pause),
5814 .media_type = ETH_PHY_XFP_FIBER,
5815 .ver_addr = 0,
5816 .req_flow_ctrl = 0,
5817 .req_line_speed = 0,
5818 .speed_cap_mask = 0,
5819 .req_duplex = 0,
5820 .rsrv = 0,
5821 .config_init = (config_init_t)bnx2x_8705_config_init,
5822 .read_status = (read_status_t)bnx2x_8705_read_status,
5823 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
5824 .config_loopback = (config_loopback_t)NULL,
5825 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
5826 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5827 .set_link_led = (set_link_led_t)NULL,
5828 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 5829};
5830static struct bnx2x_phy phy_8706 = {
5831 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
5832 .addr = 0xff,
5833 .flags = FLAGS_INIT_XGXS_FIRST,
5834 .def_md_devad = 0,
5835 .reserved = 0,
5836 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5837 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5838 .mdio_ctrl = 0,
5839 .supported = (SUPPORTED_10000baseT_Full |
5840 SUPPORTED_1000baseT_Full |
5841 SUPPORTED_FIBRE |
5842 SUPPORTED_Pause |
5843 SUPPORTED_Asym_Pause),
5844 .media_type = ETH_PHY_SFP_FIBER,
5845 .ver_addr = 0,
5846 .req_flow_ctrl = 0,
5847 .req_line_speed = 0,
5848 .speed_cap_mask = 0,
5849 .req_duplex = 0,
5850 .rsrv = 0,
5851 .config_init = (config_init_t)bnx2x_8706_config_init,
5852 .read_status = (read_status_t)bnx2x_8706_read_status,
5853 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
5854 .config_loopback = (config_loopback_t)NULL,
5855 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5856 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5857 .set_link_led = (set_link_led_t)NULL,
5858 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 5859};
5860
5861static struct bnx2x_phy phy_8726 = {
5862 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
5863 .addr = 0xff,
5864 .flags = (FLAGS_HW_LOCK_REQUIRED |
5865 FLAGS_INIT_XGXS_FIRST),
5866 .def_md_devad = 0,
5867 .reserved = 0,
5868 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5869 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5870 .mdio_ctrl = 0,
5871 .supported = (SUPPORTED_10000baseT_Full |
5872 SUPPORTED_1000baseT_Full |
5873 SUPPORTED_Autoneg |
5874 SUPPORTED_FIBRE |
5875 SUPPORTED_Pause |
5876 SUPPORTED_Asym_Pause),
5877 .media_type = ETH_PHY_SFP_FIBER,
5878 .ver_addr = 0,
5879 .req_flow_ctrl = 0,
5880 .req_line_speed = 0,
5881 .speed_cap_mask = 0,
5882 .req_duplex = 0,
5883 .rsrv = 0,
5884 .config_init = (config_init_t)bnx2x_8726_config_init,
5885 .read_status = (read_status_t)bnx2x_8726_read_status,
5886 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
5887 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
5888 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5889 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5890 .set_link_led = (set_link_led_t)NULL,
5891 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 5892};
5893
5894static struct bnx2x_phy phy_8727 = {
5895 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
5896 .addr = 0xff,
5897 .flags = FLAGS_FAN_FAILURE_DET_REQ,
5898 .def_md_devad = 0,
5899 .reserved = 0,
5900 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5901 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5902 .mdio_ctrl = 0,
5903 .supported = (SUPPORTED_10000baseT_Full |
5904 SUPPORTED_1000baseT_Full |
b7737c9b
YR		 5905 SUPPORTED_FIBRE |
5906 SUPPORTED_Pause |
5907 SUPPORTED_Asym_Pause),
5908 .media_type = ETH_PHY_SFP_FIBER,
5909 .ver_addr = 0,
5910 .req_flow_ctrl = 0,
5911 .req_line_speed = 0,
5912 .speed_cap_mask = 0,
5913 .req_duplex = 0,
5914 .rsrv = 0,
5915 .config_init = (config_init_t)bnx2x_8727_config_init,
5916 .read_status = (read_status_t)bnx2x_8727_read_status,
5917 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
5918 .config_loopback = (config_loopback_t)NULL,
5919 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5920 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
a22f0788
YR		 5921 .set_link_led = (set_link_led_t)NULL,
5922 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
b7737c9b
YR		 5923};
5924static struct bnx2x_phy phy_8481 = {
5925 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
5926 .addr = 0xff,
a22f0788
YR		 5927 .flags = FLAGS_FAN_FAILURE_DET_REQ |
5928 FLAGS_REARM_LATCH_SIGNAL,
b7737c9b
YR		 5929 .def_md_devad = 0,
5930 .reserved = 0,
5931 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5932 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5933 .mdio_ctrl = 0,
5934 .supported = (SUPPORTED_10baseT_Half |
5935 SUPPORTED_10baseT_Full |
5936 SUPPORTED_100baseT_Half |
5937 SUPPORTED_100baseT_Full |
5938 SUPPORTED_1000baseT_Full |
5939 SUPPORTED_10000baseT_Full |
5940 SUPPORTED_TP |
5941 SUPPORTED_Autoneg |
5942 SUPPORTED_Pause |
5943 SUPPORTED_Asym_Pause),
5944 .media_type = ETH_PHY_BASE_T,
5945 .ver_addr = 0,
5946 .req_flow_ctrl = 0,
5947 .req_line_speed = 0,
5948 .speed_cap_mask = 0,
5949 .req_duplex = 0,
5950 .rsrv = 0,
5951 .config_init = (config_init_t)bnx2x_8481_config_init,
5952 .read_status = (read_status_t)bnx2x_848xx_read_status,
5953 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
5954 .config_loopback = (config_loopback_t)NULL,
5955 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
5956 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
a22f0788
YR		 5957 .set_link_led = (set_link_led_t)NULL,
5958 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 5959};
5960
de6eae1f
YR		 5961static struct bnx2x_phy phy_84823 = {
5962 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
5963 .addr = 0xff,
a22f0788
YR		 5964 .flags = FLAGS_FAN_FAILURE_DET_REQ |
5965 FLAGS_REARM_LATCH_SIGNAL,
de6eae1f
YR		 5966 .def_md_devad = 0,
5967 .reserved = 0,
5968 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5969 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5970 .mdio_ctrl = 0,
5971 .supported = (SUPPORTED_10baseT_Half |
5972 SUPPORTED_10baseT_Full |
5973 SUPPORTED_100baseT_Half |
5974 SUPPORTED_100baseT_Full |
5975 SUPPORTED_1000baseT_Full |
5976 SUPPORTED_10000baseT_Full |
5977 SUPPORTED_TP |
5978 SUPPORTED_Autoneg |
5979 SUPPORTED_Pause |
5980 SUPPORTED_Asym_Pause),
5981 .media_type = ETH_PHY_BASE_T,
5982 .ver_addr = 0,
5983 .req_flow_ctrl = 0,
5984 .req_line_speed = 0,
5985 .speed_cap_mask = 0,
5986 .req_duplex = 0,
5987 .rsrv = 0,
5988 .config_init = (config_init_t)bnx2x_848x3_config_init,
5989 .read_status = (read_status_t)bnx2x_848xx_read_status,
5990 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
5991 .config_loopback = (config_loopback_t)NULL,
5992 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
5993 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 5994 .set_link_led = (set_link_led_t)NULL,
5995 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f
YR		 5996};
5997
5998/*****************************************************************/
5999/* */
6000/* Populate the phy according. Main function: bnx2x_populate_phy */
6001/* */
6002/*****************************************************************/
6003
6004static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
6005 struct bnx2x_phy *phy, u8 port,
6006 u8 phy_index)
6007{
6008 /* Get the 4 lanes xgxs config rx and tx */
6009 u32 rx = 0, tx = 0, i;
6010 for (i = 0; i < 2; i++) {
6011 /**
6012 * INT_PHY and EXT_PHY1 share the same value location in the
6013 * shmem. When num_phys is greater than 1, than this value
6014 * applies only to EXT_PHY1
6015 */
a22f0788
YR		 6016 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
6017 rx = REG_RD(bp, shmem_base +
6018 offsetof(struct shmem_region,
6019 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
6020
6021 tx = REG_RD(bp, shmem_base +
6022 offsetof(struct shmem_region,
6023 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
6024 } else {
6025 rx = REG_RD(bp, shmem_base +
6026 offsetof(struct shmem_region,
6027 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
de6eae1f 6028
a22f0788
YR		 6029 tx = REG_RD(bp, shmem_base +
6030 offsetof(struct shmem_region,
6031 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
6032 }
de6eae1f
YR		 6033
6034 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
6035 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
6036
6037 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
6038 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
6039 }
6040}
6041
6042static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
6043 u8 phy_index, u8 port)
6044{
6045 u32 ext_phy_config = 0;
6046 switch (phy_index) {
6047 case EXT_PHY1:
6048 ext_phy_config = REG_RD(bp, shmem_base +
6049 offsetof(struct shmem_region,
6050 dev_info.port_hw_config[port].external_phy_config));
6051 break;
a22f0788
YR		 6052 case EXT_PHY2:
6053 ext_phy_config = REG_RD(bp, shmem_base +
6054 offsetof(struct shmem_region,
6055 dev_info.port_hw_config[port].external_phy_config2));
6056 break;
de6eae1f
YR		 6057 default:
6058 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
6059 return -EINVAL;
6060 }
6061
6062 return ext_phy_config;
6063}
6064static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
6065 struct bnx2x_phy *phy)
6066{
6067 u32 phy_addr;
6068 u32 chip_id;
6069 u32 switch_cfg = (REG_RD(bp, shmem_base +
6070 offsetof(struct shmem_region,
6071 dev_info.port_feature_config[port].link_config)) &
6072 PORT_FEATURE_CONNECTED_SWITCH_MASK);
6073 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
6074 switch (switch_cfg) {
6075 case SWITCH_CFG_1G:
6076 phy_addr = REG_RD(bp,
6077 NIG_REG_SERDES0_CTRL_PHY_ADDR +
6078 port * 0x10);
6079 *phy = phy_serdes;
6080 break;
6081 case SWITCH_CFG_10G:
6082 phy_addr = REG_RD(bp,
6083 NIG_REG_XGXS0_CTRL_PHY_ADDR +
6084 port * 0x18);
6085 *phy = phy_xgxs;
6086 break;
6087 default:
6088 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6089 return -EINVAL;
6090 }
6091 phy->addr = (u8)phy_addr;
6092 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
6093 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
6094 port);
6095 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
6096
6097 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
6098 port, phy->addr, phy->mdio_ctrl);
6099
6100 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
6101 return 0;
6102}
6103
6104static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
6105 u8 phy_index,
6106 u32 shmem_base,
a22f0788 6107 u32 shmem2_base,
de6eae1f
YR		 6108 u8 port,
6109 struct bnx2x_phy *phy)
6110{
6111 u32 ext_phy_config, phy_type, config2;
6112 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
6113 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
6114 phy_index, port);
6115 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6116 /* Select the phy type */
6117 switch (phy_type) {
6118 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6119 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
6120 *phy = phy_8073;
6121 break;
6122 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6123 *phy = phy_8705;
6124 break;
6125 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6126 *phy = phy_8706;
6127 break;
6128 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6129 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
6130 *phy = phy_8726;
6131 break;
6132 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6133 /* BCM8727_NOC => BCM8727 no over current */
6134 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
6135 *phy = phy_8727;
6136 phy->flags |= FLAGS_NOC;
6137 break;
6138 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6139 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
6140 *phy = phy_8727;
6141 break;
6142 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
6143 *phy = phy_8481;
6144 break;
6145 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6146 *phy = phy_84823;
6147 break;
6148 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6149 *phy = phy_7101;
6150 break;
6151 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6152 *phy = phy_null;
6153 return -EINVAL;
6154 default:
6155 *phy = phy_null;
6156 return 0;
6157 }
6158
6159 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
6160 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
6161
6162 /**
6163 * The shmem address of the phy version is located on different
6164 * structures. In case this structure is too old, do not set
6165 * the address
6166 */
6167 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
6168 dev_info.shared_hw_config.config2));
a22f0788
YR		 6169 if (phy_index == EXT_PHY1) {
6170 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
6171 port_mb[port].ext_phy_fw_version);
de6eae1f
YR		 6172
6173 /* Check specific mdc mdio settings */
6174 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
6175 mdc_mdio_access = config2 &
6176 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
a22f0788
YR		 6177 } else {
6178 u32 size = REG_RD(bp, shmem2_base);
de6eae1f 6179
a22f0788
YR		 6180 if (size >
6181 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
6182 phy->ver_addr = shmem2_base +
6183 offsetof(struct shmem2_region,
6184 ext_phy_fw_version2[port]);
6185 }
6186 /* Check specific mdc mdio settings */
6187 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
6188 mdc_mdio_access = (config2 &
6189 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
6190 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
6191 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
6192 }
de6eae1f
YR		 6193 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
6194
6195 /**
6196 * In case mdc/mdio_access of the external phy is different than the
6197 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
6198 * to prevent one port interfere with another port's CL45 operations.
6199 */
6200 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
6201 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
6202 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
6203 phy_type, port, phy_index);
6204 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
6205 phy->addr, phy->mdio_ctrl);
6206 return 0;
6207}
6208
6209static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
a22f0788 6210 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
de6eae1f
YR		 6211{
6212 u8 status = 0;
6213 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
6214 if (phy_index == INT_PHY)
6215 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
a22f0788 6216 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 6217 port, phy);
6218 return status;
6219}
6220
6221static void bnx2x_phy_def_cfg(struct link_params *params,
6222 struct bnx2x_phy *phy,
a22f0788 6223 u8 phy_index)
de6eae1f
YR		 6224{
6225 struct bnx2x *bp = params->bp;
6226 u32 link_config;
6227 /* Populate the default phy configuration for MF mode */
a22f0788
YR		 6228 if (phy_index == EXT_PHY2) {
6229 link_config = REG_RD(bp, params->shmem_base +
6230 offsetof(struct shmem_region, dev_info.
6231 port_feature_config[params->port].link_config2));
6232 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
6233 offsetof(struct shmem_region, dev_info.
6234 port_hw_config[params->port].speed_capability_mask2));
6235 } else {
6236 link_config = REG_RD(bp, params->shmem_base +
6237 offsetof(struct shmem_region, dev_info.
6238 port_feature_config[params->port].link_config));
6239 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
de6eae1f 6240 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 6241 port_hw_config[params->port].speed_capability_mask));
6242 }
6243 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
6244 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
de6eae1f
YR		 6245
6246 phy->req_duplex = DUPLEX_FULL;
6247 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
6248 case PORT_FEATURE_LINK_SPEED_10M_HALF:
6249 phy->req_duplex = DUPLEX_HALF;
6250 case PORT_FEATURE_LINK_SPEED_10M_FULL:
6251 phy->req_line_speed = SPEED_10;
6252 break;
6253 case PORT_FEATURE_LINK_SPEED_100M_HALF:
6254 phy->req_duplex = DUPLEX_HALF;
6255 case PORT_FEATURE_LINK_SPEED_100M_FULL:
6256 phy->req_line_speed = SPEED_100;
6257 break;
6258 case PORT_FEATURE_LINK_SPEED_1G:
6259 phy->req_line_speed = SPEED_1000;
6260 break;
6261 case PORT_FEATURE_LINK_SPEED_2_5G:
6262 phy->req_line_speed = SPEED_2500;
6263 break;
6264 case PORT_FEATURE_LINK_SPEED_10G_CX4:
6265 phy->req_line_speed = SPEED_10000;
6266 break;
6267 default:
6268 phy->req_line_speed = SPEED_AUTO_NEG;
6269 break;
6270 }
6271
6272 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
6273 case PORT_FEATURE_FLOW_CONTROL_AUTO:
6274 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
6275 break;
6276 case PORT_FEATURE_FLOW_CONTROL_TX:
6277 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
6278 break;
6279 case PORT_FEATURE_FLOW_CONTROL_RX:
6280 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
6281 break;
6282 case PORT_FEATURE_FLOW_CONTROL_BOTH:
6283 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
6284 break;
6285 default:
6286 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6287 break;
6288 }
6289}
6290
a22f0788
YR		 6291u32 bnx2x_phy_selection(struct link_params *params)
6292{
6293 u32 phy_config_swapped, prio_cfg;
6294 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
6295
6296 phy_config_swapped = params->multi_phy_config &
6297 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
6298
6299 prio_cfg = params->multi_phy_config &
6300 PORT_HW_CFG_PHY_SELECTION_MASK;
6301
6302 if (phy_config_swapped) {
6303 switch (prio_cfg) {
6304 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6305 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
6306 break;
6307 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6308 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
6309 break;
6310 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6311 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
6312 break;
6313 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6314 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
6315 break;
6316 }
6317 } else
6318 return_cfg = prio_cfg;
6319
6320 return return_cfg;
6321}
6322
6323
de6eae1f
YR		 6324u8 bnx2x_phy_probe(struct link_params *params)
6325{
6326 u8 phy_index, actual_phy_idx, link_cfg_idx;
a22f0788 6327 u32 phy_config_swapped;
de6eae1f
YR		 6328 struct bnx2x *bp = params->bp;
6329 struct bnx2x_phy *phy;
6330 params->num_phys = 0;
6331 DP(NETIF_MSG_LINK, "Begin phy probe\n");
a22f0788
YR		 6332 phy_config_swapped = params->multi_phy_config &
6333 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 6334
6335 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
6336 phy_index++) {
6337 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
6338 actual_phy_idx = phy_index;
a22f0788
YR		 6339 if (phy_config_swapped) {
6340 if (phy_index == EXT_PHY1)
6341 actual_phy_idx = EXT_PHY2;
6342 else if (phy_index == EXT_PHY2)
6343 actual_phy_idx = EXT_PHY1;
6344 }
6345 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
6346 " actual_phy_idx %x\n", phy_config_swapped,
6347 phy_index, actual_phy_idx);
de6eae1f
YR		 6348 phy = &params->phy[actual_phy_idx];
6349 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
a22f0788 6350 params->shmem2_base, params->port,
de6eae1f
YR		 6351 phy) != 0) {
6352 params->num_phys = 0;
6353 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
6354 phy_index);
6355 for (phy_index = INT_PHY;
6356 phy_index < MAX_PHYS;
6357 phy_index++)
6358 *phy = phy_null;
6359 return -EINVAL;
6360 }
6361 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
6362 break;
6363
a22f0788 6364 bnx2x_phy_def_cfg(params, phy, phy_index);
de6eae1f
YR		 6365 params->num_phys++;
6366 }
6367
6368 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
6369 return 0;
6370}
6371
6372u32 bnx2x_supported_attr(struct link_params *params, u8 phy_idx)
6373{
6374 if (phy_idx < params->num_phys)
6375 return params->phy[phy_idx].supported;
6376 return 0;
6377}
6378
6379static void set_phy_vars(struct link_params *params)
6380{
6381 struct bnx2x *bp = params->bp;
a22f0788
YR		 6382 u8 actual_phy_idx, phy_index, link_cfg_idx;
6383 u8 phy_config_swapped = params->multi_phy_config &
6384 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 6385 for (phy_index = INT_PHY; phy_index < params->num_phys;
6386 phy_index++) {
a22f0788 6387 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
de6eae1f 6388 actual_phy_idx = phy_index;
a22f0788
YR		 6389 if (phy_config_swapped) {
6390 if (phy_index == EXT_PHY1)
6391 actual_phy_idx = EXT_PHY2;
6392 else if (phy_index == EXT_PHY2)
6393 actual_phy_idx = EXT_PHY1;
6394 }
de6eae1f 6395 params->phy[actual_phy_idx].req_flow_ctrl =
a22f0788 6396 params->req_flow_ctrl[link_cfg_idx];
de6eae1f
YR		 6397
6398 params->phy[actual_phy_idx].req_line_speed =
a22f0788 6399 params->req_line_speed[link_cfg_idx];
de6eae1f
YR		 6400
6401 params->phy[actual_phy_idx].speed_cap_mask =
a22f0788 6402 params->speed_cap_mask[link_cfg_idx];
de6eae1f
YR		 6403
6404 params->phy[actual_phy_idx].req_duplex =
a22f0788 6405 params->req_duplex[link_cfg_idx];
de6eae1f
YR		 6406
6407 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
6408 " speed_cap_mask %x\n",
6409 params->phy[actual_phy_idx].req_flow_ctrl,
6410 params->phy[actual_phy_idx].req_line_speed,
6411 params->phy[actual_phy_idx].speed_cap_mask);
6412 }
6413}
6414
6415u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6416{
6417 struct bnx2x *bp = params->bp;
de6eae1f 6418 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
a22f0788
YR		 6419 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
6420 params->req_line_speed[0], params->req_flow_ctrl[0]);
6421 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
6422 params->req_line_speed[1], params->req_flow_ctrl[1]);
de6eae1f
YR		 6423 vars->link_status = 0;
6424 vars->phy_link_up = 0;
6425 vars->link_up = 0;
6426 vars->line_speed = 0;
6427 vars->duplex = DUPLEX_FULL;
6428 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6429 vars->mac_type = MAC_TYPE_NONE;
6430 vars->phy_flags = 0;
6431
6432 /* disable attentions */
6433 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
6434 (NIG_MASK_XGXS0_LINK_STATUS |
6435 NIG_MASK_XGXS0_LINK10G |
6436 NIG_MASK_SERDES0_LINK_STATUS |
6437 NIG_MASK_MI_INT));
6438
6439 bnx2x_emac_init(params, vars);
6440
6441 if (params->num_phys == 0) {
6442 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
6443 return -EINVAL;
6444 }
6445 set_phy_vars(params);
6446
6447 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
6448 if (CHIP_REV_IS_FPGA(bp)) {
6449
6450 vars->link_up = 1;
6451 vars->line_speed = SPEED_10000;
6452 vars->duplex = DUPLEX_FULL;
6453 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6454 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
6455 /* enable on E1.5 FPGA */
6456 if (CHIP_IS_E1H(bp)) {
6457 vars->flow_ctrl |=
6458 (BNX2X_FLOW_CTRL_TX |
6459 BNX2X_FLOW_CTRL_RX);
6460 vars->link_status |=
6461 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
6462 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
6463 }
6464
6465 bnx2x_emac_enable(params, vars, 0);
6466 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
6467 /* disable drain */
6468 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
6469
6470 /* update shared memory */
6471 bnx2x_update_mng(params, vars->link_status);
6472
6473 return 0;
6474
6475 } else
6476 if (CHIP_REV_IS_EMUL(bp)) {
6477
6478 vars->link_up = 1;
6479 vars->line_speed = SPEED_10000;
6480 vars->duplex = DUPLEX_FULL;
6481 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6482 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
6483
6484 bnx2x_bmac_enable(params, vars, 0);
6485
6486 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
6487 /* Disable drain */
6488 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
6489 + params->port*4, 0);
6490
6491 /* update shared memory */
6492 bnx2x_update_mng(params, vars->link_status);
6493
6494 return 0;
6495
6496 } else
6497 if (params->loopback_mode == LOOPBACK_BMAC) {
6498
6499 vars->link_up = 1;
6500 vars->line_speed = SPEED_10000;
6501 vars->duplex = DUPLEX_FULL;
6502 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6503 vars->mac_type = MAC_TYPE_BMAC;
b7737c9b 6504
de6eae1f 6505 vars->phy_flags = PHY_XGXS_FLAG;
b7737c9b 6506
de6eae1f 6507 bnx2x_xgxs_deassert(params);
b7737c9b 6508
de6eae1f
YR		 6509 /* set bmac loopback */
6510 bnx2x_bmac_enable(params, vars, 1);
b7737c9b 6511
de6eae1f
YR		 6512 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6513 params->port*4, 0);
b7737c9b 6514
de6eae1f 6515 } else if (params->loopback_mode == LOOPBACK_EMAC) {
b7737c9b 6516
de6eae1f
YR		 6517 vars->link_up = 1;
6518 vars->line_speed = SPEED_1000;
6519 vars->duplex = DUPLEX_FULL;
6520 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6521 vars->mac_type = MAC_TYPE_EMAC;
b7737c9b 6522
de6eae1f 6523 vars->phy_flags = PHY_XGXS_FLAG;
e10bc84d 6524
de6eae1f
YR		 6525 bnx2x_xgxs_deassert(params);
6526 /* set bmac loopback */
6527 bnx2x_emac_enable(params, vars, 1);
6528 bnx2x_emac_program(params, vars);
6529 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6530 params->port*4, 0);
b7737c9b 6531
de6eae1f
YR		 6532 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
6533 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
b7737c9b 6534
de6eae1f 6535 vars->link_up = 1;
de6eae1f 6536 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
a22f0788
YR		 6537 vars->duplex = DUPLEX_FULL;
6538 if (params->req_line_speed[0] == SPEED_1000) {
6539 vars->line_speed = SPEED_1000;
6540 vars->mac_type = MAC_TYPE_EMAC;
6541 } else {
6542 vars->line_speed = SPEED_10000;
6543 vars->mac_type = MAC_TYPE_BMAC;
6544 }
62b29a5d 6545
de6eae1f
YR		 6546 bnx2x_xgxs_deassert(params);
6547 bnx2x_link_initialize(params, vars);
c18aa15d 6548
a22f0788
YR		 6549 if (params->req_line_speed[0] == SPEED_1000) {
6550 bnx2x_emac_program(params, vars);
6551 bnx2x_emac_enable(params, vars, 0);
6552 } else
de6eae1f 6553 bnx2x_bmac_enable(params, vars, 0);
c18aa15d 6554
de6eae1f
YR		 6555 if (params->loopback_mode == LOOPBACK_XGXS) {
6556 /* set 10G XGXS loopback */
6557 params->phy[INT_PHY].config_loopback(
6558 &params->phy[INT_PHY],
6559 params);
c18aa15d 6560
de6eae1f
YR		 6561 } else {
6562 /* set external phy loopback */
6563 u8 phy_index;
6564 for (phy_index = EXT_PHY1;
6565 phy_index < params->num_phys; phy_index++) {
6566 if (params->phy[phy_index].config_loopback)
6567 params->phy[phy_index].config_loopback(
6568 &params->phy[phy_index],
6569 params);
6570 }
6571 }
6572
6573 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6574 params->port*4, 0);
6575
6576 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
6577 } else
6578 /* No loopback */
6579 {
6580 if (params->switch_cfg == SWITCH_CFG_10G)
6581 bnx2x_xgxs_deassert(params);
6582 else
6583 bnx2x_serdes_deassert(bp, params->port);
6584 bnx2x_link_initialize(params, vars);
6585 msleep(30);
6586 bnx2x_link_int_enable(params);
6587 }
e10bc84d
YR		 6588 return 0;
6589}
de6eae1f
YR		 6590u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6591 u8 reset_ext_phy)
b7737c9b
YR		 6592{
6593 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6594 u8 phy_index, port = params->port;
6595 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
6596 /* disable attentions */
6597 vars->link_status = 0;
6598 bnx2x_update_mng(params, vars->link_status);
6599 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6600 (NIG_MASK_XGXS0_LINK_STATUS |
6601 NIG_MASK_XGXS0_LINK10G |
6602 NIG_MASK_SERDES0_LINK_STATUS |
6603 NIG_MASK_MI_INT));
b7737c9b 6604
de6eae1f
YR		 6605 /* activate nig drain */
6606 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
b7737c9b 6607
de6eae1f
YR		 6608 /* disable nig egress interface */
6609 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6610 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
b7737c9b 6611
de6eae1f
YR		 6612 /* Stop BigMac rx */
6613 bnx2x_bmac_rx_disable(bp, port);
b7737c9b 6614
de6eae1f
YR		 6615 /* disable emac */
6616 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
b7737c9b 6617
de6eae1f
YR		 6618 msleep(10);
6619 /* The PHY reset is controled by GPIO 1
6620 * Hold it as vars low
6621 */
6622 /* clear link led */
6623 bnx2x_set_led(params, LED_MODE_OFF, 0);
6624 if (reset_ext_phy) {
6625 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6626 phy_index++) {
6627 if (params->phy[phy_index].link_reset)
6628 params->phy[phy_index].link_reset(
6629 &params->phy[phy_index],
6630 params);
b7737c9b 6631 }
b7737c9b
YR		 6632 }
6633
de6eae1f
YR		 6634 if (params->phy[INT_PHY].link_reset)
6635 params->phy[INT_PHY].link_reset(
6636 &params->phy[INT_PHY], params);
6637 /* reset BigMac */
6638 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6639 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
b7737c9b 6640
de6eae1f
YR		 6641 /* disable nig ingress interface */
6642 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
6643 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
6644 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6645 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6646 vars->link_up = 0;
b7737c9b
YR		 6647 return 0;
6648}
6649
de6eae1f
YR		 6650/****************************************************************************/
6651/* Common function */
6652/****************************************************************************/
a22f0788 6653static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base, u8 phy_index)
6bbca910 6654{
e10bc84d
YR		 6655 struct bnx2x_phy phy[PORT_MAX];
6656 struct bnx2x_phy *phy_blk[PORT_MAX];
6bbca910
YR		 6657 u16 val;
6658 s8 port;
6659
6660 /* PART1 - Reset both phys */
6661 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6662 /* Extract the ext phy address for the port */
a22f0788 6663 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
e10bc84d
YR		 6664 port, &phy[port]) !=
6665 0) {
6666 DP(NETIF_MSG_LINK, "populate_phy failed\n");
6667 return -EINVAL;
6668 }
6bbca910
YR		 6669 /* disable attentions */
6670 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6671 (NIG_MASK_XGXS0_LINK_STATUS |
6672 NIG_MASK_XGXS0_LINK10G |
6673 NIG_MASK_SERDES0_LINK_STATUS |
6674 NIG_MASK_MI_INT));
6675
6bbca910
YR		 6676 /* Need to take the phy out of low power mode in order
6677 to write to access its registers */
6678 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6679 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6680
6681 /* Reset the phy */
e10bc84d 6682 bnx2x_cl45_write(bp, &phy[port],
6bbca910
YR		 6683 MDIO_PMA_DEVAD,
6684 MDIO_PMA_REG_CTRL,
6685 1<<15);
6686 }
6687
6688 /* Add delay of 150ms after reset */
6689 msleep(150);
6690
e10bc84d
YR		 6691 if (phy[PORT_0].addr & 0x1) {
6692 phy_blk[PORT_0] = &(phy[PORT_1]);
6693 phy_blk[PORT_1] = &(phy[PORT_0]);
6694 } else {
6695 phy_blk[PORT_0] = &(phy[PORT_0]);
6696 phy_blk[PORT_1] = &(phy[PORT_1]);
6697 }
6698
6bbca910
YR		 6699 /* PART2 - Download firmware to both phys */
6700 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6701 u16 fw_ver1;
6702
e10bc84d 6703 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
c18aa15d 6704 port);
6bbca910 6705
e10bc84d 6706 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6707 MDIO_PMA_DEVAD,
6708 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
16b311cc 6709 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6bbca910 6710 DP(NETIF_MSG_LINK,
16b311cc
EG		 6711 "bnx2x_8073_common_init_phy port %x:"
6712 "Download failed. fw version = 0x%x\n",
6713 port, fw_ver1);
6bbca910
YR		 6714 return -EINVAL;
6715 }
6716
6717 /* Only set bit 10 = 1 (Tx power down) */
e10bc84d 6718 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6719 MDIO_PMA_DEVAD,
6720 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6721
6722 /* Phase1 of TX_POWER_DOWN reset */
e10bc84d 6723 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 6724 MDIO_PMA_DEVAD,
6725 MDIO_PMA_REG_TX_POWER_DOWN,
6726 (val | 1<<10));
6727 }
6728
6729 /* Toggle Transmitter: Power down and then up with 600ms
6730 delay between */
6731 msleep(600);
6732
6733 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6734 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 6735 /* Phase2 of POWER_DOWN_RESET */
6bbca910 6736 /* Release bit 10 (Release Tx power down) */
e10bc84d 6737 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6738 MDIO_PMA_DEVAD,
6739 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6740
e10bc84d 6741 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 6742 MDIO_PMA_DEVAD,
6743 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6744 msleep(15);
6745
6746 /* Read modify write the SPI-ROM version select register */
e10bc84d 6747 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6748 MDIO_PMA_DEVAD,
6749 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
e10bc84d 6750 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 6751 MDIO_PMA_DEVAD,
6752 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6753
6754 /* set GPIO2 back to LOW */
6755 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6756 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6757 }
6758 return 0;
6bbca910
YR		 6759}
6760
a22f0788
YR		 6761static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base,
6762 u32 shmem2_base, u8 phy_index)
de6eae1f
YR		 6763{
6764 u32 val;
6765 s8 port;
6766 struct bnx2x_phy phy;
6767 /* Use port1 because of the static port-swap */
6768 /* Enable the module detection interrupt */
6769 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6770 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6771 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6772 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6773
6774 bnx2x_ext_phy_hw_reset(bp, 1);
6775 msleep(5);
6776 for (port = 0; port < PORT_MAX; port++) {
6777 /* Extract the ext phy address for the port */
a22f0788 6778 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 6779 port, &phy) !=
6780 0) {
6781 DP(NETIF_MSG_LINK, "populate phy failed\n");
6782 return -EINVAL;
6783 }
6784
6785 /* Reset phy*/
6786 bnx2x_cl45_write(bp, &phy,
6787 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
6788
6789
6790 /* Set fault module detected LED on */
6791 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6792 MISC_REGISTERS_GPIO_HIGH,
6793 port);
6794 }
6795
6796 return 0;
6797}
a22f0788
YR		 6798static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base,
6799 u32 shmem2_base, u8 phy_index)
4d295db0 6800{
a22f0788 6801 s8 port;
4d295db0 6802 u32 swap_val, swap_override;
e10bc84d
YR		 6803 struct bnx2x_phy phy[PORT_MAX];
6804 struct bnx2x_phy *phy_blk[PORT_MAX];
4d295db0
EG		 6805 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6806 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6807 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6808
a22f0788 6809 port = 1;
4d295db0 6810
a22f0788
YR		 6811 bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override));
6812
6813 /* Calculate the port based on port swap */
6814 port ^= (swap_val && swap_override);
6815
6816 msleep(5);
bc7f0a05 6817
4d295db0 6818 /* PART1 - Reset both phys */
a22f0788 6819 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4d295db0 6820 /* Extract the ext phy address for the port */
a22f0788 6821 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
e10bc84d
YR		 6822 port, &phy[port]) !=
6823 0) {
6824 DP(NETIF_MSG_LINK, "populate phy failed\n");
6825 return -EINVAL;
6826 }
4d295db0
EG		 6827 /* disable attentions */
6828 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6829 (NIG_MASK_XGXS0_LINK_STATUS |
6830 NIG_MASK_XGXS0_LINK10G |
6831 NIG_MASK_SERDES0_LINK_STATUS |
6832 NIG_MASK_MI_INT));
6833
4d295db0
EG		 6834
6835 /* Reset the phy */
e10bc84d 6836 bnx2x_cl45_write(bp, &phy[port],
4d295db0
EG		 6837 MDIO_PMA_DEVAD,
6838 MDIO_PMA_REG_CTRL,
6839 1<<15);
6840 }
6841
6842 /* Add delay of 150ms after reset */
6843 msleep(150);
e10bc84d
YR		 6844 if (phy[PORT_0].addr & 0x1) {
6845 phy_blk[PORT_0] = &(phy[PORT_1]);
6846 phy_blk[PORT_1] = &(phy[PORT_0]);
6847 } else {
6848 phy_blk[PORT_0] = &(phy[PORT_0]);
6849 phy_blk[PORT_1] = &(phy[PORT_1]);
6850 }
4d295db0 6851 /* PART2 - Download firmware to both phys */
e10bc84d 6852 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4d295db0
EG		 6853 u16 fw_ver1;
6854
e10bc84d 6855 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
c18aa15d 6856 port);
e10bc84d 6857 bnx2x_cl45_read(bp, phy_blk[port],
4d295db0
EG		 6858 MDIO_PMA_DEVAD,
6859 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6860 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6861 DP(NETIF_MSG_LINK,
bc7f0a05 6862 "bnx2x_8727_common_init_phy port %x:"
4d295db0
EG		 6863 "Download failed. fw version = 0x%x\n",
6864 port, fw_ver1);
6865 return -EINVAL;
6866 }
4d295db0
EG		 6867 }
6868
4d295db0
EG		 6869 return 0;
6870}
6871
a22f0788
YR		 6872static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base,
6873 u32 shmem2_base, u8 phy_index,
6874 u32 ext_phy_type)
6bbca910
YR		 6875{
6876 u8 rc = 0;
6bbca910
YR		 6877
6878 switch (ext_phy_type) {
6879 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
a22f0788
YR		 6880 rc = bnx2x_8073_common_init_phy(bp, shmem_base,
6881 shmem2_base, phy_index);
6bbca910 6882 break;
4d295db0
EG		 6883
6884 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6885 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
a22f0788
YR		 6886 rc = bnx2x_8727_common_init_phy(bp, shmem_base,
6887 shmem2_base, phy_index);
4d295db0
EG		 6888 break;
6889
589abe3a
EG		 6890 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6891 /* GPIO1 affects both ports, so there's need to pull
6892 it for single port alone */
a22f0788
YR		 6893 rc = bnx2x_8726_common_init_phy(bp, shmem_base,
6894 shmem2_base, phy_index);
6895 break;
6896 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6897 rc = -EINVAL;
4f60dab1 6898 break;
6bbca910
YR		 6899 default:
6900 DP(NETIF_MSG_LINK,
6901 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6902 ext_phy_type);
6903 break;
6904 }
6905
6906 return rc;
6907}
6908
a22f0788
YR		 6909u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base,
6910 u32 shmem2_base)
6911{
6912 u8 rc = 0;
6913 u8 phy_index;
6914 u32 ext_phy_type, ext_phy_config;
6915 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6916
6917 if (CHIP_REV_IS_EMUL(bp))
6918 return 0;
6919
6920 /* Read the ext_phy_type for arbitrary port(0) */
6921 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
6922 phy_index++) {
6923 ext_phy_config = bnx2x_get_ext_phy_config(bp,
6924 shmem_base,
6925 phy_index, 0);
6926 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6927 rc |= bnx2x_ext_phy_common_init(bp, shmem_base,
6928 shmem2_base,
6929 phy_index, ext_phy_type);
6930 }
6931 return rc;
6932}
d90d96ba 6933
a22f0788 6934u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
d90d96ba
YR		 6935{
6936 u8 phy_index;
6937 struct bnx2x_phy phy;
6938 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
6939 phy_index++) {
a22f0788 6940 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 6941 0, &phy) != 0) {
6942 DP(NETIF_MSG_LINK, "populate phy failed\n");
6943 return 0;
6944 }
6945
6946 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
6947 return 1;
6948 }
6949 return 0;
6950}
6951
6952u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
6953 u32 shmem_base,
a22f0788 6954 u32 shmem2_base,
d90d96ba
YR		 6955 u8 port)
6956{
6957 u8 phy_index, fan_failure_det_req = 0;
6958 struct bnx2x_phy phy;
6959 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
6960 phy_index++) {
a22f0788 6961 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 6962 port, &phy)
6963 != 0) {
6964 DP(NETIF_MSG_LINK, "populate phy failed\n");
6965 return 0;
6966 }
6967 fan_failure_det_req |= (phy.flags &
6968 FLAGS_FAN_FAILURE_DET_REQ);
6969 }
6970 return fan_failure_det_req;
6971}
6972
6973void bnx2x_hw_reset_phy(struct link_params *params)
6974{
6975 u8 phy_index;
6976 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
6977 phy_index++) {
6978 if (params->phy[phy_index].hw_reset) {
6979 params->phy[phy_index].hw_reset(
6980 &params->phy[phy_index],
6981 params);
6982 params->phy[phy_index] = phy_null;
6983 }
6984 }
6985}
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