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bnx2x: Apply logic changes for the new scheme
[mirror_ubuntu-kernels.git] / drivers / net / bnx2x / bnx2x_link.c
CommitLineData
d05c26ce 1/* Copyright 2008-2009 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
7995c64e
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
ea4e040a
YR		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
ea4e040a 26
ea4e040a
YR		 27#include "bnx2x.h"
28
29/********************************************************/
3196a88a 30#define ETH_HLEN 14
ea4e040a
YR		 31#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
32#define ETH_MIN_PACKET_SIZE 60
33#define ETH_MAX_PACKET_SIZE 1500
34#define ETH_MAX_JUMBO_PACKET_SIZE 9600
35#define MDIO_ACCESS_TIMEOUT 1000
36#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 37
38/***********************************************************/
3196a88a 39/* Shortcut definitions */
ea4e040a
YR		 40/***********************************************************/
41
2f904460
EG		 42#define NIG_LATCH_BC_ENABLE_MI_INT 0
43
44#define NIG_STATUS_EMAC0_MI_INT \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 46#define NIG_STATUS_XGXS0_LINK10G \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
48#define NIG_STATUS_XGXS0_LINK_STATUS \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
50#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
52#define NIG_STATUS_SERDES0_LINK_STATUS \
53 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
54#define NIG_MASK_MI_INT \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
56#define NIG_MASK_XGXS0_LINK10G \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
58#define NIG_MASK_XGXS0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
60#define NIG_MASK_SERDES0_LINK_STATUS \
61 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
62
63#define MDIO_AN_CL73_OR_37_COMPLETE \
64 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
65 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
66
67#define XGXS_RESET_BITS \
68 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
73
74#define SERDES_RESET_BITS \
75 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
79
80#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
3196a88a
EG		 82#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83#define AUTONEG_PARALLEL \
ea4e040a 84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 85#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 86 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 87#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 88
89#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
91#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
93#define GP_STATUS_SPEED_MASK \
94 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
95#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
96#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
97#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
98#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
99#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
100#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
101#define GP_STATUS_10G_HIG \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
103#define GP_STATUS_10G_CX4 \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
105#define GP_STATUS_12G_HIG \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
107#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
108#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
109#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
110#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
111#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
112#define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
114
115#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
122#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
123#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
138
139#define PHY_XGXS_FLAG 0x1
140#define PHY_SGMII_FLAG 0x2
141#define PHY_SERDES_FLAG 0x4
142
589abe3a
EG		 143/* */
144#define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147
4d295db0
EG		 148
149#define SFP_EEPROM_COMP_CODE_ADDR 0x3
150 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
151 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
152 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
153
589abe3a
EG		 154#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 157
589abe3a
EG		 158#define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160#define SFP_EEPROM_OPTIONS_SIZE 2
161
4d295db0
EG		 162#define EDC_MODE_LINEAR 0x0022
163#define EDC_MODE_LIMITING 0x0044
164#define EDC_MODE_PASSIVE_DAC 0x0055
165
166
589abe3a 167
ea4e040a
YR		 168/**********************************************************/
169/* INTERFACE */
170/**********************************************************/
e10bc84d
YR		 171
172#define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
173 bnx2x_cl45_write(_bp, _phy, \
7aa0711f 174 (_phy)->def_md_devad, \
ea4e040a
YR		 175 (_bank + (_addr & 0xf)), \
176 _val)
177
e10bc84d
YR		 178#define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
179 bnx2x_cl45_read(_bp, _phy, \
7aa0711f 180 (_phy)->def_md_devad, \
ea4e040a
YR		 181 (_bank + (_addr & 0xf)), \
182 _val)
183
e10bc84d 184static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
ea4e040a 185{
e10bc84d 186 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ab6ad5a4 187
c1b73990 188 /* Set Clause 22 */
e10bc84d 189 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
c1b73990
EG		 190 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
191 udelay(500);
192 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
193 udelay(500);
194 /* Set Clause 45 */
e10bc84d 195 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
c1b73990 196}
e10bc84d 197
ea4e040a
YR		 198static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
199{
200 u32 val = REG_RD(bp, reg);
201
202 val |= bits;
203 REG_WR(bp, reg, val);
204 return val;
205}
206
207static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
208{
209 u32 val = REG_RD(bp, reg);
210
211 val &= ~bits;
212 REG_WR(bp, reg, val);
213 return val;
214}
215
216static void bnx2x_emac_init(struct link_params *params,
217 struct link_vars *vars)
218{
219 /* reset and unreset the emac core */
220 struct bnx2x *bp = params->bp;
221 u8 port = params->port;
222 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
223 u32 val;
224 u16 timeout;
225
226 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
227 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
228 udelay(5);
229 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
230 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
231
232 /* init emac - use read-modify-write */
233 /* self clear reset */
234 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 235 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 236
237 timeout = 200;
3196a88a 238 do {
ea4e040a
YR		 239 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
240 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
241 if (!timeout) {
242 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
243 return;
244 }
245 timeout--;
3196a88a 246 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 247
248 /* Set mac address */
249 val = ((params->mac_addr[0] << 8) |
250 params->mac_addr[1]);
3196a88a 251 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 252
253 val = ((params->mac_addr[2] << 24) |
254 (params->mac_addr[3] << 16) |
255 (params->mac_addr[4] << 8) |
256 params->mac_addr[5]);
3196a88a 257 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 258}
259
260static u8 bnx2x_emac_enable(struct link_params *params,
261 struct link_vars *vars, u8 lb)
262{
263 struct bnx2x *bp = params->bp;
264 u8 port = params->port;
265 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
266 u32 val;
267
268 DP(NETIF_MSG_LINK, "enabling EMAC\n");
269
270 /* enable emac and not bmac */
271 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
272
273 /* for paladium */
274 if (CHIP_REV_IS_EMUL(bp)) {
275 /* Use lane 1 (of lanes 0-3) */
276 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
277 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
278 port*4, 1);
279 }
280 /* for fpga */
281 else
282
283 if (CHIP_REV_IS_FPGA(bp)) {
284 /* Use lane 1 (of lanes 0-3) */
285 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
286
287 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
288 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
289 0);
290 } else
291 /* ASIC */
292 if (vars->phy_flags & PHY_XGXS_FLAG) {
293 u32 ser_lane = ((params->lane_config &
294 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
295 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
296
297 DP(NETIF_MSG_LINK, "XGXS\n");
298 /* select the master lanes (out of 0-3) */
299 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
300 port*4, ser_lane);
301 /* select XGXS */
302 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
303 port*4, 1);
304
305 } else { /* SerDes */
306 DP(NETIF_MSG_LINK, "SerDes\n");
307 /* select SerDes */
308 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
309 port*4, 0);
310 }
311
811a2f2d
EG		 312 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
313 EMAC_RX_MODE_RESET);
314 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
315 EMAC_TX_MODE_RESET);
ea4e040a
YR		 316
317 if (CHIP_REV_IS_SLOW(bp)) {
318 /* config GMII mode */
319 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 320 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
ea4e040a
YR		 321 (val | EMAC_MODE_PORT_GMII));
322 } else { /* ASIC */
323 /* pause enable/disable */
324 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
325 EMAC_RX_MODE_FLOW_EN);
c0700f90 326 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 327 bnx2x_bits_en(bp, emac_base +
328 EMAC_REG_EMAC_RX_MODE,
329 EMAC_RX_MODE_FLOW_EN);
330
331 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 332 (EMAC_TX_MODE_EXT_PAUSE_EN |
333 EMAC_TX_MODE_FLOW_EN));
c0700f90 334 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 335 bnx2x_bits_en(bp, emac_base +
336 EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 337 (EMAC_TX_MODE_EXT_PAUSE_EN |
338 EMAC_TX_MODE_FLOW_EN));
ea4e040a
YR		 339 }
340
341 /* KEEP_VLAN_TAG, promiscuous */
342 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
343 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
3196a88a 344 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 345
346 /* Set Loopback */
347 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
348 if (lb)
349 val |= 0x810;
350 else
351 val &= ~0x810;
3196a88a 352 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 353
6c55c3cd
EG		 354 /* enable emac */
355 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
356
ea4e040a 357 /* enable emac for jumbo packets */
3196a88a 358 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 359 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
360 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
361
362 /* strip CRC */
363 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
364
365 /* disable the NIG in/out to the bmac */
366 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
367 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
368 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
369
370 /* enable the NIG in/out to the emac */
371 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
372 val = 0;
c0700f90 373 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 374 val = 1;
375
376 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
377 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
378
379 if (CHIP_REV_IS_EMUL(bp)) {
380 /* take the BigMac out of reset */
381 REG_WR(bp,
382 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
383 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
384
385 /* enable access for bmac registers */
386 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
6f65497b
EG		 387 } else
388 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 389
390 vars->mac_type = MAC_TYPE_EMAC;
391 return 0;
392}
393
394
395
396static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
397 u8 is_lb)
398{
399 struct bnx2x *bp = params->bp;
400 u8 port = params->port;
401 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
402 NIG_REG_INGRESS_BMAC0_MEM;
403 u32 wb_data[2];
404 u32 val;
405
406 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
407 /* reset and unreset the BigMac */
408 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
409 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
410 msleep(1);
411
412 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
413 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
414
415 /* enable access for bmac registers */
416 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
417
418 /* XGXS control */
419 wb_data[0] = 0x3c;
420 wb_data[1] = 0;
421 REG_WR_DMAE(bp, bmac_addr +
422 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
423 wb_data, 2);
424
425 /* tx MAC SA */
426 wb_data[0] = ((params->mac_addr[2] << 24) |
427 (params->mac_addr[3] << 16) |
428 (params->mac_addr[4] << 8) |
429 params->mac_addr[5]);
430 wb_data[1] = ((params->mac_addr[0] << 8) |
431 params->mac_addr[1]);
432 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
433 wb_data, 2);
434
435 /* tx control */
436 val = 0xc0;
c0700f90 437 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 438 val |= 0x800000;
439 wb_data[0] = val;
440 wb_data[1] = 0;
441 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
442 wb_data, 2);
443
444 /* mac control */
445 val = 0x3;
446 if (is_lb) {
447 val |= 0x4;
448 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
449 }
450 wb_data[0] = val;
451 wb_data[1] = 0;
452 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
453 wb_data, 2);
454
ea4e040a
YR		 455 /* set rx mtu */
456 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
457 wb_data[1] = 0;
458 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
459 wb_data, 2);
460
461 /* rx control set to don't strip crc */
462 val = 0x14;
c0700f90 463 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 464 val |= 0x20;
465 wb_data[0] = val;
466 wb_data[1] = 0;
467 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
468 wb_data, 2);
469
470 /* set tx mtu */
471 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
472 wb_data[1] = 0;
473 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
474 wb_data, 2);
475
476 /* set cnt max size */
477 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
478 wb_data[1] = 0;
479 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
480 wb_data, 2);
481
482 /* configure safc */
483 wb_data[0] = 0x1000200;
484 wb_data[1] = 0;
485 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
486 wb_data, 2);
487 /* fix for emulation */
488 if (CHIP_REV_IS_EMUL(bp)) {
489 wb_data[0] = 0xf000;
490 wb_data[1] = 0;
491 REG_WR_DMAE(bp,
492 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
493 wb_data, 2);
494 }
495
496 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
497 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
498 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
499 val = 0;
c0700f90 500 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 501 val = 1;
502 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
503 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
504 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
505 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
506 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
507 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
508
509 vars->mac_type = MAC_TYPE_BMAC;
510 return 0;
511}
512
c18aa15d 513static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
ea4e040a 514{
ea4e040a
YR		 515 u32 val;
516
c18aa15d 517 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
ea4e040a 518
c18aa15d 519 val = SERDES_RESET_BITS << (port*16);
ea4e040a
YR		 520
521 /* reset and unreset the SerDes/XGXS */
c18aa15d 522 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
ea4e040a 523 udelay(500);
c18aa15d
YR		 524 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
525
526 bnx2x_set_serdes_access(bp, port);
527
528 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
529 port*0x10,
530 DEFAULT_PHY_DEV_ADDR);
ea4e040a
YR		 531}
532
c18aa15d
YR		 533static void bnx2x_xgxs_deassert(struct link_params *params)
534{
535 struct bnx2x *bp = params->bp;
536 u8 port;
537 u32 val;
538 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
539 port = params->port;
540
541 val = XGXS_RESET_BITS << (port*16);
542
543 /* reset and unreset the SerDes/XGXS */
544 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
545 udelay(500);
546 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
547
548 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
549 port*0x18, 0);
550 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
551 params->phy[INT_PHY].def_md_devad);
552}
ea4e040a
YR		 553void bnx2x_link_status_update(struct link_params *params,
554 struct link_vars *vars)
555{
556 struct bnx2x *bp = params->bp;
557 u8 link_10g;
558 u8 port = params->port;
559
560 if (params->switch_cfg == SWITCH_CFG_1G)
561 vars->phy_flags = PHY_SERDES_FLAG;
562 else
563 vars->phy_flags = PHY_XGXS_FLAG;
564 vars->link_status = REG_RD(bp, params->shmem_base +
565 offsetof(struct shmem_region,
566 port_mb[port].link_status));
567
568 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
569
570 if (vars->link_up) {
571 DP(NETIF_MSG_LINK, "phy link up\n");
572
573 vars->phy_link_up = 1;
574 vars->duplex = DUPLEX_FULL;
575 switch (vars->link_status &
576 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
577 case LINK_10THD:
578 vars->duplex = DUPLEX_HALF;
579 /* fall thru */
580 case LINK_10TFD:
581 vars->line_speed = SPEED_10;
582 break;
583
584 case LINK_100TXHD:
585 vars->duplex = DUPLEX_HALF;
586 /* fall thru */
587 case LINK_100T4:
588 case LINK_100TXFD:
589 vars->line_speed = SPEED_100;
590 break;
591
592 case LINK_1000THD:
593 vars->duplex = DUPLEX_HALF;
594 /* fall thru */
595 case LINK_1000TFD:
596 vars->line_speed = SPEED_1000;
597 break;
598
599 case LINK_2500THD:
600 vars->duplex = DUPLEX_HALF;
601 /* fall thru */
602 case LINK_2500TFD:
603 vars->line_speed = SPEED_2500;
604 break;
605
606 case LINK_10GTFD:
607 vars->line_speed = SPEED_10000;
608 break;
609
610 case LINK_12GTFD:
611 vars->line_speed = SPEED_12000;
612 break;
613
614 case LINK_12_5GTFD:
615 vars->line_speed = SPEED_12500;
616 break;
617
618 case LINK_13GTFD:
619 vars->line_speed = SPEED_13000;
620 break;
621
622 case LINK_15GTFD:
623 vars->line_speed = SPEED_15000;
624 break;
625
626 case LINK_16GTFD:
627 vars->line_speed = SPEED_16000;
628 break;
629
630 default:
631 break;
632 }
633
7aa0711f 634 vars->flow_ctrl = 0;
ea4e040a 635 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
c0700f90 636 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 637
638 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
c0700f90 639 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
7aa0711f
YR		 640
641 if (!vars->flow_ctrl)
642 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
643
644 if (vars->line_speed &&
645 ((vars->line_speed == SPEED_10) ||
646 (vars->line_speed == SPEED_100))) {
647 vars->phy_flags |= PHY_SGMII_FLAG;
648 } else {
649 vars->phy_flags &= ~PHY_SGMII_FLAG;
ea4e040a
YR		 650 }
651
652 /* anything 10 and over uses the bmac */
653 link_10g = ((vars->line_speed == SPEED_10000) ||
654 (vars->line_speed == SPEED_12000) ||
655 (vars->line_speed == SPEED_12500) ||
656 (vars->line_speed == SPEED_13000) ||
657 (vars->line_speed == SPEED_15000) ||
658 (vars->line_speed == SPEED_16000));
659 if (link_10g)
660 vars->mac_type = MAC_TYPE_BMAC;
661 else
662 vars->mac_type = MAC_TYPE_EMAC;
663
664 } else { /* link down */
665 DP(NETIF_MSG_LINK, "phy link down\n");
666
667 vars->phy_link_up = 0;
668
669 vars->line_speed = 0;
670 vars->duplex = DUPLEX_FULL;
c0700f90 671 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 672
673 /* indicate no mac active */
674 vars->mac_type = MAC_TYPE_NONE;
675 }
676
677 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
678 vars->link_status, vars->phy_link_up);
679 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
680 vars->line_speed, vars->duplex, vars->flow_ctrl);
681}
682
683static void bnx2x_update_mng(struct link_params *params, u32 link_status)
684{
685 struct bnx2x *bp = params->bp;
ab6ad5a4 686
ea4e040a
YR		 687 REG_WR(bp, params->shmem_base +
688 offsetof(struct shmem_region,
689 port_mb[params->port].link_status),
690 link_status);
691}
692
693static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
694{
695 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
696 NIG_REG_INGRESS_BMAC0_MEM;
697 u32 wb_data[2];
3196a88a 698 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 699
700 /* Only if the bmac is out of reset */
701 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
702 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
703 nig_bmac_enable) {
704
705 /* Clear Rx Enable bit in BMAC_CONTROL register */
706 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
707 wb_data, 2);
708 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
709 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
710 wb_data, 2);
711
712 msleep(1);
713 }
714}
715
716static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
717 u32 line_speed)
718{
719 struct bnx2x *bp = params->bp;
720 u8 port = params->port;
721 u32 init_crd, crd;
722 u32 count = 1000;
ea4e040a
YR		 723
724 /* disable port */
725 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
726
727 /* wait for init credit */
728 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
729 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
730 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
731
732 while ((init_crd != crd) && count) {
733 msleep(5);
734
735 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
736 count--;
737 }
738 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
739 if (init_crd != crd) {
740 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
741 init_crd, crd);
742 return -EINVAL;
743 }
744
c0700f90 745 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 746 line_speed == SPEED_10 ||
747 line_speed == SPEED_100 ||
748 line_speed == SPEED_1000 ||
749 line_speed == SPEED_2500) {
750 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 751 /* update threshold */
752 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
753 /* update init credit */
8c99e7b0 754 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 755
756 } else {
757 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
758 ETH_OVREHEAD)/16;
8c99e7b0 759 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 760 /* update threshold */
761 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
762 /* update init credit */
763 switch (line_speed) {
ea4e040a
YR		 764 case SPEED_10000:
765 init_crd = thresh + 553 - 22;
766 break;
767
768 case SPEED_12000:
769 init_crd = thresh + 664 - 22;
770 break;
771
772 case SPEED_13000:
773 init_crd = thresh + 742 - 22;
774 break;
775
776 case SPEED_16000:
777 init_crd = thresh + 778 - 22;
778 break;
779 default:
780 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
781 line_speed);
782 return -EINVAL;
ea4e040a
YR		 783 }
784 }
785 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
786 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
787 line_speed, init_crd);
788
789 /* probe the credit changes */
790 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
791 msleep(5);
792 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
793
794 /* enable port */
795 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
796 return 0;
797}
798
c18aa15d
YR		 799static u32 bnx2x_get_emac_base(struct bnx2x *bp,
800 u32 mdc_mdio_access, u8 port)
ea4e040a 801{
c18aa15d
YR		 802 u32 emac_base = 0;
803 switch (mdc_mdio_access) {
804 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
805 break;
806 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
807 if (REG_RD(bp, NIG_REG_PORT_SWAP))
808 emac_base = GRCBASE_EMAC1;
809 else
810 emac_base = GRCBASE_EMAC0;
811 break;
812 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
589abe3a
EG		 813 if (REG_RD(bp, NIG_REG_PORT_SWAP))
814 emac_base = GRCBASE_EMAC0;
815 else
816 emac_base = GRCBASE_EMAC1;
ea4e040a 817 break;
c18aa15d
YR		 818 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
819 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
820 break;
821 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
6378c025 822 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 823 break;
824 default:
ea4e040a
YR		 825 break;
826 }
827 return emac_base;
828
829}
830
e10bc84d
YR		 831u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
832 u8 devad, u16 reg, u16 val)
ea4e040a
YR		 833{
834 u32 tmp, saved_mode;
835 u8 i, rc = 0;
ea4e040a
YR		 836
837 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
838 * (a value of 49==0x31) and make sure that the AUTO poll is off
839 */
589abe3a 840
e10bc84d 841 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 842 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
843 EMAC_MDIO_MODE_CLOCK_CNT);
844 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
845 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 846 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
847 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 848 udelay(40);
849
850 /* address */
851
e10bc84d 852 tmp = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 853 EMAC_MDIO_COMM_COMMAND_ADDRESS |
854 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 855 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 856
857 for (i = 0; i < 50; i++) {
858 udelay(10);
859
e10bc84d
YR		 860 tmp = REG_RD(bp, phy->mdio_ctrl +
861 EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 862 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
863 udelay(5);
864 break;
865 }
866 }
867 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
868 DP(NETIF_MSG_LINK, "write phy register failed\n");
869 rc = -EFAULT;
870 } else {
871 /* data */
e10bc84d 872 tmp = ((phy->addr << 21) | (devad << 16) | val |
ea4e040a
YR		 873 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
874 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 875 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 876
877 for (i = 0; i < 50; i++) {
878 udelay(10);
879
e10bc84d 880 tmp = REG_RD(bp, phy->mdio_ctrl +
ea4e040a
YR		 881 EMAC_REG_EMAC_MDIO_COMM);
882 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
883 udelay(5);
884 break;
885 }
886 }
887 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
888 DP(NETIF_MSG_LINK, "write phy register failed\n");
889 rc = -EFAULT;
890 }
891 }
892
893 /* Restore the saved mode */
e10bc84d 894 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 895
896 return rc;
897}
898
e10bc84d
YR		 899u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
900 u8 devad, u16 reg, u16 *ret_val)
ea4e040a
YR		 901{
902 u32 val, saved_mode;
903 u16 i;
904 u8 rc = 0;
905
ea4e040a
YR		 906 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
907 * (a value of 49==0x31) and make sure that the AUTO poll is off
908 */
589abe3a 909
e10bc84d
YR		 910 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
911 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
ea4e040a
YR		 912 EMAC_MDIO_MODE_CLOCK_CNT));
913 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
ab6ad5a4 914 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 915 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
916 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 917 udelay(40);
918
919 /* address */
e10bc84d 920 val = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 921 EMAC_MDIO_COMM_COMMAND_ADDRESS |
922 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 923 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 924
925 for (i = 0; i < 50; i++) {
926 udelay(10);
927
e10bc84d 928 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 929 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
930 udelay(5);
931 break;
932 }
933 }
934 if (val & EMAC_MDIO_COMM_START_BUSY) {
935 DP(NETIF_MSG_LINK, "read phy register failed\n");
936
937 *ret_val = 0;
938 rc = -EFAULT;
939
940 } else {
941 /* data */
e10bc84d 942 val = ((phy->addr << 21) | (devad << 16) |
ea4e040a
YR		 943 EMAC_MDIO_COMM_COMMAND_READ_45 |
944 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 945 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 946
947 for (i = 0; i < 50; i++) {
948 udelay(10);
949
e10bc84d 950 val = REG_RD(bp, phy->mdio_ctrl +
ea4e040a
YR		 951 EMAC_REG_EMAC_MDIO_COMM);
952 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
953 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
954 break;
955 }
956 }
957 if (val & EMAC_MDIO_COMM_START_BUSY) {
958 DP(NETIF_MSG_LINK, "read phy register failed\n");
959
960 *ret_val = 0;
961 rc = -EFAULT;
962 }
963 }
964
965 /* Restore the saved mode */
e10bc84d 966 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 967
968 return rc;
969}
970
e10bc84d
YR		 971u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
972 u8 devad, u16 reg, u16 *ret_val)
973{
974 u8 phy_index;
975 /**
976 * Probe for the phy according to the given phy_addr, and execute
977 * the read request on it
978 */
979 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
980 if (params->phy[phy_index].addr == phy_addr) {
981 return bnx2x_cl45_read(params->bp,
982 &params->phy[phy_index], devad,
983 reg, ret_val);
984 }
985 }
986 return -EINVAL;
987}
988
989u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
990 u8 devad, u16 reg, u16 val)
991{
992 u8 phy_index;
993 /**
994 * Probe for the phy according to the given phy_addr, and execute
995 * the write request on it
996 */
997 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
998 if (params->phy[phy_index].addr == phy_addr) {
999 return bnx2x_cl45_write(params->bp,
1000 &params->phy[phy_index], devad,
1001 reg, val);
1002 }
1003 }
1004 return -EINVAL;
1005}
1006
ea4e040a 1007static void bnx2x_set_aer_mmd(struct link_params *params,
e10bc84d 1008 struct bnx2x_phy *phy)
ea4e040a
YR		 1009{
1010 struct bnx2x *bp = params->bp;
1011 u32 ser_lane;
1012 u16 offset;
1013
1014 ser_lane = ((params->lane_config &
1015 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1016 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1017
e10bc84d
YR		 1018 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
1019 (phy->addr + ser_lane) : 0;
ea4e040a 1020
e10bc84d 1021 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1022 MDIO_REG_BANK_AER_BLOCK,
1023 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
1024}
1025
e10bc84d
YR		 1026static void bnx2x_set_master_ln(struct link_params *params,
1027 struct bnx2x_phy *phy)
ea4e040a
YR		 1028{
1029 struct bnx2x *bp = params->bp;
1030 u16 new_master_ln, ser_lane;
1031 ser_lane = ((params->lane_config &
1032 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1033 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1034
1035 /* set the master_ln for AN */
e10bc84d 1036 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1037 MDIO_REG_BANK_XGXS_BLOCK2,
1038 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1039 &new_master_ln);
1040
e10bc84d 1041 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1042 MDIO_REG_BANK_XGXS_BLOCK2 ,
1043 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1044 (new_master_ln | ser_lane));
1045}
1046
e10bc84d
YR		 1047static u8 bnx2x_reset_unicore(struct link_params *params,
1048 struct bnx2x_phy *phy,
1049 u8 set_serdes)
ea4e040a
YR		 1050{
1051 struct bnx2x *bp = params->bp;
1052 u16 mii_control;
1053 u16 i;
1054
e10bc84d 1055 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1056 MDIO_REG_BANK_COMBO_IEEE0,
1057 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1058
1059 /* reset the unicore */
e10bc84d 1060 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1061 MDIO_REG_BANK_COMBO_IEEE0,
1062 MDIO_COMBO_IEEE0_MII_CONTROL,
1063 (mii_control |
1064 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
e10bc84d
YR		 1065 if (set_serdes)
1066 bnx2x_set_serdes_access(bp, params->port);
c1b73990 1067
ea4e040a
YR		 1068 /* wait for the reset to self clear */
1069 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1070 udelay(5);
1071
1072 /* the reset erased the previous bank value */
e10bc84d 1073 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1074 MDIO_REG_BANK_COMBO_IEEE0,
1075 MDIO_COMBO_IEEE0_MII_CONTROL,
1076 &mii_control);
1077
1078 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1079 udelay(5);
1080 return 0;
1081 }
1082 }
1083
1084 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1085 return -EINVAL;
1086
1087}
1088
e10bc84d
YR		 1089static void bnx2x_set_swap_lanes(struct link_params *params,
1090 struct bnx2x_phy *phy)
ea4e040a
YR		 1091{
1092 struct bnx2x *bp = params->bp;
1093 /* Each two bits represents a lane number:
1094 No swap is 0123 => 0x1b no need to enable the swap */
1095 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1096
1097 ser_lane = ((params->lane_config &
1098 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1099 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1100 rx_lane_swap = ((params->lane_config &
1101 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1102 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1103 tx_lane_swap = ((params->lane_config &
1104 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1105 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1106
1107 if (rx_lane_swap != 0x1b) {
e10bc84d 1108 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1109 MDIO_REG_BANK_XGXS_BLOCK2,
1110 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1111 (rx_lane_swap |
1112 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1113 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1114 } else {
e10bc84d 1115 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1116 MDIO_REG_BANK_XGXS_BLOCK2,
1117 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1118 }
1119
1120 if (tx_lane_swap != 0x1b) {
e10bc84d 1121 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1122 MDIO_REG_BANK_XGXS_BLOCK2,
1123 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1124 (tx_lane_swap |
1125 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1126 } else {
e10bc84d 1127 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1128 MDIO_REG_BANK_XGXS_BLOCK2,
1129 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1130 }
1131}
1132
e10bc84d
YR		 1133static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1134 struct link_params *params)
ea4e040a
YR		 1135{
1136 struct bnx2x *bp = params->bp;
1137 u16 control2;
e10bc84d 1138 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1139 MDIO_REG_BANK_SERDES_DIGITAL,
1140 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1141 &control2);
7aa0711f 1142 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
18afb0a6
YR		 1143 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1144 else
1145 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
7aa0711f
YR		 1146 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1147 phy->speed_cap_mask, control2);
e10bc84d 1148 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1149 MDIO_REG_BANK_SERDES_DIGITAL,
1150 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1151 control2);
1152
e10bc84d 1153 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
c18aa15d 1154 (phy->speed_cap_mask &
18afb0a6 1155 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 1156 DP(NETIF_MSG_LINK, "XGXS\n");
1157
e10bc84d 1158 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1159 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1160 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1161 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1162
e10bc84d 1163 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1164 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1165 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1166 &control2);
1167
1168
1169 control2 |=
1170 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1171
e10bc84d 1172 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1173 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1174 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1175 control2);
1176
1177 /* Disable parallel detection of HiG */
e10bc84d 1178 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1179 MDIO_REG_BANK_XGXS_BLOCK2,
1180 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1181 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1182 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1183 }
1184}
1185
e10bc84d
YR		 1186static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1187 struct link_params *params,
239d686d
EG		 1188 struct link_vars *vars,
1189 u8 enable_cl73)
ea4e040a
YR		 1190{
1191 struct bnx2x *bp = params->bp;
1192 u16 reg_val;
1193
1194 /* CL37 Autoneg */
e10bc84d 1195 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1196 MDIO_REG_BANK_COMBO_IEEE0,
1197 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1198
1199 /* CL37 Autoneg Enabled */
8c99e7b0 1200 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1201 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1202 else /* CL37 Autoneg Disabled */
1203 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1204 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1205
e10bc84d 1206 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1207 MDIO_REG_BANK_COMBO_IEEE0,
1208 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1209
1210 /* Enable/Disable Autodetection */
1211
e10bc84d 1212 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1213 MDIO_REG_BANK_SERDES_DIGITAL,
1214 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 1215 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1216 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1217 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 1218 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1219 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1220 else
1221 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1222
e10bc84d 1223 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1224 MDIO_REG_BANK_SERDES_DIGITAL,
1225 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1226
1227 /* Enable TetonII and BAM autoneg */
e10bc84d 1228 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1229 MDIO_REG_BANK_BAM_NEXT_PAGE,
1230 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1231 &reg_val);
8c99e7b0 1232 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1233 /* Enable BAM aneg Mode and TetonII aneg Mode */
1234 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1235 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1236 } else {
1237 /* TetonII and BAM Autoneg Disabled */
1238 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1239 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1240 }
e10bc84d 1241 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1242 MDIO_REG_BANK_BAM_NEXT_PAGE,
1243 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1244 reg_val);
1245
239d686d
EG		 1246 if (enable_cl73) {
1247 /* Enable Cl73 FSM status bits */
e10bc84d 1248 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1249 MDIO_REG_BANK_CL73_USERB0,
1250 MDIO_CL73_USERB0_CL73_UCTRL,
7846e471 1251 0xe);
239d686d
EG		 1252
1253 /* Enable BAM Station Manager*/
e10bc84d 1254 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1255 MDIO_REG_BANK_CL73_USERB0,
1256 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1257 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1258 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1259 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1260
7846e471 1261 /* Advertise CL73 link speeds */
e10bc84d 1262 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1263 MDIO_REG_BANK_CL73_IEEEB1,
1264 MDIO_CL73_IEEEB1_AN_ADV2,
1265 &reg_val);
7aa0711f 1266 if (phy->speed_cap_mask &
7846e471
YR		 1267 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1268 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
7aa0711f 1269 if (phy->speed_cap_mask &
7846e471
YR		 1270 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1271 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d 1272
e10bc84d 1273 CL45_WR_OVER_CL22(bp, phy,
cc81735e
JL		 1274 MDIO_REG_BANK_CL73_IEEEB1,
1275 MDIO_CL73_IEEEB1_AN_ADV2,
1276 reg_val);
239d686d 1277
239d686d
EG		 1278 /* CL73 Autoneg Enabled */
1279 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1280
1281 } else /* CL73 Autoneg Disabled */
1282 reg_val = 0;
ea4e040a 1283
e10bc84d 1284 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1285 MDIO_REG_BANK_CL73_IEEEB0,
1286 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1287}
1288
1289/* program SerDes, forced speed */
e10bc84d
YR		 1290static void bnx2x_program_serdes(struct bnx2x_phy *phy,
1291 struct link_params *params,
8c99e7b0 1292 struct link_vars *vars)
ea4e040a
YR		 1293{
1294 struct bnx2x *bp = params->bp;
1295 u16 reg_val;
1296
57937203 1297 /* program duplex, disable autoneg and sgmii*/
e10bc84d 1298 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1299 MDIO_REG_BANK_COMBO_IEEE0,
1300 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1301 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 1302 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1303 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
7aa0711f 1304 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a 1305 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
e10bc84d 1306 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1307 MDIO_REG_BANK_COMBO_IEEE0,
1308 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1309
1310 /* program speed
1311 - needed only if the speed is greater than 1G (2.5G or 10G) */
e10bc84d 1312 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1313 MDIO_REG_BANK_SERDES_DIGITAL,
1314 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 1315 /* clearing the speed value before setting the right speed */
1316 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1317
1318 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1319 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1320
1321 if (!((vars->line_speed == SPEED_1000) ||
1322 (vars->line_speed == SPEED_100) ||
1323 (vars->line_speed == SPEED_10))) {
1324
ea4e040a
YR		 1325 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1326 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 1327 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 1328 reg_val |=
1329 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 1330 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 1331 reg_val |=
1332 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 1333 }
1334
e10bc84d 1335 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1336 MDIO_REG_BANK_SERDES_DIGITAL,
1337 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 1338
ea4e040a
YR		 1339}
1340
e10bc84d
YR		 1341static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
1342 struct link_params *params)
ea4e040a
YR		 1343{
1344 struct bnx2x *bp = params->bp;
1345 u16 val = 0;
1346
1347 /* configure the 48 bits for BAM AN */
1348
1349 /* set extended capabilities */
7aa0711f 1350 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
ea4e040a 1351 val |= MDIO_OVER_1G_UP1_2_5G;
7aa0711f 1352 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
ea4e040a 1353 val |= MDIO_OVER_1G_UP1_10G;
e10bc84d 1354 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1355 MDIO_REG_BANK_OVER_1G,
1356 MDIO_OVER_1G_UP1, val);
1357
e10bc84d 1358 CL45_WR_OVER_CL22(bp, phy,
ea4e040a 1359 MDIO_REG_BANK_OVER_1G,
239d686d 1360 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 1361}
1362
e10bc84d
YR		 1363static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
1364 struct link_params *params, u16 *ieee_fc)
ea4e040a 1365{
d5cb9e99 1366 struct bnx2x *bp = params->bp;
8c99e7b0 1367 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
ea4e040a
YR		 1368 /* resolve pause mode and advertisement
1369 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1370
7aa0711f 1371 switch (phy->req_flow_ctrl) {
c0700f90
DM		 1372 case BNX2X_FLOW_CTRL_AUTO:
1373 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
8c99e7b0 1374 *ieee_fc |=
ea4e040a
YR		 1375 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1376 } else {
8c99e7b0 1377 *ieee_fc |=
ea4e040a
YR		 1378 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1379 }
1380 break;
c0700f90 1381 case BNX2X_FLOW_CTRL_TX:
8c99e7b0 1382 *ieee_fc |=
ea4e040a
YR		 1383 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1384 break;
1385
c0700f90
DM		 1386 case BNX2X_FLOW_CTRL_RX:
1387 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 1388 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 1389 break;
1390
c0700f90 1391 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 1392 default:
8c99e7b0 1393 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 1394 break;
1395 }
d5cb9e99 1396 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
8c99e7b0 1397}
ea4e040a 1398
e10bc84d
YR		 1399static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
1400 struct link_params *params,
1ef70b9c 1401 u16 ieee_fc)
8c99e7b0
YR		 1402{
1403 struct bnx2x *bp = params->bp;
7846e471 1404 u16 val;
8c99e7b0 1405 /* for AN, we are always publishing full duplex */
ea4e040a 1406
e10bc84d 1407 CL45_WR_OVER_CL22(bp, phy,
ea4e040a 1408 MDIO_REG_BANK_COMBO_IEEE0,
1ef70b9c 1409 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
e10bc84d 1410 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1411 MDIO_REG_BANK_CL73_IEEEB1,
1412 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1413 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1414 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
e10bc84d 1415 CL45_WR_OVER_CL22(bp, phy,
7846e471
YR		 1416 MDIO_REG_BANK_CL73_IEEEB1,
1417 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 1418}
1419
e10bc84d
YR		 1420static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
1421 struct link_params *params,
1422 u8 enable_cl73)
ea4e040a
YR		 1423{
1424 struct bnx2x *bp = params->bp;
3a36f2ef 1425 u16 mii_control;
239d686d 1426
ea4e040a 1427 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 1428 /* Enable and restart BAM/CL37 aneg */
ea4e040a 1429
239d686d 1430 if (enable_cl73) {
e10bc84d 1431 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1432 MDIO_REG_BANK_CL73_IEEEB0,
1433 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1434 &mii_control);
1435
e10bc84d 1436 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1437 MDIO_REG_BANK_CL73_IEEEB0,
1438 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1439 (mii_control |
1440 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1441 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1442 } else {
1443
e10bc84d 1444 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1445 MDIO_REG_BANK_COMBO_IEEE0,
1446 MDIO_COMBO_IEEE0_MII_CONTROL,
1447 &mii_control);
1448 DP(NETIF_MSG_LINK,
1449 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1450 mii_control);
e10bc84d 1451 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1452 MDIO_REG_BANK_COMBO_IEEE0,
1453 MDIO_COMBO_IEEE0_MII_CONTROL,
1454 (mii_control |
1455 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1456 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1457 }
ea4e040a
YR		 1458}
1459
e10bc84d
YR		 1460static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
1461 struct link_params *params,
8c99e7b0 1462 struct link_vars *vars)
ea4e040a
YR		 1463{
1464 struct bnx2x *bp = params->bp;
1465 u16 control1;
1466
1467 /* in SGMII mode, the unicore is always slave */
1468
e10bc84d 1469 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1470 MDIO_REG_BANK_SERDES_DIGITAL,
1471 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1472 &control1);
1473 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1474 /* set sgmii mode (and not fiber) */
1475 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1476 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1477 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
e10bc84d 1478 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1479 MDIO_REG_BANK_SERDES_DIGITAL,
1480 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1481 control1);
1482
1483 /* if forced speed */
8c99e7b0 1484 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 1485 /* set speed, disable autoneg */
1486 u16 mii_control;
1487
e10bc84d 1488 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1489 MDIO_REG_BANK_COMBO_IEEE0,
1490 MDIO_COMBO_IEEE0_MII_CONTROL,
1491 &mii_control);
1492 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1493 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1494 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1495
8c99e7b0 1496 switch (vars->line_speed) {
ea4e040a
YR		 1497 case SPEED_100:
1498 mii_control |=
1499 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1500 break;
1501 case SPEED_1000:
1502 mii_control |=
1503 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1504 break;
1505 case SPEED_10:
1506 /* there is nothing to set for 10M */
1507 break;
1508 default:
1509 /* invalid speed for SGMII */
8c99e7b0
YR		 1510 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1511 vars->line_speed);
ea4e040a
YR		 1512 break;
1513 }
1514
1515 /* setting the full duplex */
7aa0711f 1516 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a
YR		 1517 mii_control |=
1518 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
e10bc84d 1519 CL45_WR_OVER_CL22(bp, phy,
ea4e040a
YR		 1520 MDIO_REG_BANK_COMBO_IEEE0,
1521 MDIO_COMBO_IEEE0_MII_CONTROL,
1522 mii_control);
1523
1524 } else { /* AN mode */
1525 /* enable and restart AN */
e10bc84d 1526 bnx2x_restart_autoneg(phy, params, 0);
ea4e040a
YR		 1527 }
1528}
1529
1530
1531/*
1532 * link management
1533 */
1534
1535static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0
YR		 1536{ /* LD LP */
1537 switch (pause_result) { /* ASYM P ASYM P */
1538 case 0xb: /* 1 0 1 1 */
c0700f90 1539 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 1540 break;
1541
8c99e7b0 1542 case 0xe: /* 1 1 1 0 */
c0700f90 1543 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 1544 break;
1545
8c99e7b0
YR		 1546 case 0x5: /* 0 1 0 1 */
1547 case 0x7: /* 0 1 1 1 */
1548 case 0xd: /* 1 1 0 1 */
1549 case 0xf: /* 1 1 1 1 */
c0700f90 1550 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 1551 break;
1552
1553 default:
1554 break;
1555 }
7aa0711f
YR		 1556 if (pause_result & (1<<0))
1557 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
1558 if (pause_result & (1<<1))
1559 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
1560
ea4e040a
YR		 1561}
1562
e10bc84d
YR		 1563static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
1564 struct link_params *params,
1565 struct link_vars *vars)
ea4e040a
YR		 1566{
1567 struct bnx2x *bp = params->bp;
ab6ad5a4
EG		 1568 u16 ld_pause; /* local */
1569 u16 lp_pause; /* link partner */
ea4e040a
YR		 1570 u16 pause_result;
1571 u8 ret = 0;
ea4e040a
YR		 1572 /* read twice */
1573
7aa0711f 1574 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 1575
7aa0711f
YR		 1576 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
1577 vars->flow_ctrl = phy->req_flow_ctrl;
1578 else if (phy->req_line_speed != SPEED_AUTO_NEG)
1579 vars->flow_ctrl = params->req_fc_auto_adv;
1580 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
ea4e040a 1581 ret = 1;
e10bc84d 1582 bnx2x_cl45_read(bp, phy,
ea4e040a
YR		 1583 MDIO_AN_DEVAD,
1584 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
e10bc84d 1585 bnx2x_cl45_read(bp, phy,
ea4e040a
YR		 1586 MDIO_AN_DEVAD,
1587 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1588 pause_result = (ld_pause &
1589 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1590 pause_result |= (lp_pause &
1591 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
2381a55c 1592 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
ea4e040a
YR		 1593 pause_result);
1594 bnx2x_pause_resolve(vars, pause_result);
1595 }
1596 return ret;
1597}
1598
e10bc84d
YR		 1599static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
1600 struct link_params *params)
15ddd2d0
YR		 1601{
1602 struct bnx2x *bp = params->bp;
1603 u16 pd_10g, status2_1000x;
7aa0711f
YR		 1604 if (phy->req_line_speed != SPEED_AUTO_NEG)
1605 return 0;
e10bc84d 1606 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 1607 MDIO_REG_BANK_SERDES_DIGITAL,
1608 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1609 &status2_1000x);
e10bc84d 1610 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 1611 MDIO_REG_BANK_SERDES_DIGITAL,
1612 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1613 &status2_1000x);
1614 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
1615 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
1616 params->port);
1617 return 1;
1618 }
1619
e10bc84d 1620 CL45_RD_OVER_CL22(bp, phy,
15ddd2d0
YR		 1621 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1622 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1623 &pd_10g);
1624
1625 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
1626 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
1627 params->port);
1628 return 1;
1629 }
1630 return 0;
1631}
ea4e040a 1632
e10bc84d
YR		 1633static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
1634 struct link_params *params,
1635 struct link_vars *vars,
1636 u32 gp_status)
ea4e040a
YR		 1637{
1638 struct bnx2x *bp = params->bp;
3196a88a
EG		 1639 u16 ld_pause; /* local driver */
1640 u16 lp_pause; /* link partner */
ea4e040a
YR		 1641 u16 pause_result;
1642
c0700f90 1643 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1644
1645 /* resolve from gp_status in case of AN complete and not sgmii */
7aa0711f
YR		 1646 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
1647 vars->flow_ctrl = phy->req_flow_ctrl;
1648 else if (phy->req_line_speed != SPEED_AUTO_NEG)
1649 vars->flow_ctrl = params->req_fc_auto_adv;
1650 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1651 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
e10bc84d 1652 if (bnx2x_direct_parallel_detect_used(phy, params)) {
15ddd2d0
YR		 1653 vars->flow_ctrl = params->req_fc_auto_adv;
1654 return;
1655 }
7846e471
YR		 1656 if ((gp_status &
1657 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1658 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
1659 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1660 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1661
e10bc84d 1662 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1663 MDIO_REG_BANK_CL73_IEEEB1,
1664 MDIO_CL73_IEEEB1_AN_ADV1,
1665 &ld_pause);
e10bc84d 1666 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1667 MDIO_REG_BANK_CL73_IEEEB1,
1668 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1669 &lp_pause);
1670 pause_result = (ld_pause &
1671 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
1672 >> 8;
1673 pause_result |= (lp_pause &
1674 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
1675 >> 10;
1676 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1677 pause_result);
1678 } else {
e10bc84d 1679 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1680 MDIO_REG_BANK_COMBO_IEEE0,
1681 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1682 &ld_pause);
e10bc84d 1683 CL45_RD_OVER_CL22(bp, phy,
7846e471
YR		 1684 MDIO_REG_BANK_COMBO_IEEE0,
1685 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1686 &lp_pause);
1687 pause_result = (ld_pause &
ea4e040a 1688 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
7846e471 1689 pause_result |= (lp_pause &
ea4e040a 1690 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
7846e471
YR		 1691 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
1692 pause_result);
1693 }
ea4e040a 1694 bnx2x_pause_resolve(vars, pause_result);
ea4e040a
YR		 1695 }
1696 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1697}
1698
e10bc84d
YR		 1699static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
1700 struct link_params *params)
239d686d
EG		 1701{
1702 struct bnx2x *bp = params->bp;
1703 u16 rx_status, ustat_val, cl37_fsm_recieved;
1704 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1705 /* Step 1: Make sure signal is detected */
e10bc84d 1706 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1707 MDIO_REG_BANK_RX0,
1708 MDIO_RX0_RX_STATUS,
1709 &rx_status);
1710 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
1711 (MDIO_RX0_RX_STATUS_SIGDET)) {
1712 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1713 "rx_status(0x80b0) = 0x%x\n", rx_status);
e10bc84d 1714 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1715 MDIO_REG_BANK_CL73_IEEEB0,
1716 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1717 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1718 return;
1719 }
1720 /* Step 2: Check CL73 state machine */
e10bc84d 1721 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1722 MDIO_REG_BANK_CL73_USERB0,
1723 MDIO_CL73_USERB0_CL73_USTAT1,
1724 &ustat_val);
1725 if ((ustat_val &
1726 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1727 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
1728 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1729 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
1730 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
1731 "ustat_val(0x8371) = 0x%x\n", ustat_val);
1732 return;
1733 }
1734 /* Step 3: Check CL37 Message Pages received to indicate LP
1735 supports only CL37 */
e10bc84d 1736 CL45_RD_OVER_CL22(bp, phy,
239d686d
EG		 1737 MDIO_REG_BANK_REMOTE_PHY,
1738 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1739 &cl37_fsm_recieved);
1740 if ((cl37_fsm_recieved &
1741 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1742 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
1743 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1744 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
1745 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
1746 "misc_rx_status(0x8330) = 0x%x\n",
1747 cl37_fsm_recieved);
1748 return;
1749 }
1750 /* The combined cl37/cl73 fsm state information indicating that we are
1751 connected to a device which does not support cl73, but does support
1752 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1753 /* Disable CL73 */
e10bc84d 1754 CL45_WR_OVER_CL22(bp, phy,
239d686d
EG		 1755 MDIO_REG_BANK_CL73_IEEEB0,
1756 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1757 0);
1758 /* Restart CL37 autoneg */
e10bc84d 1759 bnx2x_restart_autoneg(phy, params, 0);
239d686d
EG		 1760 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1761}
7aa0711f
YR		 1762
1763static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
1764 struct link_params *params,
1765 struct link_vars *vars,
1766 u32 gp_status)
1767{
1768 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1769 vars->link_status |=
1770 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1771
1772 if (bnx2x_direct_parallel_detect_used(phy, params))
1773 vars->link_status |=
1774 LINK_STATUS_PARALLEL_DETECTION_USED;
1775}
1776
b7737c9b
YR		 1777static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
1778 struct link_params *params,
1779 struct link_vars *vars)
ea4e040a
YR		 1780{
1781 struct bnx2x *bp = params->bp;
b7737c9b 1782 u16 new_line_speed , gp_status;
ea4e040a 1783 u8 rc = 0;
c18aa15d 1784
b7737c9b
YR		 1785 /* Read gp_status */
1786 CL45_RD_OVER_CL22(bp, phy,
1787 MDIO_REG_BANK_GP_STATUS,
1788 MDIO_GP_STATUS_TOP_AN_STATUS1,
1789 &gp_status);
7aa0711f
YR		 1790 if (phy->req_line_speed == SPEED_AUTO_NEG)
1791 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
ea4e040a
YR		 1792 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1793 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1794 gp_status);
1795
1796 vars->phy_link_up = 1;
1797 vars->link_status |= LINK_STATUS_LINK_UP;
1798
1799 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1800 vars->duplex = DUPLEX_FULL;
1801 else
1802 vars->duplex = DUPLEX_HALF;
1803
7aa0711f
YR		 1804 if (SINGLE_MEDIA_DIRECT(params)) {
1805 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
1806 if (phy->req_line_speed == SPEED_AUTO_NEG)
1807 bnx2x_xgxs_an_resolve(phy, params, vars,
1808 gp_status);
1809 }
ea4e040a
YR		 1810
1811 switch (gp_status & GP_STATUS_SPEED_MASK) {
1812 case GP_STATUS_10M:
6c55c3cd 1813 new_line_speed = SPEED_10;
ea4e040a
YR		 1814 if (vars->duplex == DUPLEX_FULL)
1815 vars->link_status |= LINK_10TFD;
1816 else
1817 vars->link_status |= LINK_10THD;
1818 break;
1819
1820 case GP_STATUS_100M:
6c55c3cd 1821 new_line_speed = SPEED_100;
ea4e040a
YR		 1822 if (vars->duplex == DUPLEX_FULL)
1823 vars->link_status |= LINK_100TXFD;
1824 else
1825 vars->link_status |= LINK_100TXHD;
1826 break;
1827
1828 case GP_STATUS_1G:
1829 case GP_STATUS_1G_KX:
6c55c3cd 1830 new_line_speed = SPEED_1000;
ea4e040a
YR		 1831 if (vars->duplex == DUPLEX_FULL)
1832 vars->link_status |= LINK_1000TFD;
1833 else
1834 vars->link_status |= LINK_1000THD;
1835 break;
1836
1837 case GP_STATUS_2_5G:
6c55c3cd 1838 new_line_speed = SPEED_2500;
ea4e040a
YR		 1839 if (vars->duplex == DUPLEX_FULL)
1840 vars->link_status |= LINK_2500TFD;
1841 else
1842 vars->link_status |= LINK_2500THD;
1843 break;
1844
1845 case GP_STATUS_5G:
1846 case GP_STATUS_6G:
1847 DP(NETIF_MSG_LINK,
1848 "link speed unsupported gp_status 0x%x\n",
1849 gp_status);
1850 return -EINVAL;
ab6ad5a4 1851
ea4e040a
YR		 1852 case GP_STATUS_10G_KX4:
1853 case GP_STATUS_10G_HIG:
1854 case GP_STATUS_10G_CX4:
6c55c3cd 1855 new_line_speed = SPEED_10000;
ea4e040a
YR		 1856 vars->link_status |= LINK_10GTFD;
1857 break;
1858
1859 case GP_STATUS_12G_HIG:
6c55c3cd 1860 new_line_speed = SPEED_12000;
ea4e040a
YR		 1861 vars->link_status |= LINK_12GTFD;
1862 break;
1863
1864 case GP_STATUS_12_5G:
6c55c3cd 1865 new_line_speed = SPEED_12500;
ea4e040a
YR		 1866 vars->link_status |= LINK_12_5GTFD;
1867 break;
1868
1869 case GP_STATUS_13G:
6c55c3cd 1870 new_line_speed = SPEED_13000;
ea4e040a
YR		 1871 vars->link_status |= LINK_13GTFD;
1872 break;
1873
1874 case GP_STATUS_15G:
6c55c3cd 1875 new_line_speed = SPEED_15000;
ea4e040a
YR		 1876 vars->link_status |= LINK_15GTFD;
1877 break;
1878
1879 case GP_STATUS_16G:
6c55c3cd 1880 new_line_speed = SPEED_16000;
ea4e040a
YR		 1881 vars->link_status |= LINK_16GTFD;
1882 break;
1883
1884 default:
1885 DP(NETIF_MSG_LINK,
1886 "link speed unsupported gp_status 0x%x\n",
1887 gp_status);
ab6ad5a4 1888 return -EINVAL;
ea4e040a
YR		 1889 }
1890
6c55c3cd 1891 vars->line_speed = new_line_speed;
ea4e040a 1892
e10bc84d 1893
ea4e040a
YR		 1894 } else { /* link_down */
1895 DP(NETIF_MSG_LINK, "phy link down\n");
1896
1897 vars->phy_link_up = 0;
57963ed9 1898
ea4e040a 1899 vars->duplex = DUPLEX_FULL;
c0700f90 1900 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 1901 vars->mac_type = MAC_TYPE_NONE;
239d686d 1902
c18aa15d
YR		 1903 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
1904 SINGLE_MEDIA_DIRECT(params)) {
239d686d 1905 /* Check signal is detected */
c18aa15d 1906 bnx2x_check_fallback_to_cl37(phy, params);
239d686d 1907 }
ea4e040a
YR		 1908 }
1909
2381a55c 1910 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
ea4e040a
YR		 1911 gp_status, vars->phy_link_up, vars->line_speed);
1912 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1913 " autoneg 0x%x\n",
1914 vars->duplex,
1915 vars->flow_ctrl, vars->autoneg);
1916 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1917
1918 return rc;
1919}
1920
ed8680a7 1921static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 1922{
1923 struct bnx2x *bp = params->bp;
e10bc84d 1924 struct bnx2x_phy *phy = &params->phy[INT_PHY];
ea4e040a
YR		 1925 u16 lp_up2;
1926 u16 tx_driver;
c2c8b03e 1927 u16 bank;
ea4e040a
YR		 1928
1929 /* read precomp */
e10bc84d 1930 CL45_RD_OVER_CL22(bp, phy,
ea4e040a
YR		 1931 MDIO_REG_BANK_OVER_1G,
1932 MDIO_OVER_1G_LP_UP2, &lp_up2);
1933
ea4e040a
YR		 1934 /* bits [10:7] at lp_up2, positioned at [15:12] */
1935 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1936 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1937 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1938
c2c8b03e
EG		 1939 if (lp_up2 == 0)
1940 return;
1941
1942 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
1943 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
e10bc84d 1944 CL45_RD_OVER_CL22(bp, phy,
c2c8b03e
EG		 1945 bank,
1946 MDIO_TX0_TX_DRIVER, &tx_driver);
1947
1948 /* replace tx_driver bits [15:12] */
1949 if (lp_up2 !=
1950 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
1951 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1952 tx_driver |= lp_up2;
e10bc84d 1953 CL45_WR_OVER_CL22(bp, phy,
c2c8b03e
EG		 1954 bank,
1955 MDIO_TX0_TX_DRIVER, tx_driver);
1956 }
ea4e040a
YR		 1957 }
1958}
1959
1960static u8 bnx2x_emac_program(struct link_params *params,
b7737c9b 1961 struct link_vars *vars)
ea4e040a
YR		 1962{
1963 struct bnx2x *bp = params->bp;
1964 u8 port = params->port;
1965 u16 mode = 0;
1966
1967 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1968 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1969 EMAC_REG_EMAC_MODE,
1970 (EMAC_MODE_25G_MODE |
1971 EMAC_MODE_PORT_MII_10M |
1972 EMAC_MODE_HALF_DUPLEX));
b7737c9b 1973 switch (vars->line_speed) {
ea4e040a
YR		 1974 case SPEED_10:
1975 mode |= EMAC_MODE_PORT_MII_10M;
1976 break;
1977
1978 case SPEED_100:
1979 mode |= EMAC_MODE_PORT_MII;
1980 break;
1981
1982 case SPEED_1000:
1983 mode |= EMAC_MODE_PORT_GMII;
1984 break;
1985
1986 case SPEED_2500:
1987 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1988 break;
1989
1990 default:
1991 /* 10G not valid for EMAC */
b7737c9b
YR		 1992 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1993 vars->line_speed);
ea4e040a
YR		 1994 return -EINVAL;
1995 }
1996
b7737c9b 1997 if (vars->duplex == DUPLEX_HALF)
ea4e040a
YR		 1998 mode |= EMAC_MODE_HALF_DUPLEX;
1999 bnx2x_bits_en(bp,
2000 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2001 mode);
2002
b7737c9b 2003 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 2004 return 0;
2005}
2006
b7737c9b
YR		 2007static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2008 struct link_params *params,
2009 struct link_vars *vars)
2010{
2011 u8 rc;
2012 vars->phy_flags |= PHY_SGMII_FLAG;
2013 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2014 bnx2x_set_aer_mmd(params, phy);
2015 rc = bnx2x_reset_unicore(params, phy, 1);
2016 /* reset the SerDes and wait for reset bit return low */
2017 if (rc != 0)
2018 return rc;
2019 bnx2x_set_aer_mmd(params, phy);
2020
2021 return rc;
2022}
2023
2024static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2025 struct link_params *params,
2026 struct link_vars *vars)
2027{
2028 u8 rc;
2029 vars->phy_flags = PHY_XGXS_FLAG;
2030 if ((phy->req_line_speed &&
2031 ((phy->req_line_speed == SPEED_100) ||
2032 (phy->req_line_speed == SPEED_10))) ||
2033 (!phy->req_line_speed &&
2034 (phy->speed_cap_mask >=
2035 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2036 (phy->speed_cap_mask <
2037 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2038 ))
2039 vars->phy_flags |= PHY_SGMII_FLAG;
2040 else
2041 vars->phy_flags &= ~PHY_SGMII_FLAG;
2042
2043 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2044 bnx2x_set_aer_mmd(params, phy);
2045 bnx2x_set_master_ln(params, phy);
2046
2047 rc = bnx2x_reset_unicore(params, phy, 0);
2048 /* reset the SerDes and wait for reset bit return low */
2049 if (rc != 0)
2050 return rc;
2051
2052 bnx2x_set_aer_mmd(params, phy);
e10bc84d 2053
b7737c9b
YR		 2054 /* setting the masterLn_def again after the reset */
2055 bnx2x_set_master_ln(params, phy);
2056 bnx2x_set_swap_lanes(params, phy);
2057
2058 return rc;
2059}
c18aa15d 2060
ea4e040a 2061/*****************************************************************************/
d90d96ba 2062/* External Phy section */
ea4e040a 2063/*****************************************************************************/
f57a6025 2064void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
ea4e040a
YR		 2065{
2066 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7 2067 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
ea4e040a
YR		 2068 msleep(1);
2069 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
62b29a5d 2070 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
ea4e040a
YR		 2071}
2072
a35da8db 2073static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
c18aa15d 2074 u32 spirom_ver, u32 ver_addr)
a35da8db 2075{
ab6ad5a4
EG		 2076 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
2077 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
c18aa15d
YR		 2078
2079 if (ver_addr)
2080 REG_WR(bp, ver_addr, spirom_ver);
a35da8db
EG		 2081}
2082
c18aa15d 2083static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
e10bc84d 2084 struct bnx2x_phy *phy,
c18aa15d 2085 u8 port)
a35da8db
EG		 2086{
2087 u16 fw_ver1, fw_ver2;
ab6ad5a4 2088
e10bc84d 2089 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
a35da8db 2090 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
e10bc84d 2091 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
a35da8db 2092 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
c18aa15d
YR		 2093 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
2094 phy->ver_addr);
a35da8db
EG		 2095}
2096
c18aa15d
YR		 2097static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
2098 struct link_params *params)
b1607af5
EG		 2099{
2100 u16 val, fw_ver1, fw_ver2, cnt;
e10bc84d
YR		 2101 struct bnx2x *bp = params->bp;
2102
2103 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
b1607af5 2104 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
62b29a5d
YR		 2105 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
2106 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
2107 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
2108 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
2109 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
b1607af5
EG		 2110
2111 for (cnt = 0; cnt < 100; cnt++) {
62b29a5d 2112 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
b1607af5
EG		 2113 if (val & 1)
2114 break;
2115 udelay(5);
2116 }
2117 if (cnt == 100) {
c18aa15d
YR		 2118 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
2119 bnx2x_save_spirom_version(bp, params->port, 0,
2120 phy->ver_addr);
b1607af5
EG		 2121 return;
2122 }
2123
2124
2125 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
62b29a5d
YR		 2126 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
2127 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
2128 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
b1607af5 2129 for (cnt = 0; cnt < 100; cnt++) {
62b29a5d 2130 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
b1607af5
EG		 2131 if (val & 1)
2132 break;
2133 udelay(5);
2134 }
2135 if (cnt == 100) {
62b29a5d
YR		 2136 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
2137 bnx2x_save_spirom_version(bp, params->port, 0,
2138 phy->ver_addr);
b1607af5
EG		 2139 return;
2140 }
2141
2142 /* lower 16 bits of the register SPI_FW_STATUS */
62b29a5d 2143 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
b1607af5 2144 /* upper 16 bits of register SPI_FW_STATUS */
62b29a5d 2145 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
ea4e040a 2146
62b29a5d
YR		 2147 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
2148 phy->ver_addr);
ea4e040a 2149}
e10bc84d 2150static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
ea4e040a
YR		 2151{
2152 /* This is only required for 8073A1, version 102 only */
ea4e040a
YR		 2153 u16 val;
2154
2155 /* Read 8073 HW revision*/
e10bc84d 2156 bnx2x_cl45_read(bp, phy,
ea4e040a 2157 MDIO_PMA_DEVAD,
052a38e0 2158 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2159
2160 if (val != 1) {
2161 /* No need to workaround in 8073 A1 */
2162 return 0;
2163 }
2164
e10bc84d 2165 bnx2x_cl45_read(bp, phy,
ea4e040a
YR		 2166 MDIO_PMA_DEVAD,
2167 MDIO_PMA_REG_ROM_VER2, &val);
2168
2169 /* SNR should be applied only for version 0x102 */
2170 if (val != 0x102)
2171 return 0;
2172
2173 return 1;
2174}
e10bc84d 2175static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
ea4e040a 2176{
ea4e040a
YR		 2177 u16 val, cnt, cnt1 ;
2178
e10bc84d 2179 bnx2x_cl45_read(bp, phy,
ea4e040a 2180 MDIO_PMA_DEVAD,
052a38e0 2181 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2182
2183 if (val > 0) {
2184 /* No need to workaround in 8073 A1 */
2185 return 0;
2186 }
2187 /* XAUI workaround in 8073 A0: */
2188
2189 /* After loading the boot ROM and restarting Autoneg,
2190 poll Dev1, Reg $C820: */
2191
2192 for (cnt = 0; cnt < 1000; cnt++) {
e10bc84d 2193 bnx2x_cl45_read(bp, phy,
ea4e040a 2194 MDIO_PMA_DEVAD,
052a38e0
EG		 2195 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2196 &val);
ea4e040a
YR		 2197 /* If bit [14] = 0 or bit [13] = 0, continue on with
2198 system initialization (XAUI work-around not required,
2199 as these bits indicate 2.5G or 1G link up). */
2200 if (!(val & (1<<14)) || !(val & (1<<13))) {
2201 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2202 return 0;
2203 } else if (!(val & (1<<15))) {
2204 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2205 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2206 it's MSB (bit 15) goes to 1 (indicating that the
2207 XAUI workaround has completed),
2208 then continue on with system initialization.*/
2209 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
e10bc84d 2210 bnx2x_cl45_read(bp, phy,
ea4e040a 2211 MDIO_PMA_DEVAD,
052a38e0 2212 MDIO_PMA_REG_8073_XAUI_WA, &val);
ea4e040a
YR		 2213 if (val & (1<<15)) {
2214 DP(NETIF_MSG_LINK,
2215 "XAUI workaround has completed\n");
2216 return 0;
2217 }
2218 msleep(3);
2219 }
2220 break;
2221 }
2222 msleep(3);
2223 }
2224 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2225 return -EINVAL;
ea4e040a
YR		 2226}
2227
e10bc84d
YR		 2228static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
2229 struct bnx2x_phy *phy,
c18aa15d 2230 u8 port)
ea4e040a 2231{
6bbca910 2232 /* Boot port from external ROM */
ea4e040a 2233 /* EDC grst */
e10bc84d 2234 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 2235 MDIO_PMA_DEVAD,
2236 MDIO_PMA_REG_GEN_CTRL,
2237 0x0001);
2238
2239 /* ucode reboot and rst */
e10bc84d 2240 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 2241 MDIO_PMA_DEVAD,
2242 MDIO_PMA_REG_GEN_CTRL,
2243 0x008c);
2244
e10bc84d 2245 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 2246 MDIO_PMA_DEVAD,
2247 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2248
2249 /* Reset internal microprocessor */
e10bc84d 2250 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 2251 MDIO_PMA_DEVAD,
2252 MDIO_PMA_REG_GEN_CTRL,
2253 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2254
2255 /* Release srst bit */
e10bc84d 2256 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 2257 MDIO_PMA_DEVAD,
2258 MDIO_PMA_REG_GEN_CTRL,
2259 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2260
8ca60a68
YR		 2261 /* wait for 120ms for code download via SPI port */
2262 msleep(120);
ea4e040a
YR		 2263
2264 /* Clear ser_boot_ctl bit */
e10bc84d 2265 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 2266 MDIO_PMA_DEVAD,
2267 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
c18aa15d 2268 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6bbca910 2269}
ea4e040a 2270
e10bc84d
YR		 2271static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
2272 struct link_params *params)
589abe3a
EG		 2273{
2274 struct bnx2x *bp = params->bp;
589abe3a
EG		 2275 /* Need to wait 100ms after reset */
2276 msleep(100);
2277
589abe3a 2278 /* Micro controller re-boot */
e10bc84d 2279 bnx2x_cl45_write(bp, phy,
62b29a5d 2280 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
589abe3a
EG		 2281
2282 /* Set soft reset */
e10bc84d 2283 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2284 MDIO_PMA_DEVAD,
2285 MDIO_PMA_REG_GEN_CTRL,
2286 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2287
e10bc84d 2288 bnx2x_cl45_write(bp, phy,
cc1cb004 2289 MDIO_PMA_DEVAD,
93f72884 2290 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
cc1cb004 2291
e10bc84d 2292 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2293 MDIO_PMA_DEVAD,
2294 MDIO_PMA_REG_GEN_CTRL,
2295 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2296
cc1cb004
EG		 2297 /* wait for 150ms for microcode load */
2298 msleep(150);
589abe3a
EG		 2299
2300 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
e10bc84d 2301 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2302 MDIO_PMA_DEVAD,
2303 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2304
2305 msleep(200);
c18aa15d 2306 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
589abe3a
EG		 2307}
2308
e10bc84d
YR		 2309static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
2310 struct bnx2x_phy *phy,
b7737c9b 2311 u8 port,
e10bc84d 2312 u8 tx_en)
589abe3a
EG		 2313{
2314 u16 val;
ab6ad5a4 2315
b7737c9b
YR		 2316 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
2317 tx_en, port);
589abe3a 2318 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
e10bc84d 2319 bnx2x_cl45_read(bp, phy,
589abe3a
EG		 2320 MDIO_PMA_DEVAD,
2321 MDIO_PMA_REG_PHY_IDENTIFIER,
2322 &val);
2323
2324 if (tx_en)
2325 val &= ~(1<<15);
2326 else
2327 val |= (1<<15);
2328
e10bc84d 2329 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2330 MDIO_PMA_DEVAD,
2331 MDIO_PMA_REG_PHY_IDENTIFIER,
2332 val);
2333}
2334
e10bc84d
YR		 2335static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
2336 struct link_params *params,
4d295db0
EG		 2337 u16 addr, u8 byte_cnt, u8 *o_buf)
2338{
589abe3a 2339 struct bnx2x *bp = params->bp;
4d295db0
EG		 2340 u16 val = 0;
2341 u16 i;
589abe3a
EG		 2342 if (byte_cnt > 16) {
2343 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2344 " is limited to 0xf\n");
2345 return -EINVAL;
2346 }
2347 /* Set the read command byte count */
e10bc84d
YR		 2348 bnx2x_cl45_write(bp, phy,
2349 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
589abe3a
EG		 2350 (byte_cnt | 0xa000));
2351
2352 /* Set the read command address */
e10bc84d
YR		 2353 bnx2x_cl45_write(bp, phy,
2354 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
589abe3a
EG		 2355 addr);
2356
2357 /* Activate read command */
e10bc84d
YR		 2358 bnx2x_cl45_write(bp, phy,
2359 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
589abe3a
EG		 2360 0x2c0f);
2361
2362 /* Wait up to 500us for command complete status */
2363 for (i = 0; i < 100; i++) {
e10bc84d 2364 bnx2x_cl45_read(bp, phy,
589abe3a 2365 MDIO_PMA_DEVAD,
4d295db0
EG		 2366 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2367 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2368 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
589abe3a
EG		 2369 break;
2370 udelay(5);
2371 }
2372
4d295db0
EG		 2373 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2374 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
589abe3a
EG		 2375 DP(NETIF_MSG_LINK,
2376 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4d295db0 2377 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
589abe3a
EG		 2378 return -EINVAL;
2379 }
2380
2381 /* Read the buffer */
2382 for (i = 0; i < byte_cnt; i++) {
e10bc84d 2383 bnx2x_cl45_read(bp, phy,
589abe3a
EG		 2384 MDIO_PMA_DEVAD,
2385 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2386 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2387 }
2388
2389 for (i = 0; i < 100; i++) {
e10bc84d 2390 bnx2x_cl45_read(bp, phy,
589abe3a 2391 MDIO_PMA_DEVAD,
4d295db0
EG		 2392 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2393 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2394 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
e10bc84d 2395 return 0;
4d295db0
EG		 2396 msleep(1);
2397 }
2398 return -EINVAL;
2399}
2400
e10bc84d
YR		 2401static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
2402 struct link_params *params,
4d295db0
EG		 2403 u16 addr, u8 byte_cnt, u8 *o_buf)
2404{
2405 struct bnx2x *bp = params->bp;
2406 u16 val, i;
4d295db0
EG		 2407
2408 if (byte_cnt > 16) {
2409 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2410 " is limited to 0xf\n");
2411 return -EINVAL;
2412 }
2413
2414 /* Need to read from 1.8000 to clear it */
e10bc84d 2415 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 2416 MDIO_PMA_DEVAD,
2417 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2418 &val);
2419
2420 /* Set the read command byte count */
e10bc84d 2421 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 2422 MDIO_PMA_DEVAD,
2423 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2424 ((byte_cnt < 2) ? 2 : byte_cnt));
2425
2426 /* Set the read command address */
e10bc84d 2427 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 2428 MDIO_PMA_DEVAD,
2429 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2430 addr);
2431 /* Set the destination address */
e10bc84d 2432 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 2433 MDIO_PMA_DEVAD,
2434 0x8004,
2435 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2436
2437 /* Activate read command */
e10bc84d 2438 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 2439 MDIO_PMA_DEVAD,
2440 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2441 0x8002);
2442 /* Wait appropriate time for two-wire command to finish before
2443 polling the status register */
2444 msleep(1);
2445
2446 /* Wait up to 500us for command complete status */
2447 for (i = 0; i < 100; i++) {
e10bc84d 2448 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 2449 MDIO_PMA_DEVAD,
2450 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2451 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2452 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2453 break;
2454 udelay(5);
2455 }
2456
2457 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2458 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2459 DP(NETIF_MSG_LINK,
2460 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2461 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2462 return -EINVAL;
2463 }
2464
2465 /* Read the buffer */
2466 for (i = 0; i < byte_cnt; i++) {
e10bc84d 2467 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 2468 MDIO_PMA_DEVAD,
2469 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2470 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2471 }
2472
2473 for (i = 0; i < 100; i++) {
e10bc84d 2474 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 2475 MDIO_PMA_DEVAD,
2476 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2477 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2478 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
589abe3a
EG		 2479 return 0;;
2480 msleep(1);
2481 }
4d295db0 2482
589abe3a
EG		 2483 return -EINVAL;
2484}
2485
e10bc84d
YR		 2486u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
2487 struct link_params *params, u16 addr,
4d295db0
EG		 2488 u8 byte_cnt, u8 *o_buf)
2489{
e10bc84d
YR		 2490 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2491 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4d295db0 2492 byte_cnt, o_buf);
e10bc84d
YR		 2493 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2494 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4d295db0
EG		 2495 byte_cnt, o_buf);
2496 return -EINVAL;
2497}
589abe3a 2498
e10bc84d
YR		 2499static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
2500 struct link_params *params,
4d295db0 2501 u16 *edc_mode)
589abe3a
EG		 2502{
2503 struct bnx2x *bp = params->bp;
4d295db0
EG		 2504 u8 val, check_limiting_mode = 0;
2505 *edc_mode = EDC_MODE_LIMITING;
589abe3a
EG		 2506
2507 /* First check for copper cable */
62b29a5d
YR		 2508 if (bnx2x_read_sfp_module_eeprom(phy,
2509 params,
2510 SFP_EEPROM_CON_TYPE_ADDR,
2511 1,
2512 &val) != 0) {
4d295db0 2513 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
589abe3a
EG		 2514 return -EINVAL;
2515 }
2516
2517 switch (val) {
2518 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
2519 {
2520 u8 copper_module_type;
ab6ad5a4 2521
589abe3a
EG		 2522 /* Check if its active cable( includes SFP+ module)
2523 of passive cable*/
62b29a5d
YR		 2524 if (bnx2x_read_sfp_module_eeprom(phy,
2525 params,
589abe3a
EG		 2526 SFP_EEPROM_FC_TX_TECH_ADDR,
2527 1,
2528 &copper_module_type) !=
2529 0) {
2530 DP(NETIF_MSG_LINK,
2531 "Failed to read copper-cable-type"
2532 " from SFP+ EEPROM\n");
2533 return -EINVAL;
2534 }
2535
2536 if (copper_module_type &
2537 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
2538 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4d295db0 2539 check_limiting_mode = 1;
589abe3a
EG		 2540 } else if (copper_module_type &
2541 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
2542 DP(NETIF_MSG_LINK, "Passive Copper"
2543 " cable detected\n");
4d295db0
EG		 2544 *edc_mode =
2545 EDC_MODE_PASSIVE_DAC;
589abe3a
EG		 2546 } else {
2547 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
2548 "type 0x%x !!!\n", copper_module_type);
2549 return -EINVAL;
2550 }
2551 break;
2552 }
2553 case SFP_EEPROM_CON_TYPE_VAL_LC:
2554 DP(NETIF_MSG_LINK, "Optic module detected\n");
4d295db0 2555 check_limiting_mode = 1;
589abe3a 2556 break;
589abe3a
EG		 2557 default:
2558 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
2559 val);
2560 return -EINVAL;
2561 }
4d295db0
EG		 2562
2563 if (check_limiting_mode) {
2564 u8 options[SFP_EEPROM_OPTIONS_SIZE];
62b29a5d
YR		 2565 if (bnx2x_read_sfp_module_eeprom(phy,
2566 params,
2567 SFP_EEPROM_OPTIONS_ADDR,
2568 SFP_EEPROM_OPTIONS_SIZE,
2569 options) != 0) {
4d295db0
EG		 2570 DP(NETIF_MSG_LINK, "Failed to read Option"
2571 " field from module EEPROM\n");
2572 return -EINVAL;
2573 }
2574 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
2575 *edc_mode = EDC_MODE_LINEAR;
2576 else
2577 *edc_mode = EDC_MODE_LIMITING;
2578 }
2579 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
589abe3a
EG		 2580 return 0;
2581}
589abe3a
EG		 2582/* This function read the relevant field from the module ( SFP+ ),
2583 and verify it is compliant with this board */
e10bc84d
YR		 2584static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
2585 struct link_params *params)
589abe3a
EG		 2586{
2587 struct bnx2x *bp = params->bp;
4d295db0
EG		 2588 u32 val;
2589 u32 fw_resp;
2590 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
2591 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
2592
2593 val = REG_RD(bp, params->shmem_base +
2594 offsetof(struct shmem_region, dev_info.
2595 port_feature_config[params->port].config));
2596 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2597 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
589abe3a
EG		 2598 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
2599 return 0;
2600 }
2601
4d295db0
EG		 2602 /* Ask the FW to validate the module */
2603 if (!(params->feature_config_flags &
2604 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
2605 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
2606 "verification\n");
2607 return -EINVAL;
2608 }
2609
2610 fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
2611 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
2612 DP(NETIF_MSG_LINK, "Approved module\n");
589abe3a
EG		 2613 return 0;
2614 }
2615
4d295db0 2616 /* format the warning message */
62b29a5d
YR		 2617 if (bnx2x_read_sfp_module_eeprom(phy,
2618 params,
589abe3a
EG		 2619 SFP_EEPROM_VENDOR_NAME_ADDR,
2620 SFP_EEPROM_VENDOR_NAME_SIZE,
4d295db0
EG		 2621 (u8 *)vendor_name))
2622 vendor_name[0] = '\0';
2623 else
2624 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
62b29a5d
YR		 2625 if (bnx2x_read_sfp_module_eeprom(phy,
2626 params,
4d295db0
EG		 2627 SFP_EEPROM_PART_NO_ADDR,
2628 SFP_EEPROM_PART_NO_SIZE,
2629 (u8 *)vendor_pn))
2630 vendor_pn[0] = '\0';
2631 else
2632 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
589abe3a 2633
e10bc84d
YR		 2634 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
2635 " Port %d from %s part number %s\n",
7995c64e 2636 params->port, vendor_name, vendor_pn);
589abe3a
EG		 2637 return -EINVAL;
2638}
2639
e10bc84d
YR		 2640static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
2641 struct bnx2x_phy *phy,
62b29a5d 2642 u16 edc_mode)
589abe3a 2643{
cc1cb004 2644 u16 cur_limiting_mode;
cc1cb004 2645
e10bc84d 2646 bnx2x_cl45_read(bp, phy,
cc1cb004
EG		 2647 MDIO_PMA_DEVAD,
2648 MDIO_PMA_REG_ROM_VER2,
2649 &cur_limiting_mode);
2650 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
2651 cur_limiting_mode);
2652
4d295db0 2653 if (edc_mode == EDC_MODE_LIMITING) {
589abe3a 2654 DP(NETIF_MSG_LINK,
4d295db0 2655 "Setting LIMITING MODE\n");
e10bc84d 2656 bnx2x_cl45_write(bp, phy,
62b29a5d
YR		 2657 MDIO_PMA_DEVAD,
2658 MDIO_PMA_REG_ROM_VER2,
2659 EDC_MODE_LIMITING);
589abe3a 2660 } else { /* LRM mode ( default )*/
cc1cb004 2661
4d295db0 2662 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
589abe3a 2663
589abe3a
EG		 2664 /* Changing to LRM mode takes quite few seconds.
2665 So do it only if current mode is limiting
2666 ( default is LRM )*/
4d295db0 2667 if (cur_limiting_mode != EDC_MODE_LIMITING)
589abe3a
EG		 2668 return 0;
2669
e10bc84d 2670 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2671 MDIO_PMA_DEVAD,
2672 MDIO_PMA_REG_LRM_MODE,
2673 0);
e10bc84d 2674 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2675 MDIO_PMA_DEVAD,
2676 MDIO_PMA_REG_ROM_VER2,
2677 0x128);
e10bc84d 2678 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2679 MDIO_PMA_DEVAD,
2680 MDIO_PMA_REG_MISC_CTRL0,
2681 0x4008);
e10bc84d 2682 bnx2x_cl45_write(bp, phy,
589abe3a
EG		 2683 MDIO_PMA_DEVAD,
2684 MDIO_PMA_REG_LRM_MODE,
2685 0xaaaa);
2686 }
2687 return 0;
2688}
2689
e10bc84d
YR		 2690static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
2691 struct bnx2x_phy *phy,
4d295db0
EG		 2692 u16 edc_mode)
2693{
4d295db0
EG		 2694 u16 phy_identifier;
2695 u16 rom_ver2_val;
e10bc84d 2696 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 2697 MDIO_PMA_DEVAD,
2698 MDIO_PMA_REG_PHY_IDENTIFIER,
2699 &phy_identifier);
2700
e10bc84d 2701 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 2702 MDIO_PMA_DEVAD,
2703 MDIO_PMA_REG_PHY_IDENTIFIER,
2704 (phy_identifier & ~(1<<9)));
2705
e10bc84d 2706 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 2707 MDIO_PMA_DEVAD,
2708 MDIO_PMA_REG_ROM_VER2,
2709 &rom_ver2_val);
2710 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
e10bc84d 2711 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 2712 MDIO_PMA_DEVAD,
2713 MDIO_PMA_REG_ROM_VER2,
2714 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
2715
e10bc84d 2716 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 2717 MDIO_PMA_DEVAD,
2718 MDIO_PMA_REG_PHY_IDENTIFIER,
2719 (phy_identifier | (1<<9)));
2720
2721 return 0;
2722}
2723
2724
e10bc84d
YR		 2725static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
2726 struct link_params *params)
2727
589abe3a
EG		 2728{
2729 u8 val;
2730 struct bnx2x *bp = params->bp;
2731 u16 timeout;
2732 /* Initialization time after hot-plug may take up to 300ms for some
2733 phys type ( e.g. JDSU ) */
2734 for (timeout = 0; timeout < 60; timeout++) {
e10bc84d 2735 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
589abe3a
EG		 2736 == 0) {
2737 DP(NETIF_MSG_LINK, "SFP+ module initialization "
2738 "took %d ms\n", timeout * 5);
2739 return 0;
2740 }
2741 msleep(5);
2742 }
2743 return -EINVAL;
2744}
2745
4d295db0 2746static void bnx2x_8727_power_module(struct bnx2x *bp,
e10bc84d
YR		 2747 struct bnx2x_phy *phy,
2748 u8 is_power_up) {
4d295db0
EG		 2749 /* Make sure GPIOs are not using for LED mode */
2750 u16 val;
4d295db0
EG		 2751 /*
2752 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
2753 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
2754 * output
2755 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
2756 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
2757 * where the 1st bit is the over-current(only input), and 2nd bit is
2758 * for power( only output )
2759 */
2760
2761 /*
2762 * In case of NOC feature is disabled and power is up, set GPIO control
2763 * as input to enable listening of over-current indication
2764 */
b7737c9b
YR		 2765 if (phy->flags & FLAGS_NOC)
2766 return;
2767 if (!(phy->flags &
2768 FLAGS_NOC) && is_power_up)
4d295db0
EG		 2769 val = (1<<4);
2770 else
2771 /*
2772 * Set GPIO control to OUTPUT, and set the power bit
2773 * to according to the is_power_up
2774 */
2775 val = ((!(is_power_up)) << 1);
2776
e10bc84d 2777 bnx2x_cl45_write(bp, phy,
62b29a5d
YR		 2778 MDIO_PMA_DEVAD,
2779 MDIO_PMA_REG_8727_GPIO_CTRL,
2780 val);
4d295db0
EG		 2781}
2782
e10bc84d
YR		 2783static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
2784 struct link_params *params)
589abe3a
EG		 2785{
2786 struct bnx2x *bp = params->bp;
4d295db0
EG		 2787 u16 edc_mode;
2788 u8 rc = 0;
e10bc84d 2789
4d295db0
EG		 2790 u32 val = REG_RD(bp, params->shmem_base +
2791 offsetof(struct shmem_region, dev_info.
2792 port_feature_config[params->port].config));
589abe3a
EG		 2793
2794 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
2795 params->port);
2796
e10bc84d 2797 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
589abe3a 2798 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4d295db0 2799 return -EINVAL;
e10bc84d 2800 } else if (bnx2x_verify_sfp_module(phy, params) !=
589abe3a
EG		 2801 0) {
2802 /* check SFP+ module compatibility */
2803 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4d295db0 2804 rc = -EINVAL;
589abe3a
EG		 2805 /* Turn on fault module-detected led */
2806 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
2807 MISC_REGISTERS_GPIO_HIGH,
2808 params->port);
e10bc84d 2809 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
4d295db0
EG		 2810 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2811 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
2812 /* Shutdown SFP+ module */
2813 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
62b29a5d 2814 bnx2x_8727_power_module(bp, phy, 0);
4d295db0
EG		 2815 return rc;
2816 }
2817 } else {
2818 /* Turn off fault module-detected led */
2819 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
2820 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
2821 MISC_REGISTERS_GPIO_LOW,
2822 params->port);
589abe3a
EG		 2823 }
2824
4d295db0 2825 /* power up the SFP module */
e10bc84d 2826 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
62b29a5d 2827 bnx2x_8727_power_module(bp, phy, 1);
589abe3a 2828
4d295db0
EG		 2829 /* Check and set limiting mode / LRM mode on 8726.
2830 On 8727 it is done automatically */
e10bc84d
YR		 2831 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2832 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
4d295db0 2833 else
e10bc84d 2834 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
4d295db0
EG		 2835 /*
2836 * Enable transmit for this module if the module is approved, or
2837 * if unapproved modules should also enable the Tx laser
2838 */
2839 if (rc == 0 ||
2840 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
2841 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
b7737c9b 2842 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4d295db0 2843 else
b7737c9b 2844 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
589abe3a 2845
4d295db0 2846 return rc;
589abe3a
EG		 2847}
2848
2849void bnx2x_handle_module_detect_int(struct link_params *params)
2850{
2851 struct bnx2x *bp = params->bp;
e10bc84d 2852 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
589abe3a
EG		 2853 u32 gpio_val;
2854 u8 port = params->port;
ab6ad5a4 2855
589abe3a
EG		 2856 /* Set valid module led off */
2857 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
2858 MISC_REGISTERS_GPIO_HIGH,
2859 params->port);
2860
2861 /* Get current gpio val refelecting module plugged in / out*/
e10bc84d 2862 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
589abe3a
EG		 2863
2864 /* Call the handling function in case module is detected */
2865 if (gpio_val == 0) {
2866
2867 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
e10bc84d
YR		 2868 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
2869 port);
589abe3a 2870
e10bc84d
YR		 2871 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
2872 bnx2x_sfp_module_detection(phy, params);
589abe3a
EG		 2873 else
2874 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
2875 } else {
4d295db0
EG		 2876 u32 val = REG_RD(bp, params->shmem_base +
2877 offsetof(struct shmem_region, dev_info.
2878 port_feature_config[params->port].
2879 config));
2880
589abe3a 2881 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
62b29a5d
YR		 2882 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
2883 port);
589abe3a
EG		 2884 /* Module was plugged out. */
2885 /* Disable transmit for this module */
4d295db0
EG		 2886 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2887 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
b7737c9b 2888 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
589abe3a
EG		 2889 }
2890}
2891
e10bc84d 2892static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6bbca910 2893{
6bbca910 2894 /* Force KR or KX */
e10bc84d 2895 bnx2x_cl45_write(bp, phy,
62b29a5d 2896 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
e10bc84d 2897 bnx2x_cl45_write(bp, phy,
62b29a5d 2898 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
e10bc84d 2899 bnx2x_cl45_write(bp, phy,
62b29a5d 2900 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
e10bc84d 2901 bnx2x_cl45_write(bp, phy,
62b29a5d 2902 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
ea4e040a 2903}
ab6ad5a4 2904
e10bc84d
YR		 2905static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
2906 struct bnx2x_phy *phy)
ea4e040a 2907{
ea4e040a 2908 u16 val;
e10bc84d 2909 bnx2x_cl45_read(bp, phy,
62b29a5d 2910 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2911
2912 if (val == 0) {
2913 /* Mustn't set low power mode in 8073 A0 */
2914 return;
2915 }
2916
2917 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
e10bc84d 2918 bnx2x_cl45_read(bp, phy,
62b29a5d 2919 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
ea4e040a 2920 val &= ~(1<<13);
e10bc84d 2921 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 2922 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
2923
2924 /* PLL controls */
62b29a5d
YR		 2925 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
2926 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
2927 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
2928 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
2929 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
ea4e040a
YR		 2930
2931 /* Tx Controls */
62b29a5d
YR		 2932 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
2933 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
2934 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
ea4e040a
YR		 2935
2936 /* Rx Controls */
62b29a5d
YR		 2937 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
2938 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
2939 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
ea4e040a
YR		 2940
2941 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
62b29a5d 2942 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
ea4e040a 2943 val |= (1<<13);
62b29a5d 2944 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
ea4e040a 2945}
6bbca910
YR		 2946
2947static void bnx2x_8073_set_pause_cl37(struct link_params *params,
e10bc84d
YR		 2948 struct bnx2x_phy *phy,
2949 struct link_vars *vars)
ea4e040a 2950{
6bbca910 2951 u16 cl37_val;
e10bc84d
YR		 2952 struct bnx2x *bp = params->bp;
2953 bnx2x_cl45_read(bp, phy,
62b29a5d 2954 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6bbca910
YR		 2955
2956 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2957 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
e10bc84d 2958 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6bbca910
YR		 2959 if ((vars->ieee_fc &
2960 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
2961 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
2962 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
2963 }
2964 if ((vars->ieee_fc &
2965 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
2966 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2967 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2968 }
2969 if ((vars->ieee_fc &
2970 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
2971 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2972 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2973 }
2974 DP(NETIF_MSG_LINK,
2975 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
2976
e10bc84d 2977 bnx2x_cl45_write(bp, phy,
62b29a5d 2978 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6bbca910 2979 msleep(500);
ea4e040a
YR		 2980}
2981
2982static void bnx2x_ext_phy_set_pause(struct link_params *params,
e10bc84d
YR		 2983 struct bnx2x_phy *phy,
2984 struct link_vars *vars)
ea4e040a 2985{
ea4e040a 2986 u16 val;
e10bc84d 2987 struct bnx2x *bp = params->bp;
ea4e040a 2988 /* read modify write pause advertizing */
62b29a5d 2989 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
ea4e040a
YR		 2990
2991 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
8c99e7b0 2992
ea4e040a 2993 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7aa0711f 2994 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
8c99e7b0
YR		 2995 if ((vars->ieee_fc &
2996 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
ea4e040a
YR		 2997 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2998 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
2999 }
8c99e7b0
YR		 3000 if ((vars->ieee_fc &
3001 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
ea4e040a 3002 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
62b29a5d 3003 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
ea4e040a 3004 }
62b29a5d
YR		 3005 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3006 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
ea4e040a 3007}
e10bc84d
YR		 3008
3009static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
3010 struct link_params *params)
c2c8b03e 3011{
e10bc84d 3012
c2c8b03e
EG		 3013 u16 bank, i = 0;
3014 struct bnx2x *bp = params->bp;
ea4e040a 3015
c2c8b03e
EG		 3016 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3017 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
e10bc84d 3018 CL45_WR_OVER_CL22(bp, phy,
62b29a5d
YR		 3019 bank,
3020 MDIO_RX0_RX_EQ_BOOST,
b7737c9b 3021 phy->rx_preemphasis[i]);
c2c8b03e
EG		 3022 }
3023
3024 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3025 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
e10bc84d 3026 CL45_WR_OVER_CL22(bp, phy,
62b29a5d
YR		 3027 bank,
3028 MDIO_TX0_TX_DRIVER,
b7737c9b 3029 phy->tx_preemphasis[i]);
c2c8b03e
EG		 3030 }
3031}
57963ed9 3032
c18aa15d 3033static void bnx2x_848xx_set_led(struct bnx2x *bp,
e10bc84d 3034 struct bnx2x_phy *phy)
2f904460 3035{
a1e4be39 3036 u16 val;
e10bc84d
YR		 3037
3038 /* PHYC_CTL_LED_CTL */
3039 bnx2x_cl45_read(bp, phy,
a1e4be39
YR		 3040 MDIO_PMA_DEVAD,
3041 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
3042 val &= 0xFE00;
3043 val |= 0x0092;
2f904460 3044
e10bc84d 3045 bnx2x_cl45_write(bp, phy,
a1e4be39
YR		 3046 MDIO_PMA_DEVAD,
3047 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
2f904460 3048
e10bc84d 3049 bnx2x_cl45_write(bp, phy,
a1e4be39
YR		 3050 MDIO_PMA_DEVAD,
3051 MDIO_PMA_REG_8481_LED1_MASK,
3052 0x80);
2f904460 3053
e10bc84d 3054 bnx2x_cl45_write(bp, phy,
a1e4be39
YR		 3055 MDIO_PMA_DEVAD,
3056 MDIO_PMA_REG_8481_LED2_MASK,
3057 0x18);
2f904460 3058
e10bc84d 3059 bnx2x_cl45_write(bp, phy,
a1e4be39
YR		 3060 MDIO_PMA_DEVAD,
3061 MDIO_PMA_REG_8481_LED3_MASK,
3062 0x0040);
3063
3064 /* 'Interrupt Mask' */
e10bc84d 3065 bnx2x_cl45_write(bp, phy,
a1e4be39
YR		 3066 MDIO_AN_DEVAD,
3067 0xFFFB, 0xFFFD);
2f904460
EG		 3068}
3069
e10bc84d
YR		 3070static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
3071 struct link_params *params,
3072 struct link_vars *vars)
57963ed9
YR		 3073{
3074 struct bnx2x *bp = params->bp;
e10bc84d
YR		 3075 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
3076 (params->loopback_mode == LOOPBACK_XGXS_10));
57963ed9 3077 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
e10bc84d 3078 if (SINGLE_MEDIA_DIRECT(params) &&
c2c8b03e
EG		 3079 (params->feature_config_flags &
3080 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
e10bc84d 3081 bnx2x_set_preemphasis(phy, params);
57963ed9
YR		 3082
3083 /* forced speed requested? */
7846e471 3084 if (vars->line_speed != SPEED_AUTO_NEG ||
e10bc84d 3085 (SINGLE_MEDIA_DIRECT(params) &&
7846e471 3086 params->loopback_mode == LOOPBACK_EXT)) {
57963ed9
YR		 3087 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3088
3089 /* disable autoneg */
e10bc84d 3090 bnx2x_set_autoneg(phy, params, vars, 0);
57963ed9
YR		 3091
3092 /* program speed and duplex */
e10bc84d 3093 bnx2x_program_serdes(phy, params, vars);
57963ed9
YR		 3094
3095 } else { /* AN_mode */
3096 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3097
3098 /* AN enabled */
e10bc84d 3099 bnx2x_set_brcm_cl37_advertisment(phy, params);
57963ed9
YR		 3100
3101 /* program duplex & pause advertisement (for aneg) */
e10bc84d 3102 bnx2x_set_ieee_aneg_advertisment(phy, params,
8c99e7b0 3103 vars->ieee_fc);
57963ed9
YR		 3104
3105 /* enable autoneg */
e10bc84d 3106 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
57963ed9
YR		 3107
3108 /* enable and restart AN */
e10bc84d 3109 bnx2x_restart_autoneg(phy, params, enable_cl73);
57963ed9
YR		 3110 }
3111
3112 } else { /* SGMII mode */
3113 DP(NETIF_MSG_LINK, "SGMII\n");
3114
e10bc84d 3115 bnx2x_initialize_sgmii_process(phy, params, vars);
57963ed9
YR		 3116 }
3117}
3118
b7737c9b
YR		 3119static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
3120 struct bnx2x_phy *phy)
ea4e040a 3121{
b7737c9b 3122 u16 cnt, ctrl;
62b29a5d
YR		 3123 /* Wait for soft reset to get cleared upto 1 sec */
3124 for (cnt = 0; cnt < 1000; cnt++) {
3125 bnx2x_cl45_read(bp, phy,
3126 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
3127 if (!(ctrl & (1<<15)))
3128 break;
3129 msleep(1);
3130 }
3131 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
3132 return cnt;
b7737c9b 3133}
ea4e040a 3134
b7737c9b
YR		 3135static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
3136 struct link_params *params,
3137 struct link_vars *vars)
3138{
3139 struct bnx2x *bp = params->bp;
3140 DP(NETIF_MSG_LINK, "init 8705\n");
3141 /* Restore normal power mode*/
3142 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3143 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3144 /* HW reset */
3145 bnx2x_ext_phy_hw_reset(bp, params->port);
3146 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
3147 bnx2x_wait_reset_complete(bp, phy);
a35da8db 3148
62b29a5d
YR		 3149 bnx2x_cl45_write(bp, phy,
3150 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
3151 bnx2x_cl45_write(bp, phy,
3152 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
3153 bnx2x_cl45_write(bp, phy,
3154 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
3155 bnx2x_cl45_write(bp, phy,
3156 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
3157 /* BCM8705 doesn't have microcode, hence the 0 */
3158 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
3159 return 0;
b7737c9b
YR		 3160}
3161
3162static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
3163 struct link_params *params,
3164 struct link_vars *vars)
3165{
3166 u16 cnt, val;
3167 struct bnx2x *bp = params->bp;
3168 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3169 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3170 /* HW reset */
3171 bnx2x_ext_phy_hw_reset(bp, params->port);
3172 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
b7737c9b 3173 bnx2x_wait_reset_complete(bp, phy);
ea4e040a 3174
62b29a5d
YR		 3175 /* Wait until fw is loaded */
3176 for (cnt = 0; cnt < 100; cnt++) {
3177 bnx2x_cl45_read(bp, phy,
3178 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
3179 if (val)
3180 break;
3181 msleep(10);
3182 }
3183 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
3184 if ((params->feature_config_flags &
3185 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3186 u8 i;
3187 u16 reg;
3188 for (i = 0; i < 4; i++) {
3189 reg = MDIO_XS_8706_REG_BANK_RX0 +
3190 i*(MDIO_XS_8706_REG_BANK_RX1 -
3191 MDIO_XS_8706_REG_BANK_RX0);
3192 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
3193 /* Clear first 3 bits of the control */
3194 val &= ~0x7;
3195 /* Set control bits according to configuration */
3196 val |= (phy->rx_preemphasis[i] & 0x7);
3197 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
3198 " reg 0x%x <-- val 0x%x\n", reg, val);
3199 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
3200 }
3201 }
3202 /* Force speed */
3203 if (phy->req_line_speed == SPEED_10000) {
3204 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3205
3206 bnx2x_cl45_write(bp, phy,
3207 MDIO_PMA_DEVAD,
3208 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
3209 bnx2x_cl45_write(bp, phy,
3210 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
3211 } else {
3212 /* Force 1Gbps using autoneg with 1G advertisment */
3213
3214 /* Allow CL37 through CL73 */
3215 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3216 bnx2x_cl45_write(bp, phy,
3217 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
3218
3219 /* Enable Full-Duplex advertisment on CL37 */
3220 bnx2x_cl45_write(bp, phy,
3221 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
3222 /* Enable CL37 AN */
3223 bnx2x_cl45_write(bp, phy,
3224 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
3225 /* 1G support */
3226 bnx2x_cl45_write(bp, phy,
3227 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
3228
3229 /* Enable clause 73 AN */
3230 bnx2x_cl45_write(bp, phy,
3231 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3232 bnx2x_cl45_write(bp, phy,
3233 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3234 0x0400);
3235 bnx2x_cl45_write(bp, phy,
3236 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
3237 0x0004);
3238 }
c18aa15d 3239 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
62b29a5d 3240 return 0;
b7737c9b
YR		 3241}
3242
3243static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
3244 struct link_params *params,
3245 struct link_vars *vars)
3246{
3247 struct bnx2x *bp = params->bp;
d90d96ba
YR		 3248 u32 val;
3249 u32 swap_val, swap_override, aeu_gpio_mask, offset;
b7737c9b
YR		 3250 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3251 /* Restore normal power mode*/
3252 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3253 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3254
3255 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3256 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3257
3258 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
3259 bnx2x_wait_reset_complete(bp, phy);
3260
62b29a5d 3261 bnx2x_8726_external_rom_boot(phy, params);
4d295db0 3262
62b29a5d
YR		 3263 /* Need to call module detected on initialization since
3264 the module detection triggered by actual module
3265 insertion might occur before driver is loaded, and when
3266 driver is loaded, it reset all registers, including the
3267 transmitter */
3268 bnx2x_sfp_module_detection(phy, params);
3269
3270 if (phy->req_line_speed == SPEED_1000) {
3271 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3272 bnx2x_cl45_write(bp, phy,
3273 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
3274 bnx2x_cl45_write(bp, phy,
3275 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
3276 bnx2x_cl45_write(bp, phy,
3277 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
3278 bnx2x_cl45_write(bp, phy,
3279 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3280 0x400);
3281 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
3282 (phy->speed_cap_mask &
3283 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
3284 ((phy->speed_cap_mask &
3285 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
3286 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
3287 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
3288 /* Set Flow control */
3289 bnx2x_ext_phy_set_pause(params, phy, vars);
3290 bnx2x_cl45_write(bp, phy,
3291 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
3292 bnx2x_cl45_write(bp, phy,
3293 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
3294 bnx2x_cl45_write(bp, phy,
3295 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
3296 bnx2x_cl45_write(bp, phy,
3297 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
3298 bnx2x_cl45_write(bp, phy,
3299 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3300 /* Enable RX-ALARM control to receive
3301 interrupt for 1G speed change */
3302 bnx2x_cl45_write(bp, phy,
3303 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
3304 bnx2x_cl45_write(bp, phy,
3305 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3306 0x400);
3307
3308 } else { /* Default 10G. Set only LASI control */
3309 bnx2x_cl45_write(bp, phy,
3310 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
3311 }
c2c8b03e 3312
62b29a5d
YR		 3313 /* Set TX PreEmphasis if needed */
3314 if ((params->feature_config_flags &
3315 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3316 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3317 "TX_CTRL2 0x%x\n",
b7737c9b
YR		 3318 phy->tx_preemphasis[0],
3319 phy->tx_preemphasis[1]);
62b29a5d
YR		 3320 bnx2x_cl45_write(bp, phy,
3321 MDIO_PMA_DEVAD,
3322 MDIO_PMA_REG_8726_TX_CTRL1,
b7737c9b 3323 phy->tx_preemphasis[0]);
c2c8b03e 3324
62b29a5d
YR		 3325 bnx2x_cl45_write(bp, phy,
3326 MDIO_PMA_DEVAD,
3327 MDIO_PMA_REG_8726_TX_CTRL2,
b7737c9b 3328 phy->tx_preemphasis[1]);
62b29a5d 3329 }
d90d96ba
YR		 3330
3331 /* Set GPIO3 to trigger SFP+ module insertion/removal */
3332 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
3333 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
3334
3335 /* The GPIO should be swapped if the swap register is set and active */
3336 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
3337 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
3338
3339 /* Select function upon port-swap configuration */
3340 if (params->port == 0) {
3341 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
3342 aeu_gpio_mask = (swap_val && swap_override) ?
3343 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
3344 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
3345 } else {
3346 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
3347 aeu_gpio_mask = (swap_val && swap_override) ?
3348 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
3349 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
3350 }
3351 val = REG_RD(bp, offset);
3352 /* add GPIO3 to group */
3353 val |= aeu_gpio_mask;
3354 REG_WR(bp, offset, val);
62b29a5d 3355 return 0;
b7737c9b
YR		 3356
3357}
3358
62b29a5d 3359static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 3360 struct link_params *params,
3361 struct link_vars *vars)
3362{
3363 struct bnx2x *bp = params->bp;
62b29a5d 3364 u16 val = 0, tmp1;
b7737c9b
YR		 3365 u8 gpio_port;
3366 DP(NETIF_MSG_LINK, "Init 8073\n");
3367
3368 gpio_port = params->port;
3369 /* Restore normal power mode*/
3370 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3371 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
3372
3373 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3374 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
3375
62b29a5d
YR		 3376 /* enable LASI */
3377 bnx2x_cl45_write(bp, phy,
3378 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
3379 bnx2x_cl45_write(bp, phy,
3380 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
ea4e040a 3381
62b29a5d 3382 bnx2x_8073_set_pause_cl37(params, phy, vars);
ea4e040a 3383
62b29a5d 3384 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
ea4e040a 3385
62b29a5d
YR		 3386 bnx2x_cl45_read(bp, phy,
3387 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
ea4e040a 3388
62b29a5d
YR		 3389 bnx2x_cl45_read(bp, phy,
3390 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
ea4e040a 3391
62b29a5d 3392 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
ea4e040a 3393
62b29a5d
YR		 3394 /* Enable CL37 BAM */
3395 bnx2x_cl45_read(bp, phy,
3396 MDIO_AN_DEVAD,
3397 MDIO_AN_REG_8073_BAM, &val);
3398 bnx2x_cl45_write(bp, phy,
3399 MDIO_AN_DEVAD,
3400 MDIO_AN_REG_8073_BAM, val | 1);
ea4e040a 3401
62b29a5d
YR		 3402 if (params->loopback_mode == LOOPBACK_EXT) {
3403 bnx2x_807x_force_10G(bp, phy);
3404 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
3405 return 0;
3406 } else {
3407 bnx2x_cl45_write(bp, phy,
3408 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
3409 }
3410 if (phy->req_line_speed != SPEED_AUTO_NEG) {
3411 if (phy->req_line_speed == SPEED_10000) {
3412 val = (1<<7);
3413 } else if (phy->req_line_speed == SPEED_2500) {
3414 val = (1<<5);
3415 /* Note that 2.5G works only
3416 when used with 1G advertisment */
3417 } else
3418 val = (1<<5);
3419 } else {
3420 val = 0;
3421 if (phy->speed_cap_mask &
3422 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3423 val |= (1<<7);
3424
3425 /* Note that 2.5G works only when
3426 used with 1G advertisment */
3427 if (phy->speed_cap_mask &
3428 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3429 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
3430 val |= (1<<5);
3431 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
3432 }
e10bc84d 3433
62b29a5d
YR		 3434 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
3435 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6bbca910 3436
62b29a5d
YR		 3437 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
3438 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
3439 (phy->req_line_speed == SPEED_2500)) {
3440 u16 phy_ver;
3441 /* Allow 2.5G for A1 and above */
3442 bnx2x_cl45_read(bp, phy,
3443 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
3444 &phy_ver);
3445 DP(NETIF_MSG_LINK, "Add 2.5G\n");
3446 if (phy_ver > 0)
3447 tmp1 |= 1;
3448 else
3449 tmp1 &= 0xfffe;
3450 } else {
3451 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
3452 tmp1 &= 0xfffe;
3453 }
6bbca910 3454
62b29a5d
YR		 3455 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
3456 /* Add support for CL37 (passive mode) II */
6bbca910 3457
62b29a5d
YR		 3458 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
3459 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
3460 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
3461 0x20 : 0x40)));
ea4e040a 3462
62b29a5d
YR		 3463 /* Add support for CL37 (passive mode) III */
3464 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6bbca910 3465
62b29a5d
YR		 3466 /* The SNR will improve about 2db by changing
3467 BW and FEE main tap. Rest commands are executed
3468 after link is up*/
3469 if (bnx2x_8073_is_snr_needed(bp, phy))
3470 bnx2x_cl45_write(bp, phy,
3471 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
3472 0xFB0C);
ea4e040a 3473
62b29a5d
YR		 3474 /* Enable FEC (Forware Error Correction) Request in the AN */
3475 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
3476 tmp1 |= (1<<15);
3477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
ea4e040a 3478
62b29a5d 3479 bnx2x_ext_phy_set_pause(params, phy, vars);
ea4e040a 3480
62b29a5d
YR		 3481 /* Restart autoneg */
3482 msleep(500);
3483 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3484 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
3485 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
3486 return 0;
b7737c9b 3487}
4d295db0 3488
c18aa15d 3489
b7737c9b
YR		 3490static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
3491 struct link_params *params,
3492 struct link_vars *vars)
3493{
3494 u16 tmp1, val, mod_abs;
3495 u16 rx_alarm_ctrl_val;
3496 u16 lasi_ctrl_val;
3497 struct bnx2x *bp = params->bp;
3498 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
ea4e040a 3499
62b29a5d
YR		 3500 bnx2x_wait_reset_complete(bp, phy);
3501 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
3502 lasi_ctrl_val = 0x0004;
4d295db0 3503
62b29a5d
YR		 3504 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
3505 /* enable LASI */
3506 bnx2x_cl45_write(bp, phy,
3507 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3508 rx_alarm_ctrl_val);
4d295db0 3509
62b29a5d
YR		 3510 bnx2x_cl45_write(bp, phy,
3511 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
ea4e040a 3512
62b29a5d
YR		 3513 /* Initially configure MOD_ABS to interrupt when
3514 module is presence( bit 8) */
3515 bnx2x_cl45_read(bp, phy,
3516 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
3517 /* Set EDC off by setting OPTXLOS signal input to low
3518 (bit 9).
3519 When the EDC is off it locks onto a reference clock and
3520 avoids becoming 'lost'.*/
3521 mod_abs &= ~((1<<8) | (1<<9));
3522 bnx2x_cl45_write(bp, phy,
3523 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
28577185 3524
4d295db0 3525
62b29a5d
YR		 3526 /* Make MOD_ABS give interrupt on change */
3527 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3528 &val);
3529 val |= (1<<12);
3530 bnx2x_cl45_write(bp, phy,
3531 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
3532 /* Set 8727 GPIOs to input to allow reading from the
3533 8727 GPIO0 status which reflect SFP+ module
3534 over-current */
3535
3536 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3537 &val);
3538 val &= 0xff8f; /* Reset bits 4-6 */
3539 bnx2x_cl45_write(bp, phy,
3540 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
4d295db0 3541
62b29a5d 3542 bnx2x_8727_power_module(bp, phy, 1);
4d295db0 3543
62b29a5d
YR		 3544 bnx2x_cl45_read(bp, phy,
3545 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4d295db0 3546
62b29a5d
YR		 3547 bnx2x_cl45_read(bp, phy,
3548 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4d295db0 3549
62b29a5d
YR		 3550 /* Set option 1G speed */
3551 if (phy->req_line_speed == SPEED_1000) {
3552 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3553 bnx2x_cl45_write(bp, phy,
3554 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
3555 bnx2x_cl45_write(bp, phy,
3556 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
3557 bnx2x_cl45_read(bp, phy,
3558 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
3559 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
3560 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
3561 ((phy->speed_cap_mask &
3562 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
3563 ((phy->speed_cap_mask &
3564 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
3565 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
3566
3567 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
3568 bnx2x_cl45_write(bp, phy,
3569 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
3570 bnx2x_cl45_write(bp, phy,
3571 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
3572 } else {
3573 /**
3574 * Since the 8727 has only single reset pin, need to set the 10G
3575 * registers although it is default
3576 */
3577 bnx2x_cl45_write(bp, phy,
3578 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
3579 0x0020);
3580 bnx2x_cl45_write(bp, phy,
3581 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
3582 bnx2x_cl45_write(bp, phy,
3583 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
3584 bnx2x_cl45_write(bp, phy,
3585 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
3586 0x0008);
3587 }
4d295db0 3588
62b29a5d
YR		 3589
3590 /* Set 2-wire transfer rate of SFP+ module EEPROM
3591 * to 100Khz since some DACs(direct attached cables) do
3592 * not work at 400Khz.
3593 */
3594 bnx2x_cl45_write(bp, phy,
3595 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
3596 0xa001);
3597
3598 /* Set TX PreEmphasis if needed */
3599 if ((params->feature_config_flags &
3600 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3601 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
3602 phy->tx_preemphasis[0],
b7737c9b 3603 phy->tx_preemphasis[1]);
62b29a5d
YR		 3604 bnx2x_cl45_write(bp, phy,
3605 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
3606 phy->tx_preemphasis[0]);
4d295db0 3607
62b29a5d
YR		 3608 bnx2x_cl45_write(bp, phy,
3609 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
3610 phy->tx_preemphasis[1]);
3611 }
3612
3613 return 0;
b7737c9b
YR		 3614}
3615
3616static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
3617 struct link_params *params,
3618 struct link_vars *vars)
3619{
3620 u16 fw_ver1, fw_ver2, val;
3621 struct bnx2x *bp = params->bp;
3622 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
3623
3624 /* Restore normal power mode*/
3625 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3626 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3627 /* HW reset */
3628 bnx2x_ext_phy_hw_reset(bp, params->port);
62b29a5d 3629 bnx2x_wait_reset_complete(bp, phy);
4d295db0 3630
62b29a5d
YR		 3631 bnx2x_cl45_write(bp, phy,
3632 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
3633 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
3634 bnx2x_cl45_write(bp, phy,
3635 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4d295db0 3636
62b29a5d
YR		 3637 bnx2x_ext_phy_set_pause(params, phy, vars);
3638 /* Restart autoneg */
3639 bnx2x_cl45_read(bp, phy,
3640 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
3641 val |= 0x200;
3642 bnx2x_cl45_write(bp, phy,
3643 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
a35da8db 3644
62b29a5d
YR		 3645 /* Save spirom version */
3646 bnx2x_cl45_read(bp, phy,
3647 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
a35da8db 3648
62b29a5d
YR		 3649 bnx2x_cl45_read(bp, phy,
3650 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
3651 bnx2x_save_spirom_version(bp, params->port,
3652 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
3653 return 0;
b7737c9b
YR		 3654}
3655
3656static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
3657 struct link_params *params,
3658 struct link_vars *vars)
3659{
3660 struct bnx2x *bp = params->bp;
62b29a5d
YR		 3661 u16 autoneg_val, an_1000_val, an_10_100_val;
3662 bnx2x_wait_reset_complete(bp, phy);
3663 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
3664 1 << NIG_LATCH_BC_ENABLE_MI_INT);
3665
3666 bnx2x_cl45_write(bp, phy,
3667 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
c18aa15d 3668 bnx2x_848xx_set_led(bp, phy);
62b29a5d
YR		 3669 /* set 1000 speed advertisement */
3670 bnx2x_cl45_read(bp, phy,
3671 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
3672 &an_1000_val);
a1e4be39 3673
62b29a5d
YR		 3674 bnx2x_ext_phy_set_pause(params, phy, vars);
3675 bnx2x_cl45_read(bp, phy,
3676 MDIO_AN_DEVAD,
3677 MDIO_AN_REG_8481_LEGACY_AN_ADV,
3678 &an_10_100_val);
3679 bnx2x_cl45_read(bp, phy,
3680 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
3681 &autoneg_val);
3682 /* Disable forced speed */
3683 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
3684 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
3685
3686 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3687 (phy->speed_cap_mask &
3688 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3689 (phy->req_line_speed == SPEED_1000)) {
3690 an_1000_val |= (1<<8);
3691 autoneg_val |= (1<<9 | 1<<12);
3692 if (phy->req_duplex == DUPLEX_FULL)
3693 an_1000_val |= (1<<9);
3694 DP(NETIF_MSG_LINK, "Advertising 1G\n");
3695 } else
3696 an_1000_val &= ~((1<<8) | (1<<9));
2f904460 3697
62b29a5d
YR		 3698 bnx2x_cl45_write(bp, phy,
3699 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
3700 an_1000_val);
3701
3702 /* set 10 speed advertisement */
3703 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3704 (phy->speed_cap_mask &
3705 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
3706 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
3707 an_10_100_val |= (1<<7);
3708 /* Enable autoneg and restart autoneg for legacy speeds */
3709 autoneg_val |= (1<<9 | 1<<12);
3710
3711 if (phy->req_duplex == DUPLEX_FULL)
3712 an_10_100_val |= (1<<8);
3713 DP(NETIF_MSG_LINK, "Advertising 100M\n");
3714 }
3715 /* set 10 speed advertisement */
3716 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3717 (phy->speed_cap_mask &
3718 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
3719 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
3720 an_10_100_val |= (1<<5);
3721 autoneg_val |= (1<<9 | 1<<12);
3722 if (phy->req_duplex == DUPLEX_FULL)
3723 an_10_100_val |= (1<<6);
3724 DP(NETIF_MSG_LINK, "Advertising 10M\n");
3725 }
4f60dab1 3726
62b29a5d
YR		 3727 /* Only 10/100 are allowed to work in FORCE mode */
3728 if (phy->req_line_speed == SPEED_100) {
3729 autoneg_val |= (1<<13);
3730 /* Enabled AUTO-MDIX when autoneg is disabled */
3731 bnx2x_cl45_write(bp, phy,
3732 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
3733 (1<<15 | 1<<9 | 7<<0));
3734 DP(NETIF_MSG_LINK, "Setting 100M force\n");
3735 }
3736 if (phy->req_line_speed == SPEED_10) {
3737 /* Enabled AUTO-MDIX when autoneg is disabled */
3738 bnx2x_cl45_write(bp, phy,
3739 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
3740 (1<<15 | 1<<9 | 7<<0));
3741 DP(NETIF_MSG_LINK, "Setting 10M force\n");
3742 }
2f904460 3743
62b29a5d
YR		 3744 bnx2x_cl45_write(bp, phy,
3745 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
3746 an_10_100_val);
2f904460 3747
62b29a5d
YR		 3748 if (phy->req_duplex == DUPLEX_FULL)
3749 autoneg_val |= (1<<8);
2f904460 3750
62b29a5d
YR		 3751 bnx2x_cl45_write(bp, phy,
3752 MDIO_AN_DEVAD,
3753 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
46d15cc7 3754
62b29a5d
YR		 3755 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3756 (phy->speed_cap_mask &
3757 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3758 (phy->req_line_speed == SPEED_10000)) {
3759 DP(NETIF_MSG_LINK, "Advertising 10G\n");
3760 /* Restart autoneg for 10G*/
2f904460 3761
62b29a5d
YR		 3762 bnx2x_cl45_write(bp, phy,
3763 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
3764 0x3200);
3765 } else if (phy->req_line_speed != SPEED_10 &&
3766 phy->req_line_speed != SPEED_100) {
3767 bnx2x_cl45_write(bp, phy,
3768 MDIO_AN_DEVAD,
3769 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
3770 1);
3771 }
3772 /* Save spirom version */
c18aa15d 3773 bnx2x_save_848xx_spirom_version(phy, params);
2f904460 3774
62b29a5d 3775 return 0;
b7737c9b 3776}
ea4e040a 3777
b7737c9b
YR		 3778static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
3779 struct link_params *params,
3780 struct link_vars *vars)
3781{
3782 struct bnx2x *bp = params->bp;
3783 u16 temp;
3784 msleep(1);
3785 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
3786 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
3787 params->port);
3788 msleep(200); /* 100 is not enough */
3789
3790 /**
3791 * BCM84823 requires that XGXS links up first @ 10G for normal
3792 * behavior
3793 */
3794 temp = vars->line_speed;
3795 vars->line_speed = SPEED_10000;
3796 bnx2x_set_autoneg(phy, params, vars, 0);
3797 bnx2x_program_serdes(phy, params, vars);
3798 vars->line_speed = temp;
3799 return bnx2x_848xx_cmn_config_init(phy, params, vars);
ea4e040a
YR		 3800}
3801
b7737c9b
YR		 3802static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
3803 struct link_params *params,
3804 struct link_vars *vars)
3805{
3806 struct bnx2x *bp = params->bp;
3807 /* Restore normal power mode*/
3808 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3809 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3810
3811 /* HW reset */
3812 bnx2x_ext_phy_hw_reset(bp, params->port);
3813
3814 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
3815 return bnx2x_848xx_cmn_config_init(phy, params, vars);
3816}
7aa0711f
YR		 3817
3818
3819static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3820 struct bnx2x_phy *phy,
3821 struct link_vars *vars)
3822{
3823 u16 val;
3824 bnx2x_cl45_read(bp, phy,
3825 MDIO_AN_DEVAD,
3826 MDIO_AN_REG_STATUS, &val);
3827 bnx2x_cl45_read(bp, phy,
3828 MDIO_AN_DEVAD,
3829 MDIO_AN_REG_STATUS, &val);
3830 if (val & (1<<5))
3831 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3832 if ((val & (1<<0)) == 0)
3833 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3834}
e10bc84d
YR		 3835static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
3836 struct link_params *params)
4d295db0
EG		 3837{
3838 struct bnx2x *bp = params->bp;
3839 u16 mod_abs, rx_alarm_status;
4d295db0
EG		 3840 u32 val = REG_RD(bp, params->shmem_base +
3841 offsetof(struct shmem_region, dev_info.
3842 port_feature_config[params->port].
3843 config));
e10bc84d 3844 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 3845 MDIO_PMA_DEVAD,
3846 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
3847 if (mod_abs & (1<<8)) {
3848
3849 /* Module is absent */
3850 DP(NETIF_MSG_LINK, "MOD_ABS indication "
3851 "show module is absent\n");
3852
3853 /* 1. Set mod_abs to detect next module
3854 presence event
3855 2. Set EDC off by setting OPTXLOS signal input to low
3856 (bit 9).
3857 When the EDC is off it locks onto a reference clock and
3858 avoids becoming 'lost'.*/
3859 mod_abs &= ~((1<<8)|(1<<9));
e10bc84d 3860 bnx2x_cl45_write(bp, phy,
4d295db0
EG		 3861 MDIO_PMA_DEVAD,
3862 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
3863
3864 /* Clear RX alarm since it stays up as long as
3865 the mod_abs wasn't changed */
e10bc84d 3866 bnx2x_cl45_read(bp, phy,
4d295db0
EG		 3867 MDIO_PMA_DEVAD,
3868 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
3869
3870 } else {
3871 /* Module is present */
3872 DP(NETIF_MSG_LINK, "MOD_ABS indication "
3873 "show module is present\n");
3874 /* First thing, disable transmitter,
3875 and if the module is ok, the
3876 module_detection will enable it*/
3877
3878 /* 1. Set mod_abs to detect next module
3879 absent event ( bit 8)
3880 2. Restore the default polarity of the OPRXLOS signal and
3881 this signal will then correctly indicate the presence or
3882 absence of the Rx signal. (bit 9) */
3883 mod_abs |= ((1<<8)|(1<<9));
e10bc84d 3884 bnx2x_cl45_write(bp, phy,
62b29a5d
YR		 3885 MDIO_PMA_DEVAD,
3886 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4d295db0
EG		 3887
3888 /* Clear RX alarm since it stays up as long as
3889 the mod_abs wasn't changed. This is need to be done
3890 before calling the module detection, otherwise it will clear
3891 the link update alarm */
e10bc84d 3892 bnx2x_cl45_read(bp, phy,
62b29a5d
YR		 3893 MDIO_PMA_DEVAD,
3894 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4d295db0
EG		 3895
3896
3897 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3898 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
b7737c9b 3899 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4d295db0 3900
e10bc84d
YR		 3901 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
3902 bnx2x_sfp_module_detection(phy, params);
4d295db0
EG		 3903 else
3904 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3905 }
3906
3907 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
3908 rx_alarm_status);
3909 /* No need to check link status in case of
3910 module plugged in/out */
3911}
3912
c18aa15d 3913
b7737c9b 3914static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
e10bc84d 3915 struct link_params *params,
b7737c9b 3916 struct link_vars *vars)
ea4e040a 3917{
62b29a5d 3918 u8 link_up = 0;
b7737c9b
YR		 3919 u16 val1, rx_sd;
3920 struct bnx2x *bp = params->bp;
62b29a5d
YR		 3921 DP(NETIF_MSG_LINK, "read status 8705\n");
3922 bnx2x_cl45_read(bp, phy,
3923 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
3924 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
ea4e040a 3925
62b29a5d
YR		 3926 bnx2x_cl45_read(bp, phy,
3927 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
3928 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
ea4e040a 3929
62b29a5d
YR		 3930 bnx2x_cl45_read(bp, phy,
3931 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4d295db0 3932
62b29a5d
YR		 3933 bnx2x_cl45_read(bp, phy,
3934 MDIO_PMA_DEVAD, 0xc809, &val1);
3935 bnx2x_cl45_read(bp, phy,
3936 MDIO_PMA_DEVAD, 0xc809, &val1);
4d295db0 3937
62b29a5d
YR		 3938 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
3939 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
3940 if (link_up) {
3941 vars->line_speed = SPEED_10000;
3942 bnx2x_ext_phy_resolve_fc(phy, params, vars);
3943 }
3944 return link_up;
b7737c9b 3945}
ea4e040a 3946
b7737c9b
YR		 3947static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
3948 struct link_params *params,
3949 struct link_vars *vars)
3950{
3951 u8 link_up = 0;
3952 u16 val1, val2, rx_sd, pcs_status;
3953 struct bnx2x *bp = params->bp;
62b29a5d
YR		 3954 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
3955 /* Clear RX Alarm*/
3956 bnx2x_cl45_read(bp, phy,
3957 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
3958 /* clear LASI indication*/
3959 bnx2x_cl45_read(bp, phy,
3960 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
3961 bnx2x_cl45_read(bp, phy,
3962 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
3963 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
ea4e040a 3964
62b29a5d
YR		 3965 bnx2x_cl45_read(bp, phy,
3966 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
3967 bnx2x_cl45_read(bp, phy,
3968 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
3969 bnx2x_cl45_read(bp, phy,
3970 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
3971 bnx2x_cl45_read(bp, phy,
3972 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
3973
3974 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
3975 " link_status 0x%x\n", rx_sd, pcs_status, val2);
3976 /* link is up if both bit 0 of pmd_rx_sd and
3977 * bit 0 of pcs_status are set, or if the autoneg bit
3978 * 1 is set
3979 */
3980 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
3981 if (link_up) {
3982 if (val2 & (1<<1))
3983 vars->line_speed = SPEED_1000;
3984 else
3985 vars->line_speed = SPEED_10000;
3986 bnx2x_ext_phy_resolve_fc(phy, params, vars);
3987 }
3988 return link_up;
b7737c9b 3989}
b7737c9b
YR		 3990static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
3991 struct link_params *params,
3992 struct link_vars *vars)
3993{
3994 return bnx2x_8706_8726_read_status(phy, params, vars);
3995}
3996
3997static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
3998 struct link_params *params,
3999 struct link_vars *vars)
4000{
4001 struct bnx2x *bp = params->bp;
4002 u16 val1;
4003 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
4004 if (link_up) {
4005 bnx2x_cl45_read(bp, phy,
4006 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
4007 &val1);
4008 if (val1 & (1<<15)) {
4009 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4010 link_up = 0;
4011 vars->line_speed = 0;
4012 }
4013 }
4014 return link_up;
4015}
c18aa15d 4016
b7737c9b
YR		 4017static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
4018 struct link_params *params,
4019 struct link_vars *vars)
4020
4021{
4022 struct bnx2x *bp = params->bp;
62b29a5d
YR		 4023 u8 link_up = 0;
4024 u16 link_status = 0;
4025 u16 rx_alarm_status, val1;
4026 /* Check the LASI */
4027 bnx2x_cl45_read(bp, phy,
4028 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4029 &rx_alarm_status);
4030 vars->line_speed = 0;
4031 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
4d295db0 4032
62b29a5d
YR		 4033 bnx2x_cl45_read(bp, phy,
4034 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4d295db0 4035
62b29a5d 4036 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
4d295db0 4037
62b29a5d
YR		 4038 /* Clear MSG-OUT */
4039 bnx2x_cl45_read(bp, phy,
4040 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4d295db0 4041
62b29a5d
YR		 4042 /**
4043 * If a module is present and there is need to check
4044 * for over current
4045 */
4046 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
4047 /* Check over-current using 8727 GPIO0 input*/
4048 bnx2x_cl45_read(bp, phy,
4049 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
4050 &val1);
4051
4052 if ((val1 & (1<<8)) == 0) {
4053 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
4054 " on port %d\n", params->port);
4055 netdev_err(bp->dev, "Error: Power fault on Port %d has"
4056 " been detected and the power to "
4057 "that SFP+ module has been removed"
4058 " to prevent failure of the card."
4059 " Please remove the SFP+ module and"
4060 " restart the system to clear this"
4061 " error.\n",
4062 params->port);
4d295db0
EG		 4063
4064 /*
62b29a5d
YR		 4065 * Disable all RX_ALARMs except for
4066 * mod_abs
4d295db0 4067 */
62b29a5d
YR		 4068 bnx2x_cl45_write(bp, phy,
4069 MDIO_PMA_DEVAD,
4070 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
4d295db0 4071
e10bc84d 4072 bnx2x_cl45_read(bp, phy,
62b29a5d
YR		 4073 MDIO_PMA_DEVAD,
4074 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
4075 /* Wait for module_absent_event */
4076 val1 |= (1<<8);
4077 bnx2x_cl45_write(bp, phy,
4078 MDIO_PMA_DEVAD,
4079 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
4080 /* Clear RX alarm */
e10bc84d 4081 bnx2x_cl45_read(bp, phy,
62b29a5d
YR		 4082 MDIO_PMA_DEVAD,
4083 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4084 return 0;
4085 }
4086 } /* Over current check */
4d295db0 4087
62b29a5d
YR		 4088 /* When module absent bit is set, check module */
4089 if (rx_alarm_status & (1<<5)) {
4090 bnx2x_8727_handle_mod_abs(phy, params);
4091 /* Enable all mod_abs and link detection bits */
4092 bnx2x_cl45_write(bp, phy,
4093 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4094 ((1<<5) | (1<<2)));
4095 }
4096
4097 /* If transmitter is disabled, ignore false link up indication */
4098 bnx2x_cl45_read(bp, phy,
4099 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
4100 if (val1 & (1<<15)) {
4101 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4102 return 0;
4103 }
4104
4105 bnx2x_cl45_read(bp, phy,
4106 MDIO_PMA_DEVAD,
4107 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
4108
4109 /* Bits 0..2 --> speed detected,
4110 bits 13..15--> link is down */
4111 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4112 link_up = 1;
4113 vars->line_speed = SPEED_10000;
4114 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4115 link_up = 1;
4116 vars->line_speed = SPEED_1000;
4117 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4118 params->port);
4119 } else {
4120 link_up = 0;
4121 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4122 params->port);
4123 }
4124 if (link_up)
4125 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4126 return link_up;
b7737c9b 4127}
62b29a5d 4128
7aa0711f
YR		 4129static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
4130 struct link_params *params,
4131 struct link_vars *vars)
4132{
4133 struct bnx2x *bp = params->bp;
4134 if (phy->req_line_speed == SPEED_10 ||
4135 phy->req_line_speed == SPEED_100) {
4136 vars->flow_ctrl = phy->req_flow_ctrl;
4137 return;
4138 }
4139
4140 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
4141 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
4142 u16 pause_result;
4143 u16 ld_pause; /* local */
4144 u16 lp_pause; /* link partner */
4145 bnx2x_cl45_read(bp, phy,
4146 MDIO_AN_DEVAD,
4147 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
4148
4149 bnx2x_cl45_read(bp, phy,
4150 MDIO_AN_DEVAD,
4151 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
4152 pause_result = (ld_pause &
4153 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
4154 pause_result |= (lp_pause &
4155 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
4156
4157 bnx2x_pause_resolve(vars, pause_result);
4158 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
4159 pause_result);
4160 }
4161}
b7737c9b
YR		 4162static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4163 struct link_params *params,
4164 struct link_vars *vars)
4165{
4166 struct bnx2x *bp = params->bp;
62b29a5d 4167 u8 link_up = 0;
b7737c9b 4168 u16 val1, val2;
62b29a5d
YR		 4169 u16 link_status = 0;
4170 u16 an1000_status = 0;
ab6ad5a4 4171
62b29a5d
YR		 4172 bnx2x_cl45_read(bp, phy,
4173 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
ea4e040a 4174
62b29a5d 4175 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
ea4e040a 4176
62b29a5d
YR		 4177 /* clear the interrupt LASI status register */
4178 bnx2x_cl45_read(bp, phy,
4179 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4180 bnx2x_cl45_read(bp, phy,
4181 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4182 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4183 /* Clear MSG-OUT */
4184 bnx2x_cl45_read(bp, phy,
4185 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6bbca910 4186
62b29a5d
YR		 4187 /* Check the LASI */
4188 bnx2x_cl45_read(bp, phy,
4189 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
6bbca910 4190
62b29a5d 4191 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
6bbca910 4192
62b29a5d
YR		 4193 /* Check the link status */
4194 bnx2x_cl45_read(bp, phy,
4195 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4196 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
ea4e040a 4197
62b29a5d
YR		 4198 bnx2x_cl45_read(bp, phy,
4199 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4200 bnx2x_cl45_read(bp, phy,
4201 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4202 link_up = ((val1 & 4) == 4);
4203 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
6bbca910 4204
62b29a5d
YR		 4205 if (link_up &&
4206 ((phy->req_line_speed != SPEED_10000))) {
4207 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4208 return 0;
4209 }
4210 bnx2x_cl45_read(bp, phy,
4211 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4212 bnx2x_cl45_read(bp, phy,
4213 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4214
4215 /* Check the link status on 1.1.2 */
4216 bnx2x_cl45_read(bp, phy,
4217 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4218 bnx2x_cl45_read(bp, phy,
4219 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4220 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4221 "an_link_status=0x%x\n", val2, val1, an1000_status);
4222
4223 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4224 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4225 /* The SNR will improve about 2dbby
4226 changing the BW and FEE main tap.*/
4227 /* The 1st write to change FFE main
4228 tap is set before restart AN */
4229 /* Change PLL Bandwidth in EDC
4230 register */
4231 bnx2x_cl45_write(bp, phy,
4232 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4233 0x26BC);
4234
4235 /* Change CDR Bandwidth in EDC register */
4236 bnx2x_cl45_write(bp, phy,
4237 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4238 0x0333);
4239 }
4240 bnx2x_cl45_read(bp, phy,
4241 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4242 &link_status);
4243
4244 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4245 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4246 link_up = 1;
4247 vars->line_speed = SPEED_10000;
4248 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4249 params->port);
4250 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4251 link_up = 1;
4252 vars->line_speed = SPEED_2500;
4253 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4254 params->port);
4255 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4256 link_up = 1;
4257 vars->line_speed = SPEED_1000;
4258 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4259 params->port);
4260 } else {
4261 link_up = 0;
4262 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4263 params->port);
4264 }
6bbca910 4265
7aa0711f
YR		 4266 if (link_up) {
4267 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4268 bnx2x_8073_resolve_fc(phy, params, vars);
4269 }
62b29a5d 4270 return link_up;
b7737c9b
YR		 4271}
4272
4273static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
4274 struct link_params *params,
4275 struct link_vars *vars)
4276{
4277 struct bnx2x *bp = params->bp;
62b29a5d 4278 u8 link_up;
b7737c9b 4279 u16 val1, val2;
62b29a5d
YR		 4280 bnx2x_cl45_read(bp, phy,
4281 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
4282 bnx2x_cl45_read(bp, phy,
4283 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4284 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
4285 val2, val1);
4286 bnx2x_cl45_read(bp, phy,
4287 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4288 bnx2x_cl45_read(bp, phy,
4289 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4290 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
4291 val2, val1);
4292 link_up = ((val1 & 4) == 4);
4293 /* if link is up
4294 * print the AN outcome of the SFX7101 PHY
4295 */
4296 if (link_up) {
4297 bnx2x_cl45_read(bp, phy,
4298 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
4299 &val2);
4300 vars->line_speed = SPEED_10000;
4301 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
4302 val2, (val2 & (1<<14)));
7aa0711f
YR		 4303 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4304 bnx2x_ext_phy_resolve_fc(phy, params, vars);
62b29a5d
YR		 4305 }
4306 return link_up;
b7737c9b
YR		 4307}
4308
4309static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
4310 struct link_params *params,
4311 struct link_vars *vars)
4312{
4313 struct bnx2x *bp = params->bp;
62b29a5d
YR		 4314 u16 val, val1, val2;
4315 u8 link_up = 0;
b7737c9b 4316
62b29a5d
YR		 4317 /* Check 10G-BaseT link status */
4318 /* Check PMD signal ok */
4319 bnx2x_cl45_read(bp, phy,
4320 MDIO_AN_DEVAD, 0xFFFA, &val1);
4321 bnx2x_cl45_read(bp, phy,
4322 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
4323 &val2);
4324 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
4325
4326 /* Check link 10G */
4327 if (val2 & (1<<11)) {
4328 vars->line_speed = SPEED_10000;
4329 link_up = 1;
7aa0711f 4330 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
62b29a5d
YR		 4331 } else { /* Check Legacy speed link */
4332 u16 legacy_status, legacy_speed;
4333
4334 /* Enable expansion register 0x42 (Operation mode status) */
4335 bnx2x_cl45_write(bp, phy,
4336 MDIO_AN_DEVAD,
4337 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
4338
4339 /* Get legacy speed operation status */
4340 bnx2x_cl45_read(bp, phy,
4341 MDIO_AN_DEVAD,
4342 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
4343 &legacy_status);
4344
4345 DP(NETIF_MSG_LINK, "Legacy speed status"
4346 " = 0x%x\n", legacy_status);
4347 link_up = ((legacy_status & (1<<11)) == (1<<11));
4348 if (link_up) {
4349 legacy_speed = (legacy_status & (3<<9));
4350 if (legacy_speed == (0<<9))
4351 vars->line_speed = SPEED_10;
4352 else if (legacy_speed == (1<<9))
4353 vars->line_speed = SPEED_100;
4354 else if (legacy_speed == (2<<9))
4355 vars->line_speed = SPEED_1000;
4356 else /* Should not happen */
4357 vars->line_speed = 0;
4358
4359 if (legacy_status & (1<<8))
4360 vars->duplex = DUPLEX_FULL;
4361 else
4362 vars->duplex = DUPLEX_HALF;
4363
4364 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
4365 " is_duplex_full= %d\n", vars->line_speed,
4366 (vars->duplex == DUPLEX_FULL));
4367
4368 /* Check legacy speed AN resolution */
e10bc84d 4369 bnx2x_cl45_read(bp, phy,
62b29a5d
YR		 4370 MDIO_AN_DEVAD,
4371 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
4372 &val);
4373 if (val & (1<<5))
4374 vars->link_status |=
4375 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
e10bc84d 4376 bnx2x_cl45_read(bp, phy,
62b29a5d
YR		 4377 MDIO_AN_DEVAD,
4378 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
4379 &val);
4380 if ((val & (1<<0)) == 0)
4381 vars->link_status |=
4382 LINK_STATUS_PARALLEL_DETECTION_USED;
4383 }
4384 }
7aa0711f
YR		 4385 if (link_up) {
4386 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
4387 vars->line_speed);
4388 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4389 }
4390
62b29a5d 4391 return link_up;
ea4e040a 4392}
c18aa15d 4393
ea4e040a
YR		 4394static void bnx2x_link_int_enable(struct link_params *params)
4395{
4396 u8 port = params->port;
ea4e040a
YR		 4397 u32 mask;
4398 struct bnx2x *bp = params->bp;
ab6ad5a4 4399
ea4e040a
YR		 4400 /* setting the status to report on link up
4401 for either XGXS or SerDes */
4402
4403 if (params->switch_cfg == SWITCH_CFG_10G) {
4404 mask = (NIG_MASK_XGXS0_LINK10G |
4405 NIG_MASK_XGXS0_LINK_STATUS);
4406 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
e10bc84d
YR		 4407 if (!(SINGLE_MEDIA_DIRECT(params)) &&
4408 params->phy[INT_PHY].type !=
4409 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
ea4e040a
YR		 4410 mask |= NIG_MASK_MI_INT;
4411 DP(NETIF_MSG_LINK, "enabled external phy int\n");
4412 }
4413
4414 } else { /* SerDes */
4415 mask = NIG_MASK_SERDES0_LINK_STATUS;
4416 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
e10bc84d
YR		 4417 if (!(SINGLE_MEDIA_DIRECT(params)) &&
4418 params->phy[INT_PHY].type !=
4419 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
ea4e040a
YR		 4420 mask |= NIG_MASK_MI_INT;
4421 DP(NETIF_MSG_LINK, "enabled external phy int\n");
4422 }
4423 }
4424 bnx2x_bits_en(bp,
4425 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
4426 mask);
ab6ad5a4
EG		 4427
4428 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
ea4e040a
YR		 4429 (params->switch_cfg == SWITCH_CFG_10G),
4430 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
ea4e040a
YR		 4431 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
4432 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
4433 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
4434 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
4435 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
4436 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
4437 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4438}
4439
2f904460
EG		 4440static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
4441 u8 is_mi_int)
4442{
4443 u32 latch_status = 0, is_mi_int_status;
4444 /* Disable the MI INT ( external phy int )
4445 * by writing 1 to the status register. Link down indication
4446 * is high-active-signal, so in this case we need to write the
4447 * status to clear the XOR
4448 */
4449 /* Read Latched signals */
4450 latch_status = REG_RD(bp,
4451 NIG_REG_LATCH_STATUS_0 + port*8);
4452 is_mi_int_status = REG_RD(bp,
4453 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
4454 DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
4455 "latch_status = 0x%x\n",
4456 is_mi_int, is_mi_int_status, latch_status);
4457 /* Handle only those with latched-signal=up.*/
4458 if (latch_status & 1) {
4459 /* For all latched-signal=up,Write original_signal to status */
4460 if (is_mi_int)
4461 bnx2x_bits_en(bp,
4462 NIG_REG_STATUS_INTERRUPT_PORT0
4463 + port*4,
4464 NIG_STATUS_EMAC0_MI_INT);
4465 else
4466 bnx2x_bits_dis(bp,
4467 NIG_REG_STATUS_INTERRUPT_PORT0
4468 + port*4,
4469 NIG_STATUS_EMAC0_MI_INT);
4470 /* For all latched-signal=up : Re-Arm Latch signals */
4471 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
4472 (latch_status & 0xfffe) | (latch_status & 1));
4473 }
4474}
e10bc84d 4475
ea4e040a
YR		 4476/*
4477 * link management
4478 */
4479static void bnx2x_link_int_ack(struct link_params *params,
2f904460
EG		 4480 struct link_vars *vars, u8 is_10g,
4481 u8 is_mi_int)
ea4e040a
YR		 4482{
4483 struct bnx2x *bp = params->bp;
4484 u8 port = params->port;
4485
4486 /* first reset all status
4487 * we assume only one line will be change at a time */
4488 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
4489 (NIG_STATUS_XGXS0_LINK10G |
4490 NIG_STATUS_XGXS0_LINK_STATUS |
4491 NIG_STATUS_SERDES0_LINK_STATUS));
e10bc84d 4492 if ((params->phy[EXT_PHY1].type
4f60dab1 4493 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
e10bc84d 4494 (params->phy[EXT_PHY1].type
4f60dab1 4495 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) {
2f904460
EG		 4496 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
4497 }
ea4e040a
YR		 4498 if (vars->phy_link_up) {
4499 if (is_10g) {
4500 /* Disable the 10G link interrupt
4501 * by writing 1 to the status register
4502 */
4503 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
4504 bnx2x_bits_en(bp,
4505 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
4506 NIG_STATUS_XGXS0_LINK10G);
4507
4508 } else if (params->switch_cfg == SWITCH_CFG_10G) {
4509 /* Disable the link interrupt
4510 * by writing 1 to the relevant lane
4511 * in the status register
4512 */
4513 u32 ser_lane = ((params->lane_config &
4514 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4515 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4516
2f904460
EG		 4517 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
4518 vars->line_speed);
ea4e040a
YR		 4519 bnx2x_bits_en(bp,
4520 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
4521 ((1 << ser_lane) <<
4522 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
4523
4524 } else { /* SerDes */
4525 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
4526 /* Disable the link interrupt
4527 * by writing 1 to the status register
4528 */
4529 bnx2x_bits_en(bp,
4530 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
4531 NIG_STATUS_SERDES0_LINK_STATUS);
4532 }
4533
ea4e040a
YR		 4534 }
4535}
4536
b7737c9b
YR		 4537static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
4538{
4539 if (*len < 5)
4540 return -EINVAL;
4541 str[0] = (spirom_ver & 0xFF);
4542 str[1] = (spirom_ver & 0xFF00) >> 8;
4543 str[2] = (spirom_ver & 0xFF0000) >> 16;
4544 str[3] = (spirom_ver & 0xFF000000) >> 24;
4545 str[4] = '\0';
4546 *len -= 5;
4547 return 0;
4548}
4549
4550static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
ea4e040a
YR		 4551{
4552 u8 *str_ptr = str;
4553 u32 mask = 0xf0000000;
4554 u8 shift = 8*4;
4555 u8 digit;
b7737c9b 4556 if (*len < 10) {
025dfdaf 4557 /* Need more than 10chars for this format */
ea4e040a
YR		 4558 *str_ptr = '\0';
4559 return -EINVAL;
4560 }
4561 while (shift > 0) {
4562
4563 shift -= 4;
4564 digit = ((num & mask) >> shift);
4565 if (digit < 0xa)
4566 *str_ptr = digit + '0';
4567 else
4568 *str_ptr = digit - 0xa + 'a';
4569 str_ptr++;
4570 mask = mask >> 4;
4571 if (shift == 4*4) {
4572 *str_ptr = ':';
4573 str_ptr++;
4574 }
4575 }
4576 *str_ptr = '\0';
4577 return 0;
4578}
4579
b7737c9b
YR		 4580static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
4581{
4582 u8 status = 0;
4583 u32 spirom_ver;
4584 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
4585 status = bnx2x_format_ver(spirom_ver, str, len);
4586 return status;
4587}
4588
4589static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
4590{
4591 str[0] = '\0';
4592 (*len)--;
4593 return 0;
4594}
ea4e040a
YR		 4595u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
4596 u8 *version, u16 len)
4597{
0376d5b2 4598 struct bnx2x *bp;
a35da8db 4599 u32 spirom_ver = 0;
b7737c9b
YR		 4600 u8 status = 0;
4601 u8 *ver_p = version;
ea4e040a
YR		 4602 if (version == NULL || params == NULL)
4603 return -EINVAL;
0376d5b2 4604 bp = params->bp;
ea4e040a 4605
b7737c9b
YR		 4606 /* Extract first external phy*/
4607 version[0] = '\0';
4608 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
ea4e040a 4609
b7737c9b
YR		 4610 if (params->phy[EXT_PHY1].format_fw_ver)
4611 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
4612 ver_p,
4613 &len);
ea4e040a
YR		 4614 return status;
4615}
4616
e10bc84d 4617static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
62b29a5d 4618 struct link_params *params)
ea4e040a
YR		 4619{
4620 u8 port = params->port;
4621 struct bnx2x *bp = params->bp;
4622
62b29a5d 4623 if (phy->req_line_speed != SPEED_1000) {
6378c025 4624 u32 md_devad;
ea4e040a
YR		 4625
4626 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
4627
4628 /* change the uni_phy_addr in the nig */
4629 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
4630 port*0x18));
4631
4632 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
4633
e10bc84d 4634 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 4635 5,
4636 (MDIO_REG_BANK_AER_BLOCK +
4637 (MDIO_AER_BLOCK_AER_REG & 0xf)),
4638 0x2800);
4639
e10bc84d 4640 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 4641 5,
4642 (MDIO_REG_BANK_CL73_IEEEB0 +
4643 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
4644 0x6041);
3858276b 4645 msleep(200);
ea4e040a 4646 /* set aer mmd back */
e10bc84d 4647 bnx2x_set_aer_mmd(params, phy);
ea4e040a
YR		 4648
4649 /* and md_devad */
4650 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
4651 md_devad);
4652
4653 } else {
e10bc84d 4654 u16 mii_ctrl;
ea4e040a 4655 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
e10bc84d
YR		 4656 bnx2x_cl45_read(bp, phy, 5,
4657 (MDIO_REG_BANK_COMBO_IEEE0 +
4658 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
4659 &mii_ctrl);
4660 bnx2x_cl45_write(bp, phy, 5,
4661 (MDIO_REG_BANK_COMBO_IEEE0 +
4662 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
4663 mii_ctrl |
4664 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
ea4e040a
YR		 4665 }
4666}
4667
b7737c9b
YR		 4668static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
4669 struct link_params *params)
ea4e040a
YR		 4670{
4671 struct bnx2x *bp = params->bp;
b7737c9b
YR		 4672 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
4673 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
4674}
ea4e040a 4675
b7737c9b
YR		 4676static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
4677 struct link_params *params)
4678{
4679 struct bnx2x *bp = params->bp;
4680 /* SFX7101_XGXS_TEST1 */
4681 bnx2x_cl45_write(bp, phy,
4682 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
ea4e040a 4683}
c18aa15d 4684
ea4e040a
YR		 4685/*
4686 *------------------------------------------------------------------------
4687 * bnx2x_override_led_value -
4688 *
e10bc84d 4689 * Override the led value of the requested led
ea4e040a
YR		 4690 *
4691 *------------------------------------------------------------------------
4692 */
4693u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
4694 u32 led_idx, u32 value)
4695{
4696 u32 reg_val;
4697
4698 /* If port 0 then use EMAC0, else use EMAC1*/
4699 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
4700
4701 DP(NETIF_MSG_LINK,
4702 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
4703 port, led_idx, value);
4704
4705 switch (led_idx) {
4706 case 0: /* 10MB led */
4707 /* Read the current value of the LED register in
4708 the EMAC block */
4709 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
4710 /* Set the OVERRIDE bit to 1 */
4711 reg_val |= EMAC_LED_OVERRIDE;
4712 /* If value is 1, set the 10M_OVERRIDE bit,
4713 otherwise reset it.*/
4714 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
4715 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
4716 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
4717 break;
4718 case 1: /*100MB led */
4719 /*Read the current value of the LED register in
4720 the EMAC block */
4721 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
4722 /* Set the OVERRIDE bit to 1 */
4723 reg_val |= EMAC_LED_OVERRIDE;
4724 /* If value is 1, set the 100M_OVERRIDE bit,
4725 otherwise reset it.*/
4726 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
4727 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
4728 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
4729 break;
4730 case 2: /* 1000MB led */
4731 /* Read the current value of the LED register in the
4732 EMAC block */
4733 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
4734 /* Set the OVERRIDE bit to 1 */
4735 reg_val |= EMAC_LED_OVERRIDE;
4736 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
4737 reset it. */
4738 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
4739 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
4740 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
4741 break;
4742 case 3: /* 2500MB led */
4743 /* Read the current value of the LED register in the
4744 EMAC block*/
4745 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
4746 /* Set the OVERRIDE bit to 1 */
4747 reg_val |= EMAC_LED_OVERRIDE;
4748 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
4749 reset it.*/
4750 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
4751 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
4752 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
4753 break;
4754 case 4: /*10G led */
4755 if (port == 0) {
4756 REG_WR(bp, NIG_REG_LED_10G_P0,
4757 value);
4758 } else {
4759 REG_WR(bp, NIG_REG_LED_10G_P1,
4760 value);
4761 }
4762 break;
4763 case 5: /* TRAFFIC led */
4764 /* Find if the traffic control is via BMAC or EMAC */
4765 if (port == 0)
4766 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
4767 else
4768 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
4769
4770 /* Override the traffic led in the EMAC:*/
4771 if (reg_val == 1) {
4772 /* Read the current value of the LED register in
4773 the EMAC block */
4774 reg_val = REG_RD(bp, emac_base +
4775 EMAC_REG_EMAC_LED);
4776 /* Set the TRAFFIC_OVERRIDE bit to 1 */
4777 reg_val |= EMAC_LED_OVERRIDE;
4778 /* If value is 1, set the TRAFFIC bit, otherwise
4779 reset it.*/
4780 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
4781 (reg_val & ~EMAC_LED_TRAFFIC);
4782 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
4783 } else { /* Override the traffic led in the BMAC: */
4784 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
4785 + port*4, 1);
4786 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
4787 value);
4788 }
4789 break;
4790 default:
4791 DP(NETIF_MSG_LINK,
4792 "bnx2x_override_led_value() unknown led index %d "
4793 "(should be 0-5)\n", led_idx);
4794 return -EINVAL;
4795 }
4796
4797 return 0;
4798}
4799
4800
7846e471 4801u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
ea4e040a 4802{
7846e471
YR		 4803 u8 port = params->port;
4804 u16 hw_led_mode = params->hw_led_mode;
ea4e040a 4805 u8 rc = 0;
345b5d52
EG		 4806 u32 tmp;
4807 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7846e471 4808 struct bnx2x *bp = params->bp;
ea4e040a
YR		 4809 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
4810 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
4811 speed, hw_led_mode);
4812 switch (mode) {
4813 case LED_MODE_OFF:
4814 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
4815 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
4816 SHARED_HW_CFG_LED_MAC1);
345b5d52
EG		 4817
4818 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 4819 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
ea4e040a
YR		 4820 break;
4821
4822 case LED_MODE_OPER:
e10bc84d 4823 if (SINGLE_MEDIA_DIRECT(params)) {
7846e471
YR		 4824 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
4825 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
4826 } else {
4827 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
4828 hw_led_mode);
4829 }
4830
ea4e040a
YR		 4831 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
4832 port*4, 0);
4833 /* Set blinking rate to ~15.9Hz */
4834 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
4835 LED_BLINK_RATE_VAL);
4836 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
4837 port*4, 1);
345b5d52 4838 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 4839 EMAC_WR(bp, EMAC_REG_EMAC_LED,
345b5d52
EG		 4840 (tmp & (~EMAC_LED_OVERRIDE)));
4841
7846e471 4842 if (CHIP_IS_E1(bp) &&
34f80b04 4843 ((speed == SPEED_2500) ||
ea4e040a
YR		 4844 (speed == SPEED_1000) ||
4845 (speed == SPEED_100) ||
4846 (speed == SPEED_10))) {
4847 /* On Everest 1 Ax chip versions for speeds less than
4848 10G LED scheme is different */
4849 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
4850 + port*4, 1);
4851 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
4852 port*4, 0);
4853 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
4854 port*4, 1);
4855 }
4856 break;
4857
4858 default:
4859 rc = -EINVAL;
4860 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
4861 mode);
4862 break;
4863 }
4864 return rc;
4865
4866}
4867
4868u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
4869{
4870 struct bnx2x *bp = params->bp;
c18aa15d 4871 u16 gp_status = 0, phy_index = 0;
ea4e040a 4872
e10bc84d 4873 CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
ea4e040a
YR		 4874 MDIO_REG_BANK_GP_STATUS,
4875 MDIO_GP_STATUS_TOP_AN_STATUS1,
4876 &gp_status);
4877 /* link is up only if both local phy and external phy are up */
b7737c9b
YR		 4878 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
4879 u8 ext_phy_link_up = 1;
4880 struct link_vars temp_vars;
c18aa15d
YR		 4881 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
4882 phy_index++) {
4883 if (params->phy[phy_index].read_status)
4884 ext_phy_link_up &=
4885 params->phy[phy_index].read_status(
4886 &params->phy[phy_index],
b7737c9b 4887 params, &temp_vars);
c18aa15d 4888 }
b7737c9b
YR		 4889 if (ext_phy_link_up)
4890 return 0;
4891 }
ea4e040a
YR		 4892 return -ESRCH;
4893}
4894
4895static u8 bnx2x_link_initialize(struct link_params *params,
d90d96ba 4896 struct link_vars *vars)
ea4e040a 4897{
ea4e040a 4898 u8 rc = 0;
b7737c9b 4899 u8 phy_index, non_ext_phy;
c18aa15d
YR		 4900 struct bnx2x *bp = params->bp;
4901 /**
4902 * In case of external phy existence, the line speed would be the
4903 * line speed linked up by the external phy. In case it is direct
4904 * only, then the line_speed during initialization will be
4905 * equal to the req_line_speed
4906 */
4907 vars->line_speed = params->phy[INT_PHY].req_line_speed;
ea4e040a 4908
c18aa15d
YR		 4909 /**
4910 * Initialize the internal phy in case this is a direct board
4911 * (no external phys), or this board has external phy which requires
4912 * to first.
4913 */
ea4e040a 4914
c18aa15d
YR		 4915 if (params->phy[INT_PHY].config_init)
4916 params->phy[INT_PHY].config_init(
4917 &params->phy[INT_PHY],
4918 params, vars);
ea4e040a 4919
57963ed9 4920 /* init ext phy and enable link state int */
c18aa15d 4921 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
8660d8c3 4922 (params->loopback_mode == LOOPBACK_XGXS_10));
57963ed9
YR		 4923
4924 if (non_ext_phy ||
c18aa15d 4925 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
8660d8c3 4926 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
c18aa15d 4927 struct bnx2x_phy *phy = &params->phy[INT_PHY];
e10bc84d 4928 if (vars->line_speed == SPEED_AUTO_NEG)
c18aa15d
YR		 4929 bnx2x_set_parallel_detection(phy, params);
4930 bnx2x_init_internal_phy(phy, params, vars);
ea4e040a
YR		 4931 }
4932
c18aa15d 4933 /* Init external phy*/
57963ed9 4934 if (!non_ext_phy)
b7737c9b
YR		 4935 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
4936 phy_index++) {
4937 params->phy[phy_index].config_init(
4938 &params->phy[phy_index],
4939 params, vars);
4940 }
ea4e040a 4941
d90d96ba
YR		 4942 /* Reset the interrupt indication after phy was initialized */
4943 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
4944 params->port*4,
4945 (NIG_STATUS_XGXS0_LINK10G |
4946 NIG_STATUS_XGXS0_LINK_STATUS |
4947 NIG_STATUS_SERDES0_LINK_STATUS |
4948 NIG_MASK_MI_INT));
ea4e040a 4949 return rc;
ea4e040a
YR		 4950}
4951
b7737c9b
YR		 4952static void set_phy_vars(struct link_params *params)
4953{
4954 struct bnx2x *bp = params->bp;
4955 u8 actual_phy_idx, phy_index;
4956
4957 for (phy_index = INT_PHY; phy_index < params->num_phys;
4958 phy_index++) {
4959
4960 actual_phy_idx = phy_index;
4961 params->phy[actual_phy_idx].req_flow_ctrl =
4962 params->req_flow_ctrl;
4963
4964 params->phy[actual_phy_idx].req_line_speed =
4965 params->req_line_speed;
4966
4967 params->phy[actual_phy_idx].speed_cap_mask =
4968 params->speed_cap_mask;
4969
4970 params->phy[actual_phy_idx].req_duplex =
4971 params->req_duplex;
4972
4973 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
4974 " speed_cap_mask %x\n",
4975 params->phy[actual_phy_idx].req_flow_ctrl,
4976 params->phy[actual_phy_idx].req_line_speed,
4977 params->phy[actual_phy_idx].speed_cap_mask);
4978 }
4979}
4980
ea4e040a
YR		 4981u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
4982{
4983 struct bnx2x *bp = params->bp;
ea4e040a 4984 u32 val;
ab6ad5a4
EG		 4985
4986 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
4987 DP(NETIF_MSG_LINK, "req_speed %d, req_flowctrl %d\n",
4988 params->req_line_speed, params->req_flow_ctrl);
ea4e040a 4989 vars->link_status = 0;
57963ed9
YR		 4990 vars->phy_link_up = 0;
4991 vars->link_up = 0;
4992 vars->line_speed = 0;
4993 vars->duplex = DUPLEX_FULL;
c0700f90 4994 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
57963ed9 4995 vars->mac_type = MAC_TYPE_NONE;
b7737c9b 4996 vars->phy_flags = 0;
ea4e040a
YR		 4997
4998 /* disable attentions */
4999 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
5000 (NIG_MASK_XGXS0_LINK_STATUS |
5001 NIG_MASK_XGXS0_LINK10G |
5002 NIG_MASK_SERDES0_LINK_STATUS |
5003 NIG_MASK_MI_INT));
5004
5005 bnx2x_emac_init(params, vars);
5006
b7737c9b
YR		 5007 if (params->num_phys == 0) {
5008 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
5009 return -EINVAL;
5010 }
5011 set_phy_vars(params);
5012
5013 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
ea4e040a 5014 if (CHIP_REV_IS_FPGA(bp)) {
ab6ad5a4 5015
ea4e040a
YR		 5016 vars->link_up = 1;
5017 vars->line_speed = SPEED_10000;
5018 vars->duplex = DUPLEX_FULL;
c0700f90 5019 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 5020 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
34f80b04
EG		 5021 /* enable on E1.5 FPGA */
5022 if (CHIP_IS_E1H(bp)) {
5023 vars->flow_ctrl |=
ab6ad5a4
EG		 5024 (BNX2X_FLOW_CTRL_TX |
5025 BNX2X_FLOW_CTRL_RX);
34f80b04
EG		 5026 vars->link_status |=
5027 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
5028 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
5029 }
ea4e040a
YR		 5030
5031 bnx2x_emac_enable(params, vars, 0);
5032 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5033 /* disable drain */
ab6ad5a4 5034 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
ea4e040a
YR		 5035
5036 /* update shared memory */
5037 bnx2x_update_mng(params, vars->link_status);
5038
5039 return 0;
5040
5041 } else
5042 if (CHIP_REV_IS_EMUL(bp)) {
5043
5044 vars->link_up = 1;
5045 vars->line_speed = SPEED_10000;
5046 vars->duplex = DUPLEX_FULL;
c0700f90 5047 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5048 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5049
5050 bnx2x_bmac_enable(params, vars, 0);
5051
5052 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5053 /* Disable drain */
5054 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5055 + params->port*4, 0);
5056
5057 /* update shared memory */
5058 bnx2x_update_mng(params, vars->link_status);
5059
5060 return 0;
5061
5062 } else
5063 if (params->loopback_mode == LOOPBACK_BMAC) {
ab6ad5a4 5064
ea4e040a
YR		 5065 vars->link_up = 1;
5066 vars->line_speed = SPEED_10000;
5067 vars->duplex = DUPLEX_FULL;
c0700f90 5068 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5069 vars->mac_type = MAC_TYPE_BMAC;
5070
5071 vars->phy_flags = PHY_XGXS_FLAG;
5072
c18aa15d 5073 bnx2x_xgxs_deassert(params);
e10bc84d 5074
ea4e040a
YR		 5075 /* set bmac loopback */
5076 bnx2x_bmac_enable(params, vars, 1);
5077
5078 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5079 params->port*4, 0);
ab6ad5a4 5080
ea4e040a 5081 } else if (params->loopback_mode == LOOPBACK_EMAC) {
ab6ad5a4 5082
ea4e040a
YR		 5083 vars->link_up = 1;
5084 vars->line_speed = SPEED_1000;
5085 vars->duplex = DUPLEX_FULL;
c0700f90 5086 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5087 vars->mac_type = MAC_TYPE_EMAC;
5088
5089 vars->phy_flags = PHY_XGXS_FLAG;
5090
c18aa15d 5091 bnx2x_xgxs_deassert(params);
ea4e040a
YR		 5092 /* set bmac loopback */
5093 bnx2x_emac_enable(params, vars, 1);
b7737c9b 5094 bnx2x_emac_program(params, vars);
ea4e040a
YR		 5095 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5096 params->port*4, 0);
ab6ad5a4 5097
ea4e040a 5098 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
ab6ad5a4
EG		 5099 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5100
ea4e040a
YR		 5101 vars->link_up = 1;
5102 vars->line_speed = SPEED_10000;
5103 vars->duplex = DUPLEX_FULL;
c0700f90 5104 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5105
5106 vars->phy_flags = PHY_XGXS_FLAG;
5107
5108 val = REG_RD(bp,
5109 NIG_REG_XGXS0_CTRL_PHY_ADDR+
5110 params->port*0x18);
b7737c9b 5111
c18aa15d 5112 bnx2x_xgxs_deassert(params);
ea4e040a
YR		 5113 bnx2x_link_initialize(params, vars);
5114
5115 vars->mac_type = MAC_TYPE_BMAC;
5116
5117 bnx2x_bmac_enable(params, vars, 0);
5118
5119 if (params->loopback_mode == LOOPBACK_XGXS_10) {
5120 /* set 10G XGXS loopback */
b7737c9b
YR		 5121 params->phy[INT_PHY].config_loopback(
5122 &params->phy[INT_PHY],
5123 params);
5124
ea4e040a
YR		 5125 } else {
5126 /* set external phy loopback */
b7737c9b
YR		 5127 u8 phy_index;
5128 for (phy_index = EXT_PHY1;
5129 phy_index < params->num_phys; phy_index++) {
5130 if (params->phy[phy_index].config_loopback)
5131 params->phy[phy_index].config_loopback(
5132 &params->phy[phy_index],
62b29a5d 5133 params);
b7737c9b 5134 }
ea4e040a 5135 }
e10bc84d 5136
ea4e040a
YR		 5137 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5138 params->port*4, 0);
ba71d313 5139
7846e471 5140 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 5141 } else
5142 /* No loopback */
5143 {
b7737c9b 5144 if (params->switch_cfg == SWITCH_CFG_10G)
c18aa15d
YR		 5145 bnx2x_xgxs_deassert(params);
5146 else
5147 bnx2x_serdes_deassert(bp, params->port);
ea4e040a 5148 bnx2x_link_initialize(params, vars);
57963ed9 5149 msleep(30);
ea4e040a
YR		 5150 bnx2x_link_int_enable(params);
5151 }
5152 return 0;
5153}
5154
589abe3a 5155
b7737c9b
YR		 5156static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5157 struct link_params *params)
e10bc84d 5158{
b7737c9b
YR		 5159 struct bnx2x *bp = params->bp;
5160 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
589abe3a 5161 /* Set serial boot control for external load */
e10bc84d 5162 bnx2x_cl45_write(bp, phy,
b7737c9b
YR		 5163 MDIO_PMA_DEVAD,
5164 MDIO_PMA_REG_GEN_CTRL, 0x0001);
5165}
5166
5167static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5168 struct link_params *params)
5169{
5170 struct bnx2x *bp = params->bp;
5171 /* Disable Transmitter */
5172 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5173}
5174static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
5175 struct link_params *params)
5176{
5177 struct bnx2x *bp = params->bp;
5178 u8 gpio_port;
5179 gpio_port = params->port;
5180 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
5181 gpio_port);
5182 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5183 MISC_REGISTERS_GPIO_OUTPUT_LOW,
5184 gpio_port);
5185}
5186static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
5187 struct link_params *params)
5188{
5189 bnx2x_cl45_write(params->bp, phy,
5190 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
5191 bnx2x_cl45_write(params->bp, phy,
5192 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
5193}
5194
5195static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
5196 struct link_params *params)
5197{
5198 struct bnx2x *bp = params->bp;
5199 u8 port = params->port;
5200 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5201 MISC_REGISTERS_GPIO_OUTPUT_LOW,
5202 port);
5203}
5204
5205static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
5206 struct link_params *params)
5207{
5208 struct bnx2x *bp = params->bp;
5209 u8 gpio_port;
5210 /* HW reset */
5211 gpio_port = params->port;
5212 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5213 MISC_REGISTERS_GPIO_OUTPUT_LOW,
5214 gpio_port);
5215 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5216 MISC_REGISTERS_GPIO_OUTPUT_LOW,
5217 gpio_port);
5218 DP(NETIF_MSG_LINK, "reset external PHY\n");
5219}
5220
5221static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
5222 struct link_params *params)
5223{
5224 /* reset the SerDes/XGXS */
5225 REG_WR(params->bp, GRCBASE_MISC +
5226 MISC_REGISTERS_RESET_REG_3_CLEAR,
5227 (0x1ff << (params->port*16)));
589abe3a
EG		 5228}
5229
5230u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
5231 u8 reset_ext_phy)
ea4e040a 5232{
ea4e040a 5233 struct bnx2x *bp = params->bp;
b7737c9b 5234 u8 phy_index, port = params->port;
d5cb9e99 5235 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
ea4e040a 5236 /* disable attentions */
ea4e040a
YR		 5237 vars->link_status = 0;
5238 bnx2x_update_mng(params, vars->link_status);
5239 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5240 (NIG_MASK_XGXS0_LINK_STATUS |
5241 NIG_MASK_XGXS0_LINK10G |
5242 NIG_MASK_SERDES0_LINK_STATUS |
5243 NIG_MASK_MI_INT));
5244
5245 /* activate nig drain */
5246 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
5247
5248 /* disable nig egress interface */
5249 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
5250 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
5251
5252 /* Stop BigMac rx */
5253 bnx2x_bmac_rx_disable(bp, port);
5254
5255 /* disable emac */
5256 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
5257
5258 msleep(10);
5259 /* The PHY reset is controled by GPIO 1
5260 * Hold it as vars low
5261 */
5262 /* clear link led */
7846e471 5263 bnx2x_set_led(params, LED_MODE_OFF, 0);
589abe3a 5264 if (reset_ext_phy) {
b7737c9b
YR		 5265 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
5266 phy_index++) {
5267 if (params->phy[phy_index].link_reset)
5268 params->phy[phy_index].link_reset(
5269 &params->phy[phy_index],
5270 params);
ea4e040a
YR		 5271 }
5272 }
ea4e040a 5273
b7737c9b
YR		 5274 if (params->phy[INT_PHY].link_reset)
5275 params->phy[INT_PHY].link_reset(
5276 &params->phy[INT_PHY], params);
ea4e040a
YR		 5277 /* reset BigMac */
5278 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
5279 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
5280
5281 /* disable nig ingress interface */
5282 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
5283 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
5284 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
5285 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
5286 vars->link_up = 0;
5287 return 0;
5288}
5289
57963ed9
YR		 5290static u8 bnx2x_update_link_down(struct link_params *params,
5291 struct link_vars *vars)
5292{
5293 struct bnx2x *bp = params->bp;
5294 u8 port = params->port;
ab6ad5a4 5295
57963ed9 5296 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
7846e471 5297 bnx2x_set_led(params, LED_MODE_OFF, 0);
57963ed9
YR		 5298
5299 /* indicate no mac active */
5300 vars->mac_type = MAC_TYPE_NONE;
5301
5302 /* update shared memory */
5303 vars->link_status = 0;
5304 vars->line_speed = 0;
5305 bnx2x_update_mng(params, vars->link_status);
5306
5307 /* activate nig drain */
5308 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
5309
6c55c3cd
EG		 5310 /* disable emac */
5311 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
5312
5313 msleep(10);
5314
57963ed9
YR		 5315 /* reset BigMac */
5316 bnx2x_bmac_rx_disable(bp, params->port);
5317 REG_WR(bp, GRCBASE_MISC +
5318 MISC_REGISTERS_RESET_REG_2_CLEAR,
5319 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
5320 return 0;
5321}
5322
5323static u8 bnx2x_update_link_up(struct link_params *params,
5324 struct link_vars *vars,
b7737c9b 5325 u8 link_10g)
57963ed9
YR		 5326{
5327 struct bnx2x *bp = params->bp;
5328 u8 port = params->port;
5329 u8 rc = 0;
ab6ad5a4 5330
57963ed9 5331 vars->link_status |= LINK_STATUS_LINK_UP;
7aa0711f
YR		 5332 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
5333 vars->link_status |=
5334 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
5335
5336 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
5337 vars->link_status |=
5338 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
57963ed9
YR		 5339 if (link_10g) {
5340 bnx2x_bmac_enable(params, vars, 0);
7846e471 5341 bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000);
57963ed9 5342 } else {
b7737c9b 5343 rc = bnx2x_emac_program(params, vars);
57963ed9 5344
0c786f02
YR		 5345 bnx2x_emac_enable(params, vars, 0);
5346
57963ed9 5347 /* AN complete? */
e10bc84d
YR		 5348 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
5349 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
5350 SINGLE_MEDIA_DIRECT(params))
5351 bnx2x_set_gmii_tx_driver(params);
57963ed9
YR		 5352 }
5353
5354 /* PBF - link up */
5355 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
5356 vars->line_speed);
5357
5358 /* disable drain */
5359 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
5360
5361 /* update shared memory */
5362 bnx2x_update_mng(params, vars->link_status);
6c55c3cd 5363 msleep(20);
57963ed9
YR		 5364 return rc;
5365}
b7737c9b
YR		 5366/**
5367 * The bnx2x_link_update function should be called upon link
5368 * interrupt.
5369 * Link is considered up as follows:
5370 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
5371 * to be up
5372 * - SINGLE_MEDIA - The link between the 577xx and the external
5373 * phy (XGXS) need to up as well as the external link of the
5374 * phy (PHY_EXT1)
5375 * - DUAL_MEDIA - The link between the 577xx and the first
5376 * external phy needs to be up, and at least one of the 2
5377 * external phy link must be up.
62b29a5d 5378 */
ea4e040a
YR		 5379u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
5380{
5381 struct bnx2x *bp = params->bp;
b7737c9b 5382 struct link_vars phy_vars[MAX_PHYS];
ea4e040a 5383 u8 port = params->port;
b7737c9b
YR		 5384 u8 link_10g, phy_index;
5385 u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
2f904460 5386 u8 is_mi_int = 0;
b7737c9b
YR		 5387 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
5388 u8 active_external_phy = INT_PHY;
5389 vars->link_status = 0;
5390 for (phy_index = INT_PHY; phy_index < params->num_phys;
5391 phy_index++) {
5392 phy_vars[phy_index].flow_ctrl = 0;
5393 phy_vars[phy_index].link_status = 0;
5394 phy_vars[phy_index].line_speed = 0;
5395 phy_vars[phy_index].duplex = DUPLEX_FULL;
5396 phy_vars[phy_index].phy_link_up = 0;
5397 phy_vars[phy_index].link_up = 0;
5398 }
ea4e040a
YR		 5399
5400 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
2f904460
EG		 5401 port, (vars->phy_flags & PHY_XGXS_FLAG),
5402 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
ea4e040a 5403
2f904460
EG		 5404 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
5405 port*0x18) > 0);
ea4e040a 5406 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
2f904460
EG		 5407 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5408 is_mi_int,
5409 REG_RD(bp,
5410 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
ea4e040a
YR		 5411
5412 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5413 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5414 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5415
6c55c3cd
EG		 5416 /* disable emac */
5417 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
5418
b7737c9b
YR		 5419 /**
5420 * Step 1:
5421 * Check external link change only for external phys, and apply
5422 * priority selection between them in case the link on both phys
5423 * is up. Note that the instead of the common vars, a temporary
5424 * vars argument is used since each phy may have different link/
5425 * speed/duplex result
5426 */
5427 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
5428 phy_index++) {
5429 struct bnx2x_phy *phy = &params->phy[phy_index];
5430 if (!phy->read_status)
5431 continue;
5432 /* Read link status and params of this ext phy */
5433 cur_link_up = phy->read_status(phy, params,
5434 &phy_vars[phy_index]);
5435 if (cur_link_up) {
5436 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
5437 phy_index);
5438 } else {
5439 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
5440 phy_index);
5441 continue;
5442 }
57963ed9 5443
b7737c9b
YR		 5444 if (!ext_phy_link_up) {
5445 ext_phy_link_up = 1;
5446 active_external_phy = phy_index;
5447 }
5448 }
5449 prev_line_speed = vars->line_speed;
5450 /**
5451 * Step 2:
5452 * Read the status of the internal phy. In case of
5453 * DIRECT_SINGLE_MEDIA board, this link is the external link,
5454 * otherwise this is the link between the 577xx and the first
5455 * external phy
5456 */
5457 if (params->phy[INT_PHY].read_status)
5458 params->phy[INT_PHY].read_status(
5459 &params->phy[INT_PHY],
5460 params, vars);
5461 /**
5462 * The INT_PHY flow control reside in the vars. This include the
5463 * case where the speed or flow control are not set to AUTO.
5464 * Otherwise, the active external phy flow control result is set
5465 * to the vars. The ext_phy_line_speed is needed to check if the
5466 * speed is different between the internal phy and external phy.
5467 * This case may be result of intermediate link speed change.
5468 */
5469 if (active_external_phy > INT_PHY) {
5470 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
5471 /**
5472 * Link speed is taken from the XGXS. AN and FC result from
5473 * the external phy.
5474 */
5475 vars->link_status |= phy_vars[active_external_phy].link_status;
5476 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
5477 vars->duplex = phy_vars[active_external_phy].duplex;
5478 if (params->phy[active_external_phy].supported &
5479 SUPPORTED_FIBRE)
5480 vars->link_status |= LINK_STATUS_SERDES_LINK;
5481 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
5482 active_external_phy);
5483 }
5484 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
5485 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
5486 vars->link_status, ext_phy_line_speed);
5487 /**
5488 * Upon link speed change set the NIG into drain mode. Comes to
5489 * deals with possible FIFO glitch due to clk change when speed
5490 * is decreased without link down indicator
5491 */
ea4e040a 5492
b7737c9b
YR		 5493 if (vars->phy_link_up) {
5494 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
5495 (ext_phy_line_speed != vars->line_speed)) {
5496 DP(NETIF_MSG_LINK, "Internal link speed %d is"
5497 " different than the external"
5498 " link speed %d\n", vars->line_speed,
5499 ext_phy_line_speed);
5500 vars->phy_link_up = 0;
5501 } else if (prev_line_speed != vars->line_speed) {
5502 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5503 + params->port*4, 0);
5504 msleep(1);
5505 }
5506 }
ea4e040a
YR		 5507
5508 /* anything 10 and over uses the bmac */
5509 link_10g = ((vars->line_speed == SPEED_10000) ||
5510 (vars->line_speed == SPEED_12000) ||
5511 (vars->line_speed == SPEED_12500) ||
5512 (vars->line_speed == SPEED_13000) ||
5513 (vars->line_speed == SPEED_15000) ||
5514 (vars->line_speed == SPEED_16000));
5515
2f904460 5516 bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
ea4e040a 5517
b7737c9b
YR		 5518 /**
5519 * In case external phy link is up, and internal link is down
5520 * (not initialized yet probably after link initialization, it
5521 * needs to be initialized.
5522 * Note that after link down-up as result of cable plug, the xgxs
5523 * link would probably become up again without the need
5524 * initialize it
5525 */
5526 if (!(SINGLE_MEDIA_DIRECT(params))) {
5527 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
5528 " init_preceding = %d\n", ext_phy_link_up,
5529 vars->phy_link_up,
5530 params->phy[EXT_PHY1].flags &
5531 FLAGS_INIT_XGXS_FIRST);
5532 if (!(params->phy[EXT_PHY1].flags &
5533 FLAGS_INIT_XGXS_FIRST)
5534 && ext_phy_link_up && !vars->phy_link_up) {
5535 vars->line_speed = ext_phy_line_speed;
5536 if (vars->line_speed < SPEED_1000)
5537 vars->phy_flags |= PHY_SGMII_FLAG;
5538 else
5539 vars->phy_flags &= ~PHY_SGMII_FLAG;
5540 bnx2x_init_internal_phy(&params->phy[INT_PHY],
5541 params,
5542 vars);
5543 }
5544 }
5545 /**
5546 * Link is up only if both local phy and external phy (in case of
5547 * non-direct board) are up
5548 */
5549 vars->link_up = (vars->phy_link_up &&
5550 (ext_phy_link_up ||
5551 SINGLE_MEDIA_DIRECT(params)));
ea4e040a 5552
57963ed9 5553 if (vars->link_up)
b7737c9b 5554 rc = bnx2x_update_link_up(params, vars, link_10g);
57963ed9
YR		 5555 else
5556 rc = bnx2x_update_link_down(params, vars);
ea4e040a
YR		 5557
5558 return rc;
5559}
5560
b7737c9b
YR		 5561static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
5562 struct link_params *params)
5563{
5564 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5565 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
5566 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5567 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
5568}
5569
5570static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5571 struct link_params *params) {
5572 u32 swap_val, swap_override;
5573 u8 port;
5574 /**
5575 * The PHY reset is controlled by GPIO 1. Fake the port number
5576 * to cancel the swap done in set_gpio()
5577 */
5578 struct bnx2x *bp = params->bp;
5579 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5580 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5581 port = (swap_val && swap_override) ^ 1;
5582 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5583 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5584}
5585
5586static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
5587 struct link_params *params) {
5588 /* Low power mode is controlled by GPIO 2 */
5589 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
5590 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
5591 /* The PHY reset is controlled by GPIO 1 */
5592 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5593 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
5594}
5595/******************************************************************/
5596/* STATIC PHY DECLARATION */
5597/******************************************************************/
5598
5599static struct bnx2x_phy phy_null = {
5600 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
5601 .addr = 0,
5602 .flags = FLAGS_INIT_XGXS_FIRST,
5603 .def_md_devad = 0,
5604 .reserved = 0,
5605 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5606 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5607 .mdio_ctrl = 0,
5608 .supported = 0,
5609 .media_type = ETH_PHY_NOT_PRESENT,
5610 .ver_addr = 0,
5611 .req_flow_ctrl = 0,
5612 .req_line_speed = 0,
5613 .speed_cap_mask = 0,
5614 .req_duplex = 0,
5615 .rsrv = 0,
5616 .config_init = (config_init_t)NULL,
5617 .read_status = (read_status_t)NULL,
5618 .link_reset = (link_reset_t)NULL,
5619 .config_loopback = (config_loopback_t)NULL,
5620 .format_fw_ver = (format_fw_ver_t)NULL,
5621 .hw_reset = (hw_reset_t)NULL,
5622 .set_link_led = (set_link_led_t)NULL
5623};
5624
5625static struct bnx2x_phy phy_serdes = {
5626 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
5627 .addr = 0xff,
5628 .flags = 0,
5629 .def_md_devad = 0,
5630 .reserved = 0,
5631 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5632 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5633 .mdio_ctrl = 0,
5634 .supported = (SUPPORTED_10baseT_Half |
5635 SUPPORTED_10baseT_Full |
5636 SUPPORTED_100baseT_Half |
5637 SUPPORTED_100baseT_Full |
5638 SUPPORTED_1000baseT_Full |
5639 SUPPORTED_2500baseX_Full |
5640 SUPPORTED_TP |
5641 SUPPORTED_Autoneg |
5642 SUPPORTED_Pause |
5643 SUPPORTED_Asym_Pause),
5644 .media_type = ETH_PHY_UNSPECIFIED,
5645 .ver_addr = 0,
5646 .req_flow_ctrl = 0,
5647 .req_line_speed = 0,
5648 .speed_cap_mask = 0,
5649 .req_duplex = 0,
5650 .rsrv = 0,
5651 .config_init = (config_init_t)bnx2x_init_serdes,
5652 .read_status = (read_status_t)bnx2x_link_settings_status,
5653 .link_reset = (link_reset_t)bnx2x_int_link_reset,
5654 .config_loopback = (config_loopback_t)NULL,
5655 .format_fw_ver = (format_fw_ver_t)NULL,
5656 .hw_reset = (hw_reset_t)NULL,
5657 .set_link_led = (set_link_led_t)NULL
5658};
5659
5660static struct bnx2x_phy phy_xgxs = {
5661 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
5662 .addr = 0xff,
5663 .flags = 0,
5664 .def_md_devad = 0,
5665 .reserved = 0,
5666 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5667 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5668 .mdio_ctrl = 0,
5669 .supported = (SUPPORTED_10baseT_Half |
5670 SUPPORTED_10baseT_Full |
5671 SUPPORTED_100baseT_Half |
5672 SUPPORTED_100baseT_Full |
5673 SUPPORTED_1000baseT_Full |
5674 SUPPORTED_2500baseX_Full |
5675 SUPPORTED_10000baseT_Full |
5676 SUPPORTED_FIBRE |
5677 SUPPORTED_Autoneg |
5678 SUPPORTED_Pause |
5679 SUPPORTED_Asym_Pause),
5680 .media_type = ETH_PHY_UNSPECIFIED,
5681 .ver_addr = 0,
5682 .req_flow_ctrl = 0,
5683 .req_line_speed = 0,
5684 .speed_cap_mask = 0,
5685 .req_duplex = 0,
5686 .rsrv = 0,
5687 .config_init = (config_init_t)bnx2x_init_xgxs,
5688 .read_status = (read_status_t)bnx2x_link_settings_status,
5689 .link_reset = (link_reset_t)bnx2x_int_link_reset,
5690 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
5691 .format_fw_ver = (format_fw_ver_t)NULL,
5692 .hw_reset = (hw_reset_t)NULL,
5693 .set_link_led = (set_link_led_t)NULL
5694};
5695
5696static struct bnx2x_phy phy_7101 = {
5697 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
5698 .addr = 0xff,
5699 .flags = FLAGS_FAN_FAILURE_DET_REQ,
5700 .def_md_devad = 0,
5701 .reserved = 0,
5702 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5703 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5704 .mdio_ctrl = 0,
5705 .supported = (SUPPORTED_10000baseT_Full |
5706 SUPPORTED_TP |
5707 SUPPORTED_Autoneg |
5708 SUPPORTED_Pause |
5709 SUPPORTED_Asym_Pause),
5710 .media_type = ETH_PHY_BASE_T,
5711 .ver_addr = 0,
5712 .req_flow_ctrl = 0,
5713 .req_line_speed = 0,
5714 .speed_cap_mask = 0,
5715 .req_duplex = 0,
5716 .rsrv = 0,
5717 .config_init = (config_init_t)bnx2x_7101_config_init,
5718 .read_status = (read_status_t)bnx2x_7101_read_status,
5719 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
5720 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
5721 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
5722 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
5723 .set_link_led = (set_link_led_t)NULL
5724};
5725static struct bnx2x_phy phy_8073 = {
5726 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
5727 .addr = 0xff,
5728 .flags = FLAGS_HW_LOCK_REQUIRED,
5729 .def_md_devad = 0,
5730 .reserved = 0,
5731 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5732 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5733 .mdio_ctrl = 0,
5734 .supported = (SUPPORTED_10000baseT_Full |
5735 SUPPORTED_2500baseX_Full |
5736 SUPPORTED_1000baseT_Full |
5737 SUPPORTED_FIBRE |
5738 SUPPORTED_Autoneg |
5739 SUPPORTED_Pause |
5740 SUPPORTED_Asym_Pause),
5741 .media_type = ETH_PHY_UNSPECIFIED,
5742 .ver_addr = 0,
5743 .req_flow_ctrl = 0,
5744 .req_line_speed = 0,
5745 .speed_cap_mask = 0,
5746 .req_duplex = 0,
5747 .rsrv = 0,
62b29a5d 5748 .config_init = (config_init_t)bnx2x_8073_config_init,
b7737c9b
YR		 5749 .read_status = (read_status_t)bnx2x_8073_read_status,
5750 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
5751 .config_loopback = (config_loopback_t)NULL,
5752 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5753 .hw_reset = (hw_reset_t)NULL,
5754 .set_link_led = (set_link_led_t)NULL
5755};
5756static struct bnx2x_phy phy_8705 = {
5757 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
5758 .addr = 0xff,
5759 .flags = FLAGS_INIT_XGXS_FIRST,
5760 .def_md_devad = 0,
5761 .reserved = 0,
5762 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5763 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5764 .mdio_ctrl = 0,
5765 .supported = (SUPPORTED_10000baseT_Full |
5766 SUPPORTED_FIBRE |
5767 SUPPORTED_Pause |
5768 SUPPORTED_Asym_Pause),
5769 .media_type = ETH_PHY_XFP_FIBER,
5770 .ver_addr = 0,
5771 .req_flow_ctrl = 0,
5772 .req_line_speed = 0,
5773 .speed_cap_mask = 0,
5774 .req_duplex = 0,
5775 .rsrv = 0,
5776 .config_init = (config_init_t)bnx2x_8705_config_init,
5777 .read_status = (read_status_t)bnx2x_8705_read_status,
5778 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
5779 .config_loopback = (config_loopback_t)NULL,
5780 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
5781 .hw_reset = (hw_reset_t)NULL,
5782 .set_link_led = (set_link_led_t)NULL
5783};
5784static struct bnx2x_phy phy_8706 = {
5785 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
5786 .addr = 0xff,
5787 .flags = FLAGS_INIT_XGXS_FIRST,
5788 .def_md_devad = 0,
5789 .reserved = 0,
5790 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5791 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5792 .mdio_ctrl = 0,
5793 .supported = (SUPPORTED_10000baseT_Full |
5794 SUPPORTED_1000baseT_Full |
5795 SUPPORTED_FIBRE |
5796 SUPPORTED_Pause |
5797 SUPPORTED_Asym_Pause),
5798 .media_type = ETH_PHY_SFP_FIBER,
5799 .ver_addr = 0,
5800 .req_flow_ctrl = 0,
5801 .req_line_speed = 0,
5802 .speed_cap_mask = 0,
5803 .req_duplex = 0,
5804 .rsrv = 0,
5805 .config_init = (config_init_t)bnx2x_8706_config_init,
5806 .read_status = (read_status_t)bnx2x_8706_read_status,
5807 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
5808 .config_loopback = (config_loopback_t)NULL,
5809 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5810 .hw_reset = (hw_reset_t)NULL,
5811 .set_link_led = (set_link_led_t)NULL
5812};
5813
5814static struct bnx2x_phy phy_8726 = {
5815 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
5816 .addr = 0xff,
5817 .flags = (FLAGS_HW_LOCK_REQUIRED |
5818 FLAGS_INIT_XGXS_FIRST),
5819 .def_md_devad = 0,
5820 .reserved = 0,
5821 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5822 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5823 .mdio_ctrl = 0,
5824 .supported = (SUPPORTED_10000baseT_Full |
5825 SUPPORTED_1000baseT_Full |
5826 SUPPORTED_Autoneg |
5827 SUPPORTED_FIBRE |
5828 SUPPORTED_Pause |
5829 SUPPORTED_Asym_Pause),
5830 .media_type = ETH_PHY_SFP_FIBER,
5831 .ver_addr = 0,
5832 .req_flow_ctrl = 0,
5833 .req_line_speed = 0,
5834 .speed_cap_mask = 0,
5835 .req_duplex = 0,
5836 .rsrv = 0,
5837 .config_init = (config_init_t)bnx2x_8726_config_init,
5838 .read_status = (read_status_t)bnx2x_8726_read_status,
5839 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
5840 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
5841 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5842 .hw_reset = (hw_reset_t)NULL,
5843 .set_link_led = (set_link_led_t)NULL
5844};
5845
5846static struct bnx2x_phy phy_8727 = {
5847 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
5848 .addr = 0xff,
5849 .flags = FLAGS_FAN_FAILURE_DET_REQ,
5850 .def_md_devad = 0,
5851 .reserved = 0,
5852 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5853 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5854 .mdio_ctrl = 0,
5855 .supported = (SUPPORTED_10000baseT_Full |
5856 SUPPORTED_1000baseT_Full |
5857 SUPPORTED_Autoneg |
5858 SUPPORTED_FIBRE |
5859 SUPPORTED_Pause |
5860 SUPPORTED_Asym_Pause),
5861 .media_type = ETH_PHY_SFP_FIBER,
5862 .ver_addr = 0,
5863 .req_flow_ctrl = 0,
5864 .req_line_speed = 0,
5865 .speed_cap_mask = 0,
5866 .req_duplex = 0,
5867 .rsrv = 0,
5868 .config_init = (config_init_t)bnx2x_8727_config_init,
5869 .read_status = (read_status_t)bnx2x_8727_read_status,
5870 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
5871 .config_loopback = (config_loopback_t)NULL,
5872 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5873 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
5874 .set_link_led = (set_link_led_t)NULL
5875};
5876static struct bnx2x_phy phy_8481 = {
5877 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
5878 .addr = 0xff,
5879 .flags = FLAGS_FAN_FAILURE_DET_REQ,
5880 .def_md_devad = 0,
5881 .reserved = 0,
5882 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5883 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5884 .mdio_ctrl = 0,
5885 .supported = (SUPPORTED_10baseT_Half |
5886 SUPPORTED_10baseT_Full |
5887 SUPPORTED_100baseT_Half |
5888 SUPPORTED_100baseT_Full |
5889 SUPPORTED_1000baseT_Full |
5890 SUPPORTED_10000baseT_Full |
5891 SUPPORTED_TP |
5892 SUPPORTED_Autoneg |
5893 SUPPORTED_Pause |
5894 SUPPORTED_Asym_Pause),
5895 .media_type = ETH_PHY_BASE_T,
5896 .ver_addr = 0,
5897 .req_flow_ctrl = 0,
5898 .req_line_speed = 0,
5899 .speed_cap_mask = 0,
5900 .req_duplex = 0,
5901 .rsrv = 0,
5902 .config_init = (config_init_t)bnx2x_8481_config_init,
5903 .read_status = (read_status_t)bnx2x_848xx_read_status,
5904 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
5905 .config_loopback = (config_loopback_t)NULL,
5906 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
5907 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
5908 .set_link_led = (set_link_led_t)NULL
5909};
5910
5911static struct bnx2x_phy phy_84823 = {
5912 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
5913 .addr = 0xff,
5914 .flags = FLAGS_FAN_FAILURE_DET_REQ,
5915 .def_md_devad = 0,
5916 .reserved = 0,
5917 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5918 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
5919 .mdio_ctrl = 0,
5920 .supported = (SUPPORTED_10baseT_Half |
5921 SUPPORTED_10baseT_Full |
5922 SUPPORTED_100baseT_Half |
5923 SUPPORTED_100baseT_Full |
5924 SUPPORTED_1000baseT_Full |
5925 SUPPORTED_10000baseT_Full |
5926 SUPPORTED_TP |
5927 SUPPORTED_Autoneg |
5928 SUPPORTED_Pause |
5929 SUPPORTED_Asym_Pause),
5930 .media_type = ETH_PHY_BASE_T,
5931 .ver_addr = 0,
5932 .req_flow_ctrl = 0,
5933 .req_line_speed = 0,
5934 .speed_cap_mask = 0,
5935 .req_duplex = 0,
5936 .rsrv = 0,
5937 .config_init = (config_init_t)bnx2x_848x3_config_init,
5938 .read_status = (read_status_t)bnx2x_848xx_read_status,
5939 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
5940 .config_loopback = (config_loopback_t)NULL,
5941 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
5942 .hw_reset = (hw_reset_t)NULL,
5943 .set_link_led = (set_link_led_t)NULL
5944};
5945
5946/*****************************************************************/
5947/* */
5948/* Populate the phy according. Main function: bnx2x_populate_phy */
5949/* */
5950/*****************************************************************/
5951
5952static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
5953 struct bnx2x_phy *phy, u8 port,
5954 u8 phy_index)
5955{
5956 /* Get the 4 lanes xgxs config rx and tx */
5957 u32 rx = 0, tx = 0, i;
5958 for (i = 0; i < 2; i++) {
5959 /**
5960 * INT_PHY and EXT_PHY1 share the same value location in the
5961 * shmem. When num_phys is greater than 1, than this value
5962 * applies only to EXT_PHY1
5963 */
5964
5965 rx = REG_RD(bp, shmem_base +
5966 offsetof(struct shmem_region,
5967 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
5968
5969 tx = REG_RD(bp, shmem_base +
5970 offsetof(struct shmem_region,
5971 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
5972
5973 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
5974 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
5975
5976 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
5977 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
5978 }
5979}
5980
e10bc84d
YR		 5981static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
5982 u8 phy_index, u8 port)
5983{
5984 u32 ext_phy_config = 0;
5985 switch (phy_index) {
5986 case EXT_PHY1:
5987 ext_phy_config = REG_RD(bp, shmem_base +
5988 offsetof(struct shmem_region,
5989 dev_info.port_hw_config[port].external_phy_config));
5990 break;
5991 default:
5992 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
5993 return -EINVAL;
5994 }
5995
5996 return ext_phy_config;
5997}
b7737c9b
YR		 5998static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
5999 struct bnx2x_phy *phy)
6000{
6001 u32 phy_addr;
6002 u32 chip_id;
6003 u32 switch_cfg = (REG_RD(bp, shmem_base +
6004 offsetof(struct shmem_region,
6005 dev_info.port_feature_config[port].link_config)) &
6006 PORT_FEATURE_CONNECTED_SWITCH_MASK);
6007 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
6008 switch (switch_cfg) {
6009 case SWITCH_CFG_1G:
6010 phy_addr = REG_RD(bp,
6011 NIG_REG_SERDES0_CTRL_PHY_ADDR +
6012 port * 0x10);
6013 *phy = phy_serdes;
6014 break;
6015 case SWITCH_CFG_10G:
6016 phy_addr = REG_RD(bp,
6017 NIG_REG_XGXS0_CTRL_PHY_ADDR +
6018 port * 0x18);
6019 *phy = phy_xgxs;
6020 break;
6021 default:
6022 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6023 return -EINVAL;
6024 }
6025 phy->addr = (u8)phy_addr;
6026 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
c18aa15d 6027 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
b7737c9b
YR		 6028 port);
6029 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
6030
6031 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
6032 port, phy->addr, phy->mdio_ctrl);
6033
6034 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
6035 return 0;
6036}
e10bc84d
YR		 6037
6038static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
6039 u8 phy_index,
6040 u32 shmem_base,
6041 u8 port,
6042 struct bnx2x_phy *phy)
6043{
c18aa15d
YR		 6044 u32 ext_phy_config, phy_type, config2;
6045 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
e10bc84d
YR		 6046 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
6047 phy_index, port);
b7737c9b
YR		 6048 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6049 /* Select the phy type */
6050 switch (phy_type) {
6051 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
c18aa15d 6052 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
b7737c9b
YR		 6053 *phy = phy_8073;
6054 break;
6055 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6056 *phy = phy_8705;
6057 break;
6058 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6059 *phy = phy_8706;
6060 break;
6061 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
c18aa15d 6062 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
b7737c9b
YR		 6063 *phy = phy_8726;
6064 break;
6065 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6066 /* BCM8727_NOC => BCM8727 no over current */
c18aa15d 6067 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
b7737c9b
YR		 6068 *phy = phy_8727;
6069 phy->flags |= FLAGS_NOC;
6070 break;
6071 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
c18aa15d 6072 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
b7737c9b
YR		 6073 *phy = phy_8727;
6074 break;
6075 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
6076 *phy = phy_8481;
6077 break;
6078 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6079 *phy = phy_84823;
6080 break;
6081 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6082 *phy = phy_7101;
6083 break;
6084 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6085 *phy = phy_null;
6086 return -EINVAL;
6087 default:
6088 *phy = phy_null;
6089 return 0;
6090 }
6091
e10bc84d 6092 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
b7737c9b 6093 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
62b29a5d 6094
c18aa15d
YR		 6095 /**
6096 * The shmem address of the phy version is located on different
6097 * structures. In case this structure is too old, do not set
6098 * the address
6099 */
6100 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
6101 dev_info.shared_hw_config.config2));
6102
6103 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
6104 port_mb[port].ext_phy_fw_version);
6105
6106 /* Check specific mdc mdio settings */
6107 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
6108 mdc_mdio_access = config2 &
6109 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
6110
6111 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
6112
6113 /**
6114 * In case mdc/mdio_access of the external phy is different than the
6115 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
6116 * to prevent one port interfere with another port's CL45 operations.
6117 */
6118 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
6119 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
6120 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
6121 phy_type, port, phy_index);
6122 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
6123 phy->addr, phy->mdio_ctrl);
e10bc84d
YR		 6124 return 0;
6125}
6126
6127static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
6128 u8 port, struct bnx2x_phy *phy)
6129{
6130 u8 status = 0;
b7737c9b
YR		 6131 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
6132 if (phy_index == INT_PHY)
6133 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
e10bc84d
YR		 6134 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base,
6135 port, phy);
6136 return status;
6137}
6138
b7737c9b
YR		 6139static void bnx2x_phy_def_cfg(struct link_params *params,
6140 struct bnx2x_phy *phy,
6141 u8 actual_phy_idx)
6142{
6143 struct bnx2x *bp = params->bp;
6144 u32 link_config;
6145 /* Populate the default phy configuration for MF mode */
6146 link_config = REG_RD(bp, params->shmem_base +
6147 offsetof(struct shmem_region, dev_info.
6148 port_feature_config[params->port].link_config));
6149 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
6150 offsetof(struct shmem_region, dev_info.
6151 port_hw_config[params->port].speed_capability_mask));
6152
6153 phy->req_duplex = DUPLEX_FULL;
6154 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
6155 case PORT_FEATURE_LINK_SPEED_10M_HALF:
6156 phy->req_duplex = DUPLEX_HALF;
6157 case PORT_FEATURE_LINK_SPEED_10M_FULL:
6158 phy->req_line_speed = SPEED_10;
6159 break;
6160 case PORT_FEATURE_LINK_SPEED_100M_HALF:
6161 phy->req_duplex = DUPLEX_HALF;
6162 case PORT_FEATURE_LINK_SPEED_100M_FULL:
6163 phy->req_line_speed = SPEED_100;
6164 break;
6165 case PORT_FEATURE_LINK_SPEED_1G:
6166 phy->req_line_speed = SPEED_1000;
6167 break;
6168 case PORT_FEATURE_LINK_SPEED_2_5G:
6169 phy->req_line_speed = SPEED_2500;
6170 break;
6171 case PORT_FEATURE_LINK_SPEED_10G_CX4:
6172 phy->req_line_speed = SPEED_10000;
6173 break;
6174 default:
6175 phy->req_line_speed = SPEED_AUTO_NEG;
6176 break;
6177 }
6178
6179 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
6180 case PORT_FEATURE_FLOW_CONTROL_AUTO:
6181 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
6182 break;
6183 case PORT_FEATURE_FLOW_CONTROL_TX:
6184 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
6185 break;
6186 case PORT_FEATURE_FLOW_CONTROL_RX:
6187 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
6188 break;
6189 case PORT_FEATURE_FLOW_CONTROL_BOTH:
6190 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
6191 break;
6192 default:
6193 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6194 break;
6195 }
6196}
6197
6198u8 bnx2x_phy_probe(struct link_params *params)
6199{
6200 u8 phy_index, actual_phy_idx, link_cfg_idx;
6201
6202 struct bnx2x *bp = params->bp;
6203 struct bnx2x_phy *phy;
6204 params->num_phys = 0;
6205 DP(NETIF_MSG_LINK, "Begin phy probe\n");
6206
6207 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
6208 phy_index++) {
6209 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
6210 actual_phy_idx = phy_index;
6211
6212 phy = &params->phy[actual_phy_idx];
6213 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
6214 params->port,
6215 phy) != 0) {
6216 params->num_phys = 0;
6217 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
6218 phy_index);
6219 for (phy_index = INT_PHY;
6220 phy_index < MAX_PHYS;
6221 phy_index++)
6222 *phy = phy_null;
6223 return -EINVAL;
6224 }
6225 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
6226 break;
6227
6228 bnx2x_phy_def_cfg(params, phy, actual_phy_idx);
6229 params->num_phys++;
6230 }
6231
6232 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
6233 return 0;
6234}
6235
6236u32 bnx2x_supported_attr(struct link_params *params, u8 phy_idx)
6237{
6238 if (phy_idx < params->num_phys)
6239 return params->phy[phy_idx].supported;
6240 return 0;
6241}
6242
6bbca910
YR		 6243static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6244{
e10bc84d
YR		 6245 struct bnx2x_phy phy[PORT_MAX];
6246 struct bnx2x_phy *phy_blk[PORT_MAX];
6bbca910
YR		 6247 u16 val;
6248 s8 port;
6249
6250 /* PART1 - Reset both phys */
6251 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6252 /* Extract the ext phy address for the port */
e10bc84d
YR		 6253 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base,
6254 port, &phy[port]) !=
6255 0) {
6256 DP(NETIF_MSG_LINK, "populate_phy failed\n");
6257 return -EINVAL;
6258 }
6bbca910
YR		 6259 /* disable attentions */
6260 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6261 (NIG_MASK_XGXS0_LINK_STATUS |
6262 NIG_MASK_XGXS0_LINK10G |
6263 NIG_MASK_SERDES0_LINK_STATUS |
6264 NIG_MASK_MI_INT));
6265
6bbca910
YR		 6266 /* Need to take the phy out of low power mode in order
6267 to write to access its registers */
6268 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6269 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6270
6271 /* Reset the phy */
e10bc84d 6272 bnx2x_cl45_write(bp, &phy[port],
6bbca910
YR		 6273 MDIO_PMA_DEVAD,
6274 MDIO_PMA_REG_CTRL,
6275 1<<15);
6276 }
6277
6278 /* Add delay of 150ms after reset */
6279 msleep(150);
6280
e10bc84d
YR		 6281 if (phy[PORT_0].addr & 0x1) {
6282 phy_blk[PORT_0] = &(phy[PORT_1]);
6283 phy_blk[PORT_1] = &(phy[PORT_0]);
6284 } else {
6285 phy_blk[PORT_0] = &(phy[PORT_0]);
6286 phy_blk[PORT_1] = &(phy[PORT_1]);
6287 }
6288
6bbca910
YR		 6289 /* PART2 - Download firmware to both phys */
6290 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6291 u16 fw_ver1;
6292
e10bc84d 6293 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
c18aa15d 6294 port);
6bbca910 6295
e10bc84d 6296 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6297 MDIO_PMA_DEVAD,
6298 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
16b311cc 6299 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6bbca910 6300 DP(NETIF_MSG_LINK,
16b311cc
EG		 6301 "bnx2x_8073_common_init_phy port %x:"
6302 "Download failed. fw version = 0x%x\n",
6303 port, fw_ver1);
6bbca910
YR		 6304 return -EINVAL;
6305 }
6306
6307 /* Only set bit 10 = 1 (Tx power down) */
e10bc84d 6308 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6309 MDIO_PMA_DEVAD,
6310 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6311
6312 /* Phase1 of TX_POWER_DOWN reset */
e10bc84d 6313 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 6314 MDIO_PMA_DEVAD,
6315 MDIO_PMA_REG_TX_POWER_DOWN,
6316 (val | 1<<10));
6317 }
6318
6319 /* Toggle Transmitter: Power down and then up with 600ms
6320 delay between */
6321 msleep(600);
6322
6323 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6324 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 6325 /* Phase2 of POWER_DOWN_RESET */
6bbca910 6326 /* Release bit 10 (Release Tx power down) */
e10bc84d 6327 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6328 MDIO_PMA_DEVAD,
6329 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6330
e10bc84d 6331 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 6332 MDIO_PMA_DEVAD,
6333 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6334 msleep(15);
6335
6336 /* Read modify write the SPI-ROM version select register */
e10bc84d 6337 bnx2x_cl45_read(bp, phy_blk[port],
6bbca910
YR		 6338 MDIO_PMA_DEVAD,
6339 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
e10bc84d 6340 bnx2x_cl45_write(bp, phy_blk[port],
6bbca910
YR		 6341 MDIO_PMA_DEVAD,
6342 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6343
6344 /* set GPIO2 back to LOW */
6345 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6346 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6347 }
6348 return 0;
6bbca910
YR		 6349}
6350
4d295db0
EG		 6351static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6352{
bc7f0a05 6353 s8 port, first_port, i;
4d295db0 6354 u32 swap_val, swap_override;
e10bc84d
YR		 6355 struct bnx2x_phy phy[PORT_MAX];
6356 struct bnx2x_phy *phy_blk[PORT_MAX];
4d295db0
EG		 6357 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6358 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6359 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6360
f57a6025 6361 bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override));
4d295db0
EG		 6362 msleep(5);
6363
bc7f0a05
EG		 6364 if (swap_val && swap_override)
6365 first_port = PORT_0;
6366 else
6367 first_port = PORT_1;
6368
4d295db0 6369 /* PART1 - Reset both phys */
bc7f0a05 6370 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
4d295db0 6371 /* Extract the ext phy address for the port */
e10bc84d
YR		 6372 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base,
6373 port, &phy[port]) !=
6374 0) {
6375 DP(NETIF_MSG_LINK, "populate phy failed\n");
6376 return -EINVAL;
6377 }
4d295db0
EG		 6378 /* disable attentions */
6379 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6380 (NIG_MASK_XGXS0_LINK_STATUS |
6381 NIG_MASK_XGXS0_LINK10G |
6382 NIG_MASK_SERDES0_LINK_STATUS |
6383 NIG_MASK_MI_INT));
6384
4d295db0
EG		 6385
6386 /* Reset the phy */
e10bc84d 6387 bnx2x_cl45_write(bp, &phy[port],
4d295db0
EG		 6388 MDIO_PMA_DEVAD,
6389 MDIO_PMA_REG_CTRL,
6390 1<<15);
6391 }
6392
6393 /* Add delay of 150ms after reset */
6394 msleep(150);
e10bc84d
YR		 6395 if (phy[PORT_0].addr & 0x1) {
6396 phy_blk[PORT_0] = &(phy[PORT_1]);
6397 phy_blk[PORT_1] = &(phy[PORT_0]);
6398 } else {
6399 phy_blk[PORT_0] = &(phy[PORT_0]);
6400 phy_blk[PORT_1] = &(phy[PORT_1]);
6401 }
4d295db0 6402 /* PART2 - Download firmware to both phys */
e10bc84d 6403 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4d295db0
EG		 6404 u16 fw_ver1;
6405
e10bc84d 6406 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
c18aa15d 6407 port);
e10bc84d 6408 bnx2x_cl45_read(bp, phy_blk[port],
4d295db0
EG		 6409 MDIO_PMA_DEVAD,
6410 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6411 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6412 DP(NETIF_MSG_LINK,
bc7f0a05 6413 "bnx2x_8727_common_init_phy port %x:"
4d295db0
EG		 6414 "Download failed. fw version = 0x%x\n",
6415 port, fw_ver1);
6416 return -EINVAL;
6417 }
4d295db0
EG		 6418 }
6419
4d295db0
EG		 6420 return 0;
6421}
6422
589abe3a
EG		 6423static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6424{
589abe3a
EG		 6425 u32 val;
6426 s8 port;
e10bc84d 6427 struct bnx2x_phy phy;
589abe3a
EG		 6428 /* Use port1 because of the static port-swap */
6429 /* Enable the module detection interrupt */
6430 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6431 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6432 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6433 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6434
f57a6025 6435 bnx2x_ext_phy_hw_reset(bp, 1);
589abe3a
EG		 6436 msleep(5);
6437 for (port = 0; port < PORT_MAX; port++) {
6438 /* Extract the ext phy address for the port */
e10bc84d
YR		 6439 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base,
6440 port, &phy) !=
6441 0) {
6442 DP(NETIF_MSG_LINK, "populate phy failed\n");
6443 return -EINVAL;
6444 }
589abe3a 6445
e10bc84d
YR		 6446 /* Reset phy*/
6447 bnx2x_cl45_write(bp, &phy,
6448 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
589abe3a 6449
589abe3a
EG		 6450
6451 /* Set fault module detected LED on */
6452 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6453 MISC_REGISTERS_GPIO_HIGH,
6454 port);
6455 }
6456
6457 return 0;
6458}
6459
6bbca910
YR		 6460u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6461{
6462 u8 rc = 0;
6463 u32 ext_phy_type;
6464
f5372251 6465 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6bbca910
YR		 6466
6467 /* Read the ext_phy_type for arbitrary port(0) */
6468 ext_phy_type = XGXS_EXT_PHY_TYPE(
6469 REG_RD(bp, shmem_base +
6470 offsetof(struct shmem_region,
6471 dev_info.port_hw_config[0].external_phy_config)));
6472
6473 switch (ext_phy_type) {
6474 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6475 {
6476 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
6477 break;
6478 }
4d295db0
EG		 6479
6480 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6481 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6482 rc = bnx2x_8727_common_init_phy(bp, shmem_base);
6483 break;
6484
589abe3a
EG		 6485 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6486 /* GPIO1 affects both ports, so there's need to pull
6487 it for single port alone */
6488 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
4f60dab1 6489 break;
6bbca910
YR		 6490 default:
6491 DP(NETIF_MSG_LINK,
6492 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6493 ext_phy_type);
6494 break;
6495 }
6496
6497 return rc;
6498}
6499
e10bc84d 6500void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
ea4e040a
YR		 6501{
6502 u16 val, cnt;
6503
e10bc84d 6504 bnx2x_cl45_read(bp, phy,
ea4e040a
YR		 6505 MDIO_PMA_DEVAD,
6506 MDIO_PMA_REG_7101_RESET, &val);
6507
6508 for (cnt = 0; cnt < 10; cnt++) {
6509 msleep(50);
6510 /* Writes a self-clearing reset */
e10bc84d 6511 bnx2x_cl45_write(bp, phy,
ea4e040a
YR		 6512 MDIO_PMA_DEVAD,
6513 MDIO_PMA_REG_7101_RESET,
6514 (val | (1<<15)));
6515 /* Wait for clear */
e10bc84d 6516 bnx2x_cl45_read(bp, phy,
ea4e040a
YR		 6517 MDIO_PMA_DEVAD,
6518 MDIO_PMA_REG_7101_RESET, &val);
6519
6520 if ((val & (1<<15)) == 0)
6521 break;
6522 }
6523}
d90d96ba
YR		 6524
6525u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base)
6526{
6527 u8 phy_index;
6528 struct bnx2x_phy phy;
6529 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
6530 phy_index++) {
6531 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
6532 0, &phy) != 0) {
6533 DP(NETIF_MSG_LINK, "populate phy failed\n");
6534 return 0;
6535 }
6536
6537 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
6538 return 1;
6539 }
6540 return 0;
6541}
6542
6543u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
6544 u32 shmem_base,
6545 u8 port)
6546{
6547 u8 phy_index, fan_failure_det_req = 0;
6548 struct bnx2x_phy phy;
6549 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
6550 phy_index++) {
6551 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
6552 port, &phy)
6553 != 0) {
6554 DP(NETIF_MSG_LINK, "populate phy failed\n");
6555 return 0;
6556 }
6557 fan_failure_det_req |= (phy.flags &
6558 FLAGS_FAN_FAILURE_DET_REQ);
6559 }
6560 return fan_failure_det_req;
6561}
6562
6563void bnx2x_hw_reset_phy(struct link_params *params)
6564{
6565 u8 phy_index;
6566 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
6567 phy_index++) {
6568 if (params->phy[phy_index].hw_reset) {
6569 params->phy[phy_index].hw_reset(
6570 &params->phy[phy_index],
6571 params);
6572 params->phy[phy_index] = phy_null;
6573 }
6574 }
6575}
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