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cd88ccee | 1 | /* Copyright 2008-2011 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef BNX2X_LINK_H | |
18 | #define BNX2X_LINK_H | |
19 | ||
20 | ||
21 | ||
22 | /***********************************************************/ | |
23 | /* Defines */ | |
24 | /***********************************************************/ | |
f2e0899f DK |
25 | #define DEFAULT_PHY_DEV_ADDR 3 |
26 | #define E2_DEFAULT_PHY_DEV_ADDR 5 | |
ea4e040a YR |
27 | |
28 | ||
29 | ||
c0700f90 DM |
30 | #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO |
31 | #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX | |
32 | #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX | |
33 | #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH | |
34 | #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE | |
ea4e040a | 35 | |
3c9ada22 YR |
36 | #define NET_SERDES_IF_XFI 1 |
37 | #define NET_SERDES_IF_SFI 2 | |
38 | #define NET_SERDES_IF_KR 3 | |
39 | #define NET_SERDES_IF_DXGXS 4 | |
40 | ||
cd88ccee | 41 | #define SPEED_AUTO_NEG 0 |
3c9ada22 | 42 | #define SPEED_20000 20000 |
ea4e040a | 43 | |
4d295db0 EG |
44 | #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 |
45 | #define SFP_EEPROM_VENDOR_NAME_SIZE 16 | |
46 | #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25 | |
47 | #define SFP_EEPROM_VENDOR_OUI_SIZE 3 | |
cd88ccee YR |
48 | #define SFP_EEPROM_PART_NO_ADDR 0x28 |
49 | #define SFP_EEPROM_PART_NO_SIZE 16 | |
3c9ada22 YR |
50 | #define SFP_EEPROM_REVISION_ADDR 0x38 |
51 | #define SFP_EEPROM_REVISION_SIZE 4 | |
52 | #define SFP_EEPROM_SERIAL_ADDR 0x44 | |
53 | #define SFP_EEPROM_SERIAL_SIZE 16 | |
54 | #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ | |
55 | #define SFP_EEPROM_DATE_SIZE 6 | |
4d295db0 | 56 | #define PWR_FLT_ERR_MSG_LEN 250 |
b7737c9b YR |
57 | |
58 | #define XGXS_EXT_PHY_TYPE(ext_phy_config) \ | |
59 | ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) | |
60 | #define XGXS_EXT_PHY_ADDR(ext_phy_config) \ | |
61 | (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ | |
62 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) | |
63 | #define SERDES_EXT_PHY_TYPE(ext_phy_config) \ | |
64 | ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) | |
65 | ||
e10bc84d YR |
66 | /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ |
67 | #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) | |
68 | /* Single Media board contains single external phy */ | |
69 | #define SINGLE_MEDIA(params) (params->num_phys == 2) | |
a22f0788 YR |
70 | /* Dual Media board contains two external phy with different media */ |
71 | #define DUAL_MEDIA(params) (params->num_phys == 3) | |
3c9ada22 YR |
72 | |
73 | #define FW_PARAM_PHY_ADDR_MASK 0x000000FF | |
74 | #define FW_PARAM_PHY_TYPE_MASK 0x0000FF00 | |
75 | #define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 | |
cd88ccee | 76 | #define FW_PARAM_MDIO_CTRL_OFFSET 16 |
3c9ada22 YR |
77 | #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ |
78 | FW_PARAM_PHY_ADDR_MASK) | |
79 | #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ | |
80 | FW_PARAM_PHY_TYPE_MASK) | |
81 | #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ | |
82 | FW_PARAM_MDIO_CTRL_MASK) >> \ | |
83 | FW_PARAM_MDIO_CTRL_OFFSET) | |
a22f0788 YR |
84 | #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ |
85 | (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET) | |
bcab15c5 | 86 | |
bcab15c5 VZ |
87 | |
88 | #define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 | |
89 | #define PFC_BRB_FULL_LB_XON_THRESHOLD 250 | |
90 | ||
619c5cb6 | 91 | #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) |
ea4e040a YR |
92 | /***********************************************************/ |
93 | /* Structs */ | |
94 | /***********************************************************/ | |
e10bc84d YR |
95 | #define INT_PHY 0 |
96 | #define EXT_PHY1 1 | |
a22f0788 YR |
97 | #define EXT_PHY2 2 |
98 | #define MAX_PHYS 3 | |
e10bc84d | 99 | |
b7737c9b YR |
100 | /* Same configuration is shared between the XGXS and the first external phy */ |
101 | #define LINK_CONFIG_SIZE (MAX_PHYS - 1) | |
102 | #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \ | |
103 | 0 : (_phy_idx - 1)) | |
e10bc84d YR |
104 | /***********************************************************/ |
105 | /* bnx2x_phy struct */ | |
106 | /* Defines the required arguments and function per phy */ | |
107 | /***********************************************************/ | |
108 | struct link_vars; | |
109 | struct link_params; | |
110 | struct bnx2x_phy; | |
111 | ||
b7737c9b YR |
112 | typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params, |
113 | struct link_vars *vars); | |
114 | typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params, | |
115 | struct link_vars *vars); | |
116 | typedef void (*link_reset_t)(struct bnx2x_phy *phy, | |
117 | struct link_params *params); | |
118 | typedef void (*config_loopback_t)(struct bnx2x_phy *phy, | |
119 | struct link_params *params); | |
120 | typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len); | |
121 | typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params); | |
122 | typedef void (*set_link_led_t)(struct bnx2x_phy *phy, | |
123 | struct link_params *params, u8 mode); | |
a22f0788 YR |
124 | typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy, |
125 | struct link_params *params, u32 action); | |
b7737c9b | 126 | |
e10bc84d YR |
127 | struct bnx2x_phy { |
128 | u32 type; | |
129 | ||
130 | /* Loaded during init */ | |
131 | u8 addr; | |
9045f6b4 YR |
132 | u8 def_md_devad; |
133 | u16 flags; | |
b7737c9b YR |
134 | /* Require HW lock */ |
135 | #define FLAGS_HW_LOCK_REQUIRED (1<<0) | |
136 | /* No Over-Current detection */ | |
137 | #define FLAGS_NOC (1<<1) | |
138 | /* Fan failure detection required */ | |
139 | #define FLAGS_FAN_FAILURE_DET_REQ (1<<2) | |
140 | /* Initialize first the XGXS and only then the phy itself */ | |
a22f0788 | 141 | #define FLAGS_INIT_XGXS_FIRST (1<<3) |
3c9ada22 | 142 | #define FLAGS_WC_DUAL_MODE (1<<4) |
9380bb9e | 143 | #define FLAGS_4_PORT_MODE (1<<5) |
a22f0788 YR |
144 | #define FLAGS_REARM_LATCH_SIGNAL (1<<6) |
145 | #define FLAGS_SFP_NOT_APPROVED (1<<7) | |
3c9ada22 YR |
146 | #define FLAGS_MDC_MDIO_WA (1<<8) |
147 | #define FLAGS_DUMMY_READ (1<<9) | |
b7737c9b | 148 | |
b7737c9b YR |
149 | /* preemphasis values for the rx side */ |
150 | u16 rx_preemphasis[4]; | |
151 | ||
152 | /* preemphasis values for the tx side */ | |
153 | u16 tx_preemphasis[4]; | |
154 | ||
155 | /* EMAC address for access MDIO */ | |
e10bc84d | 156 | u32 mdio_ctrl; |
b7737c9b YR |
157 | |
158 | u32 supported; | |
159 | ||
160 | u32 media_type; | |
161 | #define ETH_PHY_UNSPECIFIED 0x0 | |
162 | #define ETH_PHY_SFP_FIBER 0x1 | |
163 | #define ETH_PHY_XFP_FIBER 0x2 | |
164 | #define ETH_PHY_DA_TWINAX 0x3 | |
165 | #define ETH_PHY_BASE_T 0x4 | |
3c9ada22 YR |
166 | #define ETH_PHY_KR 0xf0 |
167 | #define ETH_PHY_CX4 0xf1 | |
b7737c9b YR |
168 | #define ETH_PHY_NOT_PRESENT 0xff |
169 | ||
170 | /* The address in which version is located*/ | |
171 | u32 ver_addr; | |
172 | ||
173 | u16 req_flow_ctrl; | |
174 | ||
175 | u16 req_line_speed; | |
176 | ||
177 | u32 speed_cap_mask; | |
178 | ||
179 | u16 req_duplex; | |
180 | u16 rsrv; | |
181 | /* Called per phy/port init, and it configures LASI, speed, autoneg, | |
182 | duplex, flow control negotiation, etc. */ | |
183 | config_init_t config_init; | |
184 | ||
185 | /* Called due to interrupt. It determines the link, speed */ | |
186 | read_status_t read_status; | |
187 | ||
188 | /* Called when driver is unloading. Should reset the phy */ | |
189 | link_reset_t link_reset; | |
190 | ||
191 | /* Set the loopback configuration for the phy */ | |
192 | config_loopback_t config_loopback; | |
193 | ||
194 | /* Format the given raw number into str up to len */ | |
195 | format_fw_ver_t format_fw_ver; | |
196 | ||
197 | /* Reset the phy (both ports) */ | |
198 | hw_reset_t hw_reset; | |
199 | ||
200 | /* Set link led mode (on/off/oper)*/ | |
201 | set_link_led_t set_link_led; | |
a22f0788 YR |
202 | |
203 | /* PHY Specific tasks */ | |
204 | phy_specific_func_t phy_specific_func; | |
205 | #define DISABLE_TX 1 | |
206 | #define ENABLE_TX 2 | |
e10bc84d YR |
207 | }; |
208 | ||
ea4e040a YR |
209 | /* Inputs parameters to the CLC */ |
210 | struct link_params { | |
211 | ||
212 | u8 port; | |
213 | ||
214 | /* Default / User Configuration */ | |
215 | u8 loopback_mode; | |
cd88ccee YR |
216 | #define LOOPBACK_NONE 0 |
217 | #define LOOPBACK_EMAC 1 | |
218 | #define LOOPBACK_BMAC 2 | |
de6eae1f | 219 | #define LOOPBACK_XGXS 3 |
ea4e040a | 220 | #define LOOPBACK_EXT_PHY 4 |
cd88ccee YR |
221 | #define LOOPBACK_EXT 5 |
222 | #define LOOPBACK_UMAC 6 | |
223 | #define LOOPBACK_XMAC 7 | |
ea4e040a | 224 | |
ea4e040a YR |
225 | /* Device parameters */ |
226 | u8 mac_addr[6]; | |
8c99e7b0 | 227 | |
a22f0788 YR |
228 | u16 req_duplex[LINK_CONFIG_SIZE]; |
229 | u16 req_flow_ctrl[LINK_CONFIG_SIZE]; | |
230 | ||
231 | u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ | |
232 | ||
ea4e040a YR |
233 | /* shmem parameters */ |
234 | u32 shmem_base; | |
a22f0788 YR |
235 | u32 shmem2_base; |
236 | u32 speed_cap_mask[LINK_CONFIG_SIZE]; | |
ea4e040a YR |
237 | u32 switch_cfg; |
238 | #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH | |
239 | #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH | |
240 | #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT | |
241 | ||
ea4e040a | 242 | u32 lane_config; |
659bc5c4 | 243 | |
ea4e040a YR |
244 | /* Phy register parameter */ |
245 | u32 chip_id; | |
246 | ||
cd88ccee | 247 | /* features */ |
589abe3a | 248 | u32 feature_config_flags; |
cd88ccee YR |
249 | #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) |
250 | #define FEATURE_CONFIG_PFC_ENABLED (1<<1) | |
251 | #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) | |
a22f0788 | 252 | #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) |
e10bc84d YR |
253 | /* Will be populated during common init */ |
254 | struct bnx2x_phy phy[MAX_PHYS]; | |
255 | ||
256 | /* Will be populated during common init */ | |
257 | u8 num_phys; | |
1ef70b9c | 258 | |
b7737c9b YR |
259 | u8 rsrv; |
260 | u16 hw_led_mode; /* part of the hw_config read from the shmem */ | |
a22f0788 | 261 | u32 multi_phy_config; |
b7737c9b | 262 | |
ea4e040a YR |
263 | /* Device pointer passed to all callback functions */ |
264 | struct bnx2x *bp; | |
a22f0788 YR |
265 | u16 req_fc_auto_adv; /* Should be set to TX / BOTH when |
266 | req_flow_ctrl is set to AUTO */ | |
ea4e040a YR |
267 | }; |
268 | ||
269 | /* Output parameters */ | |
270 | struct link_vars { | |
1ef70b9c | 271 | u8 phy_flags; |
3c9ada22 YR |
272 | #define PHY_XGXS_FLAG (1<<0) |
273 | #define PHY_SGMII_FLAG (1<<1) | |
1ef70b9c EG |
274 | |
275 | u8 mac_type; | |
276 | #define MAC_TYPE_NONE 0 | |
277 | #define MAC_TYPE_EMAC 1 | |
278 | #define MAC_TYPE_BMAC 2 | |
619c5cb6 VZ |
279 | #define MAC_TYPE_UMAC 3 |
280 | #define MAC_TYPE_XMAC 4 | |
1ef70b9c | 281 | |
ea4e040a YR |
282 | u8 phy_link_up; /* internal phy link indication */ |
283 | u8 link_up; | |
1ef70b9c EG |
284 | |
285 | u16 line_speed; | |
ea4e040a | 286 | u16 duplex; |
1ef70b9c | 287 | |
ea4e040a | 288 | u16 flow_ctrl; |
1ef70b9c | 289 | u16 ieee_fc; |
ea4e040a | 290 | |
ea4e040a YR |
291 | /* The same definitions as the shmem parameter */ |
292 | u32 link_status; | |
c688fe2f YR |
293 | u8 fault_detected; |
294 | u8 rsrv1; | |
295 | u16 rsrv2; | |
020c7e3f | 296 | u32 aeu_int_mask; |
ea4e040a YR |
297 | }; |
298 | ||
299 | /***********************************************************/ | |
300 | /* Functions */ | |
301 | /***********************************************************/ | |
fcf5b650 | 302 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars); |
ea4e040a | 303 | |
589abe3a EG |
304 | /* Reset the link. Should be called when driver or interface goes down |
305 | Before calling phy firmware upgrade, the reset_ext_phy should be set | |
306 | to 0 */ | |
fcf5b650 YR |
307 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, |
308 | u8 reset_ext_phy); | |
ea4e040a YR |
309 | |
310 | /* bnx2x_link_update should be called upon link interrupt */ | |
fcf5b650 | 311 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars); |
ea4e040a | 312 | |
e10bc84d | 313 | /* use the following phy functions to read/write from external_phy |
ea4e040a YR |
314 | In order to use it to read/write internal phy registers, use |
315 | DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as | |
ea4e040a | 316 | the register */ |
fcf5b650 YR |
317 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
318 | u8 devad, u16 reg, u16 *ret_val); | |
319 | ||
320 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, | |
321 | u8 devad, u16 reg, u16 val); | |
ea4e040a | 322 | |
ea4e040a | 323 | /* Reads the link_status from the shmem, |
33471629 | 324 | and update the link vars accordingly */ |
ea4e040a YR |
325 | void bnx2x_link_status_update(struct link_params *input, |
326 | struct link_vars *output); | |
327 | /* returns string representing the fw_version of the external phy */ | |
fcf5b650 YR |
328 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, |
329 | u8 *version, u16 len); | |
ea4e040a YR |
330 | |
331 | /* Set/Unset the led | |
332 | Basically, the CLC takes care of the led for the link, but in case one needs | |
33471629 | 333 | to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to |
ea4e040a | 334 | blink the led, and LED_MODE_OFF to set the led off.*/ |
fcf5b650 YR |
335 | int bnx2x_set_led(struct link_params *params, |
336 | struct link_vars *vars, u8 mode, u32 speed); | |
7f02c4ad YR |
337 | #define LED_MODE_OFF 0 |
338 | #define LED_MODE_ON 1 | |
339 | #define LED_MODE_OPER 2 | |
340 | #define LED_MODE_FRONT_PANEL_OFF 3 | |
ea4e040a | 341 | |
589abe3a EG |
342 | /* bnx2x_handle_module_detect_int should be called upon module detection |
343 | interrupt */ | |
344 | void bnx2x_handle_module_detect_int(struct link_params *params); | |
345 | ||
ea4e040a YR |
346 | /* Get the actual link status. In case it returns 0, link is up, |
347 | otherwise link is down*/ | |
fcf5b650 YR |
348 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
349 | u8 is_serdes); | |
ea4e040a | 350 | |
6bbca910 | 351 | /* One-time initialization for external phy after power up */ |
fcf5b650 YR |
352 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
353 | u32 shmem2_base_path[], u32 chip_id); | |
ea4e040a | 354 | |
f57a6025 EG |
355 | /* Reset the external PHY using GPIO */ |
356 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); | |
357 | ||
e10bc84d YR |
358 | /* Reset the external of SFX7101 */ |
359 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy); | |
356e2385 | 360 | |
65a001ba | 361 | /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ |
fcf5b650 YR |
362 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
363 | struct link_params *params, u16 addr, | |
364 | u8 byte_cnt, u8 *o_buf); | |
65a001ba | 365 | |
d90d96ba YR |
366 | void bnx2x_hw_reset_phy(struct link_params *params); |
367 | ||
368 | /* Checks if HW lock is required for this phy/board type */ | |
a22f0788 YR |
369 | u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, |
370 | u32 shmem2_base); | |
371 | ||
a22f0788 YR |
372 | /* Check swap bit and adjust PHY order */ |
373 | u32 bnx2x_phy_selection(struct link_params *params); | |
374 | ||
e10bc84d | 375 | /* Probe the phys on board, and populate them in "params" */ |
fcf5b650 YR |
376 | int bnx2x_phy_probe(struct link_params *params); |
377 | ||
d90d96ba | 378 | /* Checks if fan failure detection is required on one of the phys on board */ |
a22f0788 YR |
379 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base, |
380 | u32 shmem2_base, u8 port); | |
d90d96ba | 381 | |
9380bb9e YR |
382 | |
383 | ||
619c5cb6 VZ |
384 | /* DCBX structs */ |
385 | ||
386 | /* Number of maximum COS per chip */ | |
387 | #define DCBX_E2E3_MAX_NUM_COS (2) | |
388 | #define DCBX_E3B0_MAX_NUM_COS_PORT0 (6) | |
389 | #define DCBX_E3B0_MAX_NUM_COS_PORT1 (3) | |
390 | #define DCBX_E3B0_MAX_NUM_COS ( \ | |
391 | MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \ | |
392 | DCBX_E3B0_MAX_NUM_COS_PORT1)) | |
393 | ||
394 | #define DCBX_MAX_NUM_COS ( \ | |
395 | MAXVAL(DCBX_E3B0_MAX_NUM_COS, \ | |
396 | DCBX_E2E3_MAX_NUM_COS)) | |
397 | ||
e4901dde VZ |
398 | /* PFC port configuration params */ |
399 | struct bnx2x_nig_brb_pfc_port_params { | |
400 | /* NIG */ | |
401 | u32 pause_enable; | |
402 | u32 llfc_out_en; | |
403 | u32 llfc_enable; | |
404 | u32 pkt_priority_to_cos; | |
619c5cb6 VZ |
405 | u8 num_of_rx_cos_priority_mask; |
406 | u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS]; | |
e4901dde VZ |
407 | u32 llfc_high_priority_classes; |
408 | u32 llfc_low_priority_classes; | |
409 | /* BRB */ | |
410 | u32 cos0_pauseable; | |
411 | u32 cos1_pauseable; | |
412 | }; | |
413 | ||
6c3218c6 YR |
414 | |
415 | /* ETS port configuration params */ | |
416 | struct bnx2x_ets_bw_params { | |
417 | u8 bw; | |
418 | }; | |
419 | ||
420 | struct bnx2x_ets_sp_params { | |
421 | /** | |
422 | * valid values are 0 - 5. 0 is highest strict priority. | |
423 | * There can't be two COS's with the same pri. | |
424 | */ | |
425 | u8 pri; | |
426 | }; | |
427 | ||
428 | enum bnx2x_cos_state { | |
429 | bnx2x_cos_state_strict = 0, | |
430 | bnx2x_cos_state_bw = 1, | |
431 | }; | |
432 | ||
433 | struct bnx2x_ets_cos_params { | |
434 | enum bnx2x_cos_state state ; | |
435 | union { | |
436 | struct bnx2x_ets_bw_params bw_params; | |
437 | struct bnx2x_ets_sp_params sp_params; | |
438 | } params; | |
439 | }; | |
440 | ||
441 | struct bnx2x_ets_params { | |
442 | u8 num_of_cos; /* Number of valid COS entries*/ | |
443 | struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS]; | |
444 | }; | |
445 | ||
e4901dde VZ |
446 | /** |
447 | * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB | |
448 | * when link is already up | |
449 | */ | |
9380bb9e | 450 | int bnx2x_update_pfc(struct link_params *params, |
e4901dde VZ |
451 | struct link_vars *vars, |
452 | struct bnx2x_nig_brb_pfc_port_params *pfc_params); | |
453 | ||
454 | ||
455 | /* Used to configure the ETS to disable */ | |
6c3218c6 YR |
456 | int bnx2x_ets_disabled(struct link_params *params, |
457 | struct link_vars *vars); | |
e4901dde VZ |
458 | |
459 | /* Used to configure the ETS to BW limited */ | |
460 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, | |
cd88ccee | 461 | const u32 cos1_bw); |
e4901dde VZ |
462 | |
463 | /* Used to configure the ETS to strict */ | |
fcf5b650 | 464 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos); |
e4901dde | 465 | |
6c3218c6 YR |
466 | |
467 | /* Configure the COS to ETS according to BW and SP settings.*/ | |
468 | int bnx2x_ets_e3b0_config(const struct link_params *params, | |
469 | const struct link_vars *vars, | |
470 | const struct bnx2x_ets_params *ets_params); | |
e4901dde VZ |
471 | /* Read pfc statistic*/ |
472 | void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, | |
473 | u32 pfc_frames_sent[2], | |
474 | u32 pfc_frames_received[2]); | |
020c7e3f YR |
475 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, |
476 | u32 chip_id, u32 shmem_base, u32 shmem2_base, | |
477 | u8 port); | |
3c9ada22 YR |
478 | |
479 | int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, | |
480 | struct link_params *params); | |
ea4e040a | 481 | #endif /* BNX2X_LINK_H */ |