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bnx2x: prevent race between undi_unload and load flows
[mirror_ubuntu-eoan-kernel.git] / drivers / net / bnx2x / bnx2x_main.c
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34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea 41#include <net/ip.h>
619c5cb6 42#include <net/ipv6.h>
a2fbb9ea
ET		 43#include <net/tcp.h>
44#include <net/checksum.h>
34f80b04 45#include <net/ip6_checksum.h>
a2fbb9ea
ET		 46#include <linux/workqueue.h>
47#include <linux/crc32.h>
34f80b04 48#include <linux/crc32c.h>
a2fbb9ea
ET		 49#include <linux/prefetch.h>
50#include <linux/zlib.h>
a2fbb9ea 51#include <linux/io.h>
45229b42 52#include <linux/stringify.h>
7ab24bfd 53#include <linux/vmalloc.h>
a2fbb9ea 54
a2fbb9ea
ET		 55#include "bnx2x.h"
56#include "bnx2x_init.h"
94a78b79 57#include "bnx2x_init_ops.h"
9f6c9258 58#include "bnx2x_cmn.h"
e4901dde 59#include "bnx2x_dcb.h"
042181f5 60#include "bnx2x_sp.h"
a2fbb9ea 61
94a78b79
VZ		 62#include <linux/firmware.h>
63#include "bnx2x_fw_file_hdr.h"
64/* FW files */
45229b42
BH		 65#define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 70#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 72#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 73
34f80b04
EG		 74/* Time in jiffies before concluding the transmitter is hung */
75#define TX_TIMEOUT (5*HZ)
a2fbb9ea 76
53a10565 77static char version[] __devinitdata =
619c5cb6 78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
24e3fcef 81MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 82MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
a2fbb9ea
ET		 86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 88MODULE_FIRMWARE(FW_FILE_NAME_E1);
89MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 90MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 91
555f6c78
EG		 92static int multi_mode = 1;
93module_param(multi_mode, int, 0);
ca00392c
EG		 94MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
96
d6214d7a 97int num_queues;
54b9ddaa
VZ		 98module_param(num_queues, int, 0);
99MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
19680c48 103module_param(disable_tpa, int, 0);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
9ee3d37b
DK		 106#define INT_MODE_INTx 1
107#define INT_MODE_MSI 2
8badd27a
EG		 108static int int_mode;
109module_param(int_mode, int, 0);
619c5cb6 110MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 111 "(1 INT#x; 2 MSI)");
8badd27a 112
a18f5128
EG		 113static int dropless_fc;
114module_param(dropless_fc, int, 0);
115MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
9898f86d 117static int poll;
a2fbb9ea 118module_param(poll, int, 0);
9898f86d 119MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 120
121static int mrrs = -1;
122module_param(mrrs, int, 0);
123MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
124
9898f86d 125static int debug;
a2fbb9ea 126module_param(debug, int, 0);
9898f86d
EG		 127MODULE_PARM_DESC(debug, " Default debug msglevel");
128
a2fbb9ea 129
619c5cb6
VZ		 130
131struct workqueue_struct *bnx2x_wq;
ec6ba945 132
a2fbb9ea
ET		 133enum bnx2x_board_type {
134 BCM57710 = 0,
619c5cb6
VZ		 135 BCM57711,
136 BCM57711E,
137 BCM57712,
138 BCM57712_MF,
139 BCM57800,
140 BCM57800_MF,
141 BCM57810,
142 BCM57810_MF,
143 BCM57840,
144 BCM57840_MF
a2fbb9ea
ET		 145};
146
34f80b04 147/* indexed by board_type, above */
53a10565 148static struct {
a2fbb9ea
ET		 149 char *name;
150} board_info[] __devinitdata = {
619c5cb6
VZ		 151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
a2fbb9ea
ET		 163};
164
619c5cb6
VZ		 165#ifndef PCI_DEVICE_ID_NX2_57710
166#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167#endif
168#ifndef PCI_DEVICE_ID_NX2_57711
169#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170#endif
171#ifndef PCI_DEVICE_ID_NX2_57711E
172#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173#endif
174#ifndef PCI_DEVICE_ID_NX2_57712
175#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176#endif
177#ifndef PCI_DEVICE_ID_NX2_57712_MF
178#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179#endif
180#ifndef PCI_DEVICE_ID_NX2_57800
181#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182#endif
183#ifndef PCI_DEVICE_ID_NX2_57800_MF
184#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57810
187#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57810_MF
190#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57840
193#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57840_MF
196#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197#endif
a3aa1884 198static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 210 { 0 }
211};
212
213MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
214
215/****************************************************************************
216* General service functions
217****************************************************************************/
218
619c5cb6
VZ		 219static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
221{
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
224}
225
226static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
228{
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
231
232 __storm_memset_dma_mapping(bp, addr, mapping);
233}
234
235static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
236 u16 pf_id)
523224a3 237{
619c5cb6
VZ		 238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
239 pf_id);
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
241 pf_id);
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
243 pf_id);
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
245 pf_id);
523224a3
DK		 246}
247
619c5cb6
VZ		 248static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
249 u8 enable)
250{
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
252 enable);
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
254 enable);
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
256 enable);
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
258 enable);
259}
523224a3
DK		 260
261static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
263 u16 pfid)
264{
265 size_t size = sizeof(struct event_ring_data);
266
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
268
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
270}
271
272static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
273 u16 pfid)
274{
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
277}
278
a2fbb9ea
ET		 279/* used only at init
280 * locking is done by mcp
281 */
8d96286a 282static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 283{
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
288}
289
a2fbb9ea
ET		 290static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
291{
292 u32 val;
293
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
298
299 return val;
300}
a2fbb9ea 301
f2e0899f
DK		 302#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306#define DMAE_DP_DST_NONE "dst_addr [none]"
307
8d96286a 308static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
309 int msglvl)
f2e0899f
DK		 310{
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
312
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
322 dmae->comp_val);
323 else
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
330 dmae->comp_val);
331 break;
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
340 dmae->comp_val);
341 else
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
348 dmae->comp_val);
349 break;
350 default:
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
354 "dst_addr [none]\n"
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
358 dmae->comp_val);
359 else
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
362 "dst_addr [none]\n"
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
366 dmae->comp_val);
367 break;
368 }
369
370}
371
a2fbb9ea 372/* copy command into DMAE command memory and set DMAE command go */
6c719d00 373void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 374{
375 u32 cmd_offset;
376 int i;
377
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381
ad8d3948
EG		 382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 384 }
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
386}
387
f2e0899f 388u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 389{
f2e0899f
DK		 390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
391 DMAE_CMD_C_ENABLE);
392}
ad8d3948 393
f2e0899f
DK		 394u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395{
396 return opcode & ~DMAE_CMD_SRC_RESET;
397}
ad8d3948 398
f2e0899f
DK		 399u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
401{
402 u32 opcode = 0;
403
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 406
f2e0899f
DK		 407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 413
a2fbb9ea 414#ifdef __BIG_ENDIAN
f2e0899f 415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 416#else
f2e0899f 417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 418#endif
f2e0899f
DK		 419 if (with_comp)
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
421 return opcode;
422}
423
8d96286a 424static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
f2e0899f
DK		 427{
428 memset(dmae, 0, sizeof(struct dmae_command));
429
430 /* set the opcode */
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
433
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
438}
439
440/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 441static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
f2e0899f
DK		 443{
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 446 int rc = 0;
447
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 451
619c5cb6
VZ		 452 /*
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
456 */
6e30dd4e 457 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 458
f2e0899f 459 /* reset completion */
a2fbb9ea
ET		 460 *wb_comp = 0;
461
f2e0899f
DK		 462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 464
f2e0899f 465 /* wait for completion */
a2fbb9ea 466 udelay(5);
f2e0899f 467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
469
ad8d3948 470 if (!cnt) {
c3eefaf6 471 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 472 rc = DMAE_TIMEOUT;
473 goto unlock;
a2fbb9ea 474 }
ad8d3948 475 cnt--;
f2e0899f 476 udelay(50);
a2fbb9ea 477 }
f2e0899f
DK		 478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
480 rc = DMAE_PCI_ERROR;
481 }
482
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 486
f2e0899f 487unlock:
6e30dd4e 488 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 489 return rc;
490}
491
492void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
493 u32 len32)
494{
495 struct dmae_command dmae;
496
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
499
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
503 return;
504 }
505
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
514 dmae.len = len32;
515
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 520}
521
c18487ee 522void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 523{
5ff7b6d4 524 struct dmae_command dmae;
ad8d3948
EG		 525
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
528 int i;
529
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
534 return;
535 }
536
f2e0899f
DK		 537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 539
f2e0899f 540 /* fill in addresses and len */
5ff7b6d4
EG		 541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
545 dmae.len = len32;
ad8d3948 546
f2e0899f 547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 548
f2e0899f
DK		 549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 551}
552
8d96286a 553static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
554 u32 addr, u32 len)
573f2035 555{
02e3c6cb 556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 557 int offset = 0;
558
02e3c6cb 559 while (len > dmae_wr_max) {
573f2035 560 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
563 len -= dmae_wr_max;
573f2035
EG		 564 }
565
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
567}
568
ad8d3948
EG		 569/* used only for slowpath so not inlined */
570static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
571{
572 u32 wb_write[2];
573
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 577}
a2fbb9ea 578
ad8d3948
EG		 579#ifdef USE_WB_RD
580static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
581{
582 u32 wb_data[2];
583
584 REG_RD_DMAE(bp, reg, wb_data, 2);
585
586 return HILO_U64(wb_data[0], wb_data[1]);
587}
588#endif
589
a2fbb9ea
ET		 590static int bnx2x_mc_assert(struct bnx2x *bp)
591{
a2fbb9ea 592 char last_idx;
34f80b04
EG		 593 int i, rc = 0;
594 u32 row0, row1, row2, row3;
595
596 /* XSTORM */
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 if (last_idx)
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
618 rc++;
619 } else {
620 break;
621 }
622 }
623
624 /* TSTORM */
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 if (last_idx)
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 /* CSTORM */
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 if (last_idx)
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
674 rc++;
675 } else {
676 break;
677 }
678 }
679
680 /* USTORM */
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 if (last_idx)
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
a2fbb9ea
ET		 705 }
706 }
34f80b04 707
a2fbb9ea
ET		 708 return rc;
709}
c14423fe 710
7a25cc73 711void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 712{
7a25cc73 713 u32 addr, val;
a2fbb9ea 714 u32 mark, offset;
4781bfad 715 __be32 data[9];
a2fbb9ea 716 int word;
f2e0899f 717 u32 trace_shmem_base;
2145a920
VZ		 718 if (BP_NOMCP(bp)) {
719 BNX2X_ERR("NO MCP - can not dump\n");
720 return;
721 }
7a25cc73
DK		 722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
726
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 730
f2e0899f
DK		 731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
733 else
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 736 mark = REG_RD(bp, addr);
f2e0899f
DK		 737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 740
7a25cc73 741 printk("%s", lvl);
f2e0899f 742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 743 for (word = 0; word < 8; word++)
cdaa7cb8 744 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 745 data[8] = 0x0;
7995c64e 746 pr_cont("%s", (char *)data);
a2fbb9ea 747 }
cdaa7cb8 748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 749 for (word = 0; word < 8; word++)
cdaa7cb8 750 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 751 data[8] = 0x0;
7995c64e 752 pr_cont("%s", (char *)data);
a2fbb9ea 753 }
7a25cc73
DK		 754 printk("%s" "end of fw dump\n", lvl);
755}
756
757static inline void bnx2x_fw_dump(struct bnx2x *bp)
758{
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 760}
761
6c719d00 762void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 763{
764 int i;
523224a3
DK		 765 u16 j;
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768#ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
6383c0b3 770 u8 cos;
523224a3 771#endif
a2fbb9ea 772
66e855f3
YG		 773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
775
a2fbb9ea
ET		 776 BNX2X_ERR("begin crash dump -----------------\n");
777
8440d2b6
EG		 778 /* Indices */
779 /* Common */
523224a3 780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
789 BNX2X_ERR(" def (");
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
791 pr_cont("0x%x%s",
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
794
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 i*sizeof(u32));
799
619c5cb6 800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
523224a3 801 "pf_id(0x%x) vnic_id(0x%x) "
619c5cb6
VZ		 802 "vf_id(0x%x) vf_valid (0x%x) "
803 "state(0x%x)\n",
523224a3
DK		 804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 809 sp_sb_data.p_func.vf_valid,
810 sp_sb_data.state);
523224a3 811
8440d2b6 812
ec6ba945 813 for_each_eth_queue(bp, i) {
a2fbb9ea 814 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 815 int loop;
f2e0899f 816 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 819 CHIP_IS_E1x(bp) ?
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
523224a3 822 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 823 CHIP_IS_E1x(bp) ?
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
6383c0b3 826 u8 data_size, cos;
523224a3 827 u32 *sb_data_p;
6383c0b3 828 struct bnx2x_fp_txdata txdata;
523224a3
DK		 829
830 /* Rx */
cdaa7cb8 831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 832 " rx_comp_prod(0x%x)"
cdaa7cb8 833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 834 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 835 fp->rx_comp_prod,
66e855f3 836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 838 " fp_hc_idx(0x%x)\n",
8440d2b6 839 fp->rx_sge_prod, fp->last_max_sge,
523224a3 840 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 841
523224a3 842 /* Tx */
6383c0b3
AE		 843 for_each_cos_in_tx_queue(fp, cos)
844 {
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
851 txdata.tx_bd_cons,
852 le16_to_cpu(*txdata.tx_cons_sb));
853 }
523224a3 854
619c5cb6
VZ		 855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 857
858 /* host sb data */
859
ec6ba945
VZ		 860#ifdef BCM_CNIC
861 if (IS_FCOE_FP(fp))
862 continue;
863#endif
523224a3
DK		 864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
866 pr_cont("0x%x%s",
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
869
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
872 pr_cont("0x%x%s",
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
875 /* fw sb data */
619c5cb6
VZ		 876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
523224a3 879 data_size /= sizeof(u32);
619c5cb6
VZ		 880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
882 (u32 *)&sb_data_e2;
523224a3
DK		 883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
887 j * sizeof(u32));
888
619c5cb6
VZ		 889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
892 "state(0x%x)\n",
f2e0899f
DK		 893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
f2e0899f 899 } else {
619c5cb6
VZ		 900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
902 "state(0x%x)\n",
f2e0899f
DK		 903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
f2e0899f 909 }
523224a3
DK		 910
911 /* SB_SMs data */
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
917 hc_sm_p[j].__flags,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
922 }
923
924 /* Indecies data */
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
928 hc_index_p[j].flags,
929 hc_index_p[j].timeout);
930 }
8440d2b6 931 }
a2fbb9ea 932
523224a3 933#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 934 /* Rings */
935 /* Rx */
ec6ba945 936 for_each_rx_queue(bp, i) {
8440d2b6 937 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 938
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 941 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
944
c3eefaf6
EG		 945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 947 }
948
3196a88a
EG		 949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
8440d2b6 951 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
954
c3eefaf6
EG		 955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 957 }
958
a2fbb9ea
ET		 959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
963
c3eefaf6
EG		 964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 966 }
967 }
968
8440d2b6 969 /* Tx */
ec6ba945 970 for_each_tx_queue(bp, i) {
8440d2b6 971 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
974
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
980
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
984 sw_bd->first_bd);
985 }
8440d2b6 986
6383c0b3
AE		 987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 991
6383c0b3
AE		 992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
993 "[%x:%x:%x:%x]\n",
994 i, cos, j, tx_bd[0], tx_bd[1],
995 tx_bd[2], tx_bd[3]);
996 }
8440d2b6
EG		 997 }
998 }
523224a3 999#endif
34f80b04 1000 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1003}
1004
619c5cb6
VZ		 1005/*
1006 * FLR Support for E2
1007 *
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009 * initialization.
1010 */
1011#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012#define FLR_WAIT_INTERAVAL 50 /* usec */
1013#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1014
1015struct pbf_pN_buf_regs {
1016 int pN;
1017 u32 init_crd;
1018 u32 crd;
1019 u32 crd_freed;
1020};
1021
1022struct pbf_pN_cmd_regs {
1023 int pN;
1024 u32 lines_occup;
1025 u32 lines_freed;
1026};
1027
1028static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1030 u32 poll_count)
1031{
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1034
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1038
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1042
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1045 if (cur_cnt--) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1049 } else {
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1051 regs->pN);
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1053 regs->pN, crd);
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1056 break;
1057 }
1058 }
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1061}
1062
1063static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1065 u32 poll_count)
1066{
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1069
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1072
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1075
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1077 if (cur_cnt--) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1081 } else {
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1083 regs->pN);
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1085 regs->pN, occup);
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1087 regs->pN, freed);
1088 break;
1089 }
1090 }
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1093}
1094
1095static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1097{
1098 u32 cur_cnt = poll_count;
1099 u32 val;
1100
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1103
1104 return val;
1105}
1106
1107static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1109{
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1111 if (val != 0) {
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1113 return 1;
1114 }
1115 return 0;
1116}
1117
1118static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1119{
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1123
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1126
1127 return FLR_POLL_CNT;
1128}
1129
1130static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1131{
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1151 };
1152
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_CREDIT_Q0 :
1159 PBF_REG_P0_CREDIT,
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_CREDIT_Q1 :
1168 PBF_REG_P1_CREDIT,
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1177 PBF_REG_P4_CREDIT,
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1181 };
1182
1183 int i;
1184
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1188
1189
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1193}
1194
1195#define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1197
1198#define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1200
1201#define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203
1204
1205static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1206 u32 poll_cnt)
1207{
1208 struct sdm_op_gen op_gen = {0};
1209
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1212 int ret = 0;
1213
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1216 return 1;
1217 }
1218
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1223
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1226
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1229 ret = 1;
1230 }
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1233
1234 return ret;
1235}
1236
1237static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1238{
1239 int pos;
1240 u16 status;
1241
77c98e6a 1242 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1243 if (!pos)
1244 return false;
1245
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1248}
1249
1250/* PF FLR specific routines
1251*/
1252static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1253{
1254
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1259 poll_cnt))
1260 return 1;
1261
1262
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1267 poll_cnt))
1268 return 1;
1269
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1274 poll_cnt))
1275 return 1;
1276
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1281 poll_cnt))
1282 return 1;
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1286 poll_cnt))
1287 return 1;
1288
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1293 poll_cnt))
1294 return 1;
1295
1296 return 0;
1297}
1298
1299static void bnx2x_hw_enable_status(struct bnx2x *bp)
1300{
1301 u32 val;
1302
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1305
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1311
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1314
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1320
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1323
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1326 val);
1327}
1328
1329static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1330{
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1332
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1334
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1337
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1340 return -EBUSY;
1341
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1343
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1346 return -EBUSY;
1347
1348 /* ATC cleanup */
1349
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1352
1353 /* Wait 100ms (not adjusted according to platform) */
1354 msleep(100);
1355
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1359
1360 /* Debug */
1361 bnx2x_hw_enable_status(bp);
1362
1363 /*
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1366 */
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1368
1369 return 0;
1370}
1371
f2e0899f 1372static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1373{
34f80b04 1374 int port = BP_PORT(bp);
a2fbb9ea
ET		 1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1379
1380 if (msix) {
8badd27a
EG		 1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1385 } else if (msi) {
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1390 } else {
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1395
a0fd065c
DK		 1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1398 val, port, addr);
615f8fd9 1399
a0fd065c 1400 REG_WR(bp, addr, val);
615f8fd9 1401
a0fd065c
DK		 1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1403 }
a2fbb9ea
ET		 1404 }
1405
a0fd065c
DK		 1406 if (CHIP_IS_E1(bp))
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1408
8badd27a
EG		 1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1411
1412 REG_WR(bp, addr, val);
37dbbf32
EG		 1413 /*
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1415 */
1416 mmiowb();
1417 barrier();
34f80b04 1418
f2e0899f 1419 if (!CHIP_IS_E1(bp)) {
34f80b04 1420 /* init leading/trailing edge */
fb3bff17 1421 if (IS_MF(bp)) {
8badd27a 1422 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1423 if (bp->port.pmf)
4acac6a5
EG		 1424 /* enable nig and gpio3 attention */
1425 val |= 0x1100;
34f80b04
EG		 1426 } else
1427 val = 0xffff;
1428
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1431 }
37dbbf32
EG		 1432
1433 /* Make sure that interrupts are indeed enabled from here on */
1434 mmiowb();
a2fbb9ea
ET		 1435}
1436
f2e0899f
DK		 1437static void bnx2x_igu_int_enable(struct bnx2x *bp)
1438{
1439 u32 val;
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1442
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1444
1445 if (msix) {
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1451 } else if (msi) {
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1457 } else {
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1463 }
1464
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1467
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1469
1470 barrier();
1471
1472 /* init leading/trailing edge */
1473 if (IS_MF(bp)) {
1474 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1475 if (bp->port.pmf)
1476 /* enable nig and gpio3 attention */
1477 val |= 0x1100;
1478 } else
1479 val = 0xffff;
1480
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1483
1484 /* Make sure that interrupts are indeed enabled from here on */
1485 mmiowb();
1486}
1487
1488void bnx2x_int_enable(struct bnx2x *bp)
1489{
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1492 else
1493 bnx2x_igu_int_enable(bp);
1494}
1495
1496static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1497{
34f80b04 1498 int port = BP_PORT(bp);
a2fbb9ea
ET		 1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1501
a0fd065c
DK		 1502 /*
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1506 */
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1511 */
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1513
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517 } else
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1522
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1524 val, port, addr);
1525
8badd27a
EG		 1526 /* flush all outstanding writes */
1527 mmiowb();
1528
a2fbb9ea
ET		 1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532}
1533
f2e0899f
DK		 1534static void bnx2x_igu_int_disable(struct bnx2x *bp)
1535{
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1537
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1541
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1543
1544 /* flush all outstanding writes */
1545 mmiowb();
1546
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550}
1551
6383c0b3 1552void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1553{
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1556 else
1557 bnx2x_igu_int_disable(bp);
1558}
1559
9f6c9258 1560void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1561{
a2fbb9ea 1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1563 int i, offset;
a2fbb9ea 1564
f8ef6e44
YG		 1565 if (disable_hw)
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1568
1569 /* make sure all ISRs are done */
1570 if (msix) {
8badd27a
EG		 1571 synchronize_irq(bp->msix_table[0].vector);
1572 offset = 1;
37b091ba
MC		 1573#ifdef BCM_CNIC
1574 offset++;
1575#endif
ec6ba945 1576 for_each_eth_queue(bp, i)
754a2f52 1577 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1578 } else
1579 synchronize_irq(bp->pdev->irq);
1580
1581 /* make sure sp_task is not running */
1cf167f2 1582 cancel_delayed_work(&bp->sp_task);
3deb8167 1583 cancel_delayed_work(&bp->period_task);
1cf167f2 1584 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1585}
1586
34f80b04 1587/* fast path */
a2fbb9ea
ET		 1588
1589/*
34f80b04 1590 * General service functions
a2fbb9ea
ET		 1591 */
1592
72fd0718
VZ		 1593/* Return true if succeeded to acquire the lock */
1594static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1595{
1596 u32 lock_status;
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1600
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1602
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1605 DP(NETIF_MSG_HW,
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1608 return false;
72fd0718
VZ		 1609 }
1610
1611 if (func <= 5)
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1613 else
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1616
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1621 return true;
1622
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1624 return false;
1625}
1626
c9ee9206
VZ		 1627/**
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1629 *
1630 * @bp: driver handle
1631 *
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1634 */
1635static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1636{
1637 if (BP_PATH(bp))
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1639 else
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1641}
1642
1643/**
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1645 *
1646 * @bp: driver handle
1647 *
1648 * Tries to aquire a leader lock for cuurent engine.
1649 */
1650static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1651{
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1653}
1654
993ac7b5 1655#ifdef BCM_CNIC
619c5cb6 1656static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1657#endif
3196a88a 1658
619c5cb6 1659void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1660{
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1666
34f80b04 1667 DP(BNX2X_MSG_SP,
a2fbb9ea 1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1669 fp->index, cid, command, bp->state,
34f80b04 1670 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1671
619c5cb6
VZ		 1672 switch (command) {
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1674 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1676 break;
d6cae238 1677
619c5cb6 1678 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1679 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1680 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1681 break;
1682
6383c0b3
AE		 1683 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1684 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1685 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1686 break;
1687
619c5cb6 1688 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1689 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1690 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1691 break;
1692
619c5cb6 1693 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1694 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1695 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1696 break;
1697
619c5cb6 1698 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1699 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1700 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1701 break;
619c5cb6
VZ		 1702
1703 default:
1704 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1705 command, fp->index);
1706 return;
523224a3 1707 }
3196a88a 1708
619c5cb6
VZ		 1709 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1710 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1711 /* q_obj->complete_cmd() failure means that this was
1712 * an unexpected completion.
1713 *
1714 * In this case we don't want to increase the bp->spq_left
1715 * because apparently we haven't sent this command the first
1716 * place.
1717 */
1718#ifdef BNX2X_STOP_ON_ERROR
1719 bnx2x_panic();
1720#else
1721 return;
1722#endif
1723
8fe23fbd 1724 smp_mb__before_atomic_inc();
6e30dd4e 1725 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1726 /* push the change in bp->spq_left and towards the memory */
1727 smp_mb__after_atomic_inc();
49d66772 1728
d6cae238
VZ		 1729 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1730
523224a3 1731 return;
a2fbb9ea
ET		 1732}
1733
619c5cb6
VZ		 1734void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1735 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1736{
1737 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1738
1739 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1740 start);
1741}
1742
9f6c9258 1743irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1744{
555f6c78 1745 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1746 u16 status = bnx2x_ack_int(bp);
34f80b04 1747 u16 mask;
ca00392c 1748 int i;
6383c0b3 1749 u8 cos;
a2fbb9ea 1750
34f80b04 1751 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1752 if (unlikely(status == 0)) {
1753 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1754 return IRQ_NONE;
1755 }
f5372251 1756 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1757
3196a88a
EG		 1758#ifdef BNX2X_STOP_ON_ERROR
1759 if (unlikely(bp->panic))
1760 return IRQ_HANDLED;
1761#endif
1762
ec6ba945 1763 for_each_eth_queue(bp, i) {
ca00392c 1764 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1765
6383c0b3 1766 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1767 if (status & mask) {
619c5cb6 1768 /* Handle Rx or Tx according to SB id */
54b9ddaa 1769 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1770 for_each_cos_in_tx_queue(fp, cos)
1771 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1772 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1773 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1774 status &= ~mask;
1775 }
a2fbb9ea
ET		 1776 }
1777
993ac7b5 1778#ifdef BCM_CNIC
523224a3 1779 mask = 0x2;
993ac7b5
MC		 1780 if (status & (mask | 0x1)) {
1781 struct cnic_ops *c_ops = NULL;
1782
619c5cb6
VZ		 1783 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1784 rcu_read_lock();
1785 c_ops = rcu_dereference(bp->cnic_ops);
1786 if (c_ops)
1787 c_ops->cnic_handler(bp->cnic_data, NULL);
1788 rcu_read_unlock();
1789 }
993ac7b5
MC		 1790
1791 status &= ~mask;
1792 }
1793#endif
a2fbb9ea 1794
34f80b04 1795 if (unlikely(status & 0x1)) {
1cf167f2 1796 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1797
1798 status &= ~0x1;
1799 if (!status)
1800 return IRQ_HANDLED;
1801 }
1802
cdaa7cb8
VZ		 1803 if (unlikely(status))
1804 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1805 status);
a2fbb9ea 1806
c18487ee 1807 return IRQ_HANDLED;
a2fbb9ea
ET		 1808}
1809
c18487ee
YR		 1810/* Link */
1811
1812/*
1813 * General service functions
1814 */
a2fbb9ea 1815
9f6c9258 1816int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1817{
1818 u32 lock_status;
1819 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1820 int func = BP_FUNC(bp);
1821 u32 hw_lock_control_reg;
c18487ee 1822 int cnt;
a2fbb9ea 1823
c18487ee
YR		 1824 /* Validating that the resource is within range */
1825 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1826 DP(NETIF_MSG_HW,
1827 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1828 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1829 return -EINVAL;
1830 }
a2fbb9ea 1831
4a37fb66
YG		 1832 if (func <= 5) {
1833 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1834 } else {
1835 hw_lock_control_reg =
1836 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1837 }
1838
c18487ee 1839 /* Validating that the resource is not already taken */
4a37fb66 1840 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1841 if (lock_status & resource_bit) {
1842 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1843 lock_status, resource_bit);
1844 return -EEXIST;
1845 }
a2fbb9ea 1846
46230476
EG		 1847 /* Try for 5 second every 5ms */
1848 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1849 /* Try to acquire the lock */
4a37fb66
YG		 1850 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1851 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1852 if (lock_status & resource_bit)
1853 return 0;
a2fbb9ea 1854
c18487ee 1855 msleep(5);
a2fbb9ea 1856 }
c18487ee
YR		 1857 DP(NETIF_MSG_HW, "Timeout\n");
1858 return -EAGAIN;
1859}
a2fbb9ea 1860
c9ee9206
VZ		 1861int bnx2x_release_leader_lock(struct bnx2x *bp)
1862{
1863 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1864}
1865
9f6c9258 1866int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1867{
1868 u32 lock_status;
1869 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1870 int func = BP_FUNC(bp);
1871 u32 hw_lock_control_reg;
a2fbb9ea 1872
72fd0718
VZ		 1873 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1874
c18487ee
YR		 1875 /* Validating that the resource is within range */
1876 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1877 DP(NETIF_MSG_HW,
1878 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1879 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1880 return -EINVAL;
1881 }
1882
4a37fb66
YG		 1883 if (func <= 5) {
1884 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1885 } else {
1886 hw_lock_control_reg =
1887 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1888 }
1889
c18487ee 1890 /* Validating that the resource is currently taken */
4a37fb66 1891 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1892 if (!(lock_status & resource_bit)) {
1893 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1894 lock_status, resource_bit);
1895 return -EFAULT;
a2fbb9ea
ET		 1896 }
1897
9f6c9258
DK		 1898 REG_WR(bp, hw_lock_control_reg, resource_bit);
1899 return 0;
c18487ee 1900}
a2fbb9ea 1901
9f6c9258 1902
4acac6a5
EG		 1903int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1904{
1905 /* The GPIO should be swapped if swap register is set and active */
1906 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1907 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1908 int gpio_shift = gpio_num +
1909 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1910 u32 gpio_mask = (1 << gpio_shift);
1911 u32 gpio_reg;
1912 int value;
1913
1914 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1915 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1916 return -EINVAL;
1917 }
1918
1919 /* read GPIO value */
1920 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1921
1922 /* get the requested pin value */
1923 if ((gpio_reg & gpio_mask) == gpio_mask)
1924 value = 1;
1925 else
1926 value = 0;
1927
1928 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1929
1930 return value;
1931}
1932
17de50b7 1933int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1934{
1935 /* The GPIO should be swapped if swap register is set and active */
1936 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1937 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1938 int gpio_shift = gpio_num +
1939 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1940 u32 gpio_mask = (1 << gpio_shift);
1941 u32 gpio_reg;
a2fbb9ea 1942
c18487ee
YR		 1943 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1944 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1945 return -EINVAL;
1946 }
a2fbb9ea 1947
4a37fb66 1948 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1949 /* read GPIO and mask except the float bits */
1950 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1951
c18487ee
YR		 1952 switch (mode) {
1953 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1954 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1955 gpio_num, gpio_shift);
1956 /* clear FLOAT and set CLR */
1957 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1959 break;
a2fbb9ea 1960
c18487ee
YR		 1961 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1963 gpio_num, gpio_shift);
1964 /* clear FLOAT and set SET */
1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1967 break;
a2fbb9ea 1968
17de50b7 1969 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1971 gpio_num, gpio_shift);
1972 /* set FLOAT */
1973 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1974 break;
a2fbb9ea 1975
c18487ee
YR		 1976 default:
1977 break;
a2fbb9ea
ET		 1978 }
1979
c18487ee 1980 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1981 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1982
c18487ee 1983 return 0;
a2fbb9ea
ET		 1984}
1985
0d40f0d4
YR		 1986int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1987{
1988 u32 gpio_reg = 0;
1989 int rc = 0;
1990
1991 /* Any port swapping should be handled by caller. */
1992
1993 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994 /* read GPIO and mask except the float bits */
1995 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1997 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1998 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1999
2000 switch (mode) {
2001 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2002 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2003 /* set CLR */
2004 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2005 break;
2006
2007 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2008 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2009 /* set SET */
2010 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2011 break;
2012
2013 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2014 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2015 /* set FLOAT */
2016 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2017 break;
2018
2019 default:
2020 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2021 rc = -EINVAL;
2022 break;
2023 }
2024
2025 if (rc == 0)
2026 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2027
2028 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2029
2030 return rc;
2031}
2032
4acac6a5
EG		 2033int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2034{
2035 /* The GPIO should be swapped if swap register is set and active */
2036 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2037 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2038 int gpio_shift = gpio_num +
2039 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2040 u32 gpio_mask = (1 << gpio_shift);
2041 u32 gpio_reg;
2042
2043 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2044 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 return -EINVAL;
2046 }
2047
2048 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2049 /* read GPIO int */
2050 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2051
2052 switch (mode) {
2053 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2054 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2055 "output low\n", gpio_num, gpio_shift);
2056 /* clear SET and set CLR */
2057 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2058 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2059 break;
2060
2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2062 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2063 "output high\n", gpio_num, gpio_shift);
2064 /* clear CLR and set SET */
2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2067 break;
2068
2069 default:
2070 break;
2071 }
2072
2073 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2075
2076 return 0;
2077}
2078
c18487ee 2079static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 2080{
c18487ee
YR		 2081 u32 spio_mask = (1 << spio_num);
2082 u32 spio_reg;
a2fbb9ea 2083
c18487ee
YR		 2084 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2085 (spio_num > MISC_REGISTERS_SPIO_7)) {
2086 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2087 return -EINVAL;
a2fbb9ea
ET		 2088 }
2089
4a37fb66 2090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2091 /* read SPIO and mask except the float bits */
2092 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2093
c18487ee 2094 switch (mode) {
6378c025 2095 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 2096 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2097 /* clear FLOAT and set CLR */
2098 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2099 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2100 break;
a2fbb9ea 2101
6378c025 2102 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 2103 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2104 /* clear FLOAT and set SET */
2105 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2106 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2107 break;
a2fbb9ea 2108
c18487ee
YR		 2109 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2110 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2111 /* set FLOAT */
2112 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2113 break;
a2fbb9ea 2114
c18487ee
YR		 2115 default:
2116 break;
a2fbb9ea
ET		 2117 }
2118
c18487ee 2119 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2120 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2121
a2fbb9ea
ET		 2122 return 0;
2123}
2124
9f6c9258 2125void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2126{
a22f0788 2127 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2128 switch (bp->link_vars.ieee_fc &
2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2130 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2131 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2132 ADVERTISED_Pause);
c18487ee 2133 break;
356e2385 2134
c18487ee 2135 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2136 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2137 ADVERTISED_Pause);
c18487ee 2138 break;
356e2385 2139
c18487ee 2140 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2141 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2142 break;
356e2385 2143
c18487ee 2144 default:
a22f0788 2145 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2146 ADVERTISED_Pause);
c18487ee
YR		 2147 break;
2148 }
2149}
f1410647 2150
9f6c9258 2151u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2152{
19680c48
EG		 2153 if (!BP_NOMCP(bp)) {
2154 u8 rc;
a22f0788
YR		 2155 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2156 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1cb0c788
YR		 2157 /*
2158 * Initialize link parameters structure variables
2159 * It is recommended to turn off RX FC for jumbo frames
2160 * for better performance
2161 */
2162 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
c0700f90 2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2164 else
c0700f90 2165 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2166
4a37fb66 2167 bnx2x_acquire_phy_lock(bp);
b5bf9068 2168
a22f0788 2169 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2170 struct link_params *lp = &bp->link_params;
2171 lp->loopback_mode = LOOPBACK_XGXS;
2172 /* do PHY loopback at 10G speed, if possible */
2173 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2174 if (lp->speed_cap_mask[cfx_idx] &
2175 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2176 lp->req_line_speed[cfx_idx] =
2177 SPEED_10000;
2178 else
2179 lp->req_line_speed[cfx_idx] =
2180 SPEED_1000;
2181 }
a22f0788 2182 }
b5bf9068 2183
19680c48 2184 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2185
4a37fb66 2186 bnx2x_release_phy_lock(bp);
a2fbb9ea 2187
3c96c68b
EG		 2188 bnx2x_calc_fc_adv(bp);
2189
b5bf9068
EG		 2190 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2191 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2192 bnx2x_link_report(bp);
3deb8167
YR		 2193 } else
2194 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2195 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2196 return rc;
2197 }
f5372251 2198 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2199 return -EINVAL;
a2fbb9ea
ET		 2200}
2201
9f6c9258 2202void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2203{
19680c48 2204 if (!BP_NOMCP(bp)) {
4a37fb66 2205 bnx2x_acquire_phy_lock(bp);
54c2fb78 2206 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2207 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2208 bnx2x_release_phy_lock(bp);
a2fbb9ea 2209
19680c48
EG		 2210 bnx2x_calc_fc_adv(bp);
2211 } else
f5372251 2212 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2213}
a2fbb9ea 2214
c18487ee
YR		 2215static void bnx2x__link_reset(struct bnx2x *bp)
2216{
19680c48 2217 if (!BP_NOMCP(bp)) {
4a37fb66 2218 bnx2x_acquire_phy_lock(bp);
589abe3a 2219 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2220 bnx2x_release_phy_lock(bp);
19680c48 2221 } else
f5372251 2222 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2223}
a2fbb9ea 2224
a22f0788 2225u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2226{
2145a920 2227 u8 rc = 0;
a2fbb9ea 2228
2145a920
VZ		 2229 if (!BP_NOMCP(bp)) {
2230 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2231 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2232 is_serdes);
2145a920
VZ		 2233 bnx2x_release_phy_lock(bp);
2234 } else
2235 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2236
c18487ee
YR		 2237 return rc;
2238}
a2fbb9ea 2239
8a1c38d1 2240static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2241{
8a1c38d1
EG		 2242 u32 r_param = bp->link_vars.line_speed / 8;
2243 u32 fair_periodic_timeout_usec;
2244 u32 t_fair;
34f80b04 2245
8a1c38d1
EG		 2246 memset(&(bp->cmng.rs_vars), 0,
2247 sizeof(struct rate_shaping_vars_per_port));
2248 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2249
8a1c38d1
EG		 2250 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2251 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2252
8a1c38d1
EG		 2253 /* this is the threshold below which no timer arming will occur
2254 1.25 coefficient is for the threshold to be a little bigger
2255 than the real time, to compensate for timer in-accuracy */
2256 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2257 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2258
8a1c38d1
EG		 2259 /* resolution of fairness timer */
2260 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2261 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2262 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2263
8a1c38d1
EG		 2264 /* this is the threshold below which we won't arm the timer anymore */
2265 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2266
8a1c38d1
EG		 2267 /* we multiply by 1e3/8 to get bytes/msec.
2268 We don't want the credits to pass a credit
2269 of the t_fair*FAIR_MEM (algorithm resolution) */
2270 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2271 /* since each tick is 4 usec */
2272 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2273}
2274
2691d51d
EG		 2275/* Calculates the sum of vn_min_rates.
2276 It's needed for further normalizing of the min_rates.
2277 Returns:
2278 sum of vn_min_rates.
2279 or
2280 0 - if all the min_rates are 0.
2281 In the later case fainess algorithm should be deactivated.
2282 If not all min_rates are zero then those that are zeroes will be set to 1.
2283 */
2284static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2285{
2286 int all_zero = 1;
2691d51d
EG		 2287 int vn;
2288
2289 bp->vn_weight_sum = 0;
2290 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 2291 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2292 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2293 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2294
2295 /* Skip hidden vns */
2296 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2297 continue;
2298
2299 /* If min rate is zero - set it to 1 */
2300 if (!vn_min_rate)
2301 vn_min_rate = DEF_MIN_RATE;
2302 else
2303 all_zero = 0;
2304
2305 bp->vn_weight_sum += vn_min_rate;
2306 }
2307
30ae438b
DK		 2308 /* if ETS or all min rates are zeros - disable fairness */
2309 if (BNX2X_IS_ETS_ENABLED(bp)) {
2310 bp->cmng.flags.cmng_enables &=
2311 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2312 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2313 } else if (all_zero) {
b015e3d1
EG		 2314 bp->cmng.flags.cmng_enables &=
2315 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2316 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2317 " fairness will be disabled\n");
2318 } else
2319 bp->cmng.flags.cmng_enables |=
2320 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2321}
2322
f2e0899f 2323static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2324{
2325 struct rate_shaping_vars_per_vn m_rs_vn;
2326 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 2327 u32 vn_cfg = bp->mf_config[vn];
2328 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 2329 u16 vn_min_rate, vn_max_rate;
2330 int i;
2331
2332 /* If function is hidden - set min and max to zeroes */
2333 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2334 vn_min_rate = 0;
2335 vn_max_rate = 0;
2336
2337 } else {
faa6fcbb
DK		 2338 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2339
34f80b04
EG		 2340 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2341 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2342 /* If fairness is enabled (not all min rates are zeroes) and
2343 if current min rate is zero - set it to 1.
2344 This is a requirement of the algorithm. */
f2e0899f 2345 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2346 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2347
2348 if (IS_MF_SI(bp))
2349 /* maxCfg in percents of linkspeed */
2350 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2351 else
2352 /* maxCfg is absolute in 100Mb units */
2353 vn_max_rate = maxCfg * 100;
34f80b04 2354 }
f85582f8 2355
8a1c38d1 2356 DP(NETIF_MSG_IFUP,
b015e3d1 2357 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2358 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2359
2360 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2361 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2362
2363 /* global vn counter - maximal Mbps for this vn */
2364 m_rs_vn.vn_counter.rate = vn_max_rate;
2365
2366 /* quota - number of bytes transmitted in this period */
2367 m_rs_vn.vn_counter.quota =
2368 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2369
8a1c38d1 2370 if (bp->vn_weight_sum) {
34f80b04
EG		 2371 /* credit for each period of the fairness algorithm:
2372 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2373 vn_weight_sum should not be larger than 10000, thus
2374 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2375 than zero */
34f80b04 2376 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2377 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2378 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2379 (bp->cmng.fair_vars.fair_threshold +
2380 MIN_ABOVE_THRESH));
cdaa7cb8 2381 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2382 m_fair_vn.vn_credit_delta);
2383 }
2384
34f80b04
EG		 2385 /* Store it to internal memory */
2386 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2387 REG_WR(bp, BAR_XSTRORM_INTMEM +
2388 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2389 ((u32 *)(&m_rs_vn))[i]);
2390
2391 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2392 REG_WR(bp, BAR_XSTRORM_INTMEM +
2393 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2394 ((u32 *)(&m_fair_vn))[i]);
2395}
f85582f8 2396
523224a3
DK		 2397static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2398{
2399 if (CHIP_REV_IS_SLOW(bp))
2400 return CMNG_FNS_NONE;
fb3bff17 2401 if (IS_MF(bp))
523224a3
DK		 2402 return CMNG_FNS_MINMAX;
2403
2404 return CMNG_FNS_NONE;
2405}
2406
2ae17f66 2407void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2408{
0793f83f 2409 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2410
2411 if (BP_NOMCP(bp))
2412 return; /* what should be the default bvalue in this case */
2413
0793f83f
DK		 2414 /* For 2 port configuration the absolute function number formula
2415 * is:
2416 * abs_func = 2 * vn + BP_PORT + BP_PATH
2417 *
2418 * and there are 4 functions per port
2419 *
2420 * For 4 port configuration it is
2421 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2422 *
2423 * and there are 2 functions per port
2424 */
523224a3 2425 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2426 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2427
2428 if (func >= E1H_FUNC_MAX)
2429 break;
2430
f2e0899f 2431 bp->mf_config[vn] =
523224a3
DK		 2432 MF_CFG_RD(bp, func_mf_config[func].config);
2433 }
2434}
2435
2436static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2437{
2438
2439 if (cmng_type == CMNG_FNS_MINMAX) {
2440 int vn;
2441
2442 /* clear cmng_enables */
2443 bp->cmng.flags.cmng_enables = 0;
2444
2445 /* read mf conf from shmem */
2446 if (read_cfg)
2447 bnx2x_read_mf_cfg(bp);
2448
2449 /* Init rate shaping and fairness contexts */
2450 bnx2x_init_port_minmax(bp);
2451
2452 /* vn_weight_sum and enable fairness if not 0 */
2453 bnx2x_calc_vn_weight_sum(bp);
2454
2455 /* calculate and set min-max rate for each vn */
c4154f25
DK		 2456 if (bp->port.pmf)
2457 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2458 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2459
2460 /* always enable rate shaping and fairness */
2461 bp->cmng.flags.cmng_enables |=
2462 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2463 if (!bp->vn_weight_sum)
2464 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2465 " fairness will be disabled\n");
2466 return;
2467 }
2468
2469 /* rate shaping and fairness are disabled */
2470 DP(NETIF_MSG_IFUP,
2471 "rate shaping and fairness are disabled\n");
2472}
34f80b04 2473
523224a3
DK		 2474static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2475{
2476 int port = BP_PORT(bp);
2477 int func;
2478 int vn;
2479
2480 /* Set the attention towards other drivers on the same port */
2481 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2482 if (vn == BP_E1HVN(bp))
2483 continue;
2484
2485 func = ((vn << 1) | port);
2486 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2487 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2488 }
2489}
8a1c38d1 2490
c18487ee
YR		 2491/* This function is called upon link interrupt */
2492static void bnx2x_link_attn(struct bnx2x *bp)
2493{
bb2a0f7a
YG		 2494 /* Make sure that we are synced with the current statistics */
2495 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2496
c18487ee 2497 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2498
bb2a0f7a
YG		 2499 if (bp->link_vars.link_up) {
2500
1c06328c 2501 /* dropless flow control */
f2e0899f 2502 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2503 int port = BP_PORT(bp);
2504 u32 pause_enabled = 0;
2505
2506 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2507 pause_enabled = 1;
2508
2509 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2510 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2511 pause_enabled);
2512 }
2513
619c5cb6 2514 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2515 struct host_port_stats *pstats;
2516
2517 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2518 /* reset old mac stats */
bb2a0f7a
YG		 2519 memset(&(pstats->mac_stx[0]), 0,
2520 sizeof(struct mac_stx));
2521 }
f34d28ea 2522 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2523 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2524 }
2525
f2e0899f
DK		 2526 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2527 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2528
f2e0899f
DK		 2529 if (cmng_fns != CMNG_FNS_NONE) {
2530 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2531 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2532 } else
2533 /* rate shaping and fairness are disabled */
2534 DP(NETIF_MSG_IFUP,
2535 "single function mode without fairness\n");
34f80b04 2536 }
9fdc3e95 2537
2ae17f66
VZ		 2538 __bnx2x_link_report(bp);
2539
9fdc3e95
DK		 2540 if (IS_MF(bp))
2541 bnx2x_link_sync_notify(bp);
c18487ee 2542}
a2fbb9ea 2543
9f6c9258 2544void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2545{
2ae17f66 2546 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2547 return;
a2fbb9ea 2548
c18487ee 2549 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2550
bb2a0f7a
YG		 2551 if (bp->link_vars.link_up)
2552 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2553 else
2554 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2555
c18487ee
YR		 2556 /* indicate link status */
2557 bnx2x_link_report(bp);
a2fbb9ea 2558}
a2fbb9ea 2559
34f80b04
EG		 2560static void bnx2x_pmf_update(struct bnx2x *bp)
2561{
2562 int port = BP_PORT(bp);
2563 u32 val;
2564
2565 bp->port.pmf = 1;
2566 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2567
3deb8167
YR		 2568 /*
2569 * We need the mb() to ensure the ordering between the writing to
2570 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2571 */
2572 smp_mb();
2573
2574 /* queue a periodic task */
2575 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2576
ef01854e
DK		 2577 bnx2x_dcbx_pmf_update(bp);
2578
34f80b04
EG		 2579 /* enable nig attention */
2580 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2581 if (bp->common.int_block == INT_BLOCK_HC) {
2582 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2583 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2584 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2585 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2586 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2587 }
bb2a0f7a
YG		 2588
2589 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2590}
2591
c18487ee 2592/* end of Link */
a2fbb9ea
ET		 2593
2594/* slow path */
2595
2596/*
2597 * General service functions
2598 */
2599
2691d51d 2600/* send the MCP a request, block until there is a reply */
a22f0788 2601u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2602{
f2e0899f 2603 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2604 u32 seq;
2691d51d
EG		 2605 u32 rc = 0;
2606 u32 cnt = 1;
2607 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2608
c4ff7cbf 2609 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2610 seq = ++bp->fw_seq;
f2e0899f
DK		 2611 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2612 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2613
754a2f52
DK		 2614 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2615 (command | seq), param);
2691d51d
EG		 2616
2617 do {
2618 /* let the FW do it's magic ... */
2619 msleep(delay);
2620
f2e0899f 2621 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2622
c4ff7cbf
EG		 2623 /* Give the FW up to 5 second (500*10ms) */
2624 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2625
2626 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2627 cnt*delay, rc, seq);
2628
2629 /* is this a reply to our command? */
2630 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2631 rc &= FW_MSG_CODE_MASK;
2632 else {
2633 /* FW BUG! */
2634 BNX2X_ERR("FW failed to respond!\n");
2635 bnx2x_fw_dump(bp);
2636 rc = 0;
2637 }
c4ff7cbf 2638 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2639
2640 return rc;
2641}
2642
ec6ba945
VZ		 2643static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2644{
2645#ifdef BCM_CNIC
619c5cb6
VZ		 2646 /* Statistics are not supported for CNIC Clients at the moment */
2647 if (IS_FCOE_FP(fp))
ec6ba945
VZ		 2648 return false;
2649#endif
2650 return true;
2651}
2652
619c5cb6
VZ		 2653void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2654{
2655 if (CHIP_IS_E1x(bp)) {
2656 struct tstorm_eth_function_common_config tcfg = {0};
2657
2658 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2659 }
2660
2661 /* Enable the function in the FW */
2662 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2663 storm_memset_func_en(bp, p->func_id, 1);
2664
2665 /* spq */
2666 if (p->func_flgs & FUNC_FLG_SPQ) {
2667 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2668 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2669 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2670 }
2671}
2672
6383c0b3
AE		 2673/**
2674 * bnx2x_get_tx_only_flags - Return common flags
2675 *
2676 * @bp device handle
2677 * @fp queue handle
2678 * @zero_stats TRUE if statistics zeroing is needed
2679 *
2680 * Return the flags that are common for the Tx-only and not normal connections.
2681 */
2682static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2683 struct bnx2x_fastpath *fp,
2684 bool zero_stats)
28912902 2685{
619c5cb6
VZ		 2686 unsigned long flags = 0;
2687
2688 /* PF driver will always initialize the Queue to an ACTIVE state */
2689 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2690
6383c0b3
AE		 2691 /* tx only connections collect statistics (on the same index as the
2692 * parent connection). The statistics are zeroed when the parent
2693 * connection is initialized.
2694 */
2695 if (stat_counter_valid(bp, fp)) {
2696 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2697 if (zero_stats)
2698 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2699 }
2700
2701 return flags;
2702}
2703
2704static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2705 struct bnx2x_fastpath *fp,
2706 bool leading)
2707{
2708 unsigned long flags = 0;
2709
619c5cb6
VZ		 2710 /* calculate other queue flags */
2711 if (IS_MF_SD(bp))
2712 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2713
619c5cb6
VZ		 2714 if (IS_FCOE_FP(fp))
2715 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3 2716
f5219d8e 2717 if (!fp->disable_tpa) {
619c5cb6 2718 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e
VZ		 2719 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2720 }
619c5cb6 2721
619c5cb6
VZ		 2722 if (leading) {
2723 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2724 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2725 }
523224a3 2726
619c5cb6
VZ		 2727 /* Always set HW VLAN stripping */
2728 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2729
6383c0b3
AE		 2730
2731 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2732}
2733
619c5cb6 2734static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2735 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2736 u8 cos)
619c5cb6
VZ		 2737{
2738 gen_init->stat_id = bnx2x_stats_id(fp);
2739 gen_init->spcl_id = fp->cl_id;
2740
2741 /* Always use mini-jumbo MTU for FCoE L2 ring */
2742 if (IS_FCOE_FP(fp))
2743 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2744 else
2745 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2746
2747 gen_init->cos = cos;
619c5cb6
VZ		 2748}
2749
2750static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2751 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2752 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2753{
619c5cb6 2754 u8 max_sge = 0;
523224a3
DK		 2755 u16 sge_sz = 0;
2756 u16 tpa_agg_size = 0;
2757
523224a3
DK		 2758 if (!fp->disable_tpa) {
2759 pause->sge_th_hi = 250;
2760 pause->sge_th_lo = 150;
2761 tpa_agg_size = min_t(u32,
2762 (min_t(u32, 8, MAX_SKB_FRAGS) *
2763 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2764 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2765 SGE_PAGE_SHIFT;
2766 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2767 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2768 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2769 0xffff);
2770 }
2771
2772 /* pause - not for e1 */
2773 if (!CHIP_IS_E1(bp)) {
2774 pause->bd_th_hi = 350;
2775 pause->bd_th_lo = 250;
2776 pause->rcq_th_hi = 350;
2777 pause->rcq_th_lo = 250;
619c5cb6 2778
523224a3
DK		 2779 pause->pri_map = 1;
2780 }
2781
2782 /* rxq setup */
523224a3
DK		 2783 rxq_init->dscr_map = fp->rx_desc_mapping;
2784 rxq_init->sge_map = fp->rx_sge_mapping;
2785 rxq_init->rcq_map = fp->rx_comp_mapping;
2786 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2787
619c5cb6
VZ		 2788 /* This should be a maximum number of data bytes that may be
2789 * placed on the BD (not including paddings).
2790 */
2791 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2792 IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2793
523224a3 2794 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2795 rxq_init->tpa_agg_sz = tpa_agg_size;
2796 rxq_init->sge_buf_sz = sge_sz;
2797 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2798 rxq_init->rss_engine_id = BP_FUNC(bp);
2799
2800 /* Maximum number or simultaneous TPA aggregation for this Queue.
2801 *
2802 * For PF Clients it should be the maximum avaliable number.
2803 * VF driver(s) may want to define it to a smaller value.
2804 */
2805 rxq_init->max_tpa_queues =
2806 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2807 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2808
523224a3
DK		 2809 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2810 rxq_init->fw_sb_id = fp->fw_sb_id;
2811
ec6ba945
VZ		 2812 if (IS_FCOE_FP(fp))
2813 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2814 else
6383c0b3 2815 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2816}
2817
619c5cb6 2818static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2819 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2820 u8 cos)
523224a3 2821{
6383c0b3
AE		 2822 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2823 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2824 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2825 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2826
619c5cb6
VZ		 2827 /*
2828 * set the tss leading client id for TX classfication ==
2829 * leading RSS client id
2830 */
2831 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2832
ec6ba945
VZ		 2833 if (IS_FCOE_FP(fp)) {
2834 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2835 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2836 }
523224a3
DK		 2837}
2838
8d96286a 2839static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2840{
2841 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2842 struct event_ring_data eq_data = { {0} };
2843 u16 flags;
2844
619c5cb6 2845 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2846 /* reset IGU PF statistics: MSIX + ATTN */
2847 /* PF */
2848 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2849 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2850 (CHIP_MODE_IS_4_PORT(bp) ?
2851 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2852 /* ATTN */
2853 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2854 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2855 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2856 (CHIP_MODE_IS_4_PORT(bp) ?
2857 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2858 }
2859
523224a3
DK		 2860 /* function setup flags */
2861 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2862
619c5cb6
VZ		 2863 /* This flag is relevant for E1x only.
2864 * E2 doesn't have a TPA configuration in a function level.
523224a3 2865 */
619c5cb6 2866 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2867
2868 func_init.func_flgs = flags;
2869 func_init.pf_id = BP_FUNC(bp);
2870 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2871 func_init.spq_map = bp->spq_mapping;
2872 func_init.spq_prod = bp->spq_prod_idx;
2873
2874 bnx2x_func_init(bp, &func_init);
2875
2876 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2877
2878 /*
619c5cb6
VZ		 2879 * Congestion management values depend on the link rate
2880 * There is no active link so initial link rate is set to 10 Gbps.
2881 * When the link comes up The congestion management values are
2882 * re-calculated according to the actual link rate.
2883 */
523224a3
DK		 2884 bp->link_vars.line_speed = SPEED_10000;
2885 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2886
2887 /* Only the PMF sets the HW */
2888 if (bp->port.pmf)
2889 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2890
523224a3
DK		 2891 /* init Event Queue */
2892 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2893 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2894 eq_data.producer = bp->eq_prod;
2895 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2896 eq_data.sb_id = DEF_SB_ID;
2897 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2898}
2899
2900
2901static void bnx2x_e1h_disable(struct bnx2x *bp)
2902{
2903 int port = BP_PORT(bp);
2904
619c5cb6 2905 bnx2x_tx_disable(bp);
523224a3
DK		 2906
2907 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2908}
2909
2910static void bnx2x_e1h_enable(struct bnx2x *bp)
2911{
2912 int port = BP_PORT(bp);
2913
2914 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2915
2916 /* Tx queue should be only reenabled */
2917 netif_tx_wake_all_queues(bp->dev);
2918
2919 /*
2920 * Should not call netif_carrier_on since it will be called if the link
2921 * is up when checking for link state
2922 */
2923}
2924
0793f83f
DK		 2925/* called due to MCP event (on pmf):
2926 * reread new bandwidth configuration
2927 * configure FW
2928 * notify others function about the change
2929 */
2930static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2931{
2932 if (bp->link_vars.link_up) {
2933 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2934 bnx2x_link_sync_notify(bp);
2935 }
2936 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2937}
2938
2939static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2940{
2941 bnx2x_config_mf_bw(bp);
2942 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2943}
2944
523224a3
DK		 2945static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2946{
2947 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2948
2949 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2950
2951 /*
2952 * This is the only place besides the function initialization
2953 * where the bp->flags can change so it is done without any
2954 * locks
2955 */
f2e0899f 2956 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2957 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2958 bp->flags |= MF_FUNC_DIS;
2959
2960 bnx2x_e1h_disable(bp);
2961 } else {
2962 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2963 bp->flags &= ~MF_FUNC_DIS;
2964
2965 bnx2x_e1h_enable(bp);
2966 }
2967 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2968 }
2969 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2970 bnx2x_config_mf_bw(bp);
523224a3
DK		 2971 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2972 }
2973
2974 /* Report results to MCP */
2975 if (dcc_event)
2976 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2977 else
2978 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2979}
2980
2981/* must be called under the spq lock */
2982static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2983{
2984 struct eth_spe *next_spe = bp->spq_prod_bd;
2985
2986 if (bp->spq_prod_bd == bp->spq_last_bd) {
2987 bp->spq_prod_bd = bp->spq;
2988 bp->spq_prod_idx = 0;
2989 DP(NETIF_MSG_TIMER, "end of spq\n");
2990 } else {
2991 bp->spq_prod_bd++;
2992 bp->spq_prod_idx++;
2993 }
2994 return next_spe;
2995}
2996
2997/* must be called under the spq lock */
28912902
MC		 2998static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2999{
3000 int func = BP_FUNC(bp);
3001
53e51e2f
VZ		 3002 /*
3003 * Make sure that BD data is updated before writing the producer:
3004 * BD data is written to the memory, the producer is read from the
3005 * memory, thus we need a full memory barrier to ensure the ordering.
3006 */
3007 mb();
28912902 3008
523224a3 3009 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3010 bp->spq_prod_idx);
28912902
MC		 3011 mmiowb();
3012}
3013
619c5cb6
VZ		 3014/**
3015 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3016 *
3017 * @cmd: command to check
3018 * @cmd_type: command type
3019 */
3020static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3021{
3022 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3023 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3024 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3025 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3026 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3027 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3028 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3029 return true;
3030 else
3031 return false;
3032
3033}
3034
3035
3036/**
3037 * bnx2x_sp_post - place a single command on an SP ring
3038 *
3039 * @bp: driver handle
3040 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3041 * @cid: SW CID the command is related to
3042 * @data_hi: command private data address (high 32 bits)
3043 * @data_lo: command private data address (low 32 bits)
3044 * @cmd_type: command type (e.g. NONE, ETH)
3045 *
3046 * SP data is handled as if it's always an address pair, thus data fields are
3047 * not swapped to little endian in upper functions. Instead this function swaps
3048 * data as if it's two u32 fields.
3049 */
9f6c9258 3050int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3051 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3052{
28912902 3053 struct eth_spe *spe;
523224a3 3054 u16 type;
619c5cb6 3055 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3056
a2fbb9ea
ET		 3057#ifdef BNX2X_STOP_ON_ERROR
3058 if (unlikely(bp->panic))
3059 return -EIO;
3060#endif
3061
34f80b04 3062 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3063
6e30dd4e
VZ		 3064 if (common) {
3065 if (!atomic_read(&bp->eq_spq_left)) {
3066 BNX2X_ERR("BUG! EQ ring full!\n");
3067 spin_unlock_bh(&bp->spq_lock);
3068 bnx2x_panic();
3069 return -EBUSY;
3070 }
3071 } else if (!atomic_read(&bp->cq_spq_left)) {
3072 BNX2X_ERR("BUG! SPQ ring full!\n");
3073 spin_unlock_bh(&bp->spq_lock);
3074 bnx2x_panic();
3075 return -EBUSY;
a2fbb9ea 3076 }
f1410647 3077
28912902
MC		 3078 spe = bnx2x_sp_get_next(bp);
3079
a2fbb9ea 3080 /* CID needs port number to be encoded int it */
28912902 3081 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3082 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3083 HW_CID(bp, cid));
523224a3 3084
619c5cb6 3085 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3086
523224a3
DK		 3087 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3088 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3089
523224a3
DK		 3090 spe->hdr.type = cpu_to_le16(type);
3091
3092 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3093 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3094
d6cae238
VZ		 3095 /*
3096 * It's ok if the actual decrement is issued towards the memory
3097 * somewhere between the spin_lock and spin_unlock. Thus no
3098 * more explict memory barrier is needed.
3099 */
3100 if (common)
3101 atomic_dec(&bp->eq_spq_left);
3102 else
3103 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3104
a2fbb9ea 3105
cdaa7cb8 3106 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
d6cae238
VZ		 3107 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3108 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3109 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3110 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3111 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3112 HW_CID(bp, cid), data_hi, data_lo, type,
3113 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3114
28912902 3115 bnx2x_sp_prod_update(bp);
34f80b04 3116 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3117 return 0;
3118}
3119
3120/* acquire split MCP access lock register */
4a37fb66 3121static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3122{
72fd0718 3123 u32 j, val;
34f80b04 3124 int rc = 0;
a2fbb9ea
ET		 3125
3126 might_sleep();
72fd0718 3127 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3128 val = (1UL << 31);
3129 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3130 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3131 if (val & (1L << 31))
3132 break;
3133
3134 msleep(5);
3135 }
a2fbb9ea 3136 if (!(val & (1L << 31))) {
19680c48 3137 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3138 rc = -EBUSY;
3139 }
3140
3141 return rc;
3142}
3143
4a37fb66
YG		 3144/* release split MCP access lock register */
3145static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3146{
72fd0718 3147 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3148}
3149
523224a3
DK		 3150#define BNX2X_DEF_SB_ATT_IDX 0x0001
3151#define BNX2X_DEF_SB_IDX 0x0002
3152
a2fbb9ea
ET		 3153static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3154{
523224a3 3155 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3156 u16 rc = 0;
3157
3158 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3159 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3160 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3161 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3162 }
523224a3
DK		 3163
3164 if (bp->def_idx != def_sb->sp_sb.running_index) {
3165 bp->def_idx = def_sb->sp_sb.running_index;
3166 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3167 }
523224a3
DK		 3168
3169 /* Do not reorder: indecies reading should complete before handling */
3170 barrier();
a2fbb9ea
ET		 3171 return rc;
3172}
3173
3174/*
3175 * slow path service functions
3176 */
3177
3178static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3179{
34f80b04 3180 int port = BP_PORT(bp);
a2fbb9ea
ET		 3181 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3182 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3183 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3184 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3185 u32 aeu_mask;
87942b46 3186 u32 nig_mask = 0;
f2e0899f 3187 u32 reg_addr;
a2fbb9ea 3188
a2fbb9ea
ET		 3189 if (bp->attn_state & asserted)
3190 BNX2X_ERR("IGU ERROR\n");
3191
3fcaf2e5
EG		 3192 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3193 aeu_mask = REG_RD(bp, aeu_addr);
3194
a2fbb9ea 3195 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3196 aeu_mask, asserted);
72fd0718 3197 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3198 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3199
3fcaf2e5
EG		 3200 REG_WR(bp, aeu_addr, aeu_mask);
3201 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3202
3fcaf2e5 3203 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3204 bp->attn_state |= asserted;
3fcaf2e5 3205 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3206
3207 if (asserted & ATTN_HARD_WIRED_MASK) {
3208 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3209
a5e9a7cf
EG		 3210 bnx2x_acquire_phy_lock(bp);
3211
877e9aa4 3212 /* save nig interrupt mask */
87942b46 3213 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3214
361c391e
YR		 3215 /* If nig_mask is not set, no need to call the update
3216 * function.
3217 */
3218 if (nig_mask) {
3219 REG_WR(bp, nig_int_mask_addr, 0);
3220
3221 bnx2x_link_attn(bp);
3222 }
a2fbb9ea
ET		 3223
3224 /* handle unicore attn? */
3225 }
3226 if (asserted & ATTN_SW_TIMER_4_FUNC)
3227 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3228
3229 if (asserted & GPIO_2_FUNC)
3230 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3231
3232 if (asserted & GPIO_3_FUNC)
3233 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3234
3235 if (asserted & GPIO_4_FUNC)
3236 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3237
3238 if (port == 0) {
3239 if (asserted & ATTN_GENERAL_ATTN_1) {
3240 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3241 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3242 }
3243 if (asserted & ATTN_GENERAL_ATTN_2) {
3244 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3245 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3246 }
3247 if (asserted & ATTN_GENERAL_ATTN_3) {
3248 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3249 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3250 }
3251 } else {
3252 if (asserted & ATTN_GENERAL_ATTN_4) {
3253 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3254 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3255 }
3256 if (asserted & ATTN_GENERAL_ATTN_5) {
3257 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3258 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3259 }
3260 if (asserted & ATTN_GENERAL_ATTN_6) {
3261 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3262 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3263 }
3264 }
3265
3266 } /* if hardwired */
3267
f2e0899f
DK		 3268 if (bp->common.int_block == INT_BLOCK_HC)
3269 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3270 COMMAND_REG_ATTN_BITS_SET);
3271 else
3272 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3273
3274 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3275 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3276 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3277
3278 /* now set back the mask */
a5e9a7cf 3279 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3280 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3281 bnx2x_release_phy_lock(bp);
3282 }
a2fbb9ea
ET		 3283}
3284
fd4ef40d
EG		 3285static inline void bnx2x_fan_failure(struct bnx2x *bp)
3286{
3287 int port = BP_PORT(bp);
b7737c9b 3288 u32 ext_phy_config;
fd4ef40d 3289 /* mark the failure */
b7737c9b
YR		 3290 ext_phy_config =
3291 SHMEM_RD(bp,
3292 dev_info.port_hw_config[port].external_phy_config);
3293
3294 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3295 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3296 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3297 ext_phy_config);
fd4ef40d
EG		 3298
3299 /* log the failure */
cdaa7cb8
VZ		 3300 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3301 " the driver to shutdown the card to prevent permanent"
3302 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 3303}
ab6ad5a4 3304
877e9aa4 3305static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3306{
34f80b04 3307 int port = BP_PORT(bp);
877e9aa4 3308 int reg_offset;
d90d96ba 3309 u32 val;
877e9aa4 3310
34f80b04
EG		 3311 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3312 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3313
34f80b04 3314 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3315
3316 val = REG_RD(bp, reg_offset);
3317 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3318 REG_WR(bp, reg_offset, val);
3319
3320 BNX2X_ERR("SPIO5 hw attention\n");
3321
fd4ef40d 3322 /* Fan failure attention */
d90d96ba 3323 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3324 bnx2x_fan_failure(bp);
877e9aa4 3325 }
34f80b04 3326
3deb8167 3327 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3328 bnx2x_acquire_phy_lock(bp);
3329 bnx2x_handle_module_detect_int(&bp->link_params);
3330 bnx2x_release_phy_lock(bp);
3331 }
3332
34f80b04
EG		 3333 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3334
3335 val = REG_RD(bp, reg_offset);
3336 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3337 REG_WR(bp, reg_offset, val);
3338
3339 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3340 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3341 bnx2x_panic();
3342 }
877e9aa4
ET		 3343}
3344
3345static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3346{
3347 u32 val;
3348
0626b899 3349 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3350
3351 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3352 BNX2X_ERR("DB hw attention 0x%x\n", val);
3353 /* DORQ discard attention */
3354 if (val & 0x2)
3355 BNX2X_ERR("FATAL error from DORQ\n");
3356 }
34f80b04
EG		 3357
3358 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3359
3360 int port = BP_PORT(bp);
3361 int reg_offset;
3362
3363 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3364 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3365
3366 val = REG_RD(bp, reg_offset);
3367 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3368 REG_WR(bp, reg_offset, val);
3369
3370 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3371 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3372 bnx2x_panic();
3373 }
877e9aa4
ET		 3374}
3375
3376static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3377{
3378 u32 val;
3379
3380 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3381
3382 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3383 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3384 /* CFC error attention */
3385 if (val & 0x2)
3386 BNX2X_ERR("FATAL error from CFC\n");
3387 }
3388
3389 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3390 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3391 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3392 /* RQ_USDMDP_FIFO_OVERFLOW */
3393 if (val & 0x18000)
3394 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3395
3396 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3397 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3398 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3399 }
877e9aa4 3400 }
34f80b04
EG		 3401
3402 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3403
3404 int port = BP_PORT(bp);
3405 int reg_offset;
3406
3407 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3408 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3409
3410 val = REG_RD(bp, reg_offset);
3411 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3412 REG_WR(bp, reg_offset, val);
3413
3414 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3415 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3416 bnx2x_panic();
3417 }
877e9aa4
ET		 3418}
3419
3420static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3421{
34f80b04
EG		 3422 u32 val;
3423
877e9aa4
ET		 3424 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3425
34f80b04
EG		 3426 if (attn & BNX2X_PMF_LINK_ASSERT) {
3427 int func = BP_FUNC(bp);
3428
3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3430 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3431 func_mf_config[BP_ABS_FUNC(bp)].config);
3432 val = SHMEM_RD(bp,
3433 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3434 if (val & DRV_STATUS_DCC_EVENT_MASK)
3435 bnx2x_dcc_event(bp,
3436 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3437
3438 if (val & DRV_STATUS_SET_MF_BW)
3439 bnx2x_set_mf_bw(bp);
3440
2691d51d 3441 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3442 bnx2x_pmf_update(bp);
3443
e4901dde 3444 if (bp->port.pmf &&
785b9b1a
SR		 3445 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3446 bp->dcbx_enabled > 0)
e4901dde
VZ		 3447 /* start dcbx state machine */
3448 bnx2x_dcbx_set_params(bp,
3449 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3450 if (bp->link_vars.periodic_flags &
3451 PERIODIC_FLAGS_LINK_EVENT) {
3452 /* sync with link */
3453 bnx2x_acquire_phy_lock(bp);
3454 bp->link_vars.periodic_flags &=
3455 ~PERIODIC_FLAGS_LINK_EVENT;
3456 bnx2x_release_phy_lock(bp);
3457 if (IS_MF(bp))
3458 bnx2x_link_sync_notify(bp);
3459 bnx2x_link_report(bp);
3460 }
3461 /* Always call it here: bnx2x_link_report() will
3462 * prevent the link indication duplication.
3463 */
3464 bnx2x__link_status_update(bp);
34f80b04 3465 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3466
3467 BNX2X_ERR("MC assert!\n");
d6cae238 3468 bnx2x_mc_assert(bp);
877e9aa4
ET		 3469 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3470 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3472 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3473 bnx2x_panic();
3474
3475 } else if (attn & BNX2X_MCP_ASSERT) {
3476
3477 BNX2X_ERR("MCP assert!\n");
3478 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3479 bnx2x_fw_dump(bp);
877e9aa4
ET		 3480
3481 } else
3482 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3483 }
3484
3485 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3486 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3487 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3488 val = CHIP_IS_E1(bp) ? 0 :
3489 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3490 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3491 }
3492 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3493 val = CHIP_IS_E1(bp) ? 0 :
3494 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3495 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3496 }
877e9aa4 3497 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3498 }
3499}
3500
c9ee9206
VZ		 3501/*
3502 * Bits map:
3503 * 0-7 - Engine0 load counter.
3504 * 8-15 - Engine1 load counter.
3505 * 16 - Engine0 RESET_IN_PROGRESS bit.
3506 * 17 - Engine1 RESET_IN_PROGRESS bit.
3507 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3508 * on the engine
3509 * 19 - Engine1 ONE_IS_LOADED.
3510 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3511 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3512 * just the one belonging to its engine).
3513 *
3514 */
3515#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3516
3517#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3518#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3519#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3520#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3521#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3522#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3523#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3524
3525/*
3526 * Set the GLOBAL_RESET bit.
3527 *
3528 * Should be run under rtnl lock
3529 */
3530void bnx2x_set_reset_global(struct bnx2x *bp)
3531{
3532 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3533
3534 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3535 barrier();
3536 mmiowb();
3537}
3538
3539/*
3540 * Clear the GLOBAL_RESET bit.
3541 *
3542 * Should be run under rtnl lock
3543 */
3544static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3545{
3546 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3547
3548 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3549 barrier();
3550 mmiowb();
3551}
f85582f8 3552
72fd0718 3553/*
c9ee9206
VZ		 3554 * Checks the GLOBAL_RESET bit.
3555 *
72fd0718
VZ		 3556 * should be run under rtnl lock
3557 */
c9ee9206
VZ		 3558static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3559{
3560 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3561
3562 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3563 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3564}
3565
3566/*
3567 * Clear RESET_IN_PROGRESS bit for the current engine.
3568 *
3569 * Should be run under rtnl lock
3570 */
72fd0718
VZ		 3571static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3572{
c9ee9206
VZ		 3573 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3574 u32 bit = BP_PATH(bp) ?
3575 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3576
3577 /* Clear the bit */
3578 val &= ~bit;
3579 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3580 barrier();
3581 mmiowb();
3582}
3583
3584/*
c9ee9206
VZ		 3585 * Set RESET_IN_PROGRESS for the current engine.
3586 *
72fd0718
VZ		 3587 * should be run under rtnl lock
3588 */
c9ee9206 3589void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3590{
c9ee9206
VZ		 3591 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3592 u32 bit = BP_PATH(bp) ?
3593 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3594
3595 /* Set the bit */
3596 val |= bit;
3597 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3598 barrier();
3599 mmiowb();
3600}
3601
3602/*
c9ee9206 3603 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3604 * should be run under rtnl lock
3605 */
c9ee9206 3606bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3607{
c9ee9206
VZ		 3608 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3609 u32 bit = engine ?
3610 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3611
3612 /* return false if bit is set */
3613 return (val & bit) ? false : true;
72fd0718
VZ		 3614}
3615
3616/*
c9ee9206
VZ		 3617 * Increment the load counter for the current engine.
3618 *
72fd0718
VZ		 3619 * should be run under rtnl lock
3620 */
c9ee9206 3621void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718 3622{
c9ee9206
VZ		 3623 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3624 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3625 BNX2X_PATH0_LOAD_CNT_MASK;
3626 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3627 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3628
3629 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3630
c9ee9206
VZ		 3631 /* get the current counter value */
3632 val1 = (val & mask) >> shift;
3633
3634 /* increment... */
3635 val1++;
3636
3637 /* clear the old value */
3638 val &= ~mask;
3639
3640 /* set the new one */
3641 val |= ((val1 << shift) & mask);
3642
3643 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3644 barrier();
3645 mmiowb();
3646}
3647
c9ee9206
VZ		 3648/**
3649 * bnx2x_dec_load_cnt - decrement the load counter
3650 *
3651 * @bp: driver handle
3652 *
3653 * Should be run under rtnl lock.
3654 * Decrements the load counter for the current engine. Returns
3655 * the new counter value.
72fd0718 3656 */
9f6c9258 3657u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718 3658{
c9ee9206
VZ		 3659 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3660 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3661 BNX2X_PATH0_LOAD_CNT_MASK;
3662 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3663 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3664
3665 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3666
c9ee9206
VZ		 3667 /* get the current counter value */
3668 val1 = (val & mask) >> shift;
3669
3670 /* decrement... */
3671 val1--;
3672
3673 /* clear the old value */
3674 val &= ~mask;
3675
3676 /* set the new one */
3677 val |= ((val1 << shift) & mask);
3678
3679 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3680 barrier();
3681 mmiowb();
3682
3683 return val1;
3684}
3685
3686/*
c9ee9206
VZ		 3687 * Read the load counter for the current engine.
3688 *
72fd0718
VZ		 3689 * should be run under rtnl lock
3690 */
c9ee9206 3691static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
72fd0718 3692{
c9ee9206
VZ		 3693 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3694 BNX2X_PATH0_LOAD_CNT_MASK);
3695 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3696 BNX2X_PATH0_LOAD_CNT_SHIFT);
3697 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3698
3699 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3700
3701 val = (val & mask) >> shift;
3702
3703 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3704
3705 return val;
72fd0718
VZ		 3706}
3707
c9ee9206
VZ		 3708/*
3709 * Reset the load counter for the current engine.
3710 *
3711 * should be run under rtnl lock
3712 */
72fd0718
VZ		 3713static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3714{
c9ee9206
VZ		 3715 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3716 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3717 BNX2X_PATH0_LOAD_CNT_MASK);
3718
3719 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
72fd0718
VZ		 3720}
3721
3722static inline void _print_next_block(int idx, const char *blk)
3723{
3724 if (idx)
3725 pr_cont(", ");
3726 pr_cont("%s", blk);
3727}
3728
c9ee9206
VZ		 3729static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3730 bool print)
72fd0718
VZ		 3731{
3732 int i = 0;
3733 u32 cur_bit = 0;
3734 for (i = 0; sig; i++) {
3735 cur_bit = ((u32)0x1 << i);
3736 if (sig & cur_bit) {
3737 switch (cur_bit) {
3738 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3739 if (print)
3740 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3741 break;
3742 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3743 if (print)
3744 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3745 break;
3746 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3747 if (print)
3748 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3749 break;
3750 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3751 if (print)
3752 _print_next_block(par_num++,
3753 "SEARCHER");
3754 break;
3755 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3756 if (print)
3757 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3758 break;
3759 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3760 if (print)
3761 _print_next_block(par_num++, "TSEMI");
3762 break;
3763 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3764 if (print)
3765 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3766 break;
3767 }
3768
3769 /* Clear the bit */
3770 sig &= ~cur_bit;
3771 }
3772 }
3773
3774 return par_num;
3775}
3776
c9ee9206
VZ		 3777static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3778 bool *global, bool print)
72fd0718
VZ		 3779{
3780 int i = 0;
3781 u32 cur_bit = 0;
3782 for (i = 0; sig; i++) {
3783 cur_bit = ((u32)0x1 << i);
3784 if (sig & cur_bit) {
3785 switch (cur_bit) {
c9ee9206
VZ		 3786 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3787 if (print)
3788 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3789 break;
3790 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3791 if (print)
3792 _print_next_block(par_num++, "QM");
3793 break;
3794 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3795 if (print)
3796 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3797 break;
3798 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3799 if (print)
3800 _print_next_block(par_num++, "XSDM");
3801 break;
3802 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3803 if (print)
3804 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 3805 break;
3806 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 3807 if (print)
3808 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 3809 break;
3810 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 3811 if (print)
3812 _print_next_block(par_num++,
3813 "DOORBELLQ");
3814 break;
3815 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3816 if (print)
3817 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 3818 break;
3819 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 3820 if (print)
3821 _print_next_block(par_num++,
3822 "VAUX PCI CORE");
3823 *global = true;
72fd0718
VZ		 3824 break;
3825 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 3826 if (print)
3827 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 3828 break;
3829 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 3830 if (print)
3831 _print_next_block(par_num++, "USDM");
72fd0718 3832 break;
8736c826
VZ		 3833 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3834 if (print)
3835 _print_next_block(par_num++, "UCM");
3836 break;
72fd0718 3837 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 3838 if (print)
3839 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 3840 break;
3841 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 3842 if (print)
3843 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 3844 break;
3845 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 3846 if (print)
3847 _print_next_block(par_num++, "CSDM");
72fd0718 3848 break;
8736c826
VZ		 3849 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3850 if (print)
3851 _print_next_block(par_num++, "CCM");
3852 break;
72fd0718
VZ		 3853 }
3854
3855 /* Clear the bit */
3856 sig &= ~cur_bit;
3857 }
3858 }
3859
3860 return par_num;
3861}
3862
c9ee9206
VZ		 3863static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3864 bool print)
72fd0718
VZ		 3865{
3866 int i = 0;
3867 u32 cur_bit = 0;
3868 for (i = 0; sig; i++) {
3869 cur_bit = ((u32)0x1 << i);
3870 if (sig & cur_bit) {
3871 switch (cur_bit) {
3872 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 3873 if (print)
3874 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 3875 break;
3876 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 3877 if (print)
3878 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 3879 break;
3880 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 3881 if (print)
3882 _print_next_block(par_num++,
72fd0718
VZ		 3883 "PXPPCICLOCKCLIENT");
3884 break;
3885 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 3886 if (print)
3887 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 3888 break;
3889 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 3890 if (print)
3891 _print_next_block(par_num++, "CDU");
3892 break;
3893 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3894 if (print)
3895 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 3896 break;
3897 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 3898 if (print)
3899 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 3900 break;
3901 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 3902 if (print)
3903 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 3904 break;
3905 }
3906
3907 /* Clear the bit */
3908 sig &= ~cur_bit;
3909 }
3910 }
3911
3912 return par_num;
3913}
3914
c9ee9206
VZ		 3915static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3916 bool *global, bool print)
72fd0718
VZ		 3917{
3918 int i = 0;
3919 u32 cur_bit = 0;
3920 for (i = 0; sig; i++) {
3921 cur_bit = ((u32)0x1 << i);
3922 if (sig & cur_bit) {
3923 switch (cur_bit) {
3924 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 3925 if (print)
3926 _print_next_block(par_num++, "MCP ROM");
3927 *global = true;
72fd0718
VZ		 3928 break;
3929 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 3930 if (print)
3931 _print_next_block(par_num++,
3932 "MCP UMP RX");
3933 *global = true;
72fd0718
VZ		 3934 break;
3935 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 3936 if (print)
3937 _print_next_block(par_num++,
3938 "MCP UMP TX");
3939 *global = true;
72fd0718
VZ		 3940 break;
3941 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 3942 if (print)
3943 _print_next_block(par_num++,
3944 "MCP SCPAD");
3945 *global = true;
72fd0718
VZ		 3946 break;
3947 }
3948
3949 /* Clear the bit */
3950 sig &= ~cur_bit;
3951 }
3952 }
3953
3954 return par_num;
3955}
3956
8736c826
VZ		 3957static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3958 bool print)
3959{
3960 int i = 0;
3961 u32 cur_bit = 0;
3962 for (i = 0; sig; i++) {
3963 cur_bit = ((u32)0x1 << i);
3964 if (sig & cur_bit) {
3965 switch (cur_bit) {
3966 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3967 if (print)
3968 _print_next_block(par_num++, "PGLUE_B");
3969 break;
3970 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3971 if (print)
3972 _print_next_block(par_num++, "ATC");
3973 break;
3974 }
3975
3976 /* Clear the bit */
3977 sig &= ~cur_bit;
3978 }
3979 }
3980
3981 return par_num;
3982}
3983
c9ee9206 3984static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
8736c826 3985 u32 *sig)
72fd0718 3986{
8736c826
VZ		 3987 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3988 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3989 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3990 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3991 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718
VZ		 3992 int par_num = 0;
3993 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
8736c826
VZ		 3994 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
3995 "[4]:0x%08x\n",
3996 sig[0] & HW_PRTY_ASSERT_SET_0,
3997 sig[1] & HW_PRTY_ASSERT_SET_1,
3998 sig[2] & HW_PRTY_ASSERT_SET_2,
3999 sig[3] & HW_PRTY_ASSERT_SET_3,
4000 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4001 if (print)
4002 netdev_err(bp->dev,
4003 "Parity errors detected in blocks: ");
4004 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4005 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4006 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4007 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4008 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4009 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4010 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4011 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4012 par_num = bnx2x_check_blocks_with_parity4(
4013 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4014
c9ee9206
VZ		 4015 if (print)
4016 pr_cont("\n");
8736c826 4017
72fd0718
VZ		 4018 return true;
4019 } else
4020 return false;
4021}
4022
c9ee9206
VZ		 4023/**
4024 * bnx2x_chk_parity_attn - checks for parity attentions.
4025 *
4026 * @bp: driver handle
4027 * @global: true if there was a global attention
4028 * @print: show parity attention in syslog
4029 */
4030bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4031{
8736c826 4032 struct attn_route attn = { {0} };
72fd0718
VZ		 4033 int port = BP_PORT(bp);
4034
4035 attn.sig[0] = REG_RD(bp,
4036 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4037 port*4);
4038 attn.sig[1] = REG_RD(bp,
4039 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4040 port*4);
4041 attn.sig[2] = REG_RD(bp,
4042 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4043 port*4);
4044 attn.sig[3] = REG_RD(bp,
4045 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4046 port*4);
4047
8736c826
VZ		 4048 if (!CHIP_IS_E1x(bp))
4049 attn.sig[4] = REG_RD(bp,
4050 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4051 port*4);
4052
4053 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4054}
4055
f2e0899f
DK		 4056
4057static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4058{
4059 u32 val;
4060 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4061
4062 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4063 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4064 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4065 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4066 "ADDRESS_ERROR\n");
4067 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4068 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4069 "INCORRECT_RCV_BEHAVIOR\n");
4070 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4071 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4072 "WAS_ERROR_ATTN\n");
4073 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4074 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4075 "VF_LENGTH_VIOLATION_ATTN\n");
4076 if (val &
4077 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4078 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4079 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4080 if (val &
4081 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4082 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4083 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4086 "TCPL_ERROR_ATTN\n");
4087 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4088 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4089 "TCPL_IN_TWO_RCBS_ATTN\n");
4090 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4091 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4092 "CSSNOOP_FIFO_OVERFLOW\n");
4093 }
4094 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4095 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4096 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4097 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4098 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4099 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4100 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4101 "_ATC_TCPL_TO_NOT_PEND\n");
4102 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4103 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4104 "ATC_GPA_MULTIPLE_HITS\n");
4105 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4106 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4107 "ATC_RCPL_TO_EMPTY_CNT\n");
4108 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4109 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4110 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4111 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4112 "ATC_IREQ_LESS_THAN_STU\n");
4113 }
4114
4115 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4116 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4117 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4118 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4119 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4120 }
4121
4122}
4123
72fd0718
VZ		 4124static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4125{
4126 struct attn_route attn, *group_mask;
34f80b04 4127 int port = BP_PORT(bp);
877e9aa4 4128 int index;
a2fbb9ea
ET		 4129 u32 reg_addr;
4130 u32 val;
3fcaf2e5 4131 u32 aeu_mask;
c9ee9206 4132 bool global = false;
a2fbb9ea
ET		 4133
4134 /* need to take HW lock because MCP or other port might also
4135 try to handle this event */
4a37fb66 4136 bnx2x_acquire_alr(bp);
a2fbb9ea 4137
c9ee9206
VZ		 4138 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4139#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4140 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4141 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4142 /* Disable HW interrupts */
4143 bnx2x_int_disable(bp);
72fd0718
VZ		 4144 /* In case of parity errors don't handle attentions so that
4145 * other function would "see" parity errors.
4146 */
c9ee9206
VZ		 4147#else
4148 bnx2x_panic();
4149#endif
4150 bnx2x_release_alr(bp);
72fd0718
VZ		 4151 return;
4152 }
4153
a2fbb9ea
ET		 4154 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4155 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4156 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4157 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4158 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4159 attn.sig[4] =
4160 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4161 else
4162 attn.sig[4] = 0;
4163
4164 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4165 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4166
4167 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4168 if (deasserted & (1 << index)) {
72fd0718 4169 group_mask = &bp->attn_group[index];
a2fbb9ea 4170
f2e0899f
DK		 4171 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4172 "%08x %08x %08x\n",
4173 index,
4174 group_mask->sig[0], group_mask->sig[1],
4175 group_mask->sig[2], group_mask->sig[3],
4176 group_mask->sig[4]);
a2fbb9ea 4177
f2e0899f
DK		 4178 bnx2x_attn_int_deasserted4(bp,
4179 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4180 bnx2x_attn_int_deasserted3(bp,
72fd0718 4181 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4182 bnx2x_attn_int_deasserted1(bp,
72fd0718 4183 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4184 bnx2x_attn_int_deasserted2(bp,
72fd0718 4185 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4186 bnx2x_attn_int_deasserted0(bp,
72fd0718 4187 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4188 }
4189 }
4190
4a37fb66 4191 bnx2x_release_alr(bp);
a2fbb9ea 4192
f2e0899f
DK		 4193 if (bp->common.int_block == INT_BLOCK_HC)
4194 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4195 COMMAND_REG_ATTN_BITS_CLR);
4196 else
4197 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4198
4199 val = ~deasserted;
f2e0899f
DK		 4200 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4201 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4202 REG_WR(bp, reg_addr, val);
a2fbb9ea 4203
a2fbb9ea 4204 if (~bp->attn_state & deasserted)
3fcaf2e5 4205 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4206
4207 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4208 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4209
3fcaf2e5
EG		 4210 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4211 aeu_mask = REG_RD(bp, reg_addr);
4212
4213 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4214 aeu_mask, deasserted);
72fd0718 4215 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4216 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4217
3fcaf2e5
EG		 4218 REG_WR(bp, reg_addr, aeu_mask);
4219 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4220
4221 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4222 bp->attn_state &= ~deasserted;
4223 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4224}
4225
4226static void bnx2x_attn_int(struct bnx2x *bp)
4227{
4228 /* read local copy of bits */
68d59484
EG		 4229 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4230 attn_bits);
4231 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4232 attn_bits_ack);
a2fbb9ea
ET		 4233 u32 attn_state = bp->attn_state;
4234
4235 /* look for changed bits */
4236 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4237 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4238
4239 DP(NETIF_MSG_HW,
4240 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4241 attn_bits, attn_ack, asserted, deasserted);
4242
4243 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4244 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4245
4246 /* handle bits that were raised */
4247 if (asserted)
4248 bnx2x_attn_int_asserted(bp, asserted);
4249
4250 if (deasserted)
4251 bnx2x_attn_int_deasserted(bp, deasserted);
4252}
4253
619c5cb6
VZ		 4254void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4255 u16 index, u8 op, u8 update)
4256{
4257 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4258
4259 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4260 igu_addr);
4261}
4262
523224a3
DK		 4263static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4264{
4265 /* No memory barriers */
4266 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4267 mmiowb(); /* keep prod updates ordered */
4268}
4269
4270#ifdef BCM_CNIC
4271static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4272 union event_ring_elem *elem)
4273{
619c5cb6
VZ		 4274 u8 err = elem->message.error;
4275
523224a3 4276 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4277 (cid < bp->cnic_eth_dev.starting_cid &&
4278 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4279 return 1;
4280
4281 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4282
619c5cb6
VZ		 4283 if (unlikely(err)) {
4284
523224a3
DK		 4285 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4286 cid);
4287 bnx2x_panic_dump(bp);
4288 }
619c5cb6 4289 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4290 return 0;
4291}
4292#endif
4293
619c5cb6
VZ		 4294static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4295{
4296 struct bnx2x_mcast_ramrod_params rparam;
4297 int rc;
4298
4299 memset(&rparam, 0, sizeof(rparam));
4300
4301 rparam.mcast_obj = &bp->mcast_obj;
4302
4303 netif_addr_lock_bh(bp->dev);
4304
4305 /* Clear pending state for the last command */
4306 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4307
4308 /* If there are pending mcast commands - send them */
4309 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4310 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4311 if (rc < 0)
4312 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4313 rc);
4314 }
4315
4316 netif_addr_unlock_bh(bp->dev);
4317}
4318
4319static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4320 union event_ring_elem *elem)
4321{
4322 unsigned long ramrod_flags = 0;
4323 int rc = 0;
4324 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4325 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4326
4327 /* Always push next commands out, don't wait here */
4328 __set_bit(RAMROD_CONT, &ramrod_flags);
4329
4330 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4331 case BNX2X_FILTER_MAC_PENDING:
4332#ifdef BCM_CNIC
4333 if (cid == BNX2X_ISCSI_ETH_CID)
4334 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4335 else
4336#endif
4337 vlan_mac_obj = &bp->fp[cid].mac_obj;
4338
4339 break;
4340 vlan_mac_obj = &bp->fp[cid].mac_obj;
4341
4342 case BNX2X_FILTER_MCAST_PENDING:
4343 /* This is only relevant for 57710 where multicast MACs are
4344 * configured as unicast MACs using the same ramrod.
4345 */
4346 bnx2x_handle_mcast_eqe(bp);
4347 return;
4348 default:
4349 BNX2X_ERR("Unsupported classification command: %d\n",
4350 elem->message.data.eth_event.echo);
4351 return;
4352 }
4353
4354 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4355
4356 if (rc < 0)
4357 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4358 else if (rc > 0)
4359 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4360
4361}
4362
4363#ifdef BCM_CNIC
4364static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4365#endif
4366
4367static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4368{
4369 netif_addr_lock_bh(bp->dev);
4370
4371 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4372
4373 /* Send rx_mode command again if was requested */
4374 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4375 bnx2x_set_storm_rx_mode(bp);
4376#ifdef BCM_CNIC
4377 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4378 &bp->sp_state))
4379 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4380 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4381 &bp->sp_state))
4382 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4383#endif
4384
4385 netif_addr_unlock_bh(bp->dev);
4386}
4387
4388static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4389 struct bnx2x *bp, u32 cid)
4390{
6383c0b3 4391 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
619c5cb6
VZ		 4392#ifdef BCM_CNIC
4393 if (cid == BNX2X_FCOE_ETH_CID)
4394 return &bnx2x_fcoe(bp, q_obj);
4395 else
4396#endif
6383c0b3 4397 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4398}
4399
523224a3
DK		 4400static void bnx2x_eq_int(struct bnx2x *bp)
4401{
4402 u16 hw_cons, sw_cons, sw_prod;
4403 union event_ring_elem *elem;
4404 u32 cid;
4405 u8 opcode;
4406 int spqe_cnt = 0;
619c5cb6
VZ		 4407 struct bnx2x_queue_sp_obj *q_obj;
4408 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4409 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4410
4411 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4412
4413 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4414 * when we get the the next-page we nned to adjust so the loop
4415 * condition below will be met. The next element is the size of a
4416 * regular element and hence incrementing by 1
4417 */
4418 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4419 hw_cons++;
4420
25985edc 4421 /* This function may never run in parallel with itself for a
523224a3
DK		 4422 * specific bp, thus there is no need in "paired" read memory
4423 * barrier here.
4424 */
4425 sw_cons = bp->eq_cons;
4426 sw_prod = bp->eq_prod;
4427
d6cae238 4428 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4429 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4430
4431 for (; sw_cons != hw_cons;
4432 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4433
4434
4435 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4436
4437 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4438 opcode = elem->message.opcode;
4439
4440
4441 /* handle eq element */
4442 switch (opcode) {
4443 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4444 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4445 bp->stats_comp++);
523224a3 4446 /* nothing to do with stats comp */
d6cae238 4447 goto next_spqe;
523224a3
DK		 4448
4449 case EVENT_RING_OPCODE_CFC_DEL:
4450 /* handle according to cid range */
4451 /*
4452 * we may want to verify here that the bp state is
4453 * HALTING
4454 */
d6cae238 4455 DP(BNX2X_MSG_SP,
523224a3
DK		 4456 "got delete ramrod for MULTI[%d]\n", cid);
4457#ifdef BCM_CNIC
4458 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4459 goto next_spqe;
4460#endif
619c5cb6
VZ		 4461 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4462
4463 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4464 break;
4465
4466
523224a3
DK		 4467
4468 goto next_spqe;
e4901dde
VZ		 4469
4470 case EVENT_RING_OPCODE_STOP_TRAFFIC:
d6cae238 4471 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
6debea87
DK		 4472 if (f_obj->complete_cmd(bp, f_obj,
4473 BNX2X_F_CMD_TX_STOP))
4474 break;
e4901dde
VZ		 4475 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4476 goto next_spqe;
619c5cb6 4477
e4901dde 4478 case EVENT_RING_OPCODE_START_TRAFFIC:
d6cae238 4479 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
6debea87
DK		 4480 if (f_obj->complete_cmd(bp, f_obj,
4481 BNX2X_F_CMD_TX_START))
4482 break;
e4901dde
VZ		 4483 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4484 goto next_spqe;
619c5cb6 4485 case EVENT_RING_OPCODE_FUNCTION_START:
d6cae238 4486 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
619c5cb6
VZ		 4487 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4488 break;
4489
4490 goto next_spqe;
4491
4492 case EVENT_RING_OPCODE_FUNCTION_STOP:
d6cae238 4493 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 4494 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4495 break;
4496
4497 goto next_spqe;
523224a3
DK		 4498 }
4499
4500 switch (opcode | bp->state) {
619c5cb6
VZ		 4501 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4502 BNX2X_STATE_OPEN):
4503 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4504 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4505 cid = elem->message.data.eth_event.echo &
4506 BNX2X_SWCID_MASK;
d6cae238 4507 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 4508 cid);
4509 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4510 break;
4511
619c5cb6
VZ		 4512 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4513 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4514 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4515 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4516 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4517 BNX2X_STATE_OPEN):
4518 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4519 BNX2X_STATE_DIAG):
4520 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4521 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4522 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 4523 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4524 break;
4525
619c5cb6
VZ		 4526 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4527 BNX2X_STATE_OPEN):
4528 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4529 BNX2X_STATE_DIAG):
4530 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4531 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4532 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 4533 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4534 break;
4535
619c5cb6
VZ		 4536 case (EVENT_RING_OPCODE_FILTERS_RULES |
4537 BNX2X_STATE_OPEN):
4538 case (EVENT_RING_OPCODE_FILTERS_RULES |
4539 BNX2X_STATE_DIAG):
4540 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4541 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4542 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 4543 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4544 break;
4545 default:
4546 /* unknown event log error and continue */
619c5cb6
VZ		 4547 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4548 elem->message.opcode, bp->state);
523224a3
DK		 4549 }
4550next_spqe:
4551 spqe_cnt++;
4552 } /* for */
4553
8fe23fbd 4554 smp_mb__before_atomic_inc();
6e30dd4e 4555 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4556
4557 bp->eq_cons = sw_cons;
4558 bp->eq_prod = sw_prod;
4559 /* Make sure that above mem writes were issued towards the memory */
4560 smp_wmb();
4561
4562 /* update producer */
4563 bnx2x_update_eq_prod(bp, bp->eq_prod);
4564}
4565
a2fbb9ea
ET		 4566static void bnx2x_sp_task(struct work_struct *work)
4567{
1cf167f2 4568 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4569 u16 status;
4570
a2fbb9ea 4571 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4572/* if (status == 0) */
4573/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4574
cdaa7cb8 4575 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4576
877e9aa4 4577 /* HW attentions */
523224a3 4578 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4579 bnx2x_attn_int(bp);
523224a3 4580 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4581 }
4582
523224a3
DK		 4583 /* SP events: STAT_QUERY and others */
4584 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4585#ifdef BCM_CNIC
4586 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4587
ec6ba945 4588 if ((!NO_FCOE(bp)) &&
019dbb4c
VZ		 4589 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4590 /*
4591 * Prevent local bottom-halves from running as
4592 * we are going to change the local NAPI list.
4593 */
4594 local_bh_disable();
ec6ba945 4595 napi_schedule(&bnx2x_fcoe(bp, napi));
019dbb4c
VZ		 4596 local_bh_enable();
4597 }
ec6ba945 4598#endif
523224a3
DK		 4599 /* Handle EQ completions */
4600 bnx2x_eq_int(bp);
4601
4602 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4603 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4604
4605 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4606 }
4607
4608 if (unlikely(status))
4609 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4610 status);
a2fbb9ea 4611
523224a3
DK		 4612 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4613 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4614}
4615
9f6c9258 4616irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4617{
4618 struct net_device *dev = dev_instance;
4619 struct bnx2x *bp = netdev_priv(dev);
4620
523224a3
DK		 4621 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4622 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4623
4624#ifdef BNX2X_STOP_ON_ERROR
4625 if (unlikely(bp->panic))
4626 return IRQ_HANDLED;
4627#endif
4628
993ac7b5
MC		 4629#ifdef BCM_CNIC
4630 {
4631 struct cnic_ops *c_ops;
4632
4633 rcu_read_lock();
4634 c_ops = rcu_dereference(bp->cnic_ops);
4635 if (c_ops)
4636 c_ops->cnic_handler(bp->cnic_data, NULL);
4637 rcu_read_unlock();
4638 }
4639#endif
1cf167f2 4640 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4641
4642 return IRQ_HANDLED;
4643}
4644
4645/* end of slow path */
4646
619c5cb6
VZ		 4647
4648void bnx2x_drv_pulse(struct bnx2x *bp)
4649{
4650 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4651 bp->fw_drv_pulse_wr_seq);
4652}
4653
4654
a2fbb9ea
ET		 4655static void bnx2x_timer(unsigned long data)
4656{
6383c0b3 4657 u8 cos;
a2fbb9ea
ET		 4658 struct bnx2x *bp = (struct bnx2x *) data;
4659
4660 if (!netif_running(bp->dev))
4661 return;
4662
a2fbb9ea
ET		 4663 if (poll) {
4664 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4665
6383c0b3
AE		 4666 for_each_cos_in_tx_queue(fp, cos)
4667 bnx2x_tx_int(bp, &fp->txdata[cos]);
b8ee8328 4668 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4669 }
4670
34f80b04 4671 if (!BP_NOMCP(bp)) {
f2e0899f 4672 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4673 u32 drv_pulse;
4674 u32 mcp_pulse;
4675
4676 ++bp->fw_drv_pulse_wr_seq;
4677 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4678 /* TBD - add SYSTEM_TIME */
4679 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4680 bnx2x_drv_pulse(bp);
a2fbb9ea 4681
f2e0899f 4682 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4683 MCP_PULSE_SEQ_MASK);
4684 /* The delta between driver pulse and mcp response
4685 * should be 1 (before mcp response) or 0 (after mcp response)
4686 */
4687 if ((drv_pulse != mcp_pulse) &&
4688 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4689 /* someone lost a heartbeat... */
4690 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4691 drv_pulse, mcp_pulse);
4692 }
4693 }
4694
f34d28ea 4695 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4696 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4697
a2fbb9ea
ET		 4698 mod_timer(&bp->timer, jiffies + bp->current_interval);
4699}
4700
4701/* end of Statistics */
4702
4703/* nic init */
4704
4705/*
4706 * nic init service functions
4707 */
4708
523224a3 4709static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4710{
523224a3
DK		 4711 u32 i;
4712 if (!(len%4) && !(addr%4))
4713 for (i = 0; i < len; i += 4)
4714 REG_WR(bp, addr + i, fill);
4715 else
4716 for (i = 0; i < len; i++)
4717 REG_WR8(bp, addr + i, fill);
34f80b04 4718
34f80b04
EG		 4719}
4720
523224a3
DK		 4721/* helper: writes FP SP data to FW - data_size in dwords */
4722static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4723 int fw_sb_id,
4724 u32 *sb_data_p,
4725 u32 data_size)
34f80b04 4726{
a2fbb9ea 4727 int index;
523224a3
DK		 4728 for (index = 0; index < data_size; index++)
4729 REG_WR(bp, BAR_CSTRORM_INTMEM +
4730 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4731 sizeof(u32)*index,
4732 *(sb_data_p + index));
4733}
a2fbb9ea 4734
523224a3
DK		 4735static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4736{
4737 u32 *sb_data_p;
4738 u32 data_size = 0;
f2e0899f 4739 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4740 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4741
523224a3 4742 /* disable the function first */
619c5cb6 4743 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4744 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4745 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4746 sb_data_e2.common.p_func.vf_valid = false;
4747 sb_data_p = (u32 *)&sb_data_e2;
4748 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4749 } else {
4750 memset(&sb_data_e1x, 0,
4751 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4752 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4753 sb_data_e1x.common.p_func.vf_valid = false;
4754 sb_data_p = (u32 *)&sb_data_e1x;
4755 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4756 }
523224a3 4757 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4758
523224a3
DK		 4759 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4760 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4761 CSTORM_STATUS_BLOCK_SIZE);
4762 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4763 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4764 CSTORM_SYNC_BLOCK_SIZE);
4765}
34f80b04 4766
523224a3
DK		 4767/* helper: writes SP SB data to FW */
4768static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4769 struct hc_sp_status_block_data *sp_sb_data)
4770{
4771 int func = BP_FUNC(bp);
4772 int i;
4773 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4774 REG_WR(bp, BAR_CSTRORM_INTMEM +
4775 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4776 i*sizeof(u32),
4777 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4778}
4779
523224a3 4780static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4781{
4782 int func = BP_FUNC(bp);
523224a3
DK		 4783 struct hc_sp_status_block_data sp_sb_data;
4784 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4785
619c5cb6 4786 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4787 sp_sb_data.p_func.vf_valid = false;
4788
4789 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4790
4791 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4792 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4793 CSTORM_SP_STATUS_BLOCK_SIZE);
4794 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4795 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4796 CSTORM_SP_SYNC_BLOCK_SIZE);
4797
4798}
4799
4800
4801static inline
4802void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4803 int igu_sb_id, int igu_seg_id)
4804{
4805 hc_sm->igu_sb_id = igu_sb_id;
4806 hc_sm->igu_seg_id = igu_seg_id;
4807 hc_sm->timer_value = 0xFF;
4808 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4809}
4810
8d96286a 4811static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4812 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4813{
523224a3
DK		 4814 int igu_seg_id;
4815
f2e0899f 4816 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4817 struct hc_status_block_data_e1x sb_data_e1x;
4818 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4819 int data_size;
4820 u32 *sb_data_p;
4821
f2e0899f
DK		 4822 if (CHIP_INT_MODE_IS_BC(bp))
4823 igu_seg_id = HC_SEG_ACCESS_NORM;
4824 else
4825 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4826
4827 bnx2x_zero_fp_sb(bp, fw_sb_id);
4828
619c5cb6 4829 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4830 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4831 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 4832 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4833 sb_data_e2.common.p_func.vf_id = vfid;
4834 sb_data_e2.common.p_func.vf_valid = vf_valid;
4835 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4836 sb_data_e2.common.same_igu_sb_1b = true;
4837 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4838 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4839 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4840 sb_data_p = (u32 *)&sb_data_e2;
4841 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4842 } else {
4843 memset(&sb_data_e1x, 0,
4844 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4845 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 4846 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4847 sb_data_e1x.common.p_func.vf_id = 0xff;
4848 sb_data_e1x.common.p_func.vf_valid = false;
4849 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4850 sb_data_e1x.common.same_igu_sb_1b = true;
4851 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4852 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4853 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4854 sb_data_p = (u32 *)&sb_data_e1x;
4855 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4856 }
523224a3
DK		 4857
4858 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4859 igu_sb_id, igu_seg_id);
4860 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4861 igu_sb_id, igu_seg_id);
4862
4863 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4864
4865 /* write indecies to HW */
4866 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4867}
4868
619c5cb6 4869static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 4870 u16 tx_usec, u16 rx_usec)
4871{
6383c0b3 4872 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 4873 false, rx_usec);
6383c0b3
AE		 4874 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4875 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4876 tx_usec);
4877 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4878 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4879 tx_usec);
4880 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4881 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4882 tx_usec);
523224a3 4883}
f2e0899f 4884
523224a3
DK		 4885static void bnx2x_init_def_sb(struct bnx2x *bp)
4886{
4887 struct host_sp_status_block *def_sb = bp->def_status_blk;
4888 dma_addr_t mapping = bp->def_status_blk_mapping;
4889 int igu_sp_sb_index;
4890 int igu_seg_id;
34f80b04
EG		 4891 int port = BP_PORT(bp);
4892 int func = BP_FUNC(bp);
523224a3 4893 int reg_offset;
a2fbb9ea 4894 u64 section;
523224a3
DK		 4895 int index;
4896 struct hc_sp_status_block_data sp_sb_data;
4897 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4898
f2e0899f
DK		 4899 if (CHIP_INT_MODE_IS_BC(bp)) {
4900 igu_sp_sb_index = DEF_SB_IGU_ID;
4901 igu_seg_id = HC_SEG_ACCESS_DEF;
4902 } else {
4903 igu_sp_sb_index = bp->igu_dsb_id;
4904 igu_seg_id = IGU_SEG_ACCESS_DEF;
4905 }
a2fbb9ea
ET		 4906
4907 /* ATTN */
523224a3 4908 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4909 atten_status_block);
523224a3 4910 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4911
49d66772
ET		 4912 bp->attn_state = 0;
4913
a2fbb9ea
ET		 4914 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4915 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4916 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4917 int sindex;
4918 /* take care of sig[0]..sig[4] */
4919 for (sindex = 0; sindex < 4; sindex++)
4920 bp->attn_group[index].sig[sindex] =
4921 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 4922
619c5cb6 4923 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4924 /*
4925 * enable5 is separate from the rest of the registers,
4926 * and therefore the address skip is 4
4927 * and not 16 between the different groups
4928 */
4929 bp->attn_group[index].sig[4] = REG_RD(bp,
4930 reg_offset + 0x10 + 0x4*index);
4931 else
4932 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4933 }
4934
f2e0899f
DK		 4935 if (bp->common.int_block == INT_BLOCK_HC) {
4936 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4937 HC_REG_ATTN_MSG0_ADDR_L);
4938
4939 REG_WR(bp, reg_offset, U64_LO(section));
4940 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 4941 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4942 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4943 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4944 }
a2fbb9ea 4945
523224a3
DK		 4946 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4947 sp_sb);
a2fbb9ea 4948
523224a3 4949 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4950
619c5cb6 4951 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 4952 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4953 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4954 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4955 sp_sb_data.igu_seg_id = igu_seg_id;
4956 sp_sb_data.p_func.pf_id = func;
f2e0899f 4957 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4958 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4959
523224a3 4960 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4961
523224a3 4962 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4963}
4964
9f6c9258 4965void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4966{
a2fbb9ea
ET		 4967 int i;
4968
ec6ba945 4969 for_each_eth_queue(bp, i)
523224a3 4970 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4971 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4972}
4973
a2fbb9ea
ET		 4974static void bnx2x_init_sp_ring(struct bnx2x *bp)
4975{
a2fbb9ea 4976 spin_lock_init(&bp->spq_lock);
6e30dd4e 4977 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4978
a2fbb9ea 4979 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4980 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4981 bp->spq_prod_bd = bp->spq;
4982 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4983}
4984
523224a3 4985static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4986{
4987 int i;
523224a3
DK		 4988 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4989 union event_ring_elem *elem =
4990 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4991
523224a3
DK		 4992 elem->next_page.addr.hi =
4993 cpu_to_le32(U64_HI(bp->eq_mapping +
4994 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4995 elem->next_page.addr.lo =
4996 cpu_to_le32(U64_LO(bp->eq_mapping +
4997 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4998 }
523224a3
DK		 4999 bp->eq_cons = 0;
5000 bp->eq_prod = NUM_EQ_DESC;
5001 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5002 /* we want a warning message before it gets rought... */
5003 atomic_set(&bp->eq_spq_left,
5004 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5005}
5006
619c5cb6
VZ		 5007
5008/* called with netif_addr_lock_bh() */
5009void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5010 unsigned long rx_mode_flags,
5011 unsigned long rx_accept_flags,
5012 unsigned long tx_accept_flags,
5013 unsigned long ramrod_flags)
ab532cf3 5014{
619c5cb6
VZ		 5015 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5016 int rc;
5017
5018 memset(&ramrod_param, 0, sizeof(ramrod_param));
5019
5020 /* Prepare ramrod parameters */
5021 ramrod_param.cid = 0;
5022 ramrod_param.cl_id = cl_id;
5023 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5024 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5025
619c5cb6
VZ		 5026 ramrod_param.pstate = &bp->sp_state;
5027 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5028
619c5cb6
VZ		 5029 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5030 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5031
5032 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5033
5034 ramrod_param.ramrod_flags = ramrod_flags;
5035 ramrod_param.rx_mode_flags = rx_mode_flags;
5036
5037 ramrod_param.rx_accept_flags = rx_accept_flags;
5038 ramrod_param.tx_accept_flags = tx_accept_flags;
5039
5040 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5041 if (rc < 0) {
5042 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5043 return;
5044 }
a2fbb9ea
ET		 5045}
5046
619c5cb6
VZ		 5047/* called with netif_addr_lock_bh() */
5048void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5049{
619c5cb6
VZ		 5050 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5051 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5052
619c5cb6
VZ		 5053#ifdef BCM_CNIC
5054 if (!NO_FCOE(bp))
5055
5056 /* Configure rx_mode of FCoE Queue */
5057 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5058#endif
5059
5060 switch (bp->rx_mode) {
5061 case BNX2X_RX_MODE_NONE:
5062 /*
5063 * 'drop all' supersedes any accept flags that may have been
5064 * passed to the function.
5065 */
5066 break;
5067 case BNX2X_RX_MODE_NORMAL:
5068 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5069 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5070 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5071
5072 /* internal switching mode */
5073 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5074 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5075 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5076
5077 break;
5078 case BNX2X_RX_MODE_ALLMULTI:
5079 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5080 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5081 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5082
5083 /* internal switching mode */
5084 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5085 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5086 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5087
5088 break;
5089 case BNX2X_RX_MODE_PROMISC:
5090 /* According to deffinition of SI mode, iface in promisc mode
5091 * should receive matched and unmatched (in resolution of port)
5092 * unicast packets.
5093 */
5094 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5095 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5096 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5097 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5098
5099 /* internal switching mode */
5100 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5101 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5102
5103 if (IS_MF_SI(bp))
5104 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5105 else
5106 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5107
5108 break;
5109 default:
5110 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5111 return;
5112 }
de832a55 5113
619c5cb6
VZ		 5114 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5115 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5116 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5117 }
5118
619c5cb6
VZ		 5119 __set_bit(RAMROD_RX, &ramrod_flags);
5120 __set_bit(RAMROD_TX, &ramrod_flags);
5121
5122 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5123 tx_accept_flags, ramrod_flags);
5124}
5125
5126static void bnx2x_init_internal_common(struct bnx2x *bp)
5127{
5128 int i;
5129
0793f83f
DK		 5130 if (IS_MF_SI(bp))
5131 /*
5132 * In switch independent mode, the TSTORM needs to accept
5133 * packets that failed classification, since approximate match
5134 * mac addresses aren't written to NIG LLH
5135 */
5136 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5137 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5138 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5139 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5140 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5141
523224a3
DK		 5142 /* Zero this manually as its initialization is
5143 currently missing in the initTool */
5144 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5145 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5146 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5147 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5148 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5149 CHIP_INT_MODE_IS_BC(bp) ?
5150 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5151 }
523224a3 5152}
8a1c38d1 5153
471de716
EG		 5154static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5155{
5156 switch (load_code) {
5157 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5158 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5159 bnx2x_init_internal_common(bp);
5160 /* no break */
5161
5162 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5163 /* nothing to do */
471de716
EG		 5164 /* no break */
5165
5166 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5167 /* internal memory per function is
5168 initialized inside bnx2x_pf_init */
471de716
EG		 5169 break;
5170
5171 default:
5172 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5173 break;
5174 }
5175}
5176
619c5cb6 5177static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5178{
6383c0b3 5179 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5180}
523224a3 5181
619c5cb6
VZ		 5182static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5183{
6383c0b3 5184 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5185}
5186
5187static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5188{
5189 if (CHIP_IS_E1x(fp->bp))
5190 return BP_L_ID(fp->bp) + fp->index;
5191 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5192 return bnx2x_fp_igu_sb_id(fp);
5193}
5194
6383c0b3 5195static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5196{
5197 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5198 u8 cos;
619c5cb6 5199 unsigned long q_type = 0;
6383c0b3 5200 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
523224a3 5201
b3b83c3f 5202 fp->cid = fp_idx;
619c5cb6
VZ		 5203 fp->cl_id = bnx2x_fp_cl_id(fp);
5204 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5205 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5206 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5207 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5208
523224a3 5209 /* init shortcut */
619c5cb6 5210 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 5211 /* Setup SB indicies */
5212 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5213
619c5cb6
VZ		 5214 /* Configure Queue State object */
5215 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5216 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5217
5218 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5219
5220 /* init tx data */
5221 for_each_cos_in_tx_queue(fp, cos) {
5222 bnx2x_init_txdata(bp, &fp->txdata[cos],
5223 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5224 FP_COS_TO_TXQ(fp, cos),
5225 BNX2X_TX_SB_INDEX_BASE + cos);
5226 cids[cos] = fp->txdata[cos].cid;
5227 }
5228
5229 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5230 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5231 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5232
5233 /**
5234 * Configure classification DBs: Always enable Tx switching
5235 */
5236 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5237
523224a3
DK		 5238 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5239 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5240 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5241 fp->igu_sb_id);
5242 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5243 fp->fw_sb_id, fp->igu_sb_id);
5244
5245 bnx2x_update_fpsb_idx(fp);
5246}
5247
9f6c9258 5248void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5249{
5250 int i;
5251
ec6ba945 5252 for_each_eth_queue(bp, i)
6383c0b3 5253 bnx2x_init_eth_fp(bp, i);
37b091ba 5254#ifdef BCM_CNIC
ec6ba945
VZ		 5255 if (!NO_FCOE(bp))
5256 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5257
5258 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5259 BNX2X_VF_ID_INVALID, false,
619c5cb6 5260 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5261
37b091ba 5262#endif
a2fbb9ea 5263
020c7e3f
YR		 5264 /* Initialize MOD_ABS interrupts */
5265 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5266 bp->common.shmem_base, bp->common.shmem2_base,
5267 BP_PORT(bp));
16119785
EG		 5268 /* ensure status block indices were read */
5269 rmb();
5270
523224a3 5271 bnx2x_init_def_sb(bp);
5c862848 5272 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5273 bnx2x_init_rx_rings(bp);
523224a3 5274 bnx2x_init_tx_rings(bp);
a2fbb9ea 5275 bnx2x_init_sp_ring(bp);
523224a3 5276 bnx2x_init_eq_ring(bp);
471de716 5277 bnx2x_init_internal(bp, load_code);
523224a3 5278 bnx2x_pf_init(bp);
0ef00459
EG		 5279 bnx2x_stats_init(bp);
5280
0ef00459
EG		 5281 /* flush all before enabling interrupts */
5282 mb();
5283 mmiowb();
5284
615f8fd9 5285 bnx2x_int_enable(bp);
eb8da205
EG		 5286
5287 /* Check for SPIO5 */
5288 bnx2x_attn_int_deasserted0(bp,
5289 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5290 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5291}
5292
5293/* end of nic init */
5294
5295/*
5296 * gzip service functions
5297 */
5298
5299static int bnx2x_gunzip_init(struct bnx2x *bp)
5300{
1a983142
FT		 5301 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5302 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5303 if (bp->gunzip_buf == NULL)
5304 goto gunzip_nomem1;
5305
5306 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5307 if (bp->strm == NULL)
5308 goto gunzip_nomem2;
5309
7ab24bfd 5310 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5311 if (bp->strm->workspace == NULL)
5312 goto gunzip_nomem3;
5313
5314 return 0;
5315
5316gunzip_nomem3:
5317 kfree(bp->strm);
5318 bp->strm = NULL;
5319
5320gunzip_nomem2:
1a983142
FT		 5321 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5322 bp->gunzip_mapping);
a2fbb9ea
ET		 5323 bp->gunzip_buf = NULL;
5324
5325gunzip_nomem1:
cdaa7cb8
VZ		 5326 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5327 " un-compression\n");
a2fbb9ea
ET		 5328 return -ENOMEM;
5329}
5330
5331static void bnx2x_gunzip_end(struct bnx2x *bp)
5332{
b3b83c3f 5333 if (bp->strm) {
7ab24bfd 5334 vfree(bp->strm->workspace);
b3b83c3f
DK		 5335 kfree(bp->strm);
5336 bp->strm = NULL;
5337 }
a2fbb9ea
ET		 5338
5339 if (bp->gunzip_buf) {
1a983142
FT		 5340 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5341 bp->gunzip_mapping);
a2fbb9ea
ET		 5342 bp->gunzip_buf = NULL;
5343 }
5344}
5345
94a78b79 5346static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5347{
5348 int n, rc;
5349
5350 /* check gzip header */
94a78b79
VZ		 5351 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5352 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5353 return -EINVAL;
94a78b79 5354 }
a2fbb9ea
ET		 5355
5356 n = 10;
5357
34f80b04 5358#define FNAME 0x8
a2fbb9ea
ET		 5359
5360 if (zbuf[3] & FNAME)
5361 while ((zbuf[n++] != 0) && (n < len));
5362
94a78b79 5363 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5364 bp->strm->avail_in = len - n;
5365 bp->strm->next_out = bp->gunzip_buf;
5366 bp->strm->avail_out = FW_BUF_SIZE;
5367
5368 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5369 if (rc != Z_OK)
5370 return rc;
5371
5372 rc = zlib_inflate(bp->strm, Z_FINISH);
5373 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5374 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5375 bp->strm->msg);
a2fbb9ea
ET		 5376
5377 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5378 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 5379 netdev_err(bp->dev, "Firmware decompression error:"
5380 " gunzip_outlen (%d) not aligned\n",
5381 bp->gunzip_outlen);
a2fbb9ea
ET		 5382 bp->gunzip_outlen >>= 2;
5383
5384 zlib_inflateEnd(bp->strm);
5385
5386 if (rc == Z_STREAM_END)
5387 return 0;
5388
5389 return rc;
5390}
5391
5392/* nic load/unload */
5393
5394/*
34f80b04 5395 * General service functions
a2fbb9ea
ET		 5396 */
5397
5398/* send a NIG loopback debug packet */
5399static void bnx2x_lb_pckt(struct bnx2x *bp)
5400{
a2fbb9ea 5401 u32 wb_write[3];
a2fbb9ea
ET		 5402
5403 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5404 wb_write[0] = 0x55555555;
5405 wb_write[1] = 0x55555555;
34f80b04 5406 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5407 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5408
5409 /* NON-IP protocol */
a2fbb9ea
ET		 5410 wb_write[0] = 0x09000000;
5411 wb_write[1] = 0x55555555;
34f80b04 5412 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5413 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5414}
5415
5416/* some of the internal memories
5417 * are not directly readable from the driver
5418 * to test them we send debug packets
5419 */
5420static int bnx2x_int_mem_test(struct bnx2x *bp)
5421{
5422 int factor;
5423 int count, i;
5424 u32 val = 0;
5425
ad8d3948 5426 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5427 factor = 120;
ad8d3948
EG		 5428 else if (CHIP_REV_IS_EMUL(bp))
5429 factor = 200;
5430 else
a2fbb9ea 5431 factor = 1;
a2fbb9ea 5432
a2fbb9ea
ET		 5433 /* Disable inputs of parser neighbor blocks */
5434 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5435 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5436 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5437 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5438
5439 /* Write 0 to parser credits for CFC search request */
5440 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5441
5442 /* send Ethernet packet */
5443 bnx2x_lb_pckt(bp);
5444
5445 /* TODO do i reset NIG statistic? */
5446 /* Wait until NIG register shows 1 packet of size 0x10 */
5447 count = 1000 * factor;
5448 while (count) {
34f80b04 5449
a2fbb9ea
ET		 5450 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5451 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5452 if (val == 0x10)
5453 break;
5454
5455 msleep(10);
5456 count--;
5457 }
5458 if (val != 0x10) {
5459 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5460 return -1;
5461 }
5462
5463 /* Wait until PRS register shows 1 packet */
5464 count = 1000 * factor;
5465 while (count) {
5466 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5467 if (val == 1)
5468 break;
5469
5470 msleep(10);
5471 count--;
5472 }
5473 if (val != 0x1) {
5474 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5475 return -2;
5476 }
5477
5478 /* Reset and init BRB, PRS */
34f80b04 5479 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5480 msleep(50);
34f80b04 5481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5482 msleep(50);
619c5cb6
VZ		 5483 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5484 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5485
5486 DP(NETIF_MSG_HW, "part2\n");
5487
5488 /* Disable inputs of parser neighbor blocks */
5489 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5490 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5491 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5492 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5493
5494 /* Write 0 to parser credits for CFC search request */
5495 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5496
5497 /* send 10 Ethernet packets */
5498 for (i = 0; i < 10; i++)
5499 bnx2x_lb_pckt(bp);
5500
5501 /* Wait until NIG register shows 10 + 1
5502 packets of size 11*0x10 = 0xb0 */
5503 count = 1000 * factor;
5504 while (count) {
34f80b04 5505
a2fbb9ea
ET		 5506 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5507 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5508 if (val == 0xb0)
5509 break;
5510
5511 msleep(10);
5512 count--;
5513 }
5514 if (val != 0xb0) {
5515 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5516 return -3;
5517 }
5518
5519 /* Wait until PRS register shows 2 packets */
5520 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5521 if (val != 2)
5522 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5523
5524 /* Write 1 to parser credits for CFC search request */
5525 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5526
5527 /* Wait until PRS register shows 3 packets */
5528 msleep(10 * factor);
5529 /* Wait until NIG register shows 1 packet of size 0x10 */
5530 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5531 if (val != 3)
5532 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5533
5534 /* clear NIG EOP FIFO */
5535 for (i = 0; i < 11; i++)
5536 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5537 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5538 if (val != 1) {
5539 BNX2X_ERR("clear of NIG failed\n");
5540 return -4;
5541 }
5542
5543 /* Reset and init BRB, PRS, NIG */
5544 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5545 msleep(50);
5546 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5547 msleep(50);
619c5cb6
VZ		 5548 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5549 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5550#ifndef BCM_CNIC
a2fbb9ea
ET		 5551 /* set NIC mode */
5552 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5553#endif
5554
5555 /* Enable inputs of parser neighbor blocks */
5556 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5557 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5558 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5559 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5560
5561 DP(NETIF_MSG_HW, "done\n");
5562
5563 return 0; /* OK */
5564}
5565
4a33bc03 5566static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5567{
5568 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5569 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5570 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5571 else
5572 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5573 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5574 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5575 /*
5576 * mask read length error interrupts in brb for parser
5577 * (parsing unit and 'checksum and crc' unit)
5578 * these errors are legal (PU reads fixed length and CAC can cause
5579 * read length error on truncated packets)
5580 */
5581 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5582 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5583 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5584 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5585 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5586 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5587/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5588/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5589 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5590 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5591 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5592/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5593/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5594 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5595 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5596 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5597 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5598/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5599/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5600
34f80b04
EG		 5601 if (CHIP_REV_IS_FPGA(bp))
5602 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5603 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5604 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5605 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5606 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5607 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5608 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5609 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5610 else
5611 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5612 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5613 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5614 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5615/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5616
5617 if (!CHIP_IS_E1x(bp))
5618 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5619 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5620
a2fbb9ea
ET		 5621 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5622 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5623/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5624 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5625}
5626
81f75bbf
EG		 5627static void bnx2x_reset_common(struct bnx2x *bp)
5628{
619c5cb6
VZ		 5629 u32 val = 0x1400;
5630
81f75bbf
EG		 5631 /* reset_common */
5632 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5633 0xd3ffff7f);
619c5cb6
VZ		 5634
5635 if (CHIP_IS_E3(bp)) {
5636 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5637 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5638 }
5639
5640 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5641}
5642
5643static void bnx2x_setup_dmae(struct bnx2x *bp)
5644{
5645 bp->dmae_ready = 0;
5646 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5647}
5648
573f2035
EG		 5649static void bnx2x_init_pxp(struct bnx2x *bp)
5650{
5651 u16 devctl;
5652 int r_order, w_order;
5653
5654 pci_read_config_word(bp->pdev,
b6c2f86e 5655 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5656 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5657 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5658 if (bp->mrrs == -1)
5659 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5660 else {
5661 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5662 r_order = bp->mrrs;
5663 }
5664
5665 bnx2x_init_pxp_arb(bp, r_order, w_order);
5666}
fd4ef40d
EG		 5667
5668static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5669{
2145a920 5670 int is_required;
fd4ef40d 5671 u32 val;
2145a920 5672 int port;
fd4ef40d 5673
2145a920
VZ		 5674 if (BP_NOMCP(bp))
5675 return;
5676
5677 is_required = 0;
fd4ef40d
EG		 5678 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5679 SHARED_HW_CFG_FAN_FAILURE_MASK;
5680
5681 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5682 is_required = 1;
5683
5684 /*
5685 * The fan failure mechanism is usually related to the PHY type since
5686 * the power consumption of the board is affected by the PHY. Currently,
5687 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5688 */
5689 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5690 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5691 is_required |=
d90d96ba
YR		 5692 bnx2x_fan_failure_det_req(
5693 bp,
5694 bp->common.shmem_base,
a22f0788 5695 bp->common.shmem2_base,
d90d96ba 5696 port);
fd4ef40d
EG		 5697 }
5698
5699 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5700
5701 if (is_required == 0)
5702 return;
5703
5704 /* Fan failure is indicated by SPIO 5 */
5705 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5706 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5707
5708 /* set to active low mode */
5709 val = REG_RD(bp, MISC_REG_SPIO_INT);
5710 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5711 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5712 REG_WR(bp, MISC_REG_SPIO_INT, val);
5713
5714 /* enable interrupt to signal the IGU */
5715 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5716 val |= (1 << MISC_REGISTERS_SPIO_5);
5717 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5718}
5719
f2e0899f
DK		 5720static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5721{
5722 u32 offset = 0;
5723
5724 if (CHIP_IS_E1(bp))
5725 return;
5726 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5727 return;
5728
5729 switch (BP_ABS_FUNC(bp)) {
5730 case 0:
5731 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5732 break;
5733 case 1:
5734 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5735 break;
5736 case 2:
5737 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5738 break;
5739 case 3:
5740 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5741 break;
5742 case 4:
5743 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5744 break;
5745 case 5:
5746 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5747 break;
5748 case 6:
5749 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5750 break;
5751 case 7:
5752 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5753 break;
5754 default:
5755 return;
5756 }
5757
5758 REG_WR(bp, offset, pretend_func_num);
5759 REG_RD(bp, offset);
5760 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5761}
5762
c9ee9206 5763void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5764{
5765 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5766 val &= ~IGU_PF_CONF_FUNC_EN;
5767
5768 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5769 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5770 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5771}
5772
619c5cb6
VZ		 5773static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5774{
5775 u32 shmem_base[2], shmem2_base[2];
5776 shmem_base[0] = bp->common.shmem_base;
5777 shmem2_base[0] = bp->common.shmem2_base;
5778 if (!CHIP_IS_E1x(bp)) {
5779 shmem_base[1] =
5780 SHMEM2_RD(bp, other_shmem_base_addr);
5781 shmem2_base[1] =
5782 SHMEM2_RD(bp, other_shmem2_base_addr);
5783 }
5784 bnx2x_acquire_phy_lock(bp);
5785 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5786 bp->common.chip_id);
5787 bnx2x_release_phy_lock(bp);
5788}
5789
5790/**
5791 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5792 *
5793 * @bp: driver handle
5794 */
5795static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 5796{
619c5cb6 5797 u32 val;
a2fbb9ea 5798
f2e0899f 5799 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 5800
2031bd3a
DK		 5801 /*
5802 * take the UNDI lock to protect undi_unload flow from accessing
5803 * registers while we're resetting the chip
5804 */
5805 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5806
81f75bbf 5807 bnx2x_reset_common(bp);
34f80b04 5808 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 5809
619c5cb6
VZ		 5810 val = 0xfffc;
5811 if (CHIP_IS_E3(bp)) {
5812 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5813 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5814 }
5815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5816
2031bd3a
DK		 5817 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5818
619c5cb6 5819 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 5820
619c5cb6
VZ		 5821 if (!CHIP_IS_E1x(bp)) {
5822 u8 abs_func_id;
f2e0899f
DK		 5823
5824 /**
5825 * 4-port mode or 2-port mode we need to turn of master-enable
5826 * for everyone, after that, turn it back on for self.
5827 * so, we disregard multi-function or not, and always disable
5828 * for all functions on the given path, this means 0,2,4,6 for
5829 * path 0 and 1,3,5,7 for path 1
5830 */
619c5cb6
VZ		 5831 for (abs_func_id = BP_PATH(bp);
5832 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5833 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 5834 REG_WR(bp,
5835 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5836 1);
5837 continue;
5838 }
5839
619c5cb6 5840 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 5841 /* clear pf enable */
5842 bnx2x_pf_disable(bp);
5843 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5844 }
5845 }
a2fbb9ea 5846
619c5cb6 5847 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 5848 if (CHIP_IS_E1(bp)) {
5849 /* enable HW interrupt from PXP on USDM overflow
5850 bit 16 on INT_MASK_0 */
5851 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5852 }
a2fbb9ea 5853
619c5cb6 5854 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 5855 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5856
5857#ifdef __BIG_ENDIAN
34f80b04
EG		 5858 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5859 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5860 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5861 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5862 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5863 /* make sure this value is 0 */
5864 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5865
5866/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5867 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5868 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5869 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5870 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5871#endif
5872
523224a3
DK		 5873 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5874
34f80b04
EG		 5875 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5876 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5877
34f80b04
EG		 5878 /* let the HW do it's magic ... */
5879 msleep(100);
5880 /* finish PXP init */
5881 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5882 if (val != 1) {
5883 BNX2X_ERR("PXP2 CFG failed\n");
5884 return -EBUSY;
5885 }
5886 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5887 if (val != 1) {
5888 BNX2X_ERR("PXP2 RD_INIT failed\n");
5889 return -EBUSY;
5890 }
a2fbb9ea 5891
f2e0899f
DK		 5892 /* Timers bug workaround E2 only. We need to set the entire ILT to
5893 * have entries with value "0" and valid bit on.
5894 * This needs to be done by the first PF that is loaded in a path
5895 * (i.e. common phase)
5896 */
619c5cb6
VZ		 5897 if (!CHIP_IS_E1x(bp)) {
5898/* In E2 there is a bug in the timers block that can cause function 6 / 7
5899 * (i.e. vnic3) to start even if it is marked as "scan-off".
5900 * This occurs when a different function (func2,3) is being marked
5901 * as "scan-off". Real-life scenario for example: if a driver is being
5902 * load-unloaded while func6,7 are down. This will cause the timer to access
5903 * the ilt, translate to a logical address and send a request to read/write.
5904 * Since the ilt for the function that is down is not valid, this will cause
5905 * a translation error which is unrecoverable.
5906 * The Workaround is intended to make sure that when this happens nothing fatal
5907 * will occur. The workaround:
5908 * 1. First PF driver which loads on a path will:
5909 * a. After taking the chip out of reset, by using pretend,
5910 * it will write "0" to the following registers of
5911 * the other vnics.
5912 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5913 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5914 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5915 * And for itself it will write '1' to
5916 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5917 * dmae-operations (writing to pram for example.)
5918 * note: can be done for only function 6,7 but cleaner this
5919 * way.
5920 * b. Write zero+valid to the entire ILT.
5921 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5922 * VNIC3 (of that port). The range allocated will be the
5923 * entire ILT. This is needed to prevent ILT range error.
5924 * 2. Any PF driver load flow:
5925 * a. ILT update with the physical addresses of the allocated
5926 * logical pages.
5927 * b. Wait 20msec. - note that this timeout is needed to make
5928 * sure there are no requests in one of the PXP internal
5929 * queues with "old" ILT addresses.
5930 * c. PF enable in the PGLC.
5931 * d. Clear the was_error of the PF in the PGLC. (could have
5932 * occured while driver was down)
5933 * e. PF enable in the CFC (WEAK + STRONG)
5934 * f. Timers scan enable
5935 * 3. PF driver unload flow:
5936 * a. Clear the Timers scan_en.
5937 * b. Polling for scan_on=0 for that PF.
5938 * c. Clear the PF enable bit in the PXP.
5939 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5940 * e. Write zero+valid to all ILT entries (The valid bit must
5941 * stay set)
5942 * f. If this is VNIC 3 of a port then also init
5943 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5944 * to the last enrty in the ILT.
5945 *
5946 * Notes:
5947 * Currently the PF error in the PGLC is non recoverable.
5948 * In the future the there will be a recovery routine for this error.
5949 * Currently attention is masked.
5950 * Having an MCP lock on the load/unload process does not guarantee that
5951 * there is no Timer disable during Func6/7 enable. This is because the
5952 * Timers scan is currently being cleared by the MCP on FLR.
5953 * Step 2.d can be done only for PF6/7 and the driver can also check if
5954 * there is error before clearing it. But the flow above is simpler and
5955 * more general.
5956 * All ILT entries are written by zero+valid and not just PF6/7
5957 * ILT entries since in the future the ILT entries allocation for
5958 * PF-s might be dynamic.
5959 */
f2e0899f
DK		 5960 struct ilt_client_info ilt_cli;
5961 struct bnx2x_ilt ilt;
5962 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5963 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5964
b595076a 5965 /* initialize dummy TM client */
f2e0899f
DK		 5966 ilt_cli.start = 0;
5967 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5968 ilt_cli.client_num = ILT_CLIENT_TM;
5969
5970 /* Step 1: set zeroes to all ilt page entries with valid bit on
5971 * Step 2: set the timers first/last ilt entry to point
5972 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 5973 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 5974 *
5975 * both steps performed by call to bnx2x_ilt_client_init_op()
5976 * with dummy TM client
5977 *
5978 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5979 * and his brother are split registers
5980 */
5981 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5982 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5983 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5984
5985 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5986 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5987 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5988 }
5989
5990
34f80b04
EG		 5991 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5992 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5993
619c5cb6 5994 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5995 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5996 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 5997 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 5998
619c5cb6 5999 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6000
6001 /* let the HW do it's magic ... */
6002 do {
6003 msleep(200);
6004 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6005 } while (factor-- && (val != 1));
6006
6007 if (val != 1) {
6008 BNX2X_ERR("ATC_INIT failed\n");
6009 return -EBUSY;
6010 }
6011 }
6012
619c5cb6 6013 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6014
34f80b04
EG		 6015 /* clean the DMAE memory */
6016 bp->dmae_ready = 1;
619c5cb6
VZ		 6017 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6018
6019 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6020
6021 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6022
6023 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6024
619c5cb6 6025 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6026
34f80b04
EG		 6027 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6028 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6029 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6030 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6031
619c5cb6 6032 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6033
f85582f8 6034
523224a3
DK		 6035 /* QM queues pointers table */
6036 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6037
34f80b04
EG		 6038 /* soft reset pulse */
6039 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6040 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6041
37b091ba 6042#ifdef BCM_CNIC
619c5cb6 6043 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6044#endif
a2fbb9ea 6045
619c5cb6 6046 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6047 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6048 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6049 /* enable hw interrupt from doorbell Q */
6050 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6051
619c5cb6 6052 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6053
619c5cb6 6054 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6055 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6056
f2e0899f 6057 if (!CHIP_IS_E1(bp))
619c5cb6 6058 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6059
619c5cb6
VZ		 6060 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6061 /* Bit-map indicating which L2 hdrs may appear
6062 * after the basic Ethernet header
6063 */
6064 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6065 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 6066
619c5cb6
VZ		 6067 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6068 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6069 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6070 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6071
619c5cb6
VZ		 6072 if (!CHIP_IS_E1x(bp)) {
6073 /* reset VFC memories */
6074 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6075 VFC_MEMORIES_RST_REG_CAM_RST |
6076 VFC_MEMORIES_RST_REG_RAM_RST);
6077 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6078 VFC_MEMORIES_RST_REG_CAM_RST |
6079 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6080
619c5cb6
VZ		 6081 msleep(20);
6082 }
a2fbb9ea 6083
619c5cb6
VZ		 6084 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6085 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6086 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6087 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6088
34f80b04
EG		 6089 /* sync semi rtc */
6090 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6091 0x80000000);
6092 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6093 0x80000000);
a2fbb9ea 6094
619c5cb6
VZ		 6095 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6096 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6097 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6098
619c5cb6
VZ		 6099 if (!CHIP_IS_E1x(bp))
6100 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6101 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6102
34f80b04 6103 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6104
619c5cb6
VZ		 6105 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6106
37b091ba
MC		 6107#ifdef BCM_CNIC
6108 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6109 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6110 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6111 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6112 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6113 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6114 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6115 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6116 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6117 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6118#endif
34f80b04 6119 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6120
34f80b04
EG		 6121 if (sizeof(union cdu_context) != 1024)
6122 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 6123 dev_alert(&bp->pdev->dev, "please adjust the size "
6124 "of cdu_context(%ld)\n",
7995c64e 6125 (long)sizeof(union cdu_context));
a2fbb9ea 6126
619c5cb6 6127 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6128 val = (4 << 24) + (0 << 12) + 1024;
6129 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6130
619c5cb6 6131 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6132 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6133 /* enable context validation interrupt from CFC */
6134 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6135
6136 /* set the thresholds to prevent CFC/CDU race */
6137 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6138
619c5cb6 6139 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6140
619c5cb6 6141 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6142 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6143
619c5cb6
VZ		 6144 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6145 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6146
34f80b04
EG		 6147 /* Reset PCIE errors for debug */
6148 REG_WR(bp, 0x2814, 0xffffffff);
6149 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6150
619c5cb6 6151 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6152 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6153 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6154 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6155 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6156 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6157 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6158 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6159 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6160 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6161 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6162 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6163 }
6164
619c5cb6 6165 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6166 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6167 /* in E3 this done in per-port section */
6168 if (!CHIP_IS_E3(bp))
6169 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6170 }
619c5cb6
VZ		 6171 if (CHIP_IS_E1H(bp))
6172 /* not applicable for E2 (and above ...) */
6173 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6174
6175 if (CHIP_REV_IS_SLOW(bp))
6176 msleep(200);
6177
6178 /* finish CFC init */
6179 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6180 if (val != 1) {
6181 BNX2X_ERR("CFC LL_INIT failed\n");
6182 return -EBUSY;
6183 }
6184 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6185 if (val != 1) {
6186 BNX2X_ERR("CFC AC_INIT failed\n");
6187 return -EBUSY;
6188 }
6189 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6190 if (val != 1) {
6191 BNX2X_ERR("CFC CAM_INIT failed\n");
6192 return -EBUSY;
6193 }
6194 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6195
f2e0899f
DK		 6196 if (CHIP_IS_E1(bp)) {
6197 /* read NIG statistic
6198 to see if this is our first up since powerup */
6199 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6200 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6201
f2e0899f
DK		 6202 /* do internal memory self test */
6203 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6204 BNX2X_ERR("internal mem self test failed\n");
6205 return -EBUSY;
6206 }
34f80b04
EG		 6207 }
6208
fd4ef40d
EG		 6209 bnx2x_setup_fan_failure_detection(bp);
6210
34f80b04
EG		 6211 /* clear PXP2 attentions */
6212 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6213
4a33bc03 6214 bnx2x_enable_blocks_attention(bp);
c9ee9206 6215 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6216
6bbca910 6217 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6218 if (CHIP_IS_E1x(bp))
6219 bnx2x__common_init_phy(bp);
6bbca910
YR		 6220 } else
6221 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6222
34f80b04
EG		 6223 return 0;
6224}
a2fbb9ea 6225
619c5cb6
VZ		 6226/**
6227 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6228 *
6229 * @bp: driver handle
6230 */
6231static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6232{
6233 int rc = bnx2x_init_hw_common(bp);
6234
6235 if (rc)
6236 return rc;
6237
6238 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6239 if (!BP_NOMCP(bp))
6240 bnx2x__common_init_phy(bp);
6241
6242 return 0;
6243}
6244
523224a3 6245static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6246{
6247 int port = BP_PORT(bp);
619c5cb6 6248 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6249 u32 low, high;
34f80b04 6250 u32 val;
a2fbb9ea 6251
619c5cb6
VZ		 6252 bnx2x__link_reset(bp);
6253
cdaa7cb8 6254 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 6255
6256 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6257
619c5cb6
VZ		 6258 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6259 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6260 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6261
f2e0899f
DK		 6262 /* Timers bug workaround: disables the pf_master bit in pglue at
6263 * common phase, we need to enable it here before any dmae access are
6264 * attempted. Therefore we manually added the enable-master to the
6265 * port phase (it also happens in the function phase)
6266 */
619c5cb6 6267 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6268 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6269
619c5cb6
VZ		 6270 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6271 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6272 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6273 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6274
6275 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6276 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6277 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6278 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6279
523224a3
DK		 6280 /* QM cid (connection) count */
6281 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6282
523224a3 6283#ifdef BCM_CNIC
619c5cb6 6284 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6285 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6286 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6287#endif
cdaa7cb8 6288
619c5cb6 6289 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6290
6291 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6292 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6293
6294 if (IS_MF(bp))
6295 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6296 else if (bp->dev->mtu > 4096) {
6297 if (bp->flags & ONE_PORT_FLAG)
6298 low = 160;
6299 else {
6300 val = bp->dev->mtu;
6301 /* (24*1024 + val*4)/256 */
6302 low = 96 + (val/64) +
6303 ((val % 64) ? 1 : 0);
6304 }
6305 } else
6306 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6307 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6308 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6309 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6310 }
1c06328c 6311
619c5cb6
VZ		 6312 if (CHIP_MODE_IS_4_PORT(bp))
6313 REG_WR(bp, (BP_PORT(bp) ?
6314 BRB1_REG_MAC_GUARANTIED_1 :
6315 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6316
ca00392c 6317
619c5cb6
VZ		 6318 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6319 if (CHIP_IS_E3B0(bp))
6320 /* Ovlan exists only if we are in multi-function +
6321 * switch-dependent mode, in switch-independent there
6322 * is no ovlan headers
6323 */
6324 REG_WR(bp, BP_PORT(bp) ?
6325 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6326 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6327 (bp->path_has_ovlan ? 7 : 6));
356e2385 6328
619c5cb6
VZ		 6329 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6330 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6331 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6332 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6333
619c5cb6
VZ		 6334 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6335 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6336 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6337 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6338
619c5cb6
VZ		 6339 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6340 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6341
619c5cb6
VZ		 6342 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6343
6344 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6345 /* configure PBF to work without PAUSE mtu 9000 */
6346 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6347
f2e0899f
DK		 6348 /* update threshold */
6349 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6350 /* update init credit */
6351 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6352
f2e0899f
DK		 6353 /* probe changes */
6354 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6355 udelay(50);
6356 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6357 }
a2fbb9ea 6358
37b091ba 6359#ifdef BCM_CNIC
619c5cb6 6360 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6361#endif
619c5cb6
VZ		 6362 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6363 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6364
6365 if (CHIP_IS_E1(bp)) {
6366 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6367 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6368 }
619c5cb6 6369 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6370
619c5cb6 6371 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6372
619c5cb6 6373 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6374 /* init aeu_mask_attn_func_0/1:
6375 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6376 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6377 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6378 val = IS_MF(bp) ? 0xF7 : 0x7;
6379 /* Enable DCBX attention for all but E1 */
6380 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6381 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6382
619c5cb6
VZ		 6383 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6384
6385 if (!CHIP_IS_E1x(bp)) {
6386 /* Bit-map indicating which L2 hdrs may appear after the
6387 * basic Ethernet header
6388 */
6389 REG_WR(bp, BP_PORT(bp) ?
6390 NIG_REG_P1_HDRS_AFTER_BASIC :
6391 NIG_REG_P0_HDRS_AFTER_BASIC,
6392 IS_MF_SD(bp) ? 7 : 6);
6393
6394 if (CHIP_IS_E3(bp))
6395 REG_WR(bp, BP_PORT(bp) ?
6396 NIG_REG_LLH1_MF_MODE :
6397 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6398 }
6399 if (!CHIP_IS_E3(bp))
6400 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6401
f2e0899f 6402 if (!CHIP_IS_E1(bp)) {
fb3bff17 6403 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6404 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6405 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6406
619c5cb6 6407 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6408 val = 0;
6409 switch (bp->mf_mode) {
6410 case MULTI_FUNCTION_SD:
6411 val = 1;
6412 break;
6413 case MULTI_FUNCTION_SI:
6414 val = 2;
6415 break;
6416 }
6417
6418 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6419 NIG_REG_LLH0_CLS_TYPE), val);
6420 }
1c06328c
EG		 6421 {
6422 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6423 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6424 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6425 }
34f80b04
EG		 6426 }
6427
619c5cb6
VZ		 6428
6429 /* If SPIO5 is set to generate interrupts, enable it for this port */
6430 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6431 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6432 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6433 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6434 val = REG_RD(bp, reg_addr);
f1410647 6435 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6436 REG_WR(bp, reg_addr, val);
f1410647 6437 }
a2fbb9ea 6438
34f80b04
EG		 6439 return 0;
6440}
6441
34f80b04
EG		 6442static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6443{
6444 int reg;
6445
f2e0899f 6446 if (CHIP_IS_E1(bp))
34f80b04 6447 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6448 else
6449 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 6450
6451 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6452}
6453
f2e0899f
DK		 6454static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6455{
619c5cb6 6456 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6457}
6458
6459static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6460{
6461 u32 i, base = FUNC_ILT_BASE(func);
6462 for (i = base; i < base + ILT_PER_FUNC; i++)
6463 bnx2x_ilt_wr(bp, i, 0);
6464}
6465
523224a3 6466static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6467{
6468 int port = BP_PORT(bp);
6469 int func = BP_FUNC(bp);
619c5cb6 6470 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6471 struct bnx2x_ilt *ilt = BP_ILT(bp);
6472 u16 cdu_ilt_start;
8badd27a 6473 u32 addr, val;
f4a66897
VZ		 6474 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6475 int i, main_mem_width;
34f80b04 6476
cdaa7cb8 6477 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6478
619c5cb6
VZ		 6479 /* FLR cleanup - hmmm */
6480 if (!CHIP_IS_E1x(bp))
6481 bnx2x_pf_flr_clnup(bp);
6482
8badd27a 6483 /* set MSI reconfigure capability */
f2e0899f
DK		 6484 if (bp->common.int_block == INT_BLOCK_HC) {
6485 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6486 val = REG_RD(bp, addr);
6487 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6488 REG_WR(bp, addr, val);
6489 }
8badd27a 6490
619c5cb6
VZ		 6491 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6492 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6493
523224a3
DK		 6494 ilt = BP_ILT(bp);
6495 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6496
523224a3
DK		 6497 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6498 ilt->lines[cdu_ilt_start + i].page =
6499 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6500 ilt->lines[cdu_ilt_start + i].page_mapping =
6501 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6502 /* cdu ilt pages are allocated manually so there's no need to
6503 set the size */
37b091ba 6504 }
523224a3 6505 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6506
523224a3
DK		 6507#ifdef BCM_CNIC
6508 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6509
523224a3
DK		 6510 /* T1 hash bits value determines the T1 number of entries */
6511 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6512#endif
37b091ba 6513
523224a3
DK		 6514#ifndef BCM_CNIC
6515 /* set NIC mode */
6516 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6517#endif /* BCM_CNIC */
37b091ba 6518
619c5cb6 6519 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6520 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6521
6522 /* Turn on a single ISR mode in IGU if driver is going to use
6523 * INT#x or MSI
6524 */
6525 if (!(bp->flags & USING_MSIX_FLAG))
6526 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6527 /*
6528 * Timers workaround bug: function init part.
6529 * Need to wait 20msec after initializing ILT,
6530 * needed to make sure there are no requests in
6531 * one of the PXP internal queues with "old" ILT addresses
6532 */
6533 msleep(20);
6534 /*
6535 * Master enable - Due to WB DMAE writes performed before this
6536 * register is re-initialized as part of the regular function
6537 * init
6538 */
6539 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6540 /* Enable the function in IGU */
6541 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6542 }
6543
523224a3 6544 bp->dmae_ready = 1;
34f80b04 6545
619c5cb6 6546 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6547
619c5cb6 6548 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6549 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6550
619c5cb6
VZ		 6551 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6552 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6553 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6554 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6555 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6556 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6557 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6558 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6559 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6560 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6561 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6562 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6563 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6564
6565 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6566 REG_WR(bp, QM_REG_PF_EN, 1);
6567
619c5cb6
VZ		 6568 if (!CHIP_IS_E1x(bp)) {
6569 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6570 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6571 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6572 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6573 }
6574 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6575
6576 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6577 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6578 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6579 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6580 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6581 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6582 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6583 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6584 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6585 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6586 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6587 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6588 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6589
619c5cb6 6590 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6591
619c5cb6 6592 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6593
619c5cb6 6594 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6595 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6596
fb3bff17 6597 if (IS_MF(bp)) {
34f80b04 6598 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6599 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6600 }
6601
619c5cb6 6602 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6603
34f80b04 6604 /* HC init per function */
f2e0899f
DK		 6605 if (bp->common.int_block == INT_BLOCK_HC) {
6606 if (CHIP_IS_E1H(bp)) {
6607 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6608
6609 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6610 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6611 }
619c5cb6 6612 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6613
6614 } else {
6615 int num_segs, sb_idx, prod_offset;
6616
34f80b04
EG		 6617 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6618
619c5cb6 6619 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6620 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6621 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6622 }
6623
619c5cb6 6624 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6625
619c5cb6 6626 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6627 int dsb_idx = 0;
6628 /**
6629 * Producer memory:
6630 * E2 mode: address 0-135 match to the mapping memory;
6631 * 136 - PF0 default prod; 137 - PF1 default prod;
6632 * 138 - PF2 default prod; 139 - PF3 default prod;
6633 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6634 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6635 * 144-147 reserved.
6636 *
6637 * E1.5 mode - In backward compatible mode;
6638 * for non default SB; each even line in the memory
6639 * holds the U producer and each odd line hold
6640 * the C producer. The first 128 producers are for
6641 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6642 * producers are for the DSB for each PF.
6643 * Each PF has five segments: (the order inside each
6644 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6645 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6646 * 144-147 attn prods;
6647 */
6648 /* non-default-status-blocks */
6649 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6650 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6651 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6652 prod_offset = (bp->igu_base_sb + sb_idx) *
6653 num_segs;
6654
6655 for (i = 0; i < num_segs; i++) {
6656 addr = IGU_REG_PROD_CONS_MEMORY +
6657 (prod_offset + i) * 4;
6658 REG_WR(bp, addr, 0);
6659 }
6660 /* send consumer update with value 0 */
6661 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6662 USTORM_ID, 0, IGU_INT_NOP, 1);
6663 bnx2x_igu_clear_sb(bp,
6664 bp->igu_base_sb + sb_idx);
6665 }
6666
6667 /* default-status-blocks */
6668 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6669 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6670
6671 if (CHIP_MODE_IS_4_PORT(bp))
6672 dsb_idx = BP_FUNC(bp);
6673 else
6674 dsb_idx = BP_E1HVN(bp);
6675
6676 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6677 IGU_BC_BASE_DSB_PROD + dsb_idx :
6678 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6679
6680 for (i = 0; i < (num_segs * E1HVN_MAX);
6681 i += E1HVN_MAX) {
6682 addr = IGU_REG_PROD_CONS_MEMORY +
6683 (prod_offset + i)*4;
6684 REG_WR(bp, addr, 0);
6685 }
6686 /* send consumer update with 0 */
6687 if (CHIP_INT_MODE_IS_BC(bp)) {
6688 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6689 USTORM_ID, 0, IGU_INT_NOP, 1);
6690 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6691 CSTORM_ID, 0, IGU_INT_NOP, 1);
6692 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6693 XSTORM_ID, 0, IGU_INT_NOP, 1);
6694 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6695 TSTORM_ID, 0, IGU_INT_NOP, 1);
6696 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6697 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6698 } else {
6699 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6700 USTORM_ID, 0, IGU_INT_NOP, 1);
6701 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6702 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6703 }
6704 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6705
6706 /* !!! these should become driver const once
6707 rf-tool supports split-68 const */
6708 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6709 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6710 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6711 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6712 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6713 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6714 }
34f80b04 6715 }
34f80b04 6716
c14423fe 6717 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6718 REG_WR(bp, 0x2114, 0xffffffff);
6719 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6720
f4a66897
VZ		 6721 if (CHIP_IS_E1x(bp)) {
6722 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6723 main_mem_base = HC_REG_MAIN_MEMORY +
6724 BP_PORT(bp) * (main_mem_size * 4);
6725 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6726 main_mem_width = 8;
6727
6728 val = REG_RD(bp, main_mem_prty_clr);
6729 if (val)
6730 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6731 "block during "
6732 "function init (0x%x)!\n", val);
6733
6734 /* Clear "false" parity errors in MSI-X table */
6735 for (i = main_mem_base;
6736 i < main_mem_base + main_mem_size * 4;
6737 i += main_mem_width) {
6738 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6739 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6740 i, main_mem_width / 4);
6741 }
6742 /* Clear HC parity attention */
6743 REG_RD(bp, main_mem_prty_clr);
6744 }
6745
619c5cb6
VZ		 6746#ifdef BNX2X_STOP_ON_ERROR
6747 /* Enable STORMs SP logging */
6748 REG_WR8(bp, BAR_USTRORM_INTMEM +
6749 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6750 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6751 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6752 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6753 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6754 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6755 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6756#endif
6757
b7737c9b 6758 bnx2x_phy_probe(&bp->link_params);
f85582f8 6759
34f80b04
EG		 6760 return 0;
6761}
6762
a2fbb9ea 6763
9f6c9258 6764void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6765{
a2fbb9ea 6766 /* fastpath */
b3b83c3f 6767 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6768 /* end of fastpath */
6769
6770 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 6771 sizeof(struct host_sp_status_block));
a2fbb9ea 6772
619c5cb6
VZ		 6773 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6774 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6775
a2fbb9ea 6776 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 6777 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6778
523224a3
DK		 6779 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6780 bp->context.size);
6781
6782 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6783
6784 BNX2X_FREE(bp->ilt->lines);
f85582f8 6785
37b091ba 6786#ifdef BCM_CNIC
619c5cb6 6787 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6788 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6789 sizeof(struct host_hc_status_block_e2));
6790 else
6791 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6792 sizeof(struct host_hc_status_block_e1x));
f85582f8 6793
523224a3 6794 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 6795#endif
f85582f8 6796
7a9b2557 6797 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 6798
523224a3
DK		 6799 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6800 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 6801}
6802
6803static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6804{
6805 int num_groups;
6806
6807 /* number of eth_queues */
6808 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6809
6810 /* Total number of FW statistics requests =
6811 * 1 for port stats + 1 for PF stats + num_eth_queues */
6812 bp->fw_stats_num = 2 + num_queue_stats;
523224a3 6813
619c5cb6
VZ		 6814
6815 /* Request is built from stats_query_header and an array of
6816 * stats_query_cmd_group each of which contains
6817 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6818 * configured in the stats_query_header.
6819 */
6820 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6821 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6822
6823 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6824 num_groups * sizeof(struct stats_query_cmd_group);
6825
6826 /* Data for statistics requests + stats_conter
6827 *
6828 * stats_counter holds per-STORM counters that are incremented
6829 * when STORM has finished with the current request.
6830 */
6831 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6832 sizeof(struct per_pf_stats) +
6833 sizeof(struct per_queue_stats) * num_queue_stats +
6834 sizeof(struct stats_counter);
6835
6836 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6837 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6838
6839 /* Set shortcuts */
6840 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6841 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6842
6843 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6844 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6845
6846 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6847 bp->fw_stats_req_sz;
6848 return 0;
6849
6850alloc_mem_err:
6851 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6852 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6853 return -ENOMEM;
a2fbb9ea
ET		 6854}
6855
f2e0899f 6856
9f6c9258 6857int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6858{
523224a3 6859#ifdef BCM_CNIC
619c5cb6
VZ		 6860 if (!CHIP_IS_E1x(bp))
6861 /* size = the status block + ramrod buffers */
f2e0899f
DK		 6862 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6863 sizeof(struct host_hc_status_block_e2));
6864 else
6865 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6866 sizeof(struct host_hc_status_block_e1x));
8badd27a 6867
523224a3
DK		 6868 /* allocate searcher T2 table */
6869 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6870#endif
a2fbb9ea 6871
8badd27a 6872
523224a3
DK		 6873 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6874 sizeof(struct host_sp_status_block));
a2fbb9ea 6875
523224a3
DK		 6876 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6877 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6878
619c5cb6
VZ		 6879 /* Allocated memory for FW statistics */
6880 if (bnx2x_alloc_fw_stats_mem(bp))
6881 goto alloc_mem_err;
6882
6383c0b3 6883 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 6884
523224a3
DK		 6885 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6886 bp->context.size);
65abd74d 6887
523224a3 6888 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6889
523224a3
DK		 6890 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6891 goto alloc_mem_err;
65abd74d 6892
9f6c9258
DK		 6893 /* Slow path ring */
6894 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6895
523224a3
DK		 6896 /* EQ */
6897 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6898 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 6899
b3b83c3f
DK		 6900
6901 /* fastpath */
6902 /* need to be done at the end, since it's self adjusting to amount
6903 * of memory available for RSS queues
6904 */
6905 if (bnx2x_alloc_fp_mem(bp))
6906 goto alloc_mem_err;
9f6c9258 6907 return 0;
e1510706 6908
9f6c9258
DK		 6909alloc_mem_err:
6910 bnx2x_free_mem(bp);
6911 return -ENOMEM;
65abd74d
YG		 6912}
6913
a2fbb9ea
ET		 6914/*
6915 * Init service functions
6916 */
a2fbb9ea 6917
619c5cb6
VZ		 6918int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6919 struct bnx2x_vlan_mac_obj *obj, bool set,
6920 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 6921{
619c5cb6
VZ		 6922 int rc;
6923 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 6924
619c5cb6 6925 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 6926
619c5cb6
VZ		 6927 /* Fill general parameters */
6928 ramrod_param.vlan_mac_obj = obj;
6929 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 6930
619c5cb6
VZ		 6931 /* Fill a user request section if needed */
6932 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6933 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 6934
619c5cb6 6935 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 6936
619c5cb6
VZ		 6937 /* Set the command: ADD or DEL */
6938 if (set)
6939 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6940 else
6941 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 6942 }
6943
619c5cb6
VZ		 6944 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6945 if (rc < 0)
6946 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6947 return rc;
a2fbb9ea
ET		 6948}
6949
619c5cb6
VZ		 6950int bnx2x_del_all_macs(struct bnx2x *bp,
6951 struct bnx2x_vlan_mac_obj *mac_obj,
6952 int mac_type, bool wait_for_comp)
e665bfda 6953{
619c5cb6
VZ		 6954 int rc;
6955 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 6956
619c5cb6
VZ		 6957 /* Wait for completion of requested */
6958 if (wait_for_comp)
6959 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 6960
619c5cb6
VZ		 6961 /* Set the mac type of addresses we want to clear */
6962 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 6963
619c5cb6
VZ		 6964 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6965 if (rc < 0)
6966 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 6967
619c5cb6 6968 return rc;
0793f83f
DK		 6969}
6970
619c5cb6 6971int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 6972{
619c5cb6 6973 unsigned long ramrod_flags = 0;
e665bfda 6974
619c5cb6 6975 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 6976
619c5cb6
VZ		 6977 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6978 /* Eth MAC is set on RSS leading client (fp[0]) */
6979 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6980 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 6981}
6e30dd4e 6982
619c5cb6 6983int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 6984{
619c5cb6 6985 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 6986}
a2fbb9ea 6987
d6214d7a 6988/**
e8920674 6989 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 6990 *
e8920674 6991 * @bp: driver handle
d6214d7a 6992 *
e8920674 6993 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 6994 */
9ee3d37b 6995static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6996{
9ee3d37b 6997 switch (int_mode) {
d6214d7a
DK		 6998 case INT_MODE_MSI:
6999 bnx2x_enable_msi(bp);
7000 /* falling through... */
7001 case INT_MODE_INTx:
6383c0b3 7002 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7003 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 7004 break;
d6214d7a
DK		 7005 default:
7006 /* Set number of queues according to bp->multi_mode value */
7007 bnx2x_set_num_queues(bp);
ca00392c 7008
d6214d7a
DK		 7009 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7010 bp->num_queues);
ca00392c 7011
d6214d7a
DK		 7012 /* if we can't use MSI-X we only need one fp,
7013 * so try to enable MSI-X with the requested number of fp's
7014 * and fallback to MSI or legacy INTx with one fp
7015 */
9ee3d37b 7016 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 7017 /* failed to enable MSI-X */
7018 if (bp->multi_mode)
7019 DP(NETIF_MSG_IFUP,
7020 "Multi requested but failed to "
7021 "enable MSI-X (%d), "
7022 "set number of queues to %d\n",
7023 bp->num_queues,
6383c0b3
AE		 7024 1 + NON_ETH_CONTEXT_USE);
7025 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7026
9ee3d37b 7027 /* Try to enable MSI */
d6214d7a
DK		 7028 if (!(bp->flags & DISABLE_MSI_FLAG))
7029 bnx2x_enable_msi(bp);
7030 }
9f6c9258
DK		 7031 break;
7032 }
a2fbb9ea
ET		 7033}
7034
c2bff63f
DK		 7035/* must be called prioir to any HW initializations */
7036static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7037{
7038 return L2_ILT_LINES(bp);
7039}
7040
523224a3
DK		 7041void bnx2x_ilt_set_info(struct bnx2x *bp)
7042{
7043 struct ilt_client_info *ilt_client;
7044 struct bnx2x_ilt *ilt = BP_ILT(bp);
7045 u16 line = 0;
7046
7047 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7048 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7049
7050 /* CDU */
7051 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7052 ilt_client->client_num = ILT_CLIENT_CDU;
7053 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7054 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7055 ilt_client->start = line;
619c5cb6 7056 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 7057#ifdef BCM_CNIC
7058 line += CNIC_ILT_LINES;
7059#endif
7060 ilt_client->end = line - 1;
7061
7062 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7063 "flags 0x%x, hw psz %d\n",
7064 ilt_client->start,
7065 ilt_client->end,
7066 ilt_client->page_size,
7067 ilt_client->flags,
7068 ilog2(ilt_client->page_size >> 12));
7069
7070 /* QM */
7071 if (QM_INIT(bp->qm_cid_count)) {
7072 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7073 ilt_client->client_num = ILT_CLIENT_QM;
7074 ilt_client->page_size = QM_ILT_PAGE_SZ;
7075 ilt_client->flags = 0;
7076 ilt_client->start = line;
7077
7078 /* 4 bytes for each cid */
7079 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7080 QM_ILT_PAGE_SZ);
7081
7082 ilt_client->end = line - 1;
7083
7084 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7085 "flags 0x%x, hw psz %d\n",
7086 ilt_client->start,
7087 ilt_client->end,
7088 ilt_client->page_size,
7089 ilt_client->flags,
7090 ilog2(ilt_client->page_size >> 12));
7091
7092 }
7093 /* SRC */
7094 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7095#ifdef BCM_CNIC
7096 ilt_client->client_num = ILT_CLIENT_SRC;
7097 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7098 ilt_client->flags = 0;
7099 ilt_client->start = line;
7100 line += SRC_ILT_LINES;
7101 ilt_client->end = line - 1;
7102
7103 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7104 "flags 0x%x, hw psz %d\n",
7105 ilt_client->start,
7106 ilt_client->end,
7107 ilt_client->page_size,
7108 ilt_client->flags,
7109 ilog2(ilt_client->page_size >> 12));
7110
7111#else
7112 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7113#endif
9f6c9258 7114
523224a3
DK		 7115 /* TM */
7116 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7117#ifdef BCM_CNIC
7118 ilt_client->client_num = ILT_CLIENT_TM;
7119 ilt_client->page_size = TM_ILT_PAGE_SZ;
7120 ilt_client->flags = 0;
7121 ilt_client->start = line;
7122 line += TM_ILT_LINES;
7123 ilt_client->end = line - 1;
7124
7125 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7126 "flags 0x%x, hw psz %d\n",
7127 ilt_client->start,
7128 ilt_client->end,
7129 ilt_client->page_size,
7130 ilt_client->flags,
7131 ilog2(ilt_client->page_size >> 12));
9f6c9258 7132
523224a3
DK		 7133#else
7134 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7135#endif
619c5cb6 7136 BUG_ON(line > ILT_MAX_LINES);
523224a3 7137}
f85582f8 7138
619c5cb6
VZ		 7139/**
7140 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7141 *
7142 * @bp: driver handle
7143 * @fp: pointer to fastpath
7144 * @init_params: pointer to parameters structure
7145 *
7146 * parameters configured:
7147 * - HC configuration
7148 * - Queue's CDU context
7149 */
7150static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7151 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7152{
6383c0b3
AE		 7153
7154 u8 cos;
619c5cb6
VZ		 7155 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7156 if (!IS_FCOE_FP(fp)) {
7157 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7158 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7159
7160 /* If HC is supporterd, enable host coalescing in the transition
7161 * to INIT state.
7162 */
7163 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7164 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7165
7166 /* HC rate */
7167 init_params->rx.hc_rate = bp->rx_ticks ?
7168 (1000000 / bp->rx_ticks) : 0;
7169 init_params->tx.hc_rate = bp->tx_ticks ?
7170 (1000000 / bp->tx_ticks) : 0;
7171
7172 /* FW SB ID */
7173 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7174 fp->fw_sb_id;
7175
7176 /*
7177 * CQ index among the SB indices: FCoE clients uses the default
7178 * SB, therefore it's different.
7179 */
6383c0b3
AE		 7180 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7181 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7182 }
7183
6383c0b3
AE		 7184 /* set maximum number of COSs supported by this queue */
7185 init_params->max_cos = fp->max_cos;
7186
7187 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7188 fp->index, init_params->max_cos);
7189
7190 /* set the context pointers queue object */
7191 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7192 init_params->cxts[cos] =
7193 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7194}
7195
6383c0b3
AE		 7196int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7197 struct bnx2x_queue_state_params *q_params,
7198 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7199 int tx_index, bool leading)
7200{
7201 memset(tx_only_params, 0, sizeof(*tx_only_params));
7202
7203 /* Set the command */
7204 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7205
7206 /* Set tx-only QUEUE flags: don't zero statistics */
7207 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7208
7209 /* choose the index of the cid to send the slow path on */
7210 tx_only_params->cid_index = tx_index;
7211
7212 /* Set general TX_ONLY_SETUP parameters */
7213 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7214
7215 /* Set Tx TX_ONLY_SETUP parameters */
7216 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7217
7218 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7219 "cos %d, primary cid %d, cid %d, "
7220 "client id %d, sp-client id %d, flags %lx",
7221 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7222 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7223 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7224
7225 /* send the ramrod */
7226 return bnx2x_queue_state_change(bp, q_params);
7227}
7228
7229
619c5cb6
VZ		 7230/**
7231 * bnx2x_setup_queue - setup queue
7232 *
7233 * @bp: driver handle
7234 * @fp: pointer to fastpath
7235 * @leading: is leading
7236 *
7237 * This function performs 2 steps in a Queue state machine
7238 * actually: 1) RESET->INIT 2) INIT->SETUP
7239 */
7240
7241int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7242 bool leading)
7243{
7244 struct bnx2x_queue_state_params q_params = {0};
7245 struct bnx2x_queue_setup_params *setup_params =
7246 &q_params.params.setup;
6383c0b3
AE		 7247 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7248 &q_params.params.tx_only;
a2fbb9ea 7249 int rc;
6383c0b3
AE		 7250 u8 tx_index;
7251
7252 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
a2fbb9ea 7253
ec6ba945
VZ		 7254 /* reset IGU state skip FCoE L2 queue */
7255 if (!IS_FCOE_FP(fp))
7256 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7257 IGU_INT_ENABLE, 0);
a2fbb9ea 7258
619c5cb6
VZ		 7259 q_params.q_obj = &fp->q_obj;
7260 /* We want to wait for completion in this context */
7261 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7262
619c5cb6
VZ		 7263 /* Prepare the INIT parameters */
7264 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7265
619c5cb6
VZ		 7266 /* Set the command */
7267 q_params.cmd = BNX2X_Q_CMD_INIT;
7268
7269 /* Change the state to INIT */
7270 rc = bnx2x_queue_state_change(bp, &q_params);
7271 if (rc) {
6383c0b3 7272 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7273 return rc;
7274 }
ec6ba945 7275
6383c0b3
AE		 7276 DP(BNX2X_MSG_SP, "init complete");
7277
7278
619c5cb6
VZ		 7279 /* Now move the Queue to the SETUP state... */
7280 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7281
619c5cb6
VZ		 7282 /* Set QUEUE flags */
7283 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7284
619c5cb6 7285 /* Set general SETUP parameters */
6383c0b3
AE		 7286 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7287 FIRST_TX_COS_INDEX);
619c5cb6 7288
6383c0b3 7289 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7290 &setup_params->rxq_params);
7291
6383c0b3
AE		 7292 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7293 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7294
7295 /* Set the command */
7296 q_params.cmd = BNX2X_Q_CMD_SETUP;
7297
7298 /* Change the state to SETUP */
7299 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7300 if (rc) {
7301 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7302 return rc;
7303 }
7304
7305 /* loop through the relevant tx-only indices */
7306 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7307 tx_index < fp->max_cos;
7308 tx_index++) {
7309
7310 /* prepare and send tx-only ramrod*/
7311 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7312 tx_only_params, tx_index, leading);
7313 if (rc) {
7314 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7315 fp->index, tx_index);
7316 return rc;
7317 }
7318 }
523224a3 7319
34f80b04 7320 return rc;
a2fbb9ea
ET		 7321}
7322
619c5cb6 7323static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7324{
619c5cb6 7325 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7326 struct bnx2x_fp_txdata *txdata;
619c5cb6 7327 struct bnx2x_queue_state_params q_params = {0};
6383c0b3
AE		 7328 int rc, tx_index;
7329
7330 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
a2fbb9ea 7331
619c5cb6
VZ		 7332 q_params.q_obj = &fp->q_obj;
7333 /* We want to wait for completion in this context */
7334 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7335
6383c0b3
AE		 7336
7337 /* close tx-only connections */
7338 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7339 tx_index < fp->max_cos;
7340 tx_index++){
7341
7342 /* ascertain this is a normal queue*/
7343 txdata = &fp->txdata[tx_index];
7344
7345 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7346 txdata->txq_index);
7347
7348 /* send halt terminate on tx-only connection */
7349 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7350 memset(&q_params.params.terminate, 0,
7351 sizeof(q_params.params.terminate));
7352 q_params.params.terminate.cid_index = tx_index;
7353
7354 rc = bnx2x_queue_state_change(bp, &q_params);
7355 if (rc)
7356 return rc;
7357
7358 /* send halt terminate on tx-only connection */
7359 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7360 memset(&q_params.params.cfc_del, 0,
7361 sizeof(q_params.params.cfc_del));
7362 q_params.params.cfc_del.cid_index = tx_index;
7363 rc = bnx2x_queue_state_change(bp, &q_params);
7364 if (rc)
7365 return rc;
7366 }
7367 /* Stop the primary connection: */
7368 /* ...halt the connection */
619c5cb6
VZ		 7369 q_params.cmd = BNX2X_Q_CMD_HALT;
7370 rc = bnx2x_queue_state_change(bp, &q_params);
7371 if (rc)
da5a662a 7372 return rc;
a2fbb9ea 7373
6383c0b3 7374 /* ...terminate the connection */
619c5cb6 7375 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7376 memset(&q_params.params.terminate, 0,
7377 sizeof(q_params.params.terminate));
7378 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7379 rc = bnx2x_queue_state_change(bp, &q_params);
7380 if (rc)
523224a3 7381 return rc;
6383c0b3 7382 /* ...delete cfc entry */
619c5cb6 7383 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7384 memset(&q_params.params.cfc_del, 0,
7385 sizeof(q_params.params.cfc_del));
7386 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7387 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7388}
7389
7390
34f80b04
EG		 7391static void bnx2x_reset_func(struct bnx2x *bp)
7392{
7393 int port = BP_PORT(bp);
7394 int func = BP_FUNC(bp);
f2e0899f 7395 int i;
523224a3
DK		 7396
7397 /* Disable the function in the FW */
7398 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7399 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7400 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7401 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7402
7403 /* FP SBs */
ec6ba945 7404 for_each_eth_queue(bp, i) {
523224a3 7405 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7406 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7407 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7408 SB_DISABLED);
523224a3
DK		 7409 }
7410
619c5cb6
VZ		 7411#ifdef BCM_CNIC
7412 /* CNIC SB */
7413 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7414 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7415 SB_DISABLED);
7416#endif
523224a3 7417 /* SP SB */
619c5cb6 7418 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7419 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7420 SB_DISABLED);
523224a3
DK		 7421
7422 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7423 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7424 0);
34f80b04
EG		 7425
7426 /* Configure IGU */
f2e0899f
DK		 7427 if (bp->common.int_block == INT_BLOCK_HC) {
7428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7430 } else {
7431 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7432 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7433 }
34f80b04 7434
37b091ba
MC		 7435#ifdef BCM_CNIC
7436 /* Disable Timer scan */
7437 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7438 /*
7439 * Wait for at least 10ms and up to 2 second for the timers scan to
7440 * complete
7441 */
7442 for (i = 0; i < 200; i++) {
7443 msleep(10);
7444 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7445 break;
7446 }
7447#endif
34f80b04 7448 /* Clear ILT */
f2e0899f
DK		 7449 bnx2x_clear_func_ilt(bp, func);
7450
7451 /* Timers workaround bug for E2: if this is vnic-3,
7452 * we need to set the entire ilt range for this timers.
7453 */
619c5cb6 7454 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7455 struct ilt_client_info ilt_cli;
7456 /* use dummy TM client */
7457 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7458 ilt_cli.start = 0;
7459 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7460 ilt_cli.client_num = ILT_CLIENT_TM;
7461
7462 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7463 }
7464
7465 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7466 if (!CHIP_IS_E1x(bp))
f2e0899f 7467 bnx2x_pf_disable(bp);
523224a3
DK		 7468
7469 bp->dmae_ready = 0;
34f80b04
EG		 7470}
7471
7472static void bnx2x_reset_port(struct bnx2x *bp)
7473{
7474 int port = BP_PORT(bp);
7475 u32 val;
7476
619c5cb6
VZ		 7477 /* Reset physical Link */
7478 bnx2x__link_reset(bp);
7479
34f80b04
EG		 7480 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7481
7482 /* Do not rcv packets to BRB */
7483 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7484 /* Do not direct rcv packets that are not for MCP to the BRB */
7485 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7486 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7487
7488 /* Configure AEU */
7489 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7490
7491 msleep(100);
7492 /* Check for BRB port occupancy */
7493 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7494 if (val)
7495 DP(NETIF_MSG_IFDOWN,
33471629 7496 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7497
7498 /* TODO: Close Doorbell port? */
7499}
7500
619c5cb6 7501static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7502{
619c5cb6 7503 struct bnx2x_func_state_params func_params = {0};
34f80b04 7504
619c5cb6
VZ		 7505 /* Prepare parameters for function state transitions */
7506 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7507
619c5cb6
VZ		 7508 func_params.f_obj = &bp->func_obj;
7509 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7510
619c5cb6 7511 func_params.params.hw_init.load_phase = load_code;
49d66772 7512
619c5cb6 7513 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7514}
7515
619c5cb6 7516static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7517{
619c5cb6
VZ		 7518 struct bnx2x_func_state_params func_params = {0};
7519 int rc;
228241eb 7520
619c5cb6
VZ		 7521 /* Prepare parameters for function state transitions */
7522 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7523 func_params.f_obj = &bp->func_obj;
7524 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7525
619c5cb6
VZ		 7526 /*
7527 * Try to stop the function the 'good way'. If fails (in case
7528 * of a parity error during bnx2x_chip_cleanup()) and we are
7529 * not in a debug mode, perform a state transaction in order to
7530 * enable further HW_RESET transaction.
7531 */
7532 rc = bnx2x_func_state_change(bp, &func_params);
7533 if (rc) {
34f80b04 7534#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7535 return rc;
34f80b04 7536#else
619c5cb6
VZ		 7537 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7538 "transaction\n");
7539 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7540 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7541#endif
228241eb 7542 }
a2fbb9ea 7543
619c5cb6
VZ		 7544 return 0;
7545}
523224a3 7546
619c5cb6
VZ		 7547/**
7548 * bnx2x_send_unload_req - request unload mode from the MCP.
7549 *
7550 * @bp: driver handle
7551 * @unload_mode: requested function's unload mode
7552 *
7553 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7554 */
7555u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7556{
7557 u32 reset_code = 0;
7558 int port = BP_PORT(bp);
3101c2bc 7559
619c5cb6 7560 /* Select the UNLOAD request mode */
65abd74d
YG		 7561 if (unload_mode == UNLOAD_NORMAL)
7562 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7563
7d0446c2 7564 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7565 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7566
7d0446c2 7567 else if (bp->wol) {
65abd74d
YG		 7568 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7569 u8 *mac_addr = bp->dev->dev_addr;
7570 u32 val;
7571 /* The mac address is written to entries 1-4 to
7572 preserve entry 0 which is used by the PMF */
7573 u8 entry = (BP_E1HVN(bp) + 1)*8;
7574
7575 val = (mac_addr[0] << 8) | mac_addr[1];
7576 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7577
7578 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7579 (mac_addr[4] << 8) | mac_addr[5];
7580 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7581
7582 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7583
7584 } else
7585 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7586
619c5cb6
VZ		 7587 /* Send the request to the MCP */
7588 if (!BP_NOMCP(bp))
7589 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7590 else {
7591 int path = BP_PATH(bp);
7592
7593 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7594 "%d, %d, %d\n",
7595 path, load_count[path][0], load_count[path][1],
7596 load_count[path][2]);
7597 load_count[path][0]--;
7598 load_count[path][1 + port]--;
7599 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7600 "%d, %d, %d\n",
7601 path, load_count[path][0], load_count[path][1],
7602 load_count[path][2]);
7603 if (load_count[path][0] == 0)
7604 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7605 else if (load_count[path][1 + port] == 0)
7606 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7607 else
7608 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7609 }
7610
7611 return reset_code;
7612}
7613
7614/**
7615 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7616 *
7617 * @bp: driver handle
7618 */
7619void bnx2x_send_unload_done(struct bnx2x *bp)
7620{
7621 /* Report UNLOAD_DONE to MCP */
7622 if (!BP_NOMCP(bp))
7623 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7624}
7625
6debea87
DK		 7626static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7627{
7628 int tout = 50;
7629 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7630
7631 if (!bp->port.pmf)
7632 return 0;
7633
7634 /*
7635 * (assumption: No Attention from MCP at this stage)
7636 * PMF probably in the middle of TXdisable/enable transaction
7637 * 1. Sync IRS for default SB
7638 * 2. Sync SP queue - this guarantes us that attention handling started
7639 * 3. Wait, that TXdisable/enable transaction completes
7640 *
7641 * 1+2 guranty that if DCBx attention was scheduled it already changed
7642 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7643 * received complettion for the transaction the state is TX_STOPPED.
7644 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7645 * transaction.
7646 */
7647
7648 /* make sure default SB ISR is done */
7649 if (msix)
7650 synchronize_irq(bp->msix_table[0].vector);
7651 else
7652 synchronize_irq(bp->pdev->irq);
7653
7654 flush_workqueue(bnx2x_wq);
7655
7656 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7657 BNX2X_F_STATE_STARTED && tout--)
7658 msleep(20);
7659
7660 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7661 BNX2X_F_STATE_STARTED) {
7662#ifdef BNX2X_STOP_ON_ERROR
7663 return -EBUSY;
7664#else
7665 /*
7666 * Failed to complete the transaction in a "good way"
7667 * Force both transactions with CLR bit
7668 */
7669 struct bnx2x_func_state_params func_params = {0};
7670
7671 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7672 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7673
7674 func_params.f_obj = &bp->func_obj;
7675 __set_bit(RAMROD_DRV_CLR_ONLY,
7676 &func_params.ramrod_flags);
7677
7678 /* STARTED-->TX_ST0PPED */
7679 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7680 bnx2x_func_state_change(bp, &func_params);
7681
7682 /* TX_ST0PPED-->STARTED */
7683 func_params.cmd = BNX2X_F_CMD_TX_START;
7684 return bnx2x_func_state_change(bp, &func_params);
7685#endif
7686 }
7687
7688 return 0;
7689}
7690
619c5cb6
VZ		 7691void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7692{
7693 int port = BP_PORT(bp);
6383c0b3
AE		 7694 int i, rc = 0;
7695 u8 cos;
619c5cb6
VZ		 7696 struct bnx2x_mcast_ramrod_params rparam = {0};
7697 u32 reset_code;
7698
7699 /* Wait until tx fastpath tasks complete */
7700 for_each_tx_queue(bp, i) {
7701 struct bnx2x_fastpath *fp = &bp->fp[i];
7702
6383c0b3
AE		 7703 for_each_cos_in_tx_queue(fp, cos)
7704 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7705#ifdef BNX2X_STOP_ON_ERROR
7706 if (rc)
7707 return;
7708#endif
7709 }
7710
7711 /* Give HW time to discard old tx messages */
7712 usleep_range(1000, 1000);
7713
7714 /* Clean all ETH MACs */
7715 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7716 if (rc < 0)
7717 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7718
7719 /* Clean up UC list */
7720 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7721 true);
7722 if (rc < 0)
7723 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7724 "%d\n", rc);
7725
7726 /* Disable LLH */
7727 if (!CHIP_IS_E1(bp))
7728 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7729
7730 /* Set "drop all" (stop Rx).
7731 * We need to take a netif_addr_lock() here in order to prevent
7732 * a race between the completion code and this code.
7733 */
7734 netif_addr_lock_bh(bp->dev);
7735 /* Schedule the rx_mode command */
7736 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7737 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7738 else
7739 bnx2x_set_storm_rx_mode(bp);
7740
7741 /* Cleanup multicast configuration */
7742 rparam.mcast_obj = &bp->mcast_obj;
7743 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7744 if (rc < 0)
7745 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7746
7747 netif_addr_unlock_bh(bp->dev);
7748
7749
6debea87
DK		 7750
7751 /*
7752 * Send the UNLOAD_REQUEST to the MCP. This will return if
7753 * this function should perform FUNC, PORT or COMMON HW
7754 * reset.
7755 */
7756 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7757
7758 /*
7759 * (assumption: No Attention from MCP at this stage)
7760 * PMF probably in the middle of TXdisable/enable transaction
7761 */
7762 rc = bnx2x_func_wait_started(bp);
7763 if (rc) {
7764 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7765#ifdef BNX2X_STOP_ON_ERROR
7766 return;
7767#endif
7768 }
7769
34f80b04 7770 /* Close multi and leading connections
619c5cb6
VZ		 7771 * Completions for ramrods are collected in a synchronous way
7772 */
523224a3 7773 for_each_queue(bp, i)
619c5cb6 7774 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 7775#ifdef BNX2X_STOP_ON_ERROR
7776 return;
7777#else
228241eb 7778 goto unload_error;
523224a3 7779#endif
619c5cb6
VZ		 7780 /* If SP settings didn't get completed so far - something
7781 * very wrong has happen.
7782 */
7783 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7784 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 7785
619c5cb6
VZ		 7786#ifndef BNX2X_STOP_ON_ERROR
7787unload_error:
7788#endif
523224a3 7789 rc = bnx2x_func_stop(bp);
da5a662a 7790 if (rc) {
523224a3 7791 BNX2X_ERR("Function stop failed!\n");
da5a662a 7792#ifdef BNX2X_STOP_ON_ERROR
523224a3 7793 return;
523224a3 7794#endif
34f80b04 7795 }
a2fbb9ea 7796
523224a3
DK		 7797 /* Disable HW interrupts, NAPI */
7798 bnx2x_netif_stop(bp, 1);
7799
7800 /* Release IRQs */
d6214d7a 7801 bnx2x_free_irq(bp);
523224a3 7802
a2fbb9ea 7803 /* Reset the chip */
619c5cb6
VZ		 7804 rc = bnx2x_reset_hw(bp, reset_code);
7805 if (rc)
7806 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 7807
356e2385 7808
619c5cb6
VZ		 7809 /* Report UNLOAD_DONE to MCP */
7810 bnx2x_send_unload_done(bp);
72fd0718
VZ		 7811}
7812
9f6c9258 7813void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7814{
7815 u32 val;
7816
7817 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7818
7819 if (CHIP_IS_E1(bp)) {
7820 int port = BP_PORT(bp);
7821 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7822 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7823
7824 val = REG_RD(bp, addr);
7825 val &= ~(0x300);
7826 REG_WR(bp, addr, val);
619c5cb6 7827 } else {
72fd0718
VZ		 7828 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7829 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7830 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7831 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7832 }
7833}
7834
72fd0718
VZ		 7835/* Close gates #2, #3 and #4: */
7836static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7837{
c9ee9206 7838 u32 val;
72fd0718
VZ		 7839
7840 /* Gates #2 and #4a are closed/opened for "not E1" only */
7841 if (!CHIP_IS_E1(bp)) {
7842 /* #4 */
c9ee9206 7843 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 7844 /* #2 */
c9ee9206 7845 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 7846 }
7847
7848 /* #3 */
c9ee9206
VZ		 7849 if (CHIP_IS_E1x(bp)) {
7850 /* Prevent interrupts from HC on both ports */
7851 val = REG_RD(bp, HC_REG_CONFIG_1);
7852 REG_WR(bp, HC_REG_CONFIG_1,
7853 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7854 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7855
7856 val = REG_RD(bp, HC_REG_CONFIG_0);
7857 REG_WR(bp, HC_REG_CONFIG_0,
7858 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7859 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7860 } else {
7861 /* Prevent incomming interrupts in IGU */
7862 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7863
7864 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7865 (!close) ?
7866 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7867 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7868 }
72fd0718
VZ		 7869
7870 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7871 close ? "closing" : "opening");
7872 mmiowb();
7873}
7874
7875#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7876
7877static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7878{
7879 /* Do some magic... */
7880 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7881 *magic_val = val & SHARED_MF_CLP_MAGIC;
7882 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7883}
7884
e8920674
DK		 7885/**
7886 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7887 *
e8920674
DK		 7888 * @bp: driver handle
7889 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7890 */
7891static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7892{
7893 /* Restore the `magic' bit value... */
72fd0718
VZ		 7894 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7895 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7896 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7897}
7898
f85582f8 7899/**
e8920674 7900 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7901 *
e8920674
DK		 7902 * @bp: driver handle
7903 * @magic_val: old value of 'magic' bit.
7904 *
7905 * Takes care of CLP configurations.
72fd0718
VZ		 7906 */
7907static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7908{
7909 u32 shmem;
7910 u32 validity_offset;
7911
7912 DP(NETIF_MSG_HW, "Starting\n");
7913
7914 /* Set `magic' bit in order to save MF config */
7915 if (!CHIP_IS_E1(bp))
7916 bnx2x_clp_reset_prep(bp, magic_val);
7917
7918 /* Get shmem offset */
7919 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7920 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7921
7922 /* Clear validity map flags */
7923 if (shmem > 0)
7924 REG_WR(bp, shmem + validity_offset, 0);
7925}
7926
7927#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7928#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7929
e8920674
DK		 7930/**
7931 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7932 *
e8920674 7933 * @bp: driver handle
72fd0718
VZ		 7934 */
7935static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7936{
7937 /* special handling for emulation and FPGA,
7938 wait 10 times longer */
7939 if (CHIP_REV_IS_SLOW(bp))
7940 msleep(MCP_ONE_TIMEOUT*10);
7941 else
7942 msleep(MCP_ONE_TIMEOUT);
7943}
7944
1b6e2ceb
DK		 7945/*
7946 * initializes bp->common.shmem_base and waits for validity signature to appear
7947 */
7948static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 7949{
1b6e2ceb
DK		 7950 int cnt = 0;
7951 u32 val = 0;
72fd0718 7952
1b6e2ceb
DK		 7953 do {
7954 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7955 if (bp->common.shmem_base) {
7956 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7957 if (val & SHR_MEM_VALIDITY_MB)
7958 return 0;
7959 }
72fd0718 7960
1b6e2ceb 7961 bnx2x_mcp_wait_one(bp);
72fd0718 7962
1b6e2ceb 7963 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 7964
1b6e2ceb 7965 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 7966
1b6e2ceb
DK		 7967 return -ENODEV;
7968}
72fd0718 7969
1b6e2ceb
DK		 7970static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7971{
7972 int rc = bnx2x_init_shmem(bp);
72fd0718 7973
72fd0718
VZ		 7974 /* Restore the `magic' bit value */
7975 if (!CHIP_IS_E1(bp))
7976 bnx2x_clp_reset_done(bp, magic_val);
7977
7978 return rc;
7979}
7980
7981static void bnx2x_pxp_prep(struct bnx2x *bp)
7982{
7983 if (!CHIP_IS_E1(bp)) {
7984 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7985 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 7986 mmiowb();
7987 }
7988}
7989
7990/*
7991 * Reset the whole chip except for:
7992 * - PCIE core
7993 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7994 * one reset bit)
7995 * - IGU
7996 * - MISC (including AEU)
7997 * - GRC
7998 * - RBCN, RBCP
7999 */
c9ee9206 8000static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8001{
8002 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8003 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8004
8005 /*
8006 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8007 * (per chip) blocks.
8008 */
8009 global_bits2 =
8010 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8011 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8012
8736c826 8013 /* Don't reset the following blocks */
72fd0718
VZ		 8014 not_reset_mask1 =
8015 MISC_REGISTERS_RESET_REG_1_RST_HC |
8016 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8017 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8018
8019 not_reset_mask2 =
c9ee9206 8020 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8021 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8022 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8023 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8024 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8025 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8026 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8027 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8028 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8029 MISC_REGISTERS_RESET_REG_2_PGLC;
72fd0718 8030
8736c826
VZ		 8031 /*
8032 * Keep the following blocks in reset:
8033 * - all xxMACs are handled by the bnx2x_link code.
8034 */
8035 stay_reset2 =
8036 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8037 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8038 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8039 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8040 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8041 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8042 MISC_REGISTERS_RESET_REG_2_XMAC |
8043 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8044
8045 /* Full reset masks according to the chip */
72fd0718
VZ		 8046 reset_mask1 = 0xffffffff;
8047
8048 if (CHIP_IS_E1(bp))
8049 reset_mask2 = 0xffff;
8736c826 8050 else if (CHIP_IS_E1H(bp))
72fd0718 8051 reset_mask2 = 0x1ffff;
8736c826
VZ		 8052 else if (CHIP_IS_E2(bp))
8053 reset_mask2 = 0xfffff;
8054 else /* CHIP_IS_E3 */
8055 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8056
8057 /* Don't reset global blocks unless we need to */
8058 if (!global)
8059 reset_mask2 &= ~global_bits2;
8060
8061 /*
8062 * In case of attention in the QM, we need to reset PXP
8063 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8064 * because otherwise QM reset would release 'close the gates' shortly
8065 * before resetting the PXP, then the PSWRQ would send a write
8066 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8067 * read the payload data from PSWWR, but PSWWR would not
8068 * respond. The write queue in PGLUE would stuck, dmae commands
8069 * would not return. Therefore it's important to reset the second
8070 * reset register (containing the
8071 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8072 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8073 * bit).
8074 */
72fd0718
VZ		 8075 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8076 reset_mask2 & (~not_reset_mask2));
8077
c9ee9206
VZ		 8078 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8079 reset_mask1 & (~not_reset_mask1));
8080
72fd0718
VZ		 8081 barrier();
8082 mmiowb();
8083
8736c826
VZ		 8084 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8085 reset_mask2 & (~stay_reset2));
8086
8087 barrier();
8088 mmiowb();
8089
c9ee9206 8090 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8091 mmiowb();
8092}
8093
c9ee9206
VZ		 8094/**
8095 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8096 * It should get cleared in no more than 1s.
8097 *
8098 * @bp: driver handle
8099 *
8100 * It should get cleared in no more than 1s. Returns 0 if
8101 * pending writes bit gets cleared.
8102 */
8103static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8104{
8105 u32 cnt = 1000;
8106 u32 pend_bits = 0;
8107
8108 do {
8109 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8110
8111 if (pend_bits == 0)
8112 break;
8113
8114 usleep_range(1000, 1000);
8115 } while (cnt-- > 0);
8116
8117 if (cnt <= 0) {
8118 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8119 pend_bits);
8120 return -EBUSY;
8121 }
8122
8123 return 0;
8124}
8125
8126static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 8127{
8128 int cnt = 1000;
8129 u32 val = 0;
8130 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8131
8132
8133 /* Empty the Tetris buffer, wait for 1s */
8134 do {
8135 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8136 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8137 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8138 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8139 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8140 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8141 ((port_is_idle_0 & 0x1) == 0x1) &&
8142 ((port_is_idle_1 & 0x1) == 0x1) &&
8143 (pgl_exp_rom2 == 0xffffffff))
8144 break;
c9ee9206 8145 usleep_range(1000, 1000);
72fd0718
VZ		 8146 } while (cnt-- > 0);
8147
8148 if (cnt <= 0) {
8149 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8150 " are still"
8151 " outstanding read requests after 1s!\n");
8152 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8153 " port_is_idle_0=0x%08x,"
8154 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8155 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8156 pgl_exp_rom2);
8157 return -EAGAIN;
8158 }
8159
8160 barrier();
8161
8162 /* Close gates #2, #3 and #4 */
8163 bnx2x_set_234_gates(bp, true);
8164
c9ee9206
VZ		 8165 /* Poll for IGU VQs for 57712 and newer chips */
8166 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8167 return -EAGAIN;
8168
8169
72fd0718
VZ		 8170 /* TBD: Indicate that "process kill" is in progress to MCP */
8171
8172 /* Clear "unprepared" bit */
8173 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8174 barrier();
8175
8176 /* Make sure all is written to the chip before the reset */
8177 mmiowb();
8178
8179 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8180 * PSWHST, GRC and PSWRD Tetris buffer.
8181 */
c9ee9206 8182 usleep_range(1000, 1000);
72fd0718
VZ		 8183
8184 /* Prepare to chip reset: */
8185 /* MCP */
c9ee9206
VZ		 8186 if (global)
8187 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8188
8189 /* PXP */
8190 bnx2x_pxp_prep(bp);
8191 barrier();
8192
8193 /* reset the chip */
c9ee9206 8194 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8195 barrier();
8196
8197 /* Recover after reset: */
8198 /* MCP */
c9ee9206 8199 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8200 return -EAGAIN;
8201
c9ee9206
VZ		 8202 /* TBD: Add resetting the NO_MCP mode DB here */
8203
72fd0718
VZ		 8204 /* PXP */
8205 bnx2x_pxp_prep(bp);
8206
8207 /* Open the gates #2, #3 and #4 */
8208 bnx2x_set_234_gates(bp, false);
8209
8210 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8211 * reset state, re-enable attentions. */
8212
a2fbb9ea
ET		 8213 return 0;
8214}
8215
c9ee9206 8216int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8217{
8218 int rc = 0;
c9ee9206
VZ		 8219 bool global = bnx2x_reset_is_global(bp);
8220
72fd0718 8221 /* Try to recover after the failure */
c9ee9206
VZ		 8222 if (bnx2x_process_kill(bp, global)) {
8223 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8224 "Aii!\n", BP_PATH(bp));
72fd0718
VZ		 8225 rc = -EAGAIN;
8226 goto exit_leader_reset;
8227 }
8228
c9ee9206
VZ		 8229 /*
8230 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8231 * state.
8232 */
72fd0718 8233 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8234 if (global)
8235 bnx2x_clear_reset_global(bp);
72fd0718
VZ		 8236
8237exit_leader_reset:
8238 bp->is_leader = 0;
c9ee9206
VZ		 8239 bnx2x_release_leader_lock(bp);
8240 smp_mb();
72fd0718
VZ		 8241 return rc;
8242}
8243
c9ee9206
VZ		 8244static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8245{
8246 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8247
8248 /* Disconnect this device */
8249 netif_device_detach(bp->dev);
8250
8251 /*
8252 * Block ifup for all function on this engine until "process kill"
8253 * or power cycle.
8254 */
8255 bnx2x_set_reset_in_progress(bp);
8256
8257 /* Shut down the power */
8258 bnx2x_set_power_state(bp, PCI_D3hot);
8259
8260 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8261
8262 smp_mb();
8263}
8264
8265/*
8266 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8267 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8268 * will never be called when netif_running(bp->dev) is false.
8269 */
8270static void bnx2x_parity_recover(struct bnx2x *bp)
8271{
c9ee9206
VZ		 8272 bool global = false;
8273
72fd0718
VZ		 8274 DP(NETIF_MSG_HW, "Handling parity\n");
8275 while (1) {
8276 switch (bp->recovery_state) {
8277 case BNX2X_RECOVERY_INIT:
8278 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
c9ee9206
VZ		 8279 bnx2x_chk_parity_attn(bp, &global, false);
8280
72fd0718 8281 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8282 if (bnx2x_trylock_leader_lock(bp)) {
8283 bnx2x_set_reset_in_progress(bp);
8284 /*
8285 * Check if there is a global attention and if
8286 * there was a global attention, set the global
8287 * reset bit.
8288 */
8289
8290 if (global)
8291 bnx2x_set_reset_global(bp);
8292
72fd0718 8293 bp->is_leader = 1;
c9ee9206 8294 }
72fd0718
VZ		 8295
8296 /* Stop the driver */
8297 /* If interface has been removed - break */
8298 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8299 return;
8300
8301 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206
VZ		 8302
8303 /*
8304 * Reset MCP command sequence number and MCP mail box
8305 * sequence as we are going to reset the MCP.
8306 */
8307 if (global) {
8308 bp->fw_seq = 0;
8309 bp->fw_drv_pulse_wr_seq = 0;
8310 }
8311
8312 /* Ensure "is_leader", MCP command sequence and
8313 * "recovery_state" update values are seen on other
8314 * CPUs.
72fd0718 8315 */
c9ee9206 8316 smp_mb();
72fd0718
VZ		 8317 break;
8318
8319 case BNX2X_RECOVERY_WAIT:
8320 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8321 if (bp->is_leader) {
c9ee9206
VZ		 8322 int other_engine = BP_PATH(bp) ? 0 : 1;
8323 u32 other_load_counter =
8324 bnx2x_get_load_cnt(bp, other_engine);
8325 u32 load_counter =
8326 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8327 global = bnx2x_reset_is_global(bp);
8328
8329 /*
8330 * In case of a parity in a global block, let
8331 * the first leader that performs a
8332 * leader_reset() reset the global blocks in
8333 * order to clear global attentions. Otherwise
8334 * the the gates will remain closed for that
8335 * engine.
8336 */
8337 if (load_counter ||
8338 (global && other_load_counter)) {
72fd0718
VZ		 8339 /* Wait until all other functions get
8340 * down.
8341 */
7be08a72 8342 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8343 HZ/10);
8344 return;
8345 } else {
8346 /* If all other functions got down -
8347 * try to bring the chip back to
8348 * normal. In any case it's an exit
8349 * point for a leader.
8350 */
c9ee9206
VZ		 8351 if (bnx2x_leader_reset(bp)) {
8352 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8353 return;
8354 }
8355
c9ee9206
VZ		 8356 /* If we are here, means that the
8357 * leader has succeeded and doesn't
8358 * want to be a leader any more. Try
8359 * to continue as a none-leader.
8360 */
8361 break;
72fd0718
VZ		 8362 }
8363 } else { /* non-leader */
c9ee9206 8364 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8365 /* Try to get a LEADER_LOCK HW lock as
8366 * long as a former leader may have
8367 * been unloaded by the user or
8368 * released a leadership by another
8369 * reason.
8370 */
c9ee9206 8371 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8372 /* I'm a leader now! Restart a
8373 * switch case.
8374 */
8375 bp->is_leader = 1;
8376 break;
8377 }
8378
7be08a72 8379 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8380 HZ/10);
8381 return;
8382
c9ee9206
VZ		 8383 } else {
8384 /*
8385 * If there was a global attention, wait
8386 * for it to be cleared.
8387 */
8388 if (bnx2x_reset_is_global(bp)) {
8389 schedule_delayed_work(
7be08a72
AE		 8390 &bp->sp_rtnl_task,
8391 HZ/10);
c9ee9206
VZ		 8392 return;
8393 }
8394
8395 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8396 bnx2x_recovery_failed(bp);
8397 else {
8398 bp->recovery_state =
8399 BNX2X_RECOVERY_DONE;
8400 smp_mb();
8401 }
8402
72fd0718
VZ		 8403 return;
8404 }
8405 }
8406 default:
8407 return;
8408 }
8409 }
8410}
8411
8412/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8413 * scheduled on a general queue in order to prevent a dead lock.
8414 */
7be08a72 8415static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8416{
7be08a72 8417 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8418
8419 rtnl_lock();
8420
8421 if (!netif_running(bp->dev))
7be08a72
AE		 8422 goto sp_rtnl_exit;
8423
8424 /* if stop on error is defined no recovery flows should be executed */
8425#ifdef BNX2X_STOP_ON_ERROR
8426 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8427 "so reset not done to allow debug dump,\n"
8428 "you will need to reboot when done\n");
b1fb8740 8429 goto sp_rtnl_not_reset;
7be08a72 8430#endif
34f80b04 8431
7be08a72
AE		 8432 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8433 /*
b1fb8740
VZ		 8434 * Clear all pending SP commands as we are going to reset the
8435 * function anyway.
7be08a72 8436 */
b1fb8740
VZ		 8437 bp->sp_rtnl_state = 0;
8438 smp_mb();
8439
72fd0718 8440 bnx2x_parity_recover(bp);
b1fb8740
VZ		 8441
8442 goto sp_rtnl_exit;
8443 }
8444
8445 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8446 /*
8447 * Clear all pending SP commands as we are going to reset the
8448 * function anyway.
8449 */
8450 bp->sp_rtnl_state = 0;
8451 smp_mb();
8452
72fd0718
VZ		 8453 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8454 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 8455
8456 goto sp_rtnl_exit;
72fd0718 8457 }
b1fb8740
VZ		 8458#ifdef BNX2X_STOP_ON_ERROR
8459sp_rtnl_not_reset:
8460#endif
8461 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8462 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
34f80b04 8463
7be08a72 8464sp_rtnl_exit:
34f80b04
EG		 8465 rtnl_unlock();
8466}
8467
a2fbb9ea
ET		 8468/* end of nic load/unload */
8469
3deb8167
YR		 8470static void bnx2x_period_task(struct work_struct *work)
8471{
8472 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8473
8474 if (!netif_running(bp->dev))
8475 goto period_task_exit;
8476
8477 if (CHIP_REV_IS_SLOW(bp)) {
8478 BNX2X_ERR("period task called on emulation, ignoring\n");
8479 goto period_task_exit;
8480 }
8481
8482 bnx2x_acquire_phy_lock(bp);
8483 /*
8484 * The barrier is needed to ensure the ordering between the writing to
8485 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8486 * the reading here.
8487 */
8488 smp_mb();
8489 if (bp->port.pmf) {
8490 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8491
8492 /* Re-queue task in 1 sec */
8493 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8494 }
8495
8496 bnx2x_release_phy_lock(bp);
8497period_task_exit:
8498 return;
8499}
8500
a2fbb9ea
ET		 8501/*
8502 * Init service functions
8503 */
8504
8d96286a 8505static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8506{
8507 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8508 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8509 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8510}
8511
f2e0899f 8512static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8513{
f2e0899f 8514 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8515
8516 /* Flush all outstanding writes */
8517 mmiowb();
8518
8519 /* Pretend to be function 0 */
8520 REG_WR(bp, reg, 0);
f2e0899f 8521 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8522
8523 /* From now we are in the "like-E1" mode */
8524 bnx2x_int_disable(bp);
8525
8526 /* Flush all outstanding writes */
8527 mmiowb();
8528
f2e0899f
DK		 8529 /* Restore the original function */
8530 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8531 REG_RD(bp, reg);
f1ef27ef
EG		 8532}
8533
f2e0899f 8534static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8535{
f2e0899f 8536 if (CHIP_IS_E1(bp))
f1ef27ef 8537 bnx2x_int_disable(bp);
f2e0899f
DK		 8538 else
8539 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8540}
8541
34f80b04
EG		 8542static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8543{
8544 u32 val;
8545
8546 /* Check if there is any driver already loaded */
8547 val = REG_RD(bp, MISC_REG_UNPREPARED);
8548 if (val == 0x1) {
8549 /* Check if it is the UNDI driver
8550 * UNDI driver initializes CID offset for normal bell to 0x7
8551 */
4a37fb66 8552 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 8553 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8554 if (val == 0x7) {
8555 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 8556 /* save our pf_num */
8557 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 8558 int port;
8559 u32 swap_en, swap_val, value;
34f80b04 8560
b4661739
EG		 8561 /* clear the UNDI indication */
8562 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8563
34f80b04
EG		 8564 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8565
8566 /* try unload UNDI on port 0 */
f2e0899f 8567 bp->pf_num = 0;
da5a662a 8568 bp->fw_seq =
f2e0899f 8569 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8570 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 8571 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8572
8573 /* if UNDI is loaded on the other port */
8574 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8575
da5a662a 8576 /* send "DONE" for previous unload */
a22f0788
YR		 8577 bnx2x_fw_command(bp,
8578 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8579
8580 /* unload UNDI on port 1 */
f2e0899f 8581 bp->pf_num = 1;
da5a662a 8582 bp->fw_seq =
f2e0899f 8583 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 8584 DRV_MSG_SEQ_NUMBER_MASK);
8585 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8586
a22f0788 8587 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8588 }
8589
b4661739
EG		 8590 /* now it's safe to release the lock */
8591 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8592
f2e0899f 8593 bnx2x_undi_int_disable(bp);
619c5cb6 8594 port = BP_PORT(bp);
da5a662a
VZ		 8595
8596 /* close input traffic and wait for it */
8597 /* Do not rcv packets to BRB */
619c5cb6
VZ		 8598 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8599 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 8600 /* Do not direct rcv packets that are not for MCP to
8601 * the BRB */
619c5cb6
VZ		 8602 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8603 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 8604 /* clear AEU */
619c5cb6
VZ		 8605 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8606 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 8607 msleep(10);
8608
8609 /* save NIG port swap info */
8610 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8611 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 8612 /* reset device */
8613 REG_WR(bp,
8614 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 8615 0xd3ffffff);
619c5cb6
VZ		 8616
8617 value = 0x1400;
8618 if (CHIP_IS_E3(bp)) {
8619 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8620 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8621 }
8622
34f80b04
EG		 8623 REG_WR(bp,
8624 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 8625 value);
8626
da5a662a
VZ		 8627 /* take the NIG out of reset and restore swap values */
8628 REG_WR(bp,
8629 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8630 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8631 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8632 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8633
8634 /* send unload done to the MCP */
a22f0788 8635 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8636
8637 /* restore our func and fw_seq */
f2e0899f 8638 bp->pf_num = orig_pf_num;
da5a662a 8639 bp->fw_seq =
f2e0899f 8640 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8641 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 8642 } else
8643 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 8644 }
8645}
8646
8647static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8648{
8649 u32 val, val2, val3, val4, id;
72ce58c3 8650 u16 pmc;
34f80b04
EG		 8651
8652 /* Get the chip revision id and number. */
8653 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8654 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8655 id = ((val & 0xffff) << 16);
8656 val = REG_RD(bp, MISC_REG_CHIP_REV);
8657 id |= ((val & 0xf) << 12);
8658 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8659 id |= ((val & 0xff) << 4);
5a40e08e 8660 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 8661 id |= (val & 0xf);
8662 bp->common.chip_id = id;
523224a3
DK		 8663
8664 /* Set doorbell size */
8665 bp->db_size = (1 << BNX2X_DB_SHIFT);
8666
619c5cb6 8667 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8668 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8669 if ((val & 1) == 0)
8670 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8671 else
8672 val = (val >> 1) & 1;
8673 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8674 "2_PORT_MODE");
8675 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8676 CHIP_2_PORT_MODE;
8677
8678 if (CHIP_MODE_IS_4_PORT(bp))
8679 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8680 else
8681 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8682 } else {
8683 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8684 bp->pfid = bp->pf_num; /* 0..7 */
8685 }
8686
f2e0899f
DK		 8687 bp->link_params.chip_id = bp->common.chip_id;
8688 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 8689
1c06328c
EG		 8690 val = (REG_RD(bp, 0x2874) & 0x55);
8691 if ((bp->common.chip_id & 0x1) ||
8692 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8693 bp->flags |= ONE_PORT_FLAG;
8694 BNX2X_DEV_INFO("single port device\n");
8695 }
8696
34f80b04 8697 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 8698 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 8699 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8700 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8701 bp->common.flash_size, bp->common.flash_size);
8702
1b6e2ceb
DK		 8703 bnx2x_init_shmem(bp);
8704
619c5cb6
VZ		 8705
8706
f2e0899f
DK		 8707 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8708 MISC_REG_GENERIC_CR_1 :
8709 MISC_REG_GENERIC_CR_0));
1b6e2ceb 8710
34f80b04 8711 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 8712 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 8713 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8714 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 8715
f2e0899f 8716 if (!bp->common.shmem_base) {
34f80b04
EG		 8717 BNX2X_DEV_INFO("MCP not active\n");
8718 bp->flags |= NO_MCP_FLAG;
8719 return;
8720 }
8721
34f80b04 8722 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 8723 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 8724
8725 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8726 SHARED_HW_CFG_LED_MODE_MASK) >>
8727 SHARED_HW_CFG_LED_MODE_SHIFT);
8728
c2c8b03e
EG		 8729 bp->link_params.feature_config_flags = 0;
8730 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8731 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8732 bp->link_params.feature_config_flags |=
8733 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8734 else
8735 bp->link_params.feature_config_flags &=
8736 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8737
34f80b04
EG		 8738 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8739 bp->common.bc_ver = val;
8740 BNX2X_DEV_INFO("bc_ver %X\n", val);
8741 if (val < BNX2X_BC_VER) {
8742 /* for now only warn
8743 * later we might need to enforce this */
f2e0899f
DK		 8744 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8745 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 8746 }
4d295db0 8747 bp->link_params.feature_config_flags |=
a22f0788 8748 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 8749 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8750
a22f0788
YR		 8751 bp->link_params.feature_config_flags |=
8752 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8753 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 8754
85242eea
YR		 8755 bp->link_params.feature_config_flags |=
8756 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8757 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8758
f9a3ebbe
DK		 8759 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8760 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8761
72ce58c3 8762 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 8763 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 8764
8765 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8766 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8767 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8768 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8769
cdaa7cb8
VZ		 8770 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8771 val, val2, val3, val4);
34f80b04
EG		 8772}
8773
f2e0899f
DK		 8774#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8775#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8776
8777static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8778{
8779 int pfid = BP_FUNC(bp);
8780 int vn = BP_E1HVN(bp);
8781 int igu_sb_id;
8782 u32 val;
6383c0b3 8783 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 8784
8785 bp->igu_base_sb = 0xff;
f2e0899f 8786 if (CHIP_INT_MODE_IS_BC(bp)) {
6383c0b3 8787 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 8788 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8789 FP_SB_MAX_E1x;
8790
8791 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8792 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8793
8794 return;
8795 }
8796
8797 /* IGU in normal mode - read CAM */
8798 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8799 igu_sb_id++) {
8800 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8801 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8802 continue;
8803 fid = IGU_FID(val);
8804 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8805 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8806 continue;
8807 if (IGU_VEC(val) == 0)
8808 /* default status block */
8809 bp->igu_dsb_id = igu_sb_id;
8810 else {
8811 if (bp->igu_base_sb == 0xff)
8812 bp->igu_base_sb = igu_sb_id;
6383c0b3 8813 igu_sb_cnt++;
f2e0899f
DK		 8814 }
8815 }
8816 }
619c5cb6 8817
6383c0b3
AE		 8818#ifdef CONFIG_PCI_MSI
8819 /*
8820 * It's expected that number of CAM entries for this functions is equal
8821 * to the number evaluated based on the MSI-X table size. We want a
8822 * harsh warning if these values are different!
619c5cb6 8823 */
6383c0b3
AE		 8824 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8825#endif
619c5cb6 8826
6383c0b3 8827 if (igu_sb_cnt == 0)
f2e0899f
DK		 8828 BNX2X_ERR("CAM configuration error\n");
8829}
8830
34f80b04
EG		 8831static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8832 u32 switch_cfg)
a2fbb9ea 8833{
a22f0788
YR		 8834 int cfg_size = 0, idx, port = BP_PORT(bp);
8835
8836 /* Aggregation of supported attributes of all external phys */
8837 bp->port.supported[0] = 0;
8838 bp->port.supported[1] = 0;
b7737c9b
YR		 8839 switch (bp->link_params.num_phys) {
8840 case 1:
a22f0788
YR		 8841 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8842 cfg_size = 1;
8843 break;
b7737c9b 8844 case 2:
a22f0788
YR		 8845 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8846 cfg_size = 1;
8847 break;
8848 case 3:
8849 if (bp->link_params.multi_phy_config &
8850 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8851 bp->port.supported[1] =
8852 bp->link_params.phy[EXT_PHY1].supported;
8853 bp->port.supported[0] =
8854 bp->link_params.phy[EXT_PHY2].supported;
8855 } else {
8856 bp->port.supported[0] =
8857 bp->link_params.phy[EXT_PHY1].supported;
8858 bp->port.supported[1] =
8859 bp->link_params.phy[EXT_PHY2].supported;
8860 }
8861 cfg_size = 2;
8862 break;
b7737c9b 8863 }
a2fbb9ea 8864
a22f0788 8865 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8866 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8867 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8868 SHMEM_RD(bp,
a22f0788
YR		 8869 dev_info.port_hw_config[port].external_phy_config),
8870 SHMEM_RD(bp,
8871 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8872 return;
f85582f8 8873 }
a2fbb9ea 8874
619c5cb6
VZ		 8875 if (CHIP_IS_E3(bp))
8876 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8877 else {
8878 switch (switch_cfg) {
8879 case SWITCH_CFG_1G:
8880 bp->port.phy_addr = REG_RD(
8881 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8882 break;
8883 case SWITCH_CFG_10G:
8884 bp->port.phy_addr = REG_RD(
8885 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8886 break;
8887 default:
8888 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8889 bp->port.link_config[0]);
8890 return;
8891 }
a2fbb9ea 8892 }
619c5cb6 8893 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 8894 /* mask what we support according to speed_cap_mask per configuration */
8895 for (idx = 0; idx < cfg_size; idx++) {
8896 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8897 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8898 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8899
a22f0788 8900 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8901 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8902 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8903
a22f0788 8904 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8905 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8906 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8907
a22f0788 8908 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8909 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8910 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8911
a22f0788 8912 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8913 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8914 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8915 SUPPORTED_1000baseT_Full);
a2fbb9ea 8916
a22f0788 8917 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8918 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8919 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8920
a22f0788 8921 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8922 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8923 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8924
8925 }
a2fbb9ea 8926
a22f0788
YR		 8927 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8928 bp->port.supported[1]);
a2fbb9ea
ET		 8929}
8930
34f80b04 8931static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8932{
a22f0788
YR		 8933 u32 link_config, idx, cfg_size = 0;
8934 bp->port.advertising[0] = 0;
8935 bp->port.advertising[1] = 0;
8936 switch (bp->link_params.num_phys) {
8937 case 1:
8938 case 2:
8939 cfg_size = 1;
8940 break;
8941 case 3:
8942 cfg_size = 2;
8943 break;
8944 }
8945 for (idx = 0; idx < cfg_size; idx++) {
8946 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8947 link_config = bp->port.link_config[idx];
8948 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8949 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8950 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8951 bp->link_params.req_line_speed[idx] =
8952 SPEED_AUTO_NEG;
8953 bp->port.advertising[idx] |=
8954 bp->port.supported[idx];
f85582f8
DK		 8955 } else {
8956 /* force 10G, no AN */
a22f0788
YR		 8957 bp->link_params.req_line_speed[idx] =
8958 SPEED_10000;
8959 bp->port.advertising[idx] |=
8960 (ADVERTISED_10000baseT_Full |
f85582f8 8961 ADVERTISED_FIBRE);
a22f0788 8962 continue;
f85582f8
DK		 8963 }
8964 break;
a2fbb9ea 8965
f85582f8 8966 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8967 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8968 bp->link_params.req_line_speed[idx] =
8969 SPEED_10;
8970 bp->port.advertising[idx] |=
8971 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8972 ADVERTISED_TP);
8973 } else {
754a2f52 8974 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8975 "Invalid link_config 0x%x"
8976 " speed_cap_mask 0x%x\n",
8977 link_config,
a22f0788 8978 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8979 return;
8980 }
8981 break;
a2fbb9ea 8982
f85582f8 8983 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8984 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8985 bp->link_params.req_line_speed[idx] =
8986 SPEED_10;
8987 bp->link_params.req_duplex[idx] =
8988 DUPLEX_HALF;
8989 bp->port.advertising[idx] |=
8990 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8991 ADVERTISED_TP);
8992 } else {
754a2f52 8993 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8994 "Invalid link_config 0x%x"
8995 " speed_cap_mask 0x%x\n",
8996 link_config,
8997 bp->link_params.speed_cap_mask[idx]);
8998 return;
8999 }
9000 break;
a2fbb9ea 9001
f85582f8
DK		 9002 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9003 if (bp->port.supported[idx] &
9004 SUPPORTED_100baseT_Full) {
a22f0788
YR		 9005 bp->link_params.req_line_speed[idx] =
9006 SPEED_100;
9007 bp->port.advertising[idx] |=
9008 (ADVERTISED_100baseT_Full |
f85582f8
DK		 9009 ADVERTISED_TP);
9010 } else {
754a2f52 9011 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9012 "Invalid link_config 0x%x"
9013 " speed_cap_mask 0x%x\n",
9014 link_config,
9015 bp->link_params.speed_cap_mask[idx]);
9016 return;
9017 }
9018 break;
a2fbb9ea 9019
f85582f8
DK		 9020 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9021 if (bp->port.supported[idx] &
9022 SUPPORTED_100baseT_Half) {
9023 bp->link_params.req_line_speed[idx] =
9024 SPEED_100;
9025 bp->link_params.req_duplex[idx] =
9026 DUPLEX_HALF;
a22f0788
YR		 9027 bp->port.advertising[idx] |=
9028 (ADVERTISED_100baseT_Half |
f85582f8
DK		 9029 ADVERTISED_TP);
9030 } else {
754a2f52 9031 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9032 "Invalid link_config 0x%x"
9033 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9034 link_config,
9035 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9036 return;
9037 }
9038 break;
a2fbb9ea 9039
f85582f8 9040 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 9041 if (bp->port.supported[idx] &
9042 SUPPORTED_1000baseT_Full) {
9043 bp->link_params.req_line_speed[idx] =
9044 SPEED_1000;
9045 bp->port.advertising[idx] |=
9046 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 9047 ADVERTISED_TP);
9048 } else {
754a2f52 9049 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9050 "Invalid link_config 0x%x"
9051 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9052 link_config,
9053 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9054 return;
9055 }
9056 break;
a2fbb9ea 9057
f85582f8 9058 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 9059 if (bp->port.supported[idx] &
9060 SUPPORTED_2500baseX_Full) {
9061 bp->link_params.req_line_speed[idx] =
9062 SPEED_2500;
9063 bp->port.advertising[idx] |=
9064 (ADVERTISED_2500baseX_Full |
34f80b04 9065 ADVERTISED_TP);
f85582f8 9066 } else {
754a2f52 9067 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9068 "Invalid link_config 0x%x"
9069 " speed_cap_mask 0x%x\n",
a22f0788 9070 link_config,
f85582f8
DK		 9071 bp->link_params.speed_cap_mask[idx]);
9072 return;
9073 }
9074 break;
a2fbb9ea 9075
f85582f8 9076 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 9077 if (bp->port.supported[idx] &
9078 SUPPORTED_10000baseT_Full) {
9079 bp->link_params.req_line_speed[idx] =
9080 SPEED_10000;
9081 bp->port.advertising[idx] |=
9082 (ADVERTISED_10000baseT_Full |
34f80b04 9083 ADVERTISED_FIBRE);
f85582f8 9084 } else {
754a2f52 9085 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9086 "Invalid link_config 0x%x"
9087 " speed_cap_mask 0x%x\n",
a22f0788 9088 link_config,
f85582f8
DK		 9089 bp->link_params.speed_cap_mask[idx]);
9090 return;
9091 }
9092 break;
3c9ada22
YR		 9093 case PORT_FEATURE_LINK_SPEED_20G:
9094 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 9095
3c9ada22 9096 break;
f85582f8 9097 default:
754a2f52
DK		 9098 BNX2X_ERR("NVRAM config error. "
9099 "BAD link speed link_config 0x%x\n",
9100 link_config);
f85582f8
DK		 9101 bp->link_params.req_line_speed[idx] =
9102 SPEED_AUTO_NEG;
9103 bp->port.advertising[idx] =
9104 bp->port.supported[idx];
9105 break;
9106 }
a2fbb9ea 9107
a22f0788 9108 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 9109 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 9110 if ((bp->link_params.req_flow_ctrl[idx] ==
9111 BNX2X_FLOW_CTRL_AUTO) &&
9112 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9113 bp->link_params.req_flow_ctrl[idx] =
9114 BNX2X_FLOW_CTRL_NONE;
9115 }
a2fbb9ea 9116
a22f0788
YR		 9117 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9118 " 0x%x advertising 0x%x\n",
9119 bp->link_params.req_line_speed[idx],
9120 bp->link_params.req_duplex[idx],
9121 bp->link_params.req_flow_ctrl[idx],
9122 bp->port.advertising[idx]);
9123 }
a2fbb9ea
ET		 9124}
9125
e665bfda
MC		 9126static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9127{
9128 mac_hi = cpu_to_be16(mac_hi);
9129 mac_lo = cpu_to_be32(mac_lo);
9130 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9131 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9132}
9133
34f80b04 9134static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 9135{
34f80b04 9136 int port = BP_PORT(bp);
589abe3a 9137 u32 config;
6f38ad93 9138 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 9139
c18487ee 9140 bp->link_params.bp = bp;
34f80b04 9141 bp->link_params.port = port;
c18487ee 9142
c18487ee 9143 bp->link_params.lane_config =
a2fbb9ea 9144 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 9145
a22f0788 9146 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 9147 SHMEM_RD(bp,
9148 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 9149 bp->link_params.speed_cap_mask[1] =
9150 SHMEM_RD(bp,
9151 dev_info.port_hw_config[port].speed_capability_mask2);
9152 bp->port.link_config[0] =
a2fbb9ea
ET		 9153 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9154
a22f0788
YR		 9155 bp->port.link_config[1] =
9156 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 9157
a22f0788
YR		 9158 bp->link_params.multi_phy_config =
9159 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 9160 /* If the device is capable of WoL, set the default state according
9161 * to the HW
9162 */
4d295db0 9163 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 9164 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9165 (config & PORT_FEATURE_WOL_ENABLED));
9166
f85582f8 9167 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 9168 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 9169 bp->link_params.lane_config,
a22f0788
YR		 9170 bp->link_params.speed_cap_mask[0],
9171 bp->port.link_config[0]);
a2fbb9ea 9172
a22f0788 9173 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 9174 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 9175 bnx2x_phy_probe(&bp->link_params);
c18487ee 9176 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 9177
9178 bnx2x_link_settings_requested(bp);
9179
01cd4528
EG		 9180 /*
9181 * If connected directly, work with the internal PHY, otherwise, work
9182 * with the external PHY
9183 */
b7737c9b
YR		 9184 ext_phy_config =
9185 SHMEM_RD(bp,
9186 dev_info.port_hw_config[port].external_phy_config);
9187 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 9188 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 9189 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 9190
9191 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9192 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9193 bp->mdio.prtad =
b7737c9b 9194 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 9195
9196 /*
9197 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9198 * In MF mode, it is set to cover self test cases
9199 */
9200 if (IS_MF(bp))
9201 bp->port.need_hw_lock = 1;
9202 else
9203 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9204 bp->common.shmem_base,
9205 bp->common.shmem2_base);
0793f83f 9206}
01cd4528 9207
2ba45142
VZ		 9208#ifdef BCM_CNIC
9209static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9210{
bf61ee14
VZ		 9211 int port = BP_PORT(bp);
9212 int func = BP_ABS_FUNC(bp);
9213
2ba45142 9214 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9215 drv_lic_key[port].max_iscsi_conn);
2ba45142 9216 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9217 drv_lic_key[port].max_fcoe_conn);
2ba45142
VZ		 9218
9219 /* Get the number of maximum allowed iSCSI and FCoE connections */
9220 bp->cnic_eth_dev.max_iscsi_conn =
9221 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9222 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9223
9224 bp->cnic_eth_dev.max_fcoe_conn =
9225 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9226 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9227
bf61ee14
VZ		 9228 /* Read the WWN: */
9229 if (!IS_MF(bp)) {
9230 /* Port info */
9231 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9232 SHMEM_RD(bp,
9233 dev_info.port_hw_config[port].
9234 fcoe_wwn_port_name_upper);
9235 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9236 SHMEM_RD(bp,
9237 dev_info.port_hw_config[port].
9238 fcoe_wwn_port_name_lower);
9239
9240 /* Node info */
9241 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9242 SHMEM_RD(bp,
9243 dev_info.port_hw_config[port].
9244 fcoe_wwn_node_name_upper);
9245 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9246 SHMEM_RD(bp,
9247 dev_info.port_hw_config[port].
9248 fcoe_wwn_node_name_lower);
9249 } else if (!IS_MF_SD(bp)) {
9250 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9251
9252 /*
9253 * Read the WWN info only if the FCoE feature is enabled for
9254 * this function.
9255 */
9256 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9257 /* Port info */
9258 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9259 MF_CFG_RD(bp, func_ext_config[func].
9260 fcoe_wwn_port_name_upper);
9261 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9262 MF_CFG_RD(bp, func_ext_config[func].
9263 fcoe_wwn_port_name_lower);
9264
9265 /* Node info */
9266 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9267 MF_CFG_RD(bp, func_ext_config[func].
9268 fcoe_wwn_node_name_upper);
9269 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9270 MF_CFG_RD(bp, func_ext_config[func].
9271 fcoe_wwn_node_name_lower);
9272 }
9273 }
9274
2ba45142
VZ		 9275 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9276 bp->cnic_eth_dev.max_iscsi_conn,
9277 bp->cnic_eth_dev.max_fcoe_conn);
9278
bf61ee14
VZ		 9279 /*
9280 * If maximum allowed number of connections is zero -
2ba45142
VZ		 9281 * disable the feature.
9282 */
9283 if (!bp->cnic_eth_dev.max_iscsi_conn)
9284 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9285
9286 if (!bp->cnic_eth_dev.max_fcoe_conn)
9287 bp->flags |= NO_FCOE_FLAG;
9288}
9289#endif
9290
0793f83f
DK		 9291static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9292{
9293 u32 val, val2;
9294 int func = BP_ABS_FUNC(bp);
9295 int port = BP_PORT(bp);
2ba45142
VZ		 9296#ifdef BCM_CNIC
9297 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9298 u8 *fip_mac = bp->fip_mac;
9299#endif
0793f83f 9300
619c5cb6
VZ		 9301 /* Zero primary MAC configuration */
9302 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9303
0793f83f
DK		 9304 if (BP_NOMCP(bp)) {
9305 BNX2X_ERROR("warning: random MAC workaround active\n");
9306 random_ether_addr(bp->dev->dev_addr);
9307 } else if (IS_MF(bp)) {
9308 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9309 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9310 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9311 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9312 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9313
9314#ifdef BCM_CNIC
2ba45142
VZ		 9315 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9316 * FCoE MAC then the appropriate feature should be disabled.
9317 */
0793f83f
DK		 9318 if (IS_MF_SI(bp)) {
9319 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9320 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9321 val2 = MF_CFG_RD(bp, func_ext_config[func].
9322 iscsi_mac_addr_upper);
9323 val = MF_CFG_RD(bp, func_ext_config[func].
9324 iscsi_mac_addr_lower);
2ba45142 9325 bnx2x_set_mac_buf(iscsi_mac, val, val2);
619c5cb6
VZ		 9326 BNX2X_DEV_INFO("Read iSCSI MAC: "
9327 BNX2X_MAC_FMT"\n",
9328 BNX2X_MAC_PRN_LIST(iscsi_mac));
2ba45142
VZ		 9329 } else
9330 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9331
9332 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9333 val2 = MF_CFG_RD(bp, func_ext_config[func].
9334 fcoe_mac_addr_upper);
9335 val = MF_CFG_RD(bp, func_ext_config[func].
9336 fcoe_mac_addr_lower);
2ba45142 9337 bnx2x_set_mac_buf(fip_mac, val, val2);
619c5cb6
VZ		 9338 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9339 BNX2X_MAC_FMT"\n",
9340 BNX2X_MAC_PRN_LIST(fip_mac));
2ba45142 9341
2ba45142
VZ		 9342 } else
9343 bp->flags |= NO_FCOE_FLAG;
0793f83f 9344 }
37b091ba 9345#endif
0793f83f
DK		 9346 } else {
9347 /* in SF read MACs from port configuration */
9348 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9349 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9350 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9351
9352#ifdef BCM_CNIC
9353 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9354 iscsi_mac_upper);
9355 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9356 iscsi_mac_lower);
2ba45142 9357 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 9358
9359 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9360 fcoe_fip_mac_upper);
9361 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9362 fcoe_fip_mac_lower);
9363 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 9364#endif
9365 }
9366
9367 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9368 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9369
ec6ba945 9370#ifdef BCM_CNIC
c03bd39c
VZ		 9371 /* Set the FCoE MAC in MF_SD mode */
9372 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9373 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
426b9241
DK		 9374
9375 /* Disable iSCSI if MAC configuration is
9376 * invalid.
9377 */
9378 if (!is_valid_ether_addr(iscsi_mac)) {
9379 bp->flags |= NO_ISCSI_FLAG;
9380 memset(iscsi_mac, 0, ETH_ALEN);
9381 }
9382
9383 /* Disable FCoE if MAC configuration is
9384 * invalid.
9385 */
9386 if (!is_valid_ether_addr(fip_mac)) {
9387 bp->flags |= NO_FCOE_FLAG;
9388 memset(bp->fip_mac, 0, ETH_ALEN);
9389 }
ec6ba945 9390#endif
619c5cb6
VZ		 9391
9392 if (!is_valid_ether_addr(bp->dev->dev_addr))
9393 dev_err(&bp->pdev->dev,
9394 "bad Ethernet MAC address configuration: "
9395 BNX2X_MAC_FMT", change it manually before bringing up "
9396 "the appropriate network interface\n",
9397 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
34f80b04
EG		 9398}
9399
9400static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9401{
0793f83f 9402 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9403 int vn;
0793f83f 9404 u32 val = 0;
34f80b04 9405 int rc = 0;
a2fbb9ea 9406
34f80b04 9407 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9408
6383c0b3
AE		 9409 /*
9410 * initialize IGU parameters
9411 */
f2e0899f
DK		 9412 if (CHIP_IS_E1x(bp)) {
9413 bp->common.int_block = INT_BLOCK_HC;
9414
9415 bp->igu_dsb_id = DEF_SB_IGU_ID;
9416 bp->igu_base_sb = 0;
f2e0899f
DK		 9417 } else {
9418 bp->common.int_block = INT_BLOCK_IGU;
9419 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9420
9421 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9422 int tout = 5000;
9423
9424 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9425
9426 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9427 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9428 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9429
9430 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9431 tout--;
9432 usleep_range(1000, 1000);
9433 }
9434
9435 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9436 dev_err(&bp->pdev->dev,
9437 "FORCING Normal Mode failed!!!\n");
9438 return -EPERM;
9439 }
9440 }
9441
f2e0899f 9442 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9443 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9444 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9445 } else
619c5cb6 9446 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9447
f2e0899f
DK		 9448 bnx2x_get_igu_cam_info(bp);
9449
9450 }
619c5cb6
VZ		 9451
9452 /*
9453 * set base FW non-default (fast path) status block id, this value is
9454 * used to initialize the fw_sb_id saved on the fp/queue structure to
9455 * determine the id used by the FW.
9456 */
9457 if (CHIP_IS_E1x(bp))
9458 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9459 else /*
9460 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9461 * the same queue are indicated on the same IGU SB). So we prefer
9462 * FW and IGU SBs to be the same value.
9463 */
9464 bp->base_fw_ndsb = bp->igu_base_sb;
9465
9466 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9467 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9468 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9469
9470 /*
9471 * Initialize MF configuration
9472 */
523224a3 9473
fb3bff17
DK		 9474 bp->mf_ov = 0;
9475 bp->mf_mode = 0;
f2e0899f 9476 vn = BP_E1HVN(bp);
0793f83f 9477
f2e0899f 9478 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9479 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9480 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9481 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9482
f2e0899f
DK		 9483 if (SHMEM2_HAS(bp, mf_cfg_addr))
9484 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9485 else
9486 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9487 offsetof(struct shmem_region, func_mb) +
9488 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9489 /*
9490 * get mf configuration:
25985edc 9491 * 1. existence of MF configuration
0793f83f
DK		 9492 * 2. MAC address must be legal (check only upper bytes)
9493 * for Switch-Independent mode;
9494 * OVLAN must be legal for Switch-Dependent mode
9495 * 3. SF_MODE configures specific MF mode
9496 */
9497 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9498 /* get mf configuration */
9499 val = SHMEM_RD(bp,
9500 dev_info.shared_feature_config.config);
9501 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9502
9503 switch (val) {
9504 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9505 val = MF_CFG_RD(bp, func_mf_config[func].
9506 mac_upper);
9507 /* check for legal mac (upper bytes)*/
9508 if (val != 0xffff) {
9509 bp->mf_mode = MULTI_FUNCTION_SI;
9510 bp->mf_config[vn] = MF_CFG_RD(bp,
9511 func_mf_config[func].config);
9512 } else
619c5cb6
VZ		 9513 BNX2X_DEV_INFO("illegal MAC address "
9514 "for SI\n");
0793f83f
DK		 9515 break;
9516 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9517 /* get OV configuration */
9518 val = MF_CFG_RD(bp,
9519 func_mf_config[FUNC_0].e1hov_tag);
9520 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9521
9522 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9523 bp->mf_mode = MULTI_FUNCTION_SD;
9524 bp->mf_config[vn] = MF_CFG_RD(bp,
9525 func_mf_config[func].config);
9526 } else
754a2f52 9527 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9528 break;
9529 default:
9530 /* Unknown configuration: reset mf_config */
9531 bp->mf_config[vn] = 0;
754a2f52 9532 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
0793f83f
DK		 9533 }
9534 }
a2fbb9ea 9535
2691d51d 9536 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9537 IS_MF(bp) ? "multi" : "single");
2691d51d 9538
0793f83f
DK		 9539 switch (bp->mf_mode) {
9540 case MULTI_FUNCTION_SD:
9541 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9542 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 9543 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 9544 bp->mf_ov = val;
619c5cb6
VZ		 9545 bp->path_has_ovlan = true;
9546
9547 BNX2X_DEV_INFO("MF OV for func %d is %d "
9548 "(0x%04x)\n", func, bp->mf_ov,
9549 bp->mf_ov);
2691d51d 9550 } else {
619c5cb6
VZ		 9551 dev_err(&bp->pdev->dev,
9552 "No valid MF OV for func %d, "
9553 "aborting\n", func);
9554 return -EPERM;
34f80b04 9555 }
0793f83f
DK		 9556 break;
9557 case MULTI_FUNCTION_SI:
9558 BNX2X_DEV_INFO("func %d is in MF "
9559 "switch-independent mode\n", func);
9560 break;
9561 default:
9562 if (vn) {
619c5cb6
VZ		 9563 dev_err(&bp->pdev->dev,
9564 "VN %d is in a single function mode, "
9565 "aborting\n", vn);
9566 return -EPERM;
2691d51d 9567 }
0793f83f 9568 break;
34f80b04 9569 }
0793f83f 9570
619c5cb6
VZ		 9571 /* check if other port on the path needs ovlan:
9572 * Since MF configuration is shared between ports
9573 * Possible mixed modes are only
9574 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9575 */
9576 if (CHIP_MODE_IS_4_PORT(bp) &&
9577 !bp->path_has_ovlan &&
9578 !IS_MF(bp) &&
9579 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9580 u8 other_port = !BP_PORT(bp);
9581 u8 other_func = BP_PATH(bp) + 2*other_port;
9582 val = MF_CFG_RD(bp,
9583 func_mf_config[other_func].e1hov_tag);
9584 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9585 bp->path_has_ovlan = true;
9586 }
34f80b04 9587 }
a2fbb9ea 9588
f2e0899f
DK		 9589 /* adjust igu_sb_cnt to MF for E1x */
9590 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 9591 bp->igu_sb_cnt /= E1HVN_MAX;
9592
619c5cb6
VZ		 9593 /* port info */
9594 bnx2x_get_port_hwinfo(bp);
f2e0899f 9595
34f80b04 9596 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9597 bp->fw_seq =
9598 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9599 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 9600 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9601 }
9602
0793f83f
DK		 9603 /* Get MAC addresses */
9604 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 9605
2ba45142
VZ		 9606#ifdef BCM_CNIC
9607 bnx2x_get_cnic_info(bp);
9608#endif
9609
619c5cb6
VZ		 9610 /* Get current FW pulse sequence */
9611 if (!BP_NOMCP(bp)) {
9612 int mb_idx = BP_FW_MB_IDX(bp);
9613
9614 bp->fw_drv_pulse_wr_seq =
9615 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9616 DRV_PULSE_SEQ_MASK);
9617 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9618 }
9619
34f80b04
EG		 9620 return rc;
9621}
9622
34f24c7f
VZ		 9623static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9624{
9625 int cnt, i, block_end, rodi;
9626 char vpd_data[BNX2X_VPD_LEN+1];
9627 char str_id_reg[VENDOR_ID_LEN+1];
9628 char str_id_cap[VENDOR_ID_LEN+1];
9629 u8 len;
9630
9631 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9632 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9633
9634 if (cnt < BNX2X_VPD_LEN)
9635 goto out_not_found;
9636
9637 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9638 PCI_VPD_LRDT_RO_DATA);
9639 if (i < 0)
9640 goto out_not_found;
9641
9642
9643 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9644 pci_vpd_lrdt_size(&vpd_data[i]);
9645
9646 i += PCI_VPD_LRDT_TAG_SIZE;
9647
9648 if (block_end > BNX2X_VPD_LEN)
9649 goto out_not_found;
9650
9651 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9652 PCI_VPD_RO_KEYWORD_MFR_ID);
9653 if (rodi < 0)
9654 goto out_not_found;
9655
9656 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9657
9658 if (len != VENDOR_ID_LEN)
9659 goto out_not_found;
9660
9661 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9662
9663 /* vendor specific info */
9664 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9665 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9666 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9667 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9668
9669 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9670 PCI_VPD_RO_KEYWORD_VENDOR0);
9671 if (rodi >= 0) {
9672 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9673
9674 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9675
9676 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9677 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9678 bp->fw_ver[len] = ' ';
9679 }
9680 }
9681 return;
9682 }
9683out_not_found:
9684 return;
9685}
9686
619c5cb6
VZ		 9687static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9688{
9689 u32 flags = 0;
9690
9691 if (CHIP_REV_IS_FPGA(bp))
9692 SET_FLAGS(flags, MODE_FPGA);
9693 else if (CHIP_REV_IS_EMUL(bp))
9694 SET_FLAGS(flags, MODE_EMUL);
9695 else
9696 SET_FLAGS(flags, MODE_ASIC);
9697
9698 if (CHIP_MODE_IS_4_PORT(bp))
9699 SET_FLAGS(flags, MODE_PORT4);
9700 else
9701 SET_FLAGS(flags, MODE_PORT2);
9702
9703 if (CHIP_IS_E2(bp))
9704 SET_FLAGS(flags, MODE_E2);
9705 else if (CHIP_IS_E3(bp)) {
9706 SET_FLAGS(flags, MODE_E3);
9707 if (CHIP_REV(bp) == CHIP_REV_Ax)
9708 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 9709 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9710 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 9711 }
9712
9713 if (IS_MF(bp)) {
9714 SET_FLAGS(flags, MODE_MF);
9715 switch (bp->mf_mode) {
9716 case MULTI_FUNCTION_SD:
9717 SET_FLAGS(flags, MODE_MF_SD);
9718 break;
9719 case MULTI_FUNCTION_SI:
9720 SET_FLAGS(flags, MODE_MF_SI);
9721 break;
9722 }
9723 } else
9724 SET_FLAGS(flags, MODE_SF);
9725
9726#if defined(__LITTLE_ENDIAN)
9727 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9728#else /*(__BIG_ENDIAN)*/
9729 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9730#endif
9731 INIT_MODE_FLAGS(bp) = flags;
9732}
9733
34f80b04
EG		 9734static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9735{
f2e0899f 9736 int func;
87942b46 9737 int timer_interval;
34f80b04
EG		 9738 int rc;
9739
34f80b04 9740 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 9741 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 9742 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 9743#ifdef BCM_CNIC
9744 mutex_init(&bp->cnic_mutex);
9745#endif
a2fbb9ea 9746
1cf167f2 9747 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 9748 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 9749 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 9750 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 9751 if (rc)
9752 return rc;
34f80b04 9753
619c5cb6
VZ		 9754 bnx2x_set_modes_bitmap(bp);
9755
9756 rc = bnx2x_alloc_mem_bp(bp);
9757 if (rc)
9758 return rc;
523224a3 9759
34f24c7f 9760 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 9761
9762 func = BP_FUNC(bp);
9763
34f80b04
EG		 9764 /* need to reset chip if undi was active */
9765 if (!BP_NOMCP(bp))
9766 bnx2x_undi_unload(bp);
9767
9768 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 9769 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 9770
9771 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 9772 dev_err(&bp->pdev->dev, "MCP disabled, "
9773 "must load devices in order!\n");
34f80b04 9774
555f6c78 9775 bp->multi_mode = multi_mode;
555f6c78 9776
7a9b2557
VZ		 9777 /* Set TPA flags */
9778 if (disable_tpa) {
9779 bp->flags &= ~TPA_ENABLE_FLAG;
9780 bp->dev->features &= ~NETIF_F_LRO;
9781 } else {
9782 bp->flags |= TPA_ENABLE_FLAG;
9783 bp->dev->features |= NETIF_F_LRO;
9784 }
5d7cd496 9785 bp->disable_tpa = disable_tpa;
7a9b2557 9786
a18f5128
EG		 9787 if (CHIP_IS_E1(bp))
9788 bp->dropless_fc = 0;
9789 else
9790 bp->dropless_fc = dropless_fc;
9791
8d5726c4 9792 bp->mrrs = mrrs;
7a9b2557 9793
34f80b04 9794 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 9795
7d323bfd 9796 /* make sure that the numbers are in the right granularity */
523224a3
DK		 9797 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9798 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 9799
87942b46
EG		 9800 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9801 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 9802
9803 init_timer(&bp->timer);
9804 bp->timer.expires = jiffies + bp->current_interval;
9805 bp->timer.data = (unsigned long) bp;
9806 bp->timer.function = bnx2x_timer;
9807
785b9b1a 9808 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 9809 bnx2x_dcbx_init_params(bp);
9810
619c5cb6
VZ		 9811#ifdef BCM_CNIC
9812 if (CHIP_IS_E1x(bp))
9813 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9814 else
9815 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9816#endif
9817
6383c0b3
AE		 9818 /* multiple tx priority */
9819 if (CHIP_IS_E1x(bp))
9820 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9821 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9822 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9823 if (CHIP_IS_E3B0(bp))
9824 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9825
34f80b04 9826 return rc;
a2fbb9ea
ET		 9827}
9828
a2fbb9ea 9829
de0c62db
DK		 9830/****************************************************************************
9831* General service functions
9832****************************************************************************/
a2fbb9ea 9833
619c5cb6
VZ		 9834/*
9835 * net_device service functions
9836 */
9837
bb2a0f7a 9838/* called with rtnl_lock */
a2fbb9ea
ET		 9839static int bnx2x_open(struct net_device *dev)
9840{
9841 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 9842 bool global = false;
9843 int other_engine = BP_PATH(bp) ? 0 : 1;
9844 u32 other_load_counter, load_counter;
a2fbb9ea 9845
6eccabb3
EG		 9846 netif_carrier_off(dev);
9847
a2fbb9ea
ET		 9848 bnx2x_set_power_state(bp, PCI_D0);
9849
c9ee9206
VZ		 9850 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9851 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9852
9853 /*
9854 * If parity had happen during the unload, then attentions
9855 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9856 * want the first function loaded on the current engine to
9857 * complete the recovery.
9858 */
9859 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9860 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 9861 do {
c9ee9206
VZ		 9862 /*
9863 * If there are attentions and they are in a global
9864 * blocks, set the GLOBAL_RESET bit regardless whether
9865 * it will be this function that will complete the
9866 * recovery or not.
72fd0718 9867 */
c9ee9206
VZ		 9868 if (global)
9869 bnx2x_set_reset_global(bp);
72fd0718 9870
c9ee9206
VZ		 9871 /*
9872 * Only the first function on the current engine should
9873 * try to recover in open. In case of attentions in
9874 * global blocks only the first in the chip should try
9875 * to recover.
72fd0718 9876 */
c9ee9206
VZ		 9877 if ((!load_counter &&
9878 (!global || !other_load_counter)) &&
9879 bnx2x_trylock_leader_lock(bp) &&
9880 !bnx2x_leader_reset(bp)) {
9881 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 9882 break;
9883 }
9884
c9ee9206 9885 /* recovery has failed... */
72fd0718 9886 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 9887 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 9888
c9ee9206 9889 netdev_err(bp->dev, "Recovery flow hasn't been properly"
72fd0718
VZ		 9890 " completed yet. Try again later. If u still see this"
9891 " message after a few retries then power cycle is"
c9ee9206 9892 " required.\n");
72fd0718
VZ		 9893
9894 return -EAGAIN;
9895 } while (0);
72fd0718
VZ		 9896
9897 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 9898 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 9899}
9900
bb2a0f7a 9901/* called with rtnl_lock */
a2fbb9ea
ET		 9902static int bnx2x_close(struct net_device *dev)
9903{
a2fbb9ea
ET		 9904 struct bnx2x *bp = netdev_priv(dev);
9905
9906 /* Unload the driver, release IRQs */
bb2a0f7a 9907 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 9908
9909 /* Power off */
d3dbfee0 9910 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 9911
9912 return 0;
9913}
9914
619c5cb6
VZ		 9915static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9916 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 9917{
619c5cb6
VZ		 9918 int mc_count = netdev_mc_count(bp->dev);
9919 struct bnx2x_mcast_list_elem *mc_mac =
9920 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9921 struct netdev_hw_addr *ha;
6e30dd4e 9922
619c5cb6
VZ		 9923 if (!mc_mac)
9924 return -ENOMEM;
6e30dd4e 9925
619c5cb6 9926 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 9927
619c5cb6
VZ		 9928 netdev_for_each_mc_addr(ha, bp->dev) {
9929 mc_mac->mac = bnx2x_mc_addr(ha);
9930 list_add_tail(&mc_mac->link, &p->mcast_list);
9931 mc_mac++;
6e30dd4e 9932 }
619c5cb6
VZ		 9933
9934 p->mcast_list_len = mc_count;
9935
9936 return 0;
6e30dd4e
VZ		 9937}
9938
619c5cb6
VZ		 9939static inline void bnx2x_free_mcast_macs_list(
9940 struct bnx2x_mcast_ramrod_params *p)
9941{
9942 struct bnx2x_mcast_list_elem *mc_mac =
9943 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9944 link);
9945
9946 WARN_ON(!mc_mac);
9947 kfree(mc_mac);
9948}
9949
9950/**
9951 * bnx2x_set_uc_list - configure a new unicast MACs list.
9952 *
9953 * @bp: driver handle
6e30dd4e 9954 *
619c5cb6 9955 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 9956 */
619c5cb6 9957static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 9958{
619c5cb6 9959 int rc;
6e30dd4e 9960 struct net_device *dev = bp->dev;
6e30dd4e 9961 struct netdev_hw_addr *ha;
619c5cb6
VZ		 9962 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9963 unsigned long ramrod_flags = 0;
6e30dd4e 9964
619c5cb6
VZ		 9965 /* First schedule a cleanup up of old configuration */
9966 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9967 if (rc < 0) {
9968 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9969 return rc;
9970 }
6e30dd4e
VZ		 9971
9972 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 9973 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9974 BNX2X_UC_LIST_MAC, &ramrod_flags);
9975 if (rc < 0) {
9976 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9977 rc);
9978 return rc;
6e30dd4e
VZ		 9979 }
9980 }
9981
619c5cb6
VZ		 9982 /* Execute the pending commands */
9983 __set_bit(RAMROD_CONT, &ramrod_flags);
9984 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9985 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 9986}
9987
619c5cb6 9988static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 9989{
619c5cb6
VZ		 9990 struct net_device *dev = bp->dev;
9991 struct bnx2x_mcast_ramrod_params rparam = {0};
9992 int rc = 0;
6e30dd4e 9993
619c5cb6 9994 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 9995
619c5cb6
VZ		 9996 /* first, clear all configured multicast MACs */
9997 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9998 if (rc < 0) {
9999 BNX2X_ERR("Failed to clear multicast "
10000 "configuration: %d\n", rc);
10001 return rc;
10002 }
6e30dd4e 10003
619c5cb6
VZ		 10004 /* then, configure a new MACs list */
10005 if (netdev_mc_count(dev)) {
10006 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10007 if (rc) {
10008 BNX2X_ERR("Failed to create multicast MACs "
10009 "list: %d\n", rc);
10010 return rc;
10011 }
6e30dd4e 10012
619c5cb6
VZ		 10013 /* Now add the new MACs */
10014 rc = bnx2x_config_mcast(bp, &rparam,
10015 BNX2X_MCAST_CMD_ADD);
10016 if (rc < 0)
10017 BNX2X_ERR("Failed to set a new multicast "
10018 "configuration: %d\n", rc);
6e30dd4e 10019
619c5cb6
VZ		 10020 bnx2x_free_mcast_macs_list(&rparam);
10021 }
6e30dd4e 10022
619c5cb6 10023 return rc;
6e30dd4e
VZ		 10024}
10025
6e30dd4e 10026
619c5cb6 10027/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 10028void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 10029{
10030 struct bnx2x *bp = netdev_priv(dev);
10031 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 10032
10033 if (bp->state != BNX2X_STATE_OPEN) {
10034 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10035 return;
10036 }
10037
619c5cb6 10038 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 10039
10040 if (dev->flags & IFF_PROMISC)
10041 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 10042 else if ((dev->flags & IFF_ALLMULTI) ||
10043 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10044 CHIP_IS_E1(bp)))
34f80b04 10045 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 10046 else {
10047 /* some multicasts */
619c5cb6 10048 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 10049 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 10050
619c5cb6 10051 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 10052 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 10053 }
10054
10055 bp->rx_mode = rx_mode;
619c5cb6
VZ		 10056
10057 /* Schedule the rx_mode command */
10058 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10059 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10060 return;
10061 }
10062
34f80b04
EG		 10063 bnx2x_set_storm_rx_mode(bp);
10064}
10065
c18487ee 10066/* called with rtnl_lock */
01cd4528
EG		 10067static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10068 int devad, u16 addr)
a2fbb9ea 10069{
01cd4528
EG		 10070 struct bnx2x *bp = netdev_priv(netdev);
10071 u16 value;
10072 int rc;
a2fbb9ea 10073
01cd4528
EG		 10074 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10075 prtad, devad, addr);
a2fbb9ea 10076
01cd4528
EG		 10077 /* The HW expects different devad if CL22 is used */
10078 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 10079
01cd4528 10080 bnx2x_acquire_phy_lock(bp);
e10bc84d 10081 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 10082 bnx2x_release_phy_lock(bp);
10083 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 10084
01cd4528
EG		 10085 if (!rc)
10086 rc = value;
10087 return rc;
10088}
a2fbb9ea 10089
01cd4528
EG		 10090/* called with rtnl_lock */
10091static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10092 u16 addr, u16 value)
10093{
10094 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 10095 int rc;
10096
10097 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10098 " value 0x%x\n", prtad, devad, addr, value);
10099
01cd4528
EG		 10100 /* The HW expects different devad if CL22 is used */
10101 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 10102
01cd4528 10103 bnx2x_acquire_phy_lock(bp);
e10bc84d 10104 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 10105 bnx2x_release_phy_lock(bp);
10106 return rc;
10107}
c18487ee 10108
01cd4528
EG		 10109/* called with rtnl_lock */
10110static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10111{
10112 struct bnx2x *bp = netdev_priv(dev);
10113 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 10114
01cd4528
EG		 10115 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10116 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 10117
01cd4528
EG		 10118 if (!netif_running(dev))
10119 return -EAGAIN;
10120
10121 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 10122}
10123
257ddbda 10124#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 10125static void poll_bnx2x(struct net_device *dev)
10126{
10127 struct bnx2x *bp = netdev_priv(dev);
10128
10129 disable_irq(bp->pdev->irq);
10130 bnx2x_interrupt(bp->pdev->irq, dev);
10131 enable_irq(bp->pdev->irq);
10132}
10133#endif
10134
c64213cd
SH		 10135static const struct net_device_ops bnx2x_netdev_ops = {
10136 .ndo_open = bnx2x_open,
10137 .ndo_stop = bnx2x_close,
10138 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 10139 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 10140 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 10141 .ndo_set_mac_address = bnx2x_change_mac_addr,
10142 .ndo_validate_addr = eth_validate_addr,
10143 .ndo_do_ioctl = bnx2x_ioctl,
10144 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 10145 .ndo_fix_features = bnx2x_fix_features,
10146 .ndo_set_features = bnx2x_set_features,
c64213cd 10147 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 10148#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 10149 .ndo_poll_controller = poll_bnx2x,
10150#endif
6383c0b3
AE		 10151 .ndo_setup_tc = bnx2x_setup_tc,
10152
bf61ee14
VZ		 10153#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10154 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10155#endif
c64213cd
SH		 10156};
10157
619c5cb6
VZ		 10158static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10159{
10160 struct device *dev = &bp->pdev->dev;
10161
10162 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10163 bp->flags |= USING_DAC_FLAG;
10164 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10165 dev_err(dev, "dma_set_coherent_mask failed, "
10166 "aborting\n");
10167 return -EIO;
10168 }
10169 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10170 dev_err(dev, "System does not support DMA, aborting\n");
10171 return -EIO;
10172 }
10173
10174 return 0;
10175}
10176
34f80b04 10177static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 10178 struct net_device *dev,
10179 unsigned long board_type)
a2fbb9ea
ET		 10180{
10181 struct bnx2x *bp;
10182 int rc;
10183
10184 SET_NETDEV_DEV(dev, &pdev->dev);
10185 bp = netdev_priv(dev);
10186
34f80b04
EG		 10187 bp->dev = dev;
10188 bp->pdev = pdev;
a2fbb9ea 10189 bp->flags = 0;
f2e0899f 10190 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 10191
10192 rc = pci_enable_device(pdev);
10193 if (rc) {
cdaa7cb8
VZ		 10194 dev_err(&bp->pdev->dev,
10195 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 10196 goto err_out;
10197 }
10198
10199 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10200 dev_err(&bp->pdev->dev,
10201 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 10202 rc = -ENODEV;
10203 goto err_out_disable;
10204 }
10205
10206 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10207 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10208 " base address, aborting\n");
a2fbb9ea
ET		 10209 rc = -ENODEV;
10210 goto err_out_disable;
10211 }
10212
34f80b04
EG		 10213 if (atomic_read(&pdev->enable_cnt) == 1) {
10214 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10215 if (rc) {
cdaa7cb8
VZ		 10216 dev_err(&bp->pdev->dev,
10217 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 10218 goto err_out_disable;
10219 }
a2fbb9ea 10220
34f80b04
EG		 10221 pci_set_master(pdev);
10222 pci_save_state(pdev);
10223 }
a2fbb9ea
ET		 10224
10225 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10226 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 10227 dev_err(&bp->pdev->dev,
10228 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 10229 rc = -EIO;
10230 goto err_out_release;
10231 }
10232
77c98e6a
JM		 10233 if (!pci_is_pcie(pdev)) {
10234 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 10235 rc = -EIO;
10236 goto err_out_release;
10237 }
10238
619c5cb6
VZ		 10239 rc = bnx2x_set_coherency_mask(bp);
10240 if (rc)
a2fbb9ea 10241 goto err_out_release;
a2fbb9ea 10242
34f80b04
EG		 10243 dev->mem_start = pci_resource_start(pdev, 0);
10244 dev->base_addr = dev->mem_start;
10245 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 10246
10247 dev->irq = pdev->irq;
10248
275f165f 10249 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 10250 if (!bp->regview) {
cdaa7cb8
VZ		 10251 dev_err(&bp->pdev->dev,
10252 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 10253 rc = -ENOMEM;
10254 goto err_out_release;
10255 }
10256
a2fbb9ea
ET		 10257 bnx2x_set_power_state(bp, PCI_D0);
10258
34f80b04
EG		 10259 /* clean indirect addresses */
10260 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10261 PCICFG_VENDOR_ID_OFFSET);
10262 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10263 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10264 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10265 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 10266
2189400b 10267 /*
619c5cb6 10268 * Enable internal target-read (in case we are probed after PF FLR).
2189400b 10269 * Must be done prior to any BAR read access. Only for 57712 and up
619c5cb6 10270 */
2189400b
SR		 10271 if (board_type != BCM57710 &&
10272 board_type != BCM57711 &&
10273 board_type != BCM57711E)
10274 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
619c5cb6 10275
72fd0718
VZ		 10276 /* Reset the load counter */
10277 bnx2x_clear_load_cnt(bp);
10278
34f80b04 10279 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10280
c64213cd 10281 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10282 bnx2x_set_ethtool_ops(dev);
5316bc0b 10283
66371c44
MM		 10284 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10285 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10286 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10287
10288 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10289 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10290
10291 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10292 if (bp->flags & USING_DAC_FLAG)
66371c44 10293 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10294
538dd2e3
MB		 10295 /* Add Loopback capability to the device */
10296 dev->hw_features |= NETIF_F_LOOPBACK;
10297
98507672 10298#ifdef BCM_DCBNL
785b9b1a
SR		 10299 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10300#endif
10301
01cd4528
EG		 10302 /* get_port_hwinfo() will set prtad and mmds properly */
10303 bp->mdio.prtad = MDIO_PRTAD_NONE;
10304 bp->mdio.mmds = 0;
10305 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10306 bp->mdio.dev = dev;
10307 bp->mdio.mdio_read = bnx2x_mdio_read;
10308 bp->mdio.mdio_write = bnx2x_mdio_write;
10309
a2fbb9ea
ET		 10310 return 0;
10311
a2fbb9ea 10312err_out_release:
34f80b04
EG		 10313 if (atomic_read(&pdev->enable_cnt) == 1)
10314 pci_release_regions(pdev);
a2fbb9ea
ET		 10315
10316err_out_disable:
10317 pci_disable_device(pdev);
10318 pci_set_drvdata(pdev, NULL);
10319
10320err_out:
10321 return rc;
10322}
10323
37f9ce62
EG		 10324static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10325 int *width, int *speed)
25047950
ET		 10326{
10327 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10328
37f9ce62 10329 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10330
37f9ce62
EG		 10331 /* return value of 1=2.5GHz 2=5GHz */
10332 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10333}
37f9ce62 10334
6891dd25 10335static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10336{
37f9ce62 10337 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10338 struct bnx2x_fw_file_hdr *fw_hdr;
10339 struct bnx2x_fw_file_section *sections;
94a78b79 10340 u32 offset, len, num_ops;
37f9ce62 10341 u16 *ops_offsets;
94a78b79 10342 int i;
37f9ce62 10343 const u8 *fw_ver;
94a78b79
VZ		 10344
10345 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10346 return -EINVAL;
10347
10348 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10349 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10350
10351 /* Make sure none of the offsets and sizes make us read beyond
10352 * the end of the firmware data */
10353 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10354 offset = be32_to_cpu(sections[i].offset);
10355 len = be32_to_cpu(sections[i].len);
10356 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 10357 dev_err(&bp->pdev->dev,
10358 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 10359 return -EINVAL;
10360 }
10361 }
10362
10363 /* Likewise for the init_ops offsets */
10364 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10365 ops_offsets = (u16 *)(firmware->data + offset);
10366 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10367
10368 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10369 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 10370 dev_err(&bp->pdev->dev,
10371 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10372 return -EINVAL;
10373 }
10374 }
10375
10376 /* Check FW version */
10377 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10378 fw_ver = firmware->data + offset;
10379 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10380 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10381 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10382 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 10383 dev_err(&bp->pdev->dev,
10384 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 10385 fw_ver[0], fw_ver[1], fw_ver[2],
10386 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10387 BCM_5710_FW_MINOR_VERSION,
10388 BCM_5710_FW_REVISION_VERSION,
10389 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10390 return -EINVAL;
94a78b79
VZ		 10391 }
10392
10393 return 0;
10394}
10395
ab6ad5a4 10396static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10397{
ab6ad5a4
EG		 10398 const __be32 *source = (const __be32 *)_source;
10399 u32 *target = (u32 *)_target;
94a78b79 10400 u32 i;
94a78b79
VZ		 10401
10402 for (i = 0; i < n/4; i++)
10403 target[i] = be32_to_cpu(source[i]);
10404}
10405
10406/*
10407 Ops array is stored in the following format:
10408 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10409 */
ab6ad5a4 10410static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10411{
ab6ad5a4
EG		 10412 const __be32 *source = (const __be32 *)_source;
10413 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10414 u32 i, j, tmp;
94a78b79 10415
ab6ad5a4 10416 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10417 tmp = be32_to_cpu(source[j]);
10418 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10419 target[i].offset = tmp & 0xffffff;
10420 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10421 }
10422}
ab6ad5a4 10423
523224a3
DK		 10424/**
10425 * IRO array is stored in the following format:
10426 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10427 */
10428static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10429{
10430 const __be32 *source = (const __be32 *)_source;
10431 struct iro *target = (struct iro *)_target;
10432 u32 i, j, tmp;
10433
10434 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10435 target[i].base = be32_to_cpu(source[j]);
10436 j++;
10437 tmp = be32_to_cpu(source[j]);
10438 target[i].m1 = (tmp >> 16) & 0xffff;
10439 target[i].m2 = tmp & 0xffff;
10440 j++;
10441 tmp = be32_to_cpu(source[j]);
10442 target[i].m3 = (tmp >> 16) & 0xffff;
10443 target[i].size = tmp & 0xffff;
10444 j++;
10445 }
10446}
10447
ab6ad5a4 10448static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10449{
ab6ad5a4
EG		 10450 const __be16 *source = (const __be16 *)_source;
10451 u16 *target = (u16 *)_target;
94a78b79 10452 u32 i;
94a78b79
VZ		 10453
10454 for (i = 0; i < n/2; i++)
10455 target[i] = be16_to_cpu(source[i]);
10456}
10457
7995c64e
JP		 10458#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10459do { \
10460 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10461 bp->arr = kmalloc(len, GFP_KERNEL); \
10462 if (!bp->arr) { \
10463 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10464 goto lbl; \
10465 } \
10466 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10467 (u8 *)bp->arr, len); \
10468} while (0)
94a78b79 10469
6891dd25 10470int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10471{
45229b42 10472 const char *fw_file_name;
94a78b79 10473 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10474 int rc;
94a78b79 10475
94a78b79 10476 if (CHIP_IS_E1(bp))
45229b42 10477 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 10478 else if (CHIP_IS_E1H(bp))
45229b42 10479 fw_file_name = FW_FILE_NAME_E1H;
619c5cb6 10480 else if (!CHIP_IS_E1x(bp))
f2e0899f 10481 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 10482 else {
6891dd25 10483 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 10484 return -EINVAL;
10485 }
94a78b79 10486
6891dd25 10487 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 10488
6891dd25 10489 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 10490 if (rc) {
6891dd25 10491 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 10492 goto request_firmware_exit;
10493 }
10494
10495 rc = bnx2x_check_firmware(bp);
10496 if (rc) {
6891dd25 10497 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 10498 goto request_firmware_exit;
10499 }
10500
10501 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10502
10503 /* Initialize the pointers to the init arrays */
10504 /* Blob */
10505 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10506
10507 /* Opcodes */
10508 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10509
10510 /* Offsets */
ab6ad5a4
EG		 10511 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10512 be16_to_cpu_n);
94a78b79
VZ		 10513
10514 /* STORMs firmware */
573f2035
EG		 10515 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10516 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10517 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10518 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10519 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10520 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10521 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10522 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10523 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10524 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10525 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10526 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10527 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10528 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10529 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10530 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 10531 /* IRO */
10532 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 10533
10534 return 0;
ab6ad5a4 10535
523224a3
DK		 10536iro_alloc_err:
10537 kfree(bp->init_ops_offsets);
94a78b79
VZ		 10538init_offsets_alloc_err:
10539 kfree(bp->init_ops);
10540init_ops_alloc_err:
10541 kfree(bp->init_data);
10542request_firmware_exit:
10543 release_firmware(bp->firmware);
10544
10545 return rc;
10546}
10547
619c5cb6
VZ		 10548static void bnx2x_release_firmware(struct bnx2x *bp)
10549{
10550 kfree(bp->init_ops_offsets);
10551 kfree(bp->init_ops);
10552 kfree(bp->init_data);
10553 release_firmware(bp->firmware);
10554}
10555
10556
10557static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10558 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10559 .init_hw_cmn = bnx2x_init_hw_common,
10560 .init_hw_port = bnx2x_init_hw_port,
10561 .init_hw_func = bnx2x_init_hw_func,
10562
10563 .reset_hw_cmn = bnx2x_reset_common,
10564 .reset_hw_port = bnx2x_reset_port,
10565 .reset_hw_func = bnx2x_reset_func,
10566
10567 .gunzip_init = bnx2x_gunzip_init,
10568 .gunzip_end = bnx2x_gunzip_end,
10569
10570 .init_fw = bnx2x_init_firmware,
10571 .release_fw = bnx2x_release_firmware,
10572};
10573
10574void bnx2x__init_func_obj(struct bnx2x *bp)
10575{
10576 /* Prepare DMAE related driver resources */
10577 bnx2x_setup_dmae(bp);
10578
10579 bnx2x_init_func_obj(bp, &bp->func_obj,
10580 bnx2x_sp(bp, func_rdata),
10581 bnx2x_sp_mapping(bp, func_rdata),
10582 &bnx2x_func_sp_drv);
10583}
10584
10585/* must be called after sriov-enable */
6383c0b3 10586static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 10587{
6383c0b3 10588 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 10589
523224a3
DK		 10590#ifdef BCM_CNIC
10591 cid_count += CNIC_CID_MAX;
10592#endif
10593 return roundup(cid_count, QM_CID_ROUND);
10594}
f85582f8 10595
619c5cb6 10596/**
6383c0b3 10597 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 10598 *
10599 * @dev: pci device
10600 *
10601 */
6383c0b3 10602static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 10603{
10604 int pos;
10605 u16 control;
10606
10607 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 10608
10609 /*
10610 * If MSI-X is not supported - return number of SBs needed to support
10611 * one fast path queue: one FP queue + SB for CNIC
10612 */
619c5cb6 10613 if (!pos)
6383c0b3 10614 return 1 + CNIC_PRESENT;
619c5cb6 10615
6383c0b3
AE		 10616 /*
10617 * The value in the PCI configuration space is the index of the last
10618 * entry, namely one less than the actual size of the table, which is
10619 * exactly what we want to return from this function: number of all SBs
10620 * without the default SB.
10621 */
619c5cb6 10622 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 10623 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 10624}
10625
a2fbb9ea
ET		 10626static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10627 const struct pci_device_id *ent)
10628{
a2fbb9ea
ET		 10629 struct net_device *dev = NULL;
10630 struct bnx2x *bp;
37f9ce62 10631 int pcie_width, pcie_speed;
6383c0b3
AE		 10632 int rc, max_non_def_sbs;
10633 int rx_count, tx_count, rss_count;
10634 /*
10635 * An estimated maximum supported CoS number according to the chip
10636 * version.
10637 * We will try to roughly estimate the maximum number of CoSes this chip
10638 * may support in order to minimize the memory allocated for Tx
10639 * netdev_queue's. This number will be accurately calculated during the
10640 * initialization of bp->max_cos based on the chip versions AND chip
10641 * revision in the bnx2x_init_bp().
10642 */
10643 u8 max_cos_est = 0;
523224a3 10644
f2e0899f
DK		 10645 switch (ent->driver_data) {
10646 case BCM57710:
10647 case BCM57711:
10648 case BCM57711E:
6383c0b3
AE		 10649 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10650 break;
10651
f2e0899f 10652 case BCM57712:
619c5cb6 10653 case BCM57712_MF:
6383c0b3
AE		 10654 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10655 break;
10656
619c5cb6
VZ		 10657 case BCM57800:
10658 case BCM57800_MF:
10659 case BCM57810:
10660 case BCM57810_MF:
10661 case BCM57840:
10662 case BCM57840_MF:
6383c0b3 10663 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 10664 break;
a2fbb9ea 10665
f2e0899f
DK		 10666 default:
10667 pr_err("Unknown board_type (%ld), aborting\n",
10668 ent->driver_data);
870634b0 10669 return -ENODEV;
f2e0899f
DK		 10670 }
10671
6383c0b3
AE		 10672 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10673
10674 /* !!! FIXME !!!
10675 * Do not allow the maximum SB count to grow above 16
10676 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10677 * We will use the FP_SB_MAX_E1x macro for this matter.
10678 */
10679 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10680
10681 WARN_ON(!max_non_def_sbs);
10682
10683 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10684 rss_count = max_non_def_sbs - CNIC_PRESENT;
10685
10686 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10687 rx_count = rss_count + FCOE_PRESENT;
10688
10689 /*
10690 * Maximum number of netdev Tx queues:
10691 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10692 */
10693 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 10694
a2fbb9ea 10695 /* dev zeroed in init_etherdev */
6383c0b3 10696 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
34f80b04 10697 if (!dev) {
cdaa7cb8 10698 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 10699 return -ENOMEM;
34f80b04 10700 }
a2fbb9ea 10701
a2fbb9ea 10702 bp = netdev_priv(dev);
a2fbb9ea 10703
6383c0b3
AE		 10704 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10705 tx_count, rx_count);
df4770de 10706
6383c0b3
AE		 10707 bp->igu_sb_cnt = max_non_def_sbs;
10708 bp->msg_enable = debug;
10709 pci_set_drvdata(pdev, dev);
523224a3 10710
619c5cb6 10711 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 10712 if (rc < 0) {
10713 free_netdev(dev);
10714 return rc;
10715 }
10716
6383c0b3 10717 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
619c5cb6 10718
34f80b04 10719 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 10720 if (rc)
10721 goto init_one_exit;
10722
6383c0b3
AE		 10723 /*
10724 * Map doorbels here as we need the real value of bp->max_cos which
10725 * is initialized in bnx2x_init_bp().
10726 */
10727 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10728 min_t(u64, BNX2X_DB_SIZE(bp),
10729 pci_resource_len(pdev, 2)));
10730 if (!bp->doorbells) {
10731 dev_err(&bp->pdev->dev,
10732 "Cannot map doorbell space, aborting\n");
10733 rc = -ENOMEM;
10734 goto init_one_exit;
10735 }
10736
523224a3 10737 /* calc qm_cid_count */
6383c0b3 10738 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 10739
ec6ba945 10740#ifdef BCM_CNIC
928ad22a
DK		 10741 /* disable FCOE L2 queue for E1x and E3*/
10742 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
ec6ba945
VZ		 10743 bp->flags |= NO_FCOE_FLAG;
10744
10745#endif
10746
25985edc 10747 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 10748 * needed, set bp->num_queues appropriately.
10749 */
10750 bnx2x_set_int_mode(bp);
10751
10752 /* Add all NAPI objects */
10753 bnx2x_add_all_napi(bp);
10754
b340007f
VZ		 10755 rc = register_netdev(dev);
10756 if (rc) {
10757 dev_err(&pdev->dev, "Cannot register net device\n");
10758 goto init_one_exit;
10759 }
10760
ec6ba945
VZ		 10761#ifdef BCM_CNIC
10762 if (!NO_FCOE(bp)) {
10763 /* Add storage MAC address */
10764 rtnl_lock();
10765 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10766 rtnl_unlock();
10767 }
10768#endif
10769
37f9ce62 10770 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 10771
cdaa7cb8
VZ		 10772 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10773 " IRQ %d, ", board_info[ent->driver_data].name,
10774 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 10775 pcie_width,
10776 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10777 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10778 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 10779 dev->base_addr, bp->pdev->irq);
10780 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 10781
a2fbb9ea 10782 return 0;
34f80b04
EG		 10783
10784init_one_exit:
10785 if (bp->regview)
10786 iounmap(bp->regview);
10787
10788 if (bp->doorbells)
10789 iounmap(bp->doorbells);
10790
10791 free_netdev(dev);
10792
10793 if (atomic_read(&pdev->enable_cnt) == 1)
10794 pci_release_regions(pdev);
10795
10796 pci_disable_device(pdev);
10797 pci_set_drvdata(pdev, NULL);
10798
10799 return rc;
a2fbb9ea
ET		 10800}
10801
10802static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10803{
10804 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 10805 struct bnx2x *bp;
10806
10807 if (!dev) {
cdaa7cb8 10808 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 10809 return;
10810 }
228241eb 10811 bp = netdev_priv(dev);
a2fbb9ea 10812
ec6ba945
VZ		 10813#ifdef BCM_CNIC
10814 /* Delete storage MAC address */
10815 if (!NO_FCOE(bp)) {
10816 rtnl_lock();
10817 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10818 rtnl_unlock();
10819 }
10820#endif
10821
98507672
SR		 10822#ifdef BCM_DCBNL
10823 /* Delete app tlvs from dcbnl */
10824 bnx2x_dcbnl_update_applist(bp, true);
10825#endif
10826
a2fbb9ea
ET		 10827 unregister_netdev(dev);
10828
d6214d7a
DK		 10829 /* Delete all NAPI objects */
10830 bnx2x_del_all_napi(bp);
10831
084d6cbb
VZ		 10832 /* Power on: we can't let PCI layer write to us while we are in D3 */
10833 bnx2x_set_power_state(bp, PCI_D0);
10834
d6214d7a
DK		 10835 /* Disable MSI/MSI-X */
10836 bnx2x_disable_msi(bp);
f85582f8 10837
084d6cbb
VZ		 10838 /* Power off */
10839 bnx2x_set_power_state(bp, PCI_D3hot);
10840
72fd0718 10841 /* Make sure RESET task is not scheduled before continuing */
7be08a72 10842 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 10843
a2fbb9ea
ET		 10844 if (bp->regview)
10845 iounmap(bp->regview);
10846
10847 if (bp->doorbells)
10848 iounmap(bp->doorbells);
10849
523224a3
DK		 10850 bnx2x_free_mem_bp(bp);
10851
a2fbb9ea 10852 free_netdev(dev);
34f80b04
EG		 10853
10854 if (atomic_read(&pdev->enable_cnt) == 1)
10855 pci_release_regions(pdev);
10856
a2fbb9ea
ET		 10857 pci_disable_device(pdev);
10858 pci_set_drvdata(pdev, NULL);
10859}
10860
f8ef6e44
YG		 10861static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10862{
10863 int i;
10864
10865 bp->state = BNX2X_STATE_ERROR;
10866
10867 bp->rx_mode = BNX2X_RX_MODE_NONE;
10868
619c5cb6
VZ		 10869#ifdef BCM_CNIC
10870 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10871#endif
10872 /* Stop Tx */
10873 bnx2x_tx_disable(bp);
10874
f8ef6e44
YG		 10875 bnx2x_netif_stop(bp, 0);
10876
10877 del_timer_sync(&bp->timer);
619c5cb6
VZ		 10878
10879 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 10880
10881 /* Release IRQs */
d6214d7a 10882 bnx2x_free_irq(bp);
f8ef6e44 10883
f8ef6e44
YG		 10884 /* Free SKBs, SGEs, TPA pool and driver internals */
10885 bnx2x_free_skbs(bp);
523224a3 10886
ec6ba945 10887 for_each_rx_queue(bp, i)
f8ef6e44 10888 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 10889
f8ef6e44
YG		 10890 bnx2x_free_mem(bp);
10891
10892 bp->state = BNX2X_STATE_CLOSED;
10893
619c5cb6
VZ		 10894 netif_carrier_off(bp->dev);
10895
f8ef6e44
YG		 10896 return 0;
10897}
10898
10899static void bnx2x_eeh_recover(struct bnx2x *bp)
10900{
10901 u32 val;
10902
10903 mutex_init(&bp->port.phy_mutex);
10904
10905 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10906 bp->link_params.shmem_base = bp->common.shmem_base;
10907 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10908
10909 if (!bp->common.shmem_base ||
10910 (bp->common.shmem_base < 0xA0000) ||
10911 (bp->common.shmem_base >= 0xC0000)) {
10912 BNX2X_DEV_INFO("MCP not active\n");
10913 bp->flags |= NO_MCP_FLAG;
10914 return;
10915 }
10916
10917 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10918 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10919 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10920 BNX2X_ERR("BAD MCP validity signature\n");
10921
10922 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 10923 bp->fw_seq =
10924 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10925 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 10926 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10927 }
10928}
10929
493adb1f
WX		 10930/**
10931 * bnx2x_io_error_detected - called when PCI error is detected
10932 * @pdev: Pointer to PCI device
10933 * @state: The current pci connection state
10934 *
10935 * This function is called after a PCI bus error affecting
10936 * this device has been detected.
10937 */
10938static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10939 pci_channel_state_t state)
10940{
10941 struct net_device *dev = pci_get_drvdata(pdev);
10942 struct bnx2x *bp = netdev_priv(dev);
10943
10944 rtnl_lock();
10945
10946 netif_device_detach(dev);
10947
07ce50e4
DN		 10948 if (state == pci_channel_io_perm_failure) {
10949 rtnl_unlock();
10950 return PCI_ERS_RESULT_DISCONNECT;
10951 }
10952
493adb1f 10953 if (netif_running(dev))
f8ef6e44 10954 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 10955
10956 pci_disable_device(pdev);
10957
10958 rtnl_unlock();
10959
10960 /* Request a slot reset */
10961 return PCI_ERS_RESULT_NEED_RESET;
10962}
10963
10964/**
10965 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10966 * @pdev: Pointer to PCI device
10967 *
10968 * Restart the card from scratch, as if from a cold-boot.
10969 */
10970static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10971{
10972 struct net_device *dev = pci_get_drvdata(pdev);
10973 struct bnx2x *bp = netdev_priv(dev);
10974
10975 rtnl_lock();
10976
10977 if (pci_enable_device(pdev)) {
10978 dev_err(&pdev->dev,
10979 "Cannot re-enable PCI device after reset\n");
10980 rtnl_unlock();
10981 return PCI_ERS_RESULT_DISCONNECT;
10982 }
10983
10984 pci_set_master(pdev);
10985 pci_restore_state(pdev);
10986
10987 if (netif_running(dev))
10988 bnx2x_set_power_state(bp, PCI_D0);
10989
10990 rtnl_unlock();
10991
10992 return PCI_ERS_RESULT_RECOVERED;
10993}
10994
10995/**
10996 * bnx2x_io_resume - called when traffic can start flowing again
10997 * @pdev: Pointer to PCI device
10998 *
10999 * This callback is called when the error recovery driver tells us that
11000 * its OK to resume normal operation.
11001 */
11002static void bnx2x_io_resume(struct pci_dev *pdev)
11003{
11004 struct net_device *dev = pci_get_drvdata(pdev);
11005 struct bnx2x *bp = netdev_priv(dev);
11006
72fd0718 11007 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
754a2f52
DK		 11008 netdev_err(bp->dev, "Handling parity error recovery. "
11009 "Try again later\n");
72fd0718
VZ		 11010 return;
11011 }
11012
493adb1f
WX		 11013 rtnl_lock();
11014
f8ef6e44
YG		 11015 bnx2x_eeh_recover(bp);
11016
493adb1f 11017 if (netif_running(dev))
f8ef6e44 11018 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 11019
11020 netif_device_attach(dev);
11021
11022 rtnl_unlock();
11023}
11024
11025static struct pci_error_handlers bnx2x_err_handler = {
11026 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 11027 .slot_reset = bnx2x_io_slot_reset,
11028 .resume = bnx2x_io_resume,
493adb1f
WX		 11029};
11030
a2fbb9ea 11031static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 11032 .name = DRV_MODULE_NAME,
11033 .id_table = bnx2x_pci_tbl,
11034 .probe = bnx2x_init_one,
11035 .remove = __devexit_p(bnx2x_remove_one),
11036 .suspend = bnx2x_suspend,
11037 .resume = bnx2x_resume,
11038 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 11039};
11040
11041static int __init bnx2x_init(void)
11042{
dd21ca6d
SG		 11043 int ret;
11044
7995c64e 11045 pr_info("%s", version);
938cf541 11046
1cf167f2
EG		 11047 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11048 if (bnx2x_wq == NULL) {
7995c64e 11049 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 11050 return -ENOMEM;
11051 }
11052
dd21ca6d
SG		 11053 ret = pci_register_driver(&bnx2x_pci_driver);
11054 if (ret) {
7995c64e 11055 pr_err("Cannot register driver\n");
dd21ca6d
SG		 11056 destroy_workqueue(bnx2x_wq);
11057 }
11058 return ret;
a2fbb9ea
ET		 11059}
11060
11061static void __exit bnx2x_cleanup(void)
11062{
11063 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 11064
11065 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 11066}
11067
3deb8167
YR		 11068void bnx2x_notify_link_changed(struct bnx2x *bp)
11069{
11070 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11071}
11072
a2fbb9ea
ET		 11073module_init(bnx2x_init);
11074module_exit(bnx2x_cleanup);
11075
993ac7b5 11076#ifdef BCM_CNIC
619c5cb6
VZ		 11077/**
11078 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11079 *
11080 * @bp: driver handle
11081 * @set: set or clear the CAM entry
11082 *
11083 * This function will wait until the ramdord completion returns.
11084 * Return 0 if success, -ENODEV if ramrod doesn't return.
11085 */
11086static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11087{
11088 unsigned long ramrod_flags = 0;
11089
11090 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11091 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11092 &bp->iscsi_l2_mac_obj, true,
11093 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11094}
993ac7b5
MC		 11095
11096/* count denotes the number of new completions we have seen */
11097static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11098{
11099 struct eth_spe *spe;
11100
11101#ifdef BNX2X_STOP_ON_ERROR
11102 if (unlikely(bp->panic))
11103 return;
11104#endif
11105
11106 spin_lock_bh(&bp->spq_lock);
c2bff63f 11107 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 11108 bp->cnic_spq_pending -= count;
11109
993ac7b5 11110
c2bff63f
DK		 11111 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11112 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11113 & SPE_HDR_CONN_TYPE) >>
11114 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 11115 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11116 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 11117
11118 /* Set validation for iSCSI L2 client before sending SETUP
11119 * ramrod
11120 */
11121 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 11122 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 11123 bnx2x_set_ctx_validation(bp, &bp->context.
11124 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11125 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 11126 }
11127
619c5cb6
VZ		 11128 /*
11129 * There may be not more than 8 L2, not more than 8 L5 SPEs
11130 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 11131 * COMMON ramrods is not more than the EQ and SPQ can
11132 * accommodate.
c2bff63f 11133 */
6e30dd4e
VZ		 11134 if (type == ETH_CONNECTION_TYPE) {
11135 if (!atomic_read(&bp->cq_spq_left))
11136 break;
11137 else
11138 atomic_dec(&bp->cq_spq_left);
11139 } else if (type == NONE_CONNECTION_TYPE) {
11140 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 11141 break;
11142 else
6e30dd4e 11143 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 11144 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11145 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 11146 if (bp->cnic_spq_pending >=
11147 bp->cnic_eth_dev.max_kwqe_pending)
11148 break;
11149 else
11150 bp->cnic_spq_pending++;
11151 } else {
11152 BNX2X_ERR("Unknown SPE type: %d\n", type);
11153 bnx2x_panic();
993ac7b5 11154 break;
c2bff63f 11155 }
993ac7b5
MC		 11156
11157 spe = bnx2x_sp_get_next(bp);
11158 *spe = *bp->cnic_kwq_cons;
11159
993ac7b5
MC		 11160 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11161 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11162
11163 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11164 bp->cnic_kwq_cons = bp->cnic_kwq;
11165 else
11166 bp->cnic_kwq_cons++;
11167 }
11168 bnx2x_sp_prod_update(bp);
11169 spin_unlock_bh(&bp->spq_lock);
11170}
11171
11172static int bnx2x_cnic_sp_queue(struct net_device *dev,
11173 struct kwqe_16 *kwqes[], u32 count)
11174{
11175 struct bnx2x *bp = netdev_priv(dev);
11176 int i;
11177
11178#ifdef BNX2X_STOP_ON_ERROR
11179 if (unlikely(bp->panic))
11180 return -EIO;
11181#endif
11182
11183 spin_lock_bh(&bp->spq_lock);
11184
11185 for (i = 0; i < count; i++) {
11186 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11187
11188 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11189 break;
11190
11191 *bp->cnic_kwq_prod = *spe;
11192
11193 bp->cnic_kwq_pending++;
11194
11195 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11196 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 11197 spe->data.update_data_addr.hi,
11198 spe->data.update_data_addr.lo,
993ac7b5
MC		 11199 bp->cnic_kwq_pending);
11200
11201 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11202 bp->cnic_kwq_prod = bp->cnic_kwq;
11203 else
11204 bp->cnic_kwq_prod++;
11205 }
11206
11207 spin_unlock_bh(&bp->spq_lock);
11208
11209 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11210 bnx2x_cnic_sp_post(bp, 0);
11211
11212 return i;
11213}
11214
11215static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11216{
11217 struct cnic_ops *c_ops;
11218 int rc = 0;
11219
11220 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 11221 c_ops = rcu_dereference_protected(bp->cnic_ops,
11222 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 11223 if (c_ops)
11224 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11225 mutex_unlock(&bp->cnic_mutex);
11226
11227 return rc;
11228}
11229
11230static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11231{
11232 struct cnic_ops *c_ops;
11233 int rc = 0;
11234
11235 rcu_read_lock();
11236 c_ops = rcu_dereference(bp->cnic_ops);
11237 if (c_ops)
11238 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11239 rcu_read_unlock();
11240
11241 return rc;
11242}
11243
11244/*
11245 * for commands that have no data
11246 */
9f6c9258 11247int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 11248{
11249 struct cnic_ctl_info ctl = {0};
11250
11251 ctl.cmd = cmd;
11252
11253 return bnx2x_cnic_ctl_send(bp, &ctl);
11254}
11255
619c5cb6 11256static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 11257{
619c5cb6 11258 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 11259
11260 /* first we tell CNIC and only then we count this as a completion */
11261 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11262 ctl.data.comp.cid = cid;
619c5cb6 11263 ctl.data.comp.error = err;
993ac7b5
MC		 11264
11265 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11266 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11267}
11268
619c5cb6
VZ		 11269
11270/* Called with netif_addr_lock_bh() taken.
11271 * Sets an rx_mode config for an iSCSI ETH client.
11272 * Doesn't block.
11273 * Completion should be checked outside.
11274 */
11275static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11276{
11277 unsigned long accept_flags = 0, ramrod_flags = 0;
11278 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11279 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11280
11281 if (start) {
11282 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11283 * because it's the only way for UIO Queue to accept
11284 * multicasts (in non-promiscuous mode only one Queue per
11285 * function will receive multicast packets (leading in our
11286 * case).
11287 */
11288 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11289 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11290 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11291 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11292
11293 /* Clear STOP_PENDING bit if START is requested */
11294 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11295
11296 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11297 } else
11298 /* Clear START_PENDING bit if STOP is requested */
11299 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11300
11301 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11302 set_bit(sched_state, &bp->sp_state);
11303 else {
11304 __set_bit(RAMROD_RX, &ramrod_flags);
11305 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11306 ramrod_flags);
11307 }
11308}
11309
11310
993ac7b5
MC		 11311static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11312{
11313 struct bnx2x *bp = netdev_priv(dev);
11314 int rc = 0;
11315
11316 switch (ctl->cmd) {
11317 case DRV_CTL_CTXTBL_WR_CMD: {
11318 u32 index = ctl->data.io.offset;
11319 dma_addr_t addr = ctl->data.io.dma_addr;
11320
11321 bnx2x_ilt_wr(bp, index, addr);
11322 break;
11323 }
11324
c2bff63f
DK		 11325 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11326 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11327
11328 bnx2x_cnic_sp_post(bp, count);
11329 break;
11330 }
11331
11332 /* rtnl_lock is held. */
11333 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11334 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11335 unsigned long sp_bits = 0;
11336
11337 /* Configure the iSCSI classification object */
11338 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11339 cp->iscsi_l2_client_id,
11340 cp->iscsi_l2_cid, BP_FUNC(bp),
11341 bnx2x_sp(bp, mac_rdata),
11342 bnx2x_sp_mapping(bp, mac_rdata),
11343 BNX2X_FILTER_MAC_PENDING,
11344 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11345 &bp->macs_pool);
ec6ba945 11346
523224a3 11347 /* Set iSCSI MAC address */
619c5cb6
VZ		 11348 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11349 if (rc)
11350 break;
523224a3
DK		 11351
11352 mmiowb();
11353 barrier();
11354
619c5cb6
VZ		 11355 /* Start accepting on iSCSI L2 ring */
11356
11357 netif_addr_lock_bh(dev);
11358 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11359 netif_addr_unlock_bh(dev);
11360
11361 /* bits to wait on */
11362 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11363 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11364
11365 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11366 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11367
993ac7b5
MC		 11368 break;
11369 }
11370
11371 /* rtnl_lock is held. */
11372 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11373 unsigned long sp_bits = 0;
993ac7b5 11374
523224a3 11375 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11376 netif_addr_lock_bh(dev);
11377 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11378 netif_addr_unlock_bh(dev);
11379
11380 /* bits to wait on */
11381 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11382 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11383
11384 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11385 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11386
11387 mmiowb();
11388 barrier();
11389
11390 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11391 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11392 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11393 break;
11394 }
c2bff63f
DK		 11395 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11396 int count = ctl->data.credit.credit_count;
11397
11398 smp_mb__before_atomic_inc();
6e30dd4e 11399 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11400 smp_mb__after_atomic_inc();
11401 break;
11402 }
993ac7b5
MC		 11403
11404 default:
11405 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11406 rc = -EINVAL;
11407 }
11408
11409 return rc;
11410}
11411
9f6c9258 11412void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11413{
11414 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11415
11416 if (bp->flags & USING_MSIX_FLAG) {
11417 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11418 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11419 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11420 } else {
11421 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11422 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11423 }
619c5cb6 11424 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11425 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11426 else
11427 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11428
619c5cb6
VZ		 11429 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11430 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11431 cp->irq_arr[1].status_blk = bp->def_status_blk;
11432 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11433 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11434
11435 cp->num_irq = 2;
11436}
11437
11438static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11439 void *data)
11440{
11441 struct bnx2x *bp = netdev_priv(dev);
11442 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11443
11444 if (ops == NULL)
11445 return -EINVAL;
11446
993ac7b5
MC		 11447 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11448 if (!bp->cnic_kwq)
11449 return -ENOMEM;
11450
11451 bp->cnic_kwq_cons = bp->cnic_kwq;
11452 bp->cnic_kwq_prod = bp->cnic_kwq;
11453 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11454
11455 bp->cnic_spq_pending = 0;
11456 bp->cnic_kwq_pending = 0;
11457
11458 bp->cnic_data = data;
11459
11460 cp->num_irq = 0;
619c5cb6 11461 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 11462 cp->iro_arr = bp->iro_arr;
993ac7b5 11463
993ac7b5 11464 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 11465
993ac7b5
MC		 11466 rcu_assign_pointer(bp->cnic_ops, ops);
11467
11468 return 0;
11469}
11470
11471static int bnx2x_unregister_cnic(struct net_device *dev)
11472{
11473 struct bnx2x *bp = netdev_priv(dev);
11474 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11475
11476 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 11477 cp->drv_state = 0;
11478 rcu_assign_pointer(bp->cnic_ops, NULL);
11479 mutex_unlock(&bp->cnic_mutex);
11480 synchronize_rcu();
11481 kfree(bp->cnic_kwq);
11482 bp->cnic_kwq = NULL;
11483
11484 return 0;
11485}
11486
11487struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11488{
11489 struct bnx2x *bp = netdev_priv(dev);
11490 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11491
2ba45142
VZ		 11492 /* If both iSCSI and FCoE are disabled - return NULL in
11493 * order to indicate CNIC that it should not try to work
11494 * with this device.
11495 */
11496 if (NO_ISCSI(bp) && NO_FCOE(bp))
11497 return NULL;
11498
993ac7b5
MC		 11499 cp->drv_owner = THIS_MODULE;
11500 cp->chip_id = CHIP_ID(bp);
11501 cp->pdev = bp->pdev;
11502 cp->io_base = bp->regview;
11503 cp->io_base2 = bp->doorbells;
11504 cp->max_kwqe_pending = 8;
523224a3 11505 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 11506 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11507 bnx2x_cid_ilt_lines(bp);
993ac7b5 11508 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 11509 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 11510 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11511 cp->drv_ctl = bnx2x_drv_ctl;
11512 cp->drv_register_cnic = bnx2x_register_cnic;
11513 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 11514 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 11515 cp->iscsi_l2_client_id =
11516 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 11517 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11518
2ba45142
VZ		 11519 if (NO_ISCSI_OOO(bp))
11520 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11521
11522 if (NO_ISCSI(bp))
11523 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11524
11525 if (NO_FCOE(bp))
11526 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11527
c2bff63f
DK		 11528 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11529 "starting cid %d\n",
11530 cp->ctx_blk_size,
11531 cp->ctx_tbl_offset,
11532 cp->ctx_tbl_len,
11533 cp->starting_cid);
993ac7b5
MC		 11534 return cp;
11535}
11536EXPORT_SYMBOL(bnx2x_cnic_probe);
11537
11538#endif /* BCM_CNIC */
94a78b79 11539
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