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bnx2x: fix DMAE timeout according to hw specifications
[mirror_ubuntu-eoan-kernel.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea
ET		 41#include <net/ip.h>
42#include <net/tcp.h>
43#include <net/checksum.h>
34f80b04 44#include <net/ip6_checksum.h>
a2fbb9ea
ET		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
34f80b04 47#include <linux/crc32c.h>
a2fbb9ea
ET		 48#include <linux/prefetch.h>
49#include <linux/zlib.h>
a2fbb9ea 50#include <linux/io.h>
45229b42 51#include <linux/stringify.h>
a2fbb9ea 52
b0efbb99 53#define BNX2X_MAIN
a2fbb9ea
ET		 54#include "bnx2x.h"
55#include "bnx2x_init.h"
94a78b79 56#include "bnx2x_init_ops.h"
9f6c9258 57#include "bnx2x_cmn.h"
e4901dde 58#include "bnx2x_dcb.h"
a2fbb9ea 59
94a78b79
VZ		 60#include <linux/firmware.h>
61#include "bnx2x_fw_file_hdr.h"
62/* FW files */
45229b42
BH		 63#define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 68#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 70#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 71
34f80b04
EG		 72/* Time in jiffies before concluding the transmitter is hung */
73#define TX_TIMEOUT (5*HZ)
a2fbb9ea 74
53a10565 75static char version[] __devinitdata =
34f80b04 76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
a2fbb9ea
ET		 77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
24e3fcef 79MODULE_AUTHOR("Eliezer Tamir");
f2e0899f
DK		 80MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
a2fbb9ea
ET		 82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 84MODULE_FIRMWARE(FW_FILE_NAME_E1);
85MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 86MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 87
555f6c78
EG		 88static int multi_mode = 1;
89module_param(multi_mode, int, 0);
ca00392c
EG		 90MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
d6214d7a 93int num_queues;
54b9ddaa
VZ		 94module_param(num_queues, int, 0);
95MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
555f6c78 97
19680c48 98static int disable_tpa;
19680c48 99module_param(disable_tpa, int, 0);
9898f86d 100MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a
EG		 101
102static int int_mode;
103module_param(int_mode, int, 0);
cdaa7cb8
VZ		 104MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
8badd27a 106
a18f5128
EG		 107static int dropless_fc;
108module_param(dropless_fc, int, 0);
109MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
9898f86d 111static int poll;
a2fbb9ea 112module_param(poll, int, 0);
9898f86d 113MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 114
115static int mrrs = -1;
116module_param(mrrs, int, 0);
117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
a2fbb9ea 120module_param(debug, int, 0);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
1cf167f2 123static struct workqueue_struct *bnx2x_wq;
a2fbb9ea 124
ec6ba945
VZ		 125#ifdef BCM_CNIC
126static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127#endif
128
a2fbb9ea
ET		 129enum bnx2x_board_type {
130 BCM57710 = 0,
34f80b04
EG		 131 BCM57711 = 1,
132 BCM57711E = 2,
f2e0899f
DK		 133 BCM57712 = 3,
134 BCM57712E = 4
a2fbb9ea
ET		 135};
136
34f80b04 137/* indexed by board_type, above */
53a10565 138static struct {
a2fbb9ea
ET		 139 char *name;
140} board_info[] __devinitdata = {
34f80b04
EG		 141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
f2e0899f
DK		 143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
a2fbb9ea
ET		 146};
147
a3aa1884 148static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 149 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
150 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
151 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f
DK		 152 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
153 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
a2fbb9ea
ET		 154 { 0 }
155};
156
157MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
158
159/****************************************************************************
160* General service functions
161****************************************************************************/
162
523224a3
DK		 163static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
164 u32 addr, dma_addr_t mapping)
165{
166 REG_WR(bp, addr, U64_LO(mapping));
167 REG_WR(bp, addr + 4, U64_HI(mapping));
168}
169
170static inline void __storm_memset_fill(struct bnx2x *bp,
171 u32 addr, size_t size, u32 val)
172{
173 int i;
174 for (i = 0; i < size/4; i++)
175 REG_WR(bp, addr + (i * 4), val);
176}
177
178static inline void storm_memset_ustats_zero(struct bnx2x *bp,
179 u8 port, u16 stat_id)
180{
181 size_t size = sizeof(struct ustorm_per_client_stats);
182
183 u32 addr = BAR_USTRORM_INTMEM +
184 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
185
186 __storm_memset_fill(bp, addr, size, 0);
187}
188
189static inline void storm_memset_tstats_zero(struct bnx2x *bp,
190 u8 port, u16 stat_id)
191{
192 size_t size = sizeof(struct tstorm_per_client_stats);
193
194 u32 addr = BAR_TSTRORM_INTMEM +
195 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
196
197 __storm_memset_fill(bp, addr, size, 0);
198}
199
200static inline void storm_memset_xstats_zero(struct bnx2x *bp,
201 u8 port, u16 stat_id)
202{
203 size_t size = sizeof(struct xstorm_per_client_stats);
204
205 u32 addr = BAR_XSTRORM_INTMEM +
206 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
207
208 __storm_memset_fill(bp, addr, size, 0);
209}
210
211
212static inline void storm_memset_spq_addr(struct bnx2x *bp,
213 dma_addr_t mapping, u16 abs_fid)
214{
215 u32 addr = XSEM_REG_FAST_MEMORY +
216 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
217
218 __storm_memset_dma_mapping(bp, addr, mapping);
219}
220
221static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
222{
223 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
224}
225
226static inline void storm_memset_func_cfg(struct bnx2x *bp,
227 struct tstorm_eth_function_common_config *tcfg,
228 u16 abs_fid)
229{
230 size_t size = sizeof(struct tstorm_eth_function_common_config);
231
232 u32 addr = BAR_TSTRORM_INTMEM +
233 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
234
235 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
236}
237
238static inline void storm_memset_xstats_flags(struct bnx2x *bp,
239 struct stats_indication_flags *flags,
240 u16 abs_fid)
241{
242 size_t size = sizeof(struct stats_indication_flags);
243
244 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
245
246 __storm_memset_struct(bp, addr, size, (u32 *)flags);
247}
248
249static inline void storm_memset_tstats_flags(struct bnx2x *bp,
250 struct stats_indication_flags *flags,
251 u16 abs_fid)
252{
253 size_t size = sizeof(struct stats_indication_flags);
254
255 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
256
257 __storm_memset_struct(bp, addr, size, (u32 *)flags);
258}
259
260static inline void storm_memset_ustats_flags(struct bnx2x *bp,
261 struct stats_indication_flags *flags,
262 u16 abs_fid)
263{
264 size_t size = sizeof(struct stats_indication_flags);
265
266 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)flags);
269}
270
271static inline void storm_memset_cstats_flags(struct bnx2x *bp,
272 struct stats_indication_flags *flags,
273 u16 abs_fid)
274{
275 size_t size = sizeof(struct stats_indication_flags);
276
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
278
279 __storm_memset_struct(bp, addr, size, (u32 *)flags);
280}
281
282static inline void storm_memset_xstats_addr(struct bnx2x *bp,
283 dma_addr_t mapping, u16 abs_fid)
284{
285 u32 addr = BAR_XSTRORM_INTMEM +
286 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
287
288 __storm_memset_dma_mapping(bp, addr, mapping);
289}
290
291static inline void storm_memset_tstats_addr(struct bnx2x *bp,
292 dma_addr_t mapping, u16 abs_fid)
293{
294 u32 addr = BAR_TSTRORM_INTMEM +
295 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
296
297 __storm_memset_dma_mapping(bp, addr, mapping);
298}
299
300static inline void storm_memset_ustats_addr(struct bnx2x *bp,
301 dma_addr_t mapping, u16 abs_fid)
302{
303 u32 addr = BAR_USTRORM_INTMEM +
304 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
305
306 __storm_memset_dma_mapping(bp, addr, mapping);
307}
308
309static inline void storm_memset_cstats_addr(struct bnx2x *bp,
310 dma_addr_t mapping, u16 abs_fid)
311{
312 u32 addr = BAR_CSTRORM_INTMEM +
313 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
314
315 __storm_memset_dma_mapping(bp, addr, mapping);
316}
317
318static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
319 u16 pf_id)
320{
321 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
322 pf_id);
323 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
324 pf_id);
325 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
326 pf_id);
327 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
328 pf_id);
329}
330
331static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
332 u8 enable)
333{
334 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
335 enable);
336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
337 enable);
338 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
339 enable);
340 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
341 enable);
342}
343
344static inline void storm_memset_eq_data(struct bnx2x *bp,
345 struct event_ring_data *eq_data,
346 u16 pfid)
347{
348 size_t size = sizeof(struct event_ring_data);
349
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
351
352 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
353}
354
355static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
356 u16 pfid)
357{
358 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
359 REG_WR16(bp, addr, eq_prod);
360}
361
362static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
363 u16 fw_sb_id, u8 sb_index,
364 u8 ticks)
365{
366
f2e0899f
DK		 367 int index_offset = CHIP_IS_E2(bp) ?
368 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 369 offsetof(struct hc_status_block_data_e1x, index_data);
370 u32 addr = BAR_CSTRORM_INTMEM +
371 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
372 index_offset +
373 sizeof(struct hc_index_data)*sb_index +
374 offsetof(struct hc_index_data, timeout);
375 REG_WR8(bp, addr, ticks);
376 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
377 port, fw_sb_id, sb_index, ticks);
378}
379static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
380 u16 fw_sb_id, u8 sb_index,
381 u8 disable)
382{
383 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
f2e0899f
DK		 384 int index_offset = CHIP_IS_E2(bp) ?
385 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 386 offsetof(struct hc_status_block_data_e1x, index_data);
387 u32 addr = BAR_CSTRORM_INTMEM +
388 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
389 index_offset +
390 sizeof(struct hc_index_data)*sb_index +
391 offsetof(struct hc_index_data, flags);
392 u16 flags = REG_RD16(bp, addr);
393 /* clear and set */
394 flags &= ~HC_INDEX_DATA_HC_ENABLED;
395 flags |= enable_flag;
396 REG_WR16(bp, addr, flags);
397 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
398 port, fw_sb_id, sb_index, disable);
399}
400
a2fbb9ea
ET		 401/* used only at init
402 * locking is done by mcp
403 */
8d96286a 404static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 405{
406 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
407 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
408 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
409 PCICFG_VENDOR_ID_OFFSET);
410}
411
a2fbb9ea
ET		 412static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
413{
414 u32 val;
415
416 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
417 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
418 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
419 PCICFG_VENDOR_ID_OFFSET);
420
421 return val;
422}
a2fbb9ea 423
f2e0899f
DK		 424#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
425#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
426#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
427#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
428#define DMAE_DP_DST_NONE "dst_addr [none]"
429
8d96286a 430static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
431 int msglvl)
f2e0899f
DK		 432{
433 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
434
435 switch (dmae->opcode & DMAE_COMMAND_DST) {
436 case DMAE_CMD_DST_PCI:
437 if (src_type == DMAE_CMD_SRC_PCI)
438 DP(msglvl, "DMAE: opcode 0x%08x\n"
439 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
440 "comp_addr [%x:%08x], comp_val 0x%08x\n",
441 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
442 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
443 dmae->comp_addr_hi, dmae->comp_addr_lo,
444 dmae->comp_val);
445 else
446 DP(msglvl, "DMAE: opcode 0x%08x\n"
447 "src [%08x], len [%d*4], dst [%x:%08x]\n"
448 "comp_addr [%x:%08x], comp_val 0x%08x\n",
449 dmae->opcode, dmae->src_addr_lo >> 2,
450 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
451 dmae->comp_addr_hi, dmae->comp_addr_lo,
452 dmae->comp_val);
453 break;
454 case DMAE_CMD_DST_GRC:
455 if (src_type == DMAE_CMD_SRC_PCI)
456 DP(msglvl, "DMAE: opcode 0x%08x\n"
457 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
458 "comp_addr [%x:%08x], comp_val 0x%08x\n",
459 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
460 dmae->len, dmae->dst_addr_lo >> 2,
461 dmae->comp_addr_hi, dmae->comp_addr_lo,
462 dmae->comp_val);
463 else
464 DP(msglvl, "DMAE: opcode 0x%08x\n"
465 "src [%08x], len [%d*4], dst [%08x]\n"
466 "comp_addr [%x:%08x], comp_val 0x%08x\n",
467 dmae->opcode, dmae->src_addr_lo >> 2,
468 dmae->len, dmae->dst_addr_lo >> 2,
469 dmae->comp_addr_hi, dmae->comp_addr_lo,
470 dmae->comp_val);
471 break;
472 default:
473 if (src_type == DMAE_CMD_SRC_PCI)
474 DP(msglvl, "DMAE: opcode 0x%08x\n"
475 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
476 "dst_addr [none]\n"
477 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
478 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
479 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
480 dmae->comp_val);
481 else
482 DP(msglvl, "DMAE: opcode 0x%08x\n"
483 DP_LEVEL "src_addr [%08x] len [%d * 4] "
484 "dst_addr [none]\n"
485 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
486 dmae->opcode, dmae->src_addr_lo >> 2,
487 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
488 dmae->comp_val);
489 break;
490 }
491
492}
493
6c719d00 494const u32 dmae_reg_go_c[] = {
a2fbb9ea
ET		 495 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
496 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
497 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
498 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
499};
500
501/* copy command into DMAE command memory and set DMAE command go */
6c719d00 502void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 503{
504 u32 cmd_offset;
505 int i;
506
507 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
508 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
510
ad8d3948
EG		 511 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
512 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 513 }
514 REG_WR(bp, dmae_reg_go_c[idx], 1);
515}
516
f2e0899f 517u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 518{
f2e0899f
DK		 519 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
520 DMAE_CMD_C_ENABLE);
521}
ad8d3948 522
f2e0899f
DK		 523u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
524{
525 return opcode & ~DMAE_CMD_SRC_RESET;
526}
ad8d3948 527
f2e0899f
DK		 528u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
529 bool with_comp, u8 comp_type)
530{
531 u32 opcode = 0;
532
533 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
534 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 535
f2e0899f
DK		 536 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
537
538 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
539 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
540 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
541 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 542
a2fbb9ea 543#ifdef __BIG_ENDIAN
f2e0899f 544 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 545#else
f2e0899f 546 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 547#endif
f2e0899f
DK		 548 if (with_comp)
549 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
550 return opcode;
551}
552
8d96286a 553static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
554 struct dmae_command *dmae,
555 u8 src_type, u8 dst_type)
f2e0899f
DK		 556{
557 memset(dmae, 0, sizeof(struct dmae_command));
558
559 /* set the opcode */
560 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
561 true, DMAE_COMP_PCI);
562
563 /* fill in the completion parameters */
564 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
565 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
566 dmae->comp_val = DMAE_COMP_VAL;
567}
568
569/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 570static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
571 struct dmae_command *dmae)
f2e0899f
DK		 572{
573 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 574 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 575 int rc = 0;
576
577 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 578 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
579 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 580
f2e0899f 581 /* lock the dmae channel */
6e30dd4e 582 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 583
f2e0899f 584 /* reset completion */
a2fbb9ea
ET		 585 *wb_comp = 0;
586
f2e0899f
DK		 587 /* post the command on the channel used for initializations */
588 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 589
f2e0899f 590 /* wait for completion */
a2fbb9ea 591 udelay(5);
f2e0899f 592 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 593 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
594
ad8d3948 595 if (!cnt) {
c3eefaf6 596 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 597 rc = DMAE_TIMEOUT;
598 goto unlock;
a2fbb9ea 599 }
ad8d3948 600 cnt--;
f2e0899f 601 udelay(50);
a2fbb9ea 602 }
f2e0899f
DK		 603 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
604 BNX2X_ERR("DMAE PCI error!\n");
605 rc = DMAE_PCI_ERROR;
606 }
607
608 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
609 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
610 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 611
f2e0899f 612unlock:
6e30dd4e 613 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 614 return rc;
615}
616
617void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
618 u32 len32)
619{
620 struct dmae_command dmae;
621
622 if (!bp->dmae_ready) {
623 u32 *data = bnx2x_sp(bp, wb_data[0]);
624
625 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
626 " using indirect\n", dst_addr, len32);
627 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
628 return;
629 }
630
631 /* set opcode and fixed command fields */
632 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
633
634 /* fill in addresses and len */
635 dmae.src_addr_lo = U64_LO(dma_addr);
636 dmae.src_addr_hi = U64_HI(dma_addr);
637 dmae.dst_addr_lo = dst_addr >> 2;
638 dmae.dst_addr_hi = 0;
639 dmae.len = len32;
640
641 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
642
643 /* issue the command and wait for completion */
644 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 645}
646
c18487ee 647void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 648{
5ff7b6d4 649 struct dmae_command dmae;
ad8d3948
EG		 650
651 if (!bp->dmae_ready) {
652 u32 *data = bnx2x_sp(bp, wb_data[0]);
653 int i;
654
655 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
656 " using indirect\n", src_addr, len32);
657 for (i = 0; i < len32; i++)
658 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
659 return;
660 }
661
f2e0899f
DK		 662 /* set opcode and fixed command fields */
663 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 664
f2e0899f 665 /* fill in addresses and len */
5ff7b6d4
EG		 666 dmae.src_addr_lo = src_addr >> 2;
667 dmae.src_addr_hi = 0;
668 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
669 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
670 dmae.len = len32;
ad8d3948 671
f2e0899f 672 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 673
f2e0899f
DK		 674 /* issue the command and wait for completion */
675 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 676}
677
8d96286a 678static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
679 u32 addr, u32 len)
573f2035 680{
02e3c6cb 681 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 682 int offset = 0;
683
02e3c6cb 684 while (len > dmae_wr_max) {
573f2035 685 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 686 addr + offset, dmae_wr_max);
687 offset += dmae_wr_max * 4;
688 len -= dmae_wr_max;
573f2035
EG		 689 }
690
691 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
692}
693
ad8d3948
EG		 694/* used only for slowpath so not inlined */
695static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
696{
697 u32 wb_write[2];
698
699 wb_write[0] = val_hi;
700 wb_write[1] = val_lo;
701 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 702}
a2fbb9ea 703
ad8d3948
EG		 704#ifdef USE_WB_RD
705static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
706{
707 u32 wb_data[2];
708
709 REG_RD_DMAE(bp, reg, wb_data, 2);
710
711 return HILO_U64(wb_data[0], wb_data[1]);
712}
713#endif
714
a2fbb9ea
ET		 715static int bnx2x_mc_assert(struct bnx2x *bp)
716{
a2fbb9ea 717 char last_idx;
34f80b04
EG		 718 int i, rc = 0;
719 u32 row0, row1, row2, row3;
720
721 /* XSTORM */
722 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
723 XSTORM_ASSERT_LIST_INDEX_OFFSET);
724 if (last_idx)
725 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
726
727 /* print the asserts */
728 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
729
730 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
731 XSTORM_ASSERT_LIST_OFFSET(i));
732 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
733 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
734 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
735 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
736 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
737 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
738
739 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
740 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
741 " 0x%08x 0x%08x 0x%08x\n",
742 i, row3, row2, row1, row0);
743 rc++;
744 } else {
745 break;
746 }
747 }
748
749 /* TSTORM */
750 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
751 TSTORM_ASSERT_LIST_INDEX_OFFSET);
752 if (last_idx)
753 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
754
755 /* print the asserts */
756 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
757
758 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
759 TSTORM_ASSERT_LIST_OFFSET(i));
760 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
761 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
762 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
763 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
764 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
765 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
766
767 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
768 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
769 " 0x%08x 0x%08x 0x%08x\n",
770 i, row3, row2, row1, row0);
771 rc++;
772 } else {
773 break;
774 }
775 }
776
777 /* CSTORM */
778 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
779 CSTORM_ASSERT_LIST_INDEX_OFFSET);
780 if (last_idx)
781 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
782
783 /* print the asserts */
784 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
785
786 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
787 CSTORM_ASSERT_LIST_OFFSET(i));
788 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
789 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
790 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
791 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
792 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
793 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
794
795 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
796 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
797 " 0x%08x 0x%08x 0x%08x\n",
798 i, row3, row2, row1, row0);
799 rc++;
800 } else {
801 break;
802 }
803 }
804
805 /* USTORM */
806 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
807 USTORM_ASSERT_LIST_INDEX_OFFSET);
808 if (last_idx)
809 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
810
811 /* print the asserts */
812 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
813
814 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
815 USTORM_ASSERT_LIST_OFFSET(i));
816 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
817 USTORM_ASSERT_LIST_OFFSET(i) + 4);
818 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
819 USTORM_ASSERT_LIST_OFFSET(i) + 8);
820 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
821 USTORM_ASSERT_LIST_OFFSET(i) + 12);
822
823 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
824 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
825 " 0x%08x 0x%08x 0x%08x\n",
826 i, row3, row2, row1, row0);
827 rc++;
828 } else {
829 break;
a2fbb9ea
ET		 830 }
831 }
34f80b04 832
a2fbb9ea
ET		 833 return rc;
834}
c14423fe 835
a2fbb9ea
ET		 836static void bnx2x_fw_dump(struct bnx2x *bp)
837{
cdaa7cb8 838 u32 addr;
a2fbb9ea 839 u32 mark, offset;
4781bfad 840 __be32 data[9];
a2fbb9ea 841 int word;
f2e0899f 842 u32 trace_shmem_base;
2145a920
VZ		 843 if (BP_NOMCP(bp)) {
844 BNX2X_ERR("NO MCP - can not dump\n");
845 return;
846 }
cdaa7cb8 847
f2e0899f
DK		 848 if (BP_PATH(bp) == 0)
849 trace_shmem_base = bp->common.shmem_base;
850 else
851 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
852 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 853 mark = REG_RD(bp, addr);
f2e0899f
DK		 854 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
855 + ((mark + 0x3) & ~0x3) - 0x08000000;
7995c64e 856 pr_err("begin fw dump (mark 0x%x)\n", mark);
a2fbb9ea 857
7995c64e 858 pr_err("");
f2e0899f 859 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 860 for (word = 0; word < 8; word++)
cdaa7cb8 861 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 862 data[8] = 0x0;
7995c64e 863 pr_cont("%s", (char *)data);
a2fbb9ea 864 }
cdaa7cb8 865 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 866 for (word = 0; word < 8; word++)
cdaa7cb8 867 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 868 data[8] = 0x0;
7995c64e 869 pr_cont("%s", (char *)data);
a2fbb9ea 870 }
7995c64e 871 pr_err("end of fw dump\n");
a2fbb9ea
ET		 872}
873
6c719d00 874void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 875{
876 int i;
523224a3
DK		 877 u16 j;
878 struct hc_sp_status_block_data sp_sb_data;
879 int func = BP_FUNC(bp);
880#ifdef BNX2X_STOP_ON_ERROR
881 u16 start = 0, end = 0;
882#endif
a2fbb9ea 883
66e855f3
YG		 884 bp->stats_state = STATS_STATE_DISABLED;
885 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
886
a2fbb9ea
ET		 887 BNX2X_ERR("begin crash dump -----------------\n");
888
8440d2b6
EG		 889 /* Indices */
890 /* Common */
523224a3 891 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
cdaa7cb8 892 " spq_prod_idx(0x%x)\n",
523224a3
DK		 893 bp->def_idx, bp->def_att_idx,
894 bp->attn_state, bp->spq_prod_idx);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp->def_status_blk->atten_status_block.attn_bits,
897 bp->def_status_blk->atten_status_block.attn_bits_ack,
898 bp->def_status_blk->atten_status_block.status_block_id,
899 bp->def_status_blk->atten_status_block.attn_bits_index);
900 BNX2X_ERR(" def (");
901 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
902 pr_cont("0x%x%s",
903 bp->def_status_blk->sp_sb.index_values[i],
904 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
905
906 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
907 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
909 i*sizeof(u32));
910
911 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
912 "pf_id(0x%x) vnic_id(0x%x) "
913 "vf_id(0x%x) vf_valid (0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid);
920
8440d2b6 921
ec6ba945 922 for_each_eth_queue(bp, i) {
a2fbb9ea 923 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 924 int loop;
f2e0899f 925 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 926 struct hc_status_block_data_e1x sb_data_e1x;
927 struct hc_status_block_sm *hc_sm_p =
f2e0899f
DK		 928 CHIP_IS_E2(bp) ?
929 sb_data_e2.common.state_machine :
523224a3
DK		 930 sb_data_e1x.common.state_machine;
931 struct hc_index_data *hc_index_p =
f2e0899f
DK		 932 CHIP_IS_E2(bp) ?
933 sb_data_e2.index_data :
523224a3
DK		 934 sb_data_e1x.index_data;
935 int data_size;
936 u32 *sb_data_p;
937
938 /* Rx */
cdaa7cb8 939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 940 " rx_comp_prod(0x%x)"
cdaa7cb8 941 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 942 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 943 fp->rx_comp_prod,
66e855f3 944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 946 " fp_hc_idx(0x%x)\n",
8440d2b6 947 fp->rx_sge_prod, fp->last_max_sge,
523224a3 948 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 949
523224a3 950 /* Tx */
cdaa7cb8
VZ		 951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
952 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
953 " *tx_cons_sb(0x%x)\n",
8440d2b6
EG		 954 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
955 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
523224a3 956
f2e0899f
DK		 957 loop = CHIP_IS_E2(bp) ?
958 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
523224a3
DK		 959
960 /* host sb data */
961
ec6ba945
VZ		 962#ifdef BCM_CNIC
963 if (IS_FCOE_FP(fp))
964 continue;
965#endif
523224a3
DK		 966 BNX2X_ERR(" run indexes (");
967 for (j = 0; j < HC_SB_MAX_SM; j++)
968 pr_cont("0x%x%s",
969 fp->sb_running_index[j],
970 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
971
972 BNX2X_ERR(" indexes (");
973 for (j = 0; j < loop; j++)
974 pr_cont("0x%x%s",
975 fp->sb_index_values[j],
976 (j == loop - 1) ? ")" : " ");
977 /* fw sb data */
f2e0899f
DK		 978 data_size = CHIP_IS_E2(bp) ?
979 sizeof(struct hc_status_block_data_e2) :
523224a3
DK		 980 sizeof(struct hc_status_block_data_e1x);
981 data_size /= sizeof(u32);
f2e0899f
DK		 982 sb_data_p = CHIP_IS_E2(bp) ?
983 (u32 *)&sb_data_e2 :
984 (u32 *)&sb_data_e1x;
523224a3
DK		 985 /* copy sb data in here */
986 for (j = 0; j < data_size; j++)
987 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
989 j * sizeof(u32));
990
f2e0899f
DK		 991 if (CHIP_IS_E2(bp)) {
992 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
993 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
994 sb_data_e2.common.p_func.pf_id,
995 sb_data_e2.common.p_func.vf_id,
996 sb_data_e2.common.p_func.vf_valid,
997 sb_data_e2.common.p_func.vnic_id,
998 sb_data_e2.common.same_igu_sb_1b);
999 } else {
1000 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1001 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1002 sb_data_e1x.common.p_func.pf_id,
1003 sb_data_e1x.common.p_func.vf_id,
1004 sb_data_e1x.common.p_func.vf_valid,
1005 sb_data_e1x.common.p_func.vnic_id,
1006 sb_data_e1x.common.same_igu_sb_1b);
1007 }
523224a3
DK		 1008
1009 /* SB_SMs data */
1010 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011 pr_cont("SM[%d] __flags (0x%x) "
1012 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1013 "time_to_expire (0x%x) "
1014 "timer_value(0x%x)\n", j,
1015 hc_sm_p[j].__flags,
1016 hc_sm_p[j].igu_sb_id,
1017 hc_sm_p[j].igu_seg_id,
1018 hc_sm_p[j].time_to_expire,
1019 hc_sm_p[j].timer_value);
1020 }
1021
1022 /* Indecies data */
1023 for (j = 0; j < loop; j++) {
1024 pr_cont("INDEX[%d] flags (0x%x) "
1025 "timeout (0x%x)\n", j,
1026 hc_index_p[j].flags,
1027 hc_index_p[j].timeout);
1028 }
8440d2b6 1029 }
a2fbb9ea 1030
523224a3 1031#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 1032 /* Rings */
1033 /* Rx */
ec6ba945 1034 for_each_rx_queue(bp, i) {
8440d2b6 1035 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1036
1037 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1038 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1039 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1040 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1041 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1042
c3eefaf6
EG		 1043 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1044 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 1045 }
1046
3196a88a
EG		 1047 start = RX_SGE(fp->rx_sge_prod);
1048 end = RX_SGE(fp->last_max_sge);
8440d2b6 1049 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1050 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1051 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1052
c3eefaf6
EG		 1053 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1054 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1055 }
1056
a2fbb9ea
ET		 1057 start = RCQ_BD(fp->rx_comp_cons - 10);
1058 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1059 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1060 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1061
c3eefaf6
EG		 1062 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1063 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1064 }
1065 }
1066
8440d2b6 1067 /* Tx */
ec6ba945 1068 for_each_tx_queue(bp, i) {
8440d2b6
EG		 1069 struct bnx2x_fastpath *fp = &bp->fp[i];
1070
1071 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1072 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1073 for (j = start; j != end; j = TX_BD(j + 1)) {
1074 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1075
c3eefaf6
EG		 1076 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1077 i, j, sw_bd->skb, sw_bd->first_bd);
8440d2b6
EG		 1078 }
1079
1080 start = TX_BD(fp->tx_bd_cons - 10);
1081 end = TX_BD(fp->tx_bd_cons + 254);
1082 for (j = start; j != end; j = TX_BD(j + 1)) {
1083 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1084
c3eefaf6
EG		 1085 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1086 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
8440d2b6
EG		 1087 }
1088 }
523224a3 1089#endif
34f80b04 1090 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1091 bnx2x_mc_assert(bp);
1092 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1093}
1094
f2e0899f 1095static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1096{
34f80b04 1097 int port = BP_PORT(bp);
a2fbb9ea
ET		 1098 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1099 u32 val = REG_RD(bp, addr);
1100 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1101 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1102
1103 if (msix) {
8badd27a
EG		 1104 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1105 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1106 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1107 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1108 } else if (msi) {
1109 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1110 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1111 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1112 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1113 } else {
1114 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1115 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1116 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1117 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1118
a0fd065c
DK		 1119 if (!CHIP_IS_E1(bp)) {
1120 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1121 val, port, addr);
615f8fd9 1122
a0fd065c 1123 REG_WR(bp, addr, val);
615f8fd9 1124
a0fd065c
DK		 1125 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1126 }
a2fbb9ea
ET		 1127 }
1128
a0fd065c
DK		 1129 if (CHIP_IS_E1(bp))
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1131
8badd27a
EG		 1132 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1133 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1134
1135 REG_WR(bp, addr, val);
37dbbf32
EG		 1136 /*
1137 * Ensure that HC_CONFIG is written before leading/trailing edge config
1138 */
1139 mmiowb();
1140 barrier();
34f80b04 1141
f2e0899f 1142 if (!CHIP_IS_E1(bp)) {
34f80b04 1143 /* init leading/trailing edge */
fb3bff17 1144 if (IS_MF(bp)) {
8badd27a 1145 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1146 if (bp->port.pmf)
4acac6a5
EG		 1147 /* enable nig and gpio3 attention */
1148 val |= 0x1100;
34f80b04
EG		 1149 } else
1150 val = 0xffff;
1151
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1154 }
37dbbf32
EG		 1155
1156 /* Make sure that interrupts are indeed enabled from here on */
1157 mmiowb();
a2fbb9ea
ET		 1158}
1159
f2e0899f
DK		 1160static void bnx2x_igu_int_enable(struct bnx2x *bp)
1161{
1162 u32 val;
1163 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1164 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1165
1166 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1167
1168 if (msix) {
1169 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1170 IGU_PF_CONF_SINGLE_ISR_EN);
1171 val |= (IGU_PF_CONF_FUNC_EN |
1172 IGU_PF_CONF_MSI_MSIX_EN |
1173 IGU_PF_CONF_ATTN_BIT_EN);
1174 } else if (msi) {
1175 val &= ~IGU_PF_CONF_INT_LINE_EN;
1176 val |= (IGU_PF_CONF_FUNC_EN |
1177 IGU_PF_CONF_MSI_MSIX_EN |
1178 IGU_PF_CONF_ATTN_BIT_EN |
1179 IGU_PF_CONF_SINGLE_ISR_EN);
1180 } else {
1181 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1182 val |= (IGU_PF_CONF_FUNC_EN |
1183 IGU_PF_CONF_INT_LINE_EN |
1184 IGU_PF_CONF_ATTN_BIT_EN |
1185 IGU_PF_CONF_SINGLE_ISR_EN);
1186 }
1187
1188 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1189 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1190
1191 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1192
1193 barrier();
1194
1195 /* init leading/trailing edge */
1196 if (IS_MF(bp)) {
1197 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1198 if (bp->port.pmf)
1199 /* enable nig and gpio3 attention */
1200 val |= 0x1100;
1201 } else
1202 val = 0xffff;
1203
1204 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1205 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1206
1207 /* Make sure that interrupts are indeed enabled from here on */
1208 mmiowb();
1209}
1210
1211void bnx2x_int_enable(struct bnx2x *bp)
1212{
1213 if (bp->common.int_block == INT_BLOCK_HC)
1214 bnx2x_hc_int_enable(bp);
1215 else
1216 bnx2x_igu_int_enable(bp);
1217}
1218
1219static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1220{
34f80b04 1221 int port = BP_PORT(bp);
a2fbb9ea
ET		 1222 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1223 u32 val = REG_RD(bp, addr);
1224
a0fd065c
DK		 1225 /*
1226 * in E1 we must use only PCI configuration space to disable
1227 * MSI/MSIX capablility
1228 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1229 */
1230 if (CHIP_IS_E1(bp)) {
1231 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1232 * Use mask register to prevent from HC sending interrupts
1233 * after we exit the function
1234 */
1235 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1236
1237 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1238 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1239 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1240 } else
1241 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1242 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1243 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1244 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1245
1246 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1247 val, port, addr);
1248
8badd27a
EG		 1249 /* flush all outstanding writes */
1250 mmiowb();
1251
a2fbb9ea
ET		 1252 REG_WR(bp, addr, val);
1253 if (REG_RD(bp, addr) != val)
1254 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1255}
1256
f2e0899f
DK		 1257static void bnx2x_igu_int_disable(struct bnx2x *bp)
1258{
1259 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1260
1261 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1262 IGU_PF_CONF_INT_LINE_EN |
1263 IGU_PF_CONF_ATTN_BIT_EN);
1264
1265 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1266
1267 /* flush all outstanding writes */
1268 mmiowb();
1269
1270 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1271 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1272 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1273}
1274
8d96286a 1275static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1276{
1277 if (bp->common.int_block == INT_BLOCK_HC)
1278 bnx2x_hc_int_disable(bp);
1279 else
1280 bnx2x_igu_int_disable(bp);
1281}
1282
9f6c9258 1283void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1284{
a2fbb9ea 1285 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1286 int i, offset;
a2fbb9ea 1287
34f80b04 1288 /* disable interrupt handling */
a2fbb9ea 1289 atomic_inc(&bp->intr_sem);
e1510706
EG		 1290 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1291
f8ef6e44
YG		 1292 if (disable_hw)
1293 /* prevent the HW from sending interrupts */
1294 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1295
1296 /* make sure all ISRs are done */
1297 if (msix) {
8badd27a
EG		 1298 synchronize_irq(bp->msix_table[0].vector);
1299 offset = 1;
37b091ba
MC		 1300#ifdef BCM_CNIC
1301 offset++;
1302#endif
ec6ba945 1303 for_each_eth_queue(bp, i)
8badd27a 1304 synchronize_irq(bp->msix_table[i + offset].vector);
a2fbb9ea
ET		 1305 } else
1306 synchronize_irq(bp->pdev->irq);
1307
1308 /* make sure sp_task is not running */
1cf167f2
EG		 1309 cancel_delayed_work(&bp->sp_task);
1310 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1311}
1312
34f80b04 1313/* fast path */
a2fbb9ea
ET		 1314
1315/*
34f80b04 1316 * General service functions
a2fbb9ea
ET		 1317 */
1318
72fd0718
VZ		 1319/* Return true if succeeded to acquire the lock */
1320static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1321{
1322 u32 lock_status;
1323 u32 resource_bit = (1 << resource);
1324 int func = BP_FUNC(bp);
1325 u32 hw_lock_control_reg;
1326
1327 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1328
1329 /* Validating that the resource is within range */
1330 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1331 DP(NETIF_MSG_HW,
1332 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1333 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1334 return false;
72fd0718
VZ		 1335 }
1336
1337 if (func <= 5)
1338 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1339 else
1340 hw_lock_control_reg =
1341 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1342
1343 /* Try to acquire the lock */
1344 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1345 lock_status = REG_RD(bp, hw_lock_control_reg);
1346 if (lock_status & resource_bit)
1347 return true;
1348
1349 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1350 return false;
1351}
1352
993ac7b5
MC		 1353#ifdef BCM_CNIC
1354static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1355#endif
3196a88a 1356
9f6c9258 1357void bnx2x_sp_event(struct bnx2x_fastpath *fp,
a2fbb9ea
ET		 1358 union eth_rx_cqe *rr_cqe)
1359{
1360 struct bnx2x *bp = fp->bp;
1361 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1362 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1363
34f80b04 1364 DP(BNX2X_MSG_SP,
a2fbb9ea 1365 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1366 fp->index, cid, command, bp->state,
34f80b04 1367 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1368
523224a3
DK		 1369 switch (command | fp->state) {
1370 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1371 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1372 fp->state = BNX2X_FP_STATE_OPEN;
a2fbb9ea
ET		 1373 break;
1374
523224a3
DK		 1375 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1376 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
a2fbb9ea
ET		 1377 fp->state = BNX2X_FP_STATE_HALTED;
1378 break;
1379
523224a3
DK		 1380 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1381 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1382 fp->state = BNX2X_FP_STATE_TERMINATED;
a2fbb9ea
ET		 1383 break;
1384
523224a3
DK		 1385 default:
1386 BNX2X_ERR("unexpected MC reply (%d) "
1387 "fp[%d] state is %x\n",
1388 command, fp->index, fp->state);
993ac7b5 1389 break;
523224a3 1390 }
3196a88a 1391
8fe23fbd 1392 smp_mb__before_atomic_inc();
6e30dd4e 1393 atomic_inc(&bp->cq_spq_left);
523224a3
DK		 1394 /* push the change in fp->state and towards the memory */
1395 smp_wmb();
49d66772 1396
523224a3 1397 return;
a2fbb9ea
ET		 1398}
1399
9f6c9258 1400irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1401{
555f6c78 1402 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1403 u16 status = bnx2x_ack_int(bp);
34f80b04 1404 u16 mask;
ca00392c 1405 int i;
a2fbb9ea 1406
34f80b04 1407 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1408 if (unlikely(status == 0)) {
1409 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1410 return IRQ_NONE;
1411 }
f5372251 1412 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1413
34f80b04 1414 /* Return here if interrupt is disabled */
a2fbb9ea
ET		 1415 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1416 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1417 return IRQ_HANDLED;
1418 }
1419
3196a88a
EG		 1420#ifdef BNX2X_STOP_ON_ERROR
1421 if (unlikely(bp->panic))
1422 return IRQ_HANDLED;
1423#endif
1424
ec6ba945 1425 for_each_eth_queue(bp, i) {
ca00392c 1426 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1427
523224a3 1428 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
ca00392c 1429 if (status & mask) {
54b9ddaa
VZ		 1430 /* Handle Rx and Tx according to SB id */
1431 prefetch(fp->rx_cons_sb);
54b9ddaa 1432 prefetch(fp->tx_cons_sb);
523224a3 1433 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1434 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1435 status &= ~mask;
1436 }
a2fbb9ea
ET		 1437 }
1438
993ac7b5 1439#ifdef BCM_CNIC
523224a3 1440 mask = 0x2;
993ac7b5
MC		 1441 if (status & (mask | 0x1)) {
1442 struct cnic_ops *c_ops = NULL;
1443
1444 rcu_read_lock();
1445 c_ops = rcu_dereference(bp->cnic_ops);
1446 if (c_ops)
1447 c_ops->cnic_handler(bp->cnic_data, NULL);
1448 rcu_read_unlock();
1449
1450 status &= ~mask;
1451 }
1452#endif
a2fbb9ea 1453
34f80b04 1454 if (unlikely(status & 0x1)) {
1cf167f2 1455 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1456
1457 status &= ~0x1;
1458 if (!status)
1459 return IRQ_HANDLED;
1460 }
1461
cdaa7cb8
VZ		 1462 if (unlikely(status))
1463 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1464 status);
a2fbb9ea 1465
c18487ee 1466 return IRQ_HANDLED;
a2fbb9ea
ET		 1467}
1468
c18487ee 1469/* end of fast path */
a2fbb9ea 1470
a2fbb9ea 1471
c18487ee
YR		 1472/* Link */
1473
1474/*
1475 * General service functions
1476 */
a2fbb9ea 1477
9f6c9258 1478int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1479{
1480 u32 lock_status;
1481 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1482 int func = BP_FUNC(bp);
1483 u32 hw_lock_control_reg;
c18487ee 1484 int cnt;
a2fbb9ea 1485
c18487ee
YR		 1486 /* Validating that the resource is within range */
1487 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1488 DP(NETIF_MSG_HW,
1489 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1490 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1491 return -EINVAL;
1492 }
a2fbb9ea 1493
4a37fb66
YG		 1494 if (func <= 5) {
1495 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1496 } else {
1497 hw_lock_control_reg =
1498 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1499 }
1500
c18487ee 1501 /* Validating that the resource is not already taken */
4a37fb66 1502 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1503 if (lock_status & resource_bit) {
1504 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1505 lock_status, resource_bit);
1506 return -EEXIST;
1507 }
a2fbb9ea 1508
46230476
EG		 1509 /* Try for 5 second every 5ms */
1510 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1511 /* Try to acquire the lock */
4a37fb66
YG		 1512 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1513 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1514 if (lock_status & resource_bit)
1515 return 0;
a2fbb9ea 1516
c18487ee 1517 msleep(5);
a2fbb9ea 1518 }
c18487ee
YR		 1519 DP(NETIF_MSG_HW, "Timeout\n");
1520 return -EAGAIN;
1521}
a2fbb9ea 1522
9f6c9258 1523int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1524{
1525 u32 lock_status;
1526 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1527 int func = BP_FUNC(bp);
1528 u32 hw_lock_control_reg;
a2fbb9ea 1529
72fd0718
VZ		 1530 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1531
c18487ee
YR		 1532 /* Validating that the resource is within range */
1533 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1534 DP(NETIF_MSG_HW,
1535 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1536 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1537 return -EINVAL;
1538 }
1539
4a37fb66
YG		 1540 if (func <= 5) {
1541 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1542 } else {
1543 hw_lock_control_reg =
1544 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1545 }
1546
c18487ee 1547 /* Validating that the resource is currently taken */
4a37fb66 1548 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1549 if (!(lock_status & resource_bit)) {
1550 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1551 lock_status, resource_bit);
1552 return -EFAULT;
a2fbb9ea
ET		 1553 }
1554
9f6c9258
DK		 1555 REG_WR(bp, hw_lock_control_reg, resource_bit);
1556 return 0;
c18487ee 1557}
a2fbb9ea 1558
9f6c9258 1559
4acac6a5
EG		 1560int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1561{
1562 /* The GPIO should be swapped if swap register is set and active */
1563 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1564 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1565 int gpio_shift = gpio_num +
1566 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1567 u32 gpio_mask = (1 << gpio_shift);
1568 u32 gpio_reg;
1569 int value;
1570
1571 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1572 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1573 return -EINVAL;
1574 }
1575
1576 /* read GPIO value */
1577 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1578
1579 /* get the requested pin value */
1580 if ((gpio_reg & gpio_mask) == gpio_mask)
1581 value = 1;
1582 else
1583 value = 0;
1584
1585 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1586
1587 return value;
1588}
1589
17de50b7 1590int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1591{
1592 /* The GPIO should be swapped if swap register is set and active */
1593 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1594 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1595 int gpio_shift = gpio_num +
1596 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1597 u32 gpio_mask = (1 << gpio_shift);
1598 u32 gpio_reg;
a2fbb9ea 1599
c18487ee
YR		 1600 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1601 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1602 return -EINVAL;
1603 }
a2fbb9ea 1604
4a37fb66 1605 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1606 /* read GPIO and mask except the float bits */
1607 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1608
c18487ee
YR		 1609 switch (mode) {
1610 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1611 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1612 gpio_num, gpio_shift);
1613 /* clear FLOAT and set CLR */
1614 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1615 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1616 break;
a2fbb9ea 1617
c18487ee
YR		 1618 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1619 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1620 gpio_num, gpio_shift);
1621 /* clear FLOAT and set SET */
1622 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1623 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1624 break;
a2fbb9ea 1625
17de50b7 1626 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1627 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1628 gpio_num, gpio_shift);
1629 /* set FLOAT */
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1631 break;
a2fbb9ea 1632
c18487ee
YR		 1633 default:
1634 break;
a2fbb9ea
ET		 1635 }
1636
c18487ee 1637 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1638 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1639
c18487ee 1640 return 0;
a2fbb9ea
ET		 1641}
1642
4acac6a5
EG		 1643int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1644{
1645 /* The GPIO should be swapped if swap register is set and active */
1646 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1647 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1648 int gpio_shift = gpio_num +
1649 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1650 u32 gpio_mask = (1 << gpio_shift);
1651 u32 gpio_reg;
1652
1653 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1654 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1655 return -EINVAL;
1656 }
1657
1658 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1659 /* read GPIO int */
1660 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1661
1662 switch (mode) {
1663 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1664 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1665 "output low\n", gpio_num, gpio_shift);
1666 /* clear SET and set CLR */
1667 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1668 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1669 break;
1670
1671 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1672 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1673 "output high\n", gpio_num, gpio_shift);
1674 /* clear CLR and set SET */
1675 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1677 break;
1678
1679 default:
1680 break;
1681 }
1682
1683 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1684 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1685
1686 return 0;
1687}
1688
c18487ee 1689static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 1690{
c18487ee
YR		 1691 u32 spio_mask = (1 << spio_num);
1692 u32 spio_reg;
a2fbb9ea 1693
c18487ee
YR		 1694 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1695 (spio_num > MISC_REGISTERS_SPIO_7)) {
1696 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1697 return -EINVAL;
a2fbb9ea
ET		 1698 }
1699
4a37fb66 1700 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 1701 /* read SPIO and mask except the float bits */
1702 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 1703
c18487ee 1704 switch (mode) {
6378c025 1705 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 1706 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1707 /* clear FLOAT and set CLR */
1708 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1709 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1710 break;
a2fbb9ea 1711
6378c025 1712 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1714 /* clear FLOAT and set SET */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1717 break;
a2fbb9ea 1718
c18487ee
YR		 1719 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1721 /* set FLOAT */
1722 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 break;
a2fbb9ea 1724
c18487ee
YR		 1725 default:
1726 break;
a2fbb9ea
ET		 1727 }
1728
c18487ee 1729 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 1730 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 1731
a2fbb9ea
ET		 1732 return 0;
1733}
1734
a22f0788
YR		 1735int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1736{
1737 u32 sel_phy_idx = 0;
1738 if (bp->link_vars.link_up) {
1739 sel_phy_idx = EXT_PHY1;
1740 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1741 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1742 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1743 sel_phy_idx = EXT_PHY2;
1744 } else {
1745
1746 switch (bnx2x_phy_selection(&bp->link_params)) {
1747 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1748 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1749 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1750 sel_phy_idx = EXT_PHY1;
1751 break;
1752 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1753 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1754 sel_phy_idx = EXT_PHY2;
1755 break;
1756 }
1757 }
1758 /*
1759 * The selected actived PHY is always after swapping (in case PHY
1760 * swapping is enabled). So when swapping is enabled, we need to reverse
1761 * the configuration
1762 */
1763
1764 if (bp->link_params.multi_phy_config &
1765 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1766 if (sel_phy_idx == EXT_PHY1)
1767 sel_phy_idx = EXT_PHY2;
1768 else if (sel_phy_idx == EXT_PHY2)
1769 sel_phy_idx = EXT_PHY1;
1770 }
1771 return LINK_CONFIG_IDX(sel_phy_idx);
1772}
1773
9f6c9258 1774void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 1775{
a22f0788 1776 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 1777 switch (bp->link_vars.ieee_fc &
1778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 1779 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 1780 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1781 ADVERTISED_Pause);
c18487ee 1782 break;
356e2385 1783
c18487ee 1784 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 1785 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 1786 ADVERTISED_Pause);
c18487ee 1787 break;
356e2385 1788
c18487ee 1789 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 1790 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 1791 break;
356e2385 1792
c18487ee 1793 default:
a22f0788 1794 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1795 ADVERTISED_Pause);
c18487ee
YR		 1796 break;
1797 }
1798}
f1410647 1799
9f6c9258 1800u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 1801{
19680c48
EG		 1802 if (!BP_NOMCP(bp)) {
1803 u8 rc;
a22f0788
YR		 1804 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1805 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 1806 /* Initialize link parameters structure variables */
8c99e7b0
YR		 1807 /* It is recommended to turn off RX FC for jumbo frames
1808 for better performance */
f2e0899f 1809 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 1810 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 1811 else
c0700f90 1812 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 1813
4a37fb66 1814 bnx2x_acquire_phy_lock(bp);
b5bf9068 1815
a22f0788 1816 if (load_mode == LOAD_DIAG) {
de6eae1f 1817 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 1818 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1819 }
b5bf9068 1820
19680c48 1821 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 1822
4a37fb66 1823 bnx2x_release_phy_lock(bp);
a2fbb9ea 1824
3c96c68b
EG		 1825 bnx2x_calc_fc_adv(bp);
1826
b5bf9068
EG		 1827 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1828 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 1829 bnx2x_link_report(bp);
b5bf9068 1830 }
a22f0788 1831 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 1832 return rc;
1833 }
f5372251 1834 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 1835 return -EINVAL;
a2fbb9ea
ET		 1836}
1837
9f6c9258 1838void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 1839{
19680c48 1840 if (!BP_NOMCP(bp)) {
4a37fb66 1841 bnx2x_acquire_phy_lock(bp);
54c2fb78 1842 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 1843 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 1844 bnx2x_release_phy_lock(bp);
a2fbb9ea 1845
19680c48
EG		 1846 bnx2x_calc_fc_adv(bp);
1847 } else
f5372251 1848 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 1849}
a2fbb9ea 1850
c18487ee
YR		 1851static void bnx2x__link_reset(struct bnx2x *bp)
1852{
19680c48 1853 if (!BP_NOMCP(bp)) {
4a37fb66 1854 bnx2x_acquire_phy_lock(bp);
589abe3a 1855 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 1856 bnx2x_release_phy_lock(bp);
19680c48 1857 } else
f5372251 1858 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 1859}
a2fbb9ea 1860
a22f0788 1861u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 1862{
2145a920 1863 u8 rc = 0;
a2fbb9ea 1864
2145a920
VZ		 1865 if (!BP_NOMCP(bp)) {
1866 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 1867 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1868 is_serdes);
2145a920
VZ		 1869 bnx2x_release_phy_lock(bp);
1870 } else
1871 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 1872
c18487ee
YR		 1873 return rc;
1874}
a2fbb9ea 1875
8a1c38d1 1876static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 1877{
8a1c38d1
EG		 1878 u32 r_param = bp->link_vars.line_speed / 8;
1879 u32 fair_periodic_timeout_usec;
1880 u32 t_fair;
34f80b04 1881
8a1c38d1
EG		 1882 memset(&(bp->cmng.rs_vars), 0,
1883 sizeof(struct rate_shaping_vars_per_port));
1884 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 1885
8a1c38d1
EG		 1886 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1887 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 1888
8a1c38d1
EG		 1889 /* this is the threshold below which no timer arming will occur
1890 1.25 coefficient is for the threshold to be a little bigger
1891 than the real time, to compensate for timer in-accuracy */
1892 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 1893 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1894
8a1c38d1
EG		 1895 /* resolution of fairness timer */
1896 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1897 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1898 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 1899
8a1c38d1
EG		 1900 /* this is the threshold below which we won't arm the timer anymore */
1901 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 1902
8a1c38d1
EG		 1903 /* we multiply by 1e3/8 to get bytes/msec.
1904 We don't want the credits to pass a credit
1905 of the t_fair*FAIR_MEM (algorithm resolution) */
1906 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1907 /* since each tick is 4 usec */
1908 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 1909}
1910
2691d51d
EG		 1911/* Calculates the sum of vn_min_rates.
1912 It's needed for further normalizing of the min_rates.
1913 Returns:
1914 sum of vn_min_rates.
1915 or
1916 0 - if all the min_rates are 0.
1917 In the later case fainess algorithm should be deactivated.
1918 If not all min_rates are zero then those that are zeroes will be set to 1.
1919 */
1920static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1921{
1922 int all_zero = 1;
2691d51d
EG		 1923 int vn;
1924
1925 bp->vn_weight_sum = 0;
1926 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 1927 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 1928 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1929 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1930
1931 /* Skip hidden vns */
1932 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1933 continue;
1934
1935 /* If min rate is zero - set it to 1 */
1936 if (!vn_min_rate)
1937 vn_min_rate = DEF_MIN_RATE;
1938 else
1939 all_zero = 0;
1940
1941 bp->vn_weight_sum += vn_min_rate;
1942 }
1943
1944 /* ... only if all min rates are zeros - disable fairness */
b015e3d1
EG		 1945 if (all_zero) {
1946 bp->cmng.flags.cmng_enables &=
1947 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1948 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1949 " fairness will be disabled\n");
1950 } else
1951 bp->cmng.flags.cmng_enables |=
1952 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 1953}
1954
f2e0899f 1955static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 1956{
1957 struct rate_shaping_vars_per_vn m_rs_vn;
1958 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 1959 u32 vn_cfg = bp->mf_config[vn];
1960 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 1961 u16 vn_min_rate, vn_max_rate;
1962 int i;
1963
1964 /* If function is hidden - set min and max to zeroes */
1965 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1966 vn_min_rate = 0;
1967 vn_max_rate = 0;
1968
1969 } else {
faa6fcbb
DK		 1970 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
1971
34f80b04
EG		 1972 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1973 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 1974 /* If fairness is enabled (not all min rates are zeroes) and
1975 if current min rate is zero - set it to 1.
1976 This is a requirement of the algorithm. */
f2e0899f 1977 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 1978 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 1979
1980 if (IS_MF_SI(bp))
1981 /* maxCfg in percents of linkspeed */
1982 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
1983 else
1984 /* maxCfg is absolute in 100Mb units */
1985 vn_max_rate = maxCfg * 100;
34f80b04 1986 }
f85582f8 1987
8a1c38d1 1988 DP(NETIF_MSG_IFUP,
b015e3d1 1989 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 1990 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 1991
1992 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1993 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1994
1995 /* global vn counter - maximal Mbps for this vn */
1996 m_rs_vn.vn_counter.rate = vn_max_rate;
1997
1998 /* quota - number of bytes transmitted in this period */
1999 m_rs_vn.vn_counter.quota =
2000 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2001
8a1c38d1 2002 if (bp->vn_weight_sum) {
34f80b04
EG		 2003 /* credit for each period of the fairness algorithm:
2004 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2005 vn_weight_sum should not be larger than 10000, thus
2006 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2007 than zero */
34f80b04 2008 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2009 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2010 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2011 (bp->cmng.fair_vars.fair_threshold +
2012 MIN_ABOVE_THRESH));
cdaa7cb8 2013 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2014 m_fair_vn.vn_credit_delta);
2015 }
2016
34f80b04
EG		 2017 /* Store it to internal memory */
2018 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2019 REG_WR(bp, BAR_XSTRORM_INTMEM +
2020 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2021 ((u32 *)(&m_rs_vn))[i]);
2022
2023 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2024 REG_WR(bp, BAR_XSTRORM_INTMEM +
2025 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2026 ((u32 *)(&m_fair_vn))[i]);
2027}
f85582f8 2028
523224a3
DK		 2029static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2030{
2031 if (CHIP_REV_IS_SLOW(bp))
2032 return CMNG_FNS_NONE;
fb3bff17 2033 if (IS_MF(bp))
523224a3
DK		 2034 return CMNG_FNS_MINMAX;
2035
2036 return CMNG_FNS_NONE;
2037}
2038
2ae17f66 2039void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2040{
0793f83f 2041 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2042
2043 if (BP_NOMCP(bp))
2044 return; /* what should be the default bvalue in this case */
2045
0793f83f
DK		 2046 /* For 2 port configuration the absolute function number formula
2047 * is:
2048 * abs_func = 2 * vn + BP_PORT + BP_PATH
2049 *
2050 * and there are 4 functions per port
2051 *
2052 * For 4 port configuration it is
2053 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2054 *
2055 * and there are 2 functions per port
2056 */
523224a3 2057 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2058 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2059
2060 if (func >= E1H_FUNC_MAX)
2061 break;
2062
f2e0899f 2063 bp->mf_config[vn] =
523224a3
DK		 2064 MF_CFG_RD(bp, func_mf_config[func].config);
2065 }
2066}
2067
2068static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2069{
2070
2071 if (cmng_type == CMNG_FNS_MINMAX) {
2072 int vn;
2073
2074 /* clear cmng_enables */
2075 bp->cmng.flags.cmng_enables = 0;
2076
2077 /* read mf conf from shmem */
2078 if (read_cfg)
2079 bnx2x_read_mf_cfg(bp);
2080
2081 /* Init rate shaping and fairness contexts */
2082 bnx2x_init_port_minmax(bp);
2083
2084 /* vn_weight_sum and enable fairness if not 0 */
2085 bnx2x_calc_vn_weight_sum(bp);
2086
2087 /* calculate and set min-max rate for each vn */
c4154f25
DK		 2088 if (bp->port.pmf)
2089 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2090 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2091
2092 /* always enable rate shaping and fairness */
2093 bp->cmng.flags.cmng_enables |=
2094 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2095 if (!bp->vn_weight_sum)
2096 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2097 " fairness will be disabled\n");
2098 return;
2099 }
2100
2101 /* rate shaping and fairness are disabled */
2102 DP(NETIF_MSG_IFUP,
2103 "rate shaping and fairness are disabled\n");
2104}
34f80b04 2105
523224a3
DK		 2106static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2107{
2108 int port = BP_PORT(bp);
2109 int func;
2110 int vn;
2111
2112 /* Set the attention towards other drivers on the same port */
2113 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2114 if (vn == BP_E1HVN(bp))
2115 continue;
2116
2117 func = ((vn << 1) | port);
2118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2119 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2120 }
2121}
8a1c38d1 2122
c18487ee
YR		 2123/* This function is called upon link interrupt */
2124static void bnx2x_link_attn(struct bnx2x *bp)
2125{
bb2a0f7a
YG		 2126 /* Make sure that we are synced with the current statistics */
2127 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2128
c18487ee 2129 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2130
bb2a0f7a
YG		 2131 if (bp->link_vars.link_up) {
2132
1c06328c 2133 /* dropless flow control */
f2e0899f 2134 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2135 int port = BP_PORT(bp);
2136 u32 pause_enabled = 0;
2137
2138 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2139 pause_enabled = 1;
2140
2141 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2142 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2143 pause_enabled);
2144 }
2145
bb2a0f7a
YG		 2146 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2147 struct host_port_stats *pstats;
2148
2149 pstats = bnx2x_sp(bp, port_stats);
2150 /* reset old bmac stats */
2151 memset(&(pstats->mac_stx[0]), 0,
2152 sizeof(struct mac_stx));
2153 }
f34d28ea 2154 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2155 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2156 }
2157
f2e0899f
DK		 2158 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2159 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2160
f2e0899f
DK		 2161 if (cmng_fns != CMNG_FNS_NONE) {
2162 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2163 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2164 } else
2165 /* rate shaping and fairness are disabled */
2166 DP(NETIF_MSG_IFUP,
2167 "single function mode without fairness\n");
34f80b04 2168 }
9fdc3e95 2169
2ae17f66
VZ		 2170 __bnx2x_link_report(bp);
2171
9fdc3e95
DK		 2172 if (IS_MF(bp))
2173 bnx2x_link_sync_notify(bp);
c18487ee 2174}
a2fbb9ea 2175
9f6c9258 2176void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2177{
2ae17f66 2178 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2179 return;
a2fbb9ea 2180
c18487ee 2181 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2182
bb2a0f7a
YG		 2183 if (bp->link_vars.link_up)
2184 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2185 else
2186 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2187
c18487ee
YR		 2188 /* indicate link status */
2189 bnx2x_link_report(bp);
a2fbb9ea 2190}
a2fbb9ea 2191
34f80b04
EG		 2192static void bnx2x_pmf_update(struct bnx2x *bp)
2193{
2194 int port = BP_PORT(bp);
2195 u32 val;
2196
2197 bp->port.pmf = 1;
2198 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2199
2200 /* enable nig attention */
2201 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2202 if (bp->common.int_block == INT_BLOCK_HC) {
2203 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2204 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2205 } else if (CHIP_IS_E2(bp)) {
2206 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2207 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2208 }
bb2a0f7a
YG		 2209
2210 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2211}
2212
c18487ee 2213/* end of Link */
a2fbb9ea
ET		 2214
2215/* slow path */
2216
2217/*
2218 * General service functions
2219 */
2220
2691d51d 2221/* send the MCP a request, block until there is a reply */
a22f0788 2222u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2223{
f2e0899f 2224 int mb_idx = BP_FW_MB_IDX(bp);
2691d51d
EG		 2225 u32 seq = ++bp->fw_seq;
2226 u32 rc = 0;
2227 u32 cnt = 1;
2228 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2229
c4ff7cbf 2230 mutex_lock(&bp->fw_mb_mutex);
f2e0899f
DK		 2231 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2232 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2233
2691d51d
EG		 2234 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2235
2236 do {
2237 /* let the FW do it's magic ... */
2238 msleep(delay);
2239
f2e0899f 2240 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2241
c4ff7cbf
EG		 2242 /* Give the FW up to 5 second (500*10ms) */
2243 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2244
2245 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2246 cnt*delay, rc, seq);
2247
2248 /* is this a reply to our command? */
2249 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2250 rc &= FW_MSG_CODE_MASK;
2251 else {
2252 /* FW BUG! */
2253 BNX2X_ERR("FW failed to respond!\n");
2254 bnx2x_fw_dump(bp);
2255 rc = 0;
2256 }
c4ff7cbf 2257 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2258
2259 return rc;
2260}
2261
ec6ba945
VZ		 2262static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2263{
2264#ifdef BCM_CNIC
2265 if (IS_FCOE_FP(fp) && IS_MF(bp))
2266 return false;
2267#endif
2268 return true;
2269}
2270
523224a3 2271/* must be called under rtnl_lock */
8d96286a 2272static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2691d51d 2273{
523224a3 2274 u32 mask = (1 << cl_id);
2691d51d 2275
523224a3
DK		 2276 /* initial seeting is BNX2X_ACCEPT_NONE */
2277 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2278 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2279 u8 unmatched_unicast = 0;
2691d51d 2280
0793f83f
DK		 2281 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2282 unmatched_unicast = 1;
2283
523224a3
DK		 2284 if (filters & BNX2X_PROMISCUOUS_MODE) {
2285 /* promiscious - accept all, drop none */
2286 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2287 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
0793f83f
DK		 2288 if (IS_MF_SI(bp)) {
2289 /*
2290 * SI mode defines to accept in promiscuos mode
2291 * only unmatched packets
2292 */
2293 unmatched_unicast = 1;
2294 accp_all_ucast = 0;
2295 }
523224a3
DK		 2296 }
2297 if (filters & BNX2X_ACCEPT_UNICAST) {
2298 /* accept matched ucast */
2299 drop_all_ucast = 0;
2300 }
d9c8f498 2301 if (filters & BNX2X_ACCEPT_MULTICAST)
523224a3
DK		 2302 /* accept matched mcast */
2303 drop_all_mcast = 0;
d9c8f498 2304
523224a3
DK		 2305 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2306 /* accept all mcast */
2307 drop_all_ucast = 0;
2308 accp_all_ucast = 1;
2309 }
2310 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2311 /* accept all mcast */
2312 drop_all_mcast = 0;
2313 accp_all_mcast = 1;
2314 }
2315 if (filters & BNX2X_ACCEPT_BROADCAST) {
2316 /* accept (all) bcast */
2317 drop_all_bcast = 0;
2318 accp_all_bcast = 1;
2319 }
2691d51d 2320
523224a3
DK		 2321 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2322 bp->mac_filters.ucast_drop_all | mask :
2323 bp->mac_filters.ucast_drop_all & ~mask;
2691d51d 2324
523224a3
DK		 2325 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2326 bp->mac_filters.mcast_drop_all | mask :
2327 bp->mac_filters.mcast_drop_all & ~mask;
2691d51d 2328
523224a3
DK		 2329 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2330 bp->mac_filters.bcast_drop_all | mask :
2331 bp->mac_filters.bcast_drop_all & ~mask;
2691d51d 2332
523224a3
DK		 2333 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2334 bp->mac_filters.ucast_accept_all | mask :
2335 bp->mac_filters.ucast_accept_all & ~mask;
2691d51d 2336
523224a3
DK		 2337 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2338 bp->mac_filters.mcast_accept_all | mask :
2339 bp->mac_filters.mcast_accept_all & ~mask;
2340
2341 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2342 bp->mac_filters.bcast_accept_all | mask :
2343 bp->mac_filters.bcast_accept_all & ~mask;
2344
2345 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2346 bp->mac_filters.unmatched_unicast | mask :
2347 bp->mac_filters.unmatched_unicast & ~mask;
2691d51d
EG		 2348}
2349
8d96286a 2350static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2691d51d 2351{
030f3356
DK		 2352 struct tstorm_eth_function_common_config tcfg = {0};
2353 u16 rss_flgs;
2691d51d 2354
030f3356
DK		 2355 /* tpa */
2356 if (p->func_flgs & FUNC_FLG_TPA)
2357 tcfg.config_flags |=
2358 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2691d51d 2359
030f3356
DK		 2360 /* set rss flags */
2361 rss_flgs = (p->rss->mode <<
2362 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2363
2364 if (p->rss->cap & RSS_IPV4_CAP)
2365 rss_flgs |= RSS_IPV4_CAP_MASK;
2366 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2367 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2368 if (p->rss->cap & RSS_IPV6_CAP)
2369 rss_flgs |= RSS_IPV6_CAP_MASK;
2370 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2371 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2372
2373 tcfg.config_flags |= rss_flgs;
2374 tcfg.rss_result_mask = p->rss->result_mask;
2375
2376 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2691d51d 2377
523224a3
DK		 2378 /* Enable the function in the FW */
2379 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2380 storm_memset_func_en(bp, p->func_id, 1);
2691d51d 2381
523224a3
DK		 2382 /* statistics */
2383 if (p->func_flgs & FUNC_FLG_STATS) {
2384 struct stats_indication_flags stats_flags = {0};
2385 stats_flags.collect_eth = 1;
2691d51d 2386
523224a3
DK		 2387 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2388 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2389
523224a3
DK		 2390 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2391 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2392
523224a3
DK		 2393 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2394 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2395
523224a3
DK		 2396 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2397 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d
EG		 2398 }
2399
523224a3
DK		 2400 /* spq */
2401 if (p->func_flgs & FUNC_FLG_SPQ) {
2402 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2403 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2404 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2405 }
2691d51d
EG		 2406}
2407
523224a3
DK		 2408static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2409 struct bnx2x_fastpath *fp)
28912902 2410{
523224a3 2411 u16 flags = 0;
28912902 2412
523224a3
DK		 2413 /* calculate queue flags */
2414 flags |= QUEUE_FLG_CACHE_ALIGN;
2415 flags |= QUEUE_FLG_HC;
0793f83f 2416 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
28912902 2417
523224a3
DK		 2418 flags |= QUEUE_FLG_VLAN;
2419 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
523224a3
DK		 2420
2421 if (!fp->disable_tpa)
2422 flags |= QUEUE_FLG_TPA;
2423
ec6ba945
VZ		 2424 flags = stat_counter_valid(bp, fp) ?
2425 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
523224a3
DK		 2426
2427 return flags;
2428}
2429
2430static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2431 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2432 struct bnx2x_rxq_init_params *rxq_init)
2433{
2434 u16 max_sge = 0;
2435 u16 sge_sz = 0;
2436 u16 tpa_agg_size = 0;
2437
2438 /* calculate queue flags */
2439 u16 flags = bnx2x_get_cl_flags(bp, fp);
2440
2441 if (!fp->disable_tpa) {
2442 pause->sge_th_hi = 250;
2443 pause->sge_th_lo = 150;
2444 tpa_agg_size = min_t(u32,
2445 (min_t(u32, 8, MAX_SKB_FRAGS) *
2446 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2447 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2448 SGE_PAGE_SHIFT;
2449 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2450 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2451 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2452 0xffff);
2453 }
2454
2455 /* pause - not for e1 */
2456 if (!CHIP_IS_E1(bp)) {
2457 pause->bd_th_hi = 350;
2458 pause->bd_th_lo = 250;
2459 pause->rcq_th_hi = 350;
2460 pause->rcq_th_lo = 250;
2461 pause->sge_th_hi = 0;
2462 pause->sge_th_lo = 0;
2463 pause->pri_map = 1;
2464 }
2465
2466 /* rxq setup */
2467 rxq_init->flags = flags;
2468 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2469 rxq_init->dscr_map = fp->rx_desc_mapping;
2470 rxq_init->sge_map = fp->rx_sge_mapping;
2471 rxq_init->rcq_map = fp->rx_comp_mapping;
2472 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91
VZ		 2473
2474 /* Always use mini-jumbo MTU for FCoE L2 ring */
2475 if (IS_FCOE_FP(fp))
2476 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2477 else
2478 rxq_init->mtu = bp->dev->mtu;
2479
2480 rxq_init->buf_sz = fp->rx_buf_size;
523224a3
DK		 2481 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2482 rxq_init->cl_id = fp->cl_id;
2483 rxq_init->spcl_id = fp->cl_id;
2484 rxq_init->stat_id = fp->cl_id;
2485 rxq_init->tpa_agg_sz = tpa_agg_size;
2486 rxq_init->sge_buf_sz = sge_sz;
2487 rxq_init->max_sges_pkt = max_sge;
2488 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2489 rxq_init->fw_sb_id = fp->fw_sb_id;
2490
ec6ba945
VZ		 2491 if (IS_FCOE_FP(fp))
2492 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2493 else
2494 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
523224a3
DK		 2495
2496 rxq_init->cid = HW_CID(bp, fp->cid);
2497
2498 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2499}
2500
2501static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2502 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2503{
2504 u16 flags = bnx2x_get_cl_flags(bp, fp);
2505
2506 txq_init->flags = flags;
2507 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2508 txq_init->dscr_map = fp->tx_desc_mapping;
2509 txq_init->stat_id = fp->cl_id;
2510 txq_init->cid = HW_CID(bp, fp->cid);
2511 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2512 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2513 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945
VZ		 2514
2515 if (IS_FCOE_FP(fp)) {
2516 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2517 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2518 }
2519
523224a3
DK		 2520 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2521}
2522
8d96286a 2523static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2524{
2525 struct bnx2x_func_init_params func_init = {0};
2526 struct bnx2x_rss_params rss = {0};
2527 struct event_ring_data eq_data = { {0} };
2528 u16 flags;
2529
2530 /* pf specific setups */
2531 if (!CHIP_IS_E1(bp))
fb3bff17 2532 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
523224a3 2533
f2e0899f
DK		 2534 if (CHIP_IS_E2(bp)) {
2535 /* reset IGU PF statistics: MSIX + ATTN */
2536 /* PF */
2537 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2538 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2539 (CHIP_MODE_IS_4_PORT(bp) ?
2540 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2541 /* ATTN */
2542 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2543 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2544 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2545 (CHIP_MODE_IS_4_PORT(bp) ?
2546 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2547 }
2548
523224a3
DK		 2549 /* function setup flags */
2550 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2551
f2e0899f
DK		 2552 if (CHIP_IS_E1x(bp))
2553 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2554 else
2555 flags |= FUNC_FLG_TPA;
523224a3 2556
030f3356
DK		 2557 /* function setup */
2558
523224a3
DK		 2559 /**
2560 * Although RSS is meaningless when there is a single HW queue we
2561 * still need it enabled in order to have HW Rx hash generated.
523224a3 2562 */
030f3356
DK		 2563 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2564 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2565 rss.mode = bp->multi_mode;
2566 rss.result_mask = MULTI_MASK;
2567 func_init.rss = &rss;
523224a3
DK		 2568
2569 func_init.func_flgs = flags;
2570 func_init.pf_id = BP_FUNC(bp);
2571 func_init.func_id = BP_FUNC(bp);
2572 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2573 func_init.spq_map = bp->spq_mapping;
2574 func_init.spq_prod = bp->spq_prod_idx;
2575
2576 bnx2x_func_init(bp, &func_init);
2577
2578 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2579
2580 /*
2581 Congestion management values depend on the link rate
2582 There is no active link so initial link rate is set to 10 Gbps.
2583 When the link comes up The congestion management values are
2584 re-calculated according to the actual link rate.
2585 */
2586 bp->link_vars.line_speed = SPEED_10000;
2587 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2588
2589 /* Only the PMF sets the HW */
2590 if (bp->port.pmf)
2591 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2592
2593 /* no rx until link is up */
2594 bp->rx_mode = BNX2X_RX_MODE_NONE;
2595 bnx2x_set_storm_rx_mode(bp);
2596
2597 /* init Event Queue */
2598 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2599 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2600 eq_data.producer = bp->eq_prod;
2601 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2602 eq_data.sb_id = DEF_SB_ID;
2603 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2604}
2605
2606
2607static void bnx2x_e1h_disable(struct bnx2x *bp)
2608{
2609 int port = BP_PORT(bp);
2610
2611 netif_tx_disable(bp->dev);
2612
2613 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2614
2615 netif_carrier_off(bp->dev);
2616}
2617
2618static void bnx2x_e1h_enable(struct bnx2x *bp)
2619{
2620 int port = BP_PORT(bp);
2621
2622 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2623
2624 /* Tx queue should be only reenabled */
2625 netif_tx_wake_all_queues(bp->dev);
2626
2627 /*
2628 * Should not call netif_carrier_on since it will be called if the link
2629 * is up when checking for link state
2630 */
2631}
2632
0793f83f
DK		 2633/* called due to MCP event (on pmf):
2634 * reread new bandwidth configuration
2635 * configure FW
2636 * notify others function about the change
2637 */
2638static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2639{
2640 if (bp->link_vars.link_up) {
2641 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2642 bnx2x_link_sync_notify(bp);
2643 }
2644 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2645}
2646
2647static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2648{
2649 bnx2x_config_mf_bw(bp);
2650 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2651}
2652
523224a3
DK		 2653static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2654{
2655 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2656
2657 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2658
2659 /*
2660 * This is the only place besides the function initialization
2661 * where the bp->flags can change so it is done without any
2662 * locks
2663 */
f2e0899f 2664 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2665 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2666 bp->flags |= MF_FUNC_DIS;
2667
2668 bnx2x_e1h_disable(bp);
2669 } else {
2670 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2671 bp->flags &= ~MF_FUNC_DIS;
2672
2673 bnx2x_e1h_enable(bp);
2674 }
2675 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2676 }
2677 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2678 bnx2x_config_mf_bw(bp);
523224a3
DK		 2679 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2680 }
2681
2682 /* Report results to MCP */
2683 if (dcc_event)
2684 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2685 else
2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2687}
2688
2689/* must be called under the spq lock */
2690static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2691{
2692 struct eth_spe *next_spe = bp->spq_prod_bd;
2693
2694 if (bp->spq_prod_bd == bp->spq_last_bd) {
2695 bp->spq_prod_bd = bp->spq;
2696 bp->spq_prod_idx = 0;
2697 DP(NETIF_MSG_TIMER, "end of spq\n");
2698 } else {
2699 bp->spq_prod_bd++;
2700 bp->spq_prod_idx++;
2701 }
2702 return next_spe;
2703}
2704
2705/* must be called under the spq lock */
28912902
MC		 2706static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2707{
2708 int func = BP_FUNC(bp);
2709
2710 /* Make sure that BD data is updated before writing the producer */
2711 wmb();
2712
523224a3 2713 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2714 bp->spq_prod_idx);
28912902
MC		 2715 mmiowb();
2716}
2717
a2fbb9ea 2718/* the slow path queue is odd since completions arrive on the fastpath ring */
9f6c9258 2719int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
f85582f8 2720 u32 data_hi, u32 data_lo, int common)
a2fbb9ea 2721{
28912902 2722 struct eth_spe *spe;
523224a3 2723 u16 type;
a2fbb9ea 2724
a2fbb9ea
ET		 2725#ifdef BNX2X_STOP_ON_ERROR
2726 if (unlikely(bp->panic))
2727 return -EIO;
2728#endif
2729
34f80b04 2730 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 2731
6e30dd4e
VZ		 2732 if (common) {
2733 if (!atomic_read(&bp->eq_spq_left)) {
2734 BNX2X_ERR("BUG! EQ ring full!\n");
2735 spin_unlock_bh(&bp->spq_lock);
2736 bnx2x_panic();
2737 return -EBUSY;
2738 }
2739 } else if (!atomic_read(&bp->cq_spq_left)) {
2740 BNX2X_ERR("BUG! SPQ ring full!\n");
2741 spin_unlock_bh(&bp->spq_lock);
2742 bnx2x_panic();
2743 return -EBUSY;
a2fbb9ea 2744 }
f1410647 2745
28912902
MC		 2746 spe = bnx2x_sp_get_next(bp);
2747
a2fbb9ea 2748 /* CID needs port number to be encoded int it */
28912902 2749 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 2750 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2751 HW_CID(bp, cid));
523224a3 2752
a2fbb9ea 2753 if (common)
523224a3
DK		 2754 /* Common ramrods:
2755 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2756 * TRAFFIC_STOP, TRAFFIC_START
2757 */
2758 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2759 & SPE_HDR_CONN_TYPE;
2760 else
2761 /* ETH ramrods: SETUP, HALT */
2762 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2763 & SPE_HDR_CONN_TYPE;
a2fbb9ea 2764
523224a3
DK		 2765 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2766 SPE_HDR_FUNCTION_ID);
a2fbb9ea 2767
523224a3
DK		 2768 spe->hdr.type = cpu_to_le16(type);
2769
2770 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2771 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2772
2773 /* stats ramrod has it's own slot on the spq */
6e30dd4e 2774 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
523224a3
DK		 2775 /* It's ok if the actual decrement is issued towards the memory
2776 * somewhere between the spin_lock and spin_unlock. Thus no
2777 * more explict memory barrier is needed.
2778 */
6e30dd4e
VZ		 2779 if (common)
2780 atomic_dec(&bp->eq_spq_left);
2781 else
2782 atomic_dec(&bp->cq_spq_left);
2783 }
2784
a2fbb9ea 2785
cdaa7cb8 2786 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3 2787 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
6e30dd4e 2788 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
cdaa7cb8
VZ		 2789 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2790 (u32)(U64_LO(bp->spq_mapping) +
2791 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
6e30dd4e
VZ		 2792 HW_CID(bp, cid), data_hi, data_lo, type,
2793 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 2794
28912902 2795 bnx2x_sp_prod_update(bp);
34f80b04 2796 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2797 return 0;
2798}
2799
2800/* acquire split MCP access lock register */
4a37fb66 2801static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 2802{
72fd0718 2803 u32 j, val;
34f80b04 2804 int rc = 0;
a2fbb9ea
ET		 2805
2806 might_sleep();
72fd0718 2807 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 2808 val = (1UL << 31);
2809 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2810 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2811 if (val & (1L << 31))
2812 break;
2813
2814 msleep(5);
2815 }
a2fbb9ea 2816 if (!(val & (1L << 31))) {
19680c48 2817 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 2818 rc = -EBUSY;
2819 }
2820
2821 return rc;
2822}
2823
4a37fb66
YG		 2824/* release split MCP access lock register */
2825static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 2826{
72fd0718 2827 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 2828}
2829
523224a3
DK		 2830#define BNX2X_DEF_SB_ATT_IDX 0x0001
2831#define BNX2X_DEF_SB_IDX 0x0002
2832
a2fbb9ea
ET		 2833static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2834{
523224a3 2835 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 2836 u16 rc = 0;
2837
2838 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 2839 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2840 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 2841 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 2842 }
523224a3
DK		 2843
2844 if (bp->def_idx != def_sb->sp_sb.running_index) {
2845 bp->def_idx = def_sb->sp_sb.running_index;
2846 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 2847 }
523224a3
DK		 2848
2849 /* Do not reorder: indecies reading should complete before handling */
2850 barrier();
a2fbb9ea
ET		 2851 return rc;
2852}
2853
2854/*
2855 * slow path service functions
2856 */
2857
2858static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2859{
34f80b04 2860 int port = BP_PORT(bp);
a2fbb9ea
ET		 2861 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2862 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 2863 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2864 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 2865 u32 aeu_mask;
87942b46 2866 u32 nig_mask = 0;
f2e0899f 2867 u32 reg_addr;
a2fbb9ea 2868
a2fbb9ea
ET		 2869 if (bp->attn_state & asserted)
2870 BNX2X_ERR("IGU ERROR\n");
2871
3fcaf2e5
EG		 2872 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2873 aeu_mask = REG_RD(bp, aeu_addr);
2874
a2fbb9ea 2875 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 2876 aeu_mask, asserted);
72fd0718 2877 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 2878 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 2879
3fcaf2e5
EG		 2880 REG_WR(bp, aeu_addr, aeu_mask);
2881 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 2882
3fcaf2e5 2883 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 2884 bp->attn_state |= asserted;
3fcaf2e5 2885 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 2886
2887 if (asserted & ATTN_HARD_WIRED_MASK) {
2888 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 2889
a5e9a7cf
EG		 2890 bnx2x_acquire_phy_lock(bp);
2891
877e9aa4 2892 /* save nig interrupt mask */
87942b46 2893 nig_mask = REG_RD(bp, nig_int_mask_addr);
877e9aa4 2894 REG_WR(bp, nig_int_mask_addr, 0);
a2fbb9ea 2895
c18487ee 2896 bnx2x_link_attn(bp);
a2fbb9ea
ET		 2897
2898 /* handle unicore attn? */
2899 }
2900 if (asserted & ATTN_SW_TIMER_4_FUNC)
2901 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2902
2903 if (asserted & GPIO_2_FUNC)
2904 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2905
2906 if (asserted & GPIO_3_FUNC)
2907 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2908
2909 if (asserted & GPIO_4_FUNC)
2910 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2911
2912 if (port == 0) {
2913 if (asserted & ATTN_GENERAL_ATTN_1) {
2914 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2915 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2916 }
2917 if (asserted & ATTN_GENERAL_ATTN_2) {
2918 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2919 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2920 }
2921 if (asserted & ATTN_GENERAL_ATTN_3) {
2922 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2923 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2924 }
2925 } else {
2926 if (asserted & ATTN_GENERAL_ATTN_4) {
2927 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2928 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2929 }
2930 if (asserted & ATTN_GENERAL_ATTN_5) {
2931 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2932 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2933 }
2934 if (asserted & ATTN_GENERAL_ATTN_6) {
2935 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2936 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2937 }
2938 }
2939
2940 } /* if hardwired */
2941
f2e0899f
DK		 2942 if (bp->common.int_block == INT_BLOCK_HC)
2943 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2944 COMMAND_REG_ATTN_BITS_SET);
2945 else
2946 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2947
2948 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2949 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2950 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 2951
2952 /* now set back the mask */
a5e9a7cf 2953 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 2954 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 2955 bnx2x_release_phy_lock(bp);
2956 }
a2fbb9ea
ET		 2957}
2958
fd4ef40d
EG		 2959static inline void bnx2x_fan_failure(struct bnx2x *bp)
2960{
2961 int port = BP_PORT(bp);
b7737c9b 2962 u32 ext_phy_config;
fd4ef40d 2963 /* mark the failure */
b7737c9b
YR		 2964 ext_phy_config =
2965 SHMEM_RD(bp,
2966 dev_info.port_hw_config[port].external_phy_config);
2967
2968 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2969 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 2970 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 2971 ext_phy_config);
fd4ef40d
EG		 2972
2973 /* log the failure */
cdaa7cb8
VZ		 2974 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2975 " the driver to shutdown the card to prevent permanent"
2976 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 2977}
ab6ad5a4 2978
877e9aa4 2979static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 2980{
34f80b04 2981 int port = BP_PORT(bp);
877e9aa4 2982 int reg_offset;
d90d96ba 2983 u32 val;
877e9aa4 2984
34f80b04
EG		 2985 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2986 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 2987
34f80b04 2988 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 2989
2990 val = REG_RD(bp, reg_offset);
2991 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2992 REG_WR(bp, reg_offset, val);
2993
2994 BNX2X_ERR("SPIO5 hw attention\n");
2995
fd4ef40d 2996 /* Fan failure attention */
d90d96ba 2997 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 2998 bnx2x_fan_failure(bp);
877e9aa4 2999 }
34f80b04 3000
589abe3a
EG		 3001 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3002 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3003 bnx2x_acquire_phy_lock(bp);
3004 bnx2x_handle_module_detect_int(&bp->link_params);
3005 bnx2x_release_phy_lock(bp);
3006 }
3007
34f80b04
EG		 3008 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3009
3010 val = REG_RD(bp, reg_offset);
3011 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3012 REG_WR(bp, reg_offset, val);
3013
3014 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3015 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3016 bnx2x_panic();
3017 }
877e9aa4
ET		 3018}
3019
3020static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3021{
3022 u32 val;
3023
0626b899 3024 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3025
3026 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3027 BNX2X_ERR("DB hw attention 0x%x\n", val);
3028 /* DORQ discard attention */
3029 if (val & 0x2)
3030 BNX2X_ERR("FATAL error from DORQ\n");
3031 }
34f80b04
EG		 3032
3033 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3034
3035 int port = BP_PORT(bp);
3036 int reg_offset;
3037
3038 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3039 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3040
3041 val = REG_RD(bp, reg_offset);
3042 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3043 REG_WR(bp, reg_offset, val);
3044
3045 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3046 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3047 bnx2x_panic();
3048 }
877e9aa4
ET		 3049}
3050
3051static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3052{
3053 u32 val;
3054
3055 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3056
3057 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3058 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3059 /* CFC error attention */
3060 if (val & 0x2)
3061 BNX2X_ERR("FATAL error from CFC\n");
3062 }
3063
3064 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3065
3066 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3067 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3068 /* RQ_USDMDP_FIFO_OVERFLOW */
3069 if (val & 0x18000)
3070 BNX2X_ERR("FATAL error from PXP\n");
f2e0899f
DK		 3071 if (CHIP_IS_E2(bp)) {
3072 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3073 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3074 }
877e9aa4 3075 }
34f80b04
EG		 3076
3077 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3078
3079 int port = BP_PORT(bp);
3080 int reg_offset;
3081
3082 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3083 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3084
3085 val = REG_RD(bp, reg_offset);
3086 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3087 REG_WR(bp, reg_offset, val);
3088
3089 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3090 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3091 bnx2x_panic();
3092 }
877e9aa4
ET		 3093}
3094
3095static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3096{
34f80b04
EG		 3097 u32 val;
3098
877e9aa4
ET		 3099 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3100
34f80b04
EG		 3101 if (attn & BNX2X_PMF_LINK_ASSERT) {
3102 int func = BP_FUNC(bp);
3103
3104 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3105 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3106 func_mf_config[BP_ABS_FUNC(bp)].config);
3107 val = SHMEM_RD(bp,
3108 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3109 if (val & DRV_STATUS_DCC_EVENT_MASK)
3110 bnx2x_dcc_event(bp,
3111 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3112
3113 if (val & DRV_STATUS_SET_MF_BW)
3114 bnx2x_set_mf_bw(bp);
3115
2691d51d 3116 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3117 bnx2x_pmf_update(bp);
3118
2ae17f66
VZ		 3119 /* Always call it here: bnx2x_link_report() will
3120 * prevent the link indication duplication.
3121 */
3122 bnx2x__link_status_update(bp);
3123
e4901dde 3124 if (bp->port.pmf &&
785b9b1a
SR		 3125 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3126 bp->dcbx_enabled > 0)
e4901dde
VZ		 3127 /* start dcbx state machine */
3128 bnx2x_dcbx_set_params(bp,
3129 BNX2X_DCBX_STATE_NEG_RECEIVED);
34f80b04 3130 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3131
3132 BNX2X_ERR("MC assert!\n");
3133 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3134 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3135 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3136 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3137 bnx2x_panic();
3138
3139 } else if (attn & BNX2X_MCP_ASSERT) {
3140
3141 BNX2X_ERR("MCP assert!\n");
3142 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3143 bnx2x_fw_dump(bp);
877e9aa4
ET		 3144
3145 } else
3146 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3147 }
3148
3149 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3150 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3151 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3152 val = CHIP_IS_E1(bp) ? 0 :
3153 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3154 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3155 }
3156 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3157 val = CHIP_IS_E1(bp) ? 0 :
3158 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3159 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3160 }
877e9aa4 3161 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3162 }
3163}
3164
72fd0718
VZ		 3165#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3166#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3167#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3168#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3169#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
f85582f8 3170
72fd0718
VZ		 3171/*
3172 * should be run under rtnl lock
3173 */
3174static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3175{
3176 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3177 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3178 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3179 barrier();
3180 mmiowb();
3181}
3182
3183/*
3184 * should be run under rtnl lock
3185 */
3186static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3187{
3188 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3189 val |= (1 << 16);
3190 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3191 barrier();
3192 mmiowb();
3193}
3194
3195/*
3196 * should be run under rtnl lock
3197 */
9f6c9258 3198bool bnx2x_reset_is_done(struct bnx2x *bp)
72fd0718
VZ		 3199{
3200 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3201 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3202 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3203}
3204
3205/*
3206 * should be run under rtnl lock
3207 */
9f6c9258 3208inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3209{
3210 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3211
3212 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3213
3214 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3215 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3216 barrier();
3217 mmiowb();
3218}
3219
3220/*
3221 * should be run under rtnl lock
3222 */
9f6c9258 3223u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3224{
3225 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3226
3227 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3228
3229 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3230 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3231 barrier();
3232 mmiowb();
3233
3234 return val1;
3235}
3236
3237/*
3238 * should be run under rtnl lock
3239 */
3240static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3241{
3242 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3243}
3244
3245static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3246{
3247 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3248 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3249}
3250
3251static inline void _print_next_block(int idx, const char *blk)
3252{
3253 if (idx)
3254 pr_cont(", ");
3255 pr_cont("%s", blk);
3256}
3257
3258static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3259{
3260 int i = 0;
3261 u32 cur_bit = 0;
3262 for (i = 0; sig; i++) {
3263 cur_bit = ((u32)0x1 << i);
3264 if (sig & cur_bit) {
3265 switch (cur_bit) {
3266 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3267 _print_next_block(par_num++, "BRB");
3268 break;
3269 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3270 _print_next_block(par_num++, "PARSER");
3271 break;
3272 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3273 _print_next_block(par_num++, "TSDM");
3274 break;
3275 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3276 _print_next_block(par_num++, "SEARCHER");
3277 break;
3278 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3279 _print_next_block(par_num++, "TSEMI");
3280 break;
3281 }
3282
3283 /* Clear the bit */
3284 sig &= ~cur_bit;
3285 }
3286 }
3287
3288 return par_num;
3289}
3290
3291static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3292{
3293 int i = 0;
3294 u32 cur_bit = 0;
3295 for (i = 0; sig; i++) {
3296 cur_bit = ((u32)0x1 << i);
3297 if (sig & cur_bit) {
3298 switch (cur_bit) {
3299 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3300 _print_next_block(par_num++, "PBCLIENT");
3301 break;
3302 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3303 _print_next_block(par_num++, "QM");
3304 break;
3305 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3306 _print_next_block(par_num++, "XSDM");
3307 break;
3308 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3309 _print_next_block(par_num++, "XSEMI");
3310 break;
3311 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3312 _print_next_block(par_num++, "DOORBELLQ");
3313 break;
3314 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3315 _print_next_block(par_num++, "VAUX PCI CORE");
3316 break;
3317 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3318 _print_next_block(par_num++, "DEBUG");
3319 break;
3320 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3321 _print_next_block(par_num++, "USDM");
3322 break;
3323 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3324 _print_next_block(par_num++, "USEMI");
3325 break;
3326 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3327 _print_next_block(par_num++, "UPB");
3328 break;
3329 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3330 _print_next_block(par_num++, "CSDM");
3331 break;
3332 }
3333
3334 /* Clear the bit */
3335 sig &= ~cur_bit;
3336 }
3337 }
3338
3339 return par_num;
3340}
3341
3342static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3343{
3344 int i = 0;
3345 u32 cur_bit = 0;
3346 for (i = 0; sig; i++) {
3347 cur_bit = ((u32)0x1 << i);
3348 if (sig & cur_bit) {
3349 switch (cur_bit) {
3350 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3351 _print_next_block(par_num++, "CSEMI");
3352 break;
3353 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3354 _print_next_block(par_num++, "PXP");
3355 break;
3356 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3357 _print_next_block(par_num++,
3358 "PXPPCICLOCKCLIENT");
3359 break;
3360 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3361 _print_next_block(par_num++, "CFC");
3362 break;
3363 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3364 _print_next_block(par_num++, "CDU");
3365 break;
3366 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3367 _print_next_block(par_num++, "IGU");
3368 break;
3369 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3370 _print_next_block(par_num++, "MISC");
3371 break;
3372 }
3373
3374 /* Clear the bit */
3375 sig &= ~cur_bit;
3376 }
3377 }
3378
3379 return par_num;
3380}
3381
3382static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3383{
3384 int i = 0;
3385 u32 cur_bit = 0;
3386 for (i = 0; sig; i++) {
3387 cur_bit = ((u32)0x1 << i);
3388 if (sig & cur_bit) {
3389 switch (cur_bit) {
3390 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3391 _print_next_block(par_num++, "MCP ROM");
3392 break;
3393 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3394 _print_next_block(par_num++, "MCP UMP RX");
3395 break;
3396 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3397 _print_next_block(par_num++, "MCP UMP TX");
3398 break;
3399 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3400 _print_next_block(par_num++, "MCP SCPAD");
3401 break;
3402 }
3403
3404 /* Clear the bit */
3405 sig &= ~cur_bit;
3406 }
3407 }
3408
3409 return par_num;
3410}
3411
3412static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3413 u32 sig2, u32 sig3)
3414{
3415 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3416 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3417 int par_num = 0;
3418 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3419 "[0]:0x%08x [1]:0x%08x "
3420 "[2]:0x%08x [3]:0x%08x\n",
3421 sig0 & HW_PRTY_ASSERT_SET_0,
3422 sig1 & HW_PRTY_ASSERT_SET_1,
3423 sig2 & HW_PRTY_ASSERT_SET_2,
3424 sig3 & HW_PRTY_ASSERT_SET_3);
3425 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3426 bp->dev->name);
3427 par_num = bnx2x_print_blocks_with_parity0(
3428 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3429 par_num = bnx2x_print_blocks_with_parity1(
3430 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3431 par_num = bnx2x_print_blocks_with_parity2(
3432 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3433 par_num = bnx2x_print_blocks_with_parity3(
3434 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3435 printk("\n");
3436 return true;
3437 } else
3438 return false;
3439}
3440
9f6c9258 3441bool bnx2x_chk_parity_attn(struct bnx2x *bp)
877e9aa4 3442{
a2fbb9ea 3443 struct attn_route attn;
72fd0718
VZ		 3444 int port = BP_PORT(bp);
3445
3446 attn.sig[0] = REG_RD(bp,
3447 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3448 port*4);
3449 attn.sig[1] = REG_RD(bp,
3450 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3451 port*4);
3452 attn.sig[2] = REG_RD(bp,
3453 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3454 port*4);
3455 attn.sig[3] = REG_RD(bp,
3456 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3457 port*4);
3458
3459 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3460 attn.sig[3]);
3461}
3462
f2e0899f
DK		 3463
3464static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3465{
3466 u32 val;
3467 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3468
3469 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3470 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3471 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3472 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3473 "ADDRESS_ERROR\n");
3474 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3475 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3476 "INCORRECT_RCV_BEHAVIOR\n");
3477 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3478 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3479 "WAS_ERROR_ATTN\n");
3480 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3481 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3482 "VF_LENGTH_VIOLATION_ATTN\n");
3483 if (val &
3484 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3485 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3486 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3487 if (val &
3488 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3489 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3490 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3491 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3492 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3493 "TCPL_ERROR_ATTN\n");
3494 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3495 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3496 "TCPL_IN_TWO_RCBS_ATTN\n");
3497 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3498 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3499 "CSSNOOP_FIFO_OVERFLOW\n");
3500 }
3501 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3502 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3503 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3504 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3505 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3506 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3507 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3508 "_ATC_TCPL_TO_NOT_PEND\n");
3509 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3510 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3511 "ATC_GPA_MULTIPLE_HITS\n");
3512 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3513 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3514 "ATC_RCPL_TO_EMPTY_CNT\n");
3515 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3516 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3517 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3518 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3519 "ATC_IREQ_LESS_THAN_STU\n");
3520 }
3521
3522 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3523 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3524 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3525 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3526 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3527 }
3528
3529}
3530
72fd0718
VZ		 3531static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3532{
3533 struct attn_route attn, *group_mask;
34f80b04 3534 int port = BP_PORT(bp);
877e9aa4 3535 int index;
a2fbb9ea
ET		 3536 u32 reg_addr;
3537 u32 val;
3fcaf2e5 3538 u32 aeu_mask;
a2fbb9ea
ET		 3539
3540 /* need to take HW lock because MCP or other port might also
3541 try to handle this event */
4a37fb66 3542 bnx2x_acquire_alr(bp);
a2fbb9ea 3543
4a33bc03 3544 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
72fd0718
VZ		 3545 bp->recovery_state = BNX2X_RECOVERY_INIT;
3546 bnx2x_set_reset_in_progress(bp);
3547 schedule_delayed_work(&bp->reset_task, 0);
3548 /* Disable HW interrupts */
3549 bnx2x_int_disable(bp);
3550 bnx2x_release_alr(bp);
3551 /* In case of parity errors don't handle attentions so that
3552 * other function would "see" parity errors.
3553 */
3554 return;
3555 }
3556
a2fbb9ea
ET		 3557 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3558 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3559 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3560 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
f2e0899f
DK		 3561 if (CHIP_IS_E2(bp))
3562 attn.sig[4] =
3563 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3564 else
3565 attn.sig[4] = 0;
3566
3567 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3568 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 3569
3570 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3571 if (deasserted & (1 << index)) {
72fd0718 3572 group_mask = &bp->attn_group[index];
a2fbb9ea 3573
f2e0899f
DK		 3574 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3575 "%08x %08x %08x\n",
3576 index,
3577 group_mask->sig[0], group_mask->sig[1],
3578 group_mask->sig[2], group_mask->sig[3],
3579 group_mask->sig[4]);
a2fbb9ea 3580
f2e0899f
DK		 3581 bnx2x_attn_int_deasserted4(bp,
3582 attn.sig[4] & group_mask->sig[4]);
877e9aa4 3583 bnx2x_attn_int_deasserted3(bp,
72fd0718 3584 attn.sig[3] & group_mask->sig[3]);
877e9aa4 3585 bnx2x_attn_int_deasserted1(bp,
72fd0718 3586 attn.sig[1] & group_mask->sig[1]);
877e9aa4 3587 bnx2x_attn_int_deasserted2(bp,
72fd0718 3588 attn.sig[2] & group_mask->sig[2]);
877e9aa4 3589 bnx2x_attn_int_deasserted0(bp,
72fd0718 3590 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 3591 }
3592 }
3593
4a37fb66 3594 bnx2x_release_alr(bp);
a2fbb9ea 3595
f2e0899f
DK		 3596 if (bp->common.int_block == INT_BLOCK_HC)
3597 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3598 COMMAND_REG_ATTN_BITS_CLR);
3599 else
3600 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 3601
3602 val = ~deasserted;
f2e0899f
DK		 3603 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3604 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 3605 REG_WR(bp, reg_addr, val);
a2fbb9ea 3606
a2fbb9ea 3607 if (~bp->attn_state & deasserted)
3fcaf2e5 3608 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 3609
3610 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3611 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3612
3fcaf2e5
EG		 3613 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3614 aeu_mask = REG_RD(bp, reg_addr);
3615
3616 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3617 aeu_mask, deasserted);
72fd0718 3618 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 3619 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3620
3fcaf2e5
EG		 3621 REG_WR(bp, reg_addr, aeu_mask);
3622 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 3623
3624 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3625 bp->attn_state &= ~deasserted;
3626 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3627}
3628
3629static void bnx2x_attn_int(struct bnx2x *bp)
3630{
3631 /* read local copy of bits */
68d59484
EG		 3632 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3633 attn_bits);
3634 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3635 attn_bits_ack);
a2fbb9ea
ET		 3636 u32 attn_state = bp->attn_state;
3637
3638 /* look for changed bits */
3639 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3640 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3641
3642 DP(NETIF_MSG_HW,
3643 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3644 attn_bits, attn_ack, asserted, deasserted);
3645
3646 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 3647 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 3648
3649 /* handle bits that were raised */
3650 if (asserted)
3651 bnx2x_attn_int_asserted(bp, asserted);
3652
3653 if (deasserted)
3654 bnx2x_attn_int_deasserted(bp, deasserted);
3655}
3656
523224a3
DK		 3657static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3658{
3659 /* No memory barriers */
3660 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3661 mmiowb(); /* keep prod updates ordered */
3662}
3663
3664#ifdef BCM_CNIC
3665static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3666 union event_ring_elem *elem)
3667{
3668 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 3669 (cid < bp->cnic_eth_dev.starting_cid &&
3670 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 3671 return 1;
3672
3673 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3674
3675 if (unlikely(elem->message.data.cfc_del_event.error)) {
3676 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3677 cid);
3678 bnx2x_panic_dump(bp);
3679 }
3680 bnx2x_cnic_cfc_comp(bp, cid);
3681 return 0;
3682}
3683#endif
3684
3685static void bnx2x_eq_int(struct bnx2x *bp)
3686{
3687 u16 hw_cons, sw_cons, sw_prod;
3688 union event_ring_elem *elem;
3689 u32 cid;
3690 u8 opcode;
3691 int spqe_cnt = 0;
3692
3693 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3694
3695 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3696 * when we get the the next-page we nned to adjust so the loop
3697 * condition below will be met. The next element is the size of a
3698 * regular element and hence incrementing by 1
3699 */
3700 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3701 hw_cons++;
3702
25985edc 3703 /* This function may never run in parallel with itself for a
523224a3
DK		 3704 * specific bp, thus there is no need in "paired" read memory
3705 * barrier here.
3706 */
3707 sw_cons = bp->eq_cons;
3708 sw_prod = bp->eq_prod;
3709
6e30dd4e
VZ		 3710 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3711 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 3712
3713 for (; sw_cons != hw_cons;
3714 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3715
3716
3717 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3718
3719 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3720 opcode = elem->message.opcode;
3721
3722
3723 /* handle eq element */
3724 switch (opcode) {
3725 case EVENT_RING_OPCODE_STAT_QUERY:
3726 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3727 /* nothing to do with stats comp */
3728 continue;
3729
3730 case EVENT_RING_OPCODE_CFC_DEL:
3731 /* handle according to cid range */
3732 /*
3733 * we may want to verify here that the bp state is
3734 * HALTING
3735 */
3736 DP(NETIF_MSG_IFDOWN,
3737 "got delete ramrod for MULTI[%d]\n", cid);
3738#ifdef BCM_CNIC
3739 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3740 goto next_spqe;
ec6ba945
VZ		 3741 if (cid == BNX2X_FCOE_ETH_CID)
3742 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3743 else
523224a3 3744#endif
ec6ba945 3745 bnx2x_fp(bp, cid, state) =
523224a3
DK		 3746 BNX2X_FP_STATE_CLOSED;
3747
3748 goto next_spqe;
e4901dde
VZ		 3749
3750 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3751 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3752 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3753 goto next_spqe;
3754 case EVENT_RING_OPCODE_START_TRAFFIC:
3755 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3756 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3757 goto next_spqe;
523224a3
DK		 3758 }
3759
3760 switch (opcode | bp->state) {
3761 case (EVENT_RING_OPCODE_FUNCTION_START |
3762 BNX2X_STATE_OPENING_WAIT4_PORT):
3763 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3764 bp->state = BNX2X_STATE_FUNC_STARTED;
3765 break;
3766
3767 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3768 BNX2X_STATE_CLOSING_WAIT4_HALT):
3769 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3770 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3771 break;
3772
3773 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3774 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3775 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
6e30dd4e
VZ		 3776 if (elem->message.data.set_mac_event.echo)
3777 bp->set_mac_pending = 0;
523224a3
DK		 3778 break;
3779
3780 case (EVENT_RING_OPCODE_SET_MAC |
3781 BNX2X_STATE_CLOSING_WAIT4_HALT):
3782 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
6e30dd4e
VZ		 3783 if (elem->message.data.set_mac_event.echo)
3784 bp->set_mac_pending = 0;
523224a3
DK		 3785 break;
3786 default:
3787 /* unknown event log error and continue */
3788 BNX2X_ERR("Unknown EQ event %d\n",
3789 elem->message.opcode);
3790 }
3791next_spqe:
3792 spqe_cnt++;
3793 } /* for */
3794
8fe23fbd 3795 smp_mb__before_atomic_inc();
6e30dd4e 3796 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 3797
3798 bp->eq_cons = sw_cons;
3799 bp->eq_prod = sw_prod;
3800 /* Make sure that above mem writes were issued towards the memory */
3801 smp_wmb();
3802
3803 /* update producer */
3804 bnx2x_update_eq_prod(bp, bp->eq_prod);
3805}
3806
a2fbb9ea
ET		 3807static void bnx2x_sp_task(struct work_struct *work)
3808{
1cf167f2 3809 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 3810 u16 status;
3811
3812 /* Return here if interrupt is disabled */
3813 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3814 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3815 return;
3816 }
3817
3818 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 3819/* if (status == 0) */
3820/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 3821
cdaa7cb8 3822 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 3823
877e9aa4 3824 /* HW attentions */
523224a3 3825 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 3826 bnx2x_attn_int(bp);
523224a3 3827 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 3828 }
3829
523224a3
DK		 3830 /* SP events: STAT_QUERY and others */
3831 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 3832#ifdef BCM_CNIC
3833 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 3834
ec6ba945
VZ		 3835 if ((!NO_FCOE(bp)) &&
3836 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3837 napi_schedule(&bnx2x_fcoe(bp, napi));
3838#endif
523224a3
DK		 3839 /* Handle EQ completions */
3840 bnx2x_eq_int(bp);
3841
3842 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3843 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3844
3845 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 3846 }
3847
3848 if (unlikely(status))
3849 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3850 status);
a2fbb9ea 3851
523224a3
DK		 3852 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3853 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 3854}
3855
9f6c9258 3856irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 3857{
3858 struct net_device *dev = dev_instance;
3859 struct bnx2x *bp = netdev_priv(dev);
3860
3861 /* Return here if interrupt is disabled */
3862 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3863 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3864 return IRQ_HANDLED;
3865 }
3866
523224a3
DK		 3867 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3868 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 3869
3870#ifdef BNX2X_STOP_ON_ERROR
3871 if (unlikely(bp->panic))
3872 return IRQ_HANDLED;
3873#endif
3874
993ac7b5
MC		 3875#ifdef BCM_CNIC
3876 {
3877 struct cnic_ops *c_ops;
3878
3879 rcu_read_lock();
3880 c_ops = rcu_dereference(bp->cnic_ops);
3881 if (c_ops)
3882 c_ops->cnic_handler(bp->cnic_data, NULL);
3883 rcu_read_unlock();
3884 }
3885#endif
1cf167f2 3886 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 3887
3888 return IRQ_HANDLED;
3889}
3890
3891/* end of slow path */
3892
a2fbb9ea
ET		 3893static void bnx2x_timer(unsigned long data)
3894{
3895 struct bnx2x *bp = (struct bnx2x *) data;
3896
3897 if (!netif_running(bp->dev))
3898 return;
3899
3900 if (atomic_read(&bp->intr_sem) != 0)
f1410647 3901 goto timer_restart;
a2fbb9ea
ET		 3902
3903 if (poll) {
3904 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 3905
7961f791 3906 bnx2x_tx_int(fp);
b8ee8328 3907 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 3908 }
3909
34f80b04 3910 if (!BP_NOMCP(bp)) {
f2e0899f 3911 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 3912 u32 drv_pulse;
3913 u32 mcp_pulse;
3914
3915 ++bp->fw_drv_pulse_wr_seq;
3916 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3917 /* TBD - add SYSTEM_TIME */
3918 drv_pulse = bp->fw_drv_pulse_wr_seq;
f2e0899f 3919 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
a2fbb9ea 3920
f2e0899f 3921 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 3922 MCP_PULSE_SEQ_MASK);
3923 /* The delta between driver pulse and mcp response
3924 * should be 1 (before mcp response) or 0 (after mcp response)
3925 */
3926 if ((drv_pulse != mcp_pulse) &&
3927 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3928 /* someone lost a heartbeat... */
3929 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3930 drv_pulse, mcp_pulse);
3931 }
3932 }
3933
f34d28ea 3934 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 3935 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 3936
f1410647 3937timer_restart:
a2fbb9ea
ET		 3938 mod_timer(&bp->timer, jiffies + bp->current_interval);
3939}
3940
3941/* end of Statistics */
3942
3943/* nic init */
3944
3945/*
3946 * nic init service functions
3947 */
3948
523224a3 3949static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 3950{
523224a3
DK		 3951 u32 i;
3952 if (!(len%4) && !(addr%4))
3953 for (i = 0; i < len; i += 4)
3954 REG_WR(bp, addr + i, fill);
3955 else
3956 for (i = 0; i < len; i++)
3957 REG_WR8(bp, addr + i, fill);
34f80b04 3958
34f80b04
EG		 3959}
3960
523224a3
DK		 3961/* helper: writes FP SP data to FW - data_size in dwords */
3962static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3963 int fw_sb_id,
3964 u32 *sb_data_p,
3965 u32 data_size)
34f80b04 3966{
a2fbb9ea 3967 int index;
523224a3
DK		 3968 for (index = 0; index < data_size; index++)
3969 REG_WR(bp, BAR_CSTRORM_INTMEM +
3970 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3971 sizeof(u32)*index,
3972 *(sb_data_p + index));
3973}
a2fbb9ea 3974
523224a3
DK		 3975static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3976{
3977 u32 *sb_data_p;
3978 u32 data_size = 0;
f2e0899f 3979 struct hc_status_block_data_e2 sb_data_e2;
523224a3 3980 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 3981
523224a3 3982 /* disable the function first */
f2e0899f
DK		 3983 if (CHIP_IS_E2(bp)) {
3984 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3985 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3986 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3987 sb_data_e2.common.p_func.vf_valid = false;
3988 sb_data_p = (u32 *)&sb_data_e2;
3989 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3990 } else {
3991 memset(&sb_data_e1x, 0,
3992 sizeof(struct hc_status_block_data_e1x));
3993 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3994 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3995 sb_data_e1x.common.p_func.vf_valid = false;
3996 sb_data_p = (u32 *)&sb_data_e1x;
3997 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3998 }
523224a3 3999 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4000
523224a3
DK		 4001 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4002 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4003 CSTORM_STATUS_BLOCK_SIZE);
4004 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4005 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4006 CSTORM_SYNC_BLOCK_SIZE);
4007}
34f80b04 4008
523224a3
DK		 4009/* helper: writes SP SB data to FW */
4010static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4011 struct hc_sp_status_block_data *sp_sb_data)
4012{
4013 int func = BP_FUNC(bp);
4014 int i;
4015 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4016 REG_WR(bp, BAR_CSTRORM_INTMEM +
4017 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4018 i*sizeof(u32),
4019 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4020}
4021
523224a3 4022static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4023{
4024 int func = BP_FUNC(bp);
523224a3
DK		 4025 struct hc_sp_status_block_data sp_sb_data;
4026 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4027
523224a3
DK		 4028 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4029 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4030 sp_sb_data.p_func.vf_valid = false;
4031
4032 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4033
4034 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4035 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4036 CSTORM_SP_STATUS_BLOCK_SIZE);
4037 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4038 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4039 CSTORM_SP_SYNC_BLOCK_SIZE);
4040
4041}
4042
4043
4044static inline
4045void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4046 int igu_sb_id, int igu_seg_id)
4047{
4048 hc_sm->igu_sb_id = igu_sb_id;
4049 hc_sm->igu_seg_id = igu_seg_id;
4050 hc_sm->timer_value = 0xFF;
4051 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4052}
4053
8d96286a 4054static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4055 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4056{
523224a3
DK		 4057 int igu_seg_id;
4058
f2e0899f 4059 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4060 struct hc_status_block_data_e1x sb_data_e1x;
4061 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4062 int data_size;
4063 u32 *sb_data_p;
4064
f2e0899f
DK		 4065 if (CHIP_INT_MODE_IS_BC(bp))
4066 igu_seg_id = HC_SEG_ACCESS_NORM;
4067 else
4068 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4069
4070 bnx2x_zero_fp_sb(bp, fw_sb_id);
4071
f2e0899f
DK		 4072 if (CHIP_IS_E2(bp)) {
4073 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4074 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4075 sb_data_e2.common.p_func.vf_id = vfid;
4076 sb_data_e2.common.p_func.vf_valid = vf_valid;
4077 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4078 sb_data_e2.common.same_igu_sb_1b = true;
4079 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4080 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4081 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4082 sb_data_p = (u32 *)&sb_data_e2;
4083 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4084 } else {
4085 memset(&sb_data_e1x, 0,
4086 sizeof(struct hc_status_block_data_e1x));
4087 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4088 sb_data_e1x.common.p_func.vf_id = 0xff;
4089 sb_data_e1x.common.p_func.vf_valid = false;
4090 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4091 sb_data_e1x.common.same_igu_sb_1b = true;
4092 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4093 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4094 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4095 sb_data_p = (u32 *)&sb_data_e1x;
4096 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4097 }
523224a3
DK		 4098
4099 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4100 igu_sb_id, igu_seg_id);
4101 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4102 igu_sb_id, igu_seg_id);
4103
4104 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4105
4106 /* write indecies to HW */
4107 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4108}
4109
4110static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4111 u8 sb_index, u8 disable, u16 usec)
4112{
4113 int port = BP_PORT(bp);
4114 u8 ticks = usec / BNX2X_BTR;
4115
4116 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4117
4118 disable = disable ? 1 : (usec ? 0 : 1);
4119 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4120}
4121
4122static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4123 u16 tx_usec, u16 rx_usec)
4124{
4125 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4126 false, rx_usec);
4127 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4128 false, tx_usec);
4129}
f2e0899f 4130
523224a3
DK		 4131static void bnx2x_init_def_sb(struct bnx2x *bp)
4132{
4133 struct host_sp_status_block *def_sb = bp->def_status_blk;
4134 dma_addr_t mapping = bp->def_status_blk_mapping;
4135 int igu_sp_sb_index;
4136 int igu_seg_id;
34f80b04
EG		 4137 int port = BP_PORT(bp);
4138 int func = BP_FUNC(bp);
523224a3 4139 int reg_offset;
a2fbb9ea 4140 u64 section;
523224a3
DK		 4141 int index;
4142 struct hc_sp_status_block_data sp_sb_data;
4143 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4144
f2e0899f
DK		 4145 if (CHIP_INT_MODE_IS_BC(bp)) {
4146 igu_sp_sb_index = DEF_SB_IGU_ID;
4147 igu_seg_id = HC_SEG_ACCESS_DEF;
4148 } else {
4149 igu_sp_sb_index = bp->igu_dsb_id;
4150 igu_seg_id = IGU_SEG_ACCESS_DEF;
4151 }
a2fbb9ea
ET		 4152
4153 /* ATTN */
523224a3 4154 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4155 atten_status_block);
523224a3 4156 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4157
49d66772
ET		 4158 bp->attn_state = 0;
4159
a2fbb9ea
ET		 4160 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4161 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4162 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4163 int sindex;
4164 /* take care of sig[0]..sig[4] */
4165 for (sindex = 0; sindex < 4; sindex++)
4166 bp->attn_group[index].sig[sindex] =
4167 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f
DK		 4168
4169 if (CHIP_IS_E2(bp))
4170 /*
4171 * enable5 is separate from the rest of the registers,
4172 * and therefore the address skip is 4
4173 * and not 16 between the different groups
4174 */
4175 bp->attn_group[index].sig[4] = REG_RD(bp,
4176 reg_offset + 0x10 + 0x4*index);
4177 else
4178 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4179 }
4180
f2e0899f
DK		 4181 if (bp->common.int_block == INT_BLOCK_HC) {
4182 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4183 HC_REG_ATTN_MSG0_ADDR_L);
4184
4185 REG_WR(bp, reg_offset, U64_LO(section));
4186 REG_WR(bp, reg_offset + 4, U64_HI(section));
4187 } else if (CHIP_IS_E2(bp)) {
4188 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4189 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4190 }
a2fbb9ea 4191
523224a3
DK		 4192 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4193 sp_sb);
a2fbb9ea 4194
523224a3 4195 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4196
523224a3
DK		 4197 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4198 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4199 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4200 sp_sb_data.igu_seg_id = igu_seg_id;
4201 sp_sb_data.p_func.pf_id = func;
f2e0899f 4202 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4203 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4204
523224a3 4205 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4206
bb2a0f7a 4207 bp->stats_pending = 0;
66e855f3 4208 bp->set_mac_pending = 0;
bb2a0f7a 4209
523224a3 4210 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4211}
4212
9f6c9258 4213void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4214{
a2fbb9ea
ET		 4215 int i;
4216
ec6ba945 4217 for_each_eth_queue(bp, i)
523224a3 4218 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4219 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4220}
4221
a2fbb9ea
ET		 4222static void bnx2x_init_sp_ring(struct bnx2x *bp)
4223{
a2fbb9ea 4224 spin_lock_init(&bp->spq_lock);
6e30dd4e 4225 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4226
a2fbb9ea 4227 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4228 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4229 bp->spq_prod_bd = bp->spq;
4230 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4231}
4232
523224a3 4233static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4234{
4235 int i;
523224a3
DK		 4236 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4237 union event_ring_elem *elem =
4238 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4239
523224a3
DK		 4240 elem->next_page.addr.hi =
4241 cpu_to_le32(U64_HI(bp->eq_mapping +
4242 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4243 elem->next_page.addr.lo =
4244 cpu_to_le32(U64_LO(bp->eq_mapping +
4245 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4246 }
523224a3
DK		 4247 bp->eq_cons = 0;
4248 bp->eq_prod = NUM_EQ_DESC;
4249 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 4250 /* we want a warning message before it gets rought... */
4251 atomic_set(&bp->eq_spq_left,
4252 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 4253}
4254
ab532cf3 4255void bnx2x_push_indir_table(struct bnx2x *bp)
a2fbb9ea 4256{
26c8fa4d 4257 int func = BP_FUNC(bp);
a2fbb9ea
ET		 4258 int i;
4259
555f6c78 4260 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
a2fbb9ea
ET		 4261 return;
4262
4263 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
34f80b04 4264 REG_WR8(bp, BAR_TSTRORM_INTMEM +
26c8fa4d 4265 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
ab532cf3
TH		 4266 bp->fp->cl_id + bp->rx_indir_table[i]);
4267}
4268
4269static void bnx2x_init_ind_table(struct bnx2x *bp)
4270{
4271 int i;
4272
4273 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4274 bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);
4275
4276 bnx2x_push_indir_table(bp);
a2fbb9ea
ET		 4277}
4278
9f6c9258 4279void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
a2fbb9ea 4280{
34f80b04 4281 int mode = bp->rx_mode;
ec6ba945 4282 int port = BP_PORT(bp);
523224a3 4283 u16 cl_id;
ec6ba945 4284 u32 def_q_filters = 0;
523224a3 4285
581ce43d
EG		 4286 /* All but management unicast packets should pass to the host as well */
4287 u32 llh_mask =
4288 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4289 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4290 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4291 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
a2fbb9ea 4292
a2fbb9ea
ET		 4293 switch (mode) {
4294 case BNX2X_RX_MODE_NONE: /* no Rx */
ec6ba945
VZ		 4295 def_q_filters = BNX2X_ACCEPT_NONE;
4296#ifdef BCM_CNIC
4297 if (!NO_FCOE(bp)) {
4298 cl_id = bnx2x_fcoe(bp, cl_id);
4299 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4300 }
4301#endif
a2fbb9ea 4302 break;
356e2385 4303
a2fbb9ea 4304 case BNX2X_RX_MODE_NORMAL:
ec6ba945
VZ		 4305 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4306 BNX2X_ACCEPT_MULTICAST;
4307#ifdef BCM_CNIC
711c9146
VZ		 4308 if (!NO_FCOE(bp)) {
4309 cl_id = bnx2x_fcoe(bp, cl_id);
4310 bnx2x_rxq_set_mac_filters(bp, cl_id,
4311 BNX2X_ACCEPT_UNICAST |
4312 BNX2X_ACCEPT_MULTICAST);
4313 }
ec6ba945 4314#endif
a2fbb9ea 4315 break;
356e2385 4316
a2fbb9ea 4317 case BNX2X_RX_MODE_ALLMULTI:
ec6ba945
VZ		 4318 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4319 BNX2X_ACCEPT_ALL_MULTICAST;
4320#ifdef BCM_CNIC
711c9146
VZ		 4321 /*
4322 * Prevent duplication of multicast packets by configuring FCoE
4323 * L2 Client to receive only matched unicast frames.
4324 */
4325 if (!NO_FCOE(bp)) {
4326 cl_id = bnx2x_fcoe(bp, cl_id);
4327 bnx2x_rxq_set_mac_filters(bp, cl_id,
4328 BNX2X_ACCEPT_UNICAST);
4329 }
ec6ba945 4330#endif
a2fbb9ea 4331 break;
356e2385 4332
a2fbb9ea 4333 case BNX2X_RX_MODE_PROMISC:
ec6ba945
VZ		 4334 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4335#ifdef BCM_CNIC
711c9146
VZ		 4336 /*
4337 * Prevent packets duplication by configuring DROP_ALL for FCoE
4338 * L2 Client.
4339 */
4340 if (!NO_FCOE(bp)) {
4341 cl_id = bnx2x_fcoe(bp, cl_id);
4342 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4343 }
ec6ba945 4344#endif
581ce43d
EG		 4345 /* pass management unicast packets as well */
4346 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
a2fbb9ea 4347 break;
356e2385 4348
a2fbb9ea 4349 default:
34f80b04
EG		 4350 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4351 break;
a2fbb9ea
ET		 4352 }
4353
ec6ba945
VZ		 4354 cl_id = BP_L_ID(bp);
4355 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4356
581ce43d 4357 REG_WR(bp,
ec6ba945
VZ		 4358 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4359 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
581ce43d 4360
523224a3
DK		 4361 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4362 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
ec6ba945
VZ		 4363 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4364 "unmatched_ucast 0x%x\n", mode,
523224a3
DK		 4365 bp->mac_filters.ucast_drop_all,
4366 bp->mac_filters.mcast_drop_all,
4367 bp->mac_filters.bcast_drop_all,
4368 bp->mac_filters.ucast_accept_all,
4369 bp->mac_filters.mcast_accept_all,
ec6ba945
VZ		 4370 bp->mac_filters.bcast_accept_all,
4371 bp->mac_filters.unmatched_unicast
523224a3 4372 );
a2fbb9ea 4373
523224a3 4374 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
a2fbb9ea
ET		 4375}
4376
471de716
EG		 4377static void bnx2x_init_internal_common(struct bnx2x *bp)
4378{
4379 int i;
4380
523224a3 4381 if (!CHIP_IS_E1(bp)) {
de832a55 4382
523224a3
DK		 4383 /* xstorm needs to know whether to add ovlan to packets or not,
4384 * in switch-independent we'll write 0 to here... */
34f80b04 4385 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4386 bp->mf_mode);
34f80b04 4387 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4388 bp->mf_mode);
34f80b04 4389 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4390 bp->mf_mode);
34f80b04 4391 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4392 bp->mf_mode);
34f80b04
EG		 4393 }
4394
0793f83f
DK		 4395 if (IS_MF_SI(bp))
4396 /*
4397 * In switch independent mode, the TSTORM needs to accept
4398 * packets that failed classification, since approximate match
4399 * mac addresses aren't written to NIG LLH
4400 */
4401 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4402 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4403
523224a3
DK		 4404 /* Zero this manually as its initialization is
4405 currently missing in the initTool */
4406 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 4407 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 4408 USTORM_AGG_DATA_OFFSET + i * 4, 0);
f2e0899f
DK		 4409 if (CHIP_IS_E2(bp)) {
4410 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4411 CHIP_INT_MODE_IS_BC(bp) ?
4412 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4413 }
523224a3 4414}
8a1c38d1 4415
523224a3
DK		 4416static void bnx2x_init_internal_port(struct bnx2x *bp)
4417{
4418 /* port */
e4901dde 4419 bnx2x_dcb_init_intmem_pfc(bp);
a2fbb9ea
ET		 4420}
4421
471de716
EG		 4422static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4423{
4424 switch (load_code) {
4425 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 4426 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 4427 bnx2x_init_internal_common(bp);
4428 /* no break */
4429
4430 case FW_MSG_CODE_DRV_LOAD_PORT:
4431 bnx2x_init_internal_port(bp);
4432 /* no break */
4433
4434 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 4435 /* internal memory per function is
4436 initialized inside bnx2x_pf_init */
471de716
EG		 4437 break;
4438
4439 default:
4440 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4441 break;
4442 }
4443}
4444
523224a3
DK		 4445static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4446{
4447 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4448
4449 fp->state = BNX2X_FP_STATE_CLOSED;
4450
b3b83c3f 4451 fp->cid = fp_idx;
523224a3
DK		 4452 fp->cl_id = BP_L_ID(bp) + fp_idx;
4453 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4454 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4455 /* qZone id equals to FW (per path) client id */
4456 fp->cl_qzone_id = fp->cl_id +
f2e0899f
DK		 4457 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4458 ETH_MAX_RX_CLIENTS_E1H);
523224a3 4459 /* init shortcut */
f2e0899f
DK		 4460 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4461 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
523224a3
DK		 4462 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4463 /* Setup SB indicies */
4464 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4465 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4466
4467 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4468 "cl_id %d fw_sb %d igu_sb %d\n",
4469 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4470 fp->igu_sb_id);
4471 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4472 fp->fw_sb_id, fp->igu_sb_id);
4473
4474 bnx2x_update_fpsb_idx(fp);
4475}
4476
9f6c9258 4477void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 4478{
4479 int i;
4480
ec6ba945 4481 for_each_eth_queue(bp, i)
523224a3 4482 bnx2x_init_fp_sb(bp, i);
37b091ba 4483#ifdef BCM_CNIC
ec6ba945
VZ		 4484 if (!NO_FCOE(bp))
4485 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 4486
4487 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4488 BNX2X_VF_ID_INVALID, false,
4489 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4490
37b091ba 4491#endif
a2fbb9ea 4492
16119785
EG		 4493 /* ensure status block indices were read */
4494 rmb();
4495
523224a3 4496 bnx2x_init_def_sb(bp);
5c862848 4497 bnx2x_update_dsb_idx(bp);
a2fbb9ea 4498 bnx2x_init_rx_rings(bp);
523224a3 4499 bnx2x_init_tx_rings(bp);
a2fbb9ea 4500 bnx2x_init_sp_ring(bp);
523224a3 4501 bnx2x_init_eq_ring(bp);
471de716 4502 bnx2x_init_internal(bp, load_code);
523224a3 4503 bnx2x_pf_init(bp);
a2fbb9ea 4504 bnx2x_init_ind_table(bp);
0ef00459
EG		 4505 bnx2x_stats_init(bp);
4506
4507 /* At this point, we are ready for interrupts */
4508 atomic_set(&bp->intr_sem, 0);
4509
4510 /* flush all before enabling interrupts */
4511 mb();
4512 mmiowb();
4513
615f8fd9 4514 bnx2x_int_enable(bp);
eb8da205
EG		 4515
4516 /* Check for SPIO5 */
4517 bnx2x_attn_int_deasserted0(bp,
4518 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4519 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 4520}
4521
4522/* end of nic init */
4523
4524/*
4525 * gzip service functions
4526 */
4527
4528static int bnx2x_gunzip_init(struct bnx2x *bp)
4529{
1a983142
FT		 4530 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4531 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 4532 if (bp->gunzip_buf == NULL)
4533 goto gunzip_nomem1;
4534
4535 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4536 if (bp->strm == NULL)
4537 goto gunzip_nomem2;
4538
4539 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4540 GFP_KERNEL);
4541 if (bp->strm->workspace == NULL)
4542 goto gunzip_nomem3;
4543
4544 return 0;
4545
4546gunzip_nomem3:
4547 kfree(bp->strm);
4548 bp->strm = NULL;
4549
4550gunzip_nomem2:
1a983142
FT		 4551 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4552 bp->gunzip_mapping);
a2fbb9ea
ET		 4553 bp->gunzip_buf = NULL;
4554
4555gunzip_nomem1:
cdaa7cb8
VZ		 4556 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4557 " un-compression\n");
a2fbb9ea
ET		 4558 return -ENOMEM;
4559}
4560
4561static void bnx2x_gunzip_end(struct bnx2x *bp)
4562{
b3b83c3f
DK		 4563 if (bp->strm) {
4564 kfree(bp->strm->workspace);
4565 kfree(bp->strm);
4566 bp->strm = NULL;
4567 }
a2fbb9ea
ET		 4568
4569 if (bp->gunzip_buf) {
1a983142
FT		 4570 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4571 bp->gunzip_mapping);
a2fbb9ea
ET		 4572 bp->gunzip_buf = NULL;
4573 }
4574}
4575
94a78b79 4576static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 4577{
4578 int n, rc;
4579
4580 /* check gzip header */
94a78b79
VZ		 4581 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4582 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 4583 return -EINVAL;
94a78b79 4584 }
a2fbb9ea
ET		 4585
4586 n = 10;
4587
34f80b04 4588#define FNAME 0x8
a2fbb9ea
ET		 4589
4590 if (zbuf[3] & FNAME)
4591 while ((zbuf[n++] != 0) && (n < len));
4592
94a78b79 4593 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 4594 bp->strm->avail_in = len - n;
4595 bp->strm->next_out = bp->gunzip_buf;
4596 bp->strm->avail_out = FW_BUF_SIZE;
4597
4598 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4599 if (rc != Z_OK)
4600 return rc;
4601
4602 rc = zlib_inflate(bp->strm, Z_FINISH);
4603 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 4604 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4605 bp->strm->msg);
a2fbb9ea
ET		 4606
4607 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4608 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 4609 netdev_err(bp->dev, "Firmware decompression error:"
4610 " gunzip_outlen (%d) not aligned\n",
4611 bp->gunzip_outlen);
a2fbb9ea
ET		 4612 bp->gunzip_outlen >>= 2;
4613
4614 zlib_inflateEnd(bp->strm);
4615
4616 if (rc == Z_STREAM_END)
4617 return 0;
4618
4619 return rc;
4620}
4621
4622/* nic load/unload */
4623
4624/*
34f80b04 4625 * General service functions
a2fbb9ea
ET		 4626 */
4627
4628/* send a NIG loopback debug packet */
4629static void bnx2x_lb_pckt(struct bnx2x *bp)
4630{
a2fbb9ea 4631 u32 wb_write[3];
a2fbb9ea
ET		 4632
4633 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 4634 wb_write[0] = 0x55555555;
4635 wb_write[1] = 0x55555555;
34f80b04 4636 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 4637 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4638
4639 /* NON-IP protocol */
a2fbb9ea
ET		 4640 wb_write[0] = 0x09000000;
4641 wb_write[1] = 0x55555555;
34f80b04 4642 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 4643 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4644}
4645
4646/* some of the internal memories
4647 * are not directly readable from the driver
4648 * to test them we send debug packets
4649 */
4650static int bnx2x_int_mem_test(struct bnx2x *bp)
4651{
4652 int factor;
4653 int count, i;
4654 u32 val = 0;
4655
ad8d3948 4656 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 4657 factor = 120;
ad8d3948
EG		 4658 else if (CHIP_REV_IS_EMUL(bp))
4659 factor = 200;
4660 else
a2fbb9ea 4661 factor = 1;
a2fbb9ea 4662
a2fbb9ea
ET		 4663 /* Disable inputs of parser neighbor blocks */
4664 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4665 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4666 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4667 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4668
4669 /* Write 0 to parser credits for CFC search request */
4670 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4671
4672 /* send Ethernet packet */
4673 bnx2x_lb_pckt(bp);
4674
4675 /* TODO do i reset NIG statistic? */
4676 /* Wait until NIG register shows 1 packet of size 0x10 */
4677 count = 1000 * factor;
4678 while (count) {
34f80b04 4679
a2fbb9ea
ET		 4680 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4681 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4682 if (val == 0x10)
4683 break;
4684
4685 msleep(10);
4686 count--;
4687 }
4688 if (val != 0x10) {
4689 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4690 return -1;
4691 }
4692
4693 /* Wait until PRS register shows 1 packet */
4694 count = 1000 * factor;
4695 while (count) {
4696 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 4697 if (val == 1)
4698 break;
4699
4700 msleep(10);
4701 count--;
4702 }
4703 if (val != 0x1) {
4704 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4705 return -2;
4706 }
4707
4708 /* Reset and init BRB, PRS */
34f80b04 4709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 4710 msleep(50);
34f80b04 4711 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 4712 msleep(50);
94a78b79
VZ		 4713 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4714 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
a2fbb9ea
ET		 4715
4716 DP(NETIF_MSG_HW, "part2\n");
4717
4718 /* Disable inputs of parser neighbor blocks */
4719 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4720 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4721 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4722 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4723
4724 /* Write 0 to parser credits for CFC search request */
4725 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4726
4727 /* send 10 Ethernet packets */
4728 for (i = 0; i < 10; i++)
4729 bnx2x_lb_pckt(bp);
4730
4731 /* Wait until NIG register shows 10 + 1
4732 packets of size 11*0x10 = 0xb0 */
4733 count = 1000 * factor;
4734 while (count) {
34f80b04 4735
a2fbb9ea
ET		 4736 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4737 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4738 if (val == 0xb0)
4739 break;
4740
4741 msleep(10);
4742 count--;
4743 }
4744 if (val != 0xb0) {
4745 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4746 return -3;
4747 }
4748
4749 /* Wait until PRS register shows 2 packets */
4750 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4751 if (val != 2)
4752 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4753
4754 /* Write 1 to parser credits for CFC search request */
4755 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4756
4757 /* Wait until PRS register shows 3 packets */
4758 msleep(10 * factor);
4759 /* Wait until NIG register shows 1 packet of size 0x10 */
4760 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4761 if (val != 3)
4762 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4763
4764 /* clear NIG EOP FIFO */
4765 for (i = 0; i < 11; i++)
4766 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4767 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4768 if (val != 1) {
4769 BNX2X_ERR("clear of NIG failed\n");
4770 return -4;
4771 }
4772
4773 /* Reset and init BRB, PRS, NIG */
4774 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4775 msleep(50);
4776 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4777 msleep(50);
94a78b79
VZ		 4778 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4779 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
37b091ba 4780#ifndef BCM_CNIC
a2fbb9ea
ET		 4781 /* set NIC mode */
4782 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4783#endif
4784
4785 /* Enable inputs of parser neighbor blocks */
4786 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4787 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4788 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 4789 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 4790
4791 DP(NETIF_MSG_HW, "done\n");
4792
4793 return 0; /* OK */
4794}
4795
4a33bc03 4796static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 4797{
4798 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
f2e0899f
DK		 4799 if (CHIP_IS_E2(bp))
4800 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4801 else
4802 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 4803 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4804 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 4805 /*
4806 * mask read length error interrupts in brb for parser
4807 * (parsing unit and 'checksum and crc' unit)
4808 * these errors are legal (PU reads fixed length and CAC can cause
4809 * read length error on truncated packets)
4810 */
4811 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 4812 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4813 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4814 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4815 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4816 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 4817/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4818/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4819 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4820 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4821 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 4822/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4823/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4824 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4825 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4826 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4827 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 4828/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4829/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 4830
34f80b04
EG		 4831 if (CHIP_REV_IS_FPGA(bp))
4832 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
f2e0899f
DK		 4833 else if (CHIP_IS_E2(bp))
4834 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4835 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4836 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4837 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4838 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4839 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 4840 else
4841 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 4842 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4843 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4844 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04
EG		 4845/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4846/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4847 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4848 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 4849/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 4850 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 4851}
4852
81f75bbf
EG		 4853static void bnx2x_reset_common(struct bnx2x *bp)
4854{
4855 /* reset_common */
4856 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4857 0xd3ffff7f);
4858 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4859}
4860
573f2035
EG		 4861static void bnx2x_init_pxp(struct bnx2x *bp)
4862{
4863 u16 devctl;
4864 int r_order, w_order;
4865
4866 pci_read_config_word(bp->pdev,
4867 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4868 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4869 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4870 if (bp->mrrs == -1)
4871 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4872 else {
4873 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4874 r_order = bp->mrrs;
4875 }
4876
4877 bnx2x_init_pxp_arb(bp, r_order, w_order);
4878}
fd4ef40d
EG		 4879
4880static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4881{
2145a920 4882 int is_required;
fd4ef40d 4883 u32 val;
2145a920 4884 int port;
fd4ef40d 4885
2145a920
VZ		 4886 if (BP_NOMCP(bp))
4887 return;
4888
4889 is_required = 0;
fd4ef40d
EG		 4890 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4891 SHARED_HW_CFG_FAN_FAILURE_MASK;
4892
4893 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4894 is_required = 1;
4895
4896 /*
4897 * The fan failure mechanism is usually related to the PHY type since
4898 * the power consumption of the board is affected by the PHY. Currently,
4899 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4900 */
4901 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4902 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 4903 is_required |=
d90d96ba
YR		 4904 bnx2x_fan_failure_det_req(
4905 bp,
4906 bp->common.shmem_base,
a22f0788 4907 bp->common.shmem2_base,
d90d96ba 4908 port);
fd4ef40d
EG		 4909 }
4910
4911 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4912
4913 if (is_required == 0)
4914 return;
4915
4916 /* Fan failure is indicated by SPIO 5 */
4917 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4918 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4919
4920 /* set to active low mode */
4921 val = REG_RD(bp, MISC_REG_SPIO_INT);
4922 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 4923 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 4924 REG_WR(bp, MISC_REG_SPIO_INT, val);
4925
4926 /* enable interrupt to signal the IGU */
4927 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4928 val |= (1 << MISC_REGISTERS_SPIO_5);
4929 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4930}
4931
f2e0899f
DK		 4932static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4933{
4934 u32 offset = 0;
4935
4936 if (CHIP_IS_E1(bp))
4937 return;
4938 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4939 return;
4940
4941 switch (BP_ABS_FUNC(bp)) {
4942 case 0:
4943 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4944 break;
4945 case 1:
4946 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4947 break;
4948 case 2:
4949 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4950 break;
4951 case 3:
4952 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4953 break;
4954 case 4:
4955 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4956 break;
4957 case 5:
4958 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4959 break;
4960 case 6:
4961 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4962 break;
4963 case 7:
4964 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4965 break;
4966 default:
4967 return;
4968 }
4969
4970 REG_WR(bp, offset, pretend_func_num);
4971 REG_RD(bp, offset);
4972 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4973}
4974
4975static void bnx2x_pf_disable(struct bnx2x *bp)
4976{
4977 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4978 val &= ~IGU_PF_CONF_FUNC_EN;
4979
4980 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4981 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4982 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4983}
4984
523224a3 4985static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
a2fbb9ea 4986{
a2fbb9ea 4987 u32 val, i;
a2fbb9ea 4988
f2e0899f 4989 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 4990
81f75bbf 4991 bnx2x_reset_common(bp);
34f80b04
EG		 4992 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4993 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
a2fbb9ea 4994
94a78b79 4995 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
f2e0899f 4996 if (!CHIP_IS_E1(bp))
fb3bff17 4997 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
a2fbb9ea 4998
f2e0899f
DK		 4999 if (CHIP_IS_E2(bp)) {
5000 u8 fid;
5001
5002 /**
5003 * 4-port mode or 2-port mode we need to turn of master-enable
5004 * for everyone, after that, turn it back on for self.
5005 * so, we disregard multi-function or not, and always disable
5006 * for all functions on the given path, this means 0,2,4,6 for
5007 * path 0 and 1,3,5,7 for path 1
5008 */
5009 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5010 if (fid == BP_ABS_FUNC(bp)) {
5011 REG_WR(bp,
5012 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5013 1);
5014 continue;
5015 }
5016
5017 bnx2x_pretend_func(bp, fid);
5018 /* clear pf enable */
5019 bnx2x_pf_disable(bp);
5020 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5021 }
5022 }
a2fbb9ea 5023
94a78b79 5024 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
34f80b04
EG		 5025 if (CHIP_IS_E1(bp)) {
5026 /* enable HW interrupt from PXP on USDM overflow
5027 bit 16 on INT_MASK_0 */
5028 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5029 }
a2fbb9ea 5030
94a78b79 5031 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
34f80b04 5032 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5033
5034#ifdef __BIG_ENDIAN
34f80b04
EG		 5035 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5036 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5037 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5038 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5039 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5040 /* make sure this value is 0 */
5041 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5042
5043/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5044 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5045 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5046 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5047 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5048#endif
5049
523224a3
DK		 5050 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5051
34f80b04
EG		 5052 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5053 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5054
34f80b04
EG		 5055 /* let the HW do it's magic ... */
5056 msleep(100);
5057 /* finish PXP init */
5058 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5059 if (val != 1) {
5060 BNX2X_ERR("PXP2 CFG failed\n");
5061 return -EBUSY;
5062 }
5063 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5064 if (val != 1) {
5065 BNX2X_ERR("PXP2 RD_INIT failed\n");
5066 return -EBUSY;
5067 }
a2fbb9ea 5068
f2e0899f
DK		 5069 /* Timers bug workaround E2 only. We need to set the entire ILT to
5070 * have entries with value "0" and valid bit on.
5071 * This needs to be done by the first PF that is loaded in a path
5072 * (i.e. common phase)
5073 */
5074 if (CHIP_IS_E2(bp)) {
5075 struct ilt_client_info ilt_cli;
5076 struct bnx2x_ilt ilt;
5077 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5078 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5079
b595076a 5080 /* initialize dummy TM client */
f2e0899f
DK		 5081 ilt_cli.start = 0;
5082 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5083 ilt_cli.client_num = ILT_CLIENT_TM;
5084
5085 /* Step 1: set zeroes to all ilt page entries with valid bit on
5086 * Step 2: set the timers first/last ilt entry to point
5087 * to the entire range to prevent ILT range error for 3rd/4th
25985edc 5088 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 5089 *
5090 * both steps performed by call to bnx2x_ilt_client_init_op()
5091 * with dummy TM client
5092 *
5093 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5094 * and his brother are split registers
5095 */
5096 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5097 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5098 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5099
5100 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5101 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5102 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5103 }
5104
5105
34f80b04
EG		 5106 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5107 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5108
f2e0899f
DK		 5109 if (CHIP_IS_E2(bp)) {
5110 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5111 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5112 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5113
5114 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5115
5116 /* let the HW do it's magic ... */
5117 do {
5118 msleep(200);
5119 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5120 } while (factor-- && (val != 1));
5121
5122 if (val != 1) {
5123 BNX2X_ERR("ATC_INIT failed\n");
5124 return -EBUSY;
5125 }
5126 }
5127
94a78b79 5128 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
a2fbb9ea 5129
34f80b04
EG		 5130 /* clean the DMAE memory */
5131 bp->dmae_ready = 1;
5132 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
a2fbb9ea 5133
94a78b79
VZ		 5134 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5135 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5136 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5137 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
a2fbb9ea 5138
34f80b04
EG		 5139 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5140 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5141 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5142 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5143
94a78b79 5144 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
37b091ba 5145
f2e0899f
DK		 5146 if (CHIP_MODE_IS_4_PORT(bp))
5147 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
f85582f8 5148
523224a3
DK		 5149 /* QM queues pointers table */
5150 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5151
34f80b04
EG		 5152 /* soft reset pulse */
5153 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5154 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 5155
37b091ba 5156#ifdef BCM_CNIC
94a78b79 5157 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
a2fbb9ea 5158#endif
a2fbb9ea 5159
94a78b79 5160 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
523224a3
DK		 5161 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5162
34f80b04
EG		 5163 if (!CHIP_REV_IS_SLOW(bp)) {
5164 /* enable hw interrupt from doorbell Q */
5165 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5166 }
a2fbb9ea 5167
94a78b79 5168 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5169 if (CHIP_MODE_IS_4_PORT(bp)) {
5170 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5171 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5172 }
5173
94a78b79 5174 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
26c8fa4d 5175 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
37b091ba 5176#ifndef BCM_CNIC
3196a88a
EG		 5177 /* set NIC mode */
5178 REG_WR(bp, PRS_REG_NIC_MODE, 1);
37b091ba 5179#endif
f2e0899f 5180 if (!CHIP_IS_E1(bp))
0793f83f 5181 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
f85582f8 5182
f2e0899f
DK		 5183 if (CHIP_IS_E2(bp)) {
5184 /* Bit-map indicating which L2 hdrs may appear after the
5185 basic Ethernet header */
0793f83f 5186 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5187 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5188 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5189 }
a2fbb9ea 5190
94a78b79
VZ		 5191 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5192 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5193 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5194 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
a2fbb9ea 5195
ca00392c
EG		 5196 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5197 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5198 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5199 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
a2fbb9ea 5200
94a78b79
VZ		 5201 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5202 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5203 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5204 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
a2fbb9ea 5205
f2e0899f
DK		 5206 if (CHIP_MODE_IS_4_PORT(bp))
5207 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5208
34f80b04
EG		 5209 /* sync semi rtc */
5210 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5211 0x80000000);
5212 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5213 0x80000000);
a2fbb9ea 5214
94a78b79
VZ		 5215 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5216 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5217 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
a2fbb9ea 5218
f2e0899f 5219 if (CHIP_IS_E2(bp)) {
0793f83f 5220 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5221 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5222 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5223 }
5224
34f80b04 5225 REG_WR(bp, SRC_REG_SOFT_RST, 1);
c68ed255
TH		 5226 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5227 REG_WR(bp, i, random32());
f85582f8 5228
94a78b79 5229 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
37b091ba
MC		 5230#ifdef BCM_CNIC
5231 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5232 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5233 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5234 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5235 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5236 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5237 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5238 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5239 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5240 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5241#endif
34f80b04 5242 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 5243
34f80b04
EG		 5244 if (sizeof(union cdu_context) != 1024)
5245 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 5246 dev_alert(&bp->pdev->dev, "please adjust the size "
5247 "of cdu_context(%ld)\n",
7995c64e 5248 (long)sizeof(union cdu_context));
a2fbb9ea 5249
94a78b79 5250 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
34f80b04
EG		 5251 val = (4 << 24) + (0 << 12) + 1024;
5252 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 5253
94a78b79 5254 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
34f80b04 5255 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 5256 /* enable context validation interrupt from CFC */
5257 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5258
5259 /* set the thresholds to prevent CFC/CDU race */
5260 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 5261
94a78b79 5262 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5263
5264 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5265 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5266
5267 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
94a78b79 5268 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
a2fbb9ea 5269
94a78b79 5270 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
34f80b04
EG		 5271 /* Reset PCIE errors for debug */
5272 REG_WR(bp, 0x2814, 0xffffffff);
5273 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 5274
f2e0899f
DK		 5275 if (CHIP_IS_E2(bp)) {
5276 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5277 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5278 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5279 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5280 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5281 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5282 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5283 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5284 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5285 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5286 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5287 }
5288
94a78b79 5289 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
94a78b79 5290 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
94a78b79 5291 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
94a78b79 5292 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
34f80b04 5293
94a78b79 5294 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
f2e0899f 5295 if (!CHIP_IS_E1(bp)) {
fb3bff17 5296 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
0793f83f 5297 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04 5298 }
f2e0899f
DK		 5299 if (CHIP_IS_E2(bp)) {
5300 /* Bit-map indicating which L2 hdrs may appear after the
5301 basic Ethernet header */
0793f83f 5302 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
f2e0899f 5303 }
34f80b04
EG		 5304
5305 if (CHIP_REV_IS_SLOW(bp))
5306 msleep(200);
5307
5308 /* finish CFC init */
5309 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5310 if (val != 1) {
5311 BNX2X_ERR("CFC LL_INIT failed\n");
5312 return -EBUSY;
5313 }
5314 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5315 if (val != 1) {
5316 BNX2X_ERR("CFC AC_INIT failed\n");
5317 return -EBUSY;
5318 }
5319 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5320 if (val != 1) {
5321 BNX2X_ERR("CFC CAM_INIT failed\n");
5322 return -EBUSY;
5323 }
5324 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 5325
f2e0899f
DK		 5326 if (CHIP_IS_E1(bp)) {
5327 /* read NIG statistic
5328 to see if this is our first up since powerup */
5329 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5330 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 5331
f2e0899f
DK		 5332 /* do internal memory self test */
5333 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5334 BNX2X_ERR("internal mem self test failed\n");
5335 return -EBUSY;
5336 }
34f80b04
EG		 5337 }
5338
fd4ef40d
EG		 5339 bnx2x_setup_fan_failure_detection(bp);
5340
34f80b04
EG		 5341 /* clear PXP2 attentions */
5342 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 5343
4a33bc03
VZ		 5344 bnx2x_enable_blocks_attention(bp);
5345 if (CHIP_PARITY_ENABLED(bp))
5346 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 5347
6bbca910 5348 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 5349 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5350 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5351 CHIP_IS_E1x(bp)) {
5352 u32 shmem_base[2], shmem2_base[2];
5353 shmem_base[0] = bp->common.shmem_base;
5354 shmem2_base[0] = bp->common.shmem2_base;
5355 if (CHIP_IS_E2(bp)) {
5356 shmem_base[1] =
5357 SHMEM2_RD(bp, other_shmem_base_addr);
5358 shmem2_base[1] =
5359 SHMEM2_RD(bp, other_shmem2_base_addr);
5360 }
5361 bnx2x_acquire_phy_lock(bp);
5362 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5363 bp->common.chip_id);
5364 bnx2x_release_phy_lock(bp);
5365 }
6bbca910
YR		 5366 } else
5367 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5368
34f80b04
EG		 5369 return 0;
5370}
a2fbb9ea 5371
523224a3 5372static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 5373{
5374 int port = BP_PORT(bp);
94a78b79 5375 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
1c06328c 5376 u32 low, high;
34f80b04 5377 u32 val;
a2fbb9ea 5378
cdaa7cb8 5379 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 5380
5381 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 5382
94a78b79 5383 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
94a78b79 5384 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
ca00392c 5385
f2e0899f
DK		 5386 /* Timers bug workaround: disables the pf_master bit in pglue at
5387 * common phase, we need to enable it here before any dmae access are
5388 * attempted. Therefore we manually added the enable-master to the
5389 * port phase (it also happens in the function phase)
5390 */
5391 if (CHIP_IS_E2(bp))
5392 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5393
ca00392c
EG		 5394 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5395 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5396 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
94a78b79 5397 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
a2fbb9ea 5398
523224a3
DK		 5399 /* QM cid (connection) count */
5400 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 5401
523224a3 5402#ifdef BCM_CNIC
94a78b79 5403 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
37b091ba
MC		 5404 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5405 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 5406#endif
cdaa7cb8 5407
94a78b79 5408 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
1c06328c 5409
f2e0899f
DK		 5410 if (CHIP_MODE_IS_4_PORT(bp))
5411 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5412
5413 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5414 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5415 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5416 /* no pause for emulation and FPGA */
5417 low = 0;
5418 high = 513;
5419 } else {
5420 if (IS_MF(bp))
5421 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5422 else if (bp->dev->mtu > 4096) {
5423 if (bp->flags & ONE_PORT_FLAG)
5424 low = 160;
5425 else {
5426 val = bp->dev->mtu;
5427 /* (24*1024 + val*4)/256 */
5428 low = 96 + (val/64) +
5429 ((val % 64) ? 1 : 0);
5430 }
5431 } else
5432 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5433 high = low + 56; /* 14*1024/256 */
5434 }
5435 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5436 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 5437 }
1c06328c 5438
f2e0899f
DK		 5439 if (CHIP_MODE_IS_4_PORT(bp)) {
5440 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5441 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5442 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5443 BRB1_REG_MAC_GUARANTIED_0), 40);
5444 }
1c06328c 5445
94a78b79 5446 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
ca00392c 5447
94a78b79 5448 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
94a78b79 5449 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
94a78b79 5450 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
94a78b79 5451 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
356e2385 5452
94a78b79
VZ		 5453 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5454 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5455 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5456 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
f2e0899f
DK		 5457 if (CHIP_MODE_IS_4_PORT(bp))
5458 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
356e2385 5459
94a78b79 5460 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
94a78b79 5461 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
34f80b04 5462
94a78b79 5463 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
a2fbb9ea 5464
f2e0899f
DK		 5465 if (!CHIP_IS_E2(bp)) {
5466 /* configure PBF to work without PAUSE mtu 9000 */
5467 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 5468
f2e0899f
DK		 5469 /* update threshold */
5470 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5471 /* update init credit */
5472 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 5473
f2e0899f
DK		 5474 /* probe changes */
5475 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5476 udelay(50);
5477 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5478 }
a2fbb9ea 5479
37b091ba
MC		 5480#ifdef BCM_CNIC
5481 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
a2fbb9ea 5482#endif
94a78b79 5483 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
94a78b79 5484 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
34f80b04
EG		 5485
5486 if (CHIP_IS_E1(bp)) {
5487 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5488 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5489 }
94a78b79 5490 bnx2x_init_block(bp, HC_BLOCK, init_stage);
34f80b04 5491
f2e0899f
DK		 5492 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5493
94a78b79 5494 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
34f80b04
EG		 5495 /* init aeu_mask_attn_func_0/1:
5496 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5497 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5498 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 5499 val = IS_MF(bp) ? 0xF7 : 0x7;
5500 /* Enable DCBX attention for all but E1 */
5501 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5502 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 5503
94a78b79 5504 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
94a78b79 5505 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
94a78b79 5506 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
94a78b79 5507 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
94a78b79 5508 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
356e2385 5509
94a78b79 5510 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
34f80b04
EG		 5511
5512 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5513
f2e0899f 5514 if (!CHIP_IS_E1(bp)) {
fb3bff17 5515 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 5516 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 5517 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 5518
f2e0899f
DK		 5519 if (CHIP_IS_E2(bp)) {
5520 val = 0;
5521 switch (bp->mf_mode) {
5522 case MULTI_FUNCTION_SD:
5523 val = 1;
5524 break;
5525 case MULTI_FUNCTION_SI:
5526 val = 2;
5527 break;
5528 }
5529
5530 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5531 NIG_REG_LLH0_CLS_TYPE), val);
5532 }
1c06328c
EG		 5533 {
5534 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5535 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5536 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5537 }
34f80b04
EG		 5538 }
5539
94a78b79 5540 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
94a78b79 5541 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
d90d96ba 5542 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
a22f0788 5543 bp->common.shmem2_base, port)) {
4d295db0
EG		 5544 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5545 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5546 val = REG_RD(bp, reg_addr);
f1410647 5547 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 5548 REG_WR(bp, reg_addr, val);
f1410647 5549 }
c18487ee 5550 bnx2x__link_reset(bp);
a2fbb9ea 5551
34f80b04
EG		 5552 return 0;
5553}
5554
34f80b04
EG		 5555static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5556{
5557 int reg;
5558
f2e0899f 5559 if (CHIP_IS_E1(bp))
34f80b04 5560 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 5561 else
5562 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 5563
5564 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5565}
5566
f2e0899f
DK		 5567static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5568{
5569 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5570}
5571
5572static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5573{
5574 u32 i, base = FUNC_ILT_BASE(func);
5575 for (i = base; i < base + ILT_PER_FUNC; i++)
5576 bnx2x_ilt_wr(bp, i, 0);
5577}
5578
523224a3 5579static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 5580{
5581 int port = BP_PORT(bp);
5582 int func = BP_FUNC(bp);
523224a3
DK		 5583 struct bnx2x_ilt *ilt = BP_ILT(bp);
5584 u16 cdu_ilt_start;
8badd27a 5585 u32 addr, val;
f4a66897
VZ		 5586 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5587 int i, main_mem_width;
34f80b04 5588
cdaa7cb8 5589 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 5590
8badd27a 5591 /* set MSI reconfigure capability */
f2e0899f
DK		 5592 if (bp->common.int_block == INT_BLOCK_HC) {
5593 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5594 val = REG_RD(bp, addr);
5595 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5596 REG_WR(bp, addr, val);
5597 }
8badd27a 5598
523224a3
DK		 5599 ilt = BP_ILT(bp);
5600 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 5601
523224a3
DK		 5602 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5603 ilt->lines[cdu_ilt_start + i].page =
5604 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5605 ilt->lines[cdu_ilt_start + i].page_mapping =
5606 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5607 /* cdu ilt pages are allocated manually so there's no need to
5608 set the size */
37b091ba 5609 }
523224a3 5610 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 5611
523224a3
DK		 5612#ifdef BCM_CNIC
5613 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 5614
523224a3
DK		 5615 /* T1 hash bits value determines the T1 number of entries */
5616 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5617#endif
37b091ba 5618
523224a3
DK		 5619#ifndef BCM_CNIC
5620 /* set NIC mode */
5621 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5622#endif /* BCM_CNIC */
37b091ba 5623
f2e0899f
DK		 5624 if (CHIP_IS_E2(bp)) {
5625 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5626
5627 /* Turn on a single ISR mode in IGU if driver is going to use
5628 * INT#x or MSI
5629 */
5630 if (!(bp->flags & USING_MSIX_FLAG))
5631 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5632 /*
5633 * Timers workaround bug: function init part.
5634 * Need to wait 20msec after initializing ILT,
5635 * needed to make sure there are no requests in
5636 * one of the PXP internal queues with "old" ILT addresses
5637 */
5638 msleep(20);
5639 /*
5640 * Master enable - Due to WB DMAE writes performed before this
5641 * register is re-initialized as part of the regular function
5642 * init
5643 */
5644 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5645 /* Enable the function in IGU */
5646 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5647 }
5648
523224a3 5649 bp->dmae_ready = 1;
34f80b04 5650
523224a3
DK		 5651 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5652
f2e0899f
DK		 5653 if (CHIP_IS_E2(bp))
5654 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5655
523224a3
DK		 5656 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5657 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5658 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5659 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5660 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5661 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5662 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5663 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5664 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5665
f2e0899f
DK		 5666 if (CHIP_IS_E2(bp)) {
5667 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5668 BP_PATH(bp));
5669 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5670 BP_PATH(bp));
5671 }
5672
5673 if (CHIP_MODE_IS_4_PORT(bp))
5674 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5675
5676 if (CHIP_IS_E2(bp))
5677 REG_WR(bp, QM_REG_PF_EN, 1);
5678
523224a3 5679 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5680
5681 if (CHIP_MODE_IS_4_PORT(bp))
5682 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5683
523224a3
DK		 5684 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5685 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5686 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5687 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5688 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5689 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5690 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5691 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5692 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5693 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5694 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5695 if (CHIP_IS_E2(bp))
5696 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5697
523224a3
DK		 5698 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5699
5700 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
34f80b04 5701
f2e0899f
DK		 5702 if (CHIP_IS_E2(bp))
5703 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5704
fb3bff17 5705 if (IS_MF(bp)) {
34f80b04 5706 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 5707 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 5708 }
5709
523224a3
DK		 5710 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5711
34f80b04 5712 /* HC init per function */
f2e0899f
DK		 5713 if (bp->common.int_block == INT_BLOCK_HC) {
5714 if (CHIP_IS_E1H(bp)) {
5715 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5716
5717 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5718 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5719 }
5720 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5721
5722 } else {
5723 int num_segs, sb_idx, prod_offset;
5724
34f80b04
EG		 5725 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5726
f2e0899f
DK		 5727 if (CHIP_IS_E2(bp)) {
5728 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5729 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5730 }
5731
5732 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5733
5734 if (CHIP_IS_E2(bp)) {
5735 int dsb_idx = 0;
5736 /**
5737 * Producer memory:
5738 * E2 mode: address 0-135 match to the mapping memory;
5739 * 136 - PF0 default prod; 137 - PF1 default prod;
5740 * 138 - PF2 default prod; 139 - PF3 default prod;
5741 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5742 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5743 * 144-147 reserved.
5744 *
5745 * E1.5 mode - In backward compatible mode;
5746 * for non default SB; each even line in the memory
5747 * holds the U producer and each odd line hold
5748 * the C producer. The first 128 producers are for
5749 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5750 * producers are for the DSB for each PF.
5751 * Each PF has five segments: (the order inside each
5752 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5753 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5754 * 144-147 attn prods;
5755 */
5756 /* non-default-status-blocks */
5757 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5758 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5759 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5760 prod_offset = (bp->igu_base_sb + sb_idx) *
5761 num_segs;
5762
5763 for (i = 0; i < num_segs; i++) {
5764 addr = IGU_REG_PROD_CONS_MEMORY +
5765 (prod_offset + i) * 4;
5766 REG_WR(bp, addr, 0);
5767 }
5768 /* send consumer update with value 0 */
5769 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5770 USTORM_ID, 0, IGU_INT_NOP, 1);
5771 bnx2x_igu_clear_sb(bp,
5772 bp->igu_base_sb + sb_idx);
5773 }
5774
5775 /* default-status-blocks */
5776 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5777 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5778
5779 if (CHIP_MODE_IS_4_PORT(bp))
5780 dsb_idx = BP_FUNC(bp);
5781 else
5782 dsb_idx = BP_E1HVN(bp);
5783
5784 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5785 IGU_BC_BASE_DSB_PROD + dsb_idx :
5786 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5787
5788 for (i = 0; i < (num_segs * E1HVN_MAX);
5789 i += E1HVN_MAX) {
5790 addr = IGU_REG_PROD_CONS_MEMORY +
5791 (prod_offset + i)*4;
5792 REG_WR(bp, addr, 0);
5793 }
5794 /* send consumer update with 0 */
5795 if (CHIP_INT_MODE_IS_BC(bp)) {
5796 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5797 USTORM_ID, 0, IGU_INT_NOP, 1);
5798 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5799 CSTORM_ID, 0, IGU_INT_NOP, 1);
5800 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5801 XSTORM_ID, 0, IGU_INT_NOP, 1);
5802 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5803 TSTORM_ID, 0, IGU_INT_NOP, 1);
5804 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5805 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5806 } else {
5807 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5808 USTORM_ID, 0, IGU_INT_NOP, 1);
5809 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5810 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5811 }
5812 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5813
5814 /* !!! these should become driver const once
5815 rf-tool supports split-68 const */
5816 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5817 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5818 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5819 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5820 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5821 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5822 }
34f80b04 5823 }
34f80b04 5824
c14423fe 5825 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 5826 REG_WR(bp, 0x2114, 0xffffffff);
5827 REG_WR(bp, 0x2120, 0xffffffff);
523224a3
DK		 5828
5829 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5830 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5831 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5832 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5833 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5834 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5835
f4a66897
VZ		 5836 if (CHIP_IS_E1x(bp)) {
5837 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5838 main_mem_base = HC_REG_MAIN_MEMORY +
5839 BP_PORT(bp) * (main_mem_size * 4);
5840 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5841 main_mem_width = 8;
5842
5843 val = REG_RD(bp, main_mem_prty_clr);
5844 if (val)
5845 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5846 "block during "
5847 "function init (0x%x)!\n", val);
5848
5849 /* Clear "false" parity errors in MSI-X table */
5850 for (i = main_mem_base;
5851 i < main_mem_base + main_mem_size * 4;
5852 i += main_mem_width) {
5853 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5854 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5855 i, main_mem_width / 4);
5856 }
5857 /* Clear HC parity attention */
5858 REG_RD(bp, main_mem_prty_clr);
5859 }
5860
b7737c9b 5861 bnx2x_phy_probe(&bp->link_params);
f85582f8 5862
34f80b04
EG		 5863 return 0;
5864}
5865
9f6c9258 5866int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
34f80b04 5867{
523224a3 5868 int rc = 0;
a2fbb9ea 5869
34f80b04 5870 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
f2e0899f 5871 BP_ABS_FUNC(bp), load_code);
a2fbb9ea 5872
34f80b04 5873 bp->dmae_ready = 0;
6e30dd4e 5874 spin_lock_init(&bp->dmae_lock);
a2fbb9ea 5875
34f80b04
EG		 5876 switch (load_code) {
5877 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5878 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
523224a3 5879 rc = bnx2x_init_hw_common(bp, load_code);
34f80b04
EG		 5880 if (rc)
5881 goto init_hw_err;
5882 /* no break */
5883
5884 case FW_MSG_CODE_DRV_LOAD_PORT:
523224a3 5885 rc = bnx2x_init_hw_port(bp);
34f80b04
EG		 5886 if (rc)
5887 goto init_hw_err;
5888 /* no break */
5889
5890 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3 5891 rc = bnx2x_init_hw_func(bp);
34f80b04
EG		 5892 if (rc)
5893 goto init_hw_err;
5894 break;
5895
5896 default:
5897 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5898 break;
5899 }
5900
5901 if (!BP_NOMCP(bp)) {
f2e0899f 5902 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 5903
5904 bp->fw_drv_pulse_wr_seq =
f2e0899f 5905 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
a2fbb9ea 5906 DRV_PULSE_SEQ_MASK);
6fe49bb9
EG		 5907 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5908 }
a2fbb9ea 5909
34f80b04
EG		 5910init_hw_err:
5911 bnx2x_gunzip_end(bp);
5912
5913 return rc;
a2fbb9ea
ET		 5914}
5915
9f6c9258 5916void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 5917{
b3b83c3f 5918 bnx2x_gunzip_end(bp);
a2fbb9ea
ET		 5919
5920 /* fastpath */
b3b83c3f 5921 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 5922 /* end of fastpath */
5923
5924 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 5925 sizeof(struct host_sp_status_block));
a2fbb9ea
ET		 5926
5927 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 5928 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5929
523224a3
DK		 5930 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5931 bp->context.size);
5932
5933 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5934
5935 BNX2X_FREE(bp->ilt->lines);
f85582f8 5936
37b091ba 5937#ifdef BCM_CNIC
f2e0899f
DK		 5938 if (CHIP_IS_E2(bp))
5939 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5940 sizeof(struct host_hc_status_block_e2));
5941 else
5942 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5943 sizeof(struct host_hc_status_block_e1x));
f85582f8 5944
523224a3 5945 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 5946#endif
f85582f8 5947
7a9b2557 5948 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 5949
523224a3
DK		 5950 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5951 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5952
ab532cf3 5953 BNX2X_FREE(bp->rx_indir_table);
a2fbb9ea
ET		 5954}
5955
f2e0899f 5956
9f6c9258 5957int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 5958{
b3b83c3f
DK		 5959 if (bnx2x_gunzip_init(bp))
5960 return -ENOMEM;
8badd27a 5961
523224a3 5962#ifdef BCM_CNIC
f2e0899f
DK		 5963 if (CHIP_IS_E2(bp))
5964 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
5965 sizeof(struct host_hc_status_block_e2));
5966 else
5967 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
5968 sizeof(struct host_hc_status_block_e1x));
8badd27a 5969
523224a3
DK		 5970 /* allocate searcher T2 table */
5971 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
5972#endif
a2fbb9ea 5973
8badd27a 5974
523224a3
DK		 5975 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5976 sizeof(struct host_sp_status_block));
a2fbb9ea 5977
523224a3
DK		 5978 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5979 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5980
523224a3 5981 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
f85582f8 5982
523224a3
DK		 5983 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
5984 bp->context.size);
65abd74d 5985
523224a3 5986 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 5987
523224a3
DK		 5988 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
5989 goto alloc_mem_err;
65abd74d 5990
9f6c9258
DK		 5991 /* Slow path ring */
5992 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 5993
523224a3
DK		 5994 /* EQ */
5995 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
5996 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3
TH		 5997
5998 BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *
5999 TSTORM_INDIRECTION_TABLE_SIZE);
b3b83c3f
DK		 6000
6001 /* fastpath */
6002 /* need to be done at the end, since it's self adjusting to amount
6003 * of memory available for RSS queues
6004 */
6005 if (bnx2x_alloc_fp_mem(bp))
6006 goto alloc_mem_err;
9f6c9258 6007 return 0;
e1510706 6008
9f6c9258
DK		 6009alloc_mem_err:
6010 bnx2x_free_mem(bp);
6011 return -ENOMEM;
65abd74d
YG		 6012}
6013
a2fbb9ea
ET		 6014/*
6015 * Init service functions
6016 */
8d96286a 6017static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6018 int *state_p, int flags);
6019
523224a3 6020int bnx2x_func_start(struct bnx2x *bp)
a2fbb9ea 6021{
523224a3 6022 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
a2fbb9ea 6023
523224a3
DK		 6024 /* Wait for completion */
6025 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6026 WAIT_RAMROD_COMMON);
6027}
a2fbb9ea 6028
8d96286a 6029static int bnx2x_func_stop(struct bnx2x *bp)
523224a3
DK		 6030{
6031 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
a2fbb9ea 6032
523224a3
DK		 6033 /* Wait for completion */
6034 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6035 0, &(bp->state), WAIT_RAMROD_COMMON);
a2fbb9ea
ET		 6036}
6037
e665bfda 6038/**
e8920674 6039 * bnx2x_set_mac_addr_gen - set a MAC in a CAM for a few L2 Clients for E1x chips
e665bfda 6040 *
e8920674
DK		 6041 * @bp: driver handle
6042 * @set: set or clear an entry (1 or 0)
6043 * @mac: pointer to a buffer containing a MAC
6044 * @cl_bit_vec: bit vector of clients to register a MAC for
6045 * @cam_offset: offset in a CAM to use
6046 * @is_bcast: is the set MAC a broadcast address (for E1 only)
e665bfda 6047 */
215faf9c 6048static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
f85582f8
DK		 6049 u32 cl_bit_vec, u8 cam_offset,
6050 u8 is_bcast)
34f80b04 6051{
523224a3
DK		 6052 struct mac_configuration_cmd *config =
6053 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6054 int ramrod_flags = WAIT_RAMROD_COMMON;
6055
6056 bp->set_mac_pending = 1;
523224a3 6057
8d9c5f34 6058 config->hdr.length = 1;
e665bfda
MC		 6059 config->hdr.offset = cam_offset;
6060 config->hdr.client_id = 0xff;
6e30dd4e
VZ		 6061 /* Mark the single MAC configuration ramrod as opposed to a
6062 * UC/MC list configuration).
6063 */
6064 config->hdr.echo = 1;
34f80b04
EG		 6065
6066 /* primary MAC */
6067 config->config_table[0].msb_mac_addr =
e665bfda 6068 swab16(*(u16 *)&mac[0]);
34f80b04 6069 config->config_table[0].middle_mac_addr =
e665bfda 6070 swab16(*(u16 *)&mac[2]);
34f80b04 6071 config->config_table[0].lsb_mac_addr =
e665bfda 6072 swab16(*(u16 *)&mac[4]);
ca00392c 6073 config->config_table[0].clients_bit_vector =
e665bfda 6074 cpu_to_le32(cl_bit_vec);
34f80b04 6075 config->config_table[0].vlan_id = 0;
523224a3 6076 config->config_table[0].pf_id = BP_FUNC(bp);
3101c2bc 6077 if (set)
523224a3
DK		 6078 SET_FLAG(config->config_table[0].flags,
6079 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6080 T_ETH_MAC_COMMAND_SET);
3101c2bc 6081 else
523224a3
DK		 6082 SET_FLAG(config->config_table[0].flags,
6083 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6084 T_ETH_MAC_COMMAND_INVALIDATE);
34f80b04 6085
523224a3
DK		 6086 if (is_bcast)
6087 SET_FLAG(config->config_table[0].flags,
6088 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6089
6090 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
3101c2bc 6091 (set ? "setting" : "clearing"),
34f80b04
EG		 6092 config->config_table[0].msb_mac_addr,
6093 config->config_table[0].middle_mac_addr,
523224a3 6094 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
34f80b04 6095
6e30dd4e
VZ		 6096 mb();
6097
523224a3 6098 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
34f80b04 6099 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3
DK		 6100 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6101
6102 /* Wait for a completion */
6103 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
34f80b04
EG		 6104}
6105
8d96286a 6106static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6107 int *state_p, int flags)
a2fbb9ea
ET		 6108{
6109 /* can take a while if any port is running */
8b3a0f0b 6110 int cnt = 5000;
523224a3
DK		 6111 u8 poll = flags & WAIT_RAMROD_POLL;
6112 u8 common = flags & WAIT_RAMROD_COMMON;
a2fbb9ea 6113
c14423fe
ET		 6114 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6115 poll ? "polling" : "waiting", state, idx);
a2fbb9ea
ET		 6116
6117 might_sleep();
34f80b04 6118 while (cnt--) {
a2fbb9ea 6119 if (poll) {
523224a3
DK		 6120 if (common)
6121 bnx2x_eq_int(bp);
6122 else {
6123 bnx2x_rx_int(bp->fp, 10);
6124 /* if index is different from 0
6125 * the reply for some commands will
6126 * be on the non default queue
6127 */
6128 if (idx)
6129 bnx2x_rx_int(&bp->fp[idx], 10);
6130 }
a2fbb9ea 6131 }
a2fbb9ea 6132
3101c2bc 6133 mb(); /* state is changed by bnx2x_sp_event() */
8b3a0f0b
EG		 6134 if (*state_p == state) {
6135#ifdef BNX2X_STOP_ON_ERROR
6136 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6137#endif
a2fbb9ea 6138 return 0;
8b3a0f0b 6139 }
a2fbb9ea 6140
a2fbb9ea 6141 msleep(1);
e3553b29
EG		 6142
6143 if (bp->panic)
6144 return -EIO;
a2fbb9ea
ET		 6145 }
6146
a2fbb9ea 6147 /* timeout! */
49d66772
ET		 6148 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6149 poll ? "polling" : "waiting", state, idx);
34f80b04
EG		 6150#ifdef BNX2X_STOP_ON_ERROR
6151 bnx2x_panic();
6152#endif
a2fbb9ea 6153
49d66772 6154 return -EBUSY;
a2fbb9ea
ET		 6155}
6156
8d96286a 6157static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
e665bfda 6158{
f2e0899f
DK		 6159 if (CHIP_IS_E1H(bp))
6160 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6161 else if (CHIP_MODE_IS_4_PORT(bp))
6e30dd4e 6162 return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);
f2e0899f 6163 else
6e30dd4e 6164 return E2_FUNC_MAX * rel_offset + BP_VN(bp);
523224a3
DK		 6165}
6166
0793f83f
DK		 6167/**
6168 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6169 * relevant. In addition, current implementation is tuned for a
6170 * single ETH MAC.
0793f83f
DK		 6171 */
6172enum {
6173 LLH_CAM_ISCSI_ETH_LINE = 0,
6174 LLH_CAM_ETH_LINE,
6175 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6176};
6177
6178static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6179 int set,
6180 unsigned char *dev_addr,
6181 int index)
6182{
6183 u32 wb_data[2];
6184 u32 mem_offset, ena_offset, mem_index;
6185 /**
6186 * indexes mapping:
6187 * 0..7 - goes to MEM
6188 * 8..15 - goes to MEM2
6189 */
6190
6191 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6192 return;
6193
6194 /* calculate memory start offset according to the mapping
6195 * and index in the memory */
6196 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6197 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6198 NIG_REG_LLH0_FUNC_MEM;
6199 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6200 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6201 mem_index = index;
6202 } else {
6203 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6204 NIG_REG_P0_LLH_FUNC_MEM2;
6205 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6206 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6207 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6208 }
6209
6210 if (set) {
6211 /* LLH_FUNC_MEM is a u64 WB register */
6212 mem_offset += 8*mem_index;
6213
6214 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6215 (dev_addr[4] << 8) | dev_addr[5]);
6216 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6217
6218 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6219 }
6220
6221 /* enable/disable the entry */
6222 REG_WR(bp, ena_offset + 4*mem_index, set);
6223
6224}
6225
523224a3
DK		 6226void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6227{
6228 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6229 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
e665bfda 6230
523224a3
DK		 6231 /* networking MAC */
6232 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6233 (1 << bp->fp->cl_id), cam_offset , 0);
e665bfda 6234
0793f83f
DK		 6235 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6236
523224a3
DK		 6237 if (CHIP_IS_E1(bp)) {
6238 /* broadcast MAC */
215faf9c
JP		 6239 static const u8 bcast[ETH_ALEN] = {
6240 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6241 };
523224a3
DK		 6242 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6243 }
e665bfda 6244}
6e30dd4e
VZ		 6245
6246static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)
6247{
6248 return CHIP_REV_IS_SLOW(bp) ?
6249 (BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :
6250 (BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));
6251}
6252
6253/* set mc list, do not wait as wait implies sleep and
6254 * set_rx_mode can be invoked from non-sleepable context.
6255 *
6256 * Instead we use the same ramrod data buffer each time we need
6257 * to configure a list of addresses, and use the fact that the
6258 * list of MACs is changed in an incremental way and that the
6259 * function is called under the netif_addr_lock. A temporary
6260 * inconsistent CAM configuration (possible in case of a very fast
6261 * sequence of add/del/add on the host side) will shortly be
6262 * restored by the handler of the last ramrod.
6263 */
6264static int bnx2x_set_e1_mc_list(struct bnx2x *bp)
523224a3
DK		 6265{
6266 int i = 0, old;
6267 struct net_device *dev = bp->dev;
6e30dd4e 6268 u8 offset = bnx2x_e1_cam_mc_offset(bp);
523224a3
DK		 6269 struct netdev_hw_addr *ha;
6270 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6271 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6272
6e30dd4e
VZ		 6273 if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)
6274 return -EINVAL;
6275
523224a3
DK		 6276 netdev_for_each_mc_addr(ha, dev) {
6277 /* copy mac */
6278 config_cmd->config_table[i].msb_mac_addr =
6279 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6280 config_cmd->config_table[i].middle_mac_addr =
6281 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6282 config_cmd->config_table[i].lsb_mac_addr =
6283 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
e665bfda 6284
523224a3
DK		 6285 config_cmd->config_table[i].vlan_id = 0;
6286 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6287 config_cmd->config_table[i].clients_bit_vector =
6288 cpu_to_le32(1 << BP_L_ID(bp));
6289
6290 SET_FLAG(config_cmd->config_table[i].flags,
6291 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6292 T_ETH_MAC_COMMAND_SET);
6293
6294 DP(NETIF_MSG_IFUP,
6295 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6296 config_cmd->config_table[i].msb_mac_addr,
6297 config_cmd->config_table[i].middle_mac_addr,
6298 config_cmd->config_table[i].lsb_mac_addr);
6299 i++;
6300 }
6301 old = config_cmd->hdr.length;
6302 if (old > i) {
6303 for (; i < old; i++) {
6304 if (CAM_IS_INVALID(config_cmd->
6305 config_table[i])) {
6306 /* already invalidated */
6307 break;
6308 }
6309 /* invalidate */
6310 SET_FLAG(config_cmd->config_table[i].flags,
6311 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6312 T_ETH_MAC_COMMAND_INVALIDATE);
6313 }
6314 }
6315
6e30dd4e
VZ		 6316 wmb();
6317
523224a3
DK		 6318 config_cmd->hdr.length = i;
6319 config_cmd->hdr.offset = offset;
6320 config_cmd->hdr.client_id = 0xff;
6e30dd4e
VZ		 6321 /* Mark that this ramrod doesn't use bp->set_mac_pending for
6322 * synchronization.
6323 */
6324 config_cmd->hdr.echo = 0;
523224a3 6325
6e30dd4e 6326 mb();
523224a3 6327
6e30dd4e 6328 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
523224a3
DK		 6329 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6330}
6e30dd4e
VZ		 6331
6332void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)
e665bfda 6333{
523224a3
DK		 6334 int i;
6335 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6336 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6337 int ramrod_flags = WAIT_RAMROD_COMMON;
6e30dd4e 6338 u8 offset = bnx2x_e1_cam_mc_offset(bp);
523224a3 6339
6e30dd4e 6340 for (i = 0; i < BNX2X_MAX_MULTICAST; i++)
523224a3
DK		 6341 SET_FLAG(config_cmd->config_table[i].flags,
6342 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6343 T_ETH_MAC_COMMAND_INVALIDATE);
6344
6e30dd4e
VZ		 6345 wmb();
6346
6347 config_cmd->hdr.length = BNX2X_MAX_MULTICAST;
6348 config_cmd->hdr.offset = offset;
6349 config_cmd->hdr.client_id = 0xff;
6350 /* We'll wait for a completion this time... */
6351 config_cmd->hdr.echo = 1;
6352
6353 bp->set_mac_pending = 1;
6354
6355 mb();
6356
523224a3
DK		 6357 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6358 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
e665bfda
MC		 6359
6360 /* Wait for a completion */
523224a3
DK		 6361 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6362 ramrod_flags);
6363
e665bfda
MC		 6364}
6365
6e30dd4e
VZ		 6366/* Accept one or more multicasts */
6367static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)
6368{
6369 struct net_device *dev = bp->dev;
6370 struct netdev_hw_addr *ha;
6371 u32 mc_filter[MC_HASH_SIZE];
6372 u32 crc, bit, regidx;
6373 int i;
6374
6375 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6376
6377 netdev_for_each_mc_addr(ha, dev) {
6378 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6379 bnx2x_mc_addr(ha));
6380
6381 crc = crc32c_le(0, bnx2x_mc_addr(ha),
6382 ETH_ALEN);
6383 bit = (crc >> 24) & 0xff;
6384 regidx = bit >> 5;
6385 bit &= 0x1f;
6386 mc_filter[regidx] |= (1 << bit);
6387 }
6388
6389 for (i = 0; i < MC_HASH_SIZE; i++)
6390 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6391 mc_filter[i]);
6392
6393 return 0;
6394}
6395
6396void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)
6397{
6398 int i;
6399
6400 for (i = 0; i < MC_HASH_SIZE; i++)
6401 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6402}
6403
993ac7b5
MC		 6404#ifdef BCM_CNIC
6405/**
e8920674 6406 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
993ac7b5 6407 *
e8920674
DK		 6408 * @bp: driver handle
6409 * @set: set or clear the CAM entry
993ac7b5 6410 *
e8920674
DK		 6411 * This function will wait until the ramdord completion returns.
6412 * Return 0 if success, -ENODEV if ramrod doesn't return.
993ac7b5 6413 */
8d96286a 6414static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
993ac7b5 6415{
523224a3
DK		 6416 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6417 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
ec6ba945
VZ		 6418 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6419 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
523224a3 6420 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
2ba45142 6421 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
993ac7b5
MC		 6422
6423 /* Send a SET_MAC ramrod */
2ba45142 6424 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
523224a3 6425 cam_offset, 0);
0793f83f 6426
2ba45142 6427 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
ec6ba945
VZ		 6428
6429 return 0;
6430}
6431
6432/**
e8920674 6433 * bnx2x_set_fip_eth_mac_addr - set FCoE L2 MAC(s)
ec6ba945 6434 *
e8920674
DK		 6435 * @bp: driver handle
6436 * @set: set or clear the CAM entry
ec6ba945 6437 *
e8920674
DK		 6438 * This function will wait until the ramrod completion returns.
6439 * Returns 0 if success, -ENODEV if ramrod doesn't return.
ec6ba945
VZ		 6440 */
6441int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6442{
6443 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6444 /**
6445 * CAM allocation for E1H
6446 * eth unicasts: by func number
6447 * iscsi: by func number
6448 * fip unicast: by func number
6449 * fip multicast: by func number
6450 */
6451 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6452 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6453
6454 return 0;
6455}
6456
6457int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6458{
6459 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6460
6461 /**
6462 * CAM allocation for E1H
6463 * eth unicasts: by func number
6464 * iscsi: by func number
6465 * fip unicast: by func number
6466 * fip multicast: by func number
6467 */
6468 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6469 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6470
993ac7b5
MC		 6471 return 0;
6472}
6473#endif
6474
523224a3
DK		 6475static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6476 struct bnx2x_client_init_params *params,
6477 u8 activate,
6478 struct client_init_ramrod_data *data)
6479{
6480 /* Clear the buffer */
6481 memset(data, 0, sizeof(*data));
6482
6483 /* general */
6484 data->general.client_id = params->rxq_params.cl_id;
6485 data->general.statistics_counter_id = params->rxq_params.stat_id;
6486 data->general.statistics_en_flg =
6487 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
ec6ba945
VZ		 6488 data->general.is_fcoe_flg =
6489 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
523224a3
DK		 6490 data->general.activate_flg = activate;
6491 data->general.sp_client_id = params->rxq_params.spcl_id;
6492
6493 /* Rx data */
6494 data->rx.tpa_en_flg =
6495 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6496 data->rx.vmqueue_mode_en_flg = 0;
6497 data->rx.cache_line_alignment_log_size =
6498 params->rxq_params.cache_line_log;
6499 data->rx.enable_dynamic_hc =
6500 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6501 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6502 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6503 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6504
6505 /* We don't set drop flags */
6506 data->rx.drop_ip_cs_err_flg = 0;
6507 data->rx.drop_tcp_cs_err_flg = 0;
6508 data->rx.drop_ttl0_flg = 0;
6509 data->rx.drop_udp_cs_err_flg = 0;
6510
6511 data->rx.inner_vlan_removal_enable_flg =
6512 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6513 data->rx.outer_vlan_removal_enable_flg =
6514 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6515 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6516 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6517 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6518 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6519 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6520 data->rx.bd_page_base.lo =
6521 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6522 data->rx.bd_page_base.hi =
6523 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6524 data->rx.sge_page_base.lo =
6525 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6526 data->rx.sge_page_base.hi =
6527 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6528 data->rx.cqe_page_base.lo =
6529 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6530 data->rx.cqe_page_base.hi =
6531 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6532 data->rx.is_leading_rss =
6533 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6534 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6535
6536 /* Tx data */
6537 data->tx.enforce_security_flg = 0; /* VF specific */
6538 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6539 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6540 data->tx.mtu = 0; /* VF specific */
6541 data->tx.tx_bd_page_base.lo =
6542 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6543 data->tx.tx_bd_page_base.hi =
6544 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6545
6546 /* flow control data */
6547 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6548 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6549 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6550 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6551 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6552 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6553 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6554
6555 data->fc.safc_group_num = params->txq_params.cos;
6556 data->fc.safc_group_en_flg =
6557 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
ec6ba945
VZ		 6558 data->fc.traffic_type =
6559 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6560 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
523224a3
DK		 6561}
6562
6563static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6564{
6565 /* ustorm cxt validation */
6566 cxt->ustorm_ag_context.cdu_usage =
6567 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6568 ETH_CONNECTION_TYPE);
6569 /* xcontext validation */
6570 cxt->xstorm_ag_context.cdu_reserved =
6571 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6572 ETH_CONNECTION_TYPE);
6573}
6574
8d96286a 6575static int bnx2x_setup_fw_client(struct bnx2x *bp,
6576 struct bnx2x_client_init_params *params,
6577 u8 activate,
6578 struct client_init_ramrod_data *data,
6579 dma_addr_t data_mapping)
523224a3
DK		 6580{
6581 u16 hc_usec;
6582 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6583 int ramrod_flags = 0, rc;
6584
6585 /* HC and context validation values */
6586 hc_usec = params->txq_params.hc_rate ?
6587 1000000 / params->txq_params.hc_rate : 0;
6588 bnx2x_update_coalesce_sb_index(bp,
6589 params->txq_params.fw_sb_id,
6590 params->txq_params.sb_cq_index,
6591 !(params->txq_params.flags & QUEUE_FLG_HC),
6592 hc_usec);
6593
6594 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6595
6596 hc_usec = params->rxq_params.hc_rate ?
6597 1000000 / params->rxq_params.hc_rate : 0;
6598 bnx2x_update_coalesce_sb_index(bp,
6599 params->rxq_params.fw_sb_id,
6600 params->rxq_params.sb_cq_index,
6601 !(params->rxq_params.flags & QUEUE_FLG_HC),
6602 hc_usec);
6603
6604 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6605 params->rxq_params.cid);
6606
6607 /* zero stats */
6608 if (params->txq_params.flags & QUEUE_FLG_STATS)
6609 storm_memset_xstats_zero(bp, BP_PORT(bp),
6610 params->txq_params.stat_id);
6611
6612 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6613 storm_memset_ustats_zero(bp, BP_PORT(bp),
6614 params->rxq_params.stat_id);
6615 storm_memset_tstats_zero(bp, BP_PORT(bp),
6616 params->rxq_params.stat_id);
6617 }
6618
6619 /* Fill the ramrod data */
6620 bnx2x_fill_cl_init_data(bp, params, activate, data);
6621
6622 /* SETUP ramrod.
6623 *
6624 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6625 * barrier except from mmiowb() is needed to impose a
6626 * proper ordering of memory operations.
6627 */
6628 mmiowb();
a2fbb9ea 6629
a2fbb9ea 6630
523224a3
DK		 6631 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6632 U64_HI(data_mapping), U64_LO(data_mapping), 0);
a2fbb9ea 6633
34f80b04 6634 /* Wait for completion */
523224a3
DK		 6635 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6636 params->ramrod_params.index,
6637 params->ramrod_params.pstate,
6638 ramrod_flags);
34f80b04 6639 return rc;
a2fbb9ea
ET		 6640}
6641
d6214d7a 6642/**
e8920674 6643 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 6644 *
e8920674 6645 * @bp: driver handle
d6214d7a 6646 *
e8920674 6647 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a
DK		 6648 */
6649static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6650{
d6214d7a 6651 int rc = 0;
ca00392c 6652
d6214d7a
DK		 6653 switch (bp->int_mode) {
6654 case INT_MODE_MSI:
6655 bnx2x_enable_msi(bp);
6656 /* falling through... */
6657 case INT_MODE_INTx:
ec6ba945 6658 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a 6659 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6660 break;
d6214d7a
DK		 6661 default:
6662 /* Set number of queues according to bp->multi_mode value */
6663 bnx2x_set_num_queues(bp);
ca00392c 6664
d6214d7a
DK		 6665 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6666 bp->num_queues);
ca00392c 6667
d6214d7a
DK		 6668 /* if we can't use MSI-X we only need one fp,
6669 * so try to enable MSI-X with the requested number of fp's
6670 * and fallback to MSI or legacy INTx with one fp
6671 */
6672 rc = bnx2x_enable_msix(bp);
6673 if (rc) {
6674 /* failed to enable MSI-X */
6675 if (bp->multi_mode)
6676 DP(NETIF_MSG_IFUP,
6677 "Multi requested but failed to "
6678 "enable MSI-X (%d), "
6679 "set number of queues to %d\n",
6680 bp->num_queues,
ec6ba945
VZ		 6681 1 + NONE_ETH_CONTEXT_USE);
6682 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a
DK		 6683
6684 if (!(bp->flags & DISABLE_MSI_FLAG))
6685 bnx2x_enable_msi(bp);
6686 }
ca00392c 6687
9f6c9258
DK		 6688 break;
6689 }
d6214d7a
DK		 6690
6691 return rc;
a2fbb9ea
ET		 6692}
6693
c2bff63f
DK		 6694/* must be called prioir to any HW initializations */
6695static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6696{
6697 return L2_ILT_LINES(bp);
6698}
6699
523224a3
DK		 6700void bnx2x_ilt_set_info(struct bnx2x *bp)
6701{
6702 struct ilt_client_info *ilt_client;
6703 struct bnx2x_ilt *ilt = BP_ILT(bp);
6704 u16 line = 0;
6705
6706 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6707 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6708
6709 /* CDU */
6710 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6711 ilt_client->client_num = ILT_CLIENT_CDU;
6712 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6713 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6714 ilt_client->start = line;
6715 line += L2_ILT_LINES(bp);
6716#ifdef BCM_CNIC
6717 line += CNIC_ILT_LINES;
6718#endif
6719 ilt_client->end = line - 1;
6720
6721 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6722 "flags 0x%x, hw psz %d\n",
6723 ilt_client->start,
6724 ilt_client->end,
6725 ilt_client->page_size,
6726 ilt_client->flags,
6727 ilog2(ilt_client->page_size >> 12));
6728
6729 /* QM */
6730 if (QM_INIT(bp->qm_cid_count)) {
6731 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6732 ilt_client->client_num = ILT_CLIENT_QM;
6733 ilt_client->page_size = QM_ILT_PAGE_SZ;
6734 ilt_client->flags = 0;
6735 ilt_client->start = line;
6736
6737 /* 4 bytes for each cid */
6738 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6739 QM_ILT_PAGE_SZ);
6740
6741 ilt_client->end = line - 1;
6742
6743 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6744 "flags 0x%x, hw psz %d\n",
6745 ilt_client->start,
6746 ilt_client->end,
6747 ilt_client->page_size,
6748 ilt_client->flags,
6749 ilog2(ilt_client->page_size >> 12));
6750
6751 }
6752 /* SRC */
6753 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6754#ifdef BCM_CNIC
6755 ilt_client->client_num = ILT_CLIENT_SRC;
6756 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6757 ilt_client->flags = 0;
6758 ilt_client->start = line;
6759 line += SRC_ILT_LINES;
6760 ilt_client->end = line - 1;
6761
6762 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6763 "flags 0x%x, hw psz %d\n",
6764 ilt_client->start,
6765 ilt_client->end,
6766 ilt_client->page_size,
6767 ilt_client->flags,
6768 ilog2(ilt_client->page_size >> 12));
6769
6770#else
6771 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6772#endif
9f6c9258 6773
523224a3
DK		 6774 /* TM */
6775 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6776#ifdef BCM_CNIC
6777 ilt_client->client_num = ILT_CLIENT_TM;
6778 ilt_client->page_size = TM_ILT_PAGE_SZ;
6779 ilt_client->flags = 0;
6780 ilt_client->start = line;
6781 line += TM_ILT_LINES;
6782 ilt_client->end = line - 1;
6783
6784 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6785 "flags 0x%x, hw psz %d\n",
6786 ilt_client->start,
6787 ilt_client->end,
6788 ilt_client->page_size,
6789 ilt_client->flags,
6790 ilog2(ilt_client->page_size >> 12));
9f6c9258 6791
523224a3
DK		 6792#else
6793 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6794#endif
6795}
f85582f8 6796
523224a3
DK		 6797int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6798 int is_leading)
a2fbb9ea 6799{
523224a3 6800 struct bnx2x_client_init_params params = { {0} };
a2fbb9ea
ET		 6801 int rc;
6802
ec6ba945
VZ		 6803 /* reset IGU state skip FCoE L2 queue */
6804 if (!IS_FCOE_FP(fp))
6805 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 6806 IGU_INT_ENABLE, 0);
a2fbb9ea 6807
523224a3
DK		 6808 params.ramrod_params.pstate = &fp->state;
6809 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6810 params.ramrod_params.index = fp->index;
6811 params.ramrod_params.cid = fp->cid;
a2fbb9ea 6812
ec6ba945
VZ		 6813#ifdef BCM_CNIC
6814 if (IS_FCOE_FP(fp))
6815 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6816
6817#endif
6818
523224a3
DK		 6819 if (is_leading)
6820 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
a2fbb9ea 6821
523224a3
DK		 6822 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6823
6824 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6825
6826 rc = bnx2x_setup_fw_client(bp, &params, 1,
6827 bnx2x_sp(bp, client_init_data),
6828 bnx2x_sp_mapping(bp, client_init_data));
34f80b04 6829 return rc;
a2fbb9ea
ET		 6830}
6831
8d96286a 6832static int bnx2x_stop_fw_client(struct bnx2x *bp,
6833 struct bnx2x_client_ramrod_params *p)
a2fbb9ea 6834{
34f80b04 6835 int rc;
a2fbb9ea 6836
523224a3 6837 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
a2fbb9ea 6838
523224a3
DK		 6839 /* halt the connection */
6840 *p->pstate = BNX2X_FP_STATE_HALTING;
6841 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6842 p->cl_id, 0);
a2fbb9ea 6843
34f80b04 6844 /* Wait for completion */
523224a3
DK		 6845 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6846 p->pstate, poll_flag);
34f80b04 6847 if (rc) /* timeout */
da5a662a 6848 return rc;
a2fbb9ea 6849
523224a3
DK		 6850 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6851 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6852 p->cl_id, 0);
6853 /* Wait for completion */
6854 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6855 p->pstate, poll_flag);
6856 if (rc) /* timeout */
6857 return rc;
a2fbb9ea 6858
a2fbb9ea 6859
523224a3
DK		 6860 /* delete cfc entry */
6861 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
da5a662a 6862
523224a3
DK		 6863 /* Wait for completion */
6864 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6865 p->pstate, WAIT_RAMROD_COMMON);
da5a662a 6866 return rc;
a2fbb9ea
ET		 6867}
6868
523224a3
DK		 6869static int bnx2x_stop_client(struct bnx2x *bp, int index)
6870{
6871 struct bnx2x_client_ramrod_params client_stop = {0};
6872 struct bnx2x_fastpath *fp = &bp->fp[index];
6873
6874 client_stop.index = index;
6875 client_stop.cid = fp->cid;
6876 client_stop.cl_id = fp->cl_id;
6877 client_stop.pstate = &(fp->state);
6878 client_stop.poll = 0;
6879
6880 return bnx2x_stop_fw_client(bp, &client_stop);
6881}
6882
6883
34f80b04
EG		 6884static void bnx2x_reset_func(struct bnx2x *bp)
6885{
6886 int port = BP_PORT(bp);
6887 int func = BP_FUNC(bp);
f2e0899f 6888 int i;
523224a3 6889 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
f2e0899f
DK		 6890 (CHIP_IS_E2(bp) ?
6891 offsetof(struct hc_status_block_data_e2, common) :
6892 offsetof(struct hc_status_block_data_e1x, common));
523224a3
DK		 6893 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6894 int pfid_offset = offsetof(struct pci_entity, pf_id);
6895
6896 /* Disable the function in the FW */
6897 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6898 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6899 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6900 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6901
6902 /* FP SBs */
ec6ba945 6903 for_each_eth_queue(bp, i) {
523224a3
DK		 6904 struct bnx2x_fastpath *fp = &bp->fp[i];
6905 REG_WR8(bp,
6906 BAR_CSTRORM_INTMEM +
6907 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6908 + pfunc_offset_fp + pfid_offset,
6909 HC_FUNCTION_DISABLED);
6910 }
6911
6912 /* SP SB */
6913 REG_WR8(bp,
6914 BAR_CSTRORM_INTMEM +
6915 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6916 pfunc_offset_sp + pfid_offset,
6917 HC_FUNCTION_DISABLED);
6918
6919
6920 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6921 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6922 0);
34f80b04
EG		 6923
6924 /* Configure IGU */
f2e0899f
DK		 6925 if (bp->common.int_block == INT_BLOCK_HC) {
6926 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6927 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6928 } else {
6929 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6930 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6931 }
34f80b04 6932
37b091ba
MC		 6933#ifdef BCM_CNIC
6934 /* Disable Timer scan */
6935 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6936 /*
6937 * Wait for at least 10ms and up to 2 second for the timers scan to
6938 * complete
6939 */
6940 for (i = 0; i < 200; i++) {
6941 msleep(10);
6942 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6943 break;
6944 }
6945#endif
34f80b04 6946 /* Clear ILT */
f2e0899f
DK		 6947 bnx2x_clear_func_ilt(bp, func);
6948
6949 /* Timers workaround bug for E2: if this is vnic-3,
6950 * we need to set the entire ilt range for this timers.
6951 */
6952 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6953 struct ilt_client_info ilt_cli;
6954 /* use dummy TM client */
6955 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6956 ilt_cli.start = 0;
6957 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6958 ilt_cli.client_num = ILT_CLIENT_TM;
6959
6960 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
6961 }
6962
6963 /* this assumes that reset_port() called before reset_func()*/
6964 if (CHIP_IS_E2(bp))
6965 bnx2x_pf_disable(bp);
523224a3
DK		 6966
6967 bp->dmae_ready = 0;
34f80b04
EG		 6968}
6969
6970static void bnx2x_reset_port(struct bnx2x *bp)
6971{
6972 int port = BP_PORT(bp);
6973 u32 val;
6974
6975 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6976
6977 /* Do not rcv packets to BRB */
6978 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6979 /* Do not direct rcv packets that are not for MCP to the BRB */
6980 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6981 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6982
6983 /* Configure AEU */
6984 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6985
6986 msleep(100);
6987 /* Check for BRB port occupancy */
6988 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6989 if (val)
6990 DP(NETIF_MSG_IFDOWN,
33471629 6991 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 6992
6993 /* TODO: Close Doorbell port? */
6994}
6995
34f80b04
EG		 6996static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6997{
6998 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
f2e0899f 6999 BP_ABS_FUNC(bp), reset_code);
34f80b04
EG		 7000
7001 switch (reset_code) {
7002 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7003 bnx2x_reset_port(bp);
7004 bnx2x_reset_func(bp);
7005 bnx2x_reset_common(bp);
7006 break;
7007
7008 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7009 bnx2x_reset_port(bp);
7010 bnx2x_reset_func(bp);
7011 break;
7012
7013 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7014 bnx2x_reset_func(bp);
7015 break;
49d66772 7016
34f80b04
EG		 7017 default:
7018 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7019 break;
7020 }
7021}
7022
ec6ba945
VZ		 7023#ifdef BCM_CNIC
7024static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7025{
7026 if (bp->flags & FCOE_MACS_SET) {
7027 if (!IS_MF_SD(bp))
7028 bnx2x_set_fip_eth_mac_addr(bp, 0);
7029
7030 bnx2x_set_all_enode_macs(bp, 0);
7031
7032 bp->flags &= ~FCOE_MACS_SET;
7033 }
7034}
7035#endif
7036
9f6c9258 7037void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
a2fbb9ea 7038{
da5a662a 7039 int port = BP_PORT(bp);
a2fbb9ea 7040 u32 reset_code = 0;
da5a662a 7041 int i, cnt, rc;
a2fbb9ea 7042
555f6c78 7043 /* Wait until tx fastpath tasks complete */
ec6ba945 7044 for_each_tx_queue(bp, i) {
228241eb
ET		 7045 struct bnx2x_fastpath *fp = &bp->fp[i];
7046
34f80b04 7047 cnt = 1000;
e8b5fc51 7048 while (bnx2x_has_tx_work_unload(fp)) {
da5a662a 7049
34f80b04
EG		 7050 if (!cnt) {
7051 BNX2X_ERR("timeout waiting for queue[%d]\n",
7052 i);
7053#ifdef BNX2X_STOP_ON_ERROR
7054 bnx2x_panic();
7055 return -EBUSY;
7056#else
7057 break;
7058#endif
7059 }
7060 cnt--;
da5a662a 7061 msleep(1);
34f80b04 7062 }
228241eb 7063 }
da5a662a
VZ		 7064 /* Give HW time to discard old tx messages */
7065 msleep(1);
a2fbb9ea 7066
6e30dd4e 7067 bnx2x_set_eth_mac(bp, 0);
65abd74d 7068
6e30dd4e 7069 bnx2x_invalidate_uc_list(bp);
3101c2bc 7070
6e30dd4e
VZ		 7071 if (CHIP_IS_E1(bp))
7072 bnx2x_invalidate_e1_mc_list(bp);
7073 else {
7074 bnx2x_invalidate_e1h_mc_list(bp);
7075 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3101c2bc 7076 }
523224a3 7077
993ac7b5 7078#ifdef BCM_CNIC
ec6ba945 7079 bnx2x_del_fcoe_eth_macs(bp);
993ac7b5 7080#endif
3101c2bc 7081
65abd74d
YG		 7082 if (unload_mode == UNLOAD_NORMAL)
7083 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7084
7d0446c2 7085 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7086 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7087
7d0446c2 7088 else if (bp->wol) {
65abd74d
YG		 7089 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7090 u8 *mac_addr = bp->dev->dev_addr;
7091 u32 val;
7092 /* The mac address is written to entries 1-4 to
7093 preserve entry 0 which is used by the PMF */
7094 u8 entry = (BP_E1HVN(bp) + 1)*8;
7095
7096 val = (mac_addr[0] << 8) | mac_addr[1];
7097 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7098
7099 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7100 (mac_addr[4] << 8) | mac_addr[5];
7101 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7102
7103 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7104
7105 } else
7106 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7107
34f80b04
EG		 7108 /* Close multi and leading connections
7109 Completions for ramrods are collected in a synchronous way */
523224a3
DK		 7110 for_each_queue(bp, i)
7111
7112 if (bnx2x_stop_client(bp, i))
7113#ifdef BNX2X_STOP_ON_ERROR
7114 return;
7115#else
228241eb 7116 goto unload_error;
523224a3 7117#endif
a2fbb9ea 7118
523224a3 7119 rc = bnx2x_func_stop(bp);
da5a662a 7120 if (rc) {
523224a3 7121 BNX2X_ERR("Function stop failed!\n");
da5a662a 7122#ifdef BNX2X_STOP_ON_ERROR
523224a3 7123 return;
da5a662a
VZ		 7124#else
7125 goto unload_error;
34f80b04 7126#endif
228241eb 7127 }
523224a3 7128#ifndef BNX2X_STOP_ON_ERROR
228241eb 7129unload_error:
523224a3 7130#endif
34f80b04 7131 if (!BP_NOMCP(bp))
a22f0788 7132 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04 7133 else {
f2e0899f
DK		 7134 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7135 "%d, %d, %d\n", BP_PATH(bp),
7136 load_count[BP_PATH(bp)][0],
7137 load_count[BP_PATH(bp)][1],
7138 load_count[BP_PATH(bp)][2]);
7139 load_count[BP_PATH(bp)][0]--;
7140 load_count[BP_PATH(bp)][1 + port]--;
7141 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7142 "%d, %d, %d\n", BP_PATH(bp),
7143 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7144 load_count[BP_PATH(bp)][2]);
7145 if (load_count[BP_PATH(bp)][0] == 0)
34f80b04 7146 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
f2e0899f 7147 else if (load_count[BP_PATH(bp)][1 + port] == 0)
34f80b04
EG		 7148 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7149 else
7150 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7151 }
a2fbb9ea 7152
34f80b04
EG		 7153 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7154 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7155 bnx2x__link_reset(bp);
a2fbb9ea 7156
523224a3
DK		 7157 /* Disable HW interrupts, NAPI */
7158 bnx2x_netif_stop(bp, 1);
7159
7160 /* Release IRQs */
d6214d7a 7161 bnx2x_free_irq(bp);
523224a3 7162
a2fbb9ea 7163 /* Reset the chip */
228241eb 7164 bnx2x_reset_chip(bp, reset_code);
a2fbb9ea
ET		 7165
7166 /* Report UNLOAD_DONE to MCP */
34f80b04 7167 if (!BP_NOMCP(bp))
a22f0788 7168 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
356e2385 7169
72fd0718
VZ		 7170}
7171
9f6c9258 7172void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7173{
7174 u32 val;
7175
7176 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7177
7178 if (CHIP_IS_E1(bp)) {
7179 int port = BP_PORT(bp);
7180 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7181 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7182
7183 val = REG_RD(bp, addr);
7184 val &= ~(0x300);
7185 REG_WR(bp, addr, val);
7186 } else if (CHIP_IS_E1H(bp)) {
7187 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7188 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7189 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7190 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7191 }
7192}
7193
72fd0718
VZ		 7194/* Close gates #2, #3 and #4: */
7195static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7196{
7197 u32 val, addr;
7198
7199 /* Gates #2 and #4a are closed/opened for "not E1" only */
7200 if (!CHIP_IS_E1(bp)) {
7201 /* #4 */
7202 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7203 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7204 close ? (val | 0x1) : (val & (~(u32)1)));
7205 /* #2 */
7206 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7207 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7208 close ? (val | 0x1) : (val & (~(u32)1)));
7209 }
7210
7211 /* #3 */
7212 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7213 val = REG_RD(bp, addr);
7214 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7215
7216 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7217 close ? "closing" : "opening");
7218 mmiowb();
7219}
7220
7221#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7222
7223static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7224{
7225 /* Do some magic... */
7226 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7227 *magic_val = val & SHARED_MF_CLP_MAGIC;
7228 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7229}
7230
e8920674
DK		 7231/**
7232 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7233 *
e8920674
DK		 7234 * @bp: driver handle
7235 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7236 */
7237static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7238{
7239 /* Restore the `magic' bit value... */
72fd0718
VZ		 7240 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7241 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7242 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7243}
7244
f85582f8 7245/**
e8920674 7246 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7247 *
e8920674
DK		 7248 * @bp: driver handle
7249 * @magic_val: old value of 'magic' bit.
7250 *
7251 * Takes care of CLP configurations.
72fd0718
VZ		 7252 */
7253static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7254{
7255 u32 shmem;
7256 u32 validity_offset;
7257
7258 DP(NETIF_MSG_HW, "Starting\n");
7259
7260 /* Set `magic' bit in order to save MF config */
7261 if (!CHIP_IS_E1(bp))
7262 bnx2x_clp_reset_prep(bp, magic_val);
7263
7264 /* Get shmem offset */
7265 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7266 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7267
7268 /* Clear validity map flags */
7269 if (shmem > 0)
7270 REG_WR(bp, shmem + validity_offset, 0);
7271}
7272
7273#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7274#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7275
e8920674
DK		 7276/**
7277 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7278 *
e8920674 7279 * @bp: driver handle
72fd0718
VZ		 7280 */
7281static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7282{
7283 /* special handling for emulation and FPGA,
7284 wait 10 times longer */
7285 if (CHIP_REV_IS_SLOW(bp))
7286 msleep(MCP_ONE_TIMEOUT*10);
7287 else
7288 msleep(MCP_ONE_TIMEOUT);
7289}
7290
7291static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7292{
7293 u32 shmem, cnt, validity_offset, val;
7294 int rc = 0;
7295
7296 msleep(100);
7297
7298 /* Get shmem offset */
7299 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7300 if (shmem == 0) {
7301 BNX2X_ERR("Shmem 0 return failure\n");
7302 rc = -ENOTTY;
7303 goto exit_lbl;
7304 }
7305
7306 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7307
7308 /* Wait for MCP to come up */
7309 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7310 /* TBD: its best to check validity map of last port.
7311 * currently checks on port 0.
7312 */
7313 val = REG_RD(bp, shmem + validity_offset);
7314 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7315 shmem + validity_offset, val);
7316
7317 /* check that shared memory is valid. */
7318 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7319 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7320 break;
7321
7322 bnx2x_mcp_wait_one(bp);
7323 }
7324
7325 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7326
7327 /* Check that shared memory is valid. This indicates that MCP is up. */
7328 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7329 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7330 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7331 rc = -ENOTTY;
7332 goto exit_lbl;
7333 }
7334
7335exit_lbl:
7336 /* Restore the `magic' bit value */
7337 if (!CHIP_IS_E1(bp))
7338 bnx2x_clp_reset_done(bp, magic_val);
7339
7340 return rc;
7341}
7342
7343static void bnx2x_pxp_prep(struct bnx2x *bp)
7344{
7345 if (!CHIP_IS_E1(bp)) {
7346 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7347 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7348 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7349 mmiowb();
7350 }
7351}
7352
7353/*
7354 * Reset the whole chip except for:
7355 * - PCIE core
7356 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7357 * one reset bit)
7358 * - IGU
7359 * - MISC (including AEU)
7360 * - GRC
7361 * - RBCN, RBCP
7362 */
7363static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7364{
7365 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7366
7367 not_reset_mask1 =
7368 MISC_REGISTERS_RESET_REG_1_RST_HC |
7369 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7370 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7371
7372 not_reset_mask2 =
7373 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7374 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7375 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7376 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7377 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7378 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7379 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7380 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7381
7382 reset_mask1 = 0xffffffff;
7383
7384 if (CHIP_IS_E1(bp))
7385 reset_mask2 = 0xffff;
7386 else
7387 reset_mask2 = 0x1ffff;
7388
7389 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7390 reset_mask1 & (~not_reset_mask1));
7391 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7392 reset_mask2 & (~not_reset_mask2));
7393
7394 barrier();
7395 mmiowb();
7396
7397 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7398 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7399 mmiowb();
7400}
7401
7402static int bnx2x_process_kill(struct bnx2x *bp)
7403{
7404 int cnt = 1000;
7405 u32 val = 0;
7406 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7407
7408
7409 /* Empty the Tetris buffer, wait for 1s */
7410 do {
7411 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7412 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7413 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7414 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7415 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7416 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7417 ((port_is_idle_0 & 0x1) == 0x1) &&
7418 ((port_is_idle_1 & 0x1) == 0x1) &&
7419 (pgl_exp_rom2 == 0xffffffff))
7420 break;
7421 msleep(1);
7422 } while (cnt-- > 0);
7423
7424 if (cnt <= 0) {
7425 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7426 " are still"
7427 " outstanding read requests after 1s!\n");
7428 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7429 " port_is_idle_0=0x%08x,"
7430 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7431 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7432 pgl_exp_rom2);
7433 return -EAGAIN;
7434 }
7435
7436 barrier();
7437
7438 /* Close gates #2, #3 and #4 */
7439 bnx2x_set_234_gates(bp, true);
7440
7441 /* TBD: Indicate that "process kill" is in progress to MCP */
7442
7443 /* Clear "unprepared" bit */
7444 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7445 barrier();
7446
7447 /* Make sure all is written to the chip before the reset */
7448 mmiowb();
7449
7450 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7451 * PSWHST, GRC and PSWRD Tetris buffer.
7452 */
7453 msleep(1);
7454
7455 /* Prepare to chip reset: */
7456 /* MCP */
7457 bnx2x_reset_mcp_prep(bp, &val);
7458
7459 /* PXP */
7460 bnx2x_pxp_prep(bp);
7461 barrier();
7462
7463 /* reset the chip */
7464 bnx2x_process_kill_chip_reset(bp);
7465 barrier();
7466
7467 /* Recover after reset: */
7468 /* MCP */
7469 if (bnx2x_reset_mcp_comp(bp, val))
7470 return -EAGAIN;
7471
7472 /* PXP */
7473 bnx2x_pxp_prep(bp);
7474
7475 /* Open the gates #2, #3 and #4 */
7476 bnx2x_set_234_gates(bp, false);
7477
7478 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7479 * reset state, re-enable attentions. */
7480
a2fbb9ea
ET		 7481 return 0;
7482}
7483
72fd0718
VZ		 7484static int bnx2x_leader_reset(struct bnx2x *bp)
7485{
7486 int rc = 0;
7487 /* Try to recover after the failure */
7488 if (bnx2x_process_kill(bp)) {
7489 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7490 bp->dev->name);
7491 rc = -EAGAIN;
7492 goto exit_leader_reset;
7493 }
7494
7495 /* Clear "reset is in progress" bit and update the driver state */
7496 bnx2x_set_reset_done(bp);
7497 bp->recovery_state = BNX2X_RECOVERY_DONE;
7498
7499exit_leader_reset:
7500 bp->is_leader = 0;
7501 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7502 smp_wmb();
7503 return rc;
7504}
7505
72fd0718
VZ		 7506/* Assumption: runs under rtnl lock. This together with the fact
7507 * that it's called only from bnx2x_reset_task() ensure that it
7508 * will never be called when netif_running(bp->dev) is false.
7509 */
7510static void bnx2x_parity_recover(struct bnx2x *bp)
7511{
7512 DP(NETIF_MSG_HW, "Handling parity\n");
7513 while (1) {
7514 switch (bp->recovery_state) {
7515 case BNX2X_RECOVERY_INIT:
7516 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7517 /* Try to get a LEADER_LOCK HW lock */
7518 if (bnx2x_trylock_hw_lock(bp,
7519 HW_LOCK_RESOURCE_RESERVED_08))
7520 bp->is_leader = 1;
7521
7522 /* Stop the driver */
7523 /* If interface has been removed - break */
7524 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7525 return;
7526
7527 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7528 /* Ensure "is_leader" and "recovery_state"
7529 * update values are seen on other CPUs
7530 */
7531 smp_wmb();
7532 break;
7533
7534 case BNX2X_RECOVERY_WAIT:
7535 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7536 if (bp->is_leader) {
7537 u32 load_counter = bnx2x_get_load_cnt(bp);
7538 if (load_counter) {
7539 /* Wait until all other functions get
7540 * down.
7541 */
7542 schedule_delayed_work(&bp->reset_task,
7543 HZ/10);
7544 return;
7545 } else {
7546 /* If all other functions got down -
7547 * try to bring the chip back to
7548 * normal. In any case it's an exit
7549 * point for a leader.
7550 */
7551 if (bnx2x_leader_reset(bp) ||
7552 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7553 printk(KERN_ERR"%s: Recovery "
7554 "has failed. Power cycle is "
7555 "needed.\n", bp->dev->name);
7556 /* Disconnect this device */
7557 netif_device_detach(bp->dev);
7558 /* Block ifup for all function
7559 * of this ASIC until
7560 * "process kill" or power
7561 * cycle.
7562 */
7563 bnx2x_set_reset_in_progress(bp);
7564 /* Shut down the power */
7565 bnx2x_set_power_state(bp,
7566 PCI_D3hot);
7567 return;
7568 }
7569
7570 return;
7571 }
7572 } else { /* non-leader */
7573 if (!bnx2x_reset_is_done(bp)) {
7574 /* Try to get a LEADER_LOCK HW lock as
7575 * long as a former leader may have
7576 * been unloaded by the user or
7577 * released a leadership by another
7578 * reason.
7579 */
7580 if (bnx2x_trylock_hw_lock(bp,
7581 HW_LOCK_RESOURCE_RESERVED_08)) {
7582 /* I'm a leader now! Restart a
7583 * switch case.
7584 */
7585 bp->is_leader = 1;
7586 break;
7587 }
7588
7589 schedule_delayed_work(&bp->reset_task,
7590 HZ/10);
7591 return;
7592
7593 } else { /* A leader has completed
7594 * the "process kill". It's an exit
7595 * point for a non-leader.
7596 */
7597 bnx2x_nic_load(bp, LOAD_NORMAL);
7598 bp->recovery_state =
7599 BNX2X_RECOVERY_DONE;
7600 smp_wmb();
7601 return;
7602 }
7603 }
7604 default:
7605 return;
7606 }
7607 }
7608}
7609
7610/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7611 * scheduled on a general queue in order to prevent a dead lock.
7612 */
34f80b04
EG		 7613static void bnx2x_reset_task(struct work_struct *work)
7614{
72fd0718 7615 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
34f80b04
EG		 7616
7617#ifdef BNX2X_STOP_ON_ERROR
7618 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7619 " so reset not done to allow debug dump,\n"
72fd0718 7620 KERN_ERR " you will need to reboot when done\n");
34f80b04
EG		 7621 return;
7622#endif
7623
7624 rtnl_lock();
7625
7626 if (!netif_running(bp->dev))
7627 goto reset_task_exit;
7628
72fd0718
VZ		 7629 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7630 bnx2x_parity_recover(bp);
7631 else {
7632 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7633 bnx2x_nic_load(bp, LOAD_NORMAL);
7634 }
34f80b04
EG		 7635
7636reset_task_exit:
7637 rtnl_unlock();
7638}
7639
a2fbb9ea
ET		 7640/* end of nic load/unload */
7641
a2fbb9ea
ET		 7642/*
7643 * Init service functions
7644 */
7645
8d96286a 7646static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 7647{
7648 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7649 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7650 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 7651}
7652
f2e0899f 7653static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 7654{
f2e0899f 7655 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 7656
7657 /* Flush all outstanding writes */
7658 mmiowb();
7659
7660 /* Pretend to be function 0 */
7661 REG_WR(bp, reg, 0);
f2e0899f 7662 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 7663
7664 /* From now we are in the "like-E1" mode */
7665 bnx2x_int_disable(bp);
7666
7667 /* Flush all outstanding writes */
7668 mmiowb();
7669
f2e0899f
DK		 7670 /* Restore the original function */
7671 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7672 REG_RD(bp, reg);
f1ef27ef
EG		 7673}
7674
f2e0899f 7675static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 7676{
f2e0899f 7677 if (CHIP_IS_E1(bp))
f1ef27ef 7678 bnx2x_int_disable(bp);
f2e0899f
DK		 7679 else
7680 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 7681}
7682
34f80b04
EG		 7683static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7684{
7685 u32 val;
7686
7687 /* Check if there is any driver already loaded */
7688 val = REG_RD(bp, MISC_REG_UNPREPARED);
7689 if (val == 0x1) {
7690 /* Check if it is the UNDI driver
7691 * UNDI driver initializes CID offset for normal bell to 0x7
7692 */
4a37fb66 7693 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7694 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7695 if (val == 0x7) {
7696 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 7697 /* save our pf_num */
7698 int orig_pf_num = bp->pf_num;
da5a662a
VZ		 7699 u32 swap_en;
7700 u32 swap_val;
34f80b04 7701
b4661739
EG		 7702 /* clear the UNDI indication */
7703 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7704
34f80b04
EG		 7705 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7706
7707 /* try unload UNDI on port 0 */
f2e0899f 7708 bp->pf_num = 0;
da5a662a 7709 bp->fw_seq =
f2e0899f 7710 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7711 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 7712 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7713
7714 /* if UNDI is loaded on the other port */
7715 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7716
da5a662a 7717 /* send "DONE" for previous unload */
a22f0788
YR		 7718 bnx2x_fw_command(bp,
7719 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7720
7721 /* unload UNDI on port 1 */
f2e0899f 7722 bp->pf_num = 1;
da5a662a 7723 bp->fw_seq =
f2e0899f 7724 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 7725 DRV_MSG_SEQ_NUMBER_MASK);
7726 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7727
a22f0788 7728 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7729 }
7730
b4661739
EG		 7731 /* now it's safe to release the lock */
7732 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7733
f2e0899f 7734 bnx2x_undi_int_disable(bp);
da5a662a
VZ		 7735
7736 /* close input traffic and wait for it */
7737 /* Do not rcv packets to BRB */
7738 REG_WR(bp,
7739 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7740 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7741 /* Do not direct rcv packets that are not for MCP to
7742 * the BRB */
7743 REG_WR(bp,
7744 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7745 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7746 /* clear AEU */
7747 REG_WR(bp,
7748 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7749 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7750 msleep(10);
7751
7752 /* save NIG port swap info */
7753 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7754 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 7755 /* reset device */
7756 REG_WR(bp,
7757 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 7758 0xd3ffffff);
34f80b04
EG		 7759 REG_WR(bp,
7760 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7761 0x1403);
da5a662a
VZ		 7762 /* take the NIG out of reset and restore swap values */
7763 REG_WR(bp,
7764 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7765 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7766 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7767 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7768
7769 /* send unload done to the MCP */
a22f0788 7770 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7771
7772 /* restore our func and fw_seq */
f2e0899f 7773 bp->pf_num = orig_pf_num;
da5a662a 7774 bp->fw_seq =
f2e0899f 7775 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7776 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 7777 } else
7778 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7779 }
7780}
7781
7782static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7783{
7784 u32 val, val2, val3, val4, id;
72ce58c3 7785 u16 pmc;
34f80b04
EG		 7786
7787 /* Get the chip revision id and number. */
7788 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7789 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7790 id = ((val & 0xffff) << 16);
7791 val = REG_RD(bp, MISC_REG_CHIP_REV);
7792 id |= ((val & 0xf) << 12);
7793 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7794 id |= ((val & 0xff) << 4);
5a40e08e 7795 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 7796 id |= (val & 0xf);
7797 bp->common.chip_id = id;
523224a3
DK		 7798
7799 /* Set doorbell size */
7800 bp->db_size = (1 << BNX2X_DB_SHIFT);
7801
f2e0899f
DK		 7802 if (CHIP_IS_E2(bp)) {
7803 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7804 if ((val & 1) == 0)
7805 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7806 else
7807 val = (val >> 1) & 1;
7808 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7809 "2_PORT_MODE");
7810 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7811 CHIP_2_PORT_MODE;
7812
7813 if (CHIP_MODE_IS_4_PORT(bp))
7814 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7815 else
7816 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7817 } else {
7818 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7819 bp->pfid = bp->pf_num; /* 0..7 */
7820 }
7821
523224a3
DK		 7822 /*
7823 * set base FW non-default (fast path) status block id, this value is
7824 * used to initialize the fw_sb_id saved on the fp/queue structure to
7825 * determine the id used by the FW.
7826 */
f2e0899f
DK		 7827 if (CHIP_IS_E1x(bp))
7828 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7829 else /* E2 */
7830 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7831
7832 bp->link_params.chip_id = bp->common.chip_id;
7833 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 7834
1c06328c
EG		 7835 val = (REG_RD(bp, 0x2874) & 0x55);
7836 if ((bp->common.chip_id & 0x1) ||
7837 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7838 bp->flags |= ONE_PORT_FLAG;
7839 BNX2X_DEV_INFO("single port device\n");
7840 }
7841
34f80b04
EG		 7842 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7843 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7844 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7845 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7846 bp->common.flash_size, bp->common.flash_size);
7847
7848 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
f2e0899f
DK		 7849 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7850 MISC_REG_GENERIC_CR_1 :
7851 MISC_REG_GENERIC_CR_0));
34f80b04 7852 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 7853 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 7854 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7855 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 7856
f2e0899f 7857 if (!bp->common.shmem_base) {
34f80b04
EG		 7858 BNX2X_DEV_INFO("MCP not active\n");
7859 bp->flags |= NO_MCP_FLAG;
7860 return;
7861 }
7862
7863 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7864 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7865 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
f2e0899f 7866 BNX2X_ERR("BAD MCP validity signature\n");
34f80b04
EG		 7867
7868 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 7869 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 7870
7871 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7872 SHARED_HW_CFG_LED_MODE_MASK) >>
7873 SHARED_HW_CFG_LED_MODE_SHIFT);
7874
c2c8b03e
EG		 7875 bp->link_params.feature_config_flags = 0;
7876 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7877 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7878 bp->link_params.feature_config_flags |=
7879 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7880 else
7881 bp->link_params.feature_config_flags &=
7882 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7883
34f80b04
EG		 7884 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7885 bp->common.bc_ver = val;
7886 BNX2X_DEV_INFO("bc_ver %X\n", val);
7887 if (val < BNX2X_BC_VER) {
7888 /* for now only warn
7889 * later we might need to enforce this */
f2e0899f
DK		 7890 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7891 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 7892 }
4d295db0 7893 bp->link_params.feature_config_flags |=
a22f0788 7894 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 7895 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7896
a22f0788
YR		 7897 bp->link_params.feature_config_flags |=
7898 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7899 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 7900
f9a3ebbe
DK		 7901 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7902 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7903
72ce58c3 7904 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 7905 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 7906
7907 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7908 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7909 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7910 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7911
cdaa7cb8
VZ		 7912 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7913 val, val2, val3, val4);
34f80b04
EG		 7914}
7915
f2e0899f
DK		 7916#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7917#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7918
7919static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7920{
7921 int pfid = BP_FUNC(bp);
7922 int vn = BP_E1HVN(bp);
7923 int igu_sb_id;
7924 u32 val;
7925 u8 fid;
7926
7927 bp->igu_base_sb = 0xff;
7928 bp->igu_sb_cnt = 0;
7929 if (CHIP_INT_MODE_IS_BC(bp)) {
7930 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
ec6ba945 7931 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7932
7933 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7934 FP_SB_MAX_E1x;
7935
7936 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7937 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7938
7939 return;
7940 }
7941
7942 /* IGU in normal mode - read CAM */
7943 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7944 igu_sb_id++) {
7945 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7946 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7947 continue;
7948 fid = IGU_FID(val);
7949 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7950 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7951 continue;
7952 if (IGU_VEC(val) == 0)
7953 /* default status block */
7954 bp->igu_dsb_id = igu_sb_id;
7955 else {
7956 if (bp->igu_base_sb == 0xff)
7957 bp->igu_base_sb = igu_sb_id;
7958 bp->igu_sb_cnt++;
7959 }
7960 }
7961 }
ec6ba945
VZ		 7962 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
7963 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7964 if (bp->igu_sb_cnt == 0)
7965 BNX2X_ERR("CAM configuration error\n");
7966}
7967
34f80b04
EG		 7968static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7969 u32 switch_cfg)
a2fbb9ea 7970{
a22f0788
YR		 7971 int cfg_size = 0, idx, port = BP_PORT(bp);
7972
7973 /* Aggregation of supported attributes of all external phys */
7974 bp->port.supported[0] = 0;
7975 bp->port.supported[1] = 0;
b7737c9b
YR		 7976 switch (bp->link_params.num_phys) {
7977 case 1:
a22f0788
YR		 7978 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
7979 cfg_size = 1;
7980 break;
b7737c9b 7981 case 2:
a22f0788
YR		 7982 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
7983 cfg_size = 1;
7984 break;
7985 case 3:
7986 if (bp->link_params.multi_phy_config &
7987 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
7988 bp->port.supported[1] =
7989 bp->link_params.phy[EXT_PHY1].supported;
7990 bp->port.supported[0] =
7991 bp->link_params.phy[EXT_PHY2].supported;
7992 } else {
7993 bp->port.supported[0] =
7994 bp->link_params.phy[EXT_PHY1].supported;
7995 bp->port.supported[1] =
7996 bp->link_params.phy[EXT_PHY2].supported;
7997 }
7998 cfg_size = 2;
7999 break;
b7737c9b 8000 }
a2fbb9ea 8001
a22f0788 8002 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8003 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8004 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8005 SHMEM_RD(bp,
a22f0788
YR		 8006 dev_info.port_hw_config[port].external_phy_config),
8007 SHMEM_RD(bp,
8008 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8009 return;
f85582f8 8010 }
a2fbb9ea 8011
b7737c9b
YR		 8012 switch (switch_cfg) {
8013 case SWITCH_CFG_1G:
34f80b04
EG		 8014 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8015 port*0x10);
8016 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8017 break;
8018
8019 case SWITCH_CFG_10G:
34f80b04
EG		 8020 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8021 port*0x18);
8022 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8023 break;
8024
8025 default:
8026 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
a22f0788 8027 bp->port.link_config[0]);
a2fbb9ea
ET		 8028 return;
8029 }
a22f0788
YR		 8030 /* mask what we support according to speed_cap_mask per configuration */
8031 for (idx = 0; idx < cfg_size; idx++) {
8032 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8033 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8034 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8035
a22f0788 8036 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8037 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8038 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8039
a22f0788 8040 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8041 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8042 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8043
a22f0788 8044 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8045 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8046 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8047
a22f0788 8048 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8049 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8050 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8051 SUPPORTED_1000baseT_Full);
a2fbb9ea 8052
a22f0788 8053 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8054 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8055 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8056
a22f0788 8057 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8058 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8059 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8060
8061 }
a2fbb9ea 8062
a22f0788
YR		 8063 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8064 bp->port.supported[1]);
a2fbb9ea
ET		 8065}
8066
34f80b04 8067static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8068{
a22f0788
YR		 8069 u32 link_config, idx, cfg_size = 0;
8070 bp->port.advertising[0] = 0;
8071 bp->port.advertising[1] = 0;
8072 switch (bp->link_params.num_phys) {
8073 case 1:
8074 case 2:
8075 cfg_size = 1;
8076 break;
8077 case 3:
8078 cfg_size = 2;
8079 break;
8080 }
8081 for (idx = 0; idx < cfg_size; idx++) {
8082 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8083 link_config = bp->port.link_config[idx];
8084 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8085 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8086 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8087 bp->link_params.req_line_speed[idx] =
8088 SPEED_AUTO_NEG;
8089 bp->port.advertising[idx] |=
8090 bp->port.supported[idx];
f85582f8
DK		 8091 } else {
8092 /* force 10G, no AN */
a22f0788
YR		 8093 bp->link_params.req_line_speed[idx] =
8094 SPEED_10000;
8095 bp->port.advertising[idx] |=
8096 (ADVERTISED_10000baseT_Full |
f85582f8 8097 ADVERTISED_FIBRE);
a22f0788 8098 continue;
f85582f8
DK		 8099 }
8100 break;
a2fbb9ea 8101
f85582f8 8102 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8103 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8104 bp->link_params.req_line_speed[idx] =
8105 SPEED_10;
8106 bp->port.advertising[idx] |=
8107 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8108 ADVERTISED_TP);
8109 } else {
8110 BNX2X_ERROR("NVRAM config error. "
8111 "Invalid link_config 0x%x"
8112 " speed_cap_mask 0x%x\n",
8113 link_config,
a22f0788 8114 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8115 return;
8116 }
8117 break;
a2fbb9ea 8118
f85582f8 8119 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8120 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8121 bp->link_params.req_line_speed[idx] =
8122 SPEED_10;
8123 bp->link_params.req_duplex[idx] =
8124 DUPLEX_HALF;
8125 bp->port.advertising[idx] |=
8126 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8127 ADVERTISED_TP);
8128 } else {
8129 BNX2X_ERROR("NVRAM config error. "
8130 "Invalid link_config 0x%x"
8131 " speed_cap_mask 0x%x\n",
8132 link_config,
8133 bp->link_params.speed_cap_mask[idx]);
8134 return;
8135 }
8136 break;
a2fbb9ea 8137
f85582f8
DK		 8138 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8139 if (bp->port.supported[idx] &
8140 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8141 bp->link_params.req_line_speed[idx] =
8142 SPEED_100;
8143 bp->port.advertising[idx] |=
8144 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8145 ADVERTISED_TP);
8146 } else {
8147 BNX2X_ERROR("NVRAM config error. "
8148 "Invalid link_config 0x%x"
8149 " speed_cap_mask 0x%x\n",
8150 link_config,
8151 bp->link_params.speed_cap_mask[idx]);
8152 return;
8153 }
8154 break;
a2fbb9ea 8155
f85582f8
DK		 8156 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8157 if (bp->port.supported[idx] &
8158 SUPPORTED_100baseT_Half) {
8159 bp->link_params.req_line_speed[idx] =
8160 SPEED_100;
8161 bp->link_params.req_duplex[idx] =
8162 DUPLEX_HALF;
a22f0788
YR		 8163 bp->port.advertising[idx] |=
8164 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8165 ADVERTISED_TP);
8166 } else {
8167 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8168 "Invalid link_config 0x%x"
8169 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8170 link_config,
8171 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8172 return;
8173 }
8174 break;
a2fbb9ea 8175
f85582f8 8176 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 8177 if (bp->port.supported[idx] &
8178 SUPPORTED_1000baseT_Full) {
8179 bp->link_params.req_line_speed[idx] =
8180 SPEED_1000;
8181 bp->port.advertising[idx] |=
8182 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 8183 ADVERTISED_TP);
8184 } else {
8185 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8186 "Invalid link_config 0x%x"
8187 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8188 link_config,
8189 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8190 return;
8191 }
8192 break;
a2fbb9ea 8193
f85582f8 8194 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 8195 if (bp->port.supported[idx] &
8196 SUPPORTED_2500baseX_Full) {
8197 bp->link_params.req_line_speed[idx] =
8198 SPEED_2500;
8199 bp->port.advertising[idx] |=
8200 (ADVERTISED_2500baseX_Full |
34f80b04 8201 ADVERTISED_TP);
f85582f8
DK		 8202 } else {
8203 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8204 "Invalid link_config 0x%x"
8205 " speed_cap_mask 0x%x\n",
a22f0788 8206 link_config,
f85582f8
DK		 8207 bp->link_params.speed_cap_mask[idx]);
8208 return;
8209 }
8210 break;
a2fbb9ea 8211
f85582f8
DK		 8212 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8213 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8214 case PORT_FEATURE_LINK_SPEED_10G_KR:
a22f0788
YR		 8215 if (bp->port.supported[idx] &
8216 SUPPORTED_10000baseT_Full) {
8217 bp->link_params.req_line_speed[idx] =
8218 SPEED_10000;
8219 bp->port.advertising[idx] |=
8220 (ADVERTISED_10000baseT_Full |
34f80b04 8221 ADVERTISED_FIBRE);
f85582f8
DK		 8222 } else {
8223 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8224 "Invalid link_config 0x%x"
8225 " speed_cap_mask 0x%x\n",
a22f0788 8226 link_config,
f85582f8
DK		 8227 bp->link_params.speed_cap_mask[idx]);
8228 return;
8229 }
8230 break;
a2fbb9ea 8231
f85582f8
DK		 8232 default:
8233 BNX2X_ERROR("NVRAM config error. "
8234 "BAD link speed link_config 0x%x\n",
8235 link_config);
8236 bp->link_params.req_line_speed[idx] =
8237 SPEED_AUTO_NEG;
8238 bp->port.advertising[idx] =
8239 bp->port.supported[idx];
8240 break;
8241 }
a2fbb9ea 8242
a22f0788 8243 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 8244 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 8245 if ((bp->link_params.req_flow_ctrl[idx] ==
8246 BNX2X_FLOW_CTRL_AUTO) &&
8247 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8248 bp->link_params.req_flow_ctrl[idx] =
8249 BNX2X_FLOW_CTRL_NONE;
8250 }
a2fbb9ea 8251
a22f0788
YR		 8252 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8253 " 0x%x advertising 0x%x\n",
8254 bp->link_params.req_line_speed[idx],
8255 bp->link_params.req_duplex[idx],
8256 bp->link_params.req_flow_ctrl[idx],
8257 bp->port.advertising[idx]);
8258 }
a2fbb9ea
ET		 8259}
8260
e665bfda
MC		 8261static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8262{
8263 mac_hi = cpu_to_be16(mac_hi);
8264 mac_lo = cpu_to_be32(mac_lo);
8265 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8266 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8267}
8268
34f80b04 8269static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 8270{
34f80b04 8271 int port = BP_PORT(bp);
589abe3a 8272 u32 config;
6f38ad93 8273 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 8274
c18487ee 8275 bp->link_params.bp = bp;
34f80b04 8276 bp->link_params.port = port;
c18487ee 8277
c18487ee 8278 bp->link_params.lane_config =
a2fbb9ea 8279 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 8280
a22f0788 8281 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 8282 SHMEM_RD(bp,
8283 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 8284 bp->link_params.speed_cap_mask[1] =
8285 SHMEM_RD(bp,
8286 dev_info.port_hw_config[port].speed_capability_mask2);
8287 bp->port.link_config[0] =
a2fbb9ea
ET		 8288 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8289
a22f0788
YR		 8290 bp->port.link_config[1] =
8291 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 8292
a22f0788
YR		 8293 bp->link_params.multi_phy_config =
8294 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 8295 /* If the device is capable of WoL, set the default state according
8296 * to the HW
8297 */
4d295db0 8298 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 8299 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8300 (config & PORT_FEATURE_WOL_ENABLED));
8301
f85582f8 8302 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 8303 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 8304 bp->link_params.lane_config,
a22f0788
YR		 8305 bp->link_params.speed_cap_mask[0],
8306 bp->port.link_config[0]);
a2fbb9ea 8307
a22f0788 8308 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 8309 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 8310 bnx2x_phy_probe(&bp->link_params);
c18487ee 8311 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 8312
8313 bnx2x_link_settings_requested(bp);
8314
01cd4528
EG		 8315 /*
8316 * If connected directly, work with the internal PHY, otherwise, work
8317 * with the external PHY
8318 */
b7737c9b
YR		 8319 ext_phy_config =
8320 SHMEM_RD(bp,
8321 dev_info.port_hw_config[port].external_phy_config);
8322 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 8323 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 8324 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 8325
8326 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8327 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8328 bp->mdio.prtad =
b7737c9b 8329 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 8330
8331 /*
8332 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8333 * In MF mode, it is set to cover self test cases
8334 */
8335 if (IS_MF(bp))
8336 bp->port.need_hw_lock = 1;
8337 else
8338 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8339 bp->common.shmem_base,
8340 bp->common.shmem2_base);
0793f83f 8341}
01cd4528 8342
2ba45142
VZ		 8343#ifdef BCM_CNIC
8344static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8345{
8346 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8347 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8348 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8349 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8350
8351 /* Get the number of maximum allowed iSCSI and FCoE connections */
8352 bp->cnic_eth_dev.max_iscsi_conn =
8353 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8354 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8355
8356 bp->cnic_eth_dev.max_fcoe_conn =
8357 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8358 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8359
8360 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8361 bp->cnic_eth_dev.max_iscsi_conn,
8362 bp->cnic_eth_dev.max_fcoe_conn);
8363
8364 /* If mamimum allowed number of connections is zero -
8365 * disable the feature.
8366 */
8367 if (!bp->cnic_eth_dev.max_iscsi_conn)
8368 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8369
8370 if (!bp->cnic_eth_dev.max_fcoe_conn)
8371 bp->flags |= NO_FCOE_FLAG;
8372}
8373#endif
8374
0793f83f
DK		 8375static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8376{
8377 u32 val, val2;
8378 int func = BP_ABS_FUNC(bp);
8379 int port = BP_PORT(bp);
2ba45142
VZ		 8380#ifdef BCM_CNIC
8381 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8382 u8 *fip_mac = bp->fip_mac;
8383#endif
0793f83f
DK		 8384
8385 if (BP_NOMCP(bp)) {
8386 BNX2X_ERROR("warning: random MAC workaround active\n");
8387 random_ether_addr(bp->dev->dev_addr);
8388 } else if (IS_MF(bp)) {
8389 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8390 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8391 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8392 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8393 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 8394
8395#ifdef BCM_CNIC
2ba45142
VZ		 8396 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8397 * FCoE MAC then the appropriate feature should be disabled.
8398 */
0793f83f
DK		 8399 if (IS_MF_SI(bp)) {
8400 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8401 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8402 val2 = MF_CFG_RD(bp, func_ext_config[func].
8403 iscsi_mac_addr_upper);
8404 val = MF_CFG_RD(bp, func_ext_config[func].
8405 iscsi_mac_addr_lower);
2ba45142
VZ		 8406 BNX2X_DEV_INFO("Read iSCSI MAC: "
8407 "0x%x:0x%04x\n", val2, val);
8408 bnx2x_set_mac_buf(iscsi_mac, val, val2);
2ba45142
VZ		 8409 } else
8410 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8411
8412 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8413 val2 = MF_CFG_RD(bp, func_ext_config[func].
8414 fcoe_mac_addr_upper);
8415 val = MF_CFG_RD(bp, func_ext_config[func].
8416 fcoe_mac_addr_lower);
8417 BNX2X_DEV_INFO("Read FCoE MAC to "
8418 "0x%x:0x%04x\n", val2, val);
8419 bnx2x_set_mac_buf(fip_mac, val, val2);
8420
2ba45142
VZ		 8421 } else
8422 bp->flags |= NO_FCOE_FLAG;
0793f83f 8423 }
37b091ba 8424#endif
0793f83f
DK		 8425 } else {
8426 /* in SF read MACs from port configuration */
8427 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8428 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8429 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8430
8431#ifdef BCM_CNIC
8432 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8433 iscsi_mac_upper);
8434 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8435 iscsi_mac_lower);
2ba45142 8436 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0793f83f
DK		 8437#endif
8438 }
8439
8440 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8441 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8442
ec6ba945 8443#ifdef BCM_CNIC
2ba45142 8444 /* Set the FCoE MAC in modes other then MF_SI */
ec6ba945
VZ		 8445 if (!CHIP_IS_E1x(bp)) {
8446 if (IS_MF_SD(bp))
2ba45142
VZ		 8447 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8448 else if (!IS_MF(bp))
8449 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
ec6ba945 8450 }
426b9241
DK		 8451
8452 /* Disable iSCSI if MAC configuration is
8453 * invalid.
8454 */
8455 if (!is_valid_ether_addr(iscsi_mac)) {
8456 bp->flags |= NO_ISCSI_FLAG;
8457 memset(iscsi_mac, 0, ETH_ALEN);
8458 }
8459
8460 /* Disable FCoE if MAC configuration is
8461 * invalid.
8462 */
8463 if (!is_valid_ether_addr(fip_mac)) {
8464 bp->flags |= NO_FCOE_FLAG;
8465 memset(bp->fip_mac, 0, ETH_ALEN);
8466 }
ec6ba945 8467#endif
34f80b04
EG		 8468}
8469
8470static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8471{
0793f83f 8472 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 8473 int vn;
0793f83f 8474 u32 val = 0;
34f80b04 8475 int rc = 0;
a2fbb9ea 8476
34f80b04 8477 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 8478
f2e0899f
DK		 8479 if (CHIP_IS_E1x(bp)) {
8480 bp->common.int_block = INT_BLOCK_HC;
8481
8482 bp->igu_dsb_id = DEF_SB_IGU_ID;
8483 bp->igu_base_sb = 0;
ec6ba945
VZ		 8484 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8485 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8486 } else {
8487 bp->common.int_block = INT_BLOCK_IGU;
8488 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8489 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8490 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8491 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8492 } else
8493 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
523224a3 8494
f2e0899f
DK		 8495 bnx2x_get_igu_cam_info(bp);
8496
8497 }
8498 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8499 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8500
8501 /*
8502 * Initialize MF configuration
8503 */
523224a3 8504
fb3bff17
DK		 8505 bp->mf_ov = 0;
8506 bp->mf_mode = 0;
f2e0899f 8507 vn = BP_E1HVN(bp);
0793f83f 8508
f2e0899f 8509 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
0793f83f
DK		 8510 DP(NETIF_MSG_PROBE,
8511 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8512 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8513 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
f2e0899f
DK		 8514 if (SHMEM2_HAS(bp, mf_cfg_addr))
8515 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8516 else
8517 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 8518 offsetof(struct shmem_region, func_mb) +
8519 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 8520 /*
8521 * get mf configuration:
25985edc 8522 * 1. existence of MF configuration
0793f83f
DK		 8523 * 2. MAC address must be legal (check only upper bytes)
8524 * for Switch-Independent mode;
8525 * OVLAN must be legal for Switch-Dependent mode
8526 * 3. SF_MODE configures specific MF mode
8527 */
8528 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8529 /* get mf configuration */
8530 val = SHMEM_RD(bp,
8531 dev_info.shared_feature_config.config);
8532 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8533
8534 switch (val) {
8535 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8536 val = MF_CFG_RD(bp, func_mf_config[func].
8537 mac_upper);
8538 /* check for legal mac (upper bytes)*/
8539 if (val != 0xffff) {
8540 bp->mf_mode = MULTI_FUNCTION_SI;
8541 bp->mf_config[vn] = MF_CFG_RD(bp,
8542 func_mf_config[func].config);
8543 } else
8544 DP(NETIF_MSG_PROBE, "illegal MAC "
8545 "address for SI\n");
8546 break;
8547 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8548 /* get OV configuration */
8549 val = MF_CFG_RD(bp,
8550 func_mf_config[FUNC_0].e1hov_tag);
8551 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8552
8553 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8554 bp->mf_mode = MULTI_FUNCTION_SD;
8555 bp->mf_config[vn] = MF_CFG_RD(bp,
8556 func_mf_config[func].config);
8557 } else
8558 DP(NETIF_MSG_PROBE, "illegal OV for "
8559 "SD\n");
8560 break;
8561 default:
8562 /* Unknown configuration: reset mf_config */
8563 bp->mf_config[vn] = 0;
25985edc 8564 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
0793f83f
DK		 8565 val);
8566 }
8567 }
a2fbb9ea 8568
2691d51d 8569 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 8570 IS_MF(bp) ? "multi" : "single");
2691d51d 8571
0793f83f
DK		 8572 switch (bp->mf_mode) {
8573 case MULTI_FUNCTION_SD:
8574 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8575 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 8576 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 8577 bp->mf_ov = val;
0793f83f
DK		 8578 BNX2X_DEV_INFO("MF OV for func %d is %d"
8579 " (0x%04x)\n", func,
8580 bp->mf_ov, bp->mf_ov);
2691d51d 8581 } else {
0793f83f
DK		 8582 BNX2X_ERR("No valid MF OV for func %d,"
8583 " aborting\n", func);
34f80b04
EG		 8584 rc = -EPERM;
8585 }
0793f83f
DK		 8586 break;
8587 case MULTI_FUNCTION_SI:
8588 BNX2X_DEV_INFO("func %d is in MF "
8589 "switch-independent mode\n", func);
8590 break;
8591 default:
8592 if (vn) {
8593 BNX2X_ERR("VN %d in single function mode,"
8594 " aborting\n", vn);
2691d51d
EG		 8595 rc = -EPERM;
8596 }
0793f83f 8597 break;
34f80b04 8598 }
0793f83f 8599
34f80b04 8600 }
a2fbb9ea 8601
f2e0899f
DK		 8602 /* adjust igu_sb_cnt to MF for E1x */
8603 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 8604 bp->igu_sb_cnt /= E1HVN_MAX;
8605
f2e0899f
DK		 8606 /*
8607 * adjust E2 sb count: to be removed when FW will support
8608 * more then 16 L2 clients
8609 */
8610#define MAX_L2_CLIENTS 16
8611 if (CHIP_IS_E2(bp))
8612 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8613 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8614
34f80b04
EG		 8615 if (!BP_NOMCP(bp)) {
8616 bnx2x_get_port_hwinfo(bp);
8617
f2e0899f
DK		 8618 bp->fw_seq =
8619 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8620 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 8621 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8622 }
8623
0793f83f
DK		 8624 /* Get MAC addresses */
8625 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 8626
2ba45142
VZ		 8627#ifdef BCM_CNIC
8628 bnx2x_get_cnic_info(bp);
8629#endif
8630
34f80b04
EG		 8631 return rc;
8632}
8633
34f24c7f
VZ		 8634static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8635{
8636 int cnt, i, block_end, rodi;
8637 char vpd_data[BNX2X_VPD_LEN+1];
8638 char str_id_reg[VENDOR_ID_LEN+1];
8639 char str_id_cap[VENDOR_ID_LEN+1];
8640 u8 len;
8641
8642 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8643 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8644
8645 if (cnt < BNX2X_VPD_LEN)
8646 goto out_not_found;
8647
8648 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8649 PCI_VPD_LRDT_RO_DATA);
8650 if (i < 0)
8651 goto out_not_found;
8652
8653
8654 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8655 pci_vpd_lrdt_size(&vpd_data[i]);
8656
8657 i += PCI_VPD_LRDT_TAG_SIZE;
8658
8659 if (block_end > BNX2X_VPD_LEN)
8660 goto out_not_found;
8661
8662 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8663 PCI_VPD_RO_KEYWORD_MFR_ID);
8664 if (rodi < 0)
8665 goto out_not_found;
8666
8667 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8668
8669 if (len != VENDOR_ID_LEN)
8670 goto out_not_found;
8671
8672 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8673
8674 /* vendor specific info */
8675 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8676 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8677 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8678 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8679
8680 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8681 PCI_VPD_RO_KEYWORD_VENDOR0);
8682 if (rodi >= 0) {
8683 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8684
8685 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8686
8687 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8688 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8689 bp->fw_ver[len] = ' ';
8690 }
8691 }
8692 return;
8693 }
8694out_not_found:
8695 return;
8696}
8697
34f80b04
EG		 8698static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8699{
f2e0899f 8700 int func;
87942b46 8701 int timer_interval;
34f80b04
EG		 8702 int rc;
8703
da5a662a
VZ		 8704 /* Disable interrupt handling until HW is initialized */
8705 atomic_set(&bp->intr_sem, 1);
e1510706 8706 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
da5a662a 8707
34f80b04 8708 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 8709 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 8710 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 8711#ifdef BCM_CNIC
8712 mutex_init(&bp->cnic_mutex);
8713#endif
a2fbb9ea 8714
1cf167f2 8715 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
72fd0718 8716 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
34f80b04
EG		 8717
8718 rc = bnx2x_get_hwinfo(bp);
8719
523224a3
DK		 8720 if (!rc)
8721 rc = bnx2x_alloc_mem_bp(bp);
8722
34f24c7f 8723 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 8724
8725 func = BP_FUNC(bp);
8726
34f80b04
EG		 8727 /* need to reset chip if undi was active */
8728 if (!BP_NOMCP(bp))
8729 bnx2x_undi_unload(bp);
8730
8731 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 8732 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 8733
8734 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 8735 dev_err(&bp->pdev->dev, "MCP disabled, "
8736 "must load devices in order!\n");
34f80b04 8737
555f6c78 8738 bp->multi_mode = multi_mode;
5d7cd496 8739 bp->int_mode = int_mode;
555f6c78 8740
7a9b2557
VZ		 8741 /* Set TPA flags */
8742 if (disable_tpa) {
8743 bp->flags &= ~TPA_ENABLE_FLAG;
8744 bp->dev->features &= ~NETIF_F_LRO;
8745 } else {
8746 bp->flags |= TPA_ENABLE_FLAG;
8747 bp->dev->features |= NETIF_F_LRO;
8748 }
5d7cd496 8749 bp->disable_tpa = disable_tpa;
7a9b2557 8750
a18f5128
EG		 8751 if (CHIP_IS_E1(bp))
8752 bp->dropless_fc = 0;
8753 else
8754 bp->dropless_fc = dropless_fc;
8755
8d5726c4 8756 bp->mrrs = mrrs;
7a9b2557 8757
34f80b04 8758 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 8759
7d323bfd 8760 /* make sure that the numbers are in the right granularity */
523224a3
DK		 8761 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8762 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 8763
87942b46
EG		 8764 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8765 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 8766
8767 init_timer(&bp->timer);
8768 bp->timer.expires = jiffies + bp->current_interval;
8769 bp->timer.data = (unsigned long) bp;
8770 bp->timer.function = bnx2x_timer;
8771
785b9b1a 8772 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 8773 bnx2x_dcbx_init_params(bp);
8774
34f80b04 8775 return rc;
a2fbb9ea
ET		 8776}
8777
a2fbb9ea 8778
de0c62db
DK		 8779/****************************************************************************
8780* General service functions
8781****************************************************************************/
a2fbb9ea 8782
bb2a0f7a 8783/* called with rtnl_lock */
a2fbb9ea
ET		 8784static int bnx2x_open(struct net_device *dev)
8785{
8786 struct bnx2x *bp = netdev_priv(dev);
8787
6eccabb3
EG		 8788 netif_carrier_off(dev);
8789
a2fbb9ea
ET		 8790 bnx2x_set_power_state(bp, PCI_D0);
8791
72fd0718
VZ		 8792 if (!bnx2x_reset_is_done(bp)) {
8793 do {
8794 /* Reset MCP mail box sequence if there is on going
8795 * recovery
8796 */
8797 bp->fw_seq = 0;
8798
8799 /* If it's the first function to load and reset done
8800 * is still not cleared it may mean that. We don't
8801 * check the attention state here because it may have
8802 * already been cleared by a "common" reset but we
8803 * shell proceed with "process kill" anyway.
8804 */
8805 if ((bnx2x_get_load_cnt(bp) == 0) &&
8806 bnx2x_trylock_hw_lock(bp,
8807 HW_LOCK_RESOURCE_RESERVED_08) &&
8808 (!bnx2x_leader_reset(bp))) {
8809 DP(NETIF_MSG_HW, "Recovered in open\n");
8810 break;
8811 }
8812
8813 bnx2x_set_power_state(bp, PCI_D3hot);
8814
8815 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8816 " completed yet. Try again later. If u still see this"
8817 " message after a few retries then power cycle is"
8818 " required.\n", bp->dev->name);
8819
8820 return -EAGAIN;
8821 } while (0);
8822 }
8823
8824 bp->recovery_state = BNX2X_RECOVERY_DONE;
8825
bb2a0f7a 8826 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 8827}
8828
bb2a0f7a 8829/* called with rtnl_lock */
a2fbb9ea
ET		 8830static int bnx2x_close(struct net_device *dev)
8831{
a2fbb9ea
ET		 8832 struct bnx2x *bp = netdev_priv(dev);
8833
8834 /* Unload the driver, release IRQs */
bb2a0f7a 8835 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
d3dbfee0 8836 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 8837
8838 return 0;
8839}
8840
6e30dd4e
VZ		 8841#define E1_MAX_UC_LIST 29
8842#define E1H_MAX_UC_LIST 30
8843#define E2_MAX_UC_LIST 14
8844static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)
8845{
8846 if (CHIP_IS_E1(bp))
8847 return E1_MAX_UC_LIST;
8848 else if (CHIP_IS_E1H(bp))
8849 return E1H_MAX_UC_LIST;
8850 else
8851 return E2_MAX_UC_LIST;
8852}
8853
8854
8855static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)
8856{
8857 if (CHIP_IS_E1(bp))
8858 /* CAM Entries for Port0:
8859 * 0 - prim ETH MAC
8860 * 1 - BCAST MAC
8861 * 2 - iSCSI L2 ring ETH MAC
8862 * 3-31 - UC MACs
8863 *
8864 * Port1 entries are allocated the same way starting from
8865 * entry 32.
8866 */
8867 return 3 + 32 * BP_PORT(bp);
8868 else if (CHIP_IS_E1H(bp)) {
8869 /* CAM Entries:
8870 * 0-7 - prim ETH MAC for each function
8871 * 8-15 - iSCSI L2 ring ETH MAC for each function
8872 * 16 till 255 UC MAC lists for each function
8873 *
8874 * Remark: There is no FCoE support for E1H, thus FCoE related
8875 * MACs are not considered.
8876 */
8877 return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +
8878 bnx2x_max_uc_list(bp) * BP_FUNC(bp);
8879 } else {
8880 /* CAM Entries (there is a separate CAM per engine):
8881 * 0-4 - prim ETH MAC for each function
8882 * 4-7 - iSCSI L2 ring ETH MAC for each function
8883 * 8-11 - FIP ucast L2 MAC for each function
8884 * 12-15 - ALL_ENODE_MACS mcast MAC for each function
8885 * 16 till 71 UC MAC lists for each function
8886 */
8887 u8 func_idx =
8888 (CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));
8889
8890 return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +
8891 bnx2x_max_uc_list(bp) * func_idx;
8892 }
8893}
8894
8895/* set uc list, do not wait as wait implies sleep and
8896 * set_rx_mode can be invoked from non-sleepable context.
8897 *
8898 * Instead we use the same ramrod data buffer each time we need
8899 * to configure a list of addresses, and use the fact that the
8900 * list of MACs is changed in an incremental way and that the
8901 * function is called under the netif_addr_lock. A temporary
8902 * inconsistent CAM configuration (possible in case of very fast
8903 * sequence of add/del/add on the host side) will shortly be
8904 * restored by the handler of the last ramrod.
8905 */
8906static int bnx2x_set_uc_list(struct bnx2x *bp)
8907{
8908 int i = 0, old;
8909 struct net_device *dev = bp->dev;
8910 u8 offset = bnx2x_uc_list_cam_offset(bp);
8911 struct netdev_hw_addr *ha;
8912 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8913 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8914
8915 if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))
8916 return -EINVAL;
8917
8918 netdev_for_each_uc_addr(ha, dev) {
8919 /* copy mac */
8920 config_cmd->config_table[i].msb_mac_addr =
8921 swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);
8922 config_cmd->config_table[i].middle_mac_addr =
8923 swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);
8924 config_cmd->config_table[i].lsb_mac_addr =
8925 swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);
8926
8927 config_cmd->config_table[i].vlan_id = 0;
8928 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
8929 config_cmd->config_table[i].clients_bit_vector =
8930 cpu_to_le32(1 << BP_L_ID(bp));
8931
8932 SET_FLAG(config_cmd->config_table[i].flags,
8933 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8934 T_ETH_MAC_COMMAND_SET);
8935
8936 DP(NETIF_MSG_IFUP,
8937 "setting UCAST[%d] (%04x:%04x:%04x)\n", i,
8938 config_cmd->config_table[i].msb_mac_addr,
8939 config_cmd->config_table[i].middle_mac_addr,
8940 config_cmd->config_table[i].lsb_mac_addr);
8941
8942 i++;
8943
8944 /* Set uc MAC in NIG */
8945 bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),
8946 LLH_CAM_ETH_LINE + i);
8947 }
8948 old = config_cmd->hdr.length;
8949 if (old > i) {
8950 for (; i < old; i++) {
8951 if (CAM_IS_INVALID(config_cmd->
8952 config_table[i])) {
8953 /* already invalidated */
8954 break;
8955 }
8956 /* invalidate */
8957 SET_FLAG(config_cmd->config_table[i].flags,
8958 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8959 T_ETH_MAC_COMMAND_INVALIDATE);
8960 }
8961 }
8962
8963 wmb();
8964
8965 config_cmd->hdr.length = i;
8966 config_cmd->hdr.offset = offset;
8967 config_cmd->hdr.client_id = 0xff;
8968 /* Mark that this ramrod doesn't use bp->set_mac_pending for
8969 * synchronization.
8970 */
8971 config_cmd->hdr.echo = 0;
8972
8973 mb();
8974
8975 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8976 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8977
8978}
8979
8980void bnx2x_invalidate_uc_list(struct bnx2x *bp)
8981{
8982 int i;
8983 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8984 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8985 int ramrod_flags = WAIT_RAMROD_COMMON;
8986 u8 offset = bnx2x_uc_list_cam_offset(bp);
8987 u8 max_list_size = bnx2x_max_uc_list(bp);
8988
8989 for (i = 0; i < max_list_size; i++) {
8990 SET_FLAG(config_cmd->config_table[i].flags,
8991 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8992 T_ETH_MAC_COMMAND_INVALIDATE);
8993 bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);
8994 }
8995
8996 wmb();
8997
8998 config_cmd->hdr.length = max_list_size;
8999 config_cmd->hdr.offset = offset;
9000 config_cmd->hdr.client_id = 0xff;
9001 /* We'll wait for a completion this time... */
9002 config_cmd->hdr.echo = 1;
9003
9004 bp->set_mac_pending = 1;
9005
9006 mb();
9007
9008 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
9009 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
9010
9011 /* Wait for a completion */
9012 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
9013 ramrod_flags);
9014
9015}
9016
9017static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9018{
9019 /* some multicasts */
9020 if (CHIP_IS_E1(bp)) {
9021 return bnx2x_set_e1_mc_list(bp);
9022 } else { /* E1H and newer */
9023 return bnx2x_set_e1h_mc_list(bp);
9024 }
9025}
9026
f5372251 9027/* called with netif_tx_lock from dev_mcast.c */
9f6c9258 9028void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 9029{
9030 struct bnx2x *bp = netdev_priv(dev);
9031 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 9032
9033 if (bp->state != BNX2X_STATE_OPEN) {
9034 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9035 return;
9036 }
9037
9038 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9039
9040 if (dev->flags & IFF_PROMISC)
9041 rx_mode = BNX2X_RX_MODE_PROMISC;
6e30dd4e 9042 else if (dev->flags & IFF_ALLMULTI)
34f80b04 9043 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 9044 else {
9045 /* some multicasts */
9046 if (bnx2x_set_mc_list(bp))
9047 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 9048
6e30dd4e
VZ		 9049 /* some unicasts */
9050 if (bnx2x_set_uc_list(bp))
9051 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 9052 }
9053
9054 bp->rx_mode = rx_mode;
9055 bnx2x_set_storm_rx_mode(bp);
9056}
9057
c18487ee 9058/* called with rtnl_lock */
01cd4528
EG		 9059static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9060 int devad, u16 addr)
a2fbb9ea 9061{
01cd4528
EG		 9062 struct bnx2x *bp = netdev_priv(netdev);
9063 u16 value;
9064 int rc;
a2fbb9ea 9065
01cd4528
EG		 9066 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9067 prtad, devad, addr);
a2fbb9ea 9068
01cd4528
EG		 9069 /* The HW expects different devad if CL22 is used */
9070 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 9071
01cd4528 9072 bnx2x_acquire_phy_lock(bp);
e10bc84d 9073 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 9074 bnx2x_release_phy_lock(bp);
9075 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 9076
01cd4528
EG		 9077 if (!rc)
9078 rc = value;
9079 return rc;
9080}
a2fbb9ea 9081
01cd4528
EG		 9082/* called with rtnl_lock */
9083static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9084 u16 addr, u16 value)
9085{
9086 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 9087 int rc;
9088
9089 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9090 " value 0x%x\n", prtad, devad, addr, value);
9091
01cd4528
EG		 9092 /* The HW expects different devad if CL22 is used */
9093 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 9094
01cd4528 9095 bnx2x_acquire_phy_lock(bp);
e10bc84d 9096 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 9097 bnx2x_release_phy_lock(bp);
9098 return rc;
9099}
c18487ee 9100
01cd4528
EG		 9101/* called with rtnl_lock */
9102static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9103{
9104 struct bnx2x *bp = netdev_priv(dev);
9105 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 9106
01cd4528
EG		 9107 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9108 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 9109
01cd4528
EG		 9110 if (!netif_running(dev))
9111 return -EAGAIN;
9112
9113 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 9114}
9115
257ddbda 9116#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 9117static void poll_bnx2x(struct net_device *dev)
9118{
9119 struct bnx2x *bp = netdev_priv(dev);
9120
9121 disable_irq(bp->pdev->irq);
9122 bnx2x_interrupt(bp->pdev->irq, dev);
9123 enable_irq(bp->pdev->irq);
9124}
9125#endif
9126
c64213cd
SH		 9127static const struct net_device_ops bnx2x_netdev_ops = {
9128 .ndo_open = bnx2x_open,
9129 .ndo_stop = bnx2x_close,
9130 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 9131 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 9132 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 9133 .ndo_set_mac_address = bnx2x_change_mac_addr,
9134 .ndo_validate_addr = eth_validate_addr,
9135 .ndo_do_ioctl = bnx2x_ioctl,
9136 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 9137 .ndo_fix_features = bnx2x_fix_features,
9138 .ndo_set_features = bnx2x_set_features,
c64213cd 9139 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 9140#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 9141 .ndo_poll_controller = poll_bnx2x,
9142#endif
9143};
9144
34f80b04
EG		 9145static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9146 struct net_device *dev)
a2fbb9ea
ET		 9147{
9148 struct bnx2x *bp;
9149 int rc;
9150
9151 SET_NETDEV_DEV(dev, &pdev->dev);
9152 bp = netdev_priv(dev);
9153
34f80b04
EG		 9154 bp->dev = dev;
9155 bp->pdev = pdev;
a2fbb9ea 9156 bp->flags = 0;
f2e0899f 9157 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 9158
9159 rc = pci_enable_device(pdev);
9160 if (rc) {
cdaa7cb8
VZ		 9161 dev_err(&bp->pdev->dev,
9162 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 9163 goto err_out;
9164 }
9165
9166 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9167 dev_err(&bp->pdev->dev,
9168 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 9169 rc = -ENODEV;
9170 goto err_out_disable;
9171 }
9172
9173 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9174 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9175 " base address, aborting\n");
a2fbb9ea
ET		 9176 rc = -ENODEV;
9177 goto err_out_disable;
9178 }
9179
34f80b04
EG		 9180 if (atomic_read(&pdev->enable_cnt) == 1) {
9181 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9182 if (rc) {
cdaa7cb8
VZ		 9183 dev_err(&bp->pdev->dev,
9184 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 9185 goto err_out_disable;
9186 }
a2fbb9ea 9187
34f80b04
EG		 9188 pci_set_master(pdev);
9189 pci_save_state(pdev);
9190 }
a2fbb9ea
ET		 9191
9192 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9193 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 9194 dev_err(&bp->pdev->dev,
9195 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 9196 rc = -EIO;
9197 goto err_out_release;
9198 }
9199
9200 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9201 if (bp->pcie_cap == 0) {
cdaa7cb8
VZ		 9202 dev_err(&bp->pdev->dev,
9203 "Cannot find PCI Express capability, aborting\n");
a2fbb9ea
ET		 9204 rc = -EIO;
9205 goto err_out_release;
9206 }
9207
1a983142 9208 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
a2fbb9ea 9209 bp->flags |= USING_DAC_FLAG;
1a983142 9210 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
cdaa7cb8
VZ		 9211 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9212 " failed, aborting\n");
a2fbb9ea
ET		 9213 rc = -EIO;
9214 goto err_out_release;
9215 }
9216
1a983142 9217 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
cdaa7cb8
VZ		 9218 dev_err(&bp->pdev->dev,
9219 "System does not support DMA, aborting\n");
a2fbb9ea
ET		 9220 rc = -EIO;
9221 goto err_out_release;
9222 }
9223
34f80b04
EG		 9224 dev->mem_start = pci_resource_start(pdev, 0);
9225 dev->base_addr = dev->mem_start;
9226 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 9227
9228 dev->irq = pdev->irq;
9229
275f165f 9230 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 9231 if (!bp->regview) {
cdaa7cb8
VZ		 9232 dev_err(&bp->pdev->dev,
9233 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 9234 rc = -ENOMEM;
9235 goto err_out_release;
9236 }
9237
34f80b04 9238 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
523224a3 9239 min_t(u64, BNX2X_DB_SIZE(bp),
34f80b04 9240 pci_resource_len(pdev, 2)));
a2fbb9ea 9241 if (!bp->doorbells) {
cdaa7cb8
VZ		 9242 dev_err(&bp->pdev->dev,
9243 "Cannot map doorbell space, aborting\n");
a2fbb9ea
ET		 9244 rc = -ENOMEM;
9245 goto err_out_unmap;
9246 }
9247
9248 bnx2x_set_power_state(bp, PCI_D0);
9249
34f80b04
EG		 9250 /* clean indirect addresses */
9251 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9252 PCICFG_VENDOR_ID_OFFSET);
9253 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9254 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9255 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9256 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 9257
72fd0718
VZ		 9258 /* Reset the load counter */
9259 bnx2x_clear_load_cnt(bp);
9260
34f80b04 9261 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 9262
c64213cd 9263 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 9264 bnx2x_set_ethtool_ops(dev);
5316bc0b 9265
66371c44
MM		 9266 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9267 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9268 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9269
9270 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9271 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9272
9273 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 9274 if (bp->flags & USING_DAC_FLAG)
66371c44 9275 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 9276
538dd2e3
MB		 9277 /* Add Loopback capability to the device */
9278 dev->hw_features |= NETIF_F_LOOPBACK;
9279
98507672 9280#ifdef BCM_DCBNL
785b9b1a
SR		 9281 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9282#endif
9283
01cd4528
EG		 9284 /* get_port_hwinfo() will set prtad and mmds properly */
9285 bp->mdio.prtad = MDIO_PRTAD_NONE;
9286 bp->mdio.mmds = 0;
9287 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9288 bp->mdio.dev = dev;
9289 bp->mdio.mdio_read = bnx2x_mdio_read;
9290 bp->mdio.mdio_write = bnx2x_mdio_write;
9291
a2fbb9ea
ET		 9292 return 0;
9293
9294err_out_unmap:
9295 if (bp->regview) {
9296 iounmap(bp->regview);
9297 bp->regview = NULL;
9298 }
a2fbb9ea
ET		 9299 if (bp->doorbells) {
9300 iounmap(bp->doorbells);
9301 bp->doorbells = NULL;
9302 }
9303
9304err_out_release:
34f80b04
EG		 9305 if (atomic_read(&pdev->enable_cnt) == 1)
9306 pci_release_regions(pdev);
a2fbb9ea
ET		 9307
9308err_out_disable:
9309 pci_disable_device(pdev);
9310 pci_set_drvdata(pdev, NULL);
9311
9312err_out:
9313 return rc;
9314}
9315
37f9ce62
EG		 9316static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9317 int *width, int *speed)
25047950
ET		 9318{
9319 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9320
37f9ce62 9321 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 9322
37f9ce62
EG		 9323 /* return value of 1=2.5GHz 2=5GHz */
9324 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 9325}
37f9ce62 9326
6891dd25 9327static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 9328{
37f9ce62 9329 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 9330 struct bnx2x_fw_file_hdr *fw_hdr;
9331 struct bnx2x_fw_file_section *sections;
94a78b79 9332 u32 offset, len, num_ops;
37f9ce62 9333 u16 *ops_offsets;
94a78b79 9334 int i;
37f9ce62 9335 const u8 *fw_ver;
94a78b79
VZ		 9336
9337 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9338 return -EINVAL;
9339
9340 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9341 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9342
9343 /* Make sure none of the offsets and sizes make us read beyond
9344 * the end of the firmware data */
9345 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9346 offset = be32_to_cpu(sections[i].offset);
9347 len = be32_to_cpu(sections[i].len);
9348 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 9349 dev_err(&bp->pdev->dev,
9350 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 9351 return -EINVAL;
9352 }
9353 }
9354
9355 /* Likewise for the init_ops offsets */
9356 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9357 ops_offsets = (u16 *)(firmware->data + offset);
9358 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9359
9360 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9361 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 9362 dev_err(&bp->pdev->dev,
9363 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 9364 return -EINVAL;
9365 }
9366 }
9367
9368 /* Check FW version */
9369 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9370 fw_ver = firmware->data + offset;
9371 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9372 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9373 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9374 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 9375 dev_err(&bp->pdev->dev,
9376 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 9377 fw_ver[0], fw_ver[1], fw_ver[2],
9378 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9379 BCM_5710_FW_MINOR_VERSION,
9380 BCM_5710_FW_REVISION_VERSION,
9381 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 9382 return -EINVAL;
94a78b79
VZ		 9383 }
9384
9385 return 0;
9386}
9387
ab6ad5a4 9388static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9389{
ab6ad5a4
EG		 9390 const __be32 *source = (const __be32 *)_source;
9391 u32 *target = (u32 *)_target;
94a78b79 9392 u32 i;
94a78b79
VZ		 9393
9394 for (i = 0; i < n/4; i++)
9395 target[i] = be32_to_cpu(source[i]);
9396}
9397
9398/*
9399 Ops array is stored in the following format:
9400 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9401 */
ab6ad5a4 9402static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 9403{
ab6ad5a4
EG		 9404 const __be32 *source = (const __be32 *)_source;
9405 struct raw_op *target = (struct raw_op *)_target;
94a78b79 9406 u32 i, j, tmp;
94a78b79 9407
ab6ad5a4 9408 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 9409 tmp = be32_to_cpu(source[j]);
9410 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 9411 target[i].offset = tmp & 0xffffff;
9412 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 9413 }
9414}
ab6ad5a4 9415
523224a3
DK		 9416/**
9417 * IRO array is stored in the following format:
9418 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9419 */
9420static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9421{
9422 const __be32 *source = (const __be32 *)_source;
9423 struct iro *target = (struct iro *)_target;
9424 u32 i, j, tmp;
9425
9426 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9427 target[i].base = be32_to_cpu(source[j]);
9428 j++;
9429 tmp = be32_to_cpu(source[j]);
9430 target[i].m1 = (tmp >> 16) & 0xffff;
9431 target[i].m2 = tmp & 0xffff;
9432 j++;
9433 tmp = be32_to_cpu(source[j]);
9434 target[i].m3 = (tmp >> 16) & 0xffff;
9435 target[i].size = tmp & 0xffff;
9436 j++;
9437 }
9438}
9439
ab6ad5a4 9440static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9441{
ab6ad5a4
EG		 9442 const __be16 *source = (const __be16 *)_source;
9443 u16 *target = (u16 *)_target;
94a78b79 9444 u32 i;
94a78b79
VZ		 9445
9446 for (i = 0; i < n/2; i++)
9447 target[i] = be16_to_cpu(source[i]);
9448}
9449
7995c64e
JP		 9450#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9451do { \
9452 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9453 bp->arr = kmalloc(len, GFP_KERNEL); \
9454 if (!bp->arr) { \
9455 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9456 goto lbl; \
9457 } \
9458 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9459 (u8 *)bp->arr, len); \
9460} while (0)
94a78b79 9461
6891dd25 9462int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 9463{
45229b42 9464 const char *fw_file_name;
94a78b79 9465 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 9466 int rc;
94a78b79 9467
94a78b79 9468 if (CHIP_IS_E1(bp))
45229b42 9469 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 9470 else if (CHIP_IS_E1H(bp))
45229b42 9471 fw_file_name = FW_FILE_NAME_E1H;
f2e0899f
DK		 9472 else if (CHIP_IS_E2(bp))
9473 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 9474 else {
6891dd25 9475 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 9476 return -EINVAL;
9477 }
94a78b79 9478
6891dd25 9479 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 9480
6891dd25 9481 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 9482 if (rc) {
6891dd25 9483 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 9484 goto request_firmware_exit;
9485 }
9486
9487 rc = bnx2x_check_firmware(bp);
9488 if (rc) {
6891dd25 9489 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 9490 goto request_firmware_exit;
9491 }
9492
9493 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9494
9495 /* Initialize the pointers to the init arrays */
9496 /* Blob */
9497 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9498
9499 /* Opcodes */
9500 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9501
9502 /* Offsets */
ab6ad5a4
EG		 9503 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9504 be16_to_cpu_n);
94a78b79
VZ		 9505
9506 /* STORMs firmware */
573f2035
EG		 9507 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9508 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9509 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9510 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9511 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9512 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9513 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9514 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9515 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9516 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9517 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9518 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9519 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9520 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9521 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9522 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 9523 /* IRO */
9524 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 9525
9526 return 0;
ab6ad5a4 9527
523224a3
DK		 9528iro_alloc_err:
9529 kfree(bp->init_ops_offsets);
94a78b79
VZ		 9530init_offsets_alloc_err:
9531 kfree(bp->init_ops);
9532init_ops_alloc_err:
9533 kfree(bp->init_data);
9534request_firmware_exit:
9535 release_firmware(bp->firmware);
9536
9537 return rc;
9538}
9539
523224a3
DK		 9540static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9541{
9542 int cid_count = L2_FP_COUNT(l2_cid_count);
94a78b79 9543
523224a3
DK		 9544#ifdef BCM_CNIC
9545 cid_count += CNIC_CID_MAX;
9546#endif
9547 return roundup(cid_count, QM_CID_ROUND);
9548}
f85582f8 9549
a2fbb9ea
ET		 9550static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9551 const struct pci_device_id *ent)
9552{
a2fbb9ea
ET		 9553 struct net_device *dev = NULL;
9554 struct bnx2x *bp;
37f9ce62 9555 int pcie_width, pcie_speed;
523224a3
DK		 9556 int rc, cid_count;
9557
f2e0899f
DK		 9558 switch (ent->driver_data) {
9559 case BCM57710:
9560 case BCM57711:
9561 case BCM57711E:
9562 cid_count = FP_SB_MAX_E1x;
9563 break;
9564
9565 case BCM57712:
9566 case BCM57712E:
9567 cid_count = FP_SB_MAX_E2;
9568 break;
a2fbb9ea 9569
f2e0899f
DK		 9570 default:
9571 pr_err("Unknown board_type (%ld), aborting\n",
9572 ent->driver_data);
870634b0 9573 return -ENODEV;
f2e0899f
DK		 9574 }
9575
ec6ba945 9576 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
f85582f8 9577
a2fbb9ea 9578 /* dev zeroed in init_etherdev */
523224a3 9579 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
34f80b04 9580 if (!dev) {
cdaa7cb8 9581 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 9582 return -ENOMEM;
34f80b04 9583 }
a2fbb9ea 9584
a2fbb9ea 9585 bp = netdev_priv(dev);
7995c64e 9586 bp->msg_enable = debug;
a2fbb9ea 9587
df4770de
EG		 9588 pci_set_drvdata(pdev, dev);
9589
523224a3
DK		 9590 bp->l2_cid_count = cid_count;
9591
34f80b04 9592 rc = bnx2x_init_dev(pdev, dev);
a2fbb9ea
ET		 9593 if (rc < 0) {
9594 free_netdev(dev);
9595 return rc;
9596 }
9597
34f80b04 9598 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 9599 if (rc)
9600 goto init_one_exit;
9601
523224a3
DK		 9602 /* calc qm_cid_count */
9603 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9604
ec6ba945
VZ		 9605#ifdef BCM_CNIC
9606 /* disable FCOE L2 queue for E1x*/
9607 if (CHIP_IS_E1x(bp))
9608 bp->flags |= NO_FCOE_FLAG;
9609
9610#endif
9611
25985edc 9612 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 9613 * needed, set bp->num_queues appropriately.
9614 */
9615 bnx2x_set_int_mode(bp);
9616
9617 /* Add all NAPI objects */
9618 bnx2x_add_all_napi(bp);
9619
b340007f
VZ		 9620 rc = register_netdev(dev);
9621 if (rc) {
9622 dev_err(&pdev->dev, "Cannot register net device\n");
9623 goto init_one_exit;
9624 }
9625
ec6ba945
VZ		 9626#ifdef BCM_CNIC
9627 if (!NO_FCOE(bp)) {
9628 /* Add storage MAC address */
9629 rtnl_lock();
9630 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9631 rtnl_unlock();
9632 }
9633#endif
9634
37f9ce62 9635 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 9636
cdaa7cb8
VZ		 9637 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9638 " IRQ %d, ", board_info[ent->driver_data].name,
9639 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 9640 pcie_width,
9641 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9642 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9643 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 9644 dev->base_addr, bp->pdev->irq);
9645 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 9646
a2fbb9ea 9647 return 0;
34f80b04
EG		 9648
9649init_one_exit:
9650 if (bp->regview)
9651 iounmap(bp->regview);
9652
9653 if (bp->doorbells)
9654 iounmap(bp->doorbells);
9655
9656 free_netdev(dev);
9657
9658 if (atomic_read(&pdev->enable_cnt) == 1)
9659 pci_release_regions(pdev);
9660
9661 pci_disable_device(pdev);
9662 pci_set_drvdata(pdev, NULL);
9663
9664 return rc;
a2fbb9ea
ET		 9665}
9666
9667static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9668{
9669 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 9670 struct bnx2x *bp;
9671
9672 if (!dev) {
cdaa7cb8 9673 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 9674 return;
9675 }
228241eb 9676 bp = netdev_priv(dev);
a2fbb9ea 9677
ec6ba945
VZ		 9678#ifdef BCM_CNIC
9679 /* Delete storage MAC address */
9680 if (!NO_FCOE(bp)) {
9681 rtnl_lock();
9682 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9683 rtnl_unlock();
9684 }
9685#endif
9686
98507672
SR		 9687#ifdef BCM_DCBNL
9688 /* Delete app tlvs from dcbnl */
9689 bnx2x_dcbnl_update_applist(bp, true);
9690#endif
9691
a2fbb9ea
ET		 9692 unregister_netdev(dev);
9693
d6214d7a
DK		 9694 /* Delete all NAPI objects */
9695 bnx2x_del_all_napi(bp);
9696
084d6cbb
VZ		 9697 /* Power on: we can't let PCI layer write to us while we are in D3 */
9698 bnx2x_set_power_state(bp, PCI_D0);
9699
d6214d7a
DK		 9700 /* Disable MSI/MSI-X */
9701 bnx2x_disable_msi(bp);
f85582f8 9702
084d6cbb
VZ		 9703 /* Power off */
9704 bnx2x_set_power_state(bp, PCI_D3hot);
9705
72fd0718
VZ		 9706 /* Make sure RESET task is not scheduled before continuing */
9707 cancel_delayed_work_sync(&bp->reset_task);
9708
a2fbb9ea
ET		 9709 if (bp->regview)
9710 iounmap(bp->regview);
9711
9712 if (bp->doorbells)
9713 iounmap(bp->doorbells);
9714
523224a3
DK		 9715 bnx2x_free_mem_bp(bp);
9716
a2fbb9ea 9717 free_netdev(dev);
34f80b04
EG		 9718
9719 if (atomic_read(&pdev->enable_cnt) == 1)
9720 pci_release_regions(pdev);
9721
a2fbb9ea
ET		 9722 pci_disable_device(pdev);
9723 pci_set_drvdata(pdev, NULL);
9724}
9725
f8ef6e44
YG		 9726static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9727{
9728 int i;
9729
9730 bp->state = BNX2X_STATE_ERROR;
9731
9732 bp->rx_mode = BNX2X_RX_MODE_NONE;
9733
9734 bnx2x_netif_stop(bp, 0);
c89af1a3 9735 netif_carrier_off(bp->dev);
f8ef6e44
YG		 9736
9737 del_timer_sync(&bp->timer);
9738 bp->stats_state = STATS_STATE_DISABLED;
9739 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9740
9741 /* Release IRQs */
d6214d7a 9742 bnx2x_free_irq(bp);
f8ef6e44 9743
f8ef6e44
YG		 9744 /* Free SKBs, SGEs, TPA pool and driver internals */
9745 bnx2x_free_skbs(bp);
523224a3 9746
ec6ba945 9747 for_each_rx_queue(bp, i)
f8ef6e44 9748 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 9749
f8ef6e44
YG		 9750 bnx2x_free_mem(bp);
9751
9752 bp->state = BNX2X_STATE_CLOSED;
9753
f8ef6e44
YG		 9754 return 0;
9755}
9756
9757static void bnx2x_eeh_recover(struct bnx2x *bp)
9758{
9759 u32 val;
9760
9761 mutex_init(&bp->port.phy_mutex);
9762
9763 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9764 bp->link_params.shmem_base = bp->common.shmem_base;
9765 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9766
9767 if (!bp->common.shmem_base ||
9768 (bp->common.shmem_base < 0xA0000) ||
9769 (bp->common.shmem_base >= 0xC0000)) {
9770 BNX2X_DEV_INFO("MCP not active\n");
9771 bp->flags |= NO_MCP_FLAG;
9772 return;
9773 }
9774
9775 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9776 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9777 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9778 BNX2X_ERR("BAD MCP validity signature\n");
9779
9780 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9781 bp->fw_seq =
9782 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9783 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 9784 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9785 }
9786}
9787
493adb1f
WX		 9788/**
9789 * bnx2x_io_error_detected - called when PCI error is detected
9790 * @pdev: Pointer to PCI device
9791 * @state: The current pci connection state
9792 *
9793 * This function is called after a PCI bus error affecting
9794 * this device has been detected.
9795 */
9796static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9797 pci_channel_state_t state)
9798{
9799 struct net_device *dev = pci_get_drvdata(pdev);
9800 struct bnx2x *bp = netdev_priv(dev);
9801
9802 rtnl_lock();
9803
9804 netif_device_detach(dev);
9805
07ce50e4
DN		 9806 if (state == pci_channel_io_perm_failure) {
9807 rtnl_unlock();
9808 return PCI_ERS_RESULT_DISCONNECT;
9809 }
9810
493adb1f 9811 if (netif_running(dev))
f8ef6e44 9812 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 9813
9814 pci_disable_device(pdev);
9815
9816 rtnl_unlock();
9817
9818 /* Request a slot reset */
9819 return PCI_ERS_RESULT_NEED_RESET;
9820}
9821
9822/**
9823 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9824 * @pdev: Pointer to PCI device
9825 *
9826 * Restart the card from scratch, as if from a cold-boot.
9827 */
9828static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9829{
9830 struct net_device *dev = pci_get_drvdata(pdev);
9831 struct bnx2x *bp = netdev_priv(dev);
9832
9833 rtnl_lock();
9834
9835 if (pci_enable_device(pdev)) {
9836 dev_err(&pdev->dev,
9837 "Cannot re-enable PCI device after reset\n");
9838 rtnl_unlock();
9839 return PCI_ERS_RESULT_DISCONNECT;
9840 }
9841
9842 pci_set_master(pdev);
9843 pci_restore_state(pdev);
9844
9845 if (netif_running(dev))
9846 bnx2x_set_power_state(bp, PCI_D0);
9847
9848 rtnl_unlock();
9849
9850 return PCI_ERS_RESULT_RECOVERED;
9851}
9852
9853/**
9854 * bnx2x_io_resume - called when traffic can start flowing again
9855 * @pdev: Pointer to PCI device
9856 *
9857 * This callback is called when the error recovery driver tells us that
9858 * its OK to resume normal operation.
9859 */
9860static void bnx2x_io_resume(struct pci_dev *pdev)
9861{
9862 struct net_device *dev = pci_get_drvdata(pdev);
9863 struct bnx2x *bp = netdev_priv(dev);
9864
72fd0718 9865 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f2e0899f
DK		 9866 printk(KERN_ERR "Handling parity error recovery. "
9867 "Try again later\n");
72fd0718
VZ		 9868 return;
9869 }
9870
493adb1f
WX		 9871 rtnl_lock();
9872
f8ef6e44
YG		 9873 bnx2x_eeh_recover(bp);
9874
493adb1f 9875 if (netif_running(dev))
f8ef6e44 9876 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 9877
9878 netif_device_attach(dev);
9879
9880 rtnl_unlock();
9881}
9882
9883static struct pci_error_handlers bnx2x_err_handler = {
9884 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 9885 .slot_reset = bnx2x_io_slot_reset,
9886 .resume = bnx2x_io_resume,
493adb1f
WX		 9887};
9888
a2fbb9ea 9889static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 9890 .name = DRV_MODULE_NAME,
9891 .id_table = bnx2x_pci_tbl,
9892 .probe = bnx2x_init_one,
9893 .remove = __devexit_p(bnx2x_remove_one),
9894 .suspend = bnx2x_suspend,
9895 .resume = bnx2x_resume,
9896 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 9897};
9898
9899static int __init bnx2x_init(void)
9900{
dd21ca6d
SG		 9901 int ret;
9902
7995c64e 9903 pr_info("%s", version);
938cf541 9904
1cf167f2
EG		 9905 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9906 if (bnx2x_wq == NULL) {
7995c64e 9907 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 9908 return -ENOMEM;
9909 }
9910
dd21ca6d
SG		 9911 ret = pci_register_driver(&bnx2x_pci_driver);
9912 if (ret) {
7995c64e 9913 pr_err("Cannot register driver\n");
dd21ca6d
SG		 9914 destroy_workqueue(bnx2x_wq);
9915 }
9916 return ret;
a2fbb9ea
ET		 9917}
9918
9919static void __exit bnx2x_cleanup(void)
9920{
9921 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 9922
9923 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 9924}
9925
9926module_init(bnx2x_init);
9927module_exit(bnx2x_cleanup);
9928
993ac7b5
MC		 9929#ifdef BCM_CNIC
9930
9931/* count denotes the number of new completions we have seen */
9932static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9933{
9934 struct eth_spe *spe;
9935
9936#ifdef BNX2X_STOP_ON_ERROR
9937 if (unlikely(bp->panic))
9938 return;
9939#endif
9940
9941 spin_lock_bh(&bp->spq_lock);
c2bff63f 9942 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 9943 bp->cnic_spq_pending -= count;
9944
993ac7b5 9945
c2bff63f
DK		 9946 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9947 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9948 & SPE_HDR_CONN_TYPE) >>
9949 SPE_HDR_CONN_TYPE_SHIFT;
9950
9951 /* Set validation for iSCSI L2 client before sending SETUP
9952 * ramrod
9953 */
9954 if (type == ETH_CONNECTION_TYPE) {
9955 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9956 hdr.conn_and_cmd_data) >>
9957 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9958
9959 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9960 bnx2x_set_ctx_validation(&bp->context.
9961 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9962 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9963 }
9964
6e30dd4e
VZ		 9965 /* There may be not more than 8 L2 and not more than 8 L5 SPEs
9966 * We also check that the number of outstanding
9967 * COMMON ramrods is not more than the EQ and SPQ can
9968 * accommodate.
c2bff63f 9969 */
6e30dd4e
VZ		 9970 if (type == ETH_CONNECTION_TYPE) {
9971 if (!atomic_read(&bp->cq_spq_left))
9972 break;
9973 else
9974 atomic_dec(&bp->cq_spq_left);
9975 } else if (type == NONE_CONNECTION_TYPE) {
9976 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 9977 break;
9978 else
6e30dd4e 9979 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 9980 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9981 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 9982 if (bp->cnic_spq_pending >=
9983 bp->cnic_eth_dev.max_kwqe_pending)
9984 break;
9985 else
9986 bp->cnic_spq_pending++;
9987 } else {
9988 BNX2X_ERR("Unknown SPE type: %d\n", type);
9989 bnx2x_panic();
993ac7b5 9990 break;
c2bff63f 9991 }
993ac7b5
MC		 9992
9993 spe = bnx2x_sp_get_next(bp);
9994 *spe = *bp->cnic_kwq_cons;
9995
993ac7b5
MC		 9996 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9997 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9998
9999 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
10000 bp->cnic_kwq_cons = bp->cnic_kwq;
10001 else
10002 bp->cnic_kwq_cons++;
10003 }
10004 bnx2x_sp_prod_update(bp);
10005 spin_unlock_bh(&bp->spq_lock);
10006}
10007
10008static int bnx2x_cnic_sp_queue(struct net_device *dev,
10009 struct kwqe_16 *kwqes[], u32 count)
10010{
10011 struct bnx2x *bp = netdev_priv(dev);
10012 int i;
10013
10014#ifdef BNX2X_STOP_ON_ERROR
10015 if (unlikely(bp->panic))
10016 return -EIO;
10017#endif
10018
10019 spin_lock_bh(&bp->spq_lock);
10020
10021 for (i = 0; i < count; i++) {
10022 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10023
10024 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10025 break;
10026
10027 *bp->cnic_kwq_prod = *spe;
10028
10029 bp->cnic_kwq_pending++;
10030
10031 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10032 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 10033 spe->data.update_data_addr.hi,
10034 spe->data.update_data_addr.lo,
993ac7b5
MC		 10035 bp->cnic_kwq_pending);
10036
10037 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10038 bp->cnic_kwq_prod = bp->cnic_kwq;
10039 else
10040 bp->cnic_kwq_prod++;
10041 }
10042
10043 spin_unlock_bh(&bp->spq_lock);
10044
10045 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10046 bnx2x_cnic_sp_post(bp, 0);
10047
10048 return i;
10049}
10050
10051static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10052{
10053 struct cnic_ops *c_ops;
10054 int rc = 0;
10055
10056 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 10057 c_ops = rcu_dereference_protected(bp->cnic_ops,
10058 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 10059 if (c_ops)
10060 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10061 mutex_unlock(&bp->cnic_mutex);
10062
10063 return rc;
10064}
10065
10066static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10067{
10068 struct cnic_ops *c_ops;
10069 int rc = 0;
10070
10071 rcu_read_lock();
10072 c_ops = rcu_dereference(bp->cnic_ops);
10073 if (c_ops)
10074 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10075 rcu_read_unlock();
10076
10077 return rc;
10078}
10079
10080/*
10081 * for commands that have no data
10082 */
9f6c9258 10083int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 10084{
10085 struct cnic_ctl_info ctl = {0};
10086
10087 ctl.cmd = cmd;
10088
10089 return bnx2x_cnic_ctl_send(bp, &ctl);
10090}
10091
10092static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
10093{
10094 struct cnic_ctl_info ctl;
10095
10096 /* first we tell CNIC and only then we count this as a completion */
10097 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10098 ctl.data.comp.cid = cid;
10099
10100 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 10101 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 10102}
10103
10104static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10105{
10106 struct bnx2x *bp = netdev_priv(dev);
10107 int rc = 0;
10108
10109 switch (ctl->cmd) {
10110 case DRV_CTL_CTXTBL_WR_CMD: {
10111 u32 index = ctl->data.io.offset;
10112 dma_addr_t addr = ctl->data.io.dma_addr;
10113
10114 bnx2x_ilt_wr(bp, index, addr);
10115 break;
10116 }
10117
c2bff63f
DK		 10118 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10119 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 10120
10121 bnx2x_cnic_sp_post(bp, count);
10122 break;
10123 }
10124
10125 /* rtnl_lock is held. */
10126 case DRV_CTL_START_L2_CMD: {
10127 u32 cli = ctl->data.ring.client_id;
10128
ec6ba945
VZ		 10129 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
10130 bnx2x_del_fcoe_eth_macs(bp);
10131
523224a3
DK		 10132 /* Set iSCSI MAC address */
10133 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10134
10135 mmiowb();
10136 barrier();
10137
10138 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10139 * because it's the only way for UIO Client to accept
10140 * multicasts (in non-promiscuous mode only one Client per
10141 * function will receive multicast packets (leading in our
10142 * case).
10143 */
10144 bnx2x_rxq_set_mac_filters(bp, cli,
10145 BNX2X_ACCEPT_UNICAST |
10146 BNX2X_ACCEPT_BROADCAST |
10147 BNX2X_ACCEPT_ALL_MULTICAST);
10148 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10149
993ac7b5
MC		 10150 break;
10151 }
10152
10153 /* rtnl_lock is held. */
10154 case DRV_CTL_STOP_L2_CMD: {
10155 u32 cli = ctl->data.ring.client_id;
10156
523224a3
DK		 10157 /* Stop accepting on iSCSI L2 ring */
10158 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10159 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10160
10161 mmiowb();
10162 barrier();
10163
10164 /* Unset iSCSI L2 MAC */
10165 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
993ac7b5
MC		 10166 break;
10167 }
c2bff63f
DK		 10168 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10169 int count = ctl->data.credit.credit_count;
10170
10171 smp_mb__before_atomic_inc();
6e30dd4e 10172 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 10173 smp_mb__after_atomic_inc();
10174 break;
10175 }
993ac7b5 10176
fab0dc89
DK		 10177 case DRV_CTL_ISCSI_STOPPED_CMD: {
10178 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_ISCSI_STOPPED);
10179 break;
10180 }
10181
993ac7b5
MC		 10182 default:
10183 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10184 rc = -EINVAL;
10185 }
10186
10187 return rc;
10188}
10189
9f6c9258 10190void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 10191{
10192 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10193
10194 if (bp->flags & USING_MSIX_FLAG) {
10195 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10196 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10197 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10198 } else {
10199 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10200 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10201 }
f2e0899f
DK		 10202 if (CHIP_IS_E2(bp))
10203 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10204 else
10205 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10206
993ac7b5 10207 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
523224a3 10208 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
993ac7b5
MC		 10209 cp->irq_arr[1].status_blk = bp->def_status_blk;
10210 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 10211 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 10212
10213 cp->num_irq = 2;
10214}
10215
10216static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10217 void *data)
10218{
10219 struct bnx2x *bp = netdev_priv(dev);
10220 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10221
10222 if (ops == NULL)
10223 return -EINVAL;
10224
10225 if (atomic_read(&bp->intr_sem) != 0)
10226 return -EBUSY;
10227
10228 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10229 if (!bp->cnic_kwq)
10230 return -ENOMEM;
10231
10232 bp->cnic_kwq_cons = bp->cnic_kwq;
10233 bp->cnic_kwq_prod = bp->cnic_kwq;
10234 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10235
10236 bp->cnic_spq_pending = 0;
10237 bp->cnic_kwq_pending = 0;
10238
10239 bp->cnic_data = data;
10240
10241 cp->num_irq = 0;
10242 cp->drv_state = CNIC_DRV_STATE_REGD;
523224a3 10243 cp->iro_arr = bp->iro_arr;
993ac7b5 10244
993ac7b5 10245 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 10246
993ac7b5
MC		 10247 rcu_assign_pointer(bp->cnic_ops, ops);
10248
10249 return 0;
10250}
10251
10252static int bnx2x_unregister_cnic(struct net_device *dev)
10253{
10254 struct bnx2x *bp = netdev_priv(dev);
10255 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10256
10257 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 10258 cp->drv_state = 0;
10259 rcu_assign_pointer(bp->cnic_ops, NULL);
10260 mutex_unlock(&bp->cnic_mutex);
10261 synchronize_rcu();
10262 kfree(bp->cnic_kwq);
10263 bp->cnic_kwq = NULL;
10264
10265 return 0;
10266}
10267
10268struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10269{
10270 struct bnx2x *bp = netdev_priv(dev);
10271 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10272
2ba45142
VZ		 10273 /* If both iSCSI and FCoE are disabled - return NULL in
10274 * order to indicate CNIC that it should not try to work
10275 * with this device.
10276 */
10277 if (NO_ISCSI(bp) && NO_FCOE(bp))
10278 return NULL;
10279
993ac7b5
MC		 10280 cp->drv_owner = THIS_MODULE;
10281 cp->chip_id = CHIP_ID(bp);
10282 cp->pdev = bp->pdev;
10283 cp->io_base = bp->regview;
10284 cp->io_base2 = bp->doorbells;
10285 cp->max_kwqe_pending = 8;
523224a3 10286 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 10287 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10288 bnx2x_cid_ilt_lines(bp);
993ac7b5 10289 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 10290 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 10291 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10292 cp->drv_ctl = bnx2x_drv_ctl;
10293 cp->drv_register_cnic = bnx2x_register_cnic;
10294 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945
VZ		 10295 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10296 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10297 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
c2bff63f
DK		 10298 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10299
2ba45142
VZ		 10300 if (NO_ISCSI_OOO(bp))
10301 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10302
10303 if (NO_ISCSI(bp))
10304 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10305
10306 if (NO_FCOE(bp))
10307 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10308
c2bff63f
DK		 10309 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10310 "starting cid %d\n",
10311 cp->ctx_blk_size,
10312 cp->ctx_tbl_offset,
10313 cp->ctx_tbl_len,
10314 cp->starting_cid);
993ac7b5
MC		 10315 return cp;
10316}
10317EXPORT_SYMBOL(bnx2x_cnic_probe);
10318
10319#endif /* BCM_CNIC */
94a78b79 10320
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