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New 7.0 FW: bnx2x, cnic, bnx2i, bnx2fc
[mirror_ubuntu-bionic-kernel.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea 41#include <net/ip.h>
619c5cb6 42#include <net/ipv6.h>
a2fbb9ea
ET		 43#include <net/tcp.h>
44#include <net/checksum.h>
34f80b04 45#include <net/ip6_checksum.h>
a2fbb9ea
ET		 46#include <linux/workqueue.h>
47#include <linux/crc32.h>
34f80b04 48#include <linux/crc32c.h>
a2fbb9ea
ET		 49#include <linux/prefetch.h>
50#include <linux/zlib.h>
a2fbb9ea 51#include <linux/io.h>
45229b42 52#include <linux/stringify.h>
a2fbb9ea 53
a2fbb9ea
ET		 54#include "bnx2x.h"
55#include "bnx2x_init.h"
94a78b79 56#include "bnx2x_init_ops.h"
9f6c9258 57#include "bnx2x_cmn.h"
e4901dde 58#include "bnx2x_dcb.h"
042181f5 59#include "bnx2x_sp.h"
a2fbb9ea 60
94a78b79
VZ		 61#include <linux/firmware.h>
62#include "bnx2x_fw_file_hdr.h"
63/* FW files */
45229b42
BH		 64#define FW_FILE_VERSION \
65 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
66 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
67 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
68 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 69#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
70#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 71#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 72
34f80b04
EG		 73/* Time in jiffies before concluding the transmitter is hung */
74#define TX_TIMEOUT (5*HZ)
a2fbb9ea 75
53a10565 76static char version[] __devinitdata =
619c5cb6 77 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 78 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79
24e3fcef 80MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 81MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 82 "BCM57710/57711/57711E/"
83 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
84 "57840/57840_MF Driver");
a2fbb9ea
ET		 85MODULE_LICENSE("GPL");
86MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 87MODULE_FIRMWARE(FW_FILE_NAME_E1);
88MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 89MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 90
555f6c78
EG		 91static int multi_mode = 1;
92module_param(multi_mode, int, 0);
ca00392c
EG		 93MODULE_PARM_DESC(multi_mode, " Multi queue mode "
94 "(0 Disable; 1 Enable (default))");
95
d6214d7a 96int num_queues;
54b9ddaa
VZ		 97module_param(num_queues, int, 0);
98MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
99 " (default is as a number of CPUs)");
555f6c78 100
19680c48 101static int disable_tpa;
19680c48 102module_param(disable_tpa, int, 0);
9898f86d 103MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 104
9ee3d37b
DK		 105#define INT_MODE_INTx 1
106#define INT_MODE_MSI 2
8badd27a
EG		 107static int int_mode;
108module_param(int_mode, int, 0);
619c5cb6 109MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 110 "(1 INT#x; 2 MSI)");
8badd27a 111
a18f5128
EG		 112static int dropless_fc;
113module_param(dropless_fc, int, 0);
114MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
115
9898f86d 116static int poll;
a2fbb9ea 117module_param(poll, int, 0);
9898f86d 118MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 119
120static int mrrs = -1;
121module_param(mrrs, int, 0);
122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
9898f86d 124static int debug;
a2fbb9ea 125module_param(debug, int, 0);
9898f86d
EG		 126MODULE_PARM_DESC(debug, " Default debug msglevel");
127
a2fbb9ea 128
619c5cb6
VZ		 129
130struct workqueue_struct *bnx2x_wq;
ec6ba945 131
a2fbb9ea
ET		 132enum bnx2x_board_type {
133 BCM57710 = 0,
619c5cb6
VZ		 134 BCM57711,
135 BCM57711E,
136 BCM57712,
137 BCM57712_MF,
138 BCM57800,
139 BCM57800_MF,
140 BCM57810,
141 BCM57810_MF,
142 BCM57840,
143 BCM57840_MF
a2fbb9ea
ET		 144};
145
34f80b04 146/* indexed by board_type, above */
53a10565 147static struct {
a2fbb9ea
ET		 148 char *name;
149} board_info[] __devinitdata = {
619c5cb6
VZ		 150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
161 "Ethernet Multi Function"}
a2fbb9ea
ET		 162};
163
619c5cb6
VZ		 164#ifndef PCI_DEVICE_ID_NX2_57710
165#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
166#endif
167#ifndef PCI_DEVICE_ID_NX2_57711
168#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
169#endif
170#ifndef PCI_DEVICE_ID_NX2_57711E
171#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
172#endif
173#ifndef PCI_DEVICE_ID_NX2_57712
174#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
175#endif
176#ifndef PCI_DEVICE_ID_NX2_57712_MF
177#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
178#endif
179#ifndef PCI_DEVICE_ID_NX2_57800
180#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
181#endif
182#ifndef PCI_DEVICE_ID_NX2_57800_MF
183#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
184#endif
185#ifndef PCI_DEVICE_ID_NX2_57810
186#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
187#endif
188#ifndef PCI_DEVICE_ID_NX2_57810_MF
189#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
190#endif
191#ifndef PCI_DEVICE_ID_NX2_57840
192#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
193#endif
194#ifndef PCI_DEVICE_ID_NX2_57840_MF
195#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
196#endif
a3aa1884 197static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 209 { 0 }
210};
211
212MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
213
214/****************************************************************************
215* General service functions
216****************************************************************************/
217
619c5cb6
VZ		 218static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
219 u32 addr, dma_addr_t mapping)
220{
221 REG_WR(bp, addr, U64_LO(mapping));
222 REG_WR(bp, addr + 4, U64_HI(mapping));
223}
224
225static inline void storm_memset_spq_addr(struct bnx2x *bp,
226 dma_addr_t mapping, u16 abs_fid)
227{
228 u32 addr = XSEM_REG_FAST_MEMORY +
229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
230
231 __storm_memset_dma_mapping(bp, addr, mapping);
232}
233
234static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
235 u16 pf_id)
523224a3 236{
619c5cb6
VZ		 237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
238 pf_id);
239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
240 pf_id);
241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
523224a3
DK		 245}
246
619c5cb6
VZ		 247static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
248 u8 enable)
249{
250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
251 enable);
252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
253 enable);
254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258}
523224a3
DK		 259
260static inline void storm_memset_eq_data(struct bnx2x *bp,
261 struct event_ring_data *eq_data,
262 u16 pfid)
263{
264 size_t size = sizeof(struct event_ring_data);
265
266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
269}
270
271static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
272 u16 pfid)
273{
274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
275 REG_WR16(bp, addr, eq_prod);
276}
277
a2fbb9ea
ET		 278/* used only at init
279 * locking is done by mcp
280 */
8d96286a 281static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 282{
283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
286 PCICFG_VENDOR_ID_OFFSET);
287}
288
a2fbb9ea
ET		 289static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
290{
291 u32 val;
292
293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
296 PCICFG_VENDOR_ID_OFFSET);
297
298 return val;
299}
a2fbb9ea 300
f2e0899f
DK		 301#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
302#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
303#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
304#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
305#define DMAE_DP_DST_NONE "dst_addr [none]"
306
8d96286a 307static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
308 int msglvl)
f2e0899f
DK		 309{
310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
311
312 switch (dmae->opcode & DMAE_COMMAND_DST) {
313 case DMAE_CMD_DST_PCI:
314 if (src_type == DMAE_CMD_SRC_PCI)
315 DP(msglvl, "DMAE: opcode 0x%08x\n"
316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
317 "comp_addr [%x:%08x], comp_val 0x%08x\n",
318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
320 dmae->comp_addr_hi, dmae->comp_addr_lo,
321 dmae->comp_val);
322 else
323 DP(msglvl, "DMAE: opcode 0x%08x\n"
324 "src [%08x], len [%d*4], dst [%x:%08x]\n"
325 "comp_addr [%x:%08x], comp_val 0x%08x\n",
326 dmae->opcode, dmae->src_addr_lo >> 2,
327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
328 dmae->comp_addr_hi, dmae->comp_addr_lo,
329 dmae->comp_val);
330 break;
331 case DMAE_CMD_DST_GRC:
332 if (src_type == DMAE_CMD_SRC_PCI)
333 DP(msglvl, "DMAE: opcode 0x%08x\n"
334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
335 "comp_addr [%x:%08x], comp_val 0x%08x\n",
336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
337 dmae->len, dmae->dst_addr_lo >> 2,
338 dmae->comp_addr_hi, dmae->comp_addr_lo,
339 dmae->comp_val);
340 else
341 DP(msglvl, "DMAE: opcode 0x%08x\n"
342 "src [%08x], len [%d*4], dst [%08x]\n"
343 "comp_addr [%x:%08x], comp_val 0x%08x\n",
344 dmae->opcode, dmae->src_addr_lo >> 2,
345 dmae->len, dmae->dst_addr_lo >> 2,
346 dmae->comp_addr_hi, dmae->comp_addr_lo,
347 dmae->comp_val);
348 break;
349 default:
350 if (src_type == DMAE_CMD_SRC_PCI)
351 DP(msglvl, "DMAE: opcode 0x%08x\n"
352 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
353 "dst_addr [none]\n"
354 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
355 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
356 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
357 dmae->comp_val);
358 else
359 DP(msglvl, "DMAE: opcode 0x%08x\n"
360 DP_LEVEL "src_addr [%08x] len [%d * 4] "
361 "dst_addr [none]\n"
362 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
363 dmae->opcode, dmae->src_addr_lo >> 2,
364 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
365 dmae->comp_val);
366 break;
367 }
368
369}
370
a2fbb9ea 371/* copy command into DMAE command memory and set DMAE command go */
6c719d00 372void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 373{
374 u32 cmd_offset;
375 int i;
376
377 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
378 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
379 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
380
ad8d3948
EG		 381 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
382 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 383 }
384 REG_WR(bp, dmae_reg_go_c[idx], 1);
385}
386
f2e0899f 387u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 388{
f2e0899f
DK		 389 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
390 DMAE_CMD_C_ENABLE);
391}
ad8d3948 392
f2e0899f
DK		 393u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
394{
395 return opcode & ~DMAE_CMD_SRC_RESET;
396}
ad8d3948 397
f2e0899f
DK		 398u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
399 bool with_comp, u8 comp_type)
400{
401 u32 opcode = 0;
402
403 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
404 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 405
f2e0899f
DK		 406 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
407
408 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
409 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
410 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
411 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 412
a2fbb9ea 413#ifdef __BIG_ENDIAN
f2e0899f 414 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 415#else
f2e0899f 416 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 417#endif
f2e0899f
DK		 418 if (with_comp)
419 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
420 return opcode;
421}
422
8d96286a 423static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
424 struct dmae_command *dmae,
425 u8 src_type, u8 dst_type)
f2e0899f
DK		 426{
427 memset(dmae, 0, sizeof(struct dmae_command));
428
429 /* set the opcode */
430 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
431 true, DMAE_COMP_PCI);
432
433 /* fill in the completion parameters */
434 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
435 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_val = DMAE_COMP_VAL;
437}
438
439/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 440static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
441 struct dmae_command *dmae)
f2e0899f
DK		 442{
443 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 444 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 445 int rc = 0;
446
447 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 448 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
449 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 450
619c5cb6
VZ		 451 /*
452 * Lock the dmae channel. Disable BHs to prevent a dead-lock
453 * as long as this code is called both from syscall context and
454 * from ndo_set_rx_mode() flow that may be called from BH.
455 */
6e30dd4e 456 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 457
f2e0899f 458 /* reset completion */
a2fbb9ea
ET		 459 *wb_comp = 0;
460
f2e0899f
DK		 461 /* post the command on the channel used for initializations */
462 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 463
f2e0899f 464 /* wait for completion */
a2fbb9ea 465 udelay(5);
f2e0899f 466 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 467 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
468
ad8d3948 469 if (!cnt) {
c3eefaf6 470 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 471 rc = DMAE_TIMEOUT;
472 goto unlock;
a2fbb9ea 473 }
ad8d3948 474 cnt--;
f2e0899f 475 udelay(50);
a2fbb9ea 476 }
f2e0899f
DK		 477 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
478 BNX2X_ERR("DMAE PCI error!\n");
479 rc = DMAE_PCI_ERROR;
480 }
481
482 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
483 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
484 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 485
f2e0899f 486unlock:
6e30dd4e 487 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 488 return rc;
489}
490
491void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
492 u32 len32)
493{
494 struct dmae_command dmae;
495
496 if (!bp->dmae_ready) {
497 u32 *data = bnx2x_sp(bp, wb_data[0]);
498
499 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
500 " using indirect\n", dst_addr, len32);
501 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
502 return;
503 }
504
505 /* set opcode and fixed command fields */
506 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
507
508 /* fill in addresses and len */
509 dmae.src_addr_lo = U64_LO(dma_addr);
510 dmae.src_addr_hi = U64_HI(dma_addr);
511 dmae.dst_addr_lo = dst_addr >> 2;
512 dmae.dst_addr_hi = 0;
513 dmae.len = len32;
514
515 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
516
517 /* issue the command and wait for completion */
518 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 519}
520
c18487ee 521void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 522{
5ff7b6d4 523 struct dmae_command dmae;
ad8d3948
EG		 524
525 if (!bp->dmae_ready) {
526 u32 *data = bnx2x_sp(bp, wb_data[0]);
527 int i;
528
529 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
530 " using indirect\n", src_addr, len32);
531 for (i = 0; i < len32; i++)
532 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
533 return;
534 }
535
f2e0899f
DK		 536 /* set opcode and fixed command fields */
537 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 538
f2e0899f 539 /* fill in addresses and len */
5ff7b6d4
EG		 540 dmae.src_addr_lo = src_addr >> 2;
541 dmae.src_addr_hi = 0;
542 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
543 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
544 dmae.len = len32;
ad8d3948 545
f2e0899f 546 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 547
f2e0899f
DK		 548 /* issue the command and wait for completion */
549 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 550}
551
8d96286a 552static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
553 u32 addr, u32 len)
573f2035 554{
02e3c6cb 555 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 556 int offset = 0;
557
02e3c6cb 558 while (len > dmae_wr_max) {
573f2035 559 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 560 addr + offset, dmae_wr_max);
561 offset += dmae_wr_max * 4;
562 len -= dmae_wr_max;
573f2035
EG		 563 }
564
565 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
566}
567
ad8d3948
EG		 568/* used only for slowpath so not inlined */
569static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
570{
571 u32 wb_write[2];
572
573 wb_write[0] = val_hi;
574 wb_write[1] = val_lo;
575 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 576}
a2fbb9ea 577
ad8d3948
EG		 578#ifdef USE_WB_RD
579static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
580{
581 u32 wb_data[2];
582
583 REG_RD_DMAE(bp, reg, wb_data, 2);
584
585 return HILO_U64(wb_data[0], wb_data[1]);
586}
587#endif
588
a2fbb9ea
ET		 589static int bnx2x_mc_assert(struct bnx2x *bp)
590{
a2fbb9ea 591 char last_idx;
34f80b04
EG		 592 int i, rc = 0;
593 u32 row0, row1, row2, row3;
594
595 /* XSTORM */
596 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
597 XSTORM_ASSERT_LIST_INDEX_OFFSET);
598 if (last_idx)
599 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
600
601 /* print the asserts */
602 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
603
604 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
605 XSTORM_ASSERT_LIST_OFFSET(i));
606 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
608 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
610 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
612
613 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
614 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
615 " 0x%08x 0x%08x 0x%08x\n",
616 i, row3, row2, row1, row0);
617 rc++;
618 } else {
619 break;
620 }
621 }
622
623 /* TSTORM */
624 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
625 TSTORM_ASSERT_LIST_INDEX_OFFSET);
626 if (last_idx)
627 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
628
629 /* print the asserts */
630 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
631
632 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
633 TSTORM_ASSERT_LIST_OFFSET(i));
634 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
636 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
638 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
640
641 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
642 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
643 " 0x%08x 0x%08x 0x%08x\n",
644 i, row3, row2, row1, row0);
645 rc++;
646 } else {
647 break;
648 }
649 }
650
651 /* CSTORM */
652 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
653 CSTORM_ASSERT_LIST_INDEX_OFFSET);
654 if (last_idx)
655 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
656
657 /* print the asserts */
658 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
659
660 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
661 CSTORM_ASSERT_LIST_OFFSET(i));
662 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
664 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
666 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
668
669 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
670 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
671 " 0x%08x 0x%08x 0x%08x\n",
672 i, row3, row2, row1, row0);
673 rc++;
674 } else {
675 break;
676 }
677 }
678
679 /* USTORM */
680 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
681 USTORM_ASSERT_LIST_INDEX_OFFSET);
682 if (last_idx)
683 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
684
685 /* print the asserts */
686 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
687
688 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
689 USTORM_ASSERT_LIST_OFFSET(i));
690 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i) + 4);
692 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 8);
694 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 12);
696
697 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
698 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
699 " 0x%08x 0x%08x 0x%08x\n",
700 i, row3, row2, row1, row0);
701 rc++;
702 } else {
703 break;
a2fbb9ea
ET		 704 }
705 }
34f80b04 706
a2fbb9ea
ET		 707 return rc;
708}
c14423fe 709
7a25cc73 710void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 711{
7a25cc73 712 u32 addr, val;
a2fbb9ea 713 u32 mark, offset;
4781bfad 714 __be32 data[9];
a2fbb9ea 715 int word;
f2e0899f 716 u32 trace_shmem_base;
2145a920
VZ		 717 if (BP_NOMCP(bp)) {
718 BNX2X_ERR("NO MCP - can not dump\n");
719 return;
720 }
7a25cc73
DK		 721 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
722 (bp->common.bc_ver & 0xff0000) >> 16,
723 (bp->common.bc_ver & 0xff00) >> 8,
724 (bp->common.bc_ver & 0xff));
725
726 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
727 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
728 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 729
f2e0899f
DK		 730 if (BP_PATH(bp) == 0)
731 trace_shmem_base = bp->common.shmem_base;
732 else
733 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
734 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 735 mark = REG_RD(bp, addr);
f2e0899f
DK		 736 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
737 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 738 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 739
7a25cc73 740 printk("%s", lvl);
f2e0899f 741 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 742 for (word = 0; word < 8; word++)
cdaa7cb8 743 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 744 data[8] = 0x0;
7995c64e 745 pr_cont("%s", (char *)data);
a2fbb9ea 746 }
cdaa7cb8 747 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 748 for (word = 0; word < 8; word++)
cdaa7cb8 749 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 750 data[8] = 0x0;
7995c64e 751 pr_cont("%s", (char *)data);
a2fbb9ea 752 }
7a25cc73
DK		 753 printk("%s" "end of fw dump\n", lvl);
754}
755
756static inline void bnx2x_fw_dump(struct bnx2x *bp)
757{
758 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 759}
760
6c719d00 761void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 762{
763 int i;
523224a3
DK		 764 u16 j;
765 struct hc_sp_status_block_data sp_sb_data;
766 int func = BP_FUNC(bp);
767#ifdef BNX2X_STOP_ON_ERROR
768 u16 start = 0, end = 0;
769#endif
a2fbb9ea 770
66e855f3
YG		 771 bp->stats_state = STATS_STATE_DISABLED;
772 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
773
a2fbb9ea
ET		 774 BNX2X_ERR("begin crash dump -----------------\n");
775
8440d2b6
EG		 776 /* Indices */
777 /* Common */
523224a3 778 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 779 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
780 bp->def_idx, bp->def_att_idx, bp->attn_state,
781 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 782 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
783 bp->def_status_blk->atten_status_block.attn_bits,
784 bp->def_status_blk->atten_status_block.attn_bits_ack,
785 bp->def_status_blk->atten_status_block.status_block_id,
786 bp->def_status_blk->atten_status_block.attn_bits_index);
787 BNX2X_ERR(" def (");
788 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
789 pr_cont("0x%x%s",
790 bp->def_status_blk->sp_sb.index_values[i],
791 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
792
793 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
794 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
795 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
796 i*sizeof(u32));
797
619c5cb6 798 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
523224a3 799 "pf_id(0x%x) vnic_id(0x%x) "
619c5cb6
VZ		 800 "vf_id(0x%x) vf_valid (0x%x) "
801 "state(0x%x)\n",
523224a3
DK		 802 sp_sb_data.igu_sb_id,
803 sp_sb_data.igu_seg_id,
804 sp_sb_data.p_func.pf_id,
805 sp_sb_data.p_func.vnic_id,
806 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 807 sp_sb_data.p_func.vf_valid,
808 sp_sb_data.state);
523224a3 809
8440d2b6 810
ec6ba945 811 for_each_eth_queue(bp, i) {
a2fbb9ea 812 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 813 int loop;
f2e0899f 814 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 815 struct hc_status_block_data_e1x sb_data_e1x;
816 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 817 CHIP_IS_E1x(bp) ?
818 sb_data_e1x.common.state_machine :
819 sb_data_e2.common.state_machine;
523224a3 820 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 821 CHIP_IS_E1x(bp) ?
822 sb_data_e1x.index_data :
823 sb_data_e2.index_data;
523224a3
DK		 824 int data_size;
825 u32 *sb_data_p;
826
827 /* Rx */
cdaa7cb8 828 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 829 " rx_comp_prod(0x%x)"
cdaa7cb8 830 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 831 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 832 fp->rx_comp_prod,
66e855f3 833 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 834 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 835 " fp_hc_idx(0x%x)\n",
8440d2b6 836 fp->rx_sge_prod, fp->last_max_sge,
523224a3 837 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 838
523224a3 839 /* Tx */
cdaa7cb8
VZ		 840 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
841 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
842 " *tx_cons_sb(0x%x)\n",
8440d2b6
EG		 843 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
844 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
523224a3 845
619c5cb6
VZ		 846 loop = CHIP_IS_E1x(bp) ?
847 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 848
849 /* host sb data */
850
ec6ba945
VZ		 851#ifdef BCM_CNIC
852 if (IS_FCOE_FP(fp))
853 continue;
854#endif
523224a3
DK		 855 BNX2X_ERR(" run indexes (");
856 for (j = 0; j < HC_SB_MAX_SM; j++)
857 pr_cont("0x%x%s",
858 fp->sb_running_index[j],
859 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
860
861 BNX2X_ERR(" indexes (");
862 for (j = 0; j < loop; j++)
863 pr_cont("0x%x%s",
864 fp->sb_index_values[j],
865 (j == loop - 1) ? ")" : " ");
866 /* fw sb data */
619c5cb6
VZ		 867 data_size = CHIP_IS_E1x(bp) ?
868 sizeof(struct hc_status_block_data_e1x) :
869 sizeof(struct hc_status_block_data_e2);
523224a3 870 data_size /= sizeof(u32);
619c5cb6
VZ		 871 sb_data_p = CHIP_IS_E1x(bp) ?
872 (u32 *)&sb_data_e1x :
873 (u32 *)&sb_data_e2;
523224a3
DK		 874 /* copy sb data in here */
875 for (j = 0; j < data_size; j++)
876 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
877 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
878 j * sizeof(u32));
879
619c5cb6
VZ		 880 if (!CHIP_IS_E1x(bp)) {
881 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
882 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
883 "state(0x%x)\n",
f2e0899f
DK		 884 sb_data_e2.common.p_func.pf_id,
885 sb_data_e2.common.p_func.vf_id,
886 sb_data_e2.common.p_func.vf_valid,
887 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 888 sb_data_e2.common.same_igu_sb_1b,
889 sb_data_e2.common.state);
f2e0899f 890 } else {
619c5cb6
VZ		 891 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
892 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
893 "state(0x%x)\n",
f2e0899f
DK		 894 sb_data_e1x.common.p_func.pf_id,
895 sb_data_e1x.common.p_func.vf_id,
896 sb_data_e1x.common.p_func.vf_valid,
897 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 898 sb_data_e1x.common.same_igu_sb_1b,
899 sb_data_e1x.common.state);
f2e0899f 900 }
523224a3
DK		 901
902 /* SB_SMs data */
903 for (j = 0; j < HC_SB_MAX_SM; j++) {
904 pr_cont("SM[%d] __flags (0x%x) "
905 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
906 "time_to_expire (0x%x) "
907 "timer_value(0x%x)\n", j,
908 hc_sm_p[j].__flags,
909 hc_sm_p[j].igu_sb_id,
910 hc_sm_p[j].igu_seg_id,
911 hc_sm_p[j].time_to_expire,
912 hc_sm_p[j].timer_value);
913 }
914
915 /* Indecies data */
916 for (j = 0; j < loop; j++) {
917 pr_cont("INDEX[%d] flags (0x%x) "
918 "timeout (0x%x)\n", j,
919 hc_index_p[j].flags,
920 hc_index_p[j].timeout);
921 }
8440d2b6 922 }
a2fbb9ea 923
523224a3 924#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 925 /* Rings */
926 /* Rx */
ec6ba945 927 for_each_rx_queue(bp, i) {
8440d2b6 928 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 929
930 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
931 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 932 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 933 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
934 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
935
c3eefaf6
EG		 936 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
937 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 938 }
939
3196a88a
EG		 940 start = RX_SGE(fp->rx_sge_prod);
941 end = RX_SGE(fp->last_max_sge);
8440d2b6 942 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 943 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
944 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
945
c3eefaf6
EG		 946 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
947 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 948 }
949
a2fbb9ea
ET		 950 start = RCQ_BD(fp->rx_comp_cons - 10);
951 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 952 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 953 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
954
c3eefaf6
EG		 955 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
956 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 957 }
958 }
959
8440d2b6 960 /* Tx */
ec6ba945 961 for_each_tx_queue(bp, i) {
8440d2b6
EG		 962 struct bnx2x_fastpath *fp = &bp->fp[i];
963
964 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
965 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
966 for (j = start; j != end; j = TX_BD(j + 1)) {
967 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
968
c3eefaf6
EG		 969 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
970 i, j, sw_bd->skb, sw_bd->first_bd);
8440d2b6
EG		 971 }
972
973 start = TX_BD(fp->tx_bd_cons - 10);
974 end = TX_BD(fp->tx_bd_cons + 254);
975 for (j = start; j != end; j = TX_BD(j + 1)) {
976 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
977
c3eefaf6
EG		 978 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
979 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
8440d2b6
EG		 980 }
981 }
523224a3 982#endif
34f80b04 983 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 984 bnx2x_mc_assert(bp);
985 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 986}
987
619c5cb6
VZ		 988/*
989 * FLR Support for E2
990 *
991 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
992 * initialization.
993 */
994#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
995#define FLR_WAIT_INTERAVAL 50 /* usec */
996#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
997
998struct pbf_pN_buf_regs {
999 int pN;
1000 u32 init_crd;
1001 u32 crd;
1002 u32 crd_freed;
1003};
1004
1005struct pbf_pN_cmd_regs {
1006 int pN;
1007 u32 lines_occup;
1008 u32 lines_freed;
1009};
1010
1011static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1012 struct pbf_pN_buf_regs *regs,
1013 u32 poll_count)
1014{
1015 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1016 u32 cur_cnt = poll_count;
1017
1018 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1019 crd = crd_start = REG_RD(bp, regs->crd);
1020 init_crd = REG_RD(bp, regs->init_crd);
1021
1022 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1023 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1024 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1025
1026 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1027 (init_crd - crd_start))) {
1028 if (cur_cnt--) {
1029 udelay(FLR_WAIT_INTERAVAL);
1030 crd = REG_RD(bp, regs->crd);
1031 crd_freed = REG_RD(bp, regs->crd_freed);
1032 } else {
1033 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1034 regs->pN);
1035 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1036 regs->pN, crd);
1037 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1038 regs->pN, crd_freed);
1039 break;
1040 }
1041 }
1042 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1043 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1044}
1045
1046static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1047 struct pbf_pN_cmd_regs *regs,
1048 u32 poll_count)
1049{
1050 u32 occup, to_free, freed, freed_start;
1051 u32 cur_cnt = poll_count;
1052
1053 occup = to_free = REG_RD(bp, regs->lines_occup);
1054 freed = freed_start = REG_RD(bp, regs->lines_freed);
1055
1056 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1057 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1058
1059 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1060 if (cur_cnt--) {
1061 udelay(FLR_WAIT_INTERAVAL);
1062 occup = REG_RD(bp, regs->lines_occup);
1063 freed = REG_RD(bp, regs->lines_freed);
1064 } else {
1065 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1066 regs->pN);
1067 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1068 regs->pN, occup);
1069 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1070 regs->pN, freed);
1071 break;
1072 }
1073 }
1074 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1075 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1076}
1077
1078static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1079 u32 expected, u32 poll_count)
1080{
1081 u32 cur_cnt = poll_count;
1082 u32 val;
1083
1084 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1085 udelay(FLR_WAIT_INTERAVAL);
1086
1087 return val;
1088}
1089
1090static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1091 char *msg, u32 poll_cnt)
1092{
1093 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1094 if (val != 0) {
1095 BNX2X_ERR("%s usage count=%d\n", msg, val);
1096 return 1;
1097 }
1098 return 0;
1099}
1100
1101static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1102{
1103 /* adjust polling timeout */
1104 if (CHIP_REV_IS_EMUL(bp))
1105 return FLR_POLL_CNT * 2000;
1106
1107 if (CHIP_REV_IS_FPGA(bp))
1108 return FLR_POLL_CNT * 120;
1109
1110 return FLR_POLL_CNT;
1111}
1112
1113static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1114{
1115 struct pbf_pN_cmd_regs cmd_regs[] = {
1116 {0, (CHIP_IS_E3B0(bp)) ?
1117 PBF_REG_TQ_OCCUPANCY_Q0 :
1118 PBF_REG_P0_TQ_OCCUPANCY,
1119 (CHIP_IS_E3B0(bp)) ?
1120 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1121 PBF_REG_P0_TQ_LINES_FREED_CNT},
1122 {1, (CHIP_IS_E3B0(bp)) ?
1123 PBF_REG_TQ_OCCUPANCY_Q1 :
1124 PBF_REG_P1_TQ_OCCUPANCY,
1125 (CHIP_IS_E3B0(bp)) ?
1126 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1127 PBF_REG_P1_TQ_LINES_FREED_CNT},
1128 {4, (CHIP_IS_E3B0(bp)) ?
1129 PBF_REG_TQ_OCCUPANCY_LB_Q :
1130 PBF_REG_P4_TQ_OCCUPANCY,
1131 (CHIP_IS_E3B0(bp)) ?
1132 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1133 PBF_REG_P4_TQ_LINES_FREED_CNT}
1134 };
1135
1136 struct pbf_pN_buf_regs buf_regs[] = {
1137 {0, (CHIP_IS_E3B0(bp)) ?
1138 PBF_REG_INIT_CRD_Q0 :
1139 PBF_REG_P0_INIT_CRD ,
1140 (CHIP_IS_E3B0(bp)) ?
1141 PBF_REG_CREDIT_Q0 :
1142 PBF_REG_P0_CREDIT,
1143 (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1145 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1146 {1, (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_INIT_CRD_Q1 :
1148 PBF_REG_P1_INIT_CRD,
1149 (CHIP_IS_E3B0(bp)) ?
1150 PBF_REG_CREDIT_Q1 :
1151 PBF_REG_P1_CREDIT,
1152 (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1154 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1155 {4, (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_INIT_CRD_LB_Q :
1157 PBF_REG_P4_INIT_CRD,
1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_CREDIT_LB_Q :
1160 PBF_REG_P4_CREDIT,
1161 (CHIP_IS_E3B0(bp)) ?
1162 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1163 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1164 };
1165
1166 int i;
1167
1168 /* Verify the command queues are flushed P0, P1, P4 */
1169 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1170 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1171
1172
1173 /* Verify the transmission buffers are flushed P0, P1, P4 */
1174 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1175 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1176}
1177
1178#define OP_GEN_PARAM(param) \
1179 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1180
1181#define OP_GEN_TYPE(type) \
1182 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1183
1184#define OP_GEN_AGG_VECT(index) \
1185 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1186
1187
1188static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1189 u32 poll_cnt)
1190{
1191 struct sdm_op_gen op_gen = {0};
1192
1193 u32 comp_addr = BAR_CSTRORM_INTMEM +
1194 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1195 int ret = 0;
1196
1197 if (REG_RD(bp, comp_addr)) {
1198 BNX2X_ERR("Cleanup complete is not 0\n");
1199 return 1;
1200 }
1201
1202 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1203 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1204 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1205 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1206
1207 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1208 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1209
1210 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1211 BNX2X_ERR("FW final cleanup did not succeed\n");
1212 ret = 1;
1213 }
1214 /* Zero completion for nxt FLR */
1215 REG_WR(bp, comp_addr, 0);
1216
1217 return ret;
1218}
1219
1220static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1221{
1222 int pos;
1223 u16 status;
1224
1225 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1226 if (!pos)
1227 return false;
1228
1229 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1230 return status & PCI_EXP_DEVSTA_TRPND;
1231}
1232
1233/* PF FLR specific routines
1234*/
1235static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1236{
1237
1238 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1239 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1240 CFC_REG_NUM_LCIDS_INSIDE_PF,
1241 "CFC PF usage counter timed out",
1242 poll_cnt))
1243 return 1;
1244
1245
1246 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1247 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1248 DORQ_REG_PF_USAGE_CNT,
1249 "DQ PF usage counter timed out",
1250 poll_cnt))
1251 return 1;
1252
1253 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1256 "QM PF usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1261 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1262 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1263 "Timers VNIC usage counter timed out",
1264 poll_cnt))
1265 return 1;
1266 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1267 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1268 "Timers NUM_SCANS usage counter timed out",
1269 poll_cnt))
1270 return 1;
1271
1272 /* Wait DMAE PF usage counter to zero */
1273 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1274 dmae_reg_go_c[INIT_DMAE_C(bp)],
1275 "DMAE dommand register timed out",
1276 poll_cnt))
1277 return 1;
1278
1279 return 0;
1280}
1281
1282static void bnx2x_hw_enable_status(struct bnx2x *bp)
1283{
1284 u32 val;
1285
1286 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1287 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1288
1289 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1290 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1291
1292 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1293 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1294
1295 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1296 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1297
1298 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1299 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1300
1301 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1302 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1303
1304 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1305 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1306
1307 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1308 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1309 val);
1310}
1311
1312static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1313{
1314 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1315
1316 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1317
1318 /* Re-enable PF target read access */
1319 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1320
1321 /* Poll HW usage counters */
1322 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1323 return -EBUSY;
1324
1325 /* Zero the igu 'trailing edge' and 'leading edge' */
1326
1327 /* Send the FW cleanup command */
1328 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1329 return -EBUSY;
1330
1331 /* ATC cleanup */
1332
1333 /* Verify TX hw is flushed */
1334 bnx2x_tx_hw_flushed(bp, poll_cnt);
1335
1336 /* Wait 100ms (not adjusted according to platform) */
1337 msleep(100);
1338
1339 /* Verify no pending pci transactions */
1340 if (bnx2x_is_pcie_pending(bp->pdev))
1341 BNX2X_ERR("PCIE Transactions still pending\n");
1342
1343 /* Debug */
1344 bnx2x_hw_enable_status(bp);
1345
1346 /*
1347 * Master enable - Due to WB DMAE writes performed before this
1348 * register is re-initialized as part of the regular function init
1349 */
1350 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1351
1352 return 0;
1353}
1354
f2e0899f 1355static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1356{
34f80b04 1357 int port = BP_PORT(bp);
a2fbb9ea
ET		 1358 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1359 u32 val = REG_RD(bp, addr);
1360 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1361 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1362
1363 if (msix) {
8badd27a
EG		 1364 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1365 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1366 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1367 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1368 } else if (msi) {
1369 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1370 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1371 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1372 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1373 } else {
1374 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1375 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1376 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1377 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1378
a0fd065c
DK		 1379 if (!CHIP_IS_E1(bp)) {
1380 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1381 val, port, addr);
615f8fd9 1382
a0fd065c 1383 REG_WR(bp, addr, val);
615f8fd9 1384
a0fd065c
DK		 1385 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1386 }
a2fbb9ea
ET		 1387 }
1388
a0fd065c
DK		 1389 if (CHIP_IS_E1(bp))
1390 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1391
8badd27a
EG		 1392 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1393 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1394
1395 REG_WR(bp, addr, val);
37dbbf32
EG		 1396 /*
1397 * Ensure that HC_CONFIG is written before leading/trailing edge config
1398 */
1399 mmiowb();
1400 barrier();
34f80b04 1401
f2e0899f 1402 if (!CHIP_IS_E1(bp)) {
34f80b04 1403 /* init leading/trailing edge */
fb3bff17 1404 if (IS_MF(bp)) {
8badd27a 1405 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1406 if (bp->port.pmf)
4acac6a5
EG		 1407 /* enable nig and gpio3 attention */
1408 val |= 0x1100;
34f80b04
EG		 1409 } else
1410 val = 0xffff;
1411
1412 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1413 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1414 }
37dbbf32
EG		 1415
1416 /* Make sure that interrupts are indeed enabled from here on */
1417 mmiowb();
a2fbb9ea
ET		 1418}
1419
f2e0899f
DK		 1420static void bnx2x_igu_int_enable(struct bnx2x *bp)
1421{
1422 u32 val;
1423 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1424 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1425
1426 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1427
1428 if (msix) {
1429 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1430 IGU_PF_CONF_SINGLE_ISR_EN);
1431 val |= (IGU_PF_CONF_FUNC_EN |
1432 IGU_PF_CONF_MSI_MSIX_EN |
1433 IGU_PF_CONF_ATTN_BIT_EN);
1434 } else if (msi) {
1435 val &= ~IGU_PF_CONF_INT_LINE_EN;
1436 val |= (IGU_PF_CONF_FUNC_EN |
1437 IGU_PF_CONF_MSI_MSIX_EN |
1438 IGU_PF_CONF_ATTN_BIT_EN |
1439 IGU_PF_CONF_SINGLE_ISR_EN);
1440 } else {
1441 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1442 val |= (IGU_PF_CONF_FUNC_EN |
1443 IGU_PF_CONF_INT_LINE_EN |
1444 IGU_PF_CONF_ATTN_BIT_EN |
1445 IGU_PF_CONF_SINGLE_ISR_EN);
1446 }
1447
1448 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1449 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1450
1451 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1452
1453 barrier();
1454
1455 /* init leading/trailing edge */
1456 if (IS_MF(bp)) {
1457 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1458 if (bp->port.pmf)
1459 /* enable nig and gpio3 attention */
1460 val |= 0x1100;
1461 } else
1462 val = 0xffff;
1463
1464 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1465 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1466
1467 /* Make sure that interrupts are indeed enabled from here on */
1468 mmiowb();
1469}
1470
1471void bnx2x_int_enable(struct bnx2x *bp)
1472{
1473 if (bp->common.int_block == INT_BLOCK_HC)
1474 bnx2x_hc_int_enable(bp);
1475 else
1476 bnx2x_igu_int_enable(bp);
1477}
1478
1479static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1480{
34f80b04 1481 int port = BP_PORT(bp);
a2fbb9ea
ET		 1482 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1483 u32 val = REG_RD(bp, addr);
1484
a0fd065c
DK		 1485 /*
1486 * in E1 we must use only PCI configuration space to disable
1487 * MSI/MSIX capablility
1488 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1489 */
1490 if (CHIP_IS_E1(bp)) {
1491 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1492 * Use mask register to prevent from HC sending interrupts
1493 * after we exit the function
1494 */
1495 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1496
1497 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1498 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1499 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1500 } else
1501 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1502 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1503 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1504 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1505
1506 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1507 val, port, addr);
1508
8badd27a
EG		 1509 /* flush all outstanding writes */
1510 mmiowb();
1511
a2fbb9ea
ET		 1512 REG_WR(bp, addr, val);
1513 if (REG_RD(bp, addr) != val)
1514 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1515}
1516
f2e0899f
DK		 1517static void bnx2x_igu_int_disable(struct bnx2x *bp)
1518{
1519 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1520
1521 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1522 IGU_PF_CONF_INT_LINE_EN |
1523 IGU_PF_CONF_ATTN_BIT_EN);
1524
1525 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1526
1527 /* flush all outstanding writes */
1528 mmiowb();
1529
1530 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1531 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1532 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1533}
1534
8d96286a 1535static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1536{
1537 if (bp->common.int_block == INT_BLOCK_HC)
1538 bnx2x_hc_int_disable(bp);
1539 else
1540 bnx2x_igu_int_disable(bp);
1541}
1542
9f6c9258 1543void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1544{
a2fbb9ea 1545 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1546 int i, offset;
a2fbb9ea 1547
f8ef6e44
YG		 1548 if (disable_hw)
1549 /* prevent the HW from sending interrupts */
1550 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1551
1552 /* make sure all ISRs are done */
1553 if (msix) {
8badd27a
EG		 1554 synchronize_irq(bp->msix_table[0].vector);
1555 offset = 1;
37b091ba
MC		 1556#ifdef BCM_CNIC
1557 offset++;
1558#endif
ec6ba945 1559 for_each_eth_queue(bp, i)
8badd27a 1560 synchronize_irq(bp->msix_table[i + offset].vector);
a2fbb9ea
ET		 1561 } else
1562 synchronize_irq(bp->pdev->irq);
1563
1564 /* make sure sp_task is not running */
1cf167f2
EG		 1565 cancel_delayed_work(&bp->sp_task);
1566 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1567}
1568
34f80b04 1569/* fast path */
a2fbb9ea
ET		 1570
1571/*
34f80b04 1572 * General service functions
a2fbb9ea
ET		 1573 */
1574
72fd0718
VZ		 1575/* Return true if succeeded to acquire the lock */
1576static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1577{
1578 u32 lock_status;
1579 u32 resource_bit = (1 << resource);
1580 int func = BP_FUNC(bp);
1581 u32 hw_lock_control_reg;
1582
1583 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1584
1585 /* Validating that the resource is within range */
1586 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1587 DP(NETIF_MSG_HW,
1588 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1589 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1590 return false;
72fd0718
VZ		 1591 }
1592
1593 if (func <= 5)
1594 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1595 else
1596 hw_lock_control_reg =
1597 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1598
1599 /* Try to acquire the lock */
1600 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1601 lock_status = REG_RD(bp, hw_lock_control_reg);
1602 if (lock_status & resource_bit)
1603 return true;
1604
1605 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1606 return false;
1607}
1608
993ac7b5 1609#ifdef BCM_CNIC
619c5cb6 1610static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1611#endif
3196a88a 1612
619c5cb6 1613void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1614{
1615 struct bnx2x *bp = fp->bp;
1616 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1617 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1618 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1619 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1620
34f80b04 1621 DP(BNX2X_MSG_SP,
a2fbb9ea 1622 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1623 fp->index, cid, command, bp->state,
34f80b04 1624 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1625
619c5cb6
VZ		 1626 switch (command) {
1627 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1628 DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
1629 drv_cmd = BNX2X_Q_CMD_UPDATE;
1630 break;
1631 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
523224a3 1632 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1633 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1634 break;
1635
619c5cb6 1636 case (RAMROD_CMD_ID_ETH_HALT):
523224a3 1637 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1638 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1639 break;
1640
619c5cb6 1641 case (RAMROD_CMD_ID_ETH_TERMINATE):
523224a3 1642 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1643 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1644 break;
1645
619c5cb6
VZ		 1646 case (RAMROD_CMD_ID_ETH_EMPTY):
1647 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
1648 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1649 break;
619c5cb6
VZ		 1650
1651 default:
1652 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1653 command, fp->index);
1654 return;
523224a3 1655 }
3196a88a 1656
619c5cb6
VZ		 1657 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1658 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1659 /* q_obj->complete_cmd() failure means that this was
1660 * an unexpected completion.
1661 *
1662 * In this case we don't want to increase the bp->spq_left
1663 * because apparently we haven't sent this command the first
1664 * place.
1665 */
1666#ifdef BNX2X_STOP_ON_ERROR
1667 bnx2x_panic();
1668#else
1669 return;
1670#endif
1671
8fe23fbd 1672 smp_mb__before_atomic_inc();
6e30dd4e 1673 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1674 /* push the change in bp->spq_left and towards the memory */
1675 smp_mb__after_atomic_inc();
49d66772 1676
523224a3 1677 return;
a2fbb9ea
ET		 1678}
1679
619c5cb6
VZ		 1680void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1681 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1682{
1683 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1684
1685 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1686 start);
1687}
1688
9f6c9258 1689irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1690{
555f6c78 1691 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1692 u16 status = bnx2x_ack_int(bp);
34f80b04 1693 u16 mask;
ca00392c 1694 int i;
a2fbb9ea 1695
34f80b04 1696 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1697 if (unlikely(status == 0)) {
1698 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1699 return IRQ_NONE;
1700 }
f5372251 1701 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1702
3196a88a
EG		 1703#ifdef BNX2X_STOP_ON_ERROR
1704 if (unlikely(bp->panic))
1705 return IRQ_HANDLED;
1706#endif
1707
ec6ba945 1708 for_each_eth_queue(bp, i) {
ca00392c 1709 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1710
523224a3 1711 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
ca00392c 1712 if (status & mask) {
619c5cb6 1713 /* Handle Rx or Tx according to SB id */
54b9ddaa 1714 prefetch(fp->rx_cons_sb);
54b9ddaa 1715 prefetch(fp->tx_cons_sb);
523224a3 1716 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1717 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1718 status &= ~mask;
1719 }
a2fbb9ea
ET		 1720 }
1721
993ac7b5 1722#ifdef BCM_CNIC
523224a3 1723 mask = 0x2;
993ac7b5
MC		 1724 if (status & (mask | 0x1)) {
1725 struct cnic_ops *c_ops = NULL;
1726
619c5cb6
VZ		 1727 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1728 rcu_read_lock();
1729 c_ops = rcu_dereference(bp->cnic_ops);
1730 if (c_ops)
1731 c_ops->cnic_handler(bp->cnic_data, NULL);
1732 rcu_read_unlock();
1733 }
993ac7b5
MC		 1734
1735 status &= ~mask;
1736 }
1737#endif
a2fbb9ea 1738
34f80b04 1739 if (unlikely(status & 0x1)) {
1cf167f2 1740 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1741
1742 status &= ~0x1;
1743 if (!status)
1744 return IRQ_HANDLED;
1745 }
1746
cdaa7cb8
VZ		 1747 if (unlikely(status))
1748 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1749 status);
a2fbb9ea 1750
c18487ee 1751 return IRQ_HANDLED;
a2fbb9ea
ET		 1752}
1753
c18487ee
YR		 1754/* Link */
1755
1756/*
1757 * General service functions
1758 */
a2fbb9ea 1759
9f6c9258 1760int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1761{
1762 u32 lock_status;
1763 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1764 int func = BP_FUNC(bp);
1765 u32 hw_lock_control_reg;
c18487ee 1766 int cnt;
a2fbb9ea 1767
c18487ee
YR		 1768 /* Validating that the resource is within range */
1769 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1770 DP(NETIF_MSG_HW,
1771 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1772 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1773 return -EINVAL;
1774 }
a2fbb9ea 1775
4a37fb66
YG		 1776 if (func <= 5) {
1777 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1778 } else {
1779 hw_lock_control_reg =
1780 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1781 }
1782
c18487ee 1783 /* Validating that the resource is not already taken */
4a37fb66 1784 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1785 if (lock_status & resource_bit) {
1786 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1787 lock_status, resource_bit);
1788 return -EEXIST;
1789 }
a2fbb9ea 1790
46230476
EG		 1791 /* Try for 5 second every 5ms */
1792 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1793 /* Try to acquire the lock */
4a37fb66
YG		 1794 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1795 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1796 if (lock_status & resource_bit)
1797 return 0;
a2fbb9ea 1798
c18487ee 1799 msleep(5);
a2fbb9ea 1800 }
c18487ee
YR		 1801 DP(NETIF_MSG_HW, "Timeout\n");
1802 return -EAGAIN;
1803}
a2fbb9ea 1804
9f6c9258 1805int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1806{
1807 u32 lock_status;
1808 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1809 int func = BP_FUNC(bp);
1810 u32 hw_lock_control_reg;
a2fbb9ea 1811
72fd0718
VZ		 1812 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1813
c18487ee
YR		 1814 /* Validating that the resource is within range */
1815 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1816 DP(NETIF_MSG_HW,
1817 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1818 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1819 return -EINVAL;
1820 }
1821
4a37fb66
YG		 1822 if (func <= 5) {
1823 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1824 } else {
1825 hw_lock_control_reg =
1826 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1827 }
1828
c18487ee 1829 /* Validating that the resource is currently taken */
4a37fb66 1830 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1831 if (!(lock_status & resource_bit)) {
1832 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1833 lock_status, resource_bit);
1834 return -EFAULT;
a2fbb9ea
ET		 1835 }
1836
9f6c9258
DK		 1837 REG_WR(bp, hw_lock_control_reg, resource_bit);
1838 return 0;
c18487ee 1839}
a2fbb9ea 1840
9f6c9258 1841
4acac6a5
EG		 1842int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1843{
1844 /* The GPIO should be swapped if swap register is set and active */
1845 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1846 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1847 int gpio_shift = gpio_num +
1848 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1849 u32 gpio_mask = (1 << gpio_shift);
1850 u32 gpio_reg;
1851 int value;
1852
1853 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1854 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1855 return -EINVAL;
1856 }
1857
1858 /* read GPIO value */
1859 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1860
1861 /* get the requested pin value */
1862 if ((gpio_reg & gpio_mask) == gpio_mask)
1863 value = 1;
1864 else
1865 value = 0;
1866
1867 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1868
1869 return value;
1870}
1871
17de50b7 1872int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1873{
1874 /* The GPIO should be swapped if swap register is set and active */
1875 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1876 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1877 int gpio_shift = gpio_num +
1878 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1879 u32 gpio_mask = (1 << gpio_shift);
1880 u32 gpio_reg;
a2fbb9ea 1881
c18487ee
YR		 1882 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1883 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1884 return -EINVAL;
1885 }
a2fbb9ea 1886
4a37fb66 1887 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1888 /* read GPIO and mask except the float bits */
1889 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1890
c18487ee
YR		 1891 switch (mode) {
1892 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1893 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1894 gpio_num, gpio_shift);
1895 /* clear FLOAT and set CLR */
1896 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1897 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1898 break;
a2fbb9ea 1899
c18487ee
YR		 1900 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1901 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1902 gpio_num, gpio_shift);
1903 /* clear FLOAT and set SET */
1904 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1905 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1906 break;
a2fbb9ea 1907
17de50b7 1908 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1909 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1910 gpio_num, gpio_shift);
1911 /* set FLOAT */
1912 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1913 break;
a2fbb9ea 1914
c18487ee
YR		 1915 default:
1916 break;
a2fbb9ea
ET		 1917 }
1918
c18487ee 1919 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1920 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1921
c18487ee 1922 return 0;
a2fbb9ea
ET		 1923}
1924
4acac6a5
EG		 1925int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1926{
1927 /* The GPIO should be swapped if swap register is set and active */
1928 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1929 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1930 int gpio_shift = gpio_num +
1931 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1932 u32 gpio_mask = (1 << gpio_shift);
1933 u32 gpio_reg;
1934
1935 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1936 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1937 return -EINVAL;
1938 }
1939
1940 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1941 /* read GPIO int */
1942 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1943
1944 switch (mode) {
1945 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1946 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1947 "output low\n", gpio_num, gpio_shift);
1948 /* clear SET and set CLR */
1949 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1950 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1951 break;
1952
1953 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1954 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1955 "output high\n", gpio_num, gpio_shift);
1956 /* clear CLR and set SET */
1957 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1958 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1959 break;
1960
1961 default:
1962 break;
1963 }
1964
1965 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1966 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1967
1968 return 0;
1969}
1970
c18487ee 1971static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 1972{
c18487ee
YR		 1973 u32 spio_mask = (1 << spio_num);
1974 u32 spio_reg;
a2fbb9ea 1975
c18487ee
YR		 1976 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1977 (spio_num > MISC_REGISTERS_SPIO_7)) {
1978 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1979 return -EINVAL;
a2fbb9ea
ET		 1980 }
1981
4a37fb66 1982 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 1983 /* read SPIO and mask except the float bits */
1984 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 1985
c18487ee 1986 switch (mode) {
6378c025 1987 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 1988 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1989 /* clear FLOAT and set CLR */
1990 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1991 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1992 break;
a2fbb9ea 1993
6378c025 1994 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 1995 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1996 /* clear FLOAT and set SET */
1997 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1998 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1999 break;
a2fbb9ea 2000
c18487ee
YR		 2001 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2002 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2003 /* set FLOAT */
2004 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2005 break;
a2fbb9ea 2006
c18487ee
YR		 2007 default:
2008 break;
a2fbb9ea
ET		 2009 }
2010
c18487ee 2011 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2012 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2013
a2fbb9ea
ET		 2014 return 0;
2015}
2016
9f6c9258 2017void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2018{
a22f0788 2019 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2020 switch (bp->link_vars.ieee_fc &
2021 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2022 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2023 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2024 ADVERTISED_Pause);
c18487ee 2025 break;
356e2385 2026
c18487ee 2027 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2028 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2029 ADVERTISED_Pause);
c18487ee 2030 break;
356e2385 2031
c18487ee 2032 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2033 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2034 break;
356e2385 2035
c18487ee 2036 default:
a22f0788 2037 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2038 ADVERTISED_Pause);
c18487ee
YR		 2039 break;
2040 }
2041}
f1410647 2042
9f6c9258 2043u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2044{
19680c48
EG		 2045 if (!BP_NOMCP(bp)) {
2046 u8 rc;
a22f0788
YR		 2047 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2048 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 2049 /* Initialize link parameters structure variables */
8c99e7b0
YR		 2050 /* It is recommended to turn off RX FC for jumbo frames
2051 for better performance */
f2e0899f 2052 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 2053 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2054 else
c0700f90 2055 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2056
4a37fb66 2057 bnx2x_acquire_phy_lock(bp);
b5bf9068 2058
a22f0788 2059 if (load_mode == LOAD_DIAG) {
de6eae1f 2060 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 2061 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
2062 }
b5bf9068 2063
19680c48 2064 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2065
4a37fb66 2066 bnx2x_release_phy_lock(bp);
a2fbb9ea 2067
3c96c68b
EG		 2068 bnx2x_calc_fc_adv(bp);
2069
b5bf9068
EG		 2070 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2071 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2072 bnx2x_link_report(bp);
b5bf9068 2073 }
a22f0788 2074 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2075 return rc;
2076 }
f5372251 2077 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2078 return -EINVAL;
a2fbb9ea
ET		 2079}
2080
9f6c9258 2081void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2082{
19680c48 2083 if (!BP_NOMCP(bp)) {
4a37fb66 2084 bnx2x_acquire_phy_lock(bp);
54c2fb78 2085 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2086 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2087 bnx2x_release_phy_lock(bp);
a2fbb9ea 2088
19680c48
EG		 2089 bnx2x_calc_fc_adv(bp);
2090 } else
f5372251 2091 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2092}
a2fbb9ea 2093
c18487ee
YR		 2094static void bnx2x__link_reset(struct bnx2x *bp)
2095{
19680c48 2096 if (!BP_NOMCP(bp)) {
4a37fb66 2097 bnx2x_acquire_phy_lock(bp);
589abe3a 2098 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2099 bnx2x_release_phy_lock(bp);
19680c48 2100 } else
f5372251 2101 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2102}
a2fbb9ea 2103
a22f0788 2104u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2105{
2145a920 2106 u8 rc = 0;
a2fbb9ea 2107
2145a920
VZ		 2108 if (!BP_NOMCP(bp)) {
2109 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2110 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2111 is_serdes);
2145a920
VZ		 2112 bnx2x_release_phy_lock(bp);
2113 } else
2114 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2115
c18487ee
YR		 2116 return rc;
2117}
a2fbb9ea 2118
8a1c38d1 2119static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2120{
8a1c38d1
EG		 2121 u32 r_param = bp->link_vars.line_speed / 8;
2122 u32 fair_periodic_timeout_usec;
2123 u32 t_fair;
34f80b04 2124
8a1c38d1
EG		 2125 memset(&(bp->cmng.rs_vars), 0,
2126 sizeof(struct rate_shaping_vars_per_port));
2127 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2128
8a1c38d1
EG		 2129 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2130 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2131
8a1c38d1
EG		 2132 /* this is the threshold below which no timer arming will occur
2133 1.25 coefficient is for the threshold to be a little bigger
2134 than the real time, to compensate for timer in-accuracy */
2135 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2136 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2137
8a1c38d1
EG		 2138 /* resolution of fairness timer */
2139 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2140 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2141 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2142
8a1c38d1
EG		 2143 /* this is the threshold below which we won't arm the timer anymore */
2144 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2145
8a1c38d1
EG		 2146 /* we multiply by 1e3/8 to get bytes/msec.
2147 We don't want the credits to pass a credit
2148 of the t_fair*FAIR_MEM (algorithm resolution) */
2149 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2150 /* since each tick is 4 usec */
2151 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2152}
2153
2691d51d
EG		 2154/* Calculates the sum of vn_min_rates.
2155 It's needed for further normalizing of the min_rates.
2156 Returns:
2157 sum of vn_min_rates.
2158 or
2159 0 - if all the min_rates are 0.
2160 In the later case fainess algorithm should be deactivated.
2161 If not all min_rates are zero then those that are zeroes will be set to 1.
2162 */
2163static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2164{
2165 int all_zero = 1;
2691d51d
EG		 2166 int vn;
2167
2168 bp->vn_weight_sum = 0;
2169 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 2170 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2171 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2172 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2173
2174 /* Skip hidden vns */
2175 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2176 continue;
2177
2178 /* If min rate is zero - set it to 1 */
2179 if (!vn_min_rate)
2180 vn_min_rate = DEF_MIN_RATE;
2181 else
2182 all_zero = 0;
2183
2184 bp->vn_weight_sum += vn_min_rate;
2185 }
2186
30ae438b
DK		 2187 /* if ETS or all min rates are zeros - disable fairness */
2188 if (BNX2X_IS_ETS_ENABLED(bp)) {
2189 bp->cmng.flags.cmng_enables &=
2190 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2191 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2192 } else if (all_zero) {
b015e3d1
EG		 2193 bp->cmng.flags.cmng_enables &=
2194 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2195 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2196 " fairness will be disabled\n");
2197 } else
2198 bp->cmng.flags.cmng_enables |=
2199 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2200}
2201
f2e0899f 2202static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2203{
2204 struct rate_shaping_vars_per_vn m_rs_vn;
2205 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 2206 u32 vn_cfg = bp->mf_config[vn];
2207 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 2208 u16 vn_min_rate, vn_max_rate;
2209 int i;
2210
2211 /* If function is hidden - set min and max to zeroes */
2212 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2213 vn_min_rate = 0;
2214 vn_max_rate = 0;
2215
2216 } else {
faa6fcbb
DK		 2217 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2218
34f80b04
EG		 2219 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2220 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2221 /* If fairness is enabled (not all min rates are zeroes) and
2222 if current min rate is zero - set it to 1.
2223 This is a requirement of the algorithm. */
f2e0899f 2224 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2225 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2226
2227 if (IS_MF_SI(bp))
2228 /* maxCfg in percents of linkspeed */
2229 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2230 else
2231 /* maxCfg is absolute in 100Mb units */
2232 vn_max_rate = maxCfg * 100;
34f80b04 2233 }
f85582f8 2234
8a1c38d1 2235 DP(NETIF_MSG_IFUP,
b015e3d1 2236 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2237 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2238
2239 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2240 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2241
2242 /* global vn counter - maximal Mbps for this vn */
2243 m_rs_vn.vn_counter.rate = vn_max_rate;
2244
2245 /* quota - number of bytes transmitted in this period */
2246 m_rs_vn.vn_counter.quota =
2247 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2248
8a1c38d1 2249 if (bp->vn_weight_sum) {
34f80b04
EG		 2250 /* credit for each period of the fairness algorithm:
2251 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2252 vn_weight_sum should not be larger than 10000, thus
2253 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2254 than zero */
34f80b04 2255 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2256 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2257 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2258 (bp->cmng.fair_vars.fair_threshold +
2259 MIN_ABOVE_THRESH));
cdaa7cb8 2260 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2261 m_fair_vn.vn_credit_delta);
2262 }
2263
34f80b04
EG		 2264 /* Store it to internal memory */
2265 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2266 REG_WR(bp, BAR_XSTRORM_INTMEM +
2267 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2268 ((u32 *)(&m_rs_vn))[i]);
2269
2270 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2271 REG_WR(bp, BAR_XSTRORM_INTMEM +
2272 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2273 ((u32 *)(&m_fair_vn))[i]);
2274}
f85582f8 2275
523224a3
DK		 2276static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2277{
2278 if (CHIP_REV_IS_SLOW(bp))
2279 return CMNG_FNS_NONE;
fb3bff17 2280 if (IS_MF(bp))
523224a3
DK		 2281 return CMNG_FNS_MINMAX;
2282
2283 return CMNG_FNS_NONE;
2284}
2285
2ae17f66 2286void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2287{
0793f83f 2288 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2289
2290 if (BP_NOMCP(bp))
2291 return; /* what should be the default bvalue in this case */
2292
0793f83f
DK		 2293 /* For 2 port configuration the absolute function number formula
2294 * is:
2295 * abs_func = 2 * vn + BP_PORT + BP_PATH
2296 *
2297 * and there are 4 functions per port
2298 *
2299 * For 4 port configuration it is
2300 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2301 *
2302 * and there are 2 functions per port
2303 */
523224a3 2304 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2305 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2306
2307 if (func >= E1H_FUNC_MAX)
2308 break;
2309
f2e0899f 2310 bp->mf_config[vn] =
523224a3
DK		 2311 MF_CFG_RD(bp, func_mf_config[func].config);
2312 }
2313}
2314
2315static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2316{
2317
2318 if (cmng_type == CMNG_FNS_MINMAX) {
2319 int vn;
2320
2321 /* clear cmng_enables */
2322 bp->cmng.flags.cmng_enables = 0;
2323
2324 /* read mf conf from shmem */
2325 if (read_cfg)
2326 bnx2x_read_mf_cfg(bp);
2327
2328 /* Init rate shaping and fairness contexts */
2329 bnx2x_init_port_minmax(bp);
2330
2331 /* vn_weight_sum and enable fairness if not 0 */
2332 bnx2x_calc_vn_weight_sum(bp);
2333
2334 /* calculate and set min-max rate for each vn */
c4154f25
DK		 2335 if (bp->port.pmf)
2336 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2337 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2338
2339 /* always enable rate shaping and fairness */
2340 bp->cmng.flags.cmng_enables |=
2341 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2342 if (!bp->vn_weight_sum)
2343 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2344 " fairness will be disabled\n");
2345 return;
2346 }
2347
2348 /* rate shaping and fairness are disabled */
2349 DP(NETIF_MSG_IFUP,
2350 "rate shaping and fairness are disabled\n");
2351}
34f80b04 2352
523224a3
DK		 2353static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2354{
2355 int port = BP_PORT(bp);
2356 int func;
2357 int vn;
2358
2359 /* Set the attention towards other drivers on the same port */
2360 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2361 if (vn == BP_E1HVN(bp))
2362 continue;
2363
2364 func = ((vn << 1) | port);
2365 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2366 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2367 }
2368}
8a1c38d1 2369
c18487ee
YR		 2370/* This function is called upon link interrupt */
2371static void bnx2x_link_attn(struct bnx2x *bp)
2372{
bb2a0f7a
YG		 2373 /* Make sure that we are synced with the current statistics */
2374 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2375
c18487ee 2376 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2377
bb2a0f7a
YG		 2378 if (bp->link_vars.link_up) {
2379
1c06328c 2380 /* dropless flow control */
f2e0899f 2381 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2382 int port = BP_PORT(bp);
2383 u32 pause_enabled = 0;
2384
2385 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2386 pause_enabled = 1;
2387
2388 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2389 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2390 pause_enabled);
2391 }
2392
619c5cb6 2393 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2394 struct host_port_stats *pstats;
2395
2396 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2397 /* reset old mac stats */
bb2a0f7a
YG		 2398 memset(&(pstats->mac_stx[0]), 0,
2399 sizeof(struct mac_stx));
2400 }
f34d28ea 2401 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2402 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2403 }
2404
f2e0899f
DK		 2405 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2406 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2407
f2e0899f
DK		 2408 if (cmng_fns != CMNG_FNS_NONE) {
2409 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2410 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2411 } else
2412 /* rate shaping and fairness are disabled */
2413 DP(NETIF_MSG_IFUP,
2414 "single function mode without fairness\n");
34f80b04 2415 }
9fdc3e95 2416
2ae17f66
VZ		 2417 __bnx2x_link_report(bp);
2418
9fdc3e95
DK		 2419 if (IS_MF(bp))
2420 bnx2x_link_sync_notify(bp);
c18487ee 2421}
a2fbb9ea 2422
9f6c9258 2423void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2424{
2ae17f66 2425 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2426 return;
a2fbb9ea 2427
c18487ee 2428 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2429
bb2a0f7a
YG		 2430 if (bp->link_vars.link_up)
2431 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2432 else
2433 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2434
c18487ee
YR		 2435 /* indicate link status */
2436 bnx2x_link_report(bp);
a2fbb9ea 2437}
a2fbb9ea 2438
34f80b04
EG		 2439static void bnx2x_pmf_update(struct bnx2x *bp)
2440{
2441 int port = BP_PORT(bp);
2442 u32 val;
2443
2444 bp->port.pmf = 1;
2445 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2446
2447 /* enable nig attention */
2448 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2449 if (bp->common.int_block == INT_BLOCK_HC) {
2450 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2451 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2452 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2453 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2454 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2455 }
bb2a0f7a
YG		 2456
2457 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2458}
2459
c18487ee 2460/* end of Link */
a2fbb9ea
ET		 2461
2462/* slow path */
2463
2464/*
2465 * General service functions
2466 */
2467
2691d51d 2468/* send the MCP a request, block until there is a reply */
a22f0788 2469u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2470{
f2e0899f 2471 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2472 u32 seq;
2691d51d
EG		 2473 u32 rc = 0;
2474 u32 cnt = 1;
2475 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2476
c4ff7cbf 2477 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2478 seq = ++bp->fw_seq;
f2e0899f
DK		 2479 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2480 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2481
2691d51d
EG		 2482 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2483
2484 do {
2485 /* let the FW do it's magic ... */
2486 msleep(delay);
2487
f2e0899f 2488 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2489
c4ff7cbf
EG		 2490 /* Give the FW up to 5 second (500*10ms) */
2491 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2492
2493 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2494 cnt*delay, rc, seq);
2495
2496 /* is this a reply to our command? */
2497 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2498 rc &= FW_MSG_CODE_MASK;
2499 else {
2500 /* FW BUG! */
2501 BNX2X_ERR("FW failed to respond!\n");
2502 bnx2x_fw_dump(bp);
2503 rc = 0;
2504 }
c4ff7cbf 2505 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2506
2507 return rc;
2508}
2509
ec6ba945
VZ		 2510static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2511{
2512#ifdef BCM_CNIC
619c5cb6
VZ		 2513 /* Statistics are not supported for CNIC Clients at the moment */
2514 if (IS_FCOE_FP(fp))
ec6ba945
VZ		 2515 return false;
2516#endif
2517 return true;
2518}
2519
619c5cb6
VZ		 2520void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2521{
2522 if (CHIP_IS_E1x(bp)) {
2523 struct tstorm_eth_function_common_config tcfg = {0};
2524
2525 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2526 }
2527
2528 /* Enable the function in the FW */
2529 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2530 storm_memset_func_en(bp, p->func_id, 1);
2531
2532 /* spq */
2533 if (p->func_flgs & FUNC_FLG_SPQ) {
2534 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2535 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2536 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2537 }
2538}
2539
2540static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2541 struct bnx2x_fastpath *fp,
2542 bool leading)
28912902 2543{
619c5cb6
VZ		 2544 unsigned long flags = 0;
2545
2546 /* PF driver will always initialize the Queue to an ACTIVE state */
2547 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2548
619c5cb6
VZ		 2549 /* calculate other queue flags */
2550 if (IS_MF_SD(bp))
2551 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2552
619c5cb6
VZ		 2553 if (IS_FCOE_FP(fp))
2554 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3
DK		 2555
2556 if (!fp->disable_tpa)
619c5cb6
VZ		 2557 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2558
2559 if (stat_counter_valid(bp, fp)) {
2560 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2561 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2562 }
2563
2564 if (leading) {
2565 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2566 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2567 }
523224a3 2568
619c5cb6
VZ		 2569 /* Always set HW VLAN stripping */
2570 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3
DK		 2571
2572 return flags;
2573}
2574
619c5cb6
VZ		 2575static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2576 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init)
2577{
2578 gen_init->stat_id = bnx2x_stats_id(fp);
2579 gen_init->spcl_id = fp->cl_id;
2580
2581 /* Always use mini-jumbo MTU for FCoE L2 ring */
2582 if (IS_FCOE_FP(fp))
2583 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2584 else
2585 gen_init->mtu = bp->dev->mtu;
2586}
2587
2588static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2589 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2590 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2591{
619c5cb6 2592 u8 max_sge = 0;
523224a3
DK		 2593 u16 sge_sz = 0;
2594 u16 tpa_agg_size = 0;
2595
523224a3
DK		 2596 if (!fp->disable_tpa) {
2597 pause->sge_th_hi = 250;
2598 pause->sge_th_lo = 150;
2599 tpa_agg_size = min_t(u32,
2600 (min_t(u32, 8, MAX_SKB_FRAGS) *
2601 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2602 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2603 SGE_PAGE_SHIFT;
2604 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2605 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2606 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2607 0xffff);
2608 }
2609
2610 /* pause - not for e1 */
2611 if (!CHIP_IS_E1(bp)) {
2612 pause->bd_th_hi = 350;
2613 pause->bd_th_lo = 250;
2614 pause->rcq_th_hi = 350;
2615 pause->rcq_th_lo = 250;
619c5cb6 2616
523224a3
DK		 2617 pause->pri_map = 1;
2618 }
2619
2620 /* rxq setup */
523224a3
DK		 2621 rxq_init->dscr_map = fp->rx_desc_mapping;
2622 rxq_init->sge_map = fp->rx_sge_mapping;
2623 rxq_init->rcq_map = fp->rx_comp_mapping;
2624 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2625
619c5cb6
VZ		 2626 /* This should be a maximum number of data bytes that may be
2627 * placed on the BD (not including paddings).
2628 */
2629 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2630 IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2631
523224a3 2632 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2633 rxq_init->tpa_agg_sz = tpa_agg_size;
2634 rxq_init->sge_buf_sz = sge_sz;
2635 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2636 rxq_init->rss_engine_id = BP_FUNC(bp);
2637
2638 /* Maximum number or simultaneous TPA aggregation for this Queue.
2639 *
2640 * For PF Clients it should be the maximum avaliable number.
2641 * VF driver(s) may want to define it to a smaller value.
2642 */
2643 rxq_init->max_tpa_queues =
2644 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2645 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2646
523224a3
DK		 2647 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2648 rxq_init->fw_sb_id = fp->fw_sb_id;
2649
ec6ba945
VZ		 2650 if (IS_FCOE_FP(fp))
2651 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2652 else
2653 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
523224a3
DK		 2654}
2655
619c5cb6
VZ		 2656static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2657 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init)
523224a3 2658{
523224a3 2659 txq_init->dscr_map = fp->tx_desc_mapping;
523224a3
DK		 2660 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2661 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2662 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2663
619c5cb6
VZ		 2664 /*
2665 * set the tss leading client id for TX classfication ==
2666 * leading RSS client id
2667 */
2668 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2669
ec6ba945
VZ		 2670 if (IS_FCOE_FP(fp)) {
2671 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2672 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2673 }
523224a3
DK		 2674}
2675
8d96286a 2676static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2677{
2678 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2679 struct event_ring_data eq_data = { {0} };
2680 u16 flags;
2681
619c5cb6 2682 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2683 /* reset IGU PF statistics: MSIX + ATTN */
2684 /* PF */
2685 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2686 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2687 (CHIP_MODE_IS_4_PORT(bp) ?
2688 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2689 /* ATTN */
2690 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2691 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2692 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2693 (CHIP_MODE_IS_4_PORT(bp) ?
2694 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2695 }
2696
523224a3
DK		 2697 /* function setup flags */
2698 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2699
619c5cb6
VZ		 2700 /* This flag is relevant for E1x only.
2701 * E2 doesn't have a TPA configuration in a function level.
523224a3 2702 */
619c5cb6 2703 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2704
2705 func_init.func_flgs = flags;
2706 func_init.pf_id = BP_FUNC(bp);
2707 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2708 func_init.spq_map = bp->spq_mapping;
2709 func_init.spq_prod = bp->spq_prod_idx;
2710
2711 bnx2x_func_init(bp, &func_init);
2712
2713 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2714
2715 /*
619c5cb6
VZ		 2716 * Congestion management values depend on the link rate
2717 * There is no active link so initial link rate is set to 10 Gbps.
2718 * When the link comes up The congestion management values are
2719 * re-calculated according to the actual link rate.
2720 */
523224a3
DK		 2721 bp->link_vars.line_speed = SPEED_10000;
2722 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2723
2724 /* Only the PMF sets the HW */
2725 if (bp->port.pmf)
2726 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2727
523224a3
DK		 2728 /* init Event Queue */
2729 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2730 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2731 eq_data.producer = bp->eq_prod;
2732 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2733 eq_data.sb_id = DEF_SB_ID;
2734 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2735}
2736
2737
2738static void bnx2x_e1h_disable(struct bnx2x *bp)
2739{
2740 int port = BP_PORT(bp);
2741
619c5cb6 2742 bnx2x_tx_disable(bp);
523224a3
DK		 2743
2744 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2745}
2746
2747static void bnx2x_e1h_enable(struct bnx2x *bp)
2748{
2749 int port = BP_PORT(bp);
2750
2751 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2752
2753 /* Tx queue should be only reenabled */
2754 netif_tx_wake_all_queues(bp->dev);
2755
2756 /*
2757 * Should not call netif_carrier_on since it will be called if the link
2758 * is up when checking for link state
2759 */
2760}
2761
0793f83f
DK		 2762/* called due to MCP event (on pmf):
2763 * reread new bandwidth configuration
2764 * configure FW
2765 * notify others function about the change
2766 */
2767static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2768{
2769 if (bp->link_vars.link_up) {
2770 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2771 bnx2x_link_sync_notify(bp);
2772 }
2773 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2774}
2775
2776static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2777{
2778 bnx2x_config_mf_bw(bp);
2779 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2780}
2781
523224a3
DK		 2782static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2783{
2784 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2785
2786 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2787
2788 /*
2789 * This is the only place besides the function initialization
2790 * where the bp->flags can change so it is done without any
2791 * locks
2792 */
f2e0899f 2793 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2794 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2795 bp->flags |= MF_FUNC_DIS;
2796
2797 bnx2x_e1h_disable(bp);
2798 } else {
2799 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2800 bp->flags &= ~MF_FUNC_DIS;
2801
2802 bnx2x_e1h_enable(bp);
2803 }
2804 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2805 }
2806 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2807 bnx2x_config_mf_bw(bp);
523224a3
DK		 2808 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2809 }
2810
2811 /* Report results to MCP */
2812 if (dcc_event)
2813 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2814 else
2815 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2816}
2817
2818/* must be called under the spq lock */
2819static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2820{
2821 struct eth_spe *next_spe = bp->spq_prod_bd;
2822
2823 if (bp->spq_prod_bd == bp->spq_last_bd) {
2824 bp->spq_prod_bd = bp->spq;
2825 bp->spq_prod_idx = 0;
2826 DP(NETIF_MSG_TIMER, "end of spq\n");
2827 } else {
2828 bp->spq_prod_bd++;
2829 bp->spq_prod_idx++;
2830 }
2831 return next_spe;
2832}
2833
2834/* must be called under the spq lock */
28912902
MC		 2835static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2836{
2837 int func = BP_FUNC(bp);
2838
2839 /* Make sure that BD data is updated before writing the producer */
2840 wmb();
2841
523224a3 2842 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2843 bp->spq_prod_idx);
28912902
MC		 2844 mmiowb();
2845}
2846
619c5cb6
VZ		 2847/**
2848 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
2849 *
2850 * @cmd: command to check
2851 * @cmd_type: command type
2852 */
2853static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
2854{
2855 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2856 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2857 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2858 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2859 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2860 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
2861 return true;
2862 else
2863 return false;
2864
2865}
2866
2867
2868/**
2869 * bnx2x_sp_post - place a single command on an SP ring
2870 *
2871 * @bp: driver handle
2872 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2873 * @cid: SW CID the command is related to
2874 * @data_hi: command private data address (high 32 bits)
2875 * @data_lo: command private data address (low 32 bits)
2876 * @cmd_type: command type (e.g. NONE, ETH)
2877 *
2878 * SP data is handled as if it's always an address pair, thus data fields are
2879 * not swapped to little endian in upper functions. Instead this function swaps
2880 * data as if it's two u32 fields.
2881 */
9f6c9258 2882int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 2883 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 2884{
28912902 2885 struct eth_spe *spe;
523224a3 2886 u16 type;
619c5cb6 2887 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 2888
a2fbb9ea
ET		 2889#ifdef BNX2X_STOP_ON_ERROR
2890 if (unlikely(bp->panic))
2891 return -EIO;
2892#endif
2893
34f80b04 2894 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 2895
6e30dd4e
VZ		 2896 if (common) {
2897 if (!atomic_read(&bp->eq_spq_left)) {
2898 BNX2X_ERR("BUG! EQ ring full!\n");
2899 spin_unlock_bh(&bp->spq_lock);
2900 bnx2x_panic();
2901 return -EBUSY;
2902 }
2903 } else if (!atomic_read(&bp->cq_spq_left)) {
2904 BNX2X_ERR("BUG! SPQ ring full!\n");
2905 spin_unlock_bh(&bp->spq_lock);
2906 bnx2x_panic();
2907 return -EBUSY;
a2fbb9ea 2908 }
f1410647 2909
28912902
MC		 2910 spe = bnx2x_sp_get_next(bp);
2911
a2fbb9ea 2912 /* CID needs port number to be encoded int it */
28912902 2913 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 2914 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2915 HW_CID(bp, cid));
523224a3 2916
619c5cb6 2917 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 2918
523224a3
DK		 2919 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2920 SPE_HDR_FUNCTION_ID);
a2fbb9ea 2921
523224a3
DK		 2922 spe->hdr.type = cpu_to_le16(type);
2923
2924 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2925 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2926
2927 /* stats ramrod has it's own slot on the spq */
6e30dd4e 2928 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
619c5cb6
VZ		 2929 /*
2930 * It's ok if the actual decrement is issued towards the memory
523224a3
DK		 2931 * somewhere between the spin_lock and spin_unlock. Thus no
2932 * more explict memory barrier is needed.
2933 */
6e30dd4e
VZ		 2934 if (common)
2935 atomic_dec(&bp->eq_spq_left);
2936 else
2937 atomic_dec(&bp->cq_spq_left);
2938 }
2939
a2fbb9ea 2940
cdaa7cb8 2941 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3 2942 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
6e30dd4e 2943 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
cdaa7cb8
VZ		 2944 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2945 (u32)(U64_LO(bp->spq_mapping) +
2946 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
6e30dd4e
VZ		 2947 HW_CID(bp, cid), data_hi, data_lo, type,
2948 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 2949
28912902 2950 bnx2x_sp_prod_update(bp);
34f80b04 2951 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2952 return 0;
2953}
2954
2955/* acquire split MCP access lock register */
4a37fb66 2956static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 2957{
72fd0718 2958 u32 j, val;
34f80b04 2959 int rc = 0;
a2fbb9ea
ET		 2960
2961 might_sleep();
72fd0718 2962 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 2963 val = (1UL << 31);
2964 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2965 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2966 if (val & (1L << 31))
2967 break;
2968
2969 msleep(5);
2970 }
a2fbb9ea 2971 if (!(val & (1L << 31))) {
19680c48 2972 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 2973 rc = -EBUSY;
2974 }
2975
2976 return rc;
2977}
2978
4a37fb66
YG		 2979/* release split MCP access lock register */
2980static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 2981{
72fd0718 2982 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 2983}
2984
523224a3
DK		 2985#define BNX2X_DEF_SB_ATT_IDX 0x0001
2986#define BNX2X_DEF_SB_IDX 0x0002
2987
a2fbb9ea
ET		 2988static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2989{
523224a3 2990 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 2991 u16 rc = 0;
2992
2993 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 2994 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2995 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 2996 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 2997 }
523224a3
DK		 2998
2999 if (bp->def_idx != def_sb->sp_sb.running_index) {
3000 bp->def_idx = def_sb->sp_sb.running_index;
3001 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3002 }
523224a3
DK		 3003
3004 /* Do not reorder: indecies reading should complete before handling */
3005 barrier();
a2fbb9ea
ET		 3006 return rc;
3007}
3008
3009/*
3010 * slow path service functions
3011 */
3012
3013static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3014{
34f80b04 3015 int port = BP_PORT(bp);
a2fbb9ea
ET		 3016 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3017 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3018 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3019 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3020 u32 aeu_mask;
87942b46 3021 u32 nig_mask = 0;
f2e0899f 3022 u32 reg_addr;
a2fbb9ea 3023
a2fbb9ea
ET		 3024 if (bp->attn_state & asserted)
3025 BNX2X_ERR("IGU ERROR\n");
3026
3fcaf2e5
EG		 3027 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3028 aeu_mask = REG_RD(bp, aeu_addr);
3029
a2fbb9ea 3030 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3031 aeu_mask, asserted);
72fd0718 3032 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3033 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3034
3fcaf2e5
EG		 3035 REG_WR(bp, aeu_addr, aeu_mask);
3036 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3037
3fcaf2e5 3038 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3039 bp->attn_state |= asserted;
3fcaf2e5 3040 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3041
3042 if (asserted & ATTN_HARD_WIRED_MASK) {
3043 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3044
a5e9a7cf
EG		 3045 bnx2x_acquire_phy_lock(bp);
3046
877e9aa4 3047 /* save nig interrupt mask */
87942b46 3048 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3049
361c391e
YR		 3050 /* If nig_mask is not set, no need to call the update
3051 * function.
3052 */
3053 if (nig_mask) {
3054 REG_WR(bp, nig_int_mask_addr, 0);
3055
3056 bnx2x_link_attn(bp);
3057 }
a2fbb9ea
ET		 3058
3059 /* handle unicore attn? */
3060 }
3061 if (asserted & ATTN_SW_TIMER_4_FUNC)
3062 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3063
3064 if (asserted & GPIO_2_FUNC)
3065 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3066
3067 if (asserted & GPIO_3_FUNC)
3068 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3069
3070 if (asserted & GPIO_4_FUNC)
3071 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3072
3073 if (port == 0) {
3074 if (asserted & ATTN_GENERAL_ATTN_1) {
3075 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3076 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3077 }
3078 if (asserted & ATTN_GENERAL_ATTN_2) {
3079 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3080 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3081 }
3082 if (asserted & ATTN_GENERAL_ATTN_3) {
3083 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3084 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3085 }
3086 } else {
3087 if (asserted & ATTN_GENERAL_ATTN_4) {
3088 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3089 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3090 }
3091 if (asserted & ATTN_GENERAL_ATTN_5) {
3092 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3094 }
3095 if (asserted & ATTN_GENERAL_ATTN_6) {
3096 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3097 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3098 }
3099 }
3100
3101 } /* if hardwired */
3102
f2e0899f
DK		 3103 if (bp->common.int_block == INT_BLOCK_HC)
3104 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3105 COMMAND_REG_ATTN_BITS_SET);
3106 else
3107 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3108
3109 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3110 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3111 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3112
3113 /* now set back the mask */
a5e9a7cf 3114 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3115 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3116 bnx2x_release_phy_lock(bp);
3117 }
a2fbb9ea
ET		 3118}
3119
fd4ef40d
EG		 3120static inline void bnx2x_fan_failure(struct bnx2x *bp)
3121{
3122 int port = BP_PORT(bp);
b7737c9b 3123 u32 ext_phy_config;
fd4ef40d 3124 /* mark the failure */
b7737c9b
YR		 3125 ext_phy_config =
3126 SHMEM_RD(bp,
3127 dev_info.port_hw_config[port].external_phy_config);
3128
3129 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3130 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3131 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3132 ext_phy_config);
fd4ef40d
EG		 3133
3134 /* log the failure */
cdaa7cb8
VZ		 3135 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3136 " the driver to shutdown the card to prevent permanent"
3137 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 3138}
ab6ad5a4 3139
877e9aa4 3140static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3141{
34f80b04 3142 int port = BP_PORT(bp);
877e9aa4 3143 int reg_offset;
d90d96ba 3144 u32 val;
877e9aa4 3145
34f80b04
EG		 3146 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3147 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3148
34f80b04 3149 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3150
3151 val = REG_RD(bp, reg_offset);
3152 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3153 REG_WR(bp, reg_offset, val);
3154
3155 BNX2X_ERR("SPIO5 hw attention\n");
3156
fd4ef40d 3157 /* Fan failure attention */
d90d96ba 3158 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3159 bnx2x_fan_failure(bp);
877e9aa4 3160 }
34f80b04 3161
589abe3a
EG		 3162 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3163 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3164 bnx2x_acquire_phy_lock(bp);
3165 bnx2x_handle_module_detect_int(&bp->link_params);
3166 bnx2x_release_phy_lock(bp);
3167 }
3168
34f80b04
EG		 3169 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3170
3171 val = REG_RD(bp, reg_offset);
3172 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3173 REG_WR(bp, reg_offset, val);
3174
3175 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3176 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3177 bnx2x_panic();
3178 }
877e9aa4
ET		 3179}
3180
3181static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3182{
3183 u32 val;
3184
0626b899 3185 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3186
3187 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3188 BNX2X_ERR("DB hw attention 0x%x\n", val);
3189 /* DORQ discard attention */
3190 if (val & 0x2)
3191 BNX2X_ERR("FATAL error from DORQ\n");
3192 }
34f80b04
EG		 3193
3194 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3195
3196 int port = BP_PORT(bp);
3197 int reg_offset;
3198
3199 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3200 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3201
3202 val = REG_RD(bp, reg_offset);
3203 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3204 REG_WR(bp, reg_offset, val);
3205
3206 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3207 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3208 bnx2x_panic();
3209 }
877e9aa4
ET		 3210}
3211
3212static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3213{
3214 u32 val;
3215
3216 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3217
3218 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3219 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3220 /* CFC error attention */
3221 if (val & 0x2)
3222 BNX2X_ERR("FATAL error from CFC\n");
3223 }
3224
3225 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3226 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3227 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3228 /* RQ_USDMDP_FIFO_OVERFLOW */
3229 if (val & 0x18000)
3230 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3231
3232 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3233 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3234 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3235 }
877e9aa4 3236 }
34f80b04
EG		 3237
3238 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3239
3240 int port = BP_PORT(bp);
3241 int reg_offset;
3242
3243 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3244 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3245
3246 val = REG_RD(bp, reg_offset);
3247 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3248 REG_WR(bp, reg_offset, val);
3249
3250 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3251 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3252 bnx2x_panic();
3253 }
877e9aa4
ET		 3254}
3255
3256static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3257{
34f80b04
EG		 3258 u32 val;
3259
877e9aa4
ET		 3260 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3261
34f80b04
EG		 3262 if (attn & BNX2X_PMF_LINK_ASSERT) {
3263 int func = BP_FUNC(bp);
3264
3265 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3266 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3267 func_mf_config[BP_ABS_FUNC(bp)].config);
3268 val = SHMEM_RD(bp,
3269 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3270 if (val & DRV_STATUS_DCC_EVENT_MASK)
3271 bnx2x_dcc_event(bp,
3272 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3273
3274 if (val & DRV_STATUS_SET_MF_BW)
3275 bnx2x_set_mf_bw(bp);
3276
2691d51d 3277 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3278 bnx2x_pmf_update(bp);
3279
2ae17f66
VZ		 3280 /* Always call it here: bnx2x_link_report() will
3281 * prevent the link indication duplication.
3282 */
3283 bnx2x__link_status_update(bp);
3284
e4901dde 3285 if (bp->port.pmf &&
785b9b1a
SR		 3286 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3287 bp->dcbx_enabled > 0)
e4901dde
VZ		 3288 /* start dcbx state machine */
3289 bnx2x_dcbx_set_params(bp,
3290 BNX2X_DCBX_STATE_NEG_RECEIVED);
34f80b04 3291 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3292
3293 BNX2X_ERR("MC assert!\n");
3294 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3295 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3296 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3297 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3298 bnx2x_panic();
3299
3300 } else if (attn & BNX2X_MCP_ASSERT) {
3301
3302 BNX2X_ERR("MCP assert!\n");
3303 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3304 bnx2x_fw_dump(bp);
877e9aa4
ET		 3305
3306 } else
3307 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3308 }
3309
3310 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3311 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3312 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3313 val = CHIP_IS_E1(bp) ? 0 :
3314 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3315 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3316 }
3317 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3318 val = CHIP_IS_E1(bp) ? 0 :
3319 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3320 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3321 }
877e9aa4 3322 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3323 }
3324}
3325
72fd0718
VZ		 3326#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3327#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3328#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3329#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3330#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
f85582f8 3331
72fd0718
VZ		 3332/*
3333 * should be run under rtnl lock
3334 */
3335static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3336{
3337 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3338 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3339 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3340 barrier();
3341 mmiowb();
3342}
3343
3344/*
3345 * should be run under rtnl lock
3346 */
3347static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3348{
3349 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3350 val |= (1 << 16);
3351 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3352 barrier();
3353 mmiowb();
3354}
3355
3356/*
3357 * should be run under rtnl lock
3358 */
9f6c9258 3359bool bnx2x_reset_is_done(struct bnx2x *bp)
72fd0718
VZ		 3360{
3361 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3362 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3363 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3364}
3365
3366/*
3367 * should be run under rtnl lock
3368 */
9f6c9258 3369inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3370{
3371 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3372
3373 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3374
3375 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3376 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3377 barrier();
3378 mmiowb();
3379}
3380
3381/*
3382 * should be run under rtnl lock
3383 */
9f6c9258 3384u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3385{
3386 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3387
3388 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3389
3390 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3391 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3392 barrier();
3393 mmiowb();
3394
3395 return val1;
3396}
3397
3398/*
3399 * should be run under rtnl lock
3400 */
3401static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3402{
3403 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3404}
3405
3406static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3407{
3408 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3409 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3410}
3411
3412static inline void _print_next_block(int idx, const char *blk)
3413{
3414 if (idx)
3415 pr_cont(", ");
3416 pr_cont("%s", blk);
3417}
3418
3419static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3420{
3421 int i = 0;
3422 u32 cur_bit = 0;
3423 for (i = 0; sig; i++) {
3424 cur_bit = ((u32)0x1 << i);
3425 if (sig & cur_bit) {
3426 switch (cur_bit) {
3427 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3428 _print_next_block(par_num++, "BRB");
3429 break;
3430 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3431 _print_next_block(par_num++, "PARSER");
3432 break;
3433 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3434 _print_next_block(par_num++, "TSDM");
3435 break;
3436 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3437 _print_next_block(par_num++, "SEARCHER");
3438 break;
3439 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3440 _print_next_block(par_num++, "TSEMI");
3441 break;
3442 }
3443
3444 /* Clear the bit */
3445 sig &= ~cur_bit;
3446 }
3447 }
3448
3449 return par_num;
3450}
3451
3452static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3453{
3454 int i = 0;
3455 u32 cur_bit = 0;
3456 for (i = 0; sig; i++) {
3457 cur_bit = ((u32)0x1 << i);
3458 if (sig & cur_bit) {
3459 switch (cur_bit) {
3460 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3461 _print_next_block(par_num++, "PBCLIENT");
3462 break;
3463 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3464 _print_next_block(par_num++, "QM");
3465 break;
3466 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3467 _print_next_block(par_num++, "XSDM");
3468 break;
3469 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3470 _print_next_block(par_num++, "XSEMI");
3471 break;
3472 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3473 _print_next_block(par_num++, "DOORBELLQ");
3474 break;
3475 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3476 _print_next_block(par_num++, "VAUX PCI CORE");
3477 break;
3478 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3479 _print_next_block(par_num++, "DEBUG");
3480 break;
3481 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3482 _print_next_block(par_num++, "USDM");
3483 break;
3484 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3485 _print_next_block(par_num++, "USEMI");
3486 break;
3487 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3488 _print_next_block(par_num++, "UPB");
3489 break;
3490 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3491 _print_next_block(par_num++, "CSDM");
3492 break;
3493 }
3494
3495 /* Clear the bit */
3496 sig &= ~cur_bit;
3497 }
3498 }
3499
3500 return par_num;
3501}
3502
3503static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3504{
3505 int i = 0;
3506 u32 cur_bit = 0;
3507 for (i = 0; sig; i++) {
3508 cur_bit = ((u32)0x1 << i);
3509 if (sig & cur_bit) {
3510 switch (cur_bit) {
3511 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3512 _print_next_block(par_num++, "CSEMI");
3513 break;
3514 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3515 _print_next_block(par_num++, "PXP");
3516 break;
3517 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3518 _print_next_block(par_num++,
3519 "PXPPCICLOCKCLIENT");
3520 break;
3521 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3522 _print_next_block(par_num++, "CFC");
3523 break;
3524 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3525 _print_next_block(par_num++, "CDU");
3526 break;
3527 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3528 _print_next_block(par_num++, "IGU");
3529 break;
3530 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3531 _print_next_block(par_num++, "MISC");
3532 break;
3533 }
3534
3535 /* Clear the bit */
3536 sig &= ~cur_bit;
3537 }
3538 }
3539
3540 return par_num;
3541}
3542
3543static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3544{
3545 int i = 0;
3546 u32 cur_bit = 0;
3547 for (i = 0; sig; i++) {
3548 cur_bit = ((u32)0x1 << i);
3549 if (sig & cur_bit) {
3550 switch (cur_bit) {
3551 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3552 _print_next_block(par_num++, "MCP ROM");
3553 break;
3554 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3555 _print_next_block(par_num++, "MCP UMP RX");
3556 break;
3557 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3558 _print_next_block(par_num++, "MCP UMP TX");
3559 break;
3560 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3561 _print_next_block(par_num++, "MCP SCPAD");
3562 break;
3563 }
3564
3565 /* Clear the bit */
3566 sig &= ~cur_bit;
3567 }
3568 }
3569
3570 return par_num;
3571}
3572
3573static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3574 u32 sig2, u32 sig3)
3575{
3576 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3577 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3578 int par_num = 0;
3579 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3580 "[0]:0x%08x [1]:0x%08x "
3581 "[2]:0x%08x [3]:0x%08x\n",
3582 sig0 & HW_PRTY_ASSERT_SET_0,
3583 sig1 & HW_PRTY_ASSERT_SET_1,
3584 sig2 & HW_PRTY_ASSERT_SET_2,
3585 sig3 & HW_PRTY_ASSERT_SET_3);
3586 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3587 bp->dev->name);
3588 par_num = bnx2x_print_blocks_with_parity0(
3589 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3590 par_num = bnx2x_print_blocks_with_parity1(
3591 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3592 par_num = bnx2x_print_blocks_with_parity2(
3593 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3594 par_num = bnx2x_print_blocks_with_parity3(
3595 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3596 printk("\n");
3597 return true;
3598 } else
3599 return false;
3600}
3601
9f6c9258 3602bool bnx2x_chk_parity_attn(struct bnx2x *bp)
877e9aa4 3603{
a2fbb9ea 3604 struct attn_route attn;
72fd0718
VZ		 3605 int port = BP_PORT(bp);
3606
3607 attn.sig[0] = REG_RD(bp,
3608 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3609 port*4);
3610 attn.sig[1] = REG_RD(bp,
3611 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3612 port*4);
3613 attn.sig[2] = REG_RD(bp,
3614 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3615 port*4);
3616 attn.sig[3] = REG_RD(bp,
3617 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3618 port*4);
3619
3620 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3621 attn.sig[3]);
3622}
3623
f2e0899f
DK		 3624
3625static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3626{
3627 u32 val;
3628 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3629
3630 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3631 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3632 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3633 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3634 "ADDRESS_ERROR\n");
3635 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3636 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3637 "INCORRECT_RCV_BEHAVIOR\n");
3638 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3639 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3640 "WAS_ERROR_ATTN\n");
3641 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3642 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3643 "VF_LENGTH_VIOLATION_ATTN\n");
3644 if (val &
3645 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3646 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3647 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3648 if (val &
3649 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3650 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3651 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3652 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3653 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3654 "TCPL_ERROR_ATTN\n");
3655 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3656 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3657 "TCPL_IN_TWO_RCBS_ATTN\n");
3658 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3659 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3660 "CSSNOOP_FIFO_OVERFLOW\n");
3661 }
3662 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3663 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3664 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3665 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3666 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3667 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3668 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3669 "_ATC_TCPL_TO_NOT_PEND\n");
3670 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3671 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3672 "ATC_GPA_MULTIPLE_HITS\n");
3673 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3674 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3675 "ATC_RCPL_TO_EMPTY_CNT\n");
3676 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3677 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3678 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3679 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3680 "ATC_IREQ_LESS_THAN_STU\n");
3681 }
3682
3683 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3684 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3685 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3686 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3687 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3688 }
3689
3690}
3691
72fd0718
VZ		 3692static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3693{
3694 struct attn_route attn, *group_mask;
34f80b04 3695 int port = BP_PORT(bp);
877e9aa4 3696 int index;
a2fbb9ea
ET		 3697 u32 reg_addr;
3698 u32 val;
3fcaf2e5 3699 u32 aeu_mask;
a2fbb9ea
ET		 3700
3701 /* need to take HW lock because MCP or other port might also
3702 try to handle this event */
4a37fb66 3703 bnx2x_acquire_alr(bp);
a2fbb9ea 3704
4a33bc03 3705 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
72fd0718
VZ		 3706 bp->recovery_state = BNX2X_RECOVERY_INIT;
3707 bnx2x_set_reset_in_progress(bp);
3708 schedule_delayed_work(&bp->reset_task, 0);
3709 /* Disable HW interrupts */
3710 bnx2x_int_disable(bp);
3711 bnx2x_release_alr(bp);
3712 /* In case of parity errors don't handle attentions so that
3713 * other function would "see" parity errors.
3714 */
3715 return;
3716 }
3717
a2fbb9ea
ET		 3718 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3719 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3720 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3721 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 3722 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 3723 attn.sig[4] =
3724 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3725 else
3726 attn.sig[4] = 0;
3727
3728 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3729 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 3730
3731 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3732 if (deasserted & (1 << index)) {
72fd0718 3733 group_mask = &bp->attn_group[index];
a2fbb9ea 3734
f2e0899f
DK		 3735 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3736 "%08x %08x %08x\n",
3737 index,
3738 group_mask->sig[0], group_mask->sig[1],
3739 group_mask->sig[2], group_mask->sig[3],
3740 group_mask->sig[4]);
a2fbb9ea 3741
f2e0899f
DK		 3742 bnx2x_attn_int_deasserted4(bp,
3743 attn.sig[4] & group_mask->sig[4]);
877e9aa4 3744 bnx2x_attn_int_deasserted3(bp,
72fd0718 3745 attn.sig[3] & group_mask->sig[3]);
877e9aa4 3746 bnx2x_attn_int_deasserted1(bp,
72fd0718 3747 attn.sig[1] & group_mask->sig[1]);
877e9aa4 3748 bnx2x_attn_int_deasserted2(bp,
72fd0718 3749 attn.sig[2] & group_mask->sig[2]);
877e9aa4 3750 bnx2x_attn_int_deasserted0(bp,
72fd0718 3751 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 3752 }
3753 }
3754
4a37fb66 3755 bnx2x_release_alr(bp);
a2fbb9ea 3756
f2e0899f
DK		 3757 if (bp->common.int_block == INT_BLOCK_HC)
3758 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3759 COMMAND_REG_ATTN_BITS_CLR);
3760 else
3761 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 3762
3763 val = ~deasserted;
f2e0899f
DK		 3764 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3765 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 3766 REG_WR(bp, reg_addr, val);
a2fbb9ea 3767
a2fbb9ea 3768 if (~bp->attn_state & deasserted)
3fcaf2e5 3769 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 3770
3771 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3772 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3773
3fcaf2e5
EG		 3774 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3775 aeu_mask = REG_RD(bp, reg_addr);
3776
3777 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3778 aeu_mask, deasserted);
72fd0718 3779 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 3780 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3781
3fcaf2e5
EG		 3782 REG_WR(bp, reg_addr, aeu_mask);
3783 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 3784
3785 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3786 bp->attn_state &= ~deasserted;
3787 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3788}
3789
3790static void bnx2x_attn_int(struct bnx2x *bp)
3791{
3792 /* read local copy of bits */
68d59484
EG		 3793 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3794 attn_bits);
3795 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3796 attn_bits_ack);
a2fbb9ea
ET		 3797 u32 attn_state = bp->attn_state;
3798
3799 /* look for changed bits */
3800 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3801 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3802
3803 DP(NETIF_MSG_HW,
3804 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3805 attn_bits, attn_ack, asserted, deasserted);
3806
3807 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 3808 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 3809
3810 /* handle bits that were raised */
3811 if (asserted)
3812 bnx2x_attn_int_asserted(bp, asserted);
3813
3814 if (deasserted)
3815 bnx2x_attn_int_deasserted(bp, deasserted);
3816}
3817
619c5cb6
VZ		 3818void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
3819 u16 index, u8 op, u8 update)
3820{
3821 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
3822
3823 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
3824 igu_addr);
3825}
3826
523224a3
DK		 3827static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3828{
3829 /* No memory barriers */
3830 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3831 mmiowb(); /* keep prod updates ordered */
3832}
3833
3834#ifdef BCM_CNIC
3835static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3836 union event_ring_elem *elem)
3837{
619c5cb6
VZ		 3838 u8 err = elem->message.error;
3839
523224a3 3840 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 3841 (cid < bp->cnic_eth_dev.starting_cid &&
3842 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 3843 return 1;
3844
3845 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3846
619c5cb6
VZ		 3847 if (unlikely(err)) {
3848
523224a3
DK		 3849 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3850 cid);
3851 bnx2x_panic_dump(bp);
3852 }
619c5cb6 3853 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 3854 return 0;
3855}
3856#endif
3857
619c5cb6
VZ		 3858static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
3859{
3860 struct bnx2x_mcast_ramrod_params rparam;
3861 int rc;
3862
3863 memset(&rparam, 0, sizeof(rparam));
3864
3865 rparam.mcast_obj = &bp->mcast_obj;
3866
3867 netif_addr_lock_bh(bp->dev);
3868
3869 /* Clear pending state for the last command */
3870 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
3871
3872 /* If there are pending mcast commands - send them */
3873 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
3874 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
3875 if (rc < 0)
3876 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
3877 rc);
3878 }
3879
3880 netif_addr_unlock_bh(bp->dev);
3881}
3882
3883static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
3884 union event_ring_elem *elem)
3885{
3886 unsigned long ramrod_flags = 0;
3887 int rc = 0;
3888 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
3889 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
3890
3891 /* Always push next commands out, don't wait here */
3892 __set_bit(RAMROD_CONT, &ramrod_flags);
3893
3894 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
3895 case BNX2X_FILTER_MAC_PENDING:
3896#ifdef BCM_CNIC
3897 if (cid == BNX2X_ISCSI_ETH_CID)
3898 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
3899 else
3900#endif
3901 vlan_mac_obj = &bp->fp[cid].mac_obj;
3902
3903 break;
3904 vlan_mac_obj = &bp->fp[cid].mac_obj;
3905
3906 case BNX2X_FILTER_MCAST_PENDING:
3907 /* This is only relevant for 57710 where multicast MACs are
3908 * configured as unicast MACs using the same ramrod.
3909 */
3910 bnx2x_handle_mcast_eqe(bp);
3911 return;
3912 default:
3913 BNX2X_ERR("Unsupported classification command: %d\n",
3914 elem->message.data.eth_event.echo);
3915 return;
3916 }
3917
3918 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
3919
3920 if (rc < 0)
3921 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
3922 else if (rc > 0)
3923 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
3924
3925}
3926
3927#ifdef BCM_CNIC
3928static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
3929#endif
3930
3931static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
3932{
3933 netif_addr_lock_bh(bp->dev);
3934
3935 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
3936
3937 /* Send rx_mode command again if was requested */
3938 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
3939 bnx2x_set_storm_rx_mode(bp);
3940#ifdef BCM_CNIC
3941 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
3942 &bp->sp_state))
3943 bnx2x_set_iscsi_eth_rx_mode(bp, true);
3944 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
3945 &bp->sp_state))
3946 bnx2x_set_iscsi_eth_rx_mode(bp, false);
3947#endif
3948
3949 netif_addr_unlock_bh(bp->dev);
3950}
3951
3952static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
3953 struct bnx2x *bp, u32 cid)
3954{
3955#ifdef BCM_CNIC
3956 if (cid == BNX2X_FCOE_ETH_CID)
3957 return &bnx2x_fcoe(bp, q_obj);
3958 else
3959#endif
3960 return &bnx2x_fp(bp, cid, q_obj);
3961}
3962
523224a3
DK		 3963static void bnx2x_eq_int(struct bnx2x *bp)
3964{
3965 u16 hw_cons, sw_cons, sw_prod;
3966 union event_ring_elem *elem;
3967 u32 cid;
3968 u8 opcode;
3969 int spqe_cnt = 0;
619c5cb6
VZ		 3970 struct bnx2x_queue_sp_obj *q_obj;
3971 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
3972 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 3973
3974 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3975
3976 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3977 * when we get the the next-page we nned to adjust so the loop
3978 * condition below will be met. The next element is the size of a
3979 * regular element and hence incrementing by 1
3980 */
3981 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3982 hw_cons++;
3983
25985edc 3984 /* This function may never run in parallel with itself for a
523224a3
DK		 3985 * specific bp, thus there is no need in "paired" read memory
3986 * barrier here.
3987 */
3988 sw_cons = bp->eq_cons;
3989 sw_prod = bp->eq_prod;
3990
6e30dd4e
VZ		 3991 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3992 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 3993
3994 for (; sw_cons != hw_cons;
3995 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3996
3997
3998 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3999
4000 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4001 opcode = elem->message.opcode;
4002
4003
4004 /* handle eq element */
4005 switch (opcode) {
4006 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4007 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4008 bp->stats_comp++);
523224a3
DK		 4009 /* nothing to do with stats comp */
4010 continue;
4011
4012 case EVENT_RING_OPCODE_CFC_DEL:
4013 /* handle according to cid range */
4014 /*
4015 * we may want to verify here that the bp state is
4016 * HALTING
4017 */
4018 DP(NETIF_MSG_IFDOWN,
4019 "got delete ramrod for MULTI[%d]\n", cid);
4020#ifdef BCM_CNIC
4021 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4022 goto next_spqe;
4023#endif
619c5cb6
VZ		 4024 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4025
4026 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4027 break;
4028
4029
523224a3
DK		 4030
4031 goto next_spqe;
e4901dde
VZ		 4032
4033 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4034 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
4035 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4036 goto next_spqe;
619c5cb6 4037
e4901dde
VZ		 4038 case EVENT_RING_OPCODE_START_TRAFFIC:
4039 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
4040 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4041 goto next_spqe;
619c5cb6
VZ		 4042 case EVENT_RING_OPCODE_FUNCTION_START:
4043 DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
4044 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4045 break;
4046
4047 goto next_spqe;
4048
4049 case EVENT_RING_OPCODE_FUNCTION_STOP:
4050 DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
4051 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4052 break;
4053
4054 goto next_spqe;
523224a3
DK		 4055 }
4056
4057 switch (opcode | bp->state) {
619c5cb6
VZ		 4058 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4059 BNX2X_STATE_OPEN):
4060 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4061 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4062 cid = elem->message.data.eth_event.echo &
4063 BNX2X_SWCID_MASK;
4064 DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
4065 cid);
4066 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4067 break;
4068
619c5cb6
VZ		 4069 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4070 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4071 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4072 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4073 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4074 BNX2X_STATE_OPEN):
4075 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4076 BNX2X_STATE_DIAG):
4077 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4078 BNX2X_STATE_CLOSING_WAIT4_HALT):
4079 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
4080 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4081 break;
4082
619c5cb6
VZ		 4083 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4084 BNX2X_STATE_OPEN):
4085 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4086 BNX2X_STATE_DIAG):
4087 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4088 BNX2X_STATE_CLOSING_WAIT4_HALT):
4089 DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
4090 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4091 break;
4092
619c5cb6
VZ		 4093 case (EVENT_RING_OPCODE_FILTERS_RULES |
4094 BNX2X_STATE_OPEN):
4095 case (EVENT_RING_OPCODE_FILTERS_RULES |
4096 BNX2X_STATE_DIAG):
4097 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4098 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4099 DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
4100 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4101 break;
4102 default:
4103 /* unknown event log error and continue */
619c5cb6
VZ		 4104 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4105 elem->message.opcode, bp->state);
523224a3
DK		 4106 }
4107next_spqe:
4108 spqe_cnt++;
4109 } /* for */
4110
8fe23fbd 4111 smp_mb__before_atomic_inc();
6e30dd4e 4112 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4113
4114 bp->eq_cons = sw_cons;
4115 bp->eq_prod = sw_prod;
4116 /* Make sure that above mem writes were issued towards the memory */
4117 smp_wmb();
4118
4119 /* update producer */
4120 bnx2x_update_eq_prod(bp, bp->eq_prod);
4121}
4122
a2fbb9ea
ET		 4123static void bnx2x_sp_task(struct work_struct *work)
4124{
1cf167f2 4125 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4126 u16 status;
4127
a2fbb9ea 4128 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4129/* if (status == 0) */
4130/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4131
cdaa7cb8 4132 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4133
877e9aa4 4134 /* HW attentions */
523224a3 4135 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4136 bnx2x_attn_int(bp);
523224a3 4137 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4138 }
4139
523224a3
DK		 4140 /* SP events: STAT_QUERY and others */
4141 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4142#ifdef BCM_CNIC
4143 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4144
ec6ba945
VZ		 4145 if ((!NO_FCOE(bp)) &&
4146 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
4147 napi_schedule(&bnx2x_fcoe(bp, napi));
4148#endif
523224a3
DK		 4149 /* Handle EQ completions */
4150 bnx2x_eq_int(bp);
4151
4152 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4153 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4154
4155 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4156 }
4157
4158 if (unlikely(status))
4159 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4160 status);
a2fbb9ea 4161
523224a3
DK		 4162 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4163 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4164}
4165
9f6c9258 4166irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4167{
4168 struct net_device *dev = dev_instance;
4169 struct bnx2x *bp = netdev_priv(dev);
4170
523224a3
DK		 4171 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4172 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4173
4174#ifdef BNX2X_STOP_ON_ERROR
4175 if (unlikely(bp->panic))
4176 return IRQ_HANDLED;
4177#endif
4178
993ac7b5
MC		 4179#ifdef BCM_CNIC
4180 {
4181 struct cnic_ops *c_ops;
4182
4183 rcu_read_lock();
4184 c_ops = rcu_dereference(bp->cnic_ops);
4185 if (c_ops)
4186 c_ops->cnic_handler(bp->cnic_data, NULL);
4187 rcu_read_unlock();
4188 }
4189#endif
1cf167f2 4190 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4191
4192 return IRQ_HANDLED;
4193}
4194
4195/* end of slow path */
4196
619c5cb6
VZ		 4197
4198void bnx2x_drv_pulse(struct bnx2x *bp)
4199{
4200 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4201 bp->fw_drv_pulse_wr_seq);
4202}
4203
4204
a2fbb9ea
ET		 4205static void bnx2x_timer(unsigned long data)
4206{
4207 struct bnx2x *bp = (struct bnx2x *) data;
4208
4209 if (!netif_running(bp->dev))
4210 return;
4211
a2fbb9ea
ET		 4212 if (poll) {
4213 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4214
7961f791 4215 bnx2x_tx_int(fp);
b8ee8328 4216 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4217 }
4218
34f80b04 4219 if (!BP_NOMCP(bp)) {
f2e0899f 4220 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4221 u32 drv_pulse;
4222 u32 mcp_pulse;
4223
4224 ++bp->fw_drv_pulse_wr_seq;
4225 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4226 /* TBD - add SYSTEM_TIME */
4227 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4228 bnx2x_drv_pulse(bp);
a2fbb9ea 4229
f2e0899f 4230 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4231 MCP_PULSE_SEQ_MASK);
4232 /* The delta between driver pulse and mcp response
4233 * should be 1 (before mcp response) or 0 (after mcp response)
4234 */
4235 if ((drv_pulse != mcp_pulse) &&
4236 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4237 /* someone lost a heartbeat... */
4238 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4239 drv_pulse, mcp_pulse);
4240 }
4241 }
4242
f34d28ea 4243 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4244 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4245
a2fbb9ea
ET		 4246 mod_timer(&bp->timer, jiffies + bp->current_interval);
4247}
4248
4249/* end of Statistics */
4250
4251/* nic init */
4252
4253/*
4254 * nic init service functions
4255 */
4256
523224a3 4257static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4258{
523224a3
DK		 4259 u32 i;
4260 if (!(len%4) && !(addr%4))
4261 for (i = 0; i < len; i += 4)
4262 REG_WR(bp, addr + i, fill);
4263 else
4264 for (i = 0; i < len; i++)
4265 REG_WR8(bp, addr + i, fill);
34f80b04 4266
34f80b04
EG		 4267}
4268
523224a3
DK		 4269/* helper: writes FP SP data to FW - data_size in dwords */
4270static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4271 int fw_sb_id,
4272 u32 *sb_data_p,
4273 u32 data_size)
34f80b04 4274{
a2fbb9ea 4275 int index;
523224a3
DK		 4276 for (index = 0; index < data_size; index++)
4277 REG_WR(bp, BAR_CSTRORM_INTMEM +
4278 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4279 sizeof(u32)*index,
4280 *(sb_data_p + index));
4281}
a2fbb9ea 4282
523224a3
DK		 4283static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4284{
4285 u32 *sb_data_p;
4286 u32 data_size = 0;
f2e0899f 4287 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4288 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4289
523224a3 4290 /* disable the function first */
619c5cb6 4291 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4292 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4293 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4294 sb_data_e2.common.p_func.vf_valid = false;
4295 sb_data_p = (u32 *)&sb_data_e2;
4296 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4297 } else {
4298 memset(&sb_data_e1x, 0,
4299 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4300 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4301 sb_data_e1x.common.p_func.vf_valid = false;
4302 sb_data_p = (u32 *)&sb_data_e1x;
4303 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4304 }
523224a3 4305 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4306
523224a3
DK		 4307 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4308 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4309 CSTORM_STATUS_BLOCK_SIZE);
4310 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4311 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4312 CSTORM_SYNC_BLOCK_SIZE);
4313}
34f80b04 4314
523224a3
DK		 4315/* helper: writes SP SB data to FW */
4316static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4317 struct hc_sp_status_block_data *sp_sb_data)
4318{
4319 int func = BP_FUNC(bp);
4320 int i;
4321 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4322 REG_WR(bp, BAR_CSTRORM_INTMEM +
4323 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4324 i*sizeof(u32),
4325 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4326}
4327
523224a3 4328static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4329{
4330 int func = BP_FUNC(bp);
523224a3
DK		 4331 struct hc_sp_status_block_data sp_sb_data;
4332 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4333
619c5cb6 4334 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4335 sp_sb_data.p_func.vf_valid = false;
4336
4337 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4338
4339 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4340 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4341 CSTORM_SP_STATUS_BLOCK_SIZE);
4342 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4343 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4344 CSTORM_SP_SYNC_BLOCK_SIZE);
4345
4346}
4347
4348
4349static inline
4350void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4351 int igu_sb_id, int igu_seg_id)
4352{
4353 hc_sm->igu_sb_id = igu_sb_id;
4354 hc_sm->igu_seg_id = igu_seg_id;
4355 hc_sm->timer_value = 0xFF;
4356 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4357}
4358
8d96286a 4359static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4360 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4361{
523224a3
DK		 4362 int igu_seg_id;
4363
f2e0899f 4364 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4365 struct hc_status_block_data_e1x sb_data_e1x;
4366 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4367 int data_size;
4368 u32 *sb_data_p;
4369
f2e0899f
DK		 4370 if (CHIP_INT_MODE_IS_BC(bp))
4371 igu_seg_id = HC_SEG_ACCESS_NORM;
4372 else
4373 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4374
4375 bnx2x_zero_fp_sb(bp, fw_sb_id);
4376
619c5cb6 4377 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4378 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4379 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 4380 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4381 sb_data_e2.common.p_func.vf_id = vfid;
4382 sb_data_e2.common.p_func.vf_valid = vf_valid;
4383 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4384 sb_data_e2.common.same_igu_sb_1b = true;
4385 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4386 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4387 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4388 sb_data_p = (u32 *)&sb_data_e2;
4389 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4390 } else {
4391 memset(&sb_data_e1x, 0,
4392 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4393 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 4394 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4395 sb_data_e1x.common.p_func.vf_id = 0xff;
4396 sb_data_e1x.common.p_func.vf_valid = false;
4397 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4398 sb_data_e1x.common.same_igu_sb_1b = true;
4399 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4400 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4401 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4402 sb_data_p = (u32 *)&sb_data_e1x;
4403 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4404 }
523224a3
DK		 4405
4406 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4407 igu_sb_id, igu_seg_id);
4408 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4409 igu_sb_id, igu_seg_id);
4410
4411 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4412
4413 /* write indecies to HW */
4414 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4415}
4416
619c5cb6 4417static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 4418 u16 tx_usec, u16 rx_usec)
4419{
4420 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4421 false, rx_usec);
4422 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4423 false, tx_usec);
4424}
f2e0899f 4425
523224a3
DK		 4426static void bnx2x_init_def_sb(struct bnx2x *bp)
4427{
4428 struct host_sp_status_block *def_sb = bp->def_status_blk;
4429 dma_addr_t mapping = bp->def_status_blk_mapping;
4430 int igu_sp_sb_index;
4431 int igu_seg_id;
34f80b04
EG		 4432 int port = BP_PORT(bp);
4433 int func = BP_FUNC(bp);
523224a3 4434 int reg_offset;
a2fbb9ea 4435 u64 section;
523224a3
DK		 4436 int index;
4437 struct hc_sp_status_block_data sp_sb_data;
4438 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4439
f2e0899f
DK		 4440 if (CHIP_INT_MODE_IS_BC(bp)) {
4441 igu_sp_sb_index = DEF_SB_IGU_ID;
4442 igu_seg_id = HC_SEG_ACCESS_DEF;
4443 } else {
4444 igu_sp_sb_index = bp->igu_dsb_id;
4445 igu_seg_id = IGU_SEG_ACCESS_DEF;
4446 }
a2fbb9ea
ET		 4447
4448 /* ATTN */
523224a3 4449 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4450 atten_status_block);
523224a3 4451 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4452
49d66772
ET		 4453 bp->attn_state = 0;
4454
a2fbb9ea
ET		 4455 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4456 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4457 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4458 int sindex;
4459 /* take care of sig[0]..sig[4] */
4460 for (sindex = 0; sindex < 4; sindex++)
4461 bp->attn_group[index].sig[sindex] =
4462 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 4463
619c5cb6 4464 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4465 /*
4466 * enable5 is separate from the rest of the registers,
4467 * and therefore the address skip is 4
4468 * and not 16 between the different groups
4469 */
4470 bp->attn_group[index].sig[4] = REG_RD(bp,
4471 reg_offset + 0x10 + 0x4*index);
4472 else
4473 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4474 }
4475
f2e0899f
DK		 4476 if (bp->common.int_block == INT_BLOCK_HC) {
4477 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4478 HC_REG_ATTN_MSG0_ADDR_L);
4479
4480 REG_WR(bp, reg_offset, U64_LO(section));
4481 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 4482 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4483 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4484 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4485 }
a2fbb9ea 4486
523224a3
DK		 4487 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4488 sp_sb);
a2fbb9ea 4489
523224a3 4490 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4491
619c5cb6 4492 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 4493 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4494 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4495 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4496 sp_sb_data.igu_seg_id = igu_seg_id;
4497 sp_sb_data.p_func.pf_id = func;
f2e0899f 4498 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4499 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4500
523224a3 4501 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4502
523224a3 4503 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4504}
4505
9f6c9258 4506void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4507{
a2fbb9ea
ET		 4508 int i;
4509
ec6ba945 4510 for_each_eth_queue(bp, i)
523224a3 4511 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4512 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4513}
4514
a2fbb9ea
ET		 4515static void bnx2x_init_sp_ring(struct bnx2x *bp)
4516{
a2fbb9ea 4517 spin_lock_init(&bp->spq_lock);
6e30dd4e 4518 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4519
a2fbb9ea 4520 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4521 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4522 bp->spq_prod_bd = bp->spq;
4523 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4524}
4525
523224a3 4526static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4527{
4528 int i;
523224a3
DK		 4529 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4530 union event_ring_elem *elem =
4531 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4532
523224a3
DK		 4533 elem->next_page.addr.hi =
4534 cpu_to_le32(U64_HI(bp->eq_mapping +
4535 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4536 elem->next_page.addr.lo =
4537 cpu_to_le32(U64_LO(bp->eq_mapping +
4538 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4539 }
523224a3
DK		 4540 bp->eq_cons = 0;
4541 bp->eq_prod = NUM_EQ_DESC;
4542 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 4543 /* we want a warning message before it gets rought... */
4544 atomic_set(&bp->eq_spq_left,
4545 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 4546}
4547
619c5cb6
VZ		 4548
4549/* called with netif_addr_lock_bh() */
4550void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
4551 unsigned long rx_mode_flags,
4552 unsigned long rx_accept_flags,
4553 unsigned long tx_accept_flags,
4554 unsigned long ramrod_flags)
ab532cf3 4555{
619c5cb6
VZ		 4556 struct bnx2x_rx_mode_ramrod_params ramrod_param;
4557 int rc;
4558
4559 memset(&ramrod_param, 0, sizeof(ramrod_param));
4560
4561 /* Prepare ramrod parameters */
4562 ramrod_param.cid = 0;
4563 ramrod_param.cl_id = cl_id;
4564 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
4565 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 4566
619c5cb6
VZ		 4567 ramrod_param.pstate = &bp->sp_state;
4568 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 4569
619c5cb6
VZ		 4570 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
4571 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
4572
4573 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4574
4575 ramrod_param.ramrod_flags = ramrod_flags;
4576 ramrod_param.rx_mode_flags = rx_mode_flags;
4577
4578 ramrod_param.rx_accept_flags = rx_accept_flags;
4579 ramrod_param.tx_accept_flags = tx_accept_flags;
4580
4581 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
4582 if (rc < 0) {
4583 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
4584 return;
4585 }
a2fbb9ea
ET		 4586}
4587
619c5cb6
VZ		 4588/* called with netif_addr_lock_bh() */
4589void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 4590{
619c5cb6
VZ		 4591 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
4592 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 4593
619c5cb6
VZ		 4594#ifdef BCM_CNIC
4595 if (!NO_FCOE(bp))
4596
4597 /* Configure rx_mode of FCoE Queue */
4598 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
4599#endif
4600
4601 switch (bp->rx_mode) {
4602 case BNX2X_RX_MODE_NONE:
4603 /*
4604 * 'drop all' supersedes any accept flags that may have been
4605 * passed to the function.
4606 */
4607 break;
4608 case BNX2X_RX_MODE_NORMAL:
4609 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4610 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
4611 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4612
4613 /* internal switching mode */
4614 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4615 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
4616 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4617
4618 break;
4619 case BNX2X_RX_MODE_ALLMULTI:
4620 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4621 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
4622 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4623
4624 /* internal switching mode */
4625 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4626 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
4627 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4628
4629 break;
4630 case BNX2X_RX_MODE_PROMISC:
4631 /* According to deffinition of SI mode, iface in promisc mode
4632 * should receive matched and unmatched (in resolution of port)
4633 * unicast packets.
4634 */
4635 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
4636 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4637 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
4638 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4639
4640 /* internal switching mode */
4641 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
4642 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4643
4644 if (IS_MF_SI(bp))
4645 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
4646 else
4647 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4648
4649 break;
4650 default:
4651 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
4652 return;
4653 }
de832a55 4654
619c5cb6
VZ		 4655 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
4656 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
4657 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 4658 }
4659
619c5cb6
VZ		 4660 __set_bit(RAMROD_RX, &ramrod_flags);
4661 __set_bit(RAMROD_TX, &ramrod_flags);
4662
4663 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
4664 tx_accept_flags, ramrod_flags);
4665}
4666
4667static void bnx2x_init_internal_common(struct bnx2x *bp)
4668{
4669 int i;
4670
0793f83f
DK		 4671 if (IS_MF_SI(bp))
4672 /*
4673 * In switch independent mode, the TSTORM needs to accept
4674 * packets that failed classification, since approximate match
4675 * mac addresses aren't written to NIG LLH
4676 */
4677 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4678 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 4679 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
4680 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4681 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 4682
523224a3
DK		 4683 /* Zero this manually as its initialization is
4684 currently missing in the initTool */
4685 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 4686 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 4687 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 4688 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4689 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4690 CHIP_INT_MODE_IS_BC(bp) ?
4691 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4692 }
523224a3 4693}
8a1c38d1 4694
471de716
EG		 4695static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4696{
4697 switch (load_code) {
4698 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 4699 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 4700 bnx2x_init_internal_common(bp);
4701 /* no break */
4702
4703 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 4704 /* nothing to do */
471de716
EG		 4705 /* no break */
4706
4707 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 4708 /* internal memory per function is
4709 initialized inside bnx2x_pf_init */
471de716
EG		 4710 break;
4711
4712 default:
4713 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4714 break;
4715 }
4716}
4717
619c5cb6 4718static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 4719{
619c5cb6
VZ		 4720 return fp->bp->igu_base_sb + fp->index + CNIC_CONTEXT_USE;
4721}
523224a3 4722
619c5cb6
VZ		 4723static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
4724{
4725 return fp->bp->base_fw_ndsb + fp->index + CNIC_CONTEXT_USE;
4726}
4727
4728static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
4729{
4730 if (CHIP_IS_E1x(fp->bp))
4731 return BP_L_ID(fp->bp) + fp->index;
4732 else /* We want Client ID to be the same as IGU SB ID for 57712 */
4733 return bnx2x_fp_igu_sb_id(fp);
4734}
4735
4736static void bnx2x_init_fp(struct bnx2x *bp, int fp_idx)
4737{
4738 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4739 unsigned long q_type = 0;
523224a3 4740
b3b83c3f 4741 fp->cid = fp_idx;
619c5cb6
VZ		 4742 fp->cl_id = bnx2x_fp_cl_id(fp);
4743 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
4744 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 4745 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 4746 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4747
523224a3 4748 /* init shortcut */
619c5cb6 4749 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 4750 /* Setup SB indicies */
4751 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4752 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4753
619c5cb6
VZ		 4754 /* Configure Queue State object */
4755 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
4756 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
4757 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, fp->cid, BP_FUNC(bp),
4758 bnx2x_sp(bp, q_rdata), bnx2x_sp_mapping(bp, q_rdata),
4759 q_type);
4760
4761 /**
4762 * Configure classification DBs: Always enable Tx switching
4763 */
4764 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
4765
523224a3
DK		 4766 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4767 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 4768 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 4769 fp->igu_sb_id);
4770 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4771 fp->fw_sb_id, fp->igu_sb_id);
4772
4773 bnx2x_update_fpsb_idx(fp);
4774}
4775
9f6c9258 4776void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 4777{
4778 int i;
4779
ec6ba945 4780 for_each_eth_queue(bp, i)
619c5cb6 4781 bnx2x_init_fp(bp, i);
37b091ba 4782#ifdef BCM_CNIC
ec6ba945
VZ		 4783 if (!NO_FCOE(bp))
4784 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 4785
4786 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4787 BNX2X_VF_ID_INVALID, false,
619c5cb6 4788 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 4789
37b091ba 4790#endif
a2fbb9ea 4791
020c7e3f
YR		 4792 /* Initialize MOD_ABS interrupts */
4793 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
4794 bp->common.shmem_base, bp->common.shmem2_base,
4795 BP_PORT(bp));
16119785
EG		 4796 /* ensure status block indices were read */
4797 rmb();
4798
523224a3 4799 bnx2x_init_def_sb(bp);
5c862848 4800 bnx2x_update_dsb_idx(bp);
a2fbb9ea 4801 bnx2x_init_rx_rings(bp);
523224a3 4802 bnx2x_init_tx_rings(bp);
a2fbb9ea 4803 bnx2x_init_sp_ring(bp);
523224a3 4804 bnx2x_init_eq_ring(bp);
471de716 4805 bnx2x_init_internal(bp, load_code);
523224a3 4806 bnx2x_pf_init(bp);
0ef00459
EG		 4807 bnx2x_stats_init(bp);
4808
0ef00459
EG		 4809 /* flush all before enabling interrupts */
4810 mb();
4811 mmiowb();
4812
615f8fd9 4813 bnx2x_int_enable(bp);
eb8da205
EG		 4814
4815 /* Check for SPIO5 */
4816 bnx2x_attn_int_deasserted0(bp,
4817 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4818 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 4819}
4820
4821/* end of nic init */
4822
4823/*
4824 * gzip service functions
4825 */
4826
4827static int bnx2x_gunzip_init(struct bnx2x *bp)
4828{
1a983142
FT		 4829 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4830 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 4831 if (bp->gunzip_buf == NULL)
4832 goto gunzip_nomem1;
4833
4834 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4835 if (bp->strm == NULL)
4836 goto gunzip_nomem2;
4837
4838 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4839 GFP_KERNEL);
4840 if (bp->strm->workspace == NULL)
4841 goto gunzip_nomem3;
4842
4843 return 0;
4844
4845gunzip_nomem3:
4846 kfree(bp->strm);
4847 bp->strm = NULL;
4848
4849gunzip_nomem2:
1a983142
FT		 4850 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4851 bp->gunzip_mapping);
a2fbb9ea
ET		 4852 bp->gunzip_buf = NULL;
4853
4854gunzip_nomem1:
cdaa7cb8
VZ		 4855 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4856 " un-compression\n");
a2fbb9ea
ET		 4857 return -ENOMEM;
4858}
4859
4860static void bnx2x_gunzip_end(struct bnx2x *bp)
4861{
b3b83c3f
DK		 4862 if (bp->strm) {
4863 kfree(bp->strm->workspace);
4864 kfree(bp->strm);
4865 bp->strm = NULL;
4866 }
a2fbb9ea
ET		 4867
4868 if (bp->gunzip_buf) {
1a983142
FT		 4869 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4870 bp->gunzip_mapping);
a2fbb9ea
ET		 4871 bp->gunzip_buf = NULL;
4872 }
4873}
4874
94a78b79 4875static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 4876{
4877 int n, rc;
4878
4879 /* check gzip header */
94a78b79
VZ		 4880 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4881 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 4882 return -EINVAL;
94a78b79 4883 }
a2fbb9ea
ET		 4884
4885 n = 10;
4886
34f80b04 4887#define FNAME 0x8
a2fbb9ea
ET		 4888
4889 if (zbuf[3] & FNAME)
4890 while ((zbuf[n++] != 0) && (n < len));
4891
94a78b79 4892 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 4893 bp->strm->avail_in = len - n;
4894 bp->strm->next_out = bp->gunzip_buf;
4895 bp->strm->avail_out = FW_BUF_SIZE;
4896
4897 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4898 if (rc != Z_OK)
4899 return rc;
4900
4901 rc = zlib_inflate(bp->strm, Z_FINISH);
4902 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 4903 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4904 bp->strm->msg);
a2fbb9ea
ET		 4905
4906 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4907 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 4908 netdev_err(bp->dev, "Firmware decompression error:"
4909 " gunzip_outlen (%d) not aligned\n",
4910 bp->gunzip_outlen);
a2fbb9ea
ET		 4911 bp->gunzip_outlen >>= 2;
4912
4913 zlib_inflateEnd(bp->strm);
4914
4915 if (rc == Z_STREAM_END)
4916 return 0;
4917
4918 return rc;
4919}
4920
4921/* nic load/unload */
4922
4923/*
34f80b04 4924 * General service functions
a2fbb9ea
ET		 4925 */
4926
4927/* send a NIG loopback debug packet */
4928static void bnx2x_lb_pckt(struct bnx2x *bp)
4929{
a2fbb9ea 4930 u32 wb_write[3];
a2fbb9ea
ET		 4931
4932 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 4933 wb_write[0] = 0x55555555;
4934 wb_write[1] = 0x55555555;
34f80b04 4935 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 4936 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4937
4938 /* NON-IP protocol */
a2fbb9ea
ET		 4939 wb_write[0] = 0x09000000;
4940 wb_write[1] = 0x55555555;
34f80b04 4941 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 4942 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4943}
4944
4945/* some of the internal memories
4946 * are not directly readable from the driver
4947 * to test them we send debug packets
4948 */
4949static int bnx2x_int_mem_test(struct bnx2x *bp)
4950{
4951 int factor;
4952 int count, i;
4953 u32 val = 0;
4954
ad8d3948 4955 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 4956 factor = 120;
ad8d3948
EG		 4957 else if (CHIP_REV_IS_EMUL(bp))
4958 factor = 200;
4959 else
a2fbb9ea 4960 factor = 1;
a2fbb9ea 4961
a2fbb9ea
ET		 4962 /* Disable inputs of parser neighbor blocks */
4963 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4964 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4965 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4966 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4967
4968 /* Write 0 to parser credits for CFC search request */
4969 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4970
4971 /* send Ethernet packet */
4972 bnx2x_lb_pckt(bp);
4973
4974 /* TODO do i reset NIG statistic? */
4975 /* Wait until NIG register shows 1 packet of size 0x10 */
4976 count = 1000 * factor;
4977 while (count) {
34f80b04 4978
a2fbb9ea
ET		 4979 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4980 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4981 if (val == 0x10)
4982 break;
4983
4984 msleep(10);
4985 count--;
4986 }
4987 if (val != 0x10) {
4988 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4989 return -1;
4990 }
4991
4992 /* Wait until PRS register shows 1 packet */
4993 count = 1000 * factor;
4994 while (count) {
4995 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 4996 if (val == 1)
4997 break;
4998
4999 msleep(10);
5000 count--;
5001 }
5002 if (val != 0x1) {
5003 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5004 return -2;
5005 }
5006
5007 /* Reset and init BRB, PRS */
34f80b04 5008 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5009 msleep(50);
34f80b04 5010 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5011 msleep(50);
619c5cb6
VZ		 5012 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5013 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5014
5015 DP(NETIF_MSG_HW, "part2\n");
5016
5017 /* Disable inputs of parser neighbor blocks */
5018 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5019 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5020 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5021 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5022
5023 /* Write 0 to parser credits for CFC search request */
5024 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5025
5026 /* send 10 Ethernet packets */
5027 for (i = 0; i < 10; i++)
5028 bnx2x_lb_pckt(bp);
5029
5030 /* Wait until NIG register shows 10 + 1
5031 packets of size 11*0x10 = 0xb0 */
5032 count = 1000 * factor;
5033 while (count) {
34f80b04 5034
a2fbb9ea
ET		 5035 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5036 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5037 if (val == 0xb0)
5038 break;
5039
5040 msleep(10);
5041 count--;
5042 }
5043 if (val != 0xb0) {
5044 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5045 return -3;
5046 }
5047
5048 /* Wait until PRS register shows 2 packets */
5049 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5050 if (val != 2)
5051 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5052
5053 /* Write 1 to parser credits for CFC search request */
5054 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5055
5056 /* Wait until PRS register shows 3 packets */
5057 msleep(10 * factor);
5058 /* Wait until NIG register shows 1 packet of size 0x10 */
5059 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5060 if (val != 3)
5061 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5062
5063 /* clear NIG EOP FIFO */
5064 for (i = 0; i < 11; i++)
5065 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5066 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5067 if (val != 1) {
5068 BNX2X_ERR("clear of NIG failed\n");
5069 return -4;
5070 }
5071
5072 /* Reset and init BRB, PRS, NIG */
5073 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5074 msleep(50);
5075 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5076 msleep(50);
619c5cb6
VZ		 5077 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5078 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5079#ifndef BCM_CNIC
a2fbb9ea
ET		 5080 /* set NIC mode */
5081 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5082#endif
5083
5084 /* Enable inputs of parser neighbor blocks */
5085 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5086 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5087 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5088 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5089
5090 DP(NETIF_MSG_HW, "done\n");
5091
5092 return 0; /* OK */
5093}
5094
4a33bc03 5095static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5096{
5097 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5098 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5099 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5100 else
5101 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5102 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5103 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5104 /*
5105 * mask read length error interrupts in brb for parser
5106 * (parsing unit and 'checksum and crc' unit)
5107 * these errors are legal (PU reads fixed length and CAC can cause
5108 * read length error on truncated packets)
5109 */
5110 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5111 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5112 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5113 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5114 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5115 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5116/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5117/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5118 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5119 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5120 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5121/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5122/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5123 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5124 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5125 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5126 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5127/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5128/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5129
34f80b04
EG		 5130 if (CHIP_REV_IS_FPGA(bp))
5131 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5132 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5133 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5134 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5135 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5136 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5137 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5138 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5139 else
5140 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5141 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5142 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5143 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5144/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5145
5146 if (!CHIP_IS_E1x(bp))
5147 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5148 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5149
a2fbb9ea
ET		 5150 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5151 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5152/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5153 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5154}
5155
81f75bbf
EG		 5156static void bnx2x_reset_common(struct bnx2x *bp)
5157{
619c5cb6
VZ		 5158 u32 val = 0x1400;
5159
81f75bbf
EG		 5160 /* reset_common */
5161 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5162 0xd3ffff7f);
619c5cb6
VZ		 5163
5164 if (CHIP_IS_E3(bp)) {
5165 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5166 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5167 }
5168
5169 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5170}
5171
5172static void bnx2x_setup_dmae(struct bnx2x *bp)
5173{
5174 bp->dmae_ready = 0;
5175 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5176}
5177
573f2035
EG		 5178static void bnx2x_init_pxp(struct bnx2x *bp)
5179{
5180 u16 devctl;
5181 int r_order, w_order;
5182
5183 pci_read_config_word(bp->pdev,
5184 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
5185 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5186 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5187 if (bp->mrrs == -1)
5188 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5189 else {
5190 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5191 r_order = bp->mrrs;
5192 }
5193
5194 bnx2x_init_pxp_arb(bp, r_order, w_order);
5195}
fd4ef40d
EG		 5196
5197static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5198{
2145a920 5199 int is_required;
fd4ef40d 5200 u32 val;
2145a920 5201 int port;
fd4ef40d 5202
2145a920
VZ		 5203 if (BP_NOMCP(bp))
5204 return;
5205
5206 is_required = 0;
fd4ef40d
EG		 5207 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5208 SHARED_HW_CFG_FAN_FAILURE_MASK;
5209
5210 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5211 is_required = 1;
5212
5213 /*
5214 * The fan failure mechanism is usually related to the PHY type since
5215 * the power consumption of the board is affected by the PHY. Currently,
5216 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5217 */
5218 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5219 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5220 is_required |=
d90d96ba
YR		 5221 bnx2x_fan_failure_det_req(
5222 bp,
5223 bp->common.shmem_base,
a22f0788 5224 bp->common.shmem2_base,
d90d96ba 5225 port);
fd4ef40d
EG		 5226 }
5227
5228 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5229
5230 if (is_required == 0)
5231 return;
5232
5233 /* Fan failure is indicated by SPIO 5 */
5234 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5235 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5236
5237 /* set to active low mode */
5238 val = REG_RD(bp, MISC_REG_SPIO_INT);
5239 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5240 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5241 REG_WR(bp, MISC_REG_SPIO_INT, val);
5242
5243 /* enable interrupt to signal the IGU */
5244 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5245 val |= (1 << MISC_REGISTERS_SPIO_5);
5246 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5247}
5248
f2e0899f
DK		 5249static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5250{
5251 u32 offset = 0;
5252
5253 if (CHIP_IS_E1(bp))
5254 return;
5255 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5256 return;
5257
5258 switch (BP_ABS_FUNC(bp)) {
5259 case 0:
5260 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5261 break;
5262 case 1:
5263 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5264 break;
5265 case 2:
5266 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5267 break;
5268 case 3:
5269 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5270 break;
5271 case 4:
5272 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5273 break;
5274 case 5:
5275 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5276 break;
5277 case 6:
5278 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5279 break;
5280 case 7:
5281 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5282 break;
5283 default:
5284 return;
5285 }
5286
5287 REG_WR(bp, offset, pretend_func_num);
5288 REG_RD(bp, offset);
5289 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5290}
5291
5292static void bnx2x_pf_disable(struct bnx2x *bp)
5293{
5294 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5295 val &= ~IGU_PF_CONF_FUNC_EN;
5296
5297 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5298 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5299 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5300}
5301
619c5cb6
VZ		 5302static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5303{
5304 u32 shmem_base[2], shmem2_base[2];
5305 shmem_base[0] = bp->common.shmem_base;
5306 shmem2_base[0] = bp->common.shmem2_base;
5307 if (!CHIP_IS_E1x(bp)) {
5308 shmem_base[1] =
5309 SHMEM2_RD(bp, other_shmem_base_addr);
5310 shmem2_base[1] =
5311 SHMEM2_RD(bp, other_shmem2_base_addr);
5312 }
5313 bnx2x_acquire_phy_lock(bp);
5314 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5315 bp->common.chip_id);
5316 bnx2x_release_phy_lock(bp);
5317}
5318
5319/**
5320 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5321 *
5322 * @bp: driver handle
5323 */
5324static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 5325{
619c5cb6 5326 u32 val;
a2fbb9ea 5327
f2e0899f 5328 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 5329
81f75bbf 5330 bnx2x_reset_common(bp);
34f80b04 5331 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 5332
619c5cb6
VZ		 5333 val = 0xfffc;
5334 if (CHIP_IS_E3(bp)) {
5335 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5336 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5337 }
5338 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5339
5340 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 5341
619c5cb6
VZ		 5342 if (!CHIP_IS_E1x(bp)) {
5343 u8 abs_func_id;
f2e0899f
DK		 5344
5345 /**
5346 * 4-port mode or 2-port mode we need to turn of master-enable
5347 * for everyone, after that, turn it back on for self.
5348 * so, we disregard multi-function or not, and always disable
5349 * for all functions on the given path, this means 0,2,4,6 for
5350 * path 0 and 1,3,5,7 for path 1
5351 */
619c5cb6
VZ		 5352 for (abs_func_id = BP_PATH(bp);
5353 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5354 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 5355 REG_WR(bp,
5356 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5357 1);
5358 continue;
5359 }
5360
619c5cb6 5361 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 5362 /* clear pf enable */
5363 bnx2x_pf_disable(bp);
5364 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5365 }
5366 }
a2fbb9ea 5367
619c5cb6 5368 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 5369 if (CHIP_IS_E1(bp)) {
5370 /* enable HW interrupt from PXP on USDM overflow
5371 bit 16 on INT_MASK_0 */
5372 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5373 }
a2fbb9ea 5374
619c5cb6 5375 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 5376 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5377
5378#ifdef __BIG_ENDIAN
34f80b04
EG		 5379 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5380 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5381 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5382 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5383 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5384 /* make sure this value is 0 */
5385 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5386
5387/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5388 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5389 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5390 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5391 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5392#endif
5393
523224a3
DK		 5394 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5395
34f80b04
EG		 5396 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5397 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5398
34f80b04
EG		 5399 /* let the HW do it's magic ... */
5400 msleep(100);
5401 /* finish PXP init */
5402 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5403 if (val != 1) {
5404 BNX2X_ERR("PXP2 CFG failed\n");
5405 return -EBUSY;
5406 }
5407 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5408 if (val != 1) {
5409 BNX2X_ERR("PXP2 RD_INIT failed\n");
5410 return -EBUSY;
5411 }
a2fbb9ea 5412
f2e0899f
DK		 5413 /* Timers bug workaround E2 only. We need to set the entire ILT to
5414 * have entries with value "0" and valid bit on.
5415 * This needs to be done by the first PF that is loaded in a path
5416 * (i.e. common phase)
5417 */
619c5cb6
VZ		 5418 if (!CHIP_IS_E1x(bp)) {
5419/* In E2 there is a bug in the timers block that can cause function 6 / 7
5420 * (i.e. vnic3) to start even if it is marked as "scan-off".
5421 * This occurs when a different function (func2,3) is being marked
5422 * as "scan-off". Real-life scenario for example: if a driver is being
5423 * load-unloaded while func6,7 are down. This will cause the timer to access
5424 * the ilt, translate to a logical address and send a request to read/write.
5425 * Since the ilt for the function that is down is not valid, this will cause
5426 * a translation error which is unrecoverable.
5427 * The Workaround is intended to make sure that when this happens nothing fatal
5428 * will occur. The workaround:
5429 * 1. First PF driver which loads on a path will:
5430 * a. After taking the chip out of reset, by using pretend,
5431 * it will write "0" to the following registers of
5432 * the other vnics.
5433 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5434 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5435 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5436 * And for itself it will write '1' to
5437 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5438 * dmae-operations (writing to pram for example.)
5439 * note: can be done for only function 6,7 but cleaner this
5440 * way.
5441 * b. Write zero+valid to the entire ILT.
5442 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5443 * VNIC3 (of that port). The range allocated will be the
5444 * entire ILT. This is needed to prevent ILT range error.
5445 * 2. Any PF driver load flow:
5446 * a. ILT update with the physical addresses of the allocated
5447 * logical pages.
5448 * b. Wait 20msec. - note that this timeout is needed to make
5449 * sure there are no requests in one of the PXP internal
5450 * queues with "old" ILT addresses.
5451 * c. PF enable in the PGLC.
5452 * d. Clear the was_error of the PF in the PGLC. (could have
5453 * occured while driver was down)
5454 * e. PF enable in the CFC (WEAK + STRONG)
5455 * f. Timers scan enable
5456 * 3. PF driver unload flow:
5457 * a. Clear the Timers scan_en.
5458 * b. Polling for scan_on=0 for that PF.
5459 * c. Clear the PF enable bit in the PXP.
5460 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5461 * e. Write zero+valid to all ILT entries (The valid bit must
5462 * stay set)
5463 * f. If this is VNIC 3 of a port then also init
5464 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5465 * to the last enrty in the ILT.
5466 *
5467 * Notes:
5468 * Currently the PF error in the PGLC is non recoverable.
5469 * In the future the there will be a recovery routine for this error.
5470 * Currently attention is masked.
5471 * Having an MCP lock on the load/unload process does not guarantee that
5472 * there is no Timer disable during Func6/7 enable. This is because the
5473 * Timers scan is currently being cleared by the MCP on FLR.
5474 * Step 2.d can be done only for PF6/7 and the driver can also check if
5475 * there is error before clearing it. But the flow above is simpler and
5476 * more general.
5477 * All ILT entries are written by zero+valid and not just PF6/7
5478 * ILT entries since in the future the ILT entries allocation for
5479 * PF-s might be dynamic.
5480 */
f2e0899f
DK		 5481 struct ilt_client_info ilt_cli;
5482 struct bnx2x_ilt ilt;
5483 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5484 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5485
b595076a 5486 /* initialize dummy TM client */
f2e0899f
DK		 5487 ilt_cli.start = 0;
5488 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5489 ilt_cli.client_num = ILT_CLIENT_TM;
5490
5491 /* Step 1: set zeroes to all ilt page entries with valid bit on
5492 * Step 2: set the timers first/last ilt entry to point
5493 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 5494 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 5495 *
5496 * both steps performed by call to bnx2x_ilt_client_init_op()
5497 * with dummy TM client
5498 *
5499 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5500 * and his brother are split registers
5501 */
5502 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5503 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5504 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5505
5506 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5507 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5508 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5509 }
5510
5511
34f80b04
EG		 5512 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5513 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5514
619c5cb6 5515 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5516 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5517 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 5518 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 5519
619c5cb6 5520 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 5521
5522 /* let the HW do it's magic ... */
5523 do {
5524 msleep(200);
5525 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5526 } while (factor-- && (val != 1));
5527
5528 if (val != 1) {
5529 BNX2X_ERR("ATC_INIT failed\n");
5530 return -EBUSY;
5531 }
5532 }
5533
619c5cb6 5534 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 5535
34f80b04
EG		 5536 /* clean the DMAE memory */
5537 bp->dmae_ready = 1;
619c5cb6
VZ		 5538 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
5539
5540 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
5541
5542 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
5543
5544 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 5545
619c5cb6 5546 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 5547
34f80b04
EG		 5548 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5549 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5550 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5551 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5552
619c5cb6 5553 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 5554
f85582f8 5555
523224a3
DK		 5556 /* QM queues pointers table */
5557 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5558
34f80b04
EG		 5559 /* soft reset pulse */
5560 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5561 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 5562
37b091ba 5563#ifdef BCM_CNIC
619c5cb6 5564 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 5565#endif
a2fbb9ea 5566
619c5cb6 5567 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 5568 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 5569 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 5570 /* enable hw interrupt from doorbell Q */
5571 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 5572
619c5cb6 5573 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 5574
619c5cb6 5575 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 5576 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 5577
f2e0899f 5578 if (!CHIP_IS_E1(bp))
619c5cb6 5579 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 5580
619c5cb6
VZ		 5581 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
5582 /* Bit-map indicating which L2 hdrs may appear
5583 * after the basic Ethernet header
5584 */
5585 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
5586 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 5587
619c5cb6
VZ		 5588 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
5589 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
5590 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
5591 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 5592
619c5cb6
VZ		 5593 if (!CHIP_IS_E1x(bp)) {
5594 /* reset VFC memories */
5595 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5596 VFC_MEMORIES_RST_REG_CAM_RST |
5597 VFC_MEMORIES_RST_REG_RAM_RST);
5598 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5599 VFC_MEMORIES_RST_REG_CAM_RST |
5600 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 5601
619c5cb6
VZ		 5602 msleep(20);
5603 }
a2fbb9ea 5604
619c5cb6
VZ		 5605 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
5606 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
5607 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
5608 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 5609
34f80b04
EG		 5610 /* sync semi rtc */
5611 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5612 0x80000000);
5613 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5614 0x80000000);
a2fbb9ea 5615
619c5cb6
VZ		 5616 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
5617 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
5618 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 5619
619c5cb6
VZ		 5620 if (!CHIP_IS_E1x(bp))
5621 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
5622 bp->path_has_ovlan ? 7 : 6);
f2e0899f 5623
34f80b04 5624 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 5625
619c5cb6
VZ		 5626 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
5627
37b091ba
MC		 5628#ifdef BCM_CNIC
5629 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5630 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5631 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5632 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5633 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5634 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5635 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5636 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5637 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5638 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5639#endif
34f80b04 5640 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 5641
34f80b04
EG		 5642 if (sizeof(union cdu_context) != 1024)
5643 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 5644 dev_alert(&bp->pdev->dev, "please adjust the size "
5645 "of cdu_context(%ld)\n",
7995c64e 5646 (long)sizeof(union cdu_context));
a2fbb9ea 5647
619c5cb6 5648 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 5649 val = (4 << 24) + (0 << 12) + 1024;
5650 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 5651
619c5cb6 5652 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 5653 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 5654 /* enable context validation interrupt from CFC */
5655 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5656
5657 /* set the thresholds to prevent CFC/CDU race */
5658 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 5659
619c5cb6 5660 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 5661
619c5cb6 5662 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 5663 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5664
619c5cb6
VZ		 5665 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
5666 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 5667
34f80b04
EG		 5668 /* Reset PCIE errors for debug */
5669 REG_WR(bp, 0x2814, 0xffffffff);
5670 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 5671
619c5cb6 5672 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5673 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5674 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5675 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5676 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5677 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5678 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5679 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5680 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5681 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5682 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5683 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5684 }
5685
619c5cb6 5686 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 5687 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 5688 /* in E3 this done in per-port section */
5689 if (!CHIP_IS_E3(bp))
5690 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 5691 }
619c5cb6
VZ		 5692 if (CHIP_IS_E1H(bp))
5693 /* not applicable for E2 (and above ...) */
5694 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 5695
5696 if (CHIP_REV_IS_SLOW(bp))
5697 msleep(200);
5698
5699 /* finish CFC init */
5700 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5701 if (val != 1) {
5702 BNX2X_ERR("CFC LL_INIT failed\n");
5703 return -EBUSY;
5704 }
5705 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5706 if (val != 1) {
5707 BNX2X_ERR("CFC AC_INIT failed\n");
5708 return -EBUSY;
5709 }
5710 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5711 if (val != 1) {
5712 BNX2X_ERR("CFC CAM_INIT failed\n");
5713 return -EBUSY;
5714 }
5715 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 5716
f2e0899f
DK		 5717 if (CHIP_IS_E1(bp)) {
5718 /* read NIG statistic
5719 to see if this is our first up since powerup */
5720 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5721 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 5722
f2e0899f
DK		 5723 /* do internal memory self test */
5724 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5725 BNX2X_ERR("internal mem self test failed\n");
5726 return -EBUSY;
5727 }
34f80b04
EG		 5728 }
5729
fd4ef40d
EG		 5730 bnx2x_setup_fan_failure_detection(bp);
5731
34f80b04
EG		 5732 /* clear PXP2 attentions */
5733 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 5734
4a33bc03
VZ		 5735 bnx2x_enable_blocks_attention(bp);
5736 if (CHIP_PARITY_ENABLED(bp))
5737 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 5738
6bbca910 5739 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 5740 if (CHIP_IS_E1x(bp))
5741 bnx2x__common_init_phy(bp);
6bbca910
YR		 5742 } else
5743 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5744
34f80b04
EG		 5745 return 0;
5746}
a2fbb9ea 5747
619c5cb6
VZ		 5748/**
5749 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
5750 *
5751 * @bp: driver handle
5752 */
5753static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
5754{
5755 int rc = bnx2x_init_hw_common(bp);
5756
5757 if (rc)
5758 return rc;
5759
5760 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5761 if (!BP_NOMCP(bp))
5762 bnx2x__common_init_phy(bp);
5763
5764 return 0;
5765}
5766
523224a3 5767static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 5768{
5769 int port = BP_PORT(bp);
619c5cb6 5770 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 5771 u32 low, high;
34f80b04 5772 u32 val;
a2fbb9ea 5773
619c5cb6
VZ		 5774 bnx2x__link_reset(bp);
5775
cdaa7cb8 5776 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 5777
5778 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 5779
619c5cb6
VZ		 5780 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
5781 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
5782 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 5783
f2e0899f
DK		 5784 /* Timers bug workaround: disables the pf_master bit in pglue at
5785 * common phase, we need to enable it here before any dmae access are
5786 * attempted. Therefore we manually added the enable-master to the
5787 * port phase (it also happens in the function phase)
5788 */
619c5cb6 5789 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5790 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5791
619c5cb6
VZ		 5792 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
5793 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
5794 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
5795 bnx2x_init_block(bp, BLOCK_QM, init_phase);
5796
5797 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
5798 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
5799 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
5800 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 5801
523224a3
DK		 5802 /* QM cid (connection) count */
5803 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 5804
523224a3 5805#ifdef BCM_CNIC
619c5cb6 5806 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 5807 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5808 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 5809#endif
cdaa7cb8 5810
619c5cb6 5811 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 5812
5813 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 5814 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
5815
5816 if (IS_MF(bp))
5817 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5818 else if (bp->dev->mtu > 4096) {
5819 if (bp->flags & ONE_PORT_FLAG)
5820 low = 160;
5821 else {
5822 val = bp->dev->mtu;
5823 /* (24*1024 + val*4)/256 */
5824 low = 96 + (val/64) +
5825 ((val % 64) ? 1 : 0);
5826 }
5827 } else
5828 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5829 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 5830 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5831 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 5832 }
1c06328c 5833
619c5cb6
VZ		 5834 if (CHIP_MODE_IS_4_PORT(bp))
5835 REG_WR(bp, (BP_PORT(bp) ?
5836 BRB1_REG_MAC_GUARANTIED_1 :
5837 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 5838
ca00392c 5839
619c5cb6
VZ		 5840 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
5841 if (CHIP_IS_E3B0(bp))
5842 /* Ovlan exists only if we are in multi-function +
5843 * switch-dependent mode, in switch-independent there
5844 * is no ovlan headers
5845 */
5846 REG_WR(bp, BP_PORT(bp) ?
5847 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
5848 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
5849 (bp->path_has_ovlan ? 7 : 6));
356e2385 5850
619c5cb6
VZ		 5851 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
5852 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
5853 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
5854 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 5855
619c5cb6
VZ		 5856 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
5857 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
5858 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
5859 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 5860
619c5cb6
VZ		 5861 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
5862 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 5863
619c5cb6
VZ		 5864 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
5865
5866 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5867 /* configure PBF to work without PAUSE mtu 9000 */
5868 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 5869
f2e0899f
DK		 5870 /* update threshold */
5871 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5872 /* update init credit */
5873 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 5874
f2e0899f
DK		 5875 /* probe changes */
5876 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5877 udelay(50);
5878 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5879 }
a2fbb9ea 5880
37b091ba 5881#ifdef BCM_CNIC
619c5cb6 5882 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 5883#endif
619c5cb6
VZ		 5884 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
5885 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 5886
5887 if (CHIP_IS_E1(bp)) {
5888 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5889 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5890 }
619c5cb6 5891 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 5892
619c5cb6 5893 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 5894
619c5cb6 5895 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 5896 /* init aeu_mask_attn_func_0/1:
5897 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5898 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5899 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 5900 val = IS_MF(bp) ? 0xF7 : 0x7;
5901 /* Enable DCBX attention for all but E1 */
5902 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5903 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 5904
619c5cb6
VZ		 5905 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
5906
5907 if (!CHIP_IS_E1x(bp)) {
5908 /* Bit-map indicating which L2 hdrs may appear after the
5909 * basic Ethernet header
5910 */
5911 REG_WR(bp, BP_PORT(bp) ?
5912 NIG_REG_P1_HDRS_AFTER_BASIC :
5913 NIG_REG_P0_HDRS_AFTER_BASIC,
5914 IS_MF_SD(bp) ? 7 : 6);
5915
5916 if (CHIP_IS_E3(bp))
5917 REG_WR(bp, BP_PORT(bp) ?
5918 NIG_REG_LLH1_MF_MODE :
5919 NIG_REG_LLH_MF_MODE, IS_MF(bp));
5920 }
5921 if (!CHIP_IS_E3(bp))
5922 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 5923
f2e0899f 5924 if (!CHIP_IS_E1(bp)) {
fb3bff17 5925 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 5926 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 5927 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 5928
619c5cb6 5929 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5930 val = 0;
5931 switch (bp->mf_mode) {
5932 case MULTI_FUNCTION_SD:
5933 val = 1;
5934 break;
5935 case MULTI_FUNCTION_SI:
5936 val = 2;
5937 break;
5938 }
5939
5940 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5941 NIG_REG_LLH0_CLS_TYPE), val);
5942 }
1c06328c
EG		 5943 {
5944 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5945 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5946 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5947 }
34f80b04
EG		 5948 }
5949
619c5cb6
VZ		 5950
5951 /* If SPIO5 is set to generate interrupts, enable it for this port */
5952 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5953 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 5954 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5955 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5956 val = REG_RD(bp, reg_addr);
f1410647 5957 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 5958 REG_WR(bp, reg_addr, val);
f1410647 5959 }
a2fbb9ea 5960
34f80b04
EG		 5961 return 0;
5962}
5963
34f80b04
EG		 5964static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5965{
5966 int reg;
5967
f2e0899f 5968 if (CHIP_IS_E1(bp))
34f80b04 5969 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 5970 else
5971 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 5972
5973 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5974}
5975
f2e0899f
DK		 5976static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5977{
619c5cb6 5978 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 5979}
5980
5981static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5982{
5983 u32 i, base = FUNC_ILT_BASE(func);
5984 for (i = base; i < base + ILT_PER_FUNC; i++)
5985 bnx2x_ilt_wr(bp, i, 0);
5986}
5987
523224a3 5988static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 5989{
5990 int port = BP_PORT(bp);
5991 int func = BP_FUNC(bp);
619c5cb6 5992 int init_phase = PHASE_PF0 + func;
523224a3
DK		 5993 struct bnx2x_ilt *ilt = BP_ILT(bp);
5994 u16 cdu_ilt_start;
8badd27a 5995 u32 addr, val;
f4a66897
VZ		 5996 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5997 int i, main_mem_width;
34f80b04 5998
cdaa7cb8 5999 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6000
619c5cb6
VZ		 6001 /* FLR cleanup - hmmm */
6002 if (!CHIP_IS_E1x(bp))
6003 bnx2x_pf_flr_clnup(bp);
6004
8badd27a 6005 /* set MSI reconfigure capability */
f2e0899f
DK		 6006 if (bp->common.int_block == INT_BLOCK_HC) {
6007 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6008 val = REG_RD(bp, addr);
6009 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6010 REG_WR(bp, addr, val);
6011 }
8badd27a 6012
619c5cb6
VZ		 6013 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6014 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6015
523224a3
DK		 6016 ilt = BP_ILT(bp);
6017 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6018
523224a3
DK		 6019 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6020 ilt->lines[cdu_ilt_start + i].page =
6021 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6022 ilt->lines[cdu_ilt_start + i].page_mapping =
6023 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6024 /* cdu ilt pages are allocated manually so there's no need to
6025 set the size */
37b091ba 6026 }
523224a3 6027 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6028
523224a3
DK		 6029#ifdef BCM_CNIC
6030 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6031
523224a3
DK		 6032 /* T1 hash bits value determines the T1 number of entries */
6033 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6034#endif
37b091ba 6035
523224a3
DK		 6036#ifndef BCM_CNIC
6037 /* set NIC mode */
6038 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6039#endif /* BCM_CNIC */
37b091ba 6040
619c5cb6 6041 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6042 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6043
6044 /* Turn on a single ISR mode in IGU if driver is going to use
6045 * INT#x or MSI
6046 */
6047 if (!(bp->flags & USING_MSIX_FLAG))
6048 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6049 /*
6050 * Timers workaround bug: function init part.
6051 * Need to wait 20msec after initializing ILT,
6052 * needed to make sure there are no requests in
6053 * one of the PXP internal queues with "old" ILT addresses
6054 */
6055 msleep(20);
6056 /*
6057 * Master enable - Due to WB DMAE writes performed before this
6058 * register is re-initialized as part of the regular function
6059 * init
6060 */
6061 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6062 /* Enable the function in IGU */
6063 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6064 }
6065
523224a3 6066 bp->dmae_ready = 1;
34f80b04 6067
619c5cb6 6068 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6069
619c5cb6 6070 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6071 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6072
619c5cb6
VZ		 6073 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6074 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6075 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6076 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6077 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6078 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6079 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6080 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6081 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6082 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6083 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6084 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6085 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6086
6087 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6088 REG_WR(bp, QM_REG_PF_EN, 1);
6089
619c5cb6
VZ		 6090 if (!CHIP_IS_E1x(bp)) {
6091 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6092 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6093 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6094 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6095 }
6096 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6097
6098 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6099 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6100 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6101 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6102 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6103 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6104 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6105 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6106 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6107 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6108 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6109 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6110 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6111
619c5cb6 6112 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6113
619c5cb6 6114 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6115
619c5cb6 6116 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6117 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6118
fb3bff17 6119 if (IS_MF(bp)) {
34f80b04 6120 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6121 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6122 }
6123
619c5cb6 6124 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6125
34f80b04 6126 /* HC init per function */
f2e0899f
DK		 6127 if (bp->common.int_block == INT_BLOCK_HC) {
6128 if (CHIP_IS_E1H(bp)) {
6129 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6130
6131 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6132 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6133 }
619c5cb6 6134 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6135
6136 } else {
6137 int num_segs, sb_idx, prod_offset;
6138
34f80b04
EG		 6139 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6140
619c5cb6 6141 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6142 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6143 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6144 }
6145
619c5cb6 6146 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6147
619c5cb6 6148 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6149 int dsb_idx = 0;
6150 /**
6151 * Producer memory:
6152 * E2 mode: address 0-135 match to the mapping memory;
6153 * 136 - PF0 default prod; 137 - PF1 default prod;
6154 * 138 - PF2 default prod; 139 - PF3 default prod;
6155 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6156 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6157 * 144-147 reserved.
6158 *
6159 * E1.5 mode - In backward compatible mode;
6160 * for non default SB; each even line in the memory
6161 * holds the U producer and each odd line hold
6162 * the C producer. The first 128 producers are for
6163 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6164 * producers are for the DSB for each PF.
6165 * Each PF has five segments: (the order inside each
6166 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6167 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6168 * 144-147 attn prods;
6169 */
6170 /* non-default-status-blocks */
6171 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6172 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6173 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6174 prod_offset = (bp->igu_base_sb + sb_idx) *
6175 num_segs;
6176
6177 for (i = 0; i < num_segs; i++) {
6178 addr = IGU_REG_PROD_CONS_MEMORY +
6179 (prod_offset + i) * 4;
6180 REG_WR(bp, addr, 0);
6181 }
6182 /* send consumer update with value 0 */
6183 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6184 USTORM_ID, 0, IGU_INT_NOP, 1);
6185 bnx2x_igu_clear_sb(bp,
6186 bp->igu_base_sb + sb_idx);
6187 }
6188
6189 /* default-status-blocks */
6190 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6191 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6192
6193 if (CHIP_MODE_IS_4_PORT(bp))
6194 dsb_idx = BP_FUNC(bp);
6195 else
6196 dsb_idx = BP_E1HVN(bp);
6197
6198 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6199 IGU_BC_BASE_DSB_PROD + dsb_idx :
6200 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6201
6202 for (i = 0; i < (num_segs * E1HVN_MAX);
6203 i += E1HVN_MAX) {
6204 addr = IGU_REG_PROD_CONS_MEMORY +
6205 (prod_offset + i)*4;
6206 REG_WR(bp, addr, 0);
6207 }
6208 /* send consumer update with 0 */
6209 if (CHIP_INT_MODE_IS_BC(bp)) {
6210 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6211 USTORM_ID, 0, IGU_INT_NOP, 1);
6212 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6213 CSTORM_ID, 0, IGU_INT_NOP, 1);
6214 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6215 XSTORM_ID, 0, IGU_INT_NOP, 1);
6216 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6217 TSTORM_ID, 0, IGU_INT_NOP, 1);
6218 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6219 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6220 } else {
6221 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6222 USTORM_ID, 0, IGU_INT_NOP, 1);
6223 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6224 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6225 }
6226 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6227
6228 /* !!! these should become driver const once
6229 rf-tool supports split-68 const */
6230 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6231 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6232 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6233 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6234 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6235 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6236 }
34f80b04 6237 }
34f80b04 6238
c14423fe 6239 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6240 REG_WR(bp, 0x2114, 0xffffffff);
6241 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6242
f4a66897
VZ		 6243 if (CHIP_IS_E1x(bp)) {
6244 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6245 main_mem_base = HC_REG_MAIN_MEMORY +
6246 BP_PORT(bp) * (main_mem_size * 4);
6247 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6248 main_mem_width = 8;
6249
6250 val = REG_RD(bp, main_mem_prty_clr);
6251 if (val)
6252 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6253 "block during "
6254 "function init (0x%x)!\n", val);
6255
6256 /* Clear "false" parity errors in MSI-X table */
6257 for (i = main_mem_base;
6258 i < main_mem_base + main_mem_size * 4;
6259 i += main_mem_width) {
6260 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6261 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6262 i, main_mem_width / 4);
6263 }
6264 /* Clear HC parity attention */
6265 REG_RD(bp, main_mem_prty_clr);
6266 }
6267
619c5cb6
VZ		 6268#ifdef BNX2X_STOP_ON_ERROR
6269 /* Enable STORMs SP logging */
6270 REG_WR8(bp, BAR_USTRORM_INTMEM +
6271 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6272 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6273 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6274 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6275 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6276 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6277 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6278#endif
6279
b7737c9b 6280 bnx2x_phy_probe(&bp->link_params);
f85582f8 6281
34f80b04
EG		 6282 return 0;
6283}
6284
a2fbb9ea 6285
9f6c9258 6286void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6287{
a2fbb9ea 6288 /* fastpath */
b3b83c3f 6289 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6290 /* end of fastpath */
6291
6292 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 6293 sizeof(struct host_sp_status_block));
a2fbb9ea 6294
619c5cb6
VZ		 6295 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6296 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6297
a2fbb9ea 6298 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 6299 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6300
523224a3
DK		 6301 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6302 bp->context.size);
6303
6304 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6305
6306 BNX2X_FREE(bp->ilt->lines);
f85582f8 6307
37b091ba 6308#ifdef BCM_CNIC
619c5cb6 6309 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6310 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6311 sizeof(struct host_hc_status_block_e2));
6312 else
6313 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6314 sizeof(struct host_hc_status_block_e1x));
f85582f8 6315
523224a3 6316 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 6317#endif
f85582f8 6318
7a9b2557 6319 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 6320
523224a3
DK		 6321 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6322 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 6323}
6324
6325static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6326{
6327 int num_groups;
6328
6329 /* number of eth_queues */
6330 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6331
6332 /* Total number of FW statistics requests =
6333 * 1 for port stats + 1 for PF stats + num_eth_queues */
6334 bp->fw_stats_num = 2 + num_queue_stats;
523224a3 6335
619c5cb6
VZ		 6336
6337 /* Request is built from stats_query_header and an array of
6338 * stats_query_cmd_group each of which contains
6339 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6340 * configured in the stats_query_header.
6341 */
6342 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6343 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6344
6345 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6346 num_groups * sizeof(struct stats_query_cmd_group);
6347
6348 /* Data for statistics requests + stats_conter
6349 *
6350 * stats_counter holds per-STORM counters that are incremented
6351 * when STORM has finished with the current request.
6352 */
6353 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6354 sizeof(struct per_pf_stats) +
6355 sizeof(struct per_queue_stats) * num_queue_stats +
6356 sizeof(struct stats_counter);
6357
6358 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6359 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6360
6361 /* Set shortcuts */
6362 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6363 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6364
6365 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6366 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6367
6368 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6369 bp->fw_stats_req_sz;
6370 return 0;
6371
6372alloc_mem_err:
6373 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6374 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6375 return -ENOMEM;
a2fbb9ea
ET		 6376}
6377
f2e0899f 6378
9f6c9258 6379int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6380{
523224a3 6381#ifdef BCM_CNIC
619c5cb6
VZ		 6382 if (!CHIP_IS_E1x(bp))
6383 /* size = the status block + ramrod buffers */
f2e0899f
DK		 6384 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6385 sizeof(struct host_hc_status_block_e2));
6386 else
6387 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6388 sizeof(struct host_hc_status_block_e1x));
8badd27a 6389
523224a3
DK		 6390 /* allocate searcher T2 table */
6391 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6392#endif
a2fbb9ea 6393
8badd27a 6394
523224a3
DK		 6395 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6396 sizeof(struct host_sp_status_block));
a2fbb9ea 6397
523224a3
DK		 6398 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6399 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6400
619c5cb6
VZ		 6401 /* Allocated memory for FW statistics */
6402 if (bnx2x_alloc_fw_stats_mem(bp))
6403 goto alloc_mem_err;
6404
523224a3 6405 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
f85582f8 6406
523224a3
DK		 6407 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6408 bp->context.size);
65abd74d 6409
523224a3 6410 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6411
523224a3
DK		 6412 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6413 goto alloc_mem_err;
65abd74d 6414
9f6c9258
DK		 6415 /* Slow path ring */
6416 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6417
523224a3
DK		 6418 /* EQ */
6419 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6420 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 6421
b3b83c3f
DK		 6422
6423 /* fastpath */
6424 /* need to be done at the end, since it's self adjusting to amount
6425 * of memory available for RSS queues
6426 */
6427 if (bnx2x_alloc_fp_mem(bp))
6428 goto alloc_mem_err;
9f6c9258 6429 return 0;
e1510706 6430
9f6c9258
DK		 6431alloc_mem_err:
6432 bnx2x_free_mem(bp);
6433 return -ENOMEM;
65abd74d
YG		 6434}
6435
a2fbb9ea
ET		 6436/*
6437 * Init service functions
6438 */
a2fbb9ea 6439
619c5cb6
VZ		 6440int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6441 struct bnx2x_vlan_mac_obj *obj, bool set,
6442 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 6443{
619c5cb6
VZ		 6444 int rc;
6445 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 6446
619c5cb6 6447 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 6448
619c5cb6
VZ		 6449 /* Fill general parameters */
6450 ramrod_param.vlan_mac_obj = obj;
6451 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 6452
619c5cb6
VZ		 6453 /* Fill a user request section if needed */
6454 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6455 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 6456
619c5cb6 6457 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 6458
619c5cb6
VZ		 6459 /* Set the command: ADD or DEL */
6460 if (set)
6461 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6462 else
6463 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 6464 }
6465
619c5cb6
VZ		 6466 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6467 if (rc < 0)
6468 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6469 return rc;
a2fbb9ea
ET		 6470}
6471
619c5cb6
VZ		 6472int bnx2x_del_all_macs(struct bnx2x *bp,
6473 struct bnx2x_vlan_mac_obj *mac_obj,
6474 int mac_type, bool wait_for_comp)
e665bfda 6475{
619c5cb6
VZ		 6476 int rc;
6477 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 6478
619c5cb6
VZ		 6479 /* Wait for completion of requested */
6480 if (wait_for_comp)
6481 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 6482
619c5cb6
VZ		 6483 /* Set the mac type of addresses we want to clear */
6484 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 6485
619c5cb6
VZ		 6486 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6487 if (rc < 0)
6488 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 6489
619c5cb6 6490 return rc;
0793f83f
DK		 6491}
6492
619c5cb6 6493int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 6494{
619c5cb6 6495 unsigned long ramrod_flags = 0;
e665bfda 6496
619c5cb6 6497 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 6498
619c5cb6
VZ		 6499 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6500 /* Eth MAC is set on RSS leading client (fp[0]) */
6501 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6502 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 6503}
6e30dd4e 6504
619c5cb6 6505int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 6506{
619c5cb6 6507 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 6508}
a2fbb9ea 6509
d6214d7a 6510/**
e8920674 6511 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 6512 *
e8920674 6513 * @bp: driver handle
d6214d7a 6514 *
e8920674 6515 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 6516 */
9ee3d37b 6517static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6518{
9ee3d37b 6519 switch (int_mode) {
d6214d7a
DK		 6520 case INT_MODE_MSI:
6521 bnx2x_enable_msi(bp);
6522 /* falling through... */
6523 case INT_MODE_INTx:
ec6ba945 6524 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a 6525 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6526 break;
d6214d7a
DK		 6527 default:
6528 /* Set number of queues according to bp->multi_mode value */
6529 bnx2x_set_num_queues(bp);
ca00392c 6530
d6214d7a
DK		 6531 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6532 bp->num_queues);
ca00392c 6533
d6214d7a
DK		 6534 /* if we can't use MSI-X we only need one fp,
6535 * so try to enable MSI-X with the requested number of fp's
6536 * and fallback to MSI or legacy INTx with one fp
6537 */
9ee3d37b 6538 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 6539 /* failed to enable MSI-X */
6540 if (bp->multi_mode)
6541 DP(NETIF_MSG_IFUP,
6542 "Multi requested but failed to "
6543 "enable MSI-X (%d), "
6544 "set number of queues to %d\n",
6545 bp->num_queues,
ec6ba945
VZ		 6546 1 + NONE_ETH_CONTEXT_USE);
6547 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a 6548
9ee3d37b 6549 /* Try to enable MSI */
d6214d7a
DK		 6550 if (!(bp->flags & DISABLE_MSI_FLAG))
6551 bnx2x_enable_msi(bp);
6552 }
9f6c9258
DK		 6553 break;
6554 }
a2fbb9ea
ET		 6555}
6556
c2bff63f
DK		 6557/* must be called prioir to any HW initializations */
6558static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6559{
6560 return L2_ILT_LINES(bp);
6561}
6562
523224a3
DK		 6563void bnx2x_ilt_set_info(struct bnx2x *bp)
6564{
6565 struct ilt_client_info *ilt_client;
6566 struct bnx2x_ilt *ilt = BP_ILT(bp);
6567 u16 line = 0;
6568
6569 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6570 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6571
6572 /* CDU */
6573 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6574 ilt_client->client_num = ILT_CLIENT_CDU;
6575 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6576 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6577 ilt_client->start = line;
619c5cb6 6578 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 6579#ifdef BCM_CNIC
6580 line += CNIC_ILT_LINES;
6581#endif
6582 ilt_client->end = line - 1;
6583
6584 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6585 "flags 0x%x, hw psz %d\n",
6586 ilt_client->start,
6587 ilt_client->end,
6588 ilt_client->page_size,
6589 ilt_client->flags,
6590 ilog2(ilt_client->page_size >> 12));
6591
6592 /* QM */
6593 if (QM_INIT(bp->qm_cid_count)) {
6594 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6595 ilt_client->client_num = ILT_CLIENT_QM;
6596 ilt_client->page_size = QM_ILT_PAGE_SZ;
6597 ilt_client->flags = 0;
6598 ilt_client->start = line;
6599
6600 /* 4 bytes for each cid */
6601 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6602 QM_ILT_PAGE_SZ);
6603
6604 ilt_client->end = line - 1;
6605
6606 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6607 "flags 0x%x, hw psz %d\n",
6608 ilt_client->start,
6609 ilt_client->end,
6610 ilt_client->page_size,
6611 ilt_client->flags,
6612 ilog2(ilt_client->page_size >> 12));
6613
6614 }
6615 /* SRC */
6616 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6617#ifdef BCM_CNIC
6618 ilt_client->client_num = ILT_CLIENT_SRC;
6619 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6620 ilt_client->flags = 0;
6621 ilt_client->start = line;
6622 line += SRC_ILT_LINES;
6623 ilt_client->end = line - 1;
6624
6625 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6626 "flags 0x%x, hw psz %d\n",
6627 ilt_client->start,
6628 ilt_client->end,
6629 ilt_client->page_size,
6630 ilt_client->flags,
6631 ilog2(ilt_client->page_size >> 12));
6632
6633#else
6634 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6635#endif
9f6c9258 6636
523224a3
DK		 6637 /* TM */
6638 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6639#ifdef BCM_CNIC
6640 ilt_client->client_num = ILT_CLIENT_TM;
6641 ilt_client->page_size = TM_ILT_PAGE_SZ;
6642 ilt_client->flags = 0;
6643 ilt_client->start = line;
6644 line += TM_ILT_LINES;
6645 ilt_client->end = line - 1;
6646
6647 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6648 "flags 0x%x, hw psz %d\n",
6649 ilt_client->start,
6650 ilt_client->end,
6651 ilt_client->page_size,
6652 ilt_client->flags,
6653 ilog2(ilt_client->page_size >> 12));
9f6c9258 6654
523224a3
DK		 6655#else
6656 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6657#endif
619c5cb6 6658 BUG_ON(line > ILT_MAX_LINES);
523224a3 6659}
f85582f8 6660
619c5cb6
VZ		 6661/**
6662 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
6663 *
6664 * @bp: driver handle
6665 * @fp: pointer to fastpath
6666 * @init_params: pointer to parameters structure
6667 *
6668 * parameters configured:
6669 * - HC configuration
6670 * - Queue's CDU context
6671 */
6672static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
6673 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 6674{
619c5cb6
VZ		 6675 /* FCoE Queue uses Default SB, thus has no HC capabilities */
6676 if (!IS_FCOE_FP(fp)) {
6677 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
6678 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
6679
6680 /* If HC is supporterd, enable host coalescing in the transition
6681 * to INIT state.
6682 */
6683 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
6684 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
6685
6686 /* HC rate */
6687 init_params->rx.hc_rate = bp->rx_ticks ?
6688 (1000000 / bp->rx_ticks) : 0;
6689 init_params->tx.hc_rate = bp->tx_ticks ?
6690 (1000000 / bp->tx_ticks) : 0;
6691
6692 /* FW SB ID */
6693 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
6694 fp->fw_sb_id;
6695
6696 /*
6697 * CQ index among the SB indices: FCoE clients uses the default
6698 * SB, therefore it's different.
6699 */
6700 init_params->rx.sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
6701 init_params->tx.sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
6702 }
6703
6704 init_params->cxt = &bp->context.vcxt[fp->cid].eth;
6705}
6706
6707/**
6708 * bnx2x_setup_queue - setup queue
6709 *
6710 * @bp: driver handle
6711 * @fp: pointer to fastpath
6712 * @leading: is leading
6713 *
6714 * This function performs 2 steps in a Queue state machine
6715 * actually: 1) RESET->INIT 2) INIT->SETUP
6716 */
6717
6718int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6719 bool leading)
6720{
6721 struct bnx2x_queue_state_params q_params = {0};
6722 struct bnx2x_queue_setup_params *setup_params =
6723 &q_params.params.setup;
a2fbb9ea
ET		 6724 int rc;
6725
ec6ba945
VZ		 6726 /* reset IGU state skip FCoE L2 queue */
6727 if (!IS_FCOE_FP(fp))
6728 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 6729 IGU_INT_ENABLE, 0);
a2fbb9ea 6730
619c5cb6
VZ		 6731 q_params.q_obj = &fp->q_obj;
6732 /* We want to wait for completion in this context */
6733 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 6734
619c5cb6
VZ		 6735 /* Prepare the INIT parameters */
6736 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 6737
619c5cb6
VZ		 6738 /* Set the command */
6739 q_params.cmd = BNX2X_Q_CMD_INIT;
6740
6741 /* Change the state to INIT */
6742 rc = bnx2x_queue_state_change(bp, &q_params);
6743 if (rc) {
6744 BNX2X_ERR("Queue INIT failed\n");
6745 return rc;
6746 }
ec6ba945 6747
619c5cb6
VZ		 6748 /* Now move the Queue to the SETUP state... */
6749 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 6750
619c5cb6
VZ		 6751 /* Set QUEUE flags */
6752 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 6753
619c5cb6
VZ		 6754 /* Set general SETUP parameters */
6755 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params);
6756
6757 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause,
6758 &setup_params->rxq_params);
6759
6760 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params);
6761
6762 /* Set the command */
6763 q_params.cmd = BNX2X_Q_CMD_SETUP;
6764
6765 /* Change the state to SETUP */
6766 rc = bnx2x_queue_state_change(bp, &q_params);
6767 if (rc)
6768 BNX2X_ERR("Queue SETUP failed\n");
523224a3 6769
34f80b04 6770 return rc;
a2fbb9ea
ET		 6771}
6772
619c5cb6 6773static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 6774{
619c5cb6
VZ		 6775 struct bnx2x_fastpath *fp = &bp->fp[index];
6776 struct bnx2x_queue_state_params q_params = {0};
34f80b04 6777 int rc;
a2fbb9ea 6778
619c5cb6
VZ		 6779 q_params.q_obj = &fp->q_obj;
6780 /* We want to wait for completion in this context */
6781 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 6782
523224a3 6783 /* halt the connection */
619c5cb6
VZ		 6784 q_params.cmd = BNX2X_Q_CMD_HALT;
6785 rc = bnx2x_queue_state_change(bp, &q_params);
6786 if (rc)
da5a662a 6787 return rc;
a2fbb9ea 6788
619c5cb6
VZ		 6789 /* terminate the connection */
6790 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6791 rc = bnx2x_queue_state_change(bp, &q_params);
6792 if (rc)
523224a3 6793 return rc;
a2fbb9ea 6794
523224a3 6795 /* delete cfc entry */
619c5cb6
VZ		 6796 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6797 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 6798}
6799
6800
34f80b04
EG		 6801static void bnx2x_reset_func(struct bnx2x *bp)
6802{
6803 int port = BP_PORT(bp);
6804 int func = BP_FUNC(bp);
f2e0899f 6805 int i;
523224a3
DK		 6806
6807 /* Disable the function in the FW */
6808 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6809 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6810 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6811 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6812
6813 /* FP SBs */
ec6ba945 6814 for_each_eth_queue(bp, i) {
523224a3 6815 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6
VZ		 6816 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6817 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
6818 SB_DISABLED);
523224a3
DK		 6819 }
6820
619c5cb6
VZ		 6821#ifdef BCM_CNIC
6822 /* CNIC SB */
6823 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6824 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
6825 SB_DISABLED);
6826#endif
523224a3 6827 /* SP SB */
619c5cb6
VZ		 6828 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6829 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
6830 SB_DISABLED);
523224a3
DK		 6831
6832 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6833 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6834 0);
34f80b04
EG		 6835
6836 /* Configure IGU */
f2e0899f
DK		 6837 if (bp->common.int_block == INT_BLOCK_HC) {
6838 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6839 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6840 } else {
6841 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6842 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6843 }
34f80b04 6844
37b091ba
MC		 6845#ifdef BCM_CNIC
6846 /* Disable Timer scan */
6847 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6848 /*
6849 * Wait for at least 10ms and up to 2 second for the timers scan to
6850 * complete
6851 */
6852 for (i = 0; i < 200; i++) {
6853 msleep(10);
6854 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6855 break;
6856 }
6857#endif
34f80b04 6858 /* Clear ILT */
f2e0899f
DK		 6859 bnx2x_clear_func_ilt(bp, func);
6860
6861 /* Timers workaround bug for E2: if this is vnic-3,
6862 * we need to set the entire ilt range for this timers.
6863 */
619c5cb6 6864 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 6865 struct ilt_client_info ilt_cli;
6866 /* use dummy TM client */
6867 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6868 ilt_cli.start = 0;
6869 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6870 ilt_cli.client_num = ILT_CLIENT_TM;
6871
6872 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
6873 }
6874
6875 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 6876 if (!CHIP_IS_E1x(bp))
f2e0899f 6877 bnx2x_pf_disable(bp);
523224a3
DK		 6878
6879 bp->dmae_ready = 0;
34f80b04
EG		 6880}
6881
6882static void bnx2x_reset_port(struct bnx2x *bp)
6883{
6884 int port = BP_PORT(bp);
6885 u32 val;
6886
619c5cb6
VZ		 6887 /* Reset physical Link */
6888 bnx2x__link_reset(bp);
6889
34f80b04
EG		 6890 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6891
6892 /* Do not rcv packets to BRB */
6893 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6894 /* Do not direct rcv packets that are not for MCP to the BRB */
6895 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6896 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6897
6898 /* Configure AEU */
6899 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6900
6901 msleep(100);
6902 /* Check for BRB port occupancy */
6903 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6904 if (val)
6905 DP(NETIF_MSG_IFDOWN,
33471629 6906 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 6907
6908 /* TODO: Close Doorbell port? */
6909}
6910
619c5cb6 6911static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 6912{
619c5cb6 6913 struct bnx2x_func_state_params func_params = {0};
34f80b04 6914
619c5cb6
VZ		 6915 /* Prepare parameters for function state transitions */
6916 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 6917
619c5cb6
VZ		 6918 func_params.f_obj = &bp->func_obj;
6919 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 6920
619c5cb6 6921 func_params.params.hw_init.load_phase = load_code;
49d66772 6922
619c5cb6 6923 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 6924}
6925
619c5cb6 6926static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 6927{
619c5cb6
VZ		 6928 struct bnx2x_func_state_params func_params = {0};
6929 int rc;
228241eb 6930
619c5cb6
VZ		 6931 /* Prepare parameters for function state transitions */
6932 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
6933 func_params.f_obj = &bp->func_obj;
6934 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 6935
619c5cb6
VZ		 6936 /*
6937 * Try to stop the function the 'good way'. If fails (in case
6938 * of a parity error during bnx2x_chip_cleanup()) and we are
6939 * not in a debug mode, perform a state transaction in order to
6940 * enable further HW_RESET transaction.
6941 */
6942 rc = bnx2x_func_state_change(bp, &func_params);
6943 if (rc) {
34f80b04 6944#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 6945 return rc;
34f80b04 6946#else
619c5cb6
VZ		 6947 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
6948 "transaction\n");
6949 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
6950 return bnx2x_func_state_change(bp, &func_params);
34f80b04 6951#endif
228241eb 6952 }
a2fbb9ea 6953
619c5cb6
VZ		 6954 return 0;
6955}
523224a3 6956
619c5cb6
VZ		 6957/**
6958 * bnx2x_send_unload_req - request unload mode from the MCP.
6959 *
6960 * @bp: driver handle
6961 * @unload_mode: requested function's unload mode
6962 *
6963 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
6964 */
6965u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
6966{
6967 u32 reset_code = 0;
6968 int port = BP_PORT(bp);
3101c2bc 6969
619c5cb6 6970 /* Select the UNLOAD request mode */
65abd74d
YG		 6971 if (unload_mode == UNLOAD_NORMAL)
6972 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6973
7d0446c2 6974 else if (bp->flags & NO_WOL_FLAG)
65abd74d 6975 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 6976
7d0446c2 6977 else if (bp->wol) {
65abd74d
YG		 6978 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6979 u8 *mac_addr = bp->dev->dev_addr;
6980 u32 val;
6981 /* The mac address is written to entries 1-4 to
6982 preserve entry 0 which is used by the PMF */
6983 u8 entry = (BP_E1HVN(bp) + 1)*8;
6984
6985 val = (mac_addr[0] << 8) | mac_addr[1];
6986 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
6987
6988 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
6989 (mac_addr[4] << 8) | mac_addr[5];
6990 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
6991
6992 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
6993
6994 } else
6995 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 6996
619c5cb6
VZ		 6997 /* Send the request to the MCP */
6998 if (!BP_NOMCP(bp))
6999 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7000 else {
7001 int path = BP_PATH(bp);
7002
7003 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7004 "%d, %d, %d\n",
7005 path, load_count[path][0], load_count[path][1],
7006 load_count[path][2]);
7007 load_count[path][0]--;
7008 load_count[path][1 + port]--;
7009 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7010 "%d, %d, %d\n",
7011 path, load_count[path][0], load_count[path][1],
7012 load_count[path][2]);
7013 if (load_count[path][0] == 0)
7014 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7015 else if (load_count[path][1 + port] == 0)
7016 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7017 else
7018 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7019 }
7020
7021 return reset_code;
7022}
7023
7024/**
7025 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7026 *
7027 * @bp: driver handle
7028 */
7029void bnx2x_send_unload_done(struct bnx2x *bp)
7030{
7031 /* Report UNLOAD_DONE to MCP */
7032 if (!BP_NOMCP(bp))
7033 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7034}
7035
7036void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7037{
7038 int port = BP_PORT(bp);
7039 int i, rc;
7040 struct bnx2x_mcast_ramrod_params rparam = {0};
7041 u32 reset_code;
7042
7043 /* Wait until tx fastpath tasks complete */
7044 for_each_tx_queue(bp, i) {
7045 struct bnx2x_fastpath *fp = &bp->fp[i];
7046
7047 rc = bnx2x_clean_tx_queue(bp, fp);
7048#ifdef BNX2X_STOP_ON_ERROR
7049 if (rc)
7050 return;
7051#endif
7052 }
7053
7054 /* Give HW time to discard old tx messages */
7055 usleep_range(1000, 1000);
7056
7057 /* Clean all ETH MACs */
7058 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7059 if (rc < 0)
7060 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7061
7062 /* Clean up UC list */
7063 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7064 true);
7065 if (rc < 0)
7066 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7067 "%d\n", rc);
7068
7069 /* Disable LLH */
7070 if (!CHIP_IS_E1(bp))
7071 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7072
7073 /* Set "drop all" (stop Rx).
7074 * We need to take a netif_addr_lock() here in order to prevent
7075 * a race between the completion code and this code.
7076 */
7077 netif_addr_lock_bh(bp->dev);
7078 /* Schedule the rx_mode command */
7079 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7080 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7081 else
7082 bnx2x_set_storm_rx_mode(bp);
7083
7084 /* Cleanup multicast configuration */
7085 rparam.mcast_obj = &bp->mcast_obj;
7086 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7087 if (rc < 0)
7088 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7089
7090 netif_addr_unlock_bh(bp->dev);
7091
7092
34f80b04 7093 /* Close multi and leading connections
619c5cb6
VZ		 7094 * Completions for ramrods are collected in a synchronous way
7095 */
523224a3 7096 for_each_queue(bp, i)
619c5cb6 7097 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 7098#ifdef BNX2X_STOP_ON_ERROR
7099 return;
7100#else
228241eb 7101 goto unload_error;
523224a3 7102#endif
619c5cb6
VZ		 7103 /* If SP settings didn't get completed so far - something
7104 * very wrong has happen.
7105 */
7106 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7107 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 7108
619c5cb6
VZ		 7109#ifndef BNX2X_STOP_ON_ERROR
7110unload_error:
7111#endif
523224a3 7112 rc = bnx2x_func_stop(bp);
da5a662a 7113 if (rc) {
523224a3 7114 BNX2X_ERR("Function stop failed!\n");
da5a662a 7115#ifdef BNX2X_STOP_ON_ERROR
523224a3 7116 return;
523224a3 7117#endif
34f80b04 7118 }
a2fbb9ea 7119
619c5cb6
VZ		 7120 /*
7121 * Send the UNLOAD_REQUEST to the MCP. This will return if
7122 * this function should perform FUNC, PORT or COMMON HW
7123 * reset.
7124 */
7125 reset_code = bnx2x_send_unload_req(bp, unload_mode);
a2fbb9ea 7126
523224a3
DK		 7127 /* Disable HW interrupts, NAPI */
7128 bnx2x_netif_stop(bp, 1);
7129
7130 /* Release IRQs */
d6214d7a 7131 bnx2x_free_irq(bp);
523224a3 7132
a2fbb9ea 7133 /* Reset the chip */
619c5cb6
VZ		 7134 rc = bnx2x_reset_hw(bp, reset_code);
7135 if (rc)
7136 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 7137
356e2385 7138
619c5cb6
VZ		 7139 /* Report UNLOAD_DONE to MCP */
7140 bnx2x_send_unload_done(bp);
72fd0718
VZ		 7141}
7142
9f6c9258 7143void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7144{
7145 u32 val;
7146
7147 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7148
7149 if (CHIP_IS_E1(bp)) {
7150 int port = BP_PORT(bp);
7151 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7152 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7153
7154 val = REG_RD(bp, addr);
7155 val &= ~(0x300);
7156 REG_WR(bp, addr, val);
619c5cb6 7157 } else {
72fd0718
VZ		 7158 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7159 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7160 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7161 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7162 }
7163}
7164
72fd0718
VZ		 7165/* Close gates #2, #3 and #4: */
7166static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7167{
7168 u32 val, addr;
7169
7170 /* Gates #2 and #4a are closed/opened for "not E1" only */
7171 if (!CHIP_IS_E1(bp)) {
7172 /* #4 */
7173 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7174 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7175 close ? (val | 0x1) : (val & (~(u32)1)));
7176 /* #2 */
7177 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7178 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7179 close ? (val | 0x1) : (val & (~(u32)1)));
7180 }
7181
7182 /* #3 */
7183 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7184 val = REG_RD(bp, addr);
7185 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7186
7187 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7188 close ? "closing" : "opening");
7189 mmiowb();
7190}
7191
7192#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7193
7194static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7195{
7196 /* Do some magic... */
7197 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7198 *magic_val = val & SHARED_MF_CLP_MAGIC;
7199 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7200}
7201
e8920674
DK		 7202/**
7203 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7204 *
e8920674
DK		 7205 * @bp: driver handle
7206 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7207 */
7208static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7209{
7210 /* Restore the `magic' bit value... */
72fd0718
VZ		 7211 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7212 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7213 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7214}
7215
f85582f8 7216/**
e8920674 7217 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7218 *
e8920674
DK		 7219 * @bp: driver handle
7220 * @magic_val: old value of 'magic' bit.
7221 *
7222 * Takes care of CLP configurations.
72fd0718
VZ		 7223 */
7224static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7225{
7226 u32 shmem;
7227 u32 validity_offset;
7228
7229 DP(NETIF_MSG_HW, "Starting\n");
7230
7231 /* Set `magic' bit in order to save MF config */
7232 if (!CHIP_IS_E1(bp))
7233 bnx2x_clp_reset_prep(bp, magic_val);
7234
7235 /* Get shmem offset */
7236 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7237 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7238
7239 /* Clear validity map flags */
7240 if (shmem > 0)
7241 REG_WR(bp, shmem + validity_offset, 0);
7242}
7243
7244#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7245#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7246
e8920674
DK		 7247/**
7248 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7249 *
e8920674 7250 * @bp: driver handle
72fd0718
VZ		 7251 */
7252static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7253{
7254 /* special handling for emulation and FPGA,
7255 wait 10 times longer */
7256 if (CHIP_REV_IS_SLOW(bp))
7257 msleep(MCP_ONE_TIMEOUT*10);
7258 else
7259 msleep(MCP_ONE_TIMEOUT);
7260}
7261
1b6e2ceb
DK		 7262/*
7263 * initializes bp->common.shmem_base and waits for validity signature to appear
7264 */
7265static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 7266{
1b6e2ceb
DK		 7267 int cnt = 0;
7268 u32 val = 0;
72fd0718 7269
1b6e2ceb
DK		 7270 do {
7271 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7272 if (bp->common.shmem_base) {
7273 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7274 if (val & SHR_MEM_VALIDITY_MB)
7275 return 0;
7276 }
72fd0718 7277
1b6e2ceb 7278 bnx2x_mcp_wait_one(bp);
72fd0718 7279
1b6e2ceb 7280 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 7281
1b6e2ceb 7282 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 7283
1b6e2ceb
DK		 7284 return -ENODEV;
7285}
72fd0718 7286
1b6e2ceb
DK		 7287static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7288{
7289 int rc = bnx2x_init_shmem(bp);
72fd0718 7290
72fd0718
VZ		 7291 /* Restore the `magic' bit value */
7292 if (!CHIP_IS_E1(bp))
7293 bnx2x_clp_reset_done(bp, magic_val);
7294
7295 return rc;
7296}
7297
7298static void bnx2x_pxp_prep(struct bnx2x *bp)
7299{
7300 if (!CHIP_IS_E1(bp)) {
7301 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7302 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7303 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7304 mmiowb();
7305 }
7306}
7307
7308/*
7309 * Reset the whole chip except for:
7310 * - PCIE core
7311 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7312 * one reset bit)
7313 * - IGU
7314 * - MISC (including AEU)
7315 * - GRC
7316 * - RBCN, RBCP
7317 */
7318static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7319{
7320 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7321
7322 not_reset_mask1 =
7323 MISC_REGISTERS_RESET_REG_1_RST_HC |
7324 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7325 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7326
7327 not_reset_mask2 =
7328 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7329 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7330 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7331 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7332 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7333 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7334 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7335 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7336
7337 reset_mask1 = 0xffffffff;
7338
7339 if (CHIP_IS_E1(bp))
7340 reset_mask2 = 0xffff;
7341 else
7342 reset_mask2 = 0x1ffff;
7343
7344 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7345 reset_mask1 & (~not_reset_mask1));
7346 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7347 reset_mask2 & (~not_reset_mask2));
7348
7349 barrier();
7350 mmiowb();
7351
7352 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7353 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7354 mmiowb();
7355}
7356
7357static int bnx2x_process_kill(struct bnx2x *bp)
7358{
7359 int cnt = 1000;
7360 u32 val = 0;
7361 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7362
7363
7364 /* Empty the Tetris buffer, wait for 1s */
7365 do {
7366 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7367 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7368 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7369 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7370 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7371 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7372 ((port_is_idle_0 & 0x1) == 0x1) &&
7373 ((port_is_idle_1 & 0x1) == 0x1) &&
7374 (pgl_exp_rom2 == 0xffffffff))
7375 break;
7376 msleep(1);
7377 } while (cnt-- > 0);
7378
7379 if (cnt <= 0) {
7380 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7381 " are still"
7382 " outstanding read requests after 1s!\n");
7383 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7384 " port_is_idle_0=0x%08x,"
7385 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7386 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7387 pgl_exp_rom2);
7388 return -EAGAIN;
7389 }
7390
7391 barrier();
7392
7393 /* Close gates #2, #3 and #4 */
7394 bnx2x_set_234_gates(bp, true);
7395
7396 /* TBD: Indicate that "process kill" is in progress to MCP */
7397
7398 /* Clear "unprepared" bit */
7399 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7400 barrier();
7401
7402 /* Make sure all is written to the chip before the reset */
7403 mmiowb();
7404
7405 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7406 * PSWHST, GRC and PSWRD Tetris buffer.
7407 */
7408 msleep(1);
7409
7410 /* Prepare to chip reset: */
7411 /* MCP */
7412 bnx2x_reset_mcp_prep(bp, &val);
7413
7414 /* PXP */
7415 bnx2x_pxp_prep(bp);
7416 barrier();
7417
7418 /* reset the chip */
7419 bnx2x_process_kill_chip_reset(bp);
7420 barrier();
7421
7422 /* Recover after reset: */
7423 /* MCP */
7424 if (bnx2x_reset_mcp_comp(bp, val))
7425 return -EAGAIN;
7426
7427 /* PXP */
7428 bnx2x_pxp_prep(bp);
7429
7430 /* Open the gates #2, #3 and #4 */
7431 bnx2x_set_234_gates(bp, false);
7432
7433 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7434 * reset state, re-enable attentions. */
7435
a2fbb9ea
ET		 7436 return 0;
7437}
7438
72fd0718
VZ		 7439static int bnx2x_leader_reset(struct bnx2x *bp)
7440{
7441 int rc = 0;
7442 /* Try to recover after the failure */
7443 if (bnx2x_process_kill(bp)) {
7444 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7445 bp->dev->name);
7446 rc = -EAGAIN;
7447 goto exit_leader_reset;
7448 }
7449
7450 /* Clear "reset is in progress" bit and update the driver state */
7451 bnx2x_set_reset_done(bp);
7452 bp->recovery_state = BNX2X_RECOVERY_DONE;
7453
7454exit_leader_reset:
7455 bp->is_leader = 0;
7456 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7457 smp_wmb();
7458 return rc;
7459}
7460
72fd0718
VZ		 7461/* Assumption: runs under rtnl lock. This together with the fact
7462 * that it's called only from bnx2x_reset_task() ensure that it
7463 * will never be called when netif_running(bp->dev) is false.
7464 */
7465static void bnx2x_parity_recover(struct bnx2x *bp)
7466{
7467 DP(NETIF_MSG_HW, "Handling parity\n");
7468 while (1) {
7469 switch (bp->recovery_state) {
7470 case BNX2X_RECOVERY_INIT:
7471 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7472 /* Try to get a LEADER_LOCK HW lock */
7473 if (bnx2x_trylock_hw_lock(bp,
7474 HW_LOCK_RESOURCE_RESERVED_08))
7475 bp->is_leader = 1;
7476
7477 /* Stop the driver */
7478 /* If interface has been removed - break */
7479 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7480 return;
7481
7482 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7483 /* Ensure "is_leader" and "recovery_state"
7484 * update values are seen on other CPUs
7485 */
7486 smp_wmb();
7487 break;
7488
7489 case BNX2X_RECOVERY_WAIT:
7490 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7491 if (bp->is_leader) {
7492 u32 load_counter = bnx2x_get_load_cnt(bp);
7493 if (load_counter) {
7494 /* Wait until all other functions get
7495 * down.
7496 */
7497 schedule_delayed_work(&bp->reset_task,
7498 HZ/10);
7499 return;
7500 } else {
7501 /* If all other functions got down -
7502 * try to bring the chip back to
7503 * normal. In any case it's an exit
7504 * point for a leader.
7505 */
7506 if (bnx2x_leader_reset(bp) ||
7507 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7508 printk(KERN_ERR"%s: Recovery "
7509 "has failed. Power cycle is "
7510 "needed.\n", bp->dev->name);
7511 /* Disconnect this device */
7512 netif_device_detach(bp->dev);
7513 /* Block ifup for all function
7514 * of this ASIC until
7515 * "process kill" or power
7516 * cycle.
7517 */
7518 bnx2x_set_reset_in_progress(bp);
7519 /* Shut down the power */
7520 bnx2x_set_power_state(bp,
7521 PCI_D3hot);
7522 return;
7523 }
7524
7525 return;
7526 }
7527 } else { /* non-leader */
7528 if (!bnx2x_reset_is_done(bp)) {
7529 /* Try to get a LEADER_LOCK HW lock as
7530 * long as a former leader may have
7531 * been unloaded by the user or
7532 * released a leadership by another
7533 * reason.
7534 */
7535 if (bnx2x_trylock_hw_lock(bp,
7536 HW_LOCK_RESOURCE_RESERVED_08)) {
7537 /* I'm a leader now! Restart a
7538 * switch case.
7539 */
7540 bp->is_leader = 1;
7541 break;
7542 }
7543
7544 schedule_delayed_work(&bp->reset_task,
7545 HZ/10);
7546 return;
7547
7548 } else { /* A leader has completed
7549 * the "process kill". It's an exit
7550 * point for a non-leader.
7551 */
7552 bnx2x_nic_load(bp, LOAD_NORMAL);
7553 bp->recovery_state =
7554 BNX2X_RECOVERY_DONE;
7555 smp_wmb();
7556 return;
7557 }
7558 }
7559 default:
7560 return;
7561 }
7562 }
7563}
7564
7565/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7566 * scheduled on a general queue in order to prevent a dead lock.
7567 */
34f80b04
EG		 7568static void bnx2x_reset_task(struct work_struct *work)
7569{
72fd0718 7570 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
34f80b04
EG		 7571
7572#ifdef BNX2X_STOP_ON_ERROR
7573 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7574 " so reset not done to allow debug dump,\n"
72fd0718 7575 KERN_ERR " you will need to reboot when done\n");
34f80b04
EG		 7576 return;
7577#endif
7578
7579 rtnl_lock();
7580
7581 if (!netif_running(bp->dev))
7582 goto reset_task_exit;
7583
72fd0718
VZ		 7584 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7585 bnx2x_parity_recover(bp);
7586 else {
7587 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7588 bnx2x_nic_load(bp, LOAD_NORMAL);
7589 }
34f80b04
EG		 7590
7591reset_task_exit:
7592 rtnl_unlock();
7593}
7594
a2fbb9ea
ET		 7595/* end of nic load/unload */
7596
a2fbb9ea
ET		 7597/*
7598 * Init service functions
7599 */
7600
8d96286a 7601static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 7602{
7603 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7604 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7605 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 7606}
7607
f2e0899f 7608static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 7609{
f2e0899f 7610 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 7611
7612 /* Flush all outstanding writes */
7613 mmiowb();
7614
7615 /* Pretend to be function 0 */
7616 REG_WR(bp, reg, 0);
f2e0899f 7617 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 7618
7619 /* From now we are in the "like-E1" mode */
7620 bnx2x_int_disable(bp);
7621
7622 /* Flush all outstanding writes */
7623 mmiowb();
7624
f2e0899f
DK		 7625 /* Restore the original function */
7626 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7627 REG_RD(bp, reg);
f1ef27ef
EG		 7628}
7629
f2e0899f 7630static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 7631{
f2e0899f 7632 if (CHIP_IS_E1(bp))
f1ef27ef 7633 bnx2x_int_disable(bp);
f2e0899f
DK		 7634 else
7635 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 7636}
7637
34f80b04
EG		 7638static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7639{
7640 u32 val;
7641
7642 /* Check if there is any driver already loaded */
7643 val = REG_RD(bp, MISC_REG_UNPREPARED);
7644 if (val == 0x1) {
7645 /* Check if it is the UNDI driver
7646 * UNDI driver initializes CID offset for normal bell to 0x7
7647 */
4a37fb66 7648 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7649 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7650 if (val == 0x7) {
7651 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 7652 /* save our pf_num */
7653 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 7654 int port;
7655 u32 swap_en, swap_val, value;
34f80b04 7656
b4661739
EG		 7657 /* clear the UNDI indication */
7658 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7659
34f80b04
EG		 7660 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7661
7662 /* try unload UNDI on port 0 */
f2e0899f 7663 bp->pf_num = 0;
da5a662a 7664 bp->fw_seq =
f2e0899f 7665 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7666 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 7667 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7668
7669 /* if UNDI is loaded on the other port */
7670 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7671
da5a662a 7672 /* send "DONE" for previous unload */
a22f0788
YR		 7673 bnx2x_fw_command(bp,
7674 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7675
7676 /* unload UNDI on port 1 */
f2e0899f 7677 bp->pf_num = 1;
da5a662a 7678 bp->fw_seq =
f2e0899f 7679 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 7680 DRV_MSG_SEQ_NUMBER_MASK);
7681 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7682
a22f0788 7683 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7684 }
7685
b4661739
EG		 7686 /* now it's safe to release the lock */
7687 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7688
f2e0899f 7689 bnx2x_undi_int_disable(bp);
619c5cb6 7690 port = BP_PORT(bp);
da5a662a
VZ		 7691
7692 /* close input traffic and wait for it */
7693 /* Do not rcv packets to BRB */
619c5cb6
VZ		 7694 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
7695 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 7696 /* Do not direct rcv packets that are not for MCP to
7697 * the BRB */
619c5cb6
VZ		 7698 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7699 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 7700 /* clear AEU */
619c5cb6
VZ		 7701 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7702 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 7703 msleep(10);
7704
7705 /* save NIG port swap info */
7706 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7707 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 7708 /* reset device */
7709 REG_WR(bp,
7710 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 7711 0xd3ffffff);
619c5cb6
VZ		 7712
7713 value = 0x1400;
7714 if (CHIP_IS_E3(bp)) {
7715 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7716 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7717 }
7718
34f80b04
EG		 7719 REG_WR(bp,
7720 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 7721 value);
7722
da5a662a
VZ		 7723 /* take the NIG out of reset and restore swap values */
7724 REG_WR(bp,
7725 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7726 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7727 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7728 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7729
7730 /* send unload done to the MCP */
a22f0788 7731 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7732
7733 /* restore our func and fw_seq */
f2e0899f 7734 bp->pf_num = orig_pf_num;
da5a662a 7735 bp->fw_seq =
f2e0899f 7736 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7737 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 7738 } else
7739 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7740 }
7741}
7742
7743static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7744{
7745 u32 val, val2, val3, val4, id;
72ce58c3 7746 u16 pmc;
34f80b04
EG		 7747
7748 /* Get the chip revision id and number. */
7749 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7750 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7751 id = ((val & 0xffff) << 16);
7752 val = REG_RD(bp, MISC_REG_CHIP_REV);
7753 id |= ((val & 0xf) << 12);
7754 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7755 id |= ((val & 0xff) << 4);
5a40e08e 7756 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 7757 id |= (val & 0xf);
7758 bp->common.chip_id = id;
523224a3
DK		 7759
7760 /* Set doorbell size */
7761 bp->db_size = (1 << BNX2X_DB_SHIFT);
7762
619c5cb6 7763 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7764 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7765 if ((val & 1) == 0)
7766 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7767 else
7768 val = (val >> 1) & 1;
7769 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7770 "2_PORT_MODE");
7771 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7772 CHIP_2_PORT_MODE;
7773
7774 if (CHIP_MODE_IS_4_PORT(bp))
7775 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7776 else
7777 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7778 } else {
7779 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7780 bp->pfid = bp->pf_num; /* 0..7 */
7781 }
7782
f2e0899f
DK		 7783 bp->link_params.chip_id = bp->common.chip_id;
7784 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 7785
1c06328c
EG		 7786 val = (REG_RD(bp, 0x2874) & 0x55);
7787 if ((bp->common.chip_id & 0x1) ||
7788 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7789 bp->flags |= ONE_PORT_FLAG;
7790 BNX2X_DEV_INFO("single port device\n");
7791 }
7792
34f80b04
EG		 7793 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7794 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7795 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7796 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7797 bp->common.flash_size, bp->common.flash_size);
7798
1b6e2ceb
DK		 7799 bnx2x_init_shmem(bp);
7800
619c5cb6
VZ		 7801
7802
f2e0899f
DK		 7803 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7804 MISC_REG_GENERIC_CR_1 :
7805 MISC_REG_GENERIC_CR_0));
1b6e2ceb 7806
34f80b04 7807 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 7808 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 7809 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7810 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 7811
f2e0899f 7812 if (!bp->common.shmem_base) {
34f80b04
EG		 7813 BNX2X_DEV_INFO("MCP not active\n");
7814 bp->flags |= NO_MCP_FLAG;
7815 return;
7816 }
7817
34f80b04 7818 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 7819 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 7820
7821 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7822 SHARED_HW_CFG_LED_MODE_MASK) >>
7823 SHARED_HW_CFG_LED_MODE_SHIFT);
7824
c2c8b03e
EG		 7825 bp->link_params.feature_config_flags = 0;
7826 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7827 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7828 bp->link_params.feature_config_flags |=
7829 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7830 else
7831 bp->link_params.feature_config_flags &=
7832 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7833
34f80b04
EG		 7834 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7835 bp->common.bc_ver = val;
7836 BNX2X_DEV_INFO("bc_ver %X\n", val);
7837 if (val < BNX2X_BC_VER) {
7838 /* for now only warn
7839 * later we might need to enforce this */
f2e0899f
DK		 7840 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7841 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 7842 }
4d295db0 7843 bp->link_params.feature_config_flags |=
a22f0788 7844 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 7845 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7846
a22f0788
YR		 7847 bp->link_params.feature_config_flags |=
7848 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7849 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 7850
f9a3ebbe
DK		 7851 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7852 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7853
72ce58c3 7854 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 7855 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 7856
7857 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7858 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7859 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7860 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7861
cdaa7cb8
VZ		 7862 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7863 val, val2, val3, val4);
34f80b04
EG		 7864}
7865
f2e0899f
DK		 7866#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7867#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7868
7869static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7870{
7871 int pfid = BP_FUNC(bp);
7872 int vn = BP_E1HVN(bp);
7873 int igu_sb_id;
7874 u32 val;
7875 u8 fid;
7876
7877 bp->igu_base_sb = 0xff;
7878 bp->igu_sb_cnt = 0;
7879 if (CHIP_INT_MODE_IS_BC(bp)) {
7880 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
ec6ba945 7881 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7882
7883 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7884 FP_SB_MAX_E1x;
7885
7886 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7887 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7888
7889 return;
7890 }
7891
7892 /* IGU in normal mode - read CAM */
7893 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7894 igu_sb_id++) {
7895 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7896 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7897 continue;
7898 fid = IGU_FID(val);
7899 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7900 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7901 continue;
7902 if (IGU_VEC(val) == 0)
7903 /* default status block */
7904 bp->igu_dsb_id = igu_sb_id;
7905 else {
7906 if (bp->igu_base_sb == 0xff)
7907 bp->igu_base_sb = igu_sb_id;
7908 bp->igu_sb_cnt++;
7909 }
7910 }
7911 }
619c5cb6
VZ		 7912
7913 /* It's expected that number of CAM entries for this
7914 * functions is equal to the MSI-X table size (which was a
7915 * used during bp->l2_cid_count value calculation.
7916 * We want a harsh warning if these values are different!
7917 */
7918 WARN_ON(bp->igu_sb_cnt != NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7919
f2e0899f
DK		 7920 if (bp->igu_sb_cnt == 0)
7921 BNX2X_ERR("CAM configuration error\n");
7922}
7923
34f80b04
EG		 7924static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7925 u32 switch_cfg)
a2fbb9ea 7926{
a22f0788
YR		 7927 int cfg_size = 0, idx, port = BP_PORT(bp);
7928
7929 /* Aggregation of supported attributes of all external phys */
7930 bp->port.supported[0] = 0;
7931 bp->port.supported[1] = 0;
b7737c9b
YR		 7932 switch (bp->link_params.num_phys) {
7933 case 1:
a22f0788
YR		 7934 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
7935 cfg_size = 1;
7936 break;
b7737c9b 7937 case 2:
a22f0788
YR		 7938 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
7939 cfg_size = 1;
7940 break;
7941 case 3:
7942 if (bp->link_params.multi_phy_config &
7943 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
7944 bp->port.supported[1] =
7945 bp->link_params.phy[EXT_PHY1].supported;
7946 bp->port.supported[0] =
7947 bp->link_params.phy[EXT_PHY2].supported;
7948 } else {
7949 bp->port.supported[0] =
7950 bp->link_params.phy[EXT_PHY1].supported;
7951 bp->port.supported[1] =
7952 bp->link_params.phy[EXT_PHY2].supported;
7953 }
7954 cfg_size = 2;
7955 break;
b7737c9b 7956 }
a2fbb9ea 7957
a22f0788 7958 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 7959 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 7960 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 7961 SHMEM_RD(bp,
a22f0788
YR		 7962 dev_info.port_hw_config[port].external_phy_config),
7963 SHMEM_RD(bp,
7964 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 7965 return;
f85582f8 7966 }
a2fbb9ea 7967
619c5cb6
VZ		 7968 if (CHIP_IS_E3(bp))
7969 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
7970 else {
7971 switch (switch_cfg) {
7972 case SWITCH_CFG_1G:
7973 bp->port.phy_addr = REG_RD(
7974 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
7975 break;
7976 case SWITCH_CFG_10G:
7977 bp->port.phy_addr = REG_RD(
7978 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
7979 break;
7980 default:
7981 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
7982 bp->port.link_config[0]);
7983 return;
7984 }
a2fbb9ea 7985 }
619c5cb6 7986 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 7987 /* mask what we support according to speed_cap_mask per configuration */
7988 for (idx = 0; idx < cfg_size; idx++) {
7989 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7990 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 7991 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 7992
a22f0788 7993 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7994 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 7995 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 7996
a22f0788 7997 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 7998 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 7999 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8000
a22f0788 8001 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8002 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8003 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8004
a22f0788 8005 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8006 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8007 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8008 SUPPORTED_1000baseT_Full);
a2fbb9ea 8009
a22f0788 8010 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8011 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8012 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8013
a22f0788 8014 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8015 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8016 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8017
8018 }
a2fbb9ea 8019
a22f0788
YR		 8020 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8021 bp->port.supported[1]);
a2fbb9ea
ET		 8022}
8023
34f80b04 8024static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8025{
a22f0788
YR		 8026 u32 link_config, idx, cfg_size = 0;
8027 bp->port.advertising[0] = 0;
8028 bp->port.advertising[1] = 0;
8029 switch (bp->link_params.num_phys) {
8030 case 1:
8031 case 2:
8032 cfg_size = 1;
8033 break;
8034 case 3:
8035 cfg_size = 2;
8036 break;
8037 }
8038 for (idx = 0; idx < cfg_size; idx++) {
8039 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8040 link_config = bp->port.link_config[idx];
8041 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8042 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8043 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8044 bp->link_params.req_line_speed[idx] =
8045 SPEED_AUTO_NEG;
8046 bp->port.advertising[idx] |=
8047 bp->port.supported[idx];
f85582f8
DK		 8048 } else {
8049 /* force 10G, no AN */
a22f0788
YR		 8050 bp->link_params.req_line_speed[idx] =
8051 SPEED_10000;
8052 bp->port.advertising[idx] |=
8053 (ADVERTISED_10000baseT_Full |
f85582f8 8054 ADVERTISED_FIBRE);
a22f0788 8055 continue;
f85582f8
DK		 8056 }
8057 break;
a2fbb9ea 8058
f85582f8 8059 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8060 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8061 bp->link_params.req_line_speed[idx] =
8062 SPEED_10;
8063 bp->port.advertising[idx] |=
8064 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8065 ADVERTISED_TP);
8066 } else {
8067 BNX2X_ERROR("NVRAM config error. "
8068 "Invalid link_config 0x%x"
8069 " speed_cap_mask 0x%x\n",
8070 link_config,
a22f0788 8071 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8072 return;
8073 }
8074 break;
a2fbb9ea 8075
f85582f8 8076 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8077 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8078 bp->link_params.req_line_speed[idx] =
8079 SPEED_10;
8080 bp->link_params.req_duplex[idx] =
8081 DUPLEX_HALF;
8082 bp->port.advertising[idx] |=
8083 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8084 ADVERTISED_TP);
8085 } else {
8086 BNX2X_ERROR("NVRAM config error. "
8087 "Invalid link_config 0x%x"
8088 " speed_cap_mask 0x%x\n",
8089 link_config,
8090 bp->link_params.speed_cap_mask[idx]);
8091 return;
8092 }
8093 break;
a2fbb9ea 8094
f85582f8
DK		 8095 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8096 if (bp->port.supported[idx] &
8097 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8098 bp->link_params.req_line_speed[idx] =
8099 SPEED_100;
8100 bp->port.advertising[idx] |=
8101 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8102 ADVERTISED_TP);
8103 } else {
8104 BNX2X_ERROR("NVRAM config error. "
8105 "Invalid link_config 0x%x"
8106 " speed_cap_mask 0x%x\n",
8107 link_config,
8108 bp->link_params.speed_cap_mask[idx]);
8109 return;
8110 }
8111 break;
a2fbb9ea 8112
f85582f8
DK		 8113 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8114 if (bp->port.supported[idx] &
8115 SUPPORTED_100baseT_Half) {
8116 bp->link_params.req_line_speed[idx] =
8117 SPEED_100;
8118 bp->link_params.req_duplex[idx] =
8119 DUPLEX_HALF;
a22f0788
YR		 8120 bp->port.advertising[idx] |=
8121 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8122 ADVERTISED_TP);
8123 } else {
8124 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8125 "Invalid link_config 0x%x"
8126 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8127 link_config,
8128 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8129 return;
8130 }
8131 break;
a2fbb9ea 8132
f85582f8 8133 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 8134 if (bp->port.supported[idx] &
8135 SUPPORTED_1000baseT_Full) {
8136 bp->link_params.req_line_speed[idx] =
8137 SPEED_1000;
8138 bp->port.advertising[idx] |=
8139 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 8140 ADVERTISED_TP);
8141 } else {
8142 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8143 "Invalid link_config 0x%x"
8144 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8145 link_config,
8146 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8147 return;
8148 }
8149 break;
a2fbb9ea 8150
f85582f8 8151 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 8152 if (bp->port.supported[idx] &
8153 SUPPORTED_2500baseX_Full) {
8154 bp->link_params.req_line_speed[idx] =
8155 SPEED_2500;
8156 bp->port.advertising[idx] |=
8157 (ADVERTISED_2500baseX_Full |
34f80b04 8158 ADVERTISED_TP);
f85582f8
DK		 8159 } else {
8160 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8161 "Invalid link_config 0x%x"
8162 " speed_cap_mask 0x%x\n",
a22f0788 8163 link_config,
f85582f8
DK		 8164 bp->link_params.speed_cap_mask[idx]);
8165 return;
8166 }
8167 break;
a2fbb9ea 8168
f85582f8 8169 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 8170 if (bp->port.supported[idx] &
8171 SUPPORTED_10000baseT_Full) {
8172 bp->link_params.req_line_speed[idx] =
8173 SPEED_10000;
8174 bp->port.advertising[idx] |=
8175 (ADVERTISED_10000baseT_Full |
34f80b04 8176 ADVERTISED_FIBRE);
f85582f8
DK		 8177 } else {
8178 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8179 "Invalid link_config 0x%x"
8180 " speed_cap_mask 0x%x\n",
a22f0788 8181 link_config,
f85582f8
DK		 8182 bp->link_params.speed_cap_mask[idx]);
8183 return;
8184 }
8185 break;
a2fbb9ea 8186
f85582f8
DK		 8187 default:
8188 BNX2X_ERROR("NVRAM config error. "
8189 "BAD link speed link_config 0x%x\n",
8190 link_config);
8191 bp->link_params.req_line_speed[idx] =
8192 SPEED_AUTO_NEG;
8193 bp->port.advertising[idx] =
8194 bp->port.supported[idx];
8195 break;
8196 }
a2fbb9ea 8197
a22f0788 8198 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 8199 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 8200 if ((bp->link_params.req_flow_ctrl[idx] ==
8201 BNX2X_FLOW_CTRL_AUTO) &&
8202 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8203 bp->link_params.req_flow_ctrl[idx] =
8204 BNX2X_FLOW_CTRL_NONE;
8205 }
a2fbb9ea 8206
a22f0788
YR		 8207 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8208 " 0x%x advertising 0x%x\n",
8209 bp->link_params.req_line_speed[idx],
8210 bp->link_params.req_duplex[idx],
8211 bp->link_params.req_flow_ctrl[idx],
8212 bp->port.advertising[idx]);
8213 }
a2fbb9ea
ET		 8214}
8215
e665bfda
MC		 8216static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8217{
8218 mac_hi = cpu_to_be16(mac_hi);
8219 mac_lo = cpu_to_be32(mac_lo);
8220 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8221 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8222}
8223
34f80b04 8224static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 8225{
34f80b04 8226 int port = BP_PORT(bp);
589abe3a 8227 u32 config;
6f38ad93 8228 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 8229
c18487ee 8230 bp->link_params.bp = bp;
34f80b04 8231 bp->link_params.port = port;
c18487ee 8232
c18487ee 8233 bp->link_params.lane_config =
a2fbb9ea 8234 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 8235
a22f0788 8236 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 8237 SHMEM_RD(bp,
8238 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 8239 bp->link_params.speed_cap_mask[1] =
8240 SHMEM_RD(bp,
8241 dev_info.port_hw_config[port].speed_capability_mask2);
8242 bp->port.link_config[0] =
a2fbb9ea
ET		 8243 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8244
a22f0788
YR		 8245 bp->port.link_config[1] =
8246 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 8247
a22f0788
YR		 8248 bp->link_params.multi_phy_config =
8249 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 8250 /* If the device is capable of WoL, set the default state according
8251 * to the HW
8252 */
4d295db0 8253 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 8254 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8255 (config & PORT_FEATURE_WOL_ENABLED));
8256
f85582f8 8257 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 8258 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 8259 bp->link_params.lane_config,
a22f0788
YR		 8260 bp->link_params.speed_cap_mask[0],
8261 bp->port.link_config[0]);
a2fbb9ea 8262
a22f0788 8263 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 8264 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 8265 bnx2x_phy_probe(&bp->link_params);
c18487ee 8266 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 8267
8268 bnx2x_link_settings_requested(bp);
8269
01cd4528
EG		 8270 /*
8271 * If connected directly, work with the internal PHY, otherwise, work
8272 * with the external PHY
8273 */
b7737c9b
YR		 8274 ext_phy_config =
8275 SHMEM_RD(bp,
8276 dev_info.port_hw_config[port].external_phy_config);
8277 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 8278 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 8279 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 8280
8281 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8282 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8283 bp->mdio.prtad =
b7737c9b 8284 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 8285
8286 /*
8287 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8288 * In MF mode, it is set to cover self test cases
8289 */
8290 if (IS_MF(bp))
8291 bp->port.need_hw_lock = 1;
8292 else
8293 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8294 bp->common.shmem_base,
8295 bp->common.shmem2_base);
0793f83f 8296}
01cd4528 8297
2ba45142
VZ		 8298#ifdef BCM_CNIC
8299static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8300{
8301 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8302 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8303 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8304 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8305
8306 /* Get the number of maximum allowed iSCSI and FCoE connections */
8307 bp->cnic_eth_dev.max_iscsi_conn =
8308 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8309 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8310
8311 bp->cnic_eth_dev.max_fcoe_conn =
8312 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8313 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8314
8315 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8316 bp->cnic_eth_dev.max_iscsi_conn,
8317 bp->cnic_eth_dev.max_fcoe_conn);
8318
8319 /* If mamimum allowed number of connections is zero -
8320 * disable the feature.
8321 */
8322 if (!bp->cnic_eth_dev.max_iscsi_conn)
8323 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8324
8325 if (!bp->cnic_eth_dev.max_fcoe_conn)
8326 bp->flags |= NO_FCOE_FLAG;
8327}
8328#endif
8329
0793f83f
DK		 8330static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8331{
8332 u32 val, val2;
8333 int func = BP_ABS_FUNC(bp);
8334 int port = BP_PORT(bp);
2ba45142
VZ		 8335#ifdef BCM_CNIC
8336 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8337 u8 *fip_mac = bp->fip_mac;
8338#endif
0793f83f 8339
619c5cb6
VZ		 8340 /* Zero primary MAC configuration */
8341 memset(bp->dev->dev_addr, 0, ETH_ALEN);
8342
0793f83f
DK		 8343 if (BP_NOMCP(bp)) {
8344 BNX2X_ERROR("warning: random MAC workaround active\n");
8345 random_ether_addr(bp->dev->dev_addr);
8346 } else if (IS_MF(bp)) {
8347 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8348 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8349 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8350 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8351 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 8352
8353#ifdef BCM_CNIC
2ba45142
VZ		 8354 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8355 * FCoE MAC then the appropriate feature should be disabled.
8356 */
0793f83f
DK		 8357 if (IS_MF_SI(bp)) {
8358 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8359 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8360 val2 = MF_CFG_RD(bp, func_ext_config[func].
8361 iscsi_mac_addr_upper);
8362 val = MF_CFG_RD(bp, func_ext_config[func].
8363 iscsi_mac_addr_lower);
2ba45142 8364 bnx2x_set_mac_buf(iscsi_mac, val, val2);
619c5cb6
VZ		 8365 BNX2X_DEV_INFO("Read iSCSI MAC: "
8366 BNX2X_MAC_FMT"\n",
8367 BNX2X_MAC_PRN_LIST(iscsi_mac));
2ba45142
VZ		 8368 } else
8369 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8370
8371 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8372 val2 = MF_CFG_RD(bp, func_ext_config[func].
8373 fcoe_mac_addr_upper);
8374 val = MF_CFG_RD(bp, func_ext_config[func].
8375 fcoe_mac_addr_lower);
2ba45142 8376 bnx2x_set_mac_buf(fip_mac, val, val2);
619c5cb6
VZ		 8377 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
8378 BNX2X_MAC_FMT"\n",
8379 BNX2X_MAC_PRN_LIST(fip_mac));
2ba45142 8380
2ba45142
VZ		 8381 } else
8382 bp->flags |= NO_FCOE_FLAG;
0793f83f 8383 }
37b091ba 8384#endif
0793f83f
DK		 8385 } else {
8386 /* in SF read MACs from port configuration */
8387 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8388 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8389 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8390
8391#ifdef BCM_CNIC
8392 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8393 iscsi_mac_upper);
8394 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8395 iscsi_mac_lower);
2ba45142 8396 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0793f83f
DK		 8397#endif
8398 }
8399
8400 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8401 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8402
ec6ba945 8403#ifdef BCM_CNIC
2ba45142 8404 /* Set the FCoE MAC in modes other then MF_SI */
ec6ba945
VZ		 8405 if (!CHIP_IS_E1x(bp)) {
8406 if (IS_MF_SD(bp))
2ba45142
VZ		 8407 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8408 else if (!IS_MF(bp))
8409 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
ec6ba945 8410 }
426b9241
DK		 8411
8412 /* Disable iSCSI if MAC configuration is
8413 * invalid.
8414 */
8415 if (!is_valid_ether_addr(iscsi_mac)) {
8416 bp->flags |= NO_ISCSI_FLAG;
8417 memset(iscsi_mac, 0, ETH_ALEN);
8418 }
8419
8420 /* Disable FCoE if MAC configuration is
8421 * invalid.
8422 */
8423 if (!is_valid_ether_addr(fip_mac)) {
8424 bp->flags |= NO_FCOE_FLAG;
8425 memset(bp->fip_mac, 0, ETH_ALEN);
8426 }
ec6ba945 8427#endif
619c5cb6
VZ		 8428
8429 if (!is_valid_ether_addr(bp->dev->dev_addr))
8430 dev_err(&bp->pdev->dev,
8431 "bad Ethernet MAC address configuration: "
8432 BNX2X_MAC_FMT", change it manually before bringing up "
8433 "the appropriate network interface\n",
8434 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
34f80b04
EG		 8435}
8436
8437static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8438{
0793f83f 8439 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 8440 int vn;
0793f83f 8441 u32 val = 0;
34f80b04 8442 int rc = 0;
a2fbb9ea 8443
34f80b04 8444 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 8445
f2e0899f
DK		 8446 if (CHIP_IS_E1x(bp)) {
8447 bp->common.int_block = INT_BLOCK_HC;
8448
8449 bp->igu_dsb_id = DEF_SB_IGU_ID;
8450 bp->igu_base_sb = 0;
ec6ba945
VZ		 8451 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8452 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8453 } else {
8454 bp->common.int_block = INT_BLOCK_IGU;
8455 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 8456
8457 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8458 int tout = 5000;
8459
8460 BNX2X_DEV_INFO("FORCING Normal Mode\n");
8461
8462 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8463 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
8464 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
8465
8466 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
8467 tout--;
8468 usleep_range(1000, 1000);
8469 }
8470
8471 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
8472 dev_err(&bp->pdev->dev,
8473 "FORCING Normal Mode failed!!!\n");
8474 return -EPERM;
8475 }
8476 }
8477
f2e0899f 8478 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 8479 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 8480 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8481 } else
619c5cb6 8482 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 8483
f2e0899f
DK		 8484 bnx2x_get_igu_cam_info(bp);
8485
8486 }
619c5cb6
VZ		 8487
8488 /*
8489 * set base FW non-default (fast path) status block id, this value is
8490 * used to initialize the fw_sb_id saved on the fp/queue structure to
8491 * determine the id used by the FW.
8492 */
8493 if (CHIP_IS_E1x(bp))
8494 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
8495 else /*
8496 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
8497 * the same queue are indicated on the same IGU SB). So we prefer
8498 * FW and IGU SBs to be the same value.
8499 */
8500 bp->base_fw_ndsb = bp->igu_base_sb;
8501
8502 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
8503 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
8504 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 8505
8506 /*
8507 * Initialize MF configuration
8508 */
523224a3 8509
fb3bff17
DK		 8510 bp->mf_ov = 0;
8511 bp->mf_mode = 0;
f2e0899f 8512 vn = BP_E1HVN(bp);
0793f83f 8513
f2e0899f 8514 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 8515 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
8516 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8517 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8518
f2e0899f
DK		 8519 if (SHMEM2_HAS(bp, mf_cfg_addr))
8520 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8521 else
8522 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 8523 offsetof(struct shmem_region, func_mb) +
8524 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 8525 /*
8526 * get mf configuration:
25985edc 8527 * 1. existence of MF configuration
0793f83f
DK		 8528 * 2. MAC address must be legal (check only upper bytes)
8529 * for Switch-Independent mode;
8530 * OVLAN must be legal for Switch-Dependent mode
8531 * 3. SF_MODE configures specific MF mode
8532 */
8533 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8534 /* get mf configuration */
8535 val = SHMEM_RD(bp,
8536 dev_info.shared_feature_config.config);
8537 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8538
8539 switch (val) {
8540 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8541 val = MF_CFG_RD(bp, func_mf_config[func].
8542 mac_upper);
8543 /* check for legal mac (upper bytes)*/
8544 if (val != 0xffff) {
8545 bp->mf_mode = MULTI_FUNCTION_SI;
8546 bp->mf_config[vn] = MF_CFG_RD(bp,
8547 func_mf_config[func].config);
8548 } else
619c5cb6
VZ		 8549 BNX2X_DEV_INFO("illegal MAC address "
8550 "for SI\n");
0793f83f
DK		 8551 break;
8552 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8553 /* get OV configuration */
8554 val = MF_CFG_RD(bp,
8555 func_mf_config[FUNC_0].e1hov_tag);
8556 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8557
8558 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8559 bp->mf_mode = MULTI_FUNCTION_SD;
8560 bp->mf_config[vn] = MF_CFG_RD(bp,
8561 func_mf_config[func].config);
8562 } else
8563 DP(NETIF_MSG_PROBE, "illegal OV for "
8564 "SD\n");
8565 break;
8566 default:
8567 /* Unknown configuration: reset mf_config */
8568 bp->mf_config[vn] = 0;
25985edc 8569 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
0793f83f
DK		 8570 val);
8571 }
8572 }
a2fbb9ea 8573
2691d51d 8574 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 8575 IS_MF(bp) ? "multi" : "single");
2691d51d 8576
0793f83f
DK		 8577 switch (bp->mf_mode) {
8578 case MULTI_FUNCTION_SD:
8579 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8580 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 8581 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 8582 bp->mf_ov = val;
619c5cb6
VZ		 8583 bp->path_has_ovlan = true;
8584
8585 BNX2X_DEV_INFO("MF OV for func %d is %d "
8586 "(0x%04x)\n", func, bp->mf_ov,
8587 bp->mf_ov);
2691d51d 8588 } else {
619c5cb6
VZ		 8589 dev_err(&bp->pdev->dev,
8590 "No valid MF OV for func %d, "
8591 "aborting\n", func);
8592 return -EPERM;
34f80b04 8593 }
0793f83f
DK		 8594 break;
8595 case MULTI_FUNCTION_SI:
8596 BNX2X_DEV_INFO("func %d is in MF "
8597 "switch-independent mode\n", func);
8598 break;
8599 default:
8600 if (vn) {
619c5cb6
VZ		 8601 dev_err(&bp->pdev->dev,
8602 "VN %d is in a single function mode, "
8603 "aborting\n", vn);
8604 return -EPERM;
2691d51d 8605 }
0793f83f 8606 break;
34f80b04 8607 }
0793f83f 8608
619c5cb6
VZ		 8609 /* check if other port on the path needs ovlan:
8610 * Since MF configuration is shared between ports
8611 * Possible mixed modes are only
8612 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
8613 */
8614 if (CHIP_MODE_IS_4_PORT(bp) &&
8615 !bp->path_has_ovlan &&
8616 !IS_MF(bp) &&
8617 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8618 u8 other_port = !BP_PORT(bp);
8619 u8 other_func = BP_PATH(bp) + 2*other_port;
8620 val = MF_CFG_RD(bp,
8621 func_mf_config[other_func].e1hov_tag);
8622 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
8623 bp->path_has_ovlan = true;
8624 }
34f80b04 8625 }
a2fbb9ea 8626
f2e0899f
DK		 8627 /* adjust igu_sb_cnt to MF for E1x */
8628 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 8629 bp->igu_sb_cnt /= E1HVN_MAX;
8630
619c5cb6
VZ		 8631 /* port info */
8632 bnx2x_get_port_hwinfo(bp);
f2e0899f 8633
34f80b04 8634 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 8635 bp->fw_seq =
8636 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8637 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 8638 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8639 }
8640
0793f83f
DK		 8641 /* Get MAC addresses */
8642 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 8643
2ba45142
VZ		 8644#ifdef BCM_CNIC
8645 bnx2x_get_cnic_info(bp);
8646#endif
8647
619c5cb6
VZ		 8648 /* Get current FW pulse sequence */
8649 if (!BP_NOMCP(bp)) {
8650 int mb_idx = BP_FW_MB_IDX(bp);
8651
8652 bp->fw_drv_pulse_wr_seq =
8653 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
8654 DRV_PULSE_SEQ_MASK);
8655 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
8656 }
8657
34f80b04
EG		 8658 return rc;
8659}
8660
34f24c7f
VZ		 8661static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8662{
8663 int cnt, i, block_end, rodi;
8664 char vpd_data[BNX2X_VPD_LEN+1];
8665 char str_id_reg[VENDOR_ID_LEN+1];
8666 char str_id_cap[VENDOR_ID_LEN+1];
8667 u8 len;
8668
8669 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8670 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8671
8672 if (cnt < BNX2X_VPD_LEN)
8673 goto out_not_found;
8674
8675 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8676 PCI_VPD_LRDT_RO_DATA);
8677 if (i < 0)
8678 goto out_not_found;
8679
8680
8681 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8682 pci_vpd_lrdt_size(&vpd_data[i]);
8683
8684 i += PCI_VPD_LRDT_TAG_SIZE;
8685
8686 if (block_end > BNX2X_VPD_LEN)
8687 goto out_not_found;
8688
8689 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8690 PCI_VPD_RO_KEYWORD_MFR_ID);
8691 if (rodi < 0)
8692 goto out_not_found;
8693
8694 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8695
8696 if (len != VENDOR_ID_LEN)
8697 goto out_not_found;
8698
8699 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8700
8701 /* vendor specific info */
8702 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8703 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8704 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8705 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8706
8707 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8708 PCI_VPD_RO_KEYWORD_VENDOR0);
8709 if (rodi >= 0) {
8710 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8711
8712 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8713
8714 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8715 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8716 bp->fw_ver[len] = ' ';
8717 }
8718 }
8719 return;
8720 }
8721out_not_found:
8722 return;
8723}
8724
619c5cb6
VZ		 8725static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
8726{
8727 u32 flags = 0;
8728
8729 if (CHIP_REV_IS_FPGA(bp))
8730 SET_FLAGS(flags, MODE_FPGA);
8731 else if (CHIP_REV_IS_EMUL(bp))
8732 SET_FLAGS(flags, MODE_EMUL);
8733 else
8734 SET_FLAGS(flags, MODE_ASIC);
8735
8736 if (CHIP_MODE_IS_4_PORT(bp))
8737 SET_FLAGS(flags, MODE_PORT4);
8738 else
8739 SET_FLAGS(flags, MODE_PORT2);
8740
8741 if (CHIP_IS_E2(bp))
8742 SET_FLAGS(flags, MODE_E2);
8743 else if (CHIP_IS_E3(bp)) {
8744 SET_FLAGS(flags, MODE_E3);
8745 if (CHIP_REV(bp) == CHIP_REV_Ax)
8746 SET_FLAGS(flags, MODE_E3_A0);
8747 else {/*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
8748 SET_FLAGS(flags, MODE_E3_B0);
8749 SET_FLAGS(flags, MODE_COS_BC);
8750 }
8751 }
8752
8753 if (IS_MF(bp)) {
8754 SET_FLAGS(flags, MODE_MF);
8755 switch (bp->mf_mode) {
8756 case MULTI_FUNCTION_SD:
8757 SET_FLAGS(flags, MODE_MF_SD);
8758 break;
8759 case MULTI_FUNCTION_SI:
8760 SET_FLAGS(flags, MODE_MF_SI);
8761 break;
8762 }
8763 } else
8764 SET_FLAGS(flags, MODE_SF);
8765
8766#if defined(__LITTLE_ENDIAN)
8767 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
8768#else /*(__BIG_ENDIAN)*/
8769 SET_FLAGS(flags, MODE_BIG_ENDIAN);
8770#endif
8771 INIT_MODE_FLAGS(bp) = flags;
8772}
8773
34f80b04
EG		 8774static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8775{
f2e0899f 8776 int func;
87942b46 8777 int timer_interval;
34f80b04
EG		 8778 int rc;
8779
34f80b04 8780 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 8781 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 8782 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 8783#ifdef BCM_CNIC
8784 mutex_init(&bp->cnic_mutex);
8785#endif
a2fbb9ea 8786
1cf167f2 8787 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
72fd0718 8788 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
34f80b04
EG		 8789
8790 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 8791 if (rc)
8792 return rc;
34f80b04 8793
619c5cb6
VZ		 8794 bnx2x_set_modes_bitmap(bp);
8795
8796 rc = bnx2x_alloc_mem_bp(bp);
8797 if (rc)
8798 return rc;
523224a3 8799
34f24c7f 8800 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 8801
8802 func = BP_FUNC(bp);
8803
34f80b04
EG		 8804 /* need to reset chip if undi was active */
8805 if (!BP_NOMCP(bp))
8806 bnx2x_undi_unload(bp);
8807
8808 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 8809 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 8810
8811 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 8812 dev_err(&bp->pdev->dev, "MCP disabled, "
8813 "must load devices in order!\n");
34f80b04 8814
555f6c78 8815 bp->multi_mode = multi_mode;
555f6c78 8816
7a9b2557
VZ		 8817 /* Set TPA flags */
8818 if (disable_tpa) {
8819 bp->flags &= ~TPA_ENABLE_FLAG;
8820 bp->dev->features &= ~NETIF_F_LRO;
8821 } else {
8822 bp->flags |= TPA_ENABLE_FLAG;
8823 bp->dev->features |= NETIF_F_LRO;
8824 }
5d7cd496 8825 bp->disable_tpa = disable_tpa;
7a9b2557 8826
a18f5128
EG		 8827 if (CHIP_IS_E1(bp))
8828 bp->dropless_fc = 0;
8829 else
8830 bp->dropless_fc = dropless_fc;
8831
8d5726c4 8832 bp->mrrs = mrrs;
7a9b2557 8833
34f80b04 8834 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 8835
7d323bfd 8836 /* make sure that the numbers are in the right granularity */
523224a3
DK		 8837 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8838 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 8839
87942b46
EG		 8840 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8841 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 8842
8843 init_timer(&bp->timer);
8844 bp->timer.expires = jiffies + bp->current_interval;
8845 bp->timer.data = (unsigned long) bp;
8846 bp->timer.function = bnx2x_timer;
8847
785b9b1a 8848 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 8849 bnx2x_dcbx_init_params(bp);
8850
619c5cb6
VZ		 8851#ifdef BCM_CNIC
8852 if (CHIP_IS_E1x(bp))
8853 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
8854 else
8855 bp->cnic_base_cl_id = FP_SB_MAX_E2;
8856#endif
8857
34f80b04 8858 return rc;
a2fbb9ea
ET		 8859}
8860
a2fbb9ea 8861
de0c62db
DK		 8862/****************************************************************************
8863* General service functions
8864****************************************************************************/
a2fbb9ea 8865
619c5cb6
VZ		 8866/*
8867 * net_device service functions
8868 */
8869
bb2a0f7a 8870/* called with rtnl_lock */
a2fbb9ea
ET		 8871static int bnx2x_open(struct net_device *dev)
8872{
8873 struct bnx2x *bp = netdev_priv(dev);
8874
6eccabb3
EG		 8875 netif_carrier_off(dev);
8876
a2fbb9ea
ET		 8877 bnx2x_set_power_state(bp, PCI_D0);
8878
72fd0718
VZ		 8879 if (!bnx2x_reset_is_done(bp)) {
8880 do {
8881 /* Reset MCP mail box sequence if there is on going
8882 * recovery
8883 */
8884 bp->fw_seq = 0;
8885
8886 /* If it's the first function to load and reset done
8887 * is still not cleared it may mean that. We don't
8888 * check the attention state here because it may have
8889 * already been cleared by a "common" reset but we
8890 * shell proceed with "process kill" anyway.
8891 */
8892 if ((bnx2x_get_load_cnt(bp) == 0) &&
8893 bnx2x_trylock_hw_lock(bp,
8894 HW_LOCK_RESOURCE_RESERVED_08) &&
8895 (!bnx2x_leader_reset(bp))) {
8896 DP(NETIF_MSG_HW, "Recovered in open\n");
8897 break;
8898 }
8899
8900 bnx2x_set_power_state(bp, PCI_D3hot);
8901
8902 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8903 " completed yet. Try again later. If u still see this"
8904 " message after a few retries then power cycle is"
8905 " required.\n", bp->dev->name);
8906
8907 return -EAGAIN;
8908 } while (0);
8909 }
8910
8911 bp->recovery_state = BNX2X_RECOVERY_DONE;
8912
bb2a0f7a 8913 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 8914}
8915
bb2a0f7a 8916/* called with rtnl_lock */
a2fbb9ea
ET		 8917static int bnx2x_close(struct net_device *dev)
8918{
a2fbb9ea
ET		 8919 struct bnx2x *bp = netdev_priv(dev);
8920
8921 /* Unload the driver, release IRQs */
bb2a0f7a 8922 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
d3dbfee0 8923 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 8924
8925 return 0;
8926}
8927
619c5cb6
VZ		 8928static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
8929 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 8930{
619c5cb6
VZ		 8931 int mc_count = netdev_mc_count(bp->dev);
8932 struct bnx2x_mcast_list_elem *mc_mac =
8933 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
8934 struct netdev_hw_addr *ha;
6e30dd4e 8935
619c5cb6
VZ		 8936 if (!mc_mac)
8937 return -ENOMEM;
6e30dd4e 8938
619c5cb6 8939 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 8940
619c5cb6
VZ		 8941 netdev_for_each_mc_addr(ha, bp->dev) {
8942 mc_mac->mac = bnx2x_mc_addr(ha);
8943 list_add_tail(&mc_mac->link, &p->mcast_list);
8944 mc_mac++;
6e30dd4e 8945 }
619c5cb6
VZ		 8946
8947 p->mcast_list_len = mc_count;
8948
8949 return 0;
6e30dd4e
VZ		 8950}
8951
619c5cb6
VZ		 8952static inline void bnx2x_free_mcast_macs_list(
8953 struct bnx2x_mcast_ramrod_params *p)
8954{
8955 struct bnx2x_mcast_list_elem *mc_mac =
8956 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
8957 link);
8958
8959 WARN_ON(!mc_mac);
8960 kfree(mc_mac);
8961}
8962
8963/**
8964 * bnx2x_set_uc_list - configure a new unicast MACs list.
8965 *
8966 * @bp: driver handle
6e30dd4e 8967 *
619c5cb6 8968 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 8969 */
619c5cb6 8970static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 8971{
619c5cb6 8972 int rc;
6e30dd4e 8973 struct net_device *dev = bp->dev;
6e30dd4e 8974 struct netdev_hw_addr *ha;
619c5cb6
VZ		 8975 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
8976 unsigned long ramrod_flags = 0;
6e30dd4e 8977
619c5cb6
VZ		 8978 /* First schedule a cleanup up of old configuration */
8979 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
8980 if (rc < 0) {
8981 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
8982 return rc;
8983 }
6e30dd4e
VZ		 8984
8985 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 8986 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
8987 BNX2X_UC_LIST_MAC, &ramrod_flags);
8988 if (rc < 0) {
8989 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
8990 rc);
8991 return rc;
6e30dd4e
VZ		 8992 }
8993 }
8994
619c5cb6
VZ		 8995 /* Execute the pending commands */
8996 __set_bit(RAMROD_CONT, &ramrod_flags);
8997 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
8998 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 8999}
9000
619c5cb6 9001static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 9002{
619c5cb6
VZ		 9003 struct net_device *dev = bp->dev;
9004 struct bnx2x_mcast_ramrod_params rparam = {0};
9005 int rc = 0;
6e30dd4e 9006
619c5cb6 9007 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 9008
619c5cb6
VZ		 9009 /* first, clear all configured multicast MACs */
9010 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9011 if (rc < 0) {
9012 BNX2X_ERR("Failed to clear multicast "
9013 "configuration: %d\n", rc);
9014 return rc;
9015 }
6e30dd4e 9016
619c5cb6
VZ		 9017 /* then, configure a new MACs list */
9018 if (netdev_mc_count(dev)) {
9019 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9020 if (rc) {
9021 BNX2X_ERR("Failed to create multicast MACs "
9022 "list: %d\n", rc);
9023 return rc;
9024 }
6e30dd4e 9025
619c5cb6
VZ		 9026 /* Now add the new MACs */
9027 rc = bnx2x_config_mcast(bp, &rparam,
9028 BNX2X_MCAST_CMD_ADD);
9029 if (rc < 0)
9030 BNX2X_ERR("Failed to set a new multicast "
9031 "configuration: %d\n", rc);
6e30dd4e 9032
619c5cb6
VZ		 9033 bnx2x_free_mcast_macs_list(&rparam);
9034 }
6e30dd4e 9035
619c5cb6 9036 return rc;
6e30dd4e
VZ		 9037}
9038
6e30dd4e 9039
619c5cb6 9040/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 9041void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 9042{
9043 struct bnx2x *bp = netdev_priv(dev);
9044 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 9045
9046 if (bp->state != BNX2X_STATE_OPEN) {
9047 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9048 return;
9049 }
9050
619c5cb6 9051 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 9052
9053 if (dev->flags & IFF_PROMISC)
9054 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 9055 else if ((dev->flags & IFF_ALLMULTI) ||
9056 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
9057 CHIP_IS_E1(bp)))
34f80b04 9058 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 9059 else {
9060 /* some multicasts */
619c5cb6 9061 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 9062 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 9063
619c5cb6 9064 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 9065 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 9066 }
9067
9068 bp->rx_mode = rx_mode;
619c5cb6
VZ		 9069
9070 /* Schedule the rx_mode command */
9071 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
9072 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9073 return;
9074 }
9075
34f80b04
EG		 9076 bnx2x_set_storm_rx_mode(bp);
9077}
9078
c18487ee 9079/* called with rtnl_lock */
01cd4528
EG		 9080static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9081 int devad, u16 addr)
a2fbb9ea 9082{
01cd4528
EG		 9083 struct bnx2x *bp = netdev_priv(netdev);
9084 u16 value;
9085 int rc;
a2fbb9ea 9086
01cd4528
EG		 9087 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9088 prtad, devad, addr);
a2fbb9ea 9089
01cd4528
EG		 9090 /* The HW expects different devad if CL22 is used */
9091 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 9092
01cd4528 9093 bnx2x_acquire_phy_lock(bp);
e10bc84d 9094 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 9095 bnx2x_release_phy_lock(bp);
9096 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 9097
01cd4528
EG		 9098 if (!rc)
9099 rc = value;
9100 return rc;
9101}
a2fbb9ea 9102
01cd4528
EG		 9103/* called with rtnl_lock */
9104static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9105 u16 addr, u16 value)
9106{
9107 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 9108 int rc;
9109
9110 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9111 " value 0x%x\n", prtad, devad, addr, value);
9112
01cd4528
EG		 9113 /* The HW expects different devad if CL22 is used */
9114 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 9115
01cd4528 9116 bnx2x_acquire_phy_lock(bp);
e10bc84d 9117 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 9118 bnx2x_release_phy_lock(bp);
9119 return rc;
9120}
c18487ee 9121
01cd4528
EG		 9122/* called with rtnl_lock */
9123static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9124{
9125 struct bnx2x *bp = netdev_priv(dev);
9126 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 9127
01cd4528
EG		 9128 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9129 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 9130
01cd4528
EG		 9131 if (!netif_running(dev))
9132 return -EAGAIN;
9133
9134 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 9135}
9136
257ddbda 9137#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 9138static void poll_bnx2x(struct net_device *dev)
9139{
9140 struct bnx2x *bp = netdev_priv(dev);
9141
9142 disable_irq(bp->pdev->irq);
9143 bnx2x_interrupt(bp->pdev->irq, dev);
9144 enable_irq(bp->pdev->irq);
9145}
9146#endif
9147
c64213cd
SH		 9148static const struct net_device_ops bnx2x_netdev_ops = {
9149 .ndo_open = bnx2x_open,
9150 .ndo_stop = bnx2x_close,
9151 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 9152 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 9153 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 9154 .ndo_set_mac_address = bnx2x_change_mac_addr,
9155 .ndo_validate_addr = eth_validate_addr,
9156 .ndo_do_ioctl = bnx2x_ioctl,
9157 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 9158 .ndo_fix_features = bnx2x_fix_features,
9159 .ndo_set_features = bnx2x_set_features,
c64213cd 9160 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 9161#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 9162 .ndo_poll_controller = poll_bnx2x,
9163#endif
9164};
9165
619c5cb6
VZ		 9166static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
9167{
9168 struct device *dev = &bp->pdev->dev;
9169
9170 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
9171 bp->flags |= USING_DAC_FLAG;
9172 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
9173 dev_err(dev, "dma_set_coherent_mask failed, "
9174 "aborting\n");
9175 return -EIO;
9176 }
9177 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
9178 dev_err(dev, "System does not support DMA, aborting\n");
9179 return -EIO;
9180 }
9181
9182 return 0;
9183}
9184
34f80b04 9185static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 9186 struct net_device *dev,
9187 unsigned long board_type)
a2fbb9ea
ET		 9188{
9189 struct bnx2x *bp;
9190 int rc;
9191
9192 SET_NETDEV_DEV(dev, &pdev->dev);
9193 bp = netdev_priv(dev);
9194
34f80b04
EG		 9195 bp->dev = dev;
9196 bp->pdev = pdev;
a2fbb9ea 9197 bp->flags = 0;
f2e0899f 9198 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 9199
9200 rc = pci_enable_device(pdev);
9201 if (rc) {
cdaa7cb8
VZ		 9202 dev_err(&bp->pdev->dev,
9203 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 9204 goto err_out;
9205 }
9206
9207 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9208 dev_err(&bp->pdev->dev,
9209 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 9210 rc = -ENODEV;
9211 goto err_out_disable;
9212 }
9213
9214 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9215 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9216 " base address, aborting\n");
a2fbb9ea
ET		 9217 rc = -ENODEV;
9218 goto err_out_disable;
9219 }
9220
34f80b04
EG		 9221 if (atomic_read(&pdev->enable_cnt) == 1) {
9222 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9223 if (rc) {
cdaa7cb8
VZ		 9224 dev_err(&bp->pdev->dev,
9225 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 9226 goto err_out_disable;
9227 }
a2fbb9ea 9228
34f80b04
EG		 9229 pci_set_master(pdev);
9230 pci_save_state(pdev);
9231 }
a2fbb9ea
ET		 9232
9233 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9234 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 9235 dev_err(&bp->pdev->dev,
9236 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 9237 rc = -EIO;
9238 goto err_out_release;
9239 }
9240
9241 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9242 if (bp->pcie_cap == 0) {
cdaa7cb8
VZ		 9243 dev_err(&bp->pdev->dev,
9244 "Cannot find PCI Express capability, aborting\n");
a2fbb9ea
ET		 9245 rc = -EIO;
9246 goto err_out_release;
9247 }
9248
619c5cb6
VZ		 9249 rc = bnx2x_set_coherency_mask(bp);
9250 if (rc)
a2fbb9ea 9251 goto err_out_release;
a2fbb9ea 9252
34f80b04
EG		 9253 dev->mem_start = pci_resource_start(pdev, 0);
9254 dev->base_addr = dev->mem_start;
9255 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 9256
9257 dev->irq = pdev->irq;
9258
275f165f 9259 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 9260 if (!bp->regview) {
cdaa7cb8
VZ		 9261 dev_err(&bp->pdev->dev,
9262 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 9263 rc = -ENOMEM;
9264 goto err_out_release;
9265 }
9266
34f80b04 9267 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
523224a3 9268 min_t(u64, BNX2X_DB_SIZE(bp),
34f80b04 9269 pci_resource_len(pdev, 2)));
a2fbb9ea 9270 if (!bp->doorbells) {
cdaa7cb8
VZ		 9271 dev_err(&bp->pdev->dev,
9272 "Cannot map doorbell space, aborting\n");
a2fbb9ea
ET		 9273 rc = -ENOMEM;
9274 goto err_out_unmap;
9275 }
9276
9277 bnx2x_set_power_state(bp, PCI_D0);
9278
34f80b04
EG		 9279 /* clean indirect addresses */
9280 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9281 PCICFG_VENDOR_ID_OFFSET);
9282 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9283 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9284 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9285 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 9286
619c5cb6
VZ		 9287 /**
9288 * Enable internal target-read (in case we are probed after PF FLR).
9289 * Must be done prior to any BAR read access
9290 */
9291 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
9292
72fd0718
VZ		 9293 /* Reset the load counter */
9294 bnx2x_clear_load_cnt(bp);
9295
34f80b04 9296 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 9297
c64213cd 9298 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 9299 bnx2x_set_ethtool_ops(dev);
5316bc0b 9300
66371c44
MM		 9301 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9302 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9303 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9304
9305 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9306 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9307
9308 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 9309 if (bp->flags & USING_DAC_FLAG)
66371c44 9310 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 9311
538dd2e3
MB		 9312 /* Add Loopback capability to the device */
9313 dev->hw_features |= NETIF_F_LOOPBACK;
9314
98507672 9315#ifdef BCM_DCBNL
785b9b1a
SR		 9316 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9317#endif
9318
01cd4528
EG		 9319 /* get_port_hwinfo() will set prtad and mmds properly */
9320 bp->mdio.prtad = MDIO_PRTAD_NONE;
9321 bp->mdio.mmds = 0;
9322 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9323 bp->mdio.dev = dev;
9324 bp->mdio.mdio_read = bnx2x_mdio_read;
9325 bp->mdio.mdio_write = bnx2x_mdio_write;
9326
a2fbb9ea
ET		 9327 return 0;
9328
9329err_out_unmap:
9330 if (bp->regview) {
9331 iounmap(bp->regview);
9332 bp->regview = NULL;
9333 }
a2fbb9ea
ET		 9334 if (bp->doorbells) {
9335 iounmap(bp->doorbells);
9336 bp->doorbells = NULL;
9337 }
9338
9339err_out_release:
34f80b04
EG		 9340 if (atomic_read(&pdev->enable_cnt) == 1)
9341 pci_release_regions(pdev);
a2fbb9ea
ET		 9342
9343err_out_disable:
9344 pci_disable_device(pdev);
9345 pci_set_drvdata(pdev, NULL);
9346
9347err_out:
9348 return rc;
9349}
9350
37f9ce62
EG		 9351static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9352 int *width, int *speed)
25047950
ET		 9353{
9354 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9355
37f9ce62 9356 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 9357
37f9ce62
EG		 9358 /* return value of 1=2.5GHz 2=5GHz */
9359 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 9360}
37f9ce62 9361
6891dd25 9362static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 9363{
37f9ce62 9364 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 9365 struct bnx2x_fw_file_hdr *fw_hdr;
9366 struct bnx2x_fw_file_section *sections;
94a78b79 9367 u32 offset, len, num_ops;
37f9ce62 9368 u16 *ops_offsets;
94a78b79 9369 int i;
37f9ce62 9370 const u8 *fw_ver;
94a78b79
VZ		 9371
9372 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9373 return -EINVAL;
9374
9375 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9376 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9377
9378 /* Make sure none of the offsets and sizes make us read beyond
9379 * the end of the firmware data */
9380 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9381 offset = be32_to_cpu(sections[i].offset);
9382 len = be32_to_cpu(sections[i].len);
9383 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 9384 dev_err(&bp->pdev->dev,
9385 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 9386 return -EINVAL;
9387 }
9388 }
9389
9390 /* Likewise for the init_ops offsets */
9391 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9392 ops_offsets = (u16 *)(firmware->data + offset);
9393 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9394
9395 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9396 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 9397 dev_err(&bp->pdev->dev,
9398 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 9399 return -EINVAL;
9400 }
9401 }
9402
9403 /* Check FW version */
9404 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9405 fw_ver = firmware->data + offset;
9406 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9407 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9408 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9409 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 9410 dev_err(&bp->pdev->dev,
9411 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 9412 fw_ver[0], fw_ver[1], fw_ver[2],
9413 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9414 BCM_5710_FW_MINOR_VERSION,
9415 BCM_5710_FW_REVISION_VERSION,
9416 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 9417 return -EINVAL;
94a78b79
VZ		 9418 }
9419
9420 return 0;
9421}
9422
ab6ad5a4 9423static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9424{
ab6ad5a4
EG		 9425 const __be32 *source = (const __be32 *)_source;
9426 u32 *target = (u32 *)_target;
94a78b79 9427 u32 i;
94a78b79
VZ		 9428
9429 for (i = 0; i < n/4; i++)
9430 target[i] = be32_to_cpu(source[i]);
9431}
9432
9433/*
9434 Ops array is stored in the following format:
9435 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9436 */
ab6ad5a4 9437static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 9438{
ab6ad5a4
EG		 9439 const __be32 *source = (const __be32 *)_source;
9440 struct raw_op *target = (struct raw_op *)_target;
94a78b79 9441 u32 i, j, tmp;
94a78b79 9442
ab6ad5a4 9443 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 9444 tmp = be32_to_cpu(source[j]);
9445 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 9446 target[i].offset = tmp & 0xffffff;
9447 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 9448 }
9449}
ab6ad5a4 9450
523224a3
DK		 9451/**
9452 * IRO array is stored in the following format:
9453 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9454 */
9455static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9456{
9457 const __be32 *source = (const __be32 *)_source;
9458 struct iro *target = (struct iro *)_target;
9459 u32 i, j, tmp;
9460
9461 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9462 target[i].base = be32_to_cpu(source[j]);
9463 j++;
9464 tmp = be32_to_cpu(source[j]);
9465 target[i].m1 = (tmp >> 16) & 0xffff;
9466 target[i].m2 = tmp & 0xffff;
9467 j++;
9468 tmp = be32_to_cpu(source[j]);
9469 target[i].m3 = (tmp >> 16) & 0xffff;
9470 target[i].size = tmp & 0xffff;
9471 j++;
9472 }
9473}
9474
ab6ad5a4 9475static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9476{
ab6ad5a4
EG		 9477 const __be16 *source = (const __be16 *)_source;
9478 u16 *target = (u16 *)_target;
94a78b79 9479 u32 i;
94a78b79
VZ		 9480
9481 for (i = 0; i < n/2; i++)
9482 target[i] = be16_to_cpu(source[i]);
9483}
9484
7995c64e
JP		 9485#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9486do { \
9487 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9488 bp->arr = kmalloc(len, GFP_KERNEL); \
9489 if (!bp->arr) { \
9490 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9491 goto lbl; \
9492 } \
9493 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9494 (u8 *)bp->arr, len); \
9495} while (0)
94a78b79 9496
6891dd25 9497int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 9498{
45229b42 9499 const char *fw_file_name;
94a78b79 9500 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 9501 int rc;
94a78b79 9502
94a78b79 9503 if (CHIP_IS_E1(bp))
45229b42 9504 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 9505 else if (CHIP_IS_E1H(bp))
45229b42 9506 fw_file_name = FW_FILE_NAME_E1H;
619c5cb6 9507 else if (!CHIP_IS_E1x(bp))
f2e0899f 9508 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 9509 else {
6891dd25 9510 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 9511 return -EINVAL;
9512 }
94a78b79 9513
6891dd25 9514 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 9515
6891dd25 9516 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 9517 if (rc) {
6891dd25 9518 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 9519 goto request_firmware_exit;
9520 }
9521
9522 rc = bnx2x_check_firmware(bp);
9523 if (rc) {
6891dd25 9524 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 9525 goto request_firmware_exit;
9526 }
9527
9528 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9529
9530 /* Initialize the pointers to the init arrays */
9531 /* Blob */
9532 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9533
9534 /* Opcodes */
9535 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9536
9537 /* Offsets */
ab6ad5a4
EG		 9538 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9539 be16_to_cpu_n);
94a78b79
VZ		 9540
9541 /* STORMs firmware */
573f2035
EG		 9542 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9543 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9544 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9545 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9546 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9547 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9548 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9549 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9550 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9551 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9552 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9553 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9554 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9555 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9556 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9557 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 9558 /* IRO */
9559 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 9560
9561 return 0;
ab6ad5a4 9562
523224a3
DK		 9563iro_alloc_err:
9564 kfree(bp->init_ops_offsets);
94a78b79
VZ		 9565init_offsets_alloc_err:
9566 kfree(bp->init_ops);
9567init_ops_alloc_err:
9568 kfree(bp->init_data);
9569request_firmware_exit:
9570 release_firmware(bp->firmware);
9571
9572 return rc;
9573}
9574
619c5cb6
VZ		 9575static void bnx2x_release_firmware(struct bnx2x *bp)
9576{
9577 kfree(bp->init_ops_offsets);
9578 kfree(bp->init_ops);
9579 kfree(bp->init_data);
9580 release_firmware(bp->firmware);
9581}
9582
9583
9584static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
9585 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
9586 .init_hw_cmn = bnx2x_init_hw_common,
9587 .init_hw_port = bnx2x_init_hw_port,
9588 .init_hw_func = bnx2x_init_hw_func,
9589
9590 .reset_hw_cmn = bnx2x_reset_common,
9591 .reset_hw_port = bnx2x_reset_port,
9592 .reset_hw_func = bnx2x_reset_func,
9593
9594 .gunzip_init = bnx2x_gunzip_init,
9595 .gunzip_end = bnx2x_gunzip_end,
9596
9597 .init_fw = bnx2x_init_firmware,
9598 .release_fw = bnx2x_release_firmware,
9599};
9600
9601void bnx2x__init_func_obj(struct bnx2x *bp)
9602{
9603 /* Prepare DMAE related driver resources */
9604 bnx2x_setup_dmae(bp);
9605
9606 bnx2x_init_func_obj(bp, &bp->func_obj,
9607 bnx2x_sp(bp, func_rdata),
9608 bnx2x_sp_mapping(bp, func_rdata),
9609 &bnx2x_func_sp_drv);
9610}
9611
9612/* must be called after sriov-enable */
523224a3
DK		 9613static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9614{
9615 int cid_count = L2_FP_COUNT(l2_cid_count);
94a78b79 9616
523224a3
DK		 9617#ifdef BCM_CNIC
9618 cid_count += CNIC_CID_MAX;
9619#endif
9620 return roundup(cid_count, QM_CID_ROUND);
9621}
f85582f8 9622
619c5cb6
VZ		 9623/**
9624 * bnx2x_pci_msix_table_size - get the size of the MSI-X table.
9625 *
9626 * @dev: pci device
9627 *
9628 */
9629static inline int bnx2x_pci_msix_table_size(struct pci_dev *pdev)
9630{
9631 int pos;
9632 u16 control;
9633
9634 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
9635 if (!pos)
9636 return 0;
9637
9638 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
9639 return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
9640}
9641
a2fbb9ea
ET		 9642static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9643 const struct pci_device_id *ent)
9644{
a2fbb9ea
ET		 9645 struct net_device *dev = NULL;
9646 struct bnx2x *bp;
37f9ce62 9647 int pcie_width, pcie_speed;
523224a3
DK		 9648 int rc, cid_count;
9649
f2e0899f
DK		 9650 switch (ent->driver_data) {
9651 case BCM57710:
9652 case BCM57711:
9653 case BCM57711E:
f2e0899f 9654 case BCM57712:
619c5cb6
VZ		 9655 case BCM57712_MF:
9656 case BCM57800:
9657 case BCM57800_MF:
9658 case BCM57810:
9659 case BCM57810_MF:
9660 case BCM57840:
9661 case BCM57840_MF:
9662 /* The size requested for the MSI-X table corresponds to the
9663 * actual amount of avaliable IGU/HC status blocks. It includes
9664 * the default SB vector but we want cid_count to contain the
9665 * amount of only non-default SBs, that's what '-1' stands for.
9666 */
9667 cid_count = bnx2x_pci_msix_table_size(pdev) - 1;
9668
9669 /* do not allow initial cid_count grow above 16
9670 * since Special CIDs starts from this number
9671 * use old FP_SB_MAX_E1x define for this matter
9672 */
9673 cid_count = min_t(int, FP_SB_MAX_E1x, cid_count);
9674
9675 WARN_ON(!cid_count);
f2e0899f 9676 break;
a2fbb9ea 9677
f2e0899f
DK		 9678 default:
9679 pr_err("Unknown board_type (%ld), aborting\n",
9680 ent->driver_data);
870634b0 9681 return -ENODEV;
f2e0899f
DK		 9682 }
9683
619c5cb6 9684 cid_count += FCOE_CONTEXT_USE;
f85582f8 9685
a2fbb9ea 9686 /* dev zeroed in init_etherdev */
523224a3 9687 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
34f80b04 9688 if (!dev) {
cdaa7cb8 9689 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 9690 return -ENOMEM;
34f80b04 9691 }
a2fbb9ea 9692
619c5cb6
VZ		 9693 /* We don't need a Tx queue for a CNIC and an OOO Rx-only ring,
9694 * so update a cid_count after a netdev allocation.
9695 */
9696 cid_count += CNIC_CONTEXT_USE;
9697
a2fbb9ea 9698 bp = netdev_priv(dev);
7995c64e 9699 bp->msg_enable = debug;
a2fbb9ea 9700
df4770de
EG		 9701 pci_set_drvdata(pdev, dev);
9702
523224a3
DK		 9703 bp->l2_cid_count = cid_count;
9704
619c5cb6 9705 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 9706 if (rc < 0) {
9707 free_netdev(dev);
9708 return rc;
9709 }
9710
619c5cb6
VZ		 9711 BNX2X_DEV_INFO("cid_count=%d\n", cid_count);
9712
34f80b04 9713 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 9714 if (rc)
9715 goto init_one_exit;
9716
523224a3
DK		 9717 /* calc qm_cid_count */
9718 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9719
ec6ba945
VZ		 9720#ifdef BCM_CNIC
9721 /* disable FCOE L2 queue for E1x*/
9722 if (CHIP_IS_E1x(bp))
9723 bp->flags |= NO_FCOE_FLAG;
9724
9725#endif
9726
25985edc 9727 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 9728 * needed, set bp->num_queues appropriately.
9729 */
9730 bnx2x_set_int_mode(bp);
9731
9732 /* Add all NAPI objects */
9733 bnx2x_add_all_napi(bp);
9734
b340007f
VZ		 9735 rc = register_netdev(dev);
9736 if (rc) {
9737 dev_err(&pdev->dev, "Cannot register net device\n");
9738 goto init_one_exit;
9739 }
9740
ec6ba945
VZ		 9741#ifdef BCM_CNIC
9742 if (!NO_FCOE(bp)) {
9743 /* Add storage MAC address */
9744 rtnl_lock();
9745 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9746 rtnl_unlock();
9747 }
9748#endif
9749
37f9ce62 9750 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 9751
cdaa7cb8
VZ		 9752 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9753 " IRQ %d, ", board_info[ent->driver_data].name,
9754 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 9755 pcie_width,
9756 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9757 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9758 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 9759 dev->base_addr, bp->pdev->irq);
9760 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 9761
a2fbb9ea 9762 return 0;
34f80b04
EG		 9763
9764init_one_exit:
9765 if (bp->regview)
9766 iounmap(bp->regview);
9767
9768 if (bp->doorbells)
9769 iounmap(bp->doorbells);
9770
9771 free_netdev(dev);
9772
9773 if (atomic_read(&pdev->enable_cnt) == 1)
9774 pci_release_regions(pdev);
9775
9776 pci_disable_device(pdev);
9777 pci_set_drvdata(pdev, NULL);
9778
9779 return rc;
a2fbb9ea
ET		 9780}
9781
9782static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9783{
9784 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 9785 struct bnx2x *bp;
9786
9787 if (!dev) {
cdaa7cb8 9788 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 9789 return;
9790 }
228241eb 9791 bp = netdev_priv(dev);
a2fbb9ea 9792
ec6ba945
VZ		 9793#ifdef BCM_CNIC
9794 /* Delete storage MAC address */
9795 if (!NO_FCOE(bp)) {
9796 rtnl_lock();
9797 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9798 rtnl_unlock();
9799 }
9800#endif
9801
98507672
SR		 9802#ifdef BCM_DCBNL
9803 /* Delete app tlvs from dcbnl */
9804 bnx2x_dcbnl_update_applist(bp, true);
9805#endif
9806
a2fbb9ea
ET		 9807 unregister_netdev(dev);
9808
d6214d7a
DK		 9809 /* Delete all NAPI objects */
9810 bnx2x_del_all_napi(bp);
9811
084d6cbb
VZ		 9812 /* Power on: we can't let PCI layer write to us while we are in D3 */
9813 bnx2x_set_power_state(bp, PCI_D0);
9814
d6214d7a
DK		 9815 /* Disable MSI/MSI-X */
9816 bnx2x_disable_msi(bp);
f85582f8 9817
084d6cbb
VZ		 9818 /* Power off */
9819 bnx2x_set_power_state(bp, PCI_D3hot);
9820
72fd0718
VZ		 9821 /* Make sure RESET task is not scheduled before continuing */
9822 cancel_delayed_work_sync(&bp->reset_task);
9823
a2fbb9ea
ET		 9824 if (bp->regview)
9825 iounmap(bp->regview);
9826
9827 if (bp->doorbells)
9828 iounmap(bp->doorbells);
9829
523224a3
DK		 9830 bnx2x_free_mem_bp(bp);
9831
a2fbb9ea 9832 free_netdev(dev);
34f80b04
EG		 9833
9834 if (atomic_read(&pdev->enable_cnt) == 1)
9835 pci_release_regions(pdev);
9836
a2fbb9ea
ET		 9837 pci_disable_device(pdev);
9838 pci_set_drvdata(pdev, NULL);
9839}
9840
f8ef6e44
YG		 9841static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9842{
9843 int i;
9844
9845 bp->state = BNX2X_STATE_ERROR;
9846
9847 bp->rx_mode = BNX2X_RX_MODE_NONE;
9848
619c5cb6
VZ		 9849#ifdef BCM_CNIC
9850 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
9851#endif
9852 /* Stop Tx */
9853 bnx2x_tx_disable(bp);
9854
f8ef6e44
YG		 9855 bnx2x_netif_stop(bp, 0);
9856
9857 del_timer_sync(&bp->timer);
619c5cb6
VZ		 9858
9859 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 9860
9861 /* Release IRQs */
d6214d7a 9862 bnx2x_free_irq(bp);
f8ef6e44 9863
f8ef6e44
YG		 9864 /* Free SKBs, SGEs, TPA pool and driver internals */
9865 bnx2x_free_skbs(bp);
523224a3 9866
ec6ba945 9867 for_each_rx_queue(bp, i)
f8ef6e44 9868 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 9869
f8ef6e44
YG		 9870 bnx2x_free_mem(bp);
9871
9872 bp->state = BNX2X_STATE_CLOSED;
9873
619c5cb6
VZ		 9874 netif_carrier_off(bp->dev);
9875
f8ef6e44
YG		 9876 return 0;
9877}
9878
9879static void bnx2x_eeh_recover(struct bnx2x *bp)
9880{
9881 u32 val;
9882
9883 mutex_init(&bp->port.phy_mutex);
9884
9885 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9886 bp->link_params.shmem_base = bp->common.shmem_base;
9887 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9888
9889 if (!bp->common.shmem_base ||
9890 (bp->common.shmem_base < 0xA0000) ||
9891 (bp->common.shmem_base >= 0xC0000)) {
9892 BNX2X_DEV_INFO("MCP not active\n");
9893 bp->flags |= NO_MCP_FLAG;
9894 return;
9895 }
9896
9897 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9898 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9899 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9900 BNX2X_ERR("BAD MCP validity signature\n");
9901
9902 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9903 bp->fw_seq =
9904 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9905 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 9906 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9907 }
9908}
9909
493adb1f
WX		 9910/**
9911 * bnx2x_io_error_detected - called when PCI error is detected
9912 * @pdev: Pointer to PCI device
9913 * @state: The current pci connection state
9914 *
9915 * This function is called after a PCI bus error affecting
9916 * this device has been detected.
9917 */
9918static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9919 pci_channel_state_t state)
9920{
9921 struct net_device *dev = pci_get_drvdata(pdev);
9922 struct bnx2x *bp = netdev_priv(dev);
9923
9924 rtnl_lock();
9925
9926 netif_device_detach(dev);
9927
07ce50e4
DN		 9928 if (state == pci_channel_io_perm_failure) {
9929 rtnl_unlock();
9930 return PCI_ERS_RESULT_DISCONNECT;
9931 }
9932
493adb1f 9933 if (netif_running(dev))
f8ef6e44 9934 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 9935
9936 pci_disable_device(pdev);
9937
9938 rtnl_unlock();
9939
9940 /* Request a slot reset */
9941 return PCI_ERS_RESULT_NEED_RESET;
9942}
9943
9944/**
9945 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9946 * @pdev: Pointer to PCI device
9947 *
9948 * Restart the card from scratch, as if from a cold-boot.
9949 */
9950static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9951{
9952 struct net_device *dev = pci_get_drvdata(pdev);
9953 struct bnx2x *bp = netdev_priv(dev);
9954
9955 rtnl_lock();
9956
9957 if (pci_enable_device(pdev)) {
9958 dev_err(&pdev->dev,
9959 "Cannot re-enable PCI device after reset\n");
9960 rtnl_unlock();
9961 return PCI_ERS_RESULT_DISCONNECT;
9962 }
9963
9964 pci_set_master(pdev);
9965 pci_restore_state(pdev);
9966
9967 if (netif_running(dev))
9968 bnx2x_set_power_state(bp, PCI_D0);
9969
9970 rtnl_unlock();
9971
9972 return PCI_ERS_RESULT_RECOVERED;
9973}
9974
9975/**
9976 * bnx2x_io_resume - called when traffic can start flowing again
9977 * @pdev: Pointer to PCI device
9978 *
9979 * This callback is called when the error recovery driver tells us that
9980 * its OK to resume normal operation.
9981 */
9982static void bnx2x_io_resume(struct pci_dev *pdev)
9983{
9984 struct net_device *dev = pci_get_drvdata(pdev);
9985 struct bnx2x *bp = netdev_priv(dev);
9986
72fd0718 9987 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f2e0899f
DK		 9988 printk(KERN_ERR "Handling parity error recovery. "
9989 "Try again later\n");
72fd0718
VZ		 9990 return;
9991 }
9992
493adb1f
WX		 9993 rtnl_lock();
9994
f8ef6e44
YG		 9995 bnx2x_eeh_recover(bp);
9996
493adb1f 9997 if (netif_running(dev))
f8ef6e44 9998 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 9999
10000 netif_device_attach(dev);
10001
10002 rtnl_unlock();
10003}
10004
10005static struct pci_error_handlers bnx2x_err_handler = {
10006 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 10007 .slot_reset = bnx2x_io_slot_reset,
10008 .resume = bnx2x_io_resume,
493adb1f
WX		 10009};
10010
a2fbb9ea 10011static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 10012 .name = DRV_MODULE_NAME,
10013 .id_table = bnx2x_pci_tbl,
10014 .probe = bnx2x_init_one,
10015 .remove = __devexit_p(bnx2x_remove_one),
10016 .suspend = bnx2x_suspend,
10017 .resume = bnx2x_resume,
10018 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 10019};
10020
10021static int __init bnx2x_init(void)
10022{
dd21ca6d
SG		 10023 int ret;
10024
7995c64e 10025 pr_info("%s", version);
938cf541 10026
1cf167f2
EG		 10027 bnx2x_wq = create_singlethread_workqueue("bnx2x");
10028 if (bnx2x_wq == NULL) {
7995c64e 10029 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 10030 return -ENOMEM;
10031 }
10032
dd21ca6d
SG		 10033 ret = pci_register_driver(&bnx2x_pci_driver);
10034 if (ret) {
7995c64e 10035 pr_err("Cannot register driver\n");
dd21ca6d
SG		 10036 destroy_workqueue(bnx2x_wq);
10037 }
10038 return ret;
a2fbb9ea
ET		 10039}
10040
10041static void __exit bnx2x_cleanup(void)
10042{
10043 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 10044
10045 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 10046}
10047
10048module_init(bnx2x_init);
10049module_exit(bnx2x_cleanup);
10050
993ac7b5 10051#ifdef BCM_CNIC
619c5cb6
VZ		 10052/**
10053 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
10054 *
10055 * @bp: driver handle
10056 * @set: set or clear the CAM entry
10057 *
10058 * This function will wait until the ramdord completion returns.
10059 * Return 0 if success, -ENODEV if ramrod doesn't return.
10060 */
10061static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
10062{
10063 unsigned long ramrod_flags = 0;
10064
10065 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
10066 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
10067 &bp->iscsi_l2_mac_obj, true,
10068 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
10069}
993ac7b5
MC		 10070
10071/* count denotes the number of new completions we have seen */
10072static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
10073{
10074 struct eth_spe *spe;
10075
10076#ifdef BNX2X_STOP_ON_ERROR
10077 if (unlikely(bp->panic))
10078 return;
10079#endif
10080
10081 spin_lock_bh(&bp->spq_lock);
c2bff63f 10082 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 10083 bp->cnic_spq_pending -= count;
10084
993ac7b5 10085
c2bff63f
DK		 10086 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
10087 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
10088 & SPE_HDR_CONN_TYPE) >>
10089 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 10090 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
10091 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 10092
10093 /* Set validation for iSCSI L2 client before sending SETUP
10094 * ramrod
10095 */
10096 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 10097 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 10098 bnx2x_set_ctx_validation(bp, &bp->context.
10099 vcxt[BNX2X_ISCSI_ETH_CID].eth,
10100 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 10101 }
10102
619c5cb6
VZ		 10103 /*
10104 * There may be not more than 8 L2, not more than 8 L5 SPEs
10105 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 10106 * COMMON ramrods is not more than the EQ and SPQ can
10107 * accommodate.
c2bff63f 10108 */
6e30dd4e
VZ		 10109 if (type == ETH_CONNECTION_TYPE) {
10110 if (!atomic_read(&bp->cq_spq_left))
10111 break;
10112 else
10113 atomic_dec(&bp->cq_spq_left);
10114 } else if (type == NONE_CONNECTION_TYPE) {
10115 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 10116 break;
10117 else
6e30dd4e 10118 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 10119 } else if ((type == ISCSI_CONNECTION_TYPE) ||
10120 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 10121 if (bp->cnic_spq_pending >=
10122 bp->cnic_eth_dev.max_kwqe_pending)
10123 break;
10124 else
10125 bp->cnic_spq_pending++;
10126 } else {
10127 BNX2X_ERR("Unknown SPE type: %d\n", type);
10128 bnx2x_panic();
993ac7b5 10129 break;
c2bff63f 10130 }
993ac7b5
MC		 10131
10132 spe = bnx2x_sp_get_next(bp);
10133 *spe = *bp->cnic_kwq_cons;
10134
993ac7b5
MC		 10135 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
10136 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
10137
10138 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
10139 bp->cnic_kwq_cons = bp->cnic_kwq;
10140 else
10141 bp->cnic_kwq_cons++;
10142 }
10143 bnx2x_sp_prod_update(bp);
10144 spin_unlock_bh(&bp->spq_lock);
10145}
10146
10147static int bnx2x_cnic_sp_queue(struct net_device *dev,
10148 struct kwqe_16 *kwqes[], u32 count)
10149{
10150 struct bnx2x *bp = netdev_priv(dev);
10151 int i;
10152
10153#ifdef BNX2X_STOP_ON_ERROR
10154 if (unlikely(bp->panic))
10155 return -EIO;
10156#endif
10157
10158 spin_lock_bh(&bp->spq_lock);
10159
10160 for (i = 0; i < count; i++) {
10161 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10162
10163 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10164 break;
10165
10166 *bp->cnic_kwq_prod = *spe;
10167
10168 bp->cnic_kwq_pending++;
10169
10170 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10171 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 10172 spe->data.update_data_addr.hi,
10173 spe->data.update_data_addr.lo,
993ac7b5
MC		 10174 bp->cnic_kwq_pending);
10175
10176 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10177 bp->cnic_kwq_prod = bp->cnic_kwq;
10178 else
10179 bp->cnic_kwq_prod++;
10180 }
10181
10182 spin_unlock_bh(&bp->spq_lock);
10183
10184 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10185 bnx2x_cnic_sp_post(bp, 0);
10186
10187 return i;
10188}
10189
10190static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10191{
10192 struct cnic_ops *c_ops;
10193 int rc = 0;
10194
10195 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 10196 c_ops = rcu_dereference_protected(bp->cnic_ops,
10197 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 10198 if (c_ops)
10199 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10200 mutex_unlock(&bp->cnic_mutex);
10201
10202 return rc;
10203}
10204
10205static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10206{
10207 struct cnic_ops *c_ops;
10208 int rc = 0;
10209
10210 rcu_read_lock();
10211 c_ops = rcu_dereference(bp->cnic_ops);
10212 if (c_ops)
10213 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10214 rcu_read_unlock();
10215
10216 return rc;
10217}
10218
10219/*
10220 * for commands that have no data
10221 */
9f6c9258 10222int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 10223{
10224 struct cnic_ctl_info ctl = {0};
10225
10226 ctl.cmd = cmd;
10227
10228 return bnx2x_cnic_ctl_send(bp, &ctl);
10229}
10230
619c5cb6 10231static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 10232{
619c5cb6 10233 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 10234
10235 /* first we tell CNIC and only then we count this as a completion */
10236 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10237 ctl.data.comp.cid = cid;
619c5cb6 10238 ctl.data.comp.error = err;
993ac7b5
MC		 10239
10240 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 10241 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 10242}
10243
619c5cb6
VZ		 10244
10245/* Called with netif_addr_lock_bh() taken.
10246 * Sets an rx_mode config for an iSCSI ETH client.
10247 * Doesn't block.
10248 * Completion should be checked outside.
10249 */
10250static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
10251{
10252 unsigned long accept_flags = 0, ramrod_flags = 0;
10253 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
10254 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
10255
10256 if (start) {
10257 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10258 * because it's the only way for UIO Queue to accept
10259 * multicasts (in non-promiscuous mode only one Queue per
10260 * function will receive multicast packets (leading in our
10261 * case).
10262 */
10263 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
10264 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
10265 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
10266 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
10267
10268 /* Clear STOP_PENDING bit if START is requested */
10269 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
10270
10271 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
10272 } else
10273 /* Clear START_PENDING bit if STOP is requested */
10274 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
10275
10276 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
10277 set_bit(sched_state, &bp->sp_state);
10278 else {
10279 __set_bit(RAMROD_RX, &ramrod_flags);
10280 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
10281 ramrod_flags);
10282 }
10283}
10284
10285
993ac7b5
MC		 10286static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10287{
10288 struct bnx2x *bp = netdev_priv(dev);
10289 int rc = 0;
10290
10291 switch (ctl->cmd) {
10292 case DRV_CTL_CTXTBL_WR_CMD: {
10293 u32 index = ctl->data.io.offset;
10294 dma_addr_t addr = ctl->data.io.dma_addr;
10295
10296 bnx2x_ilt_wr(bp, index, addr);
10297 break;
10298 }
10299
c2bff63f
DK		 10300 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10301 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 10302
10303 bnx2x_cnic_sp_post(bp, count);
10304 break;
10305 }
10306
10307 /* rtnl_lock is held. */
10308 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 10309 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10310 unsigned long sp_bits = 0;
10311
10312 /* Configure the iSCSI classification object */
10313 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
10314 cp->iscsi_l2_client_id,
10315 cp->iscsi_l2_cid, BP_FUNC(bp),
10316 bnx2x_sp(bp, mac_rdata),
10317 bnx2x_sp_mapping(bp, mac_rdata),
10318 BNX2X_FILTER_MAC_PENDING,
10319 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
10320 &bp->macs_pool);
ec6ba945 10321
523224a3 10322 /* Set iSCSI MAC address */
619c5cb6
VZ		 10323 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
10324 if (rc)
10325 break;
523224a3
DK		 10326
10327 mmiowb();
10328 barrier();
10329
619c5cb6
VZ		 10330 /* Start accepting on iSCSI L2 ring */
10331
10332 netif_addr_lock_bh(dev);
10333 bnx2x_set_iscsi_eth_rx_mode(bp, true);
10334 netif_addr_unlock_bh(dev);
10335
10336 /* bits to wait on */
10337 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
10338 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
10339
10340 if (!bnx2x_wait_sp_comp(bp, sp_bits))
10341 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 10342
993ac7b5
MC		 10343 break;
10344 }
10345
10346 /* rtnl_lock is held. */
10347 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 10348 unsigned long sp_bits = 0;
993ac7b5 10349
523224a3 10350 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 10351 netif_addr_lock_bh(dev);
10352 bnx2x_set_iscsi_eth_rx_mode(bp, false);
10353 netif_addr_unlock_bh(dev);
10354
10355 /* bits to wait on */
10356 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
10357 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
10358
10359 if (!bnx2x_wait_sp_comp(bp, sp_bits))
10360 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 10361
10362 mmiowb();
10363 barrier();
10364
10365 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 10366 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
10367 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 10368 break;
10369 }
c2bff63f
DK		 10370 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10371 int count = ctl->data.credit.credit_count;
10372
10373 smp_mb__before_atomic_inc();
6e30dd4e 10374 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 10375 smp_mb__after_atomic_inc();
10376 break;
10377 }
993ac7b5
MC		 10378
10379 default:
10380 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10381 rc = -EINVAL;
10382 }
10383
10384 return rc;
10385}
10386
9f6c9258 10387void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 10388{
10389 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10390
10391 if (bp->flags & USING_MSIX_FLAG) {
10392 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10393 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10394 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10395 } else {
10396 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10397 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10398 }
619c5cb6 10399 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 10400 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10401 else
10402 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10403
619c5cb6
VZ		 10404 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
10405 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 10406 cp->irq_arr[1].status_blk = bp->def_status_blk;
10407 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 10408 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 10409
10410 cp->num_irq = 2;
10411}
10412
10413static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10414 void *data)
10415{
10416 struct bnx2x *bp = netdev_priv(dev);
10417 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10418
10419 if (ops == NULL)
10420 return -EINVAL;
10421
993ac7b5
MC		 10422 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10423 if (!bp->cnic_kwq)
10424 return -ENOMEM;
10425
10426 bp->cnic_kwq_cons = bp->cnic_kwq;
10427 bp->cnic_kwq_prod = bp->cnic_kwq;
10428 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10429
10430 bp->cnic_spq_pending = 0;
10431 bp->cnic_kwq_pending = 0;
10432
10433 bp->cnic_data = data;
10434
10435 cp->num_irq = 0;
619c5cb6 10436 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 10437 cp->iro_arr = bp->iro_arr;
993ac7b5 10438
993ac7b5 10439 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 10440
993ac7b5
MC		 10441 rcu_assign_pointer(bp->cnic_ops, ops);
10442
10443 return 0;
10444}
10445
10446static int bnx2x_unregister_cnic(struct net_device *dev)
10447{
10448 struct bnx2x *bp = netdev_priv(dev);
10449 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10450
10451 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 10452 cp->drv_state = 0;
10453 rcu_assign_pointer(bp->cnic_ops, NULL);
10454 mutex_unlock(&bp->cnic_mutex);
10455 synchronize_rcu();
10456 kfree(bp->cnic_kwq);
10457 bp->cnic_kwq = NULL;
10458
10459 return 0;
10460}
10461
10462struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10463{
10464 struct bnx2x *bp = netdev_priv(dev);
10465 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10466
2ba45142
VZ		 10467 /* If both iSCSI and FCoE are disabled - return NULL in
10468 * order to indicate CNIC that it should not try to work
10469 * with this device.
10470 */
10471 if (NO_ISCSI(bp) && NO_FCOE(bp))
10472 return NULL;
10473
993ac7b5
MC		 10474 cp->drv_owner = THIS_MODULE;
10475 cp->chip_id = CHIP_ID(bp);
10476 cp->pdev = bp->pdev;
10477 cp->io_base = bp->regview;
10478 cp->io_base2 = bp->doorbells;
10479 cp->max_kwqe_pending = 8;
523224a3 10480 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 10481 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10482 bnx2x_cid_ilt_lines(bp);
993ac7b5 10483 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 10484 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 10485 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10486 cp->drv_ctl = bnx2x_drv_ctl;
10487 cp->drv_register_cnic = bnx2x_register_cnic;
10488 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 10489 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 10490 cp->iscsi_l2_client_id =
10491 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 10492 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10493
2ba45142
VZ		 10494 if (NO_ISCSI_OOO(bp))
10495 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10496
10497 if (NO_ISCSI(bp))
10498 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10499
10500 if (NO_FCOE(bp))
10501 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10502
c2bff63f
DK		 10503 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10504 "starting cid %d\n",
10505 cp->ctx_blk_size,
10506 cp->ctx_tbl_offset,
10507 cp->ctx_tbl_len,
10508 cp->starting_cid);
993ac7b5
MC		 10509 return cp;
10510}
10511EXPORT_SYMBOL(bnx2x_cnic_probe);
10512
10513#endif /* BCM_CNIC */
94a78b79 10514
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