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bnx2x: MTU for FCoE L2 ring
[mirror_ubuntu-eoan-kernel.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
3359fced 3 * Copyright (c) 2007-2010 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea
ET		 41#include <net/ip.h>
42#include <net/tcp.h>
43#include <net/checksum.h>
34f80b04 44#include <net/ip6_checksum.h>
a2fbb9ea
ET		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
34f80b04 47#include <linux/crc32c.h>
a2fbb9ea
ET		 48#include <linux/prefetch.h>
49#include <linux/zlib.h>
a2fbb9ea 50#include <linux/io.h>
45229b42 51#include <linux/stringify.h>
a2fbb9ea 52
b0efbb99 53#define BNX2X_MAIN
a2fbb9ea
ET		 54#include "bnx2x.h"
55#include "bnx2x_init.h"
94a78b79 56#include "bnx2x_init_ops.h"
9f6c9258 57#include "bnx2x_cmn.h"
e4901dde 58#include "bnx2x_dcb.h"
a2fbb9ea 59
94a78b79
VZ		 60#include <linux/firmware.h>
61#include "bnx2x_fw_file_hdr.h"
62/* FW files */
45229b42
BH		 63#define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 68#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 70#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 71
34f80b04
EG		 72/* Time in jiffies before concluding the transmitter is hung */
73#define TX_TIMEOUT (5*HZ)
a2fbb9ea 74
53a10565 75static char version[] __devinitdata =
34f80b04 76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
a2fbb9ea
ET		 77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
24e3fcef 79MODULE_AUTHOR("Eliezer Tamir");
f2e0899f
DK		 80MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
a2fbb9ea
ET		 82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 84MODULE_FIRMWARE(FW_FILE_NAME_E1);
85MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 86MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 87
555f6c78
EG		 88static int multi_mode = 1;
89module_param(multi_mode, int, 0);
ca00392c
EG		 90MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
d6214d7a 93int num_queues;
54b9ddaa
VZ		 94module_param(num_queues, int, 0);
95MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
555f6c78 97
19680c48 98static int disable_tpa;
19680c48 99module_param(disable_tpa, int, 0);
9898f86d 100MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a
EG		 101
102static int int_mode;
103module_param(int_mode, int, 0);
cdaa7cb8
VZ		 104MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
8badd27a 106
a18f5128
EG		 107static int dropless_fc;
108module_param(dropless_fc, int, 0);
109MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
9898f86d 111static int poll;
a2fbb9ea 112module_param(poll, int, 0);
9898f86d 113MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 114
115static int mrrs = -1;
116module_param(mrrs, int, 0);
117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
a2fbb9ea 120module_param(debug, int, 0);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
1cf167f2 123static struct workqueue_struct *bnx2x_wq;
a2fbb9ea 124
ec6ba945
VZ		 125#ifdef BCM_CNIC
126static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127#endif
128
a2fbb9ea
ET		 129enum bnx2x_board_type {
130 BCM57710 = 0,
34f80b04
EG		 131 BCM57711 = 1,
132 BCM57711E = 2,
f2e0899f
DK		 133 BCM57712 = 3,
134 BCM57712E = 4
a2fbb9ea
ET		 135};
136
34f80b04 137/* indexed by board_type, above */
53a10565 138static struct {
a2fbb9ea
ET		 139 char *name;
140} board_info[] __devinitdata = {
34f80b04
EG		 141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
f2e0899f
DK		 143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
a2fbb9ea
ET		 146};
147
f2e0899f
DK		 148#ifndef PCI_DEVICE_ID_NX2_57712
149#define PCI_DEVICE_ID_NX2_57712 0x1662
150#endif
151#ifndef PCI_DEVICE_ID_NX2_57712E
152#define PCI_DEVICE_ID_NX2_57712E 0x1663
153#endif
34f80b04 154
a3aa1884 155static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 156 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
157 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
158 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f
DK		 159 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
160 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
a2fbb9ea
ET		 161 { 0 }
162};
163
164MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
165
166/****************************************************************************
167* General service functions
168****************************************************************************/
169
523224a3
DK		 170static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
171 u32 addr, dma_addr_t mapping)
172{
173 REG_WR(bp, addr, U64_LO(mapping));
174 REG_WR(bp, addr + 4, U64_HI(mapping));
175}
176
177static inline void __storm_memset_fill(struct bnx2x *bp,
178 u32 addr, size_t size, u32 val)
179{
180 int i;
181 for (i = 0; i < size/4; i++)
182 REG_WR(bp, addr + (i * 4), val);
183}
184
185static inline void storm_memset_ustats_zero(struct bnx2x *bp,
186 u8 port, u16 stat_id)
187{
188 size_t size = sizeof(struct ustorm_per_client_stats);
189
190 u32 addr = BAR_USTRORM_INTMEM +
191 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
192
193 __storm_memset_fill(bp, addr, size, 0);
194}
195
196static inline void storm_memset_tstats_zero(struct bnx2x *bp,
197 u8 port, u16 stat_id)
198{
199 size_t size = sizeof(struct tstorm_per_client_stats);
200
201 u32 addr = BAR_TSTRORM_INTMEM +
202 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
203
204 __storm_memset_fill(bp, addr, size, 0);
205}
206
207static inline void storm_memset_xstats_zero(struct bnx2x *bp,
208 u8 port, u16 stat_id)
209{
210 size_t size = sizeof(struct xstorm_per_client_stats);
211
212 u32 addr = BAR_XSTRORM_INTMEM +
213 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
214
215 __storm_memset_fill(bp, addr, size, 0);
216}
217
218
219static inline void storm_memset_spq_addr(struct bnx2x *bp,
220 dma_addr_t mapping, u16 abs_fid)
221{
222 u32 addr = XSEM_REG_FAST_MEMORY +
223 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
224
225 __storm_memset_dma_mapping(bp, addr, mapping);
226}
227
228static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
229{
230 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
231}
232
233static inline void storm_memset_func_cfg(struct bnx2x *bp,
234 struct tstorm_eth_function_common_config *tcfg,
235 u16 abs_fid)
236{
237 size_t size = sizeof(struct tstorm_eth_function_common_config);
238
239 u32 addr = BAR_TSTRORM_INTMEM +
240 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
241
242 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
243}
244
245static inline void storm_memset_xstats_flags(struct bnx2x *bp,
246 struct stats_indication_flags *flags,
247 u16 abs_fid)
248{
249 size_t size = sizeof(struct stats_indication_flags);
250
251 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
252
253 __storm_memset_struct(bp, addr, size, (u32 *)flags);
254}
255
256static inline void storm_memset_tstats_flags(struct bnx2x *bp,
257 struct stats_indication_flags *flags,
258 u16 abs_fid)
259{
260 size_t size = sizeof(struct stats_indication_flags);
261
262 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
263
264 __storm_memset_struct(bp, addr, size, (u32 *)flags);
265}
266
267static inline void storm_memset_ustats_flags(struct bnx2x *bp,
268 struct stats_indication_flags *flags,
269 u16 abs_fid)
270{
271 size_t size = sizeof(struct stats_indication_flags);
272
273 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
274
275 __storm_memset_struct(bp, addr, size, (u32 *)flags);
276}
277
278static inline void storm_memset_cstats_flags(struct bnx2x *bp,
279 struct stats_indication_flags *flags,
280 u16 abs_fid)
281{
282 size_t size = sizeof(struct stats_indication_flags);
283
284 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
285
286 __storm_memset_struct(bp, addr, size, (u32 *)flags);
287}
288
289static inline void storm_memset_xstats_addr(struct bnx2x *bp,
290 dma_addr_t mapping, u16 abs_fid)
291{
292 u32 addr = BAR_XSTRORM_INTMEM +
293 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
294
295 __storm_memset_dma_mapping(bp, addr, mapping);
296}
297
298static inline void storm_memset_tstats_addr(struct bnx2x *bp,
299 dma_addr_t mapping, u16 abs_fid)
300{
301 u32 addr = BAR_TSTRORM_INTMEM +
302 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
303
304 __storm_memset_dma_mapping(bp, addr, mapping);
305}
306
307static inline void storm_memset_ustats_addr(struct bnx2x *bp,
308 dma_addr_t mapping, u16 abs_fid)
309{
310 u32 addr = BAR_USTRORM_INTMEM +
311 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
312
313 __storm_memset_dma_mapping(bp, addr, mapping);
314}
315
316static inline void storm_memset_cstats_addr(struct bnx2x *bp,
317 dma_addr_t mapping, u16 abs_fid)
318{
319 u32 addr = BAR_CSTRORM_INTMEM +
320 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
321
322 __storm_memset_dma_mapping(bp, addr, mapping);
323}
324
325static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
326 u16 pf_id)
327{
328 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
329 pf_id);
330 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
331 pf_id);
332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
333 pf_id);
334 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
335 pf_id);
336}
337
338static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
339 u8 enable)
340{
341 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
342 enable);
343 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
344 enable);
345 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
346 enable);
347 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
348 enable);
349}
350
351static inline void storm_memset_eq_data(struct bnx2x *bp,
352 struct event_ring_data *eq_data,
353 u16 pfid)
354{
355 size_t size = sizeof(struct event_ring_data);
356
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
358
359 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
360}
361
362static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
363 u16 pfid)
364{
365 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
366 REG_WR16(bp, addr, eq_prod);
367}
368
369static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
370 u16 fw_sb_id, u8 sb_index,
371 u8 ticks)
372{
373
f2e0899f
DK		 374 int index_offset = CHIP_IS_E2(bp) ?
375 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 376 offsetof(struct hc_status_block_data_e1x, index_data);
377 u32 addr = BAR_CSTRORM_INTMEM +
378 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
379 index_offset +
380 sizeof(struct hc_index_data)*sb_index +
381 offsetof(struct hc_index_data, timeout);
382 REG_WR8(bp, addr, ticks);
383 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
384 port, fw_sb_id, sb_index, ticks);
385}
386static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
387 u16 fw_sb_id, u8 sb_index,
388 u8 disable)
389{
390 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
f2e0899f
DK		 391 int index_offset = CHIP_IS_E2(bp) ?
392 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 393 offsetof(struct hc_status_block_data_e1x, index_data);
394 u32 addr = BAR_CSTRORM_INTMEM +
395 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
396 index_offset +
397 sizeof(struct hc_index_data)*sb_index +
398 offsetof(struct hc_index_data, flags);
399 u16 flags = REG_RD16(bp, addr);
400 /* clear and set */
401 flags &= ~HC_INDEX_DATA_HC_ENABLED;
402 flags |= enable_flag;
403 REG_WR16(bp, addr, flags);
404 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
405 port, fw_sb_id, sb_index, disable);
406}
407
a2fbb9ea
ET		 408/* used only at init
409 * locking is done by mcp
410 */
8d96286a 411static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 412{
413 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
414 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
415 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
416 PCICFG_VENDOR_ID_OFFSET);
417}
418
a2fbb9ea
ET		 419static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
420{
421 u32 val;
422
423 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
424 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
425 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
426 PCICFG_VENDOR_ID_OFFSET);
427
428 return val;
429}
a2fbb9ea 430
f2e0899f
DK		 431#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
432#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
433#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
434#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
435#define DMAE_DP_DST_NONE "dst_addr [none]"
436
8d96286a 437static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
438 int msglvl)
f2e0899f
DK		 439{
440 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
441
442 switch (dmae->opcode & DMAE_COMMAND_DST) {
443 case DMAE_CMD_DST_PCI:
444 if (src_type == DMAE_CMD_SRC_PCI)
445 DP(msglvl, "DMAE: opcode 0x%08x\n"
446 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
447 "comp_addr [%x:%08x], comp_val 0x%08x\n",
448 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
449 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
450 dmae->comp_addr_hi, dmae->comp_addr_lo,
451 dmae->comp_val);
452 else
453 DP(msglvl, "DMAE: opcode 0x%08x\n"
454 "src [%08x], len [%d*4], dst [%x:%08x]\n"
455 "comp_addr [%x:%08x], comp_val 0x%08x\n",
456 dmae->opcode, dmae->src_addr_lo >> 2,
457 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
458 dmae->comp_addr_hi, dmae->comp_addr_lo,
459 dmae->comp_val);
460 break;
461 case DMAE_CMD_DST_GRC:
462 if (src_type == DMAE_CMD_SRC_PCI)
463 DP(msglvl, "DMAE: opcode 0x%08x\n"
464 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
465 "comp_addr [%x:%08x], comp_val 0x%08x\n",
466 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
467 dmae->len, dmae->dst_addr_lo >> 2,
468 dmae->comp_addr_hi, dmae->comp_addr_lo,
469 dmae->comp_val);
470 else
471 DP(msglvl, "DMAE: opcode 0x%08x\n"
472 "src [%08x], len [%d*4], dst [%08x]\n"
473 "comp_addr [%x:%08x], comp_val 0x%08x\n",
474 dmae->opcode, dmae->src_addr_lo >> 2,
475 dmae->len, dmae->dst_addr_lo >> 2,
476 dmae->comp_addr_hi, dmae->comp_addr_lo,
477 dmae->comp_val);
478 break;
479 default:
480 if (src_type == DMAE_CMD_SRC_PCI)
481 DP(msglvl, "DMAE: opcode 0x%08x\n"
482 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
483 "dst_addr [none]\n"
484 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
485 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
486 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
487 dmae->comp_val);
488 else
489 DP(msglvl, "DMAE: opcode 0x%08x\n"
490 DP_LEVEL "src_addr [%08x] len [%d * 4] "
491 "dst_addr [none]\n"
492 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
493 dmae->opcode, dmae->src_addr_lo >> 2,
494 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
495 dmae->comp_val);
496 break;
497 }
498
499}
500
6c719d00 501const u32 dmae_reg_go_c[] = {
a2fbb9ea
ET		 502 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
503 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
504 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
505 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
506};
507
508/* copy command into DMAE command memory and set DMAE command go */
6c719d00 509void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 510{
511 u32 cmd_offset;
512 int i;
513
514 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
515 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
516 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
517
ad8d3948
EG		 518 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
519 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 520 }
521 REG_WR(bp, dmae_reg_go_c[idx], 1);
522}
523
f2e0899f 524u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 525{
f2e0899f
DK		 526 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
527 DMAE_CMD_C_ENABLE);
528}
ad8d3948 529
f2e0899f
DK		 530u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
531{
532 return opcode & ~DMAE_CMD_SRC_RESET;
533}
ad8d3948 534
f2e0899f
DK		 535u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
536 bool with_comp, u8 comp_type)
537{
538 u32 opcode = 0;
539
540 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
541 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 542
f2e0899f
DK		 543 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
544
545 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
546 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
547 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
548 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 549
a2fbb9ea 550#ifdef __BIG_ENDIAN
f2e0899f 551 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 552#else
f2e0899f 553 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 554#endif
f2e0899f
DK		 555 if (with_comp)
556 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
557 return opcode;
558}
559
8d96286a 560static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
561 struct dmae_command *dmae,
562 u8 src_type, u8 dst_type)
f2e0899f
DK		 563{
564 memset(dmae, 0, sizeof(struct dmae_command));
565
566 /* set the opcode */
567 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
568 true, DMAE_COMP_PCI);
569
570 /* fill in the completion parameters */
571 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
572 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
573 dmae->comp_val = DMAE_COMP_VAL;
574}
575
576/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 577static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
578 struct dmae_command *dmae)
f2e0899f
DK		 579{
580 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
581 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
582 int rc = 0;
583
584 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 585 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
586 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 587
f2e0899f 588 /* lock the dmae channel */
5ff7b6d4
EG		 589 mutex_lock(&bp->dmae_mutex);
590
f2e0899f 591 /* reset completion */
a2fbb9ea
ET		 592 *wb_comp = 0;
593
f2e0899f
DK		 594 /* post the command on the channel used for initializations */
595 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 596
f2e0899f 597 /* wait for completion */
a2fbb9ea 598 udelay(5);
f2e0899f 599 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 600 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
601
ad8d3948 602 if (!cnt) {
c3eefaf6 603 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 604 rc = DMAE_TIMEOUT;
605 goto unlock;
a2fbb9ea 606 }
ad8d3948 607 cnt--;
f2e0899f 608 udelay(50);
a2fbb9ea 609 }
f2e0899f
DK		 610 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
611 BNX2X_ERR("DMAE PCI error!\n");
612 rc = DMAE_PCI_ERROR;
613 }
614
615 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
616 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
617 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 618
f2e0899f 619unlock:
ad8d3948 620 mutex_unlock(&bp->dmae_mutex);
f2e0899f
DK		 621 return rc;
622}
623
624void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
625 u32 len32)
626{
627 struct dmae_command dmae;
628
629 if (!bp->dmae_ready) {
630 u32 *data = bnx2x_sp(bp, wb_data[0]);
631
632 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
633 " using indirect\n", dst_addr, len32);
634 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
635 return;
636 }
637
638 /* set opcode and fixed command fields */
639 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
640
641 /* fill in addresses and len */
642 dmae.src_addr_lo = U64_LO(dma_addr);
643 dmae.src_addr_hi = U64_HI(dma_addr);
644 dmae.dst_addr_lo = dst_addr >> 2;
645 dmae.dst_addr_hi = 0;
646 dmae.len = len32;
647
648 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
649
650 /* issue the command and wait for completion */
651 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 652}
653
c18487ee 654void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 655{
5ff7b6d4 656 struct dmae_command dmae;
ad8d3948
EG		 657
658 if (!bp->dmae_ready) {
659 u32 *data = bnx2x_sp(bp, wb_data[0]);
660 int i;
661
662 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
663 " using indirect\n", src_addr, len32);
664 for (i = 0; i < len32; i++)
665 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
666 return;
667 }
668
f2e0899f
DK		 669 /* set opcode and fixed command fields */
670 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 671
f2e0899f 672 /* fill in addresses and len */
5ff7b6d4
EG		 673 dmae.src_addr_lo = src_addr >> 2;
674 dmae.src_addr_hi = 0;
675 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
676 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
677 dmae.len = len32;
ad8d3948 678
f2e0899f 679 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 680
f2e0899f
DK		 681 /* issue the command and wait for completion */
682 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 683}
684
8d96286a 685static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
686 u32 addr, u32 len)
573f2035 687{
02e3c6cb 688 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 689 int offset = 0;
690
02e3c6cb 691 while (len > dmae_wr_max) {
573f2035 692 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 693 addr + offset, dmae_wr_max);
694 offset += dmae_wr_max * 4;
695 len -= dmae_wr_max;
573f2035
EG		 696 }
697
698 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
699}
700
ad8d3948
EG		 701/* used only for slowpath so not inlined */
702static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
703{
704 u32 wb_write[2];
705
706 wb_write[0] = val_hi;
707 wb_write[1] = val_lo;
708 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 709}
a2fbb9ea 710
ad8d3948
EG		 711#ifdef USE_WB_RD
712static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
713{
714 u32 wb_data[2];
715
716 REG_RD_DMAE(bp, reg, wb_data, 2);
717
718 return HILO_U64(wb_data[0], wb_data[1]);
719}
720#endif
721
a2fbb9ea
ET		 722static int bnx2x_mc_assert(struct bnx2x *bp)
723{
a2fbb9ea 724 char last_idx;
34f80b04
EG		 725 int i, rc = 0;
726 u32 row0, row1, row2, row3;
727
728 /* XSTORM */
729 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
730 XSTORM_ASSERT_LIST_INDEX_OFFSET);
731 if (last_idx)
732 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
733
734 /* print the asserts */
735 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
736
737 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
738 XSTORM_ASSERT_LIST_OFFSET(i));
739 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
740 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
741 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
742 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
743 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
744 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
745
746 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
747 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
748 " 0x%08x 0x%08x 0x%08x\n",
749 i, row3, row2, row1, row0);
750 rc++;
751 } else {
752 break;
753 }
754 }
755
756 /* TSTORM */
757 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
758 TSTORM_ASSERT_LIST_INDEX_OFFSET);
759 if (last_idx)
760 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
761
762 /* print the asserts */
763 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
764
765 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
766 TSTORM_ASSERT_LIST_OFFSET(i));
767 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
768 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
769 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
770 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
771 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
772 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
773
774 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
775 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
776 " 0x%08x 0x%08x 0x%08x\n",
777 i, row3, row2, row1, row0);
778 rc++;
779 } else {
780 break;
781 }
782 }
783
784 /* CSTORM */
785 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
786 CSTORM_ASSERT_LIST_INDEX_OFFSET);
787 if (last_idx)
788 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
789
790 /* print the asserts */
791 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
792
793 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
794 CSTORM_ASSERT_LIST_OFFSET(i));
795 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
796 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
797 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
799 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
800 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
801
802 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
803 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
804 " 0x%08x 0x%08x 0x%08x\n",
805 i, row3, row2, row1, row0);
806 rc++;
807 } else {
808 break;
809 }
810 }
811
812 /* USTORM */
813 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
814 USTORM_ASSERT_LIST_INDEX_OFFSET);
815 if (last_idx)
816 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
817
818 /* print the asserts */
819 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
820
821 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
822 USTORM_ASSERT_LIST_OFFSET(i));
823 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
824 USTORM_ASSERT_LIST_OFFSET(i) + 4);
825 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
826 USTORM_ASSERT_LIST_OFFSET(i) + 8);
827 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
828 USTORM_ASSERT_LIST_OFFSET(i) + 12);
829
830 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
831 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
832 " 0x%08x 0x%08x 0x%08x\n",
833 i, row3, row2, row1, row0);
834 rc++;
835 } else {
836 break;
a2fbb9ea
ET		 837 }
838 }
34f80b04 839
a2fbb9ea
ET		 840 return rc;
841}
c14423fe 842
a2fbb9ea
ET		 843static void bnx2x_fw_dump(struct bnx2x *bp)
844{
cdaa7cb8 845 u32 addr;
a2fbb9ea 846 u32 mark, offset;
4781bfad 847 __be32 data[9];
a2fbb9ea 848 int word;
f2e0899f 849 u32 trace_shmem_base;
2145a920
VZ		 850 if (BP_NOMCP(bp)) {
851 BNX2X_ERR("NO MCP - can not dump\n");
852 return;
853 }
cdaa7cb8 854
f2e0899f
DK		 855 if (BP_PATH(bp) == 0)
856 trace_shmem_base = bp->common.shmem_base;
857 else
858 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
859 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 860 mark = REG_RD(bp, addr);
f2e0899f
DK		 861 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
862 + ((mark + 0x3) & ~0x3) - 0x08000000;
7995c64e 863 pr_err("begin fw dump (mark 0x%x)\n", mark);
a2fbb9ea 864
7995c64e 865 pr_err("");
f2e0899f 866 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 867 for (word = 0; word < 8; word++)
cdaa7cb8 868 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 869 data[8] = 0x0;
7995c64e 870 pr_cont("%s", (char *)data);
a2fbb9ea 871 }
cdaa7cb8 872 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 873 for (word = 0; word < 8; word++)
cdaa7cb8 874 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 875 data[8] = 0x0;
7995c64e 876 pr_cont("%s", (char *)data);
a2fbb9ea 877 }
7995c64e 878 pr_err("end of fw dump\n");
a2fbb9ea
ET		 879}
880
6c719d00 881void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 882{
883 int i;
523224a3
DK		 884 u16 j;
885 struct hc_sp_status_block_data sp_sb_data;
886 int func = BP_FUNC(bp);
887#ifdef BNX2X_STOP_ON_ERROR
888 u16 start = 0, end = 0;
889#endif
a2fbb9ea 890
66e855f3
YG		 891 bp->stats_state = STATS_STATE_DISABLED;
892 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
893
a2fbb9ea
ET		 894 BNX2X_ERR("begin crash dump -----------------\n");
895
8440d2b6
EG		 896 /* Indices */
897 /* Common */
523224a3 898 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
cdaa7cb8 899 " spq_prod_idx(0x%x)\n",
523224a3
DK		 900 bp->def_idx, bp->def_att_idx,
901 bp->attn_state, bp->spq_prod_idx);
902 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
903 bp->def_status_blk->atten_status_block.attn_bits,
904 bp->def_status_blk->atten_status_block.attn_bits_ack,
905 bp->def_status_blk->atten_status_block.status_block_id,
906 bp->def_status_blk->atten_status_block.attn_bits_index);
907 BNX2X_ERR(" def (");
908 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
909 pr_cont("0x%x%s",
910 bp->def_status_blk->sp_sb.index_values[i],
911 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
912
913 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
914 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
915 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
916 i*sizeof(u32));
917
918 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
919 "pf_id(0x%x) vnic_id(0x%x) "
920 "vf_id(0x%x) vf_valid (0x%x)\n",
921 sp_sb_data.igu_sb_id,
922 sp_sb_data.igu_seg_id,
923 sp_sb_data.p_func.pf_id,
924 sp_sb_data.p_func.vnic_id,
925 sp_sb_data.p_func.vf_id,
926 sp_sb_data.p_func.vf_valid);
927
8440d2b6 928
ec6ba945 929 for_each_eth_queue(bp, i) {
a2fbb9ea 930 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 931 int loop;
f2e0899f 932 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 933 struct hc_status_block_data_e1x sb_data_e1x;
934 struct hc_status_block_sm *hc_sm_p =
f2e0899f
DK		 935 CHIP_IS_E2(bp) ?
936 sb_data_e2.common.state_machine :
523224a3
DK		 937 sb_data_e1x.common.state_machine;
938 struct hc_index_data *hc_index_p =
f2e0899f
DK		 939 CHIP_IS_E2(bp) ?
940 sb_data_e2.index_data :
523224a3
DK		 941 sb_data_e1x.index_data;
942 int data_size;
943 u32 *sb_data_p;
944
945 /* Rx */
cdaa7cb8 946 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 947 " rx_comp_prod(0x%x)"
cdaa7cb8 948 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 949 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 950 fp->rx_comp_prod,
66e855f3 951 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 952 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 953 " fp_hc_idx(0x%x)\n",
8440d2b6 954 fp->rx_sge_prod, fp->last_max_sge,
523224a3 955 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 956
523224a3 957 /* Tx */
cdaa7cb8
VZ		 958 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
959 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
960 " *tx_cons_sb(0x%x)\n",
8440d2b6
EG		 961 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
962 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
523224a3 963
f2e0899f
DK		 964 loop = CHIP_IS_E2(bp) ?
965 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
523224a3
DK		 966
967 /* host sb data */
968
ec6ba945
VZ		 969#ifdef BCM_CNIC
970 if (IS_FCOE_FP(fp))
971 continue;
972#endif
523224a3
DK		 973 BNX2X_ERR(" run indexes (");
974 for (j = 0; j < HC_SB_MAX_SM; j++)
975 pr_cont("0x%x%s",
976 fp->sb_running_index[j],
977 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
978
979 BNX2X_ERR(" indexes (");
980 for (j = 0; j < loop; j++)
981 pr_cont("0x%x%s",
982 fp->sb_index_values[j],
983 (j == loop - 1) ? ")" : " ");
984 /* fw sb data */
f2e0899f
DK		 985 data_size = CHIP_IS_E2(bp) ?
986 sizeof(struct hc_status_block_data_e2) :
523224a3
DK		 987 sizeof(struct hc_status_block_data_e1x);
988 data_size /= sizeof(u32);
f2e0899f
DK		 989 sb_data_p = CHIP_IS_E2(bp) ?
990 (u32 *)&sb_data_e2 :
991 (u32 *)&sb_data_e1x;
523224a3
DK		 992 /* copy sb data in here */
993 for (j = 0; j < data_size; j++)
994 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
995 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
996 j * sizeof(u32));
997
f2e0899f
DK		 998 if (CHIP_IS_E2(bp)) {
999 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1000 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1001 sb_data_e2.common.p_func.pf_id,
1002 sb_data_e2.common.p_func.vf_id,
1003 sb_data_e2.common.p_func.vf_valid,
1004 sb_data_e2.common.p_func.vnic_id,
1005 sb_data_e2.common.same_igu_sb_1b);
1006 } else {
1007 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1008 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1009 sb_data_e1x.common.p_func.pf_id,
1010 sb_data_e1x.common.p_func.vf_id,
1011 sb_data_e1x.common.p_func.vf_valid,
1012 sb_data_e1x.common.p_func.vnic_id,
1013 sb_data_e1x.common.same_igu_sb_1b);
1014 }
523224a3
DK		 1015
1016 /* SB_SMs data */
1017 for (j = 0; j < HC_SB_MAX_SM; j++) {
1018 pr_cont("SM[%d] __flags (0x%x) "
1019 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1020 "time_to_expire (0x%x) "
1021 "timer_value(0x%x)\n", j,
1022 hc_sm_p[j].__flags,
1023 hc_sm_p[j].igu_sb_id,
1024 hc_sm_p[j].igu_seg_id,
1025 hc_sm_p[j].time_to_expire,
1026 hc_sm_p[j].timer_value);
1027 }
1028
1029 /* Indecies data */
1030 for (j = 0; j < loop; j++) {
1031 pr_cont("INDEX[%d] flags (0x%x) "
1032 "timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1035 }
8440d2b6 1036 }
a2fbb9ea 1037
523224a3 1038#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 1039 /* Rings */
1040 /* Rx */
ec6ba945 1041 for_each_rx_queue(bp, i) {
8440d2b6 1042 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1043
1044 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1046 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1047 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
c3eefaf6
EG		 1050 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1051 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 1052 }
1053
3196a88a
EG		 1054 start = RX_SGE(fp->rx_sge_prod);
1055 end = RX_SGE(fp->last_max_sge);
8440d2b6 1056 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1057 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
c3eefaf6
EG		 1060 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1061 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1062 }
1063
a2fbb9ea
ET		 1064 start = RCQ_BD(fp->rx_comp_cons - 10);
1065 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1066 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1067 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
c3eefaf6
EG		 1069 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1071 }
1072 }
1073
8440d2b6 1074 /* Tx */
ec6ba945 1075 for_each_tx_queue(bp, i) {
8440d2b6
EG		 1076 struct bnx2x_fastpath *fp = &bp->fp[i];
1077
1078 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1079 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1080 for (j = start; j != end; j = TX_BD(j + 1)) {
1081 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1082
c3eefaf6
EG		 1083 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1084 i, j, sw_bd->skb, sw_bd->first_bd);
8440d2b6
EG		 1085 }
1086
1087 start = TX_BD(fp->tx_bd_cons - 10);
1088 end = TX_BD(fp->tx_bd_cons + 254);
1089 for (j = start; j != end; j = TX_BD(j + 1)) {
1090 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1091
c3eefaf6
EG		 1092 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1093 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
8440d2b6
EG		 1094 }
1095 }
523224a3 1096#endif
34f80b04 1097 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1098 bnx2x_mc_assert(bp);
1099 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1100}
1101
f2e0899f 1102static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1103{
34f80b04 1104 int port = BP_PORT(bp);
a2fbb9ea
ET		 1105 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1106 u32 val = REG_RD(bp, addr);
1107 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1108 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1109
1110 if (msix) {
8badd27a
EG		 1111 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1112 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1113 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1114 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1115 } else if (msi) {
1116 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1117 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1118 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1119 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1120 } else {
1121 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1122 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1123 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1124 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1125
a0fd065c
DK		 1126 if (!CHIP_IS_E1(bp)) {
1127 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1128 val, port, addr);
615f8fd9 1129
a0fd065c 1130 REG_WR(bp, addr, val);
615f8fd9 1131
a0fd065c
DK		 1132 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1133 }
a2fbb9ea
ET		 1134 }
1135
a0fd065c
DK		 1136 if (CHIP_IS_E1(bp))
1137 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1138
8badd27a
EG		 1139 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1140 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1141
1142 REG_WR(bp, addr, val);
37dbbf32
EG		 1143 /*
1144 * Ensure that HC_CONFIG is written before leading/trailing edge config
1145 */
1146 mmiowb();
1147 barrier();
34f80b04 1148
f2e0899f 1149 if (!CHIP_IS_E1(bp)) {
34f80b04 1150 /* init leading/trailing edge */
fb3bff17 1151 if (IS_MF(bp)) {
8badd27a 1152 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1153 if (bp->port.pmf)
4acac6a5
EG		 1154 /* enable nig and gpio3 attention */
1155 val |= 0x1100;
34f80b04
EG		 1156 } else
1157 val = 0xffff;
1158
1159 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1160 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1161 }
37dbbf32
EG		 1162
1163 /* Make sure that interrupts are indeed enabled from here on */
1164 mmiowb();
a2fbb9ea
ET		 1165}
1166
f2e0899f
DK		 1167static void bnx2x_igu_int_enable(struct bnx2x *bp)
1168{
1169 u32 val;
1170 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1171 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1172
1173 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1174
1175 if (msix) {
1176 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1177 IGU_PF_CONF_SINGLE_ISR_EN);
1178 val |= (IGU_PF_CONF_FUNC_EN |
1179 IGU_PF_CONF_MSI_MSIX_EN |
1180 IGU_PF_CONF_ATTN_BIT_EN);
1181 } else if (msi) {
1182 val &= ~IGU_PF_CONF_INT_LINE_EN;
1183 val |= (IGU_PF_CONF_FUNC_EN |
1184 IGU_PF_CONF_MSI_MSIX_EN |
1185 IGU_PF_CONF_ATTN_BIT_EN |
1186 IGU_PF_CONF_SINGLE_ISR_EN);
1187 } else {
1188 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1189 val |= (IGU_PF_CONF_FUNC_EN |
1190 IGU_PF_CONF_INT_LINE_EN |
1191 IGU_PF_CONF_ATTN_BIT_EN |
1192 IGU_PF_CONF_SINGLE_ISR_EN);
1193 }
1194
1195 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1196 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1197
1198 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1199
1200 barrier();
1201
1202 /* init leading/trailing edge */
1203 if (IS_MF(bp)) {
1204 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1205 if (bp->port.pmf)
1206 /* enable nig and gpio3 attention */
1207 val |= 0x1100;
1208 } else
1209 val = 0xffff;
1210
1211 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1212 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1213
1214 /* Make sure that interrupts are indeed enabled from here on */
1215 mmiowb();
1216}
1217
1218void bnx2x_int_enable(struct bnx2x *bp)
1219{
1220 if (bp->common.int_block == INT_BLOCK_HC)
1221 bnx2x_hc_int_enable(bp);
1222 else
1223 bnx2x_igu_int_enable(bp);
1224}
1225
1226static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1227{
34f80b04 1228 int port = BP_PORT(bp);
a2fbb9ea
ET		 1229 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1230 u32 val = REG_RD(bp, addr);
1231
a0fd065c
DK		 1232 /*
1233 * in E1 we must use only PCI configuration space to disable
1234 * MSI/MSIX capablility
1235 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1236 */
1237 if (CHIP_IS_E1(bp)) {
1238 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1239 * Use mask register to prevent from HC sending interrupts
1240 * after we exit the function
1241 */
1242 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1243
1244 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1245 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1246 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1247 } else
1248 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1249 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1250 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1251 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1252
1253 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1254 val, port, addr);
1255
8badd27a
EG		 1256 /* flush all outstanding writes */
1257 mmiowb();
1258
a2fbb9ea
ET		 1259 REG_WR(bp, addr, val);
1260 if (REG_RD(bp, addr) != val)
1261 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1262}
1263
f2e0899f
DK		 1264static void bnx2x_igu_int_disable(struct bnx2x *bp)
1265{
1266 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1267
1268 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1269 IGU_PF_CONF_INT_LINE_EN |
1270 IGU_PF_CONF_ATTN_BIT_EN);
1271
1272 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1273
1274 /* flush all outstanding writes */
1275 mmiowb();
1276
1277 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1278 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1279 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1280}
1281
8d96286a 1282static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1283{
1284 if (bp->common.int_block == INT_BLOCK_HC)
1285 bnx2x_hc_int_disable(bp);
1286 else
1287 bnx2x_igu_int_disable(bp);
1288}
1289
9f6c9258 1290void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1291{
a2fbb9ea 1292 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1293 int i, offset;
a2fbb9ea 1294
34f80b04 1295 /* disable interrupt handling */
a2fbb9ea 1296 atomic_inc(&bp->intr_sem);
e1510706
EG		 1297 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1298
f8ef6e44
YG		 1299 if (disable_hw)
1300 /* prevent the HW from sending interrupts */
1301 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1302
1303 /* make sure all ISRs are done */
1304 if (msix) {
8badd27a
EG		 1305 synchronize_irq(bp->msix_table[0].vector);
1306 offset = 1;
37b091ba
MC		 1307#ifdef BCM_CNIC
1308 offset++;
1309#endif
ec6ba945 1310 for_each_eth_queue(bp, i)
8badd27a 1311 synchronize_irq(bp->msix_table[i + offset].vector);
a2fbb9ea
ET		 1312 } else
1313 synchronize_irq(bp->pdev->irq);
1314
1315 /* make sure sp_task is not running */
1cf167f2
EG		 1316 cancel_delayed_work(&bp->sp_task);
1317 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1318}
1319
34f80b04 1320/* fast path */
a2fbb9ea
ET		 1321
1322/*
34f80b04 1323 * General service functions
a2fbb9ea
ET		 1324 */
1325
72fd0718
VZ		 1326/* Return true if succeeded to acquire the lock */
1327static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1328{
1329 u32 lock_status;
1330 u32 resource_bit = (1 << resource);
1331 int func = BP_FUNC(bp);
1332 u32 hw_lock_control_reg;
1333
1334 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1335
1336 /* Validating that the resource is within range */
1337 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1338 DP(NETIF_MSG_HW,
1339 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1340 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1341 return false;
72fd0718
VZ		 1342 }
1343
1344 if (func <= 5)
1345 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1346 else
1347 hw_lock_control_reg =
1348 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1349
1350 /* Try to acquire the lock */
1351 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1352 lock_status = REG_RD(bp, hw_lock_control_reg);
1353 if (lock_status & resource_bit)
1354 return true;
1355
1356 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1357 return false;
1358}
1359
993ac7b5
MC		 1360#ifdef BCM_CNIC
1361static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1362#endif
3196a88a 1363
9f6c9258 1364void bnx2x_sp_event(struct bnx2x_fastpath *fp,
a2fbb9ea
ET		 1365 union eth_rx_cqe *rr_cqe)
1366{
1367 struct bnx2x *bp = fp->bp;
1368 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1369 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1370
34f80b04 1371 DP(BNX2X_MSG_SP,
a2fbb9ea 1372 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1373 fp->index, cid, command, bp->state,
34f80b04 1374 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1375
523224a3
DK		 1376 switch (command | fp->state) {
1377 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1378 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1379 fp->state = BNX2X_FP_STATE_OPEN;
a2fbb9ea
ET		 1380 break;
1381
523224a3
DK		 1382 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1383 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
a2fbb9ea
ET		 1384 fp->state = BNX2X_FP_STATE_HALTED;
1385 break;
1386
523224a3
DK		 1387 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1388 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1389 fp->state = BNX2X_FP_STATE_TERMINATED;
a2fbb9ea
ET		 1390 break;
1391
523224a3
DK		 1392 default:
1393 BNX2X_ERR("unexpected MC reply (%d) "
1394 "fp[%d] state is %x\n",
1395 command, fp->index, fp->state);
993ac7b5 1396 break;
523224a3 1397 }
3196a88a 1398
8fe23fbd
DK		 1399 smp_mb__before_atomic_inc();
1400 atomic_inc(&bp->spq_left);
523224a3
DK		 1401 /* push the change in fp->state and towards the memory */
1402 smp_wmb();
49d66772 1403
523224a3 1404 return;
a2fbb9ea
ET		 1405}
1406
9f6c9258 1407irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1408{
555f6c78 1409 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1410 u16 status = bnx2x_ack_int(bp);
34f80b04 1411 u16 mask;
ca00392c 1412 int i;
a2fbb9ea 1413
34f80b04 1414 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1415 if (unlikely(status == 0)) {
1416 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1417 return IRQ_NONE;
1418 }
f5372251 1419 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1420
34f80b04 1421 /* Return here if interrupt is disabled */
a2fbb9ea
ET		 1422 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1423 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1424 return IRQ_HANDLED;
1425 }
1426
3196a88a
EG		 1427#ifdef BNX2X_STOP_ON_ERROR
1428 if (unlikely(bp->panic))
1429 return IRQ_HANDLED;
1430#endif
1431
ec6ba945 1432 for_each_eth_queue(bp, i) {
ca00392c 1433 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1434
523224a3 1435 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
ca00392c 1436 if (status & mask) {
54b9ddaa
VZ		 1437 /* Handle Rx and Tx according to SB id */
1438 prefetch(fp->rx_cons_sb);
54b9ddaa 1439 prefetch(fp->tx_cons_sb);
523224a3 1440 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1441 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1442 status &= ~mask;
1443 }
a2fbb9ea
ET		 1444 }
1445
993ac7b5 1446#ifdef BCM_CNIC
523224a3 1447 mask = 0x2;
993ac7b5
MC		 1448 if (status & (mask | 0x1)) {
1449 struct cnic_ops *c_ops = NULL;
1450
1451 rcu_read_lock();
1452 c_ops = rcu_dereference(bp->cnic_ops);
1453 if (c_ops)
1454 c_ops->cnic_handler(bp->cnic_data, NULL);
1455 rcu_read_unlock();
1456
1457 status &= ~mask;
1458 }
1459#endif
a2fbb9ea 1460
34f80b04 1461 if (unlikely(status & 0x1)) {
1cf167f2 1462 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1463
1464 status &= ~0x1;
1465 if (!status)
1466 return IRQ_HANDLED;
1467 }
1468
cdaa7cb8
VZ		 1469 if (unlikely(status))
1470 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1471 status);
a2fbb9ea 1472
c18487ee 1473 return IRQ_HANDLED;
a2fbb9ea
ET		 1474}
1475
c18487ee 1476/* end of fast path */
a2fbb9ea 1477
a2fbb9ea 1478
c18487ee
YR		 1479/* Link */
1480
1481/*
1482 * General service functions
1483 */
a2fbb9ea 1484
9f6c9258 1485int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1486{
1487 u32 lock_status;
1488 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1489 int func = BP_FUNC(bp);
1490 u32 hw_lock_control_reg;
c18487ee 1491 int cnt;
a2fbb9ea 1492
c18487ee
YR		 1493 /* Validating that the resource is within range */
1494 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1495 DP(NETIF_MSG_HW,
1496 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1497 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1498 return -EINVAL;
1499 }
a2fbb9ea 1500
4a37fb66
YG		 1501 if (func <= 5) {
1502 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1503 } else {
1504 hw_lock_control_reg =
1505 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1506 }
1507
c18487ee 1508 /* Validating that the resource is not already taken */
4a37fb66 1509 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1510 if (lock_status & resource_bit) {
1511 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1512 lock_status, resource_bit);
1513 return -EEXIST;
1514 }
a2fbb9ea 1515
46230476
EG		 1516 /* Try for 5 second every 5ms */
1517 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1518 /* Try to acquire the lock */
4a37fb66
YG		 1519 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1520 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1521 if (lock_status & resource_bit)
1522 return 0;
a2fbb9ea 1523
c18487ee 1524 msleep(5);
a2fbb9ea 1525 }
c18487ee
YR		 1526 DP(NETIF_MSG_HW, "Timeout\n");
1527 return -EAGAIN;
1528}
a2fbb9ea 1529
9f6c9258 1530int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1531{
1532 u32 lock_status;
1533 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1534 int func = BP_FUNC(bp);
1535 u32 hw_lock_control_reg;
a2fbb9ea 1536
72fd0718
VZ		 1537 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1538
c18487ee
YR		 1539 /* Validating that the resource is within range */
1540 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1541 DP(NETIF_MSG_HW,
1542 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1543 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1544 return -EINVAL;
1545 }
1546
4a37fb66
YG		 1547 if (func <= 5) {
1548 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1549 } else {
1550 hw_lock_control_reg =
1551 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1552 }
1553
c18487ee 1554 /* Validating that the resource is currently taken */
4a37fb66 1555 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1556 if (!(lock_status & resource_bit)) {
1557 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1558 lock_status, resource_bit);
1559 return -EFAULT;
a2fbb9ea
ET		 1560 }
1561
9f6c9258
DK		 1562 REG_WR(bp, hw_lock_control_reg, resource_bit);
1563 return 0;
c18487ee 1564}
a2fbb9ea 1565
9f6c9258 1566
4acac6a5
EG		 1567int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1568{
1569 /* The GPIO should be swapped if swap register is set and active */
1570 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1571 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1572 int gpio_shift = gpio_num +
1573 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1574 u32 gpio_mask = (1 << gpio_shift);
1575 u32 gpio_reg;
1576 int value;
1577
1578 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1579 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1580 return -EINVAL;
1581 }
1582
1583 /* read GPIO value */
1584 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1585
1586 /* get the requested pin value */
1587 if ((gpio_reg & gpio_mask) == gpio_mask)
1588 value = 1;
1589 else
1590 value = 0;
1591
1592 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1593
1594 return value;
1595}
1596
17de50b7 1597int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1598{
1599 /* The GPIO should be swapped if swap register is set and active */
1600 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1601 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1602 int gpio_shift = gpio_num +
1603 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1604 u32 gpio_mask = (1 << gpio_shift);
1605 u32 gpio_reg;
a2fbb9ea 1606
c18487ee
YR		 1607 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1608 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1609 return -EINVAL;
1610 }
a2fbb9ea 1611
4a37fb66 1612 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1613 /* read GPIO and mask except the float bits */
1614 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1615
c18487ee
YR		 1616 switch (mode) {
1617 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1618 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1619 gpio_num, gpio_shift);
1620 /* clear FLOAT and set CLR */
1621 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1622 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1623 break;
a2fbb9ea 1624
c18487ee
YR		 1625 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1626 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1627 gpio_num, gpio_shift);
1628 /* clear FLOAT and set SET */
1629 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1631 break;
a2fbb9ea 1632
17de50b7 1633 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1634 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1635 gpio_num, gpio_shift);
1636 /* set FLOAT */
1637 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1638 break;
a2fbb9ea 1639
c18487ee
YR		 1640 default:
1641 break;
a2fbb9ea
ET		 1642 }
1643
c18487ee 1644 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1645 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1646
c18487ee 1647 return 0;
a2fbb9ea
ET		 1648}
1649
4acac6a5
EG		 1650int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1651{
1652 /* The GPIO should be swapped if swap register is set and active */
1653 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1654 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1655 int gpio_shift = gpio_num +
1656 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1657 u32 gpio_mask = (1 << gpio_shift);
1658 u32 gpio_reg;
1659
1660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1661 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1662 return -EINVAL;
1663 }
1664
1665 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1666 /* read GPIO int */
1667 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1668
1669 switch (mode) {
1670 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1671 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1672 "output low\n", gpio_num, gpio_shift);
1673 /* clear SET and set CLR */
1674 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1675 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 break;
1677
1678 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1679 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1680 "output high\n", gpio_num, gpio_shift);
1681 /* clear CLR and set SET */
1682 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1683 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1684 break;
1685
1686 default:
1687 break;
1688 }
1689
1690 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1691 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1692
1693 return 0;
1694}
1695
c18487ee 1696static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 1697{
c18487ee
YR		 1698 u32 spio_mask = (1 << spio_num);
1699 u32 spio_reg;
a2fbb9ea 1700
c18487ee
YR		 1701 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1702 (spio_num > MISC_REGISTERS_SPIO_7)) {
1703 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1704 return -EINVAL;
a2fbb9ea
ET		 1705 }
1706
4a37fb66 1707 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 1708 /* read SPIO and mask except the float bits */
1709 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 1710
c18487ee 1711 switch (mode) {
6378c025 1712 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1714 /* clear FLOAT and set CLR */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1717 break;
a2fbb9ea 1718
6378c025 1719 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1721 /* clear FLOAT and set SET */
1722 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1724 break;
a2fbb9ea 1725
c18487ee
YR		 1726 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1727 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1728 /* set FLOAT */
1729 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1730 break;
a2fbb9ea 1731
c18487ee
YR		 1732 default:
1733 break;
a2fbb9ea
ET		 1734 }
1735
c18487ee 1736 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 1737 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 1738
a2fbb9ea
ET		 1739 return 0;
1740}
1741
a22f0788
YR		 1742int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1743{
1744 u32 sel_phy_idx = 0;
1745 if (bp->link_vars.link_up) {
1746 sel_phy_idx = EXT_PHY1;
1747 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1748 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1749 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1750 sel_phy_idx = EXT_PHY2;
1751 } else {
1752
1753 switch (bnx2x_phy_selection(&bp->link_params)) {
1754 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1755 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1756 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1757 sel_phy_idx = EXT_PHY1;
1758 break;
1759 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1760 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1761 sel_phy_idx = EXT_PHY2;
1762 break;
1763 }
1764 }
1765 /*
1766 * The selected actived PHY is always after swapping (in case PHY
1767 * swapping is enabled). So when swapping is enabled, we need to reverse
1768 * the configuration
1769 */
1770
1771 if (bp->link_params.multi_phy_config &
1772 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1773 if (sel_phy_idx == EXT_PHY1)
1774 sel_phy_idx = EXT_PHY2;
1775 else if (sel_phy_idx == EXT_PHY2)
1776 sel_phy_idx = EXT_PHY1;
1777 }
1778 return LINK_CONFIG_IDX(sel_phy_idx);
1779}
1780
9f6c9258 1781void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 1782{
a22f0788 1783 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 1784 switch (bp->link_vars.ieee_fc &
1785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 1786 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 1787 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1788 ADVERTISED_Pause);
c18487ee 1789 break;
356e2385 1790
c18487ee 1791 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 1792 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 1793 ADVERTISED_Pause);
c18487ee 1794 break;
356e2385 1795
c18487ee 1796 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 1797 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 1798 break;
356e2385 1799
c18487ee 1800 default:
a22f0788 1801 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1802 ADVERTISED_Pause);
c18487ee
YR		 1803 break;
1804 }
1805}
f1410647 1806
9f6c9258 1807u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 1808{
19680c48
EG		 1809 if (!BP_NOMCP(bp)) {
1810 u8 rc;
a22f0788
YR		 1811 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1812 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 1813 /* Initialize link parameters structure variables */
8c99e7b0
YR		 1814 /* It is recommended to turn off RX FC for jumbo frames
1815 for better performance */
f2e0899f 1816 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 1817 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 1818 else
c0700f90 1819 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 1820
4a37fb66 1821 bnx2x_acquire_phy_lock(bp);
b5bf9068 1822
a22f0788 1823 if (load_mode == LOAD_DIAG) {
de6eae1f 1824 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 1825 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1826 }
b5bf9068 1827
19680c48 1828 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 1829
4a37fb66 1830 bnx2x_release_phy_lock(bp);
a2fbb9ea 1831
3c96c68b
EG		 1832 bnx2x_calc_fc_adv(bp);
1833
b5bf9068
EG		 1834 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1835 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 1836 bnx2x_link_report(bp);
b5bf9068 1837 }
a22f0788 1838 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 1839 return rc;
1840 }
f5372251 1841 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 1842 return -EINVAL;
a2fbb9ea
ET		 1843}
1844
9f6c9258 1845void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 1846{
19680c48 1847 if (!BP_NOMCP(bp)) {
4a37fb66 1848 bnx2x_acquire_phy_lock(bp);
54c2fb78 1849 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 1850 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 1851 bnx2x_release_phy_lock(bp);
a2fbb9ea 1852
19680c48
EG		 1853 bnx2x_calc_fc_adv(bp);
1854 } else
f5372251 1855 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 1856}
a2fbb9ea 1857
c18487ee
YR		 1858static void bnx2x__link_reset(struct bnx2x *bp)
1859{
19680c48 1860 if (!BP_NOMCP(bp)) {
4a37fb66 1861 bnx2x_acquire_phy_lock(bp);
589abe3a 1862 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 1863 bnx2x_release_phy_lock(bp);
19680c48 1864 } else
f5372251 1865 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 1866}
a2fbb9ea 1867
a22f0788 1868u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 1869{
2145a920 1870 u8 rc = 0;
a2fbb9ea 1871
2145a920
VZ		 1872 if (!BP_NOMCP(bp)) {
1873 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 1874 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1875 is_serdes);
2145a920
VZ		 1876 bnx2x_release_phy_lock(bp);
1877 } else
1878 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 1879
c18487ee
YR		 1880 return rc;
1881}
a2fbb9ea 1882
8a1c38d1 1883static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 1884{
8a1c38d1
EG		 1885 u32 r_param = bp->link_vars.line_speed / 8;
1886 u32 fair_periodic_timeout_usec;
1887 u32 t_fair;
34f80b04 1888
8a1c38d1
EG		 1889 memset(&(bp->cmng.rs_vars), 0,
1890 sizeof(struct rate_shaping_vars_per_port));
1891 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 1892
8a1c38d1
EG		 1893 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1894 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 1895
8a1c38d1
EG		 1896 /* this is the threshold below which no timer arming will occur
1897 1.25 coefficient is for the threshold to be a little bigger
1898 than the real time, to compensate for timer in-accuracy */
1899 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 1900 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1901
8a1c38d1
EG		 1902 /* resolution of fairness timer */
1903 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1904 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1905 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 1906
8a1c38d1
EG		 1907 /* this is the threshold below which we won't arm the timer anymore */
1908 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 1909
8a1c38d1
EG		 1910 /* we multiply by 1e3/8 to get bytes/msec.
1911 We don't want the credits to pass a credit
1912 of the t_fair*FAIR_MEM (algorithm resolution) */
1913 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1914 /* since each tick is 4 usec */
1915 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 1916}
1917
2691d51d
EG		 1918/* Calculates the sum of vn_min_rates.
1919 It's needed for further normalizing of the min_rates.
1920 Returns:
1921 sum of vn_min_rates.
1922 or
1923 0 - if all the min_rates are 0.
1924 In the later case fainess algorithm should be deactivated.
1925 If not all min_rates are zero then those that are zeroes will be set to 1.
1926 */
1927static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1928{
1929 int all_zero = 1;
2691d51d
EG		 1930 int vn;
1931
1932 bp->vn_weight_sum = 0;
1933 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 1934 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 1935 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1936 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1937
1938 /* Skip hidden vns */
1939 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1940 continue;
1941
1942 /* If min rate is zero - set it to 1 */
1943 if (!vn_min_rate)
1944 vn_min_rate = DEF_MIN_RATE;
1945 else
1946 all_zero = 0;
1947
1948 bp->vn_weight_sum += vn_min_rate;
1949 }
1950
1951 /* ... only if all min rates are zeros - disable fairness */
b015e3d1
EG		 1952 if (all_zero) {
1953 bp->cmng.flags.cmng_enables &=
1954 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1955 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1956 " fairness will be disabled\n");
1957 } else
1958 bp->cmng.flags.cmng_enables |=
1959 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 1960}
1961
f2e0899f 1962static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 1963{
1964 struct rate_shaping_vars_per_vn m_rs_vn;
1965 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 1966 u32 vn_cfg = bp->mf_config[vn];
1967 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 1968 u16 vn_min_rate, vn_max_rate;
1969 int i;
1970
1971 /* If function is hidden - set min and max to zeroes */
1972 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1973 vn_min_rate = 0;
1974 vn_max_rate = 0;
1975
1976 } else {
1977 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1978 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
b015e3d1 1979 /* If min rate is zero - set it to 1 */
f2e0899f 1980 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04
EG		 1981 vn_min_rate = DEF_MIN_RATE;
1982 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1983 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
1984 }
f85582f8 1985
8a1c38d1 1986 DP(NETIF_MSG_IFUP,
b015e3d1 1987 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 1988 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 1989
1990 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1991 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1992
1993 /* global vn counter - maximal Mbps for this vn */
1994 m_rs_vn.vn_counter.rate = vn_max_rate;
1995
1996 /* quota - number of bytes transmitted in this period */
1997 m_rs_vn.vn_counter.quota =
1998 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
1999
8a1c38d1 2000 if (bp->vn_weight_sum) {
34f80b04
EG		 2001 /* credit for each period of the fairness algorithm:
2002 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2003 vn_weight_sum should not be larger than 10000, thus
2004 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2005 than zero */
34f80b04 2006 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2007 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2008 (8 * bp->vn_weight_sum))),
2009 (bp->cmng.fair_vars.fair_threshold * 2));
2010 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2011 m_fair_vn.vn_credit_delta);
2012 }
2013
34f80b04
EG		 2014 /* Store it to internal memory */
2015 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2016 REG_WR(bp, BAR_XSTRORM_INTMEM +
2017 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2018 ((u32 *)(&m_rs_vn))[i]);
2019
2020 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2021 REG_WR(bp, BAR_XSTRORM_INTMEM +
2022 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2023 ((u32 *)(&m_fair_vn))[i]);
2024}
f85582f8 2025
523224a3
DK		 2026static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2027{
2028 if (CHIP_REV_IS_SLOW(bp))
2029 return CMNG_FNS_NONE;
fb3bff17 2030 if (IS_MF(bp))
523224a3
DK		 2031 return CMNG_FNS_MINMAX;
2032
2033 return CMNG_FNS_NONE;
2034}
2035
2036static void bnx2x_read_mf_cfg(struct bnx2x *bp)
2037{
0793f83f 2038 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2039
2040 if (BP_NOMCP(bp))
2041 return; /* what should be the default bvalue in this case */
2042
0793f83f
DK		 2043 /* For 2 port configuration the absolute function number formula
2044 * is:
2045 * abs_func = 2 * vn + BP_PORT + BP_PATH
2046 *
2047 * and there are 4 functions per port
2048 *
2049 * For 4 port configuration it is
2050 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2051 *
2052 * and there are 2 functions per port
2053 */
523224a3 2054 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2055 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2056
2057 if (func >= E1H_FUNC_MAX)
2058 break;
2059
f2e0899f 2060 bp->mf_config[vn] =
523224a3
DK		 2061 MF_CFG_RD(bp, func_mf_config[func].config);
2062 }
2063}
2064
2065static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2066{
2067
2068 if (cmng_type == CMNG_FNS_MINMAX) {
2069 int vn;
2070
2071 /* clear cmng_enables */
2072 bp->cmng.flags.cmng_enables = 0;
2073
2074 /* read mf conf from shmem */
2075 if (read_cfg)
2076 bnx2x_read_mf_cfg(bp);
2077
2078 /* Init rate shaping and fairness contexts */
2079 bnx2x_init_port_minmax(bp);
2080
2081 /* vn_weight_sum and enable fairness if not 0 */
2082 bnx2x_calc_vn_weight_sum(bp);
2083
2084 /* calculate and set min-max rate for each vn */
2085 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2086 bnx2x_init_vn_minmax(bp, vn);
2087
2088 /* always enable rate shaping and fairness */
2089 bp->cmng.flags.cmng_enables |=
2090 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2091 if (!bp->vn_weight_sum)
2092 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2093 " fairness will be disabled\n");
2094 return;
2095 }
2096
2097 /* rate shaping and fairness are disabled */
2098 DP(NETIF_MSG_IFUP,
2099 "rate shaping and fairness are disabled\n");
2100}
34f80b04 2101
523224a3
DK		 2102static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2103{
2104 int port = BP_PORT(bp);
2105 int func;
2106 int vn;
2107
2108 /* Set the attention towards other drivers on the same port */
2109 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2110 if (vn == BP_E1HVN(bp))
2111 continue;
2112
2113 func = ((vn << 1) | port);
2114 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2115 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2116 }
2117}
8a1c38d1 2118
c18487ee
YR		 2119/* This function is called upon link interrupt */
2120static void bnx2x_link_attn(struct bnx2x *bp)
2121{
d9e8b185 2122 u32 prev_link_status = bp->link_vars.link_status;
bb2a0f7a
YG		 2123 /* Make sure that we are synced with the current statistics */
2124 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2125
c18487ee 2126 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2127
bb2a0f7a
YG		 2128 if (bp->link_vars.link_up) {
2129
1c06328c 2130 /* dropless flow control */
f2e0899f 2131 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2132 int port = BP_PORT(bp);
2133 u32 pause_enabled = 0;
2134
2135 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2136 pause_enabled = 1;
2137
2138 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2139 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2140 pause_enabled);
2141 }
2142
bb2a0f7a
YG		 2143 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2144 struct host_port_stats *pstats;
2145
2146 pstats = bnx2x_sp(bp, port_stats);
2147 /* reset old bmac stats */
2148 memset(&(pstats->mac_stx[0]), 0,
2149 sizeof(struct mac_stx));
2150 }
f34d28ea 2151 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2152 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2153 }
2154
d9e8b185
VZ		 2155 /* indicate link status only if link status actually changed */
2156 if (prev_link_status != bp->link_vars.link_status)
2157 bnx2x_link_report(bp);
34f80b04 2158
f2e0899f
DK		 2159 if (IS_MF(bp))
2160 bnx2x_link_sync_notify(bp);
34f80b04 2161
f2e0899f
DK		 2162 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2163 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2164
f2e0899f
DK		 2165 if (cmng_fns != CMNG_FNS_NONE) {
2166 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2167 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2168 } else
2169 /* rate shaping and fairness are disabled */
2170 DP(NETIF_MSG_IFUP,
2171 "single function mode without fairness\n");
34f80b04 2172 }
c18487ee 2173}
a2fbb9ea 2174
9f6c9258 2175void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2176{
f34d28ea 2177 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
c18487ee 2178 return;
a2fbb9ea 2179
c18487ee 2180 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2181
bb2a0f7a
YG		 2182 if (bp->link_vars.link_up)
2183 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2184 else
2185 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2186
f2e0899f
DK		 2187 /* the link status update could be the result of a DCC event
2188 hence re-read the shmem mf configuration */
2189 bnx2x_read_mf_cfg(bp);
2691d51d 2190
c18487ee
YR		 2191 /* indicate link status */
2192 bnx2x_link_report(bp);
a2fbb9ea 2193}
a2fbb9ea 2194
34f80b04
EG		 2195static void bnx2x_pmf_update(struct bnx2x *bp)
2196{
2197 int port = BP_PORT(bp);
2198 u32 val;
2199
2200 bp->port.pmf = 1;
2201 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2202
2203 /* enable nig attention */
2204 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2205 if (bp->common.int_block == INT_BLOCK_HC) {
2206 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2207 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2208 } else if (CHIP_IS_E2(bp)) {
2209 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2210 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2211 }
bb2a0f7a
YG		 2212
2213 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2214}
2215
c18487ee 2216/* end of Link */
a2fbb9ea
ET		 2217
2218/* slow path */
2219
2220/*
2221 * General service functions
2222 */
2223
2691d51d 2224/* send the MCP a request, block until there is a reply */
a22f0788 2225u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2226{
f2e0899f 2227 int mb_idx = BP_FW_MB_IDX(bp);
2691d51d
EG		 2228 u32 seq = ++bp->fw_seq;
2229 u32 rc = 0;
2230 u32 cnt = 1;
2231 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2232
c4ff7cbf 2233 mutex_lock(&bp->fw_mb_mutex);
f2e0899f
DK		 2234 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2235 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2236
2691d51d
EG		 2237 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2238
2239 do {
2240 /* let the FW do it's magic ... */
2241 msleep(delay);
2242
f2e0899f 2243 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2244
c4ff7cbf
EG		 2245 /* Give the FW up to 5 second (500*10ms) */
2246 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2247
2248 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2249 cnt*delay, rc, seq);
2250
2251 /* is this a reply to our command? */
2252 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2253 rc &= FW_MSG_CODE_MASK;
2254 else {
2255 /* FW BUG! */
2256 BNX2X_ERR("FW failed to respond!\n");
2257 bnx2x_fw_dump(bp);
2258 rc = 0;
2259 }
c4ff7cbf 2260 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2261
2262 return rc;
2263}
2264
ec6ba945
VZ		 2265static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2266{
2267#ifdef BCM_CNIC
2268 if (IS_FCOE_FP(fp) && IS_MF(bp))
2269 return false;
2270#endif
2271 return true;
2272}
2273
523224a3 2274/* must be called under rtnl_lock */
8d96286a 2275static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2691d51d 2276{
523224a3 2277 u32 mask = (1 << cl_id);
2691d51d 2278
523224a3
DK		 2279 /* initial seeting is BNX2X_ACCEPT_NONE */
2280 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2281 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2282 u8 unmatched_unicast = 0;
2691d51d 2283
0793f83f
DK		 2284 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2285 unmatched_unicast = 1;
2286
523224a3
DK		 2287 if (filters & BNX2X_PROMISCUOUS_MODE) {
2288 /* promiscious - accept all, drop none */
2289 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2290 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
0793f83f
DK		 2291 if (IS_MF_SI(bp)) {
2292 /*
2293 * SI mode defines to accept in promiscuos mode
2294 * only unmatched packets
2295 */
2296 unmatched_unicast = 1;
2297 accp_all_ucast = 0;
2298 }
523224a3
DK		 2299 }
2300 if (filters & BNX2X_ACCEPT_UNICAST) {
2301 /* accept matched ucast */
2302 drop_all_ucast = 0;
2303 }
d9c8f498 2304 if (filters & BNX2X_ACCEPT_MULTICAST)
523224a3
DK		 2305 /* accept matched mcast */
2306 drop_all_mcast = 0;
d9c8f498 2307
523224a3
DK		 2308 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2309 /* accept all mcast */
2310 drop_all_ucast = 0;
2311 accp_all_ucast = 1;
2312 }
2313 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2314 /* accept all mcast */
2315 drop_all_mcast = 0;
2316 accp_all_mcast = 1;
2317 }
2318 if (filters & BNX2X_ACCEPT_BROADCAST) {
2319 /* accept (all) bcast */
2320 drop_all_bcast = 0;
2321 accp_all_bcast = 1;
2322 }
2691d51d 2323
523224a3
DK		 2324 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2325 bp->mac_filters.ucast_drop_all | mask :
2326 bp->mac_filters.ucast_drop_all & ~mask;
2691d51d 2327
523224a3
DK		 2328 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2329 bp->mac_filters.mcast_drop_all | mask :
2330 bp->mac_filters.mcast_drop_all & ~mask;
2691d51d 2331
523224a3
DK		 2332 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2333 bp->mac_filters.bcast_drop_all | mask :
2334 bp->mac_filters.bcast_drop_all & ~mask;
2691d51d 2335
523224a3
DK		 2336 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2337 bp->mac_filters.ucast_accept_all | mask :
2338 bp->mac_filters.ucast_accept_all & ~mask;
2691d51d 2339
523224a3
DK		 2340 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2341 bp->mac_filters.mcast_accept_all | mask :
2342 bp->mac_filters.mcast_accept_all & ~mask;
2343
2344 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2345 bp->mac_filters.bcast_accept_all | mask :
2346 bp->mac_filters.bcast_accept_all & ~mask;
2347
2348 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2349 bp->mac_filters.unmatched_unicast | mask :
2350 bp->mac_filters.unmatched_unicast & ~mask;
2691d51d
EG		 2351}
2352
8d96286a 2353static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2691d51d 2354{
030f3356
DK		 2355 struct tstorm_eth_function_common_config tcfg = {0};
2356 u16 rss_flgs;
2691d51d 2357
030f3356
DK		 2358 /* tpa */
2359 if (p->func_flgs & FUNC_FLG_TPA)
2360 tcfg.config_flags |=
2361 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2691d51d 2362
030f3356
DK		 2363 /* set rss flags */
2364 rss_flgs = (p->rss->mode <<
2365 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2366
2367 if (p->rss->cap & RSS_IPV4_CAP)
2368 rss_flgs |= RSS_IPV4_CAP_MASK;
2369 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2370 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2371 if (p->rss->cap & RSS_IPV6_CAP)
2372 rss_flgs |= RSS_IPV6_CAP_MASK;
2373 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2374 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2375
2376 tcfg.config_flags |= rss_flgs;
2377 tcfg.rss_result_mask = p->rss->result_mask;
2378
2379 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2691d51d 2380
523224a3
DK		 2381 /* Enable the function in the FW */
2382 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2383 storm_memset_func_en(bp, p->func_id, 1);
2691d51d 2384
523224a3
DK		 2385 /* statistics */
2386 if (p->func_flgs & FUNC_FLG_STATS) {
2387 struct stats_indication_flags stats_flags = {0};
2388 stats_flags.collect_eth = 1;
2691d51d 2389
523224a3
DK		 2390 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2391 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2392
523224a3
DK		 2393 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2394 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2395
523224a3
DK		 2396 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2397 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2398
523224a3
DK		 2399 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2400 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d
EG		 2401 }
2402
523224a3
DK		 2403 /* spq */
2404 if (p->func_flgs & FUNC_FLG_SPQ) {
2405 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2406 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2407 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2408 }
2691d51d
EG		 2409}
2410
523224a3
DK		 2411static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2412 struct bnx2x_fastpath *fp)
28912902 2413{
523224a3 2414 u16 flags = 0;
28912902 2415
523224a3
DK		 2416 /* calculate queue flags */
2417 flags |= QUEUE_FLG_CACHE_ALIGN;
2418 flags |= QUEUE_FLG_HC;
0793f83f 2419 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
28912902 2420
523224a3
DK		 2421 flags |= QUEUE_FLG_VLAN;
2422 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
523224a3
DK		 2423
2424 if (!fp->disable_tpa)
2425 flags |= QUEUE_FLG_TPA;
2426
ec6ba945
VZ		 2427 flags = stat_counter_valid(bp, fp) ?
2428 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
523224a3
DK		 2429
2430 return flags;
2431}
2432
2433static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2434 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2435 struct bnx2x_rxq_init_params *rxq_init)
2436{
2437 u16 max_sge = 0;
2438 u16 sge_sz = 0;
2439 u16 tpa_agg_size = 0;
2440
2441 /* calculate queue flags */
2442 u16 flags = bnx2x_get_cl_flags(bp, fp);
2443
2444 if (!fp->disable_tpa) {
2445 pause->sge_th_hi = 250;
2446 pause->sge_th_lo = 150;
2447 tpa_agg_size = min_t(u32,
2448 (min_t(u32, 8, MAX_SKB_FRAGS) *
2449 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2450 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2451 SGE_PAGE_SHIFT;
2452 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2453 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2454 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2455 0xffff);
2456 }
2457
2458 /* pause - not for e1 */
2459 if (!CHIP_IS_E1(bp)) {
2460 pause->bd_th_hi = 350;
2461 pause->bd_th_lo = 250;
2462 pause->rcq_th_hi = 350;
2463 pause->rcq_th_lo = 250;
2464 pause->sge_th_hi = 0;
2465 pause->sge_th_lo = 0;
2466 pause->pri_map = 1;
2467 }
2468
2469 /* rxq setup */
2470 rxq_init->flags = flags;
2471 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2472 rxq_init->dscr_map = fp->rx_desc_mapping;
2473 rxq_init->sge_map = fp->rx_sge_mapping;
2474 rxq_init->rcq_map = fp->rx_comp_mapping;
2475 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91
VZ		 2476
2477 /* Always use mini-jumbo MTU for FCoE L2 ring */
2478 if (IS_FCOE_FP(fp))
2479 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2480 else
2481 rxq_init->mtu = bp->dev->mtu;
2482
2483 rxq_init->buf_sz = fp->rx_buf_size;
523224a3
DK		 2484 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2485 rxq_init->cl_id = fp->cl_id;
2486 rxq_init->spcl_id = fp->cl_id;
2487 rxq_init->stat_id = fp->cl_id;
2488 rxq_init->tpa_agg_sz = tpa_agg_size;
2489 rxq_init->sge_buf_sz = sge_sz;
2490 rxq_init->max_sges_pkt = max_sge;
2491 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2492 rxq_init->fw_sb_id = fp->fw_sb_id;
2493
ec6ba945
VZ		 2494 if (IS_FCOE_FP(fp))
2495 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2496 else
2497 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
523224a3
DK		 2498
2499 rxq_init->cid = HW_CID(bp, fp->cid);
2500
2501 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2502}
2503
2504static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2505 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2506{
2507 u16 flags = bnx2x_get_cl_flags(bp, fp);
2508
2509 txq_init->flags = flags;
2510 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2511 txq_init->dscr_map = fp->tx_desc_mapping;
2512 txq_init->stat_id = fp->cl_id;
2513 txq_init->cid = HW_CID(bp, fp->cid);
2514 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2515 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2516 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945
VZ		 2517
2518 if (IS_FCOE_FP(fp)) {
2519 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2520 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2521 }
2522
523224a3
DK		 2523 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2524}
2525
8d96286a 2526static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2527{
2528 struct bnx2x_func_init_params func_init = {0};
2529 struct bnx2x_rss_params rss = {0};
2530 struct event_ring_data eq_data = { {0} };
2531 u16 flags;
2532
2533 /* pf specific setups */
2534 if (!CHIP_IS_E1(bp))
fb3bff17 2535 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
523224a3 2536
f2e0899f
DK		 2537 if (CHIP_IS_E2(bp)) {
2538 /* reset IGU PF statistics: MSIX + ATTN */
2539 /* PF */
2540 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2541 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2542 (CHIP_MODE_IS_4_PORT(bp) ?
2543 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2544 /* ATTN */
2545 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2546 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2547 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2548 (CHIP_MODE_IS_4_PORT(bp) ?
2549 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2550 }
2551
523224a3
DK		 2552 /* function setup flags */
2553 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2554
f2e0899f
DK		 2555 if (CHIP_IS_E1x(bp))
2556 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2557 else
2558 flags |= FUNC_FLG_TPA;
523224a3 2559
030f3356
DK		 2560 /* function setup */
2561
523224a3
DK		 2562 /**
2563 * Although RSS is meaningless when there is a single HW queue we
2564 * still need it enabled in order to have HW Rx hash generated.
523224a3 2565 */
030f3356
DK		 2566 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2567 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2568 rss.mode = bp->multi_mode;
2569 rss.result_mask = MULTI_MASK;
2570 func_init.rss = &rss;
523224a3
DK		 2571
2572 func_init.func_flgs = flags;
2573 func_init.pf_id = BP_FUNC(bp);
2574 func_init.func_id = BP_FUNC(bp);
2575 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2576 func_init.spq_map = bp->spq_mapping;
2577 func_init.spq_prod = bp->spq_prod_idx;
2578
2579 bnx2x_func_init(bp, &func_init);
2580
2581 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2582
2583 /*
2584 Congestion management values depend on the link rate
2585 There is no active link so initial link rate is set to 10 Gbps.
2586 When the link comes up The congestion management values are
2587 re-calculated according to the actual link rate.
2588 */
2589 bp->link_vars.line_speed = SPEED_10000;
2590 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2591
2592 /* Only the PMF sets the HW */
2593 if (bp->port.pmf)
2594 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2595
2596 /* no rx until link is up */
2597 bp->rx_mode = BNX2X_RX_MODE_NONE;
2598 bnx2x_set_storm_rx_mode(bp);
2599
2600 /* init Event Queue */
2601 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2602 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2603 eq_data.producer = bp->eq_prod;
2604 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2605 eq_data.sb_id = DEF_SB_ID;
2606 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2607}
2608
2609
2610static void bnx2x_e1h_disable(struct bnx2x *bp)
2611{
2612 int port = BP_PORT(bp);
2613
2614 netif_tx_disable(bp->dev);
2615
2616 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2617
2618 netif_carrier_off(bp->dev);
2619}
2620
2621static void bnx2x_e1h_enable(struct bnx2x *bp)
2622{
2623 int port = BP_PORT(bp);
2624
2625 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2626
2627 /* Tx queue should be only reenabled */
2628 netif_tx_wake_all_queues(bp->dev);
2629
2630 /*
2631 * Should not call netif_carrier_on since it will be called if the link
2632 * is up when checking for link state
2633 */
2634}
2635
0793f83f
DK		 2636/* called due to MCP event (on pmf):
2637 * reread new bandwidth configuration
2638 * configure FW
2639 * notify others function about the change
2640 */
2641static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2642{
2643 if (bp->link_vars.link_up) {
2644 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2645 bnx2x_link_sync_notify(bp);
2646 }
2647 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2648}
2649
2650static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2651{
2652 bnx2x_config_mf_bw(bp);
2653 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2654}
2655
523224a3
DK		 2656static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2657{
2658 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2659
2660 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2661
2662 /*
2663 * This is the only place besides the function initialization
2664 * where the bp->flags can change so it is done without any
2665 * locks
2666 */
f2e0899f 2667 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2668 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2669 bp->flags |= MF_FUNC_DIS;
2670
2671 bnx2x_e1h_disable(bp);
2672 } else {
2673 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2674 bp->flags &= ~MF_FUNC_DIS;
2675
2676 bnx2x_e1h_enable(bp);
2677 }
2678 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2679 }
2680 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2681 bnx2x_config_mf_bw(bp);
523224a3
DK		 2682 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2683 }
2684
2685 /* Report results to MCP */
2686 if (dcc_event)
2687 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2688 else
2689 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2690}
2691
2692/* must be called under the spq lock */
2693static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2694{
2695 struct eth_spe *next_spe = bp->spq_prod_bd;
2696
2697 if (bp->spq_prod_bd == bp->spq_last_bd) {
2698 bp->spq_prod_bd = bp->spq;
2699 bp->spq_prod_idx = 0;
2700 DP(NETIF_MSG_TIMER, "end of spq\n");
2701 } else {
2702 bp->spq_prod_bd++;
2703 bp->spq_prod_idx++;
2704 }
2705 return next_spe;
2706}
2707
2708/* must be called under the spq lock */
28912902
MC		 2709static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2710{
2711 int func = BP_FUNC(bp);
2712
2713 /* Make sure that BD data is updated before writing the producer */
2714 wmb();
2715
523224a3 2716 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2717 bp->spq_prod_idx);
28912902
MC		 2718 mmiowb();
2719}
2720
a2fbb9ea 2721/* the slow path queue is odd since completions arrive on the fastpath ring */
9f6c9258 2722int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
f85582f8 2723 u32 data_hi, u32 data_lo, int common)
a2fbb9ea 2724{
28912902 2725 struct eth_spe *spe;
523224a3 2726 u16 type;
a2fbb9ea 2727
a2fbb9ea
ET		 2728#ifdef BNX2X_STOP_ON_ERROR
2729 if (unlikely(bp->panic))
2730 return -EIO;
2731#endif
2732
34f80b04 2733 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 2734
8fe23fbd 2735 if (!atomic_read(&bp->spq_left)) {
a2fbb9ea 2736 BNX2X_ERR("BUG! SPQ ring full!\n");
34f80b04 2737 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2738 bnx2x_panic();
2739 return -EBUSY;
2740 }
f1410647 2741
28912902
MC		 2742 spe = bnx2x_sp_get_next(bp);
2743
a2fbb9ea 2744 /* CID needs port number to be encoded int it */
28912902 2745 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 2746 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2747 HW_CID(bp, cid));
523224a3 2748
a2fbb9ea 2749 if (common)
523224a3
DK		 2750 /* Common ramrods:
2751 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2752 * TRAFFIC_STOP, TRAFFIC_START
2753 */
2754 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2755 & SPE_HDR_CONN_TYPE;
2756 else
2757 /* ETH ramrods: SETUP, HALT */
2758 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2759 & SPE_HDR_CONN_TYPE;
a2fbb9ea 2760
523224a3
DK		 2761 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2762 SPE_HDR_FUNCTION_ID);
a2fbb9ea 2763
523224a3
DK		 2764 spe->hdr.type = cpu_to_le16(type);
2765
2766 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2767 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2768
2769 /* stats ramrod has it's own slot on the spq */
2770 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY)
2771 /* It's ok if the actual decrement is issued towards the memory
2772 * somewhere between the spin_lock and spin_unlock. Thus no
2773 * more explict memory barrier is needed.
2774 */
8fe23fbd 2775 atomic_dec(&bp->spq_left);
a2fbb9ea 2776
cdaa7cb8 2777 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3
DK		 2778 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2779 "type(0x%x) left %x\n",
cdaa7cb8
VZ		 2780 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2781 (u32)(U64_LO(bp->spq_mapping) +
2782 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
8fe23fbd 2783 HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));
cdaa7cb8 2784
28912902 2785 bnx2x_sp_prod_update(bp);
34f80b04 2786 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2787 return 0;
2788}
2789
2790/* acquire split MCP access lock register */
4a37fb66 2791static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 2792{
72fd0718 2793 u32 j, val;
34f80b04 2794 int rc = 0;
a2fbb9ea
ET		 2795
2796 might_sleep();
72fd0718 2797 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 2798 val = (1UL << 31);
2799 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2800 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2801 if (val & (1L << 31))
2802 break;
2803
2804 msleep(5);
2805 }
a2fbb9ea 2806 if (!(val & (1L << 31))) {
19680c48 2807 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 2808 rc = -EBUSY;
2809 }
2810
2811 return rc;
2812}
2813
4a37fb66
YG		 2814/* release split MCP access lock register */
2815static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 2816{
72fd0718 2817 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 2818}
2819
523224a3
DK		 2820#define BNX2X_DEF_SB_ATT_IDX 0x0001
2821#define BNX2X_DEF_SB_IDX 0x0002
2822
a2fbb9ea
ET		 2823static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2824{
523224a3 2825 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 2826 u16 rc = 0;
2827
2828 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 2829 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2830 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 2831 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 2832 }
523224a3
DK		 2833
2834 if (bp->def_idx != def_sb->sp_sb.running_index) {
2835 bp->def_idx = def_sb->sp_sb.running_index;
2836 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 2837 }
523224a3
DK		 2838
2839 /* Do not reorder: indecies reading should complete before handling */
2840 barrier();
a2fbb9ea
ET		 2841 return rc;
2842}
2843
2844/*
2845 * slow path service functions
2846 */
2847
2848static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2849{
34f80b04 2850 int port = BP_PORT(bp);
a2fbb9ea
ET		 2851 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2852 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 2853 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2854 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 2855 u32 aeu_mask;
87942b46 2856 u32 nig_mask = 0;
f2e0899f 2857 u32 reg_addr;
a2fbb9ea 2858
a2fbb9ea
ET		 2859 if (bp->attn_state & asserted)
2860 BNX2X_ERR("IGU ERROR\n");
2861
3fcaf2e5
EG		 2862 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2863 aeu_mask = REG_RD(bp, aeu_addr);
2864
a2fbb9ea 2865 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 2866 aeu_mask, asserted);
72fd0718 2867 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 2868 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 2869
3fcaf2e5
EG		 2870 REG_WR(bp, aeu_addr, aeu_mask);
2871 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 2872
3fcaf2e5 2873 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 2874 bp->attn_state |= asserted;
3fcaf2e5 2875 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 2876
2877 if (asserted & ATTN_HARD_WIRED_MASK) {
2878 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 2879
a5e9a7cf
EG		 2880 bnx2x_acquire_phy_lock(bp);
2881
877e9aa4 2882 /* save nig interrupt mask */
87942b46 2883 nig_mask = REG_RD(bp, nig_int_mask_addr);
877e9aa4 2884 REG_WR(bp, nig_int_mask_addr, 0);
a2fbb9ea 2885
c18487ee 2886 bnx2x_link_attn(bp);
a2fbb9ea
ET		 2887
2888 /* handle unicore attn? */
2889 }
2890 if (asserted & ATTN_SW_TIMER_4_FUNC)
2891 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2892
2893 if (asserted & GPIO_2_FUNC)
2894 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2895
2896 if (asserted & GPIO_3_FUNC)
2897 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2898
2899 if (asserted & GPIO_4_FUNC)
2900 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2901
2902 if (port == 0) {
2903 if (asserted & ATTN_GENERAL_ATTN_1) {
2904 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2905 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2906 }
2907 if (asserted & ATTN_GENERAL_ATTN_2) {
2908 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2909 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2910 }
2911 if (asserted & ATTN_GENERAL_ATTN_3) {
2912 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2913 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2914 }
2915 } else {
2916 if (asserted & ATTN_GENERAL_ATTN_4) {
2917 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2918 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2919 }
2920 if (asserted & ATTN_GENERAL_ATTN_5) {
2921 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2922 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2923 }
2924 if (asserted & ATTN_GENERAL_ATTN_6) {
2925 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2926 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2927 }
2928 }
2929
2930 } /* if hardwired */
2931
f2e0899f
DK		 2932 if (bp->common.int_block == INT_BLOCK_HC)
2933 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2934 COMMAND_REG_ATTN_BITS_SET);
2935 else
2936 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2937
2938 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2939 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2940 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 2941
2942 /* now set back the mask */
a5e9a7cf 2943 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 2944 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 2945 bnx2x_release_phy_lock(bp);
2946 }
a2fbb9ea
ET		 2947}
2948
fd4ef40d
EG		 2949static inline void bnx2x_fan_failure(struct bnx2x *bp)
2950{
2951 int port = BP_PORT(bp);
b7737c9b 2952 u32 ext_phy_config;
fd4ef40d 2953 /* mark the failure */
b7737c9b
YR		 2954 ext_phy_config =
2955 SHMEM_RD(bp,
2956 dev_info.port_hw_config[port].external_phy_config);
2957
2958 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2959 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 2960 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 2961 ext_phy_config);
fd4ef40d
EG		 2962
2963 /* log the failure */
cdaa7cb8
VZ		 2964 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2965 " the driver to shutdown the card to prevent permanent"
2966 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 2967}
ab6ad5a4 2968
877e9aa4 2969static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 2970{
34f80b04 2971 int port = BP_PORT(bp);
877e9aa4 2972 int reg_offset;
d90d96ba 2973 u32 val;
877e9aa4 2974
34f80b04
EG		 2975 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2976 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 2977
34f80b04 2978 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 2979
2980 val = REG_RD(bp, reg_offset);
2981 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2982 REG_WR(bp, reg_offset, val);
2983
2984 BNX2X_ERR("SPIO5 hw attention\n");
2985
fd4ef40d 2986 /* Fan failure attention */
d90d96ba 2987 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 2988 bnx2x_fan_failure(bp);
877e9aa4 2989 }
34f80b04 2990
589abe3a
EG		 2991 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2992 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2993 bnx2x_acquire_phy_lock(bp);
2994 bnx2x_handle_module_detect_int(&bp->link_params);
2995 bnx2x_release_phy_lock(bp);
2996 }
2997
34f80b04
EG		 2998 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2999
3000 val = REG_RD(bp, reg_offset);
3001 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3002 REG_WR(bp, reg_offset, val);
3003
3004 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3005 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3006 bnx2x_panic();
3007 }
877e9aa4
ET		 3008}
3009
3010static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3011{
3012 u32 val;
3013
0626b899 3014 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3015
3016 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3017 BNX2X_ERR("DB hw attention 0x%x\n", val);
3018 /* DORQ discard attention */
3019 if (val & 0x2)
3020 BNX2X_ERR("FATAL error from DORQ\n");
3021 }
34f80b04
EG		 3022
3023 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3024
3025 int port = BP_PORT(bp);
3026 int reg_offset;
3027
3028 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3029 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3030
3031 val = REG_RD(bp, reg_offset);
3032 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3033 REG_WR(bp, reg_offset, val);
3034
3035 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3036 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3037 bnx2x_panic();
3038 }
877e9aa4
ET		 3039}
3040
3041static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3042{
3043 u32 val;
3044
3045 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3046
3047 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3048 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3049 /* CFC error attention */
3050 if (val & 0x2)
3051 BNX2X_ERR("FATAL error from CFC\n");
3052 }
3053
3054 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3055
3056 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3057 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3058 /* RQ_USDMDP_FIFO_OVERFLOW */
3059 if (val & 0x18000)
3060 BNX2X_ERR("FATAL error from PXP\n");
f2e0899f
DK		 3061 if (CHIP_IS_E2(bp)) {
3062 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3063 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3064 }
877e9aa4 3065 }
34f80b04
EG		 3066
3067 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3068
3069 int port = BP_PORT(bp);
3070 int reg_offset;
3071
3072 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3073 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3074
3075 val = REG_RD(bp, reg_offset);
3076 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3077 REG_WR(bp, reg_offset, val);
3078
3079 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3080 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3081 bnx2x_panic();
3082 }
877e9aa4
ET		 3083}
3084
3085static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3086{
34f80b04
EG		 3087 u32 val;
3088
877e9aa4
ET		 3089 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3090
34f80b04
EG		 3091 if (attn & BNX2X_PMF_LINK_ASSERT) {
3092 int func = BP_FUNC(bp);
3093
3094 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3095 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3096 func_mf_config[BP_ABS_FUNC(bp)].config);
3097 val = SHMEM_RD(bp,
3098 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3099 if (val & DRV_STATUS_DCC_EVENT_MASK)
3100 bnx2x_dcc_event(bp,
3101 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3102
3103 if (val & DRV_STATUS_SET_MF_BW)
3104 bnx2x_set_mf_bw(bp);
3105
34f80b04 3106 bnx2x__link_status_update(bp);
2691d51d 3107 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3108 bnx2x_pmf_update(bp);
3109
e4901dde 3110 if (bp->port.pmf &&
785b9b1a
SR		 3111 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3112 bp->dcbx_enabled > 0)
e4901dde
VZ		 3113 /* start dcbx state machine */
3114 bnx2x_dcbx_set_params(bp,
3115 BNX2X_DCBX_STATE_NEG_RECEIVED);
34f80b04 3116 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3117
3118 BNX2X_ERR("MC assert!\n");
3119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3121 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3122 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3123 bnx2x_panic();
3124
3125 } else if (attn & BNX2X_MCP_ASSERT) {
3126
3127 BNX2X_ERR("MCP assert!\n");
3128 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3129 bnx2x_fw_dump(bp);
877e9aa4
ET		 3130
3131 } else
3132 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3133 }
3134
3135 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3136 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3137 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3138 val = CHIP_IS_E1(bp) ? 0 :
3139 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3140 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3141 }
3142 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3143 val = CHIP_IS_E1(bp) ? 0 :
3144 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3145 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3146 }
877e9aa4 3147 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3148 }
3149}
3150
72fd0718
VZ		 3151#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3152#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3153#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3154#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3155#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
f85582f8 3156
72fd0718
VZ		 3157/*
3158 * should be run under rtnl lock
3159 */
3160static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3161{
3162 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3163 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3164 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3165 barrier();
3166 mmiowb();
3167}
3168
3169/*
3170 * should be run under rtnl lock
3171 */
3172static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3173{
3174 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3175 val |= (1 << 16);
3176 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3177 barrier();
3178 mmiowb();
3179}
3180
3181/*
3182 * should be run under rtnl lock
3183 */
9f6c9258 3184bool bnx2x_reset_is_done(struct bnx2x *bp)
72fd0718
VZ		 3185{
3186 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3187 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3188 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3189}
3190
3191/*
3192 * should be run under rtnl lock
3193 */
9f6c9258 3194inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3195{
3196 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3197
3198 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3199
3200 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3201 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3202 barrier();
3203 mmiowb();
3204}
3205
3206/*
3207 * should be run under rtnl lock
3208 */
9f6c9258 3209u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3210{
3211 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3212
3213 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3214
3215 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3216 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3217 barrier();
3218 mmiowb();
3219
3220 return val1;
3221}
3222
3223/*
3224 * should be run under rtnl lock
3225 */
3226static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3227{
3228 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3229}
3230
3231static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3232{
3233 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3234 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3235}
3236
3237static inline void _print_next_block(int idx, const char *blk)
3238{
3239 if (idx)
3240 pr_cont(", ");
3241 pr_cont("%s", blk);
3242}
3243
3244static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3245{
3246 int i = 0;
3247 u32 cur_bit = 0;
3248 for (i = 0; sig; i++) {
3249 cur_bit = ((u32)0x1 << i);
3250 if (sig & cur_bit) {
3251 switch (cur_bit) {
3252 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3253 _print_next_block(par_num++, "BRB");
3254 break;
3255 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3256 _print_next_block(par_num++, "PARSER");
3257 break;
3258 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3259 _print_next_block(par_num++, "TSDM");
3260 break;
3261 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3262 _print_next_block(par_num++, "SEARCHER");
3263 break;
3264 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3265 _print_next_block(par_num++, "TSEMI");
3266 break;
3267 }
3268
3269 /* Clear the bit */
3270 sig &= ~cur_bit;
3271 }
3272 }
3273
3274 return par_num;
3275}
3276
3277static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3278{
3279 int i = 0;
3280 u32 cur_bit = 0;
3281 for (i = 0; sig; i++) {
3282 cur_bit = ((u32)0x1 << i);
3283 if (sig & cur_bit) {
3284 switch (cur_bit) {
3285 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3286 _print_next_block(par_num++, "PBCLIENT");
3287 break;
3288 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3289 _print_next_block(par_num++, "QM");
3290 break;
3291 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3292 _print_next_block(par_num++, "XSDM");
3293 break;
3294 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3295 _print_next_block(par_num++, "XSEMI");
3296 break;
3297 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3298 _print_next_block(par_num++, "DOORBELLQ");
3299 break;
3300 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3301 _print_next_block(par_num++, "VAUX PCI CORE");
3302 break;
3303 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3304 _print_next_block(par_num++, "DEBUG");
3305 break;
3306 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3307 _print_next_block(par_num++, "USDM");
3308 break;
3309 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3310 _print_next_block(par_num++, "USEMI");
3311 break;
3312 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3313 _print_next_block(par_num++, "UPB");
3314 break;
3315 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3316 _print_next_block(par_num++, "CSDM");
3317 break;
3318 }
3319
3320 /* Clear the bit */
3321 sig &= ~cur_bit;
3322 }
3323 }
3324
3325 return par_num;
3326}
3327
3328static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3329{
3330 int i = 0;
3331 u32 cur_bit = 0;
3332 for (i = 0; sig; i++) {
3333 cur_bit = ((u32)0x1 << i);
3334 if (sig & cur_bit) {
3335 switch (cur_bit) {
3336 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3337 _print_next_block(par_num++, "CSEMI");
3338 break;
3339 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3340 _print_next_block(par_num++, "PXP");
3341 break;
3342 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3343 _print_next_block(par_num++,
3344 "PXPPCICLOCKCLIENT");
3345 break;
3346 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3347 _print_next_block(par_num++, "CFC");
3348 break;
3349 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3350 _print_next_block(par_num++, "CDU");
3351 break;
3352 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3353 _print_next_block(par_num++, "IGU");
3354 break;
3355 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3356 _print_next_block(par_num++, "MISC");
3357 break;
3358 }
3359
3360 /* Clear the bit */
3361 sig &= ~cur_bit;
3362 }
3363 }
3364
3365 return par_num;
3366}
3367
3368static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3369{
3370 int i = 0;
3371 u32 cur_bit = 0;
3372 for (i = 0; sig; i++) {
3373 cur_bit = ((u32)0x1 << i);
3374 if (sig & cur_bit) {
3375 switch (cur_bit) {
3376 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3377 _print_next_block(par_num++, "MCP ROM");
3378 break;
3379 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3380 _print_next_block(par_num++, "MCP UMP RX");
3381 break;
3382 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3383 _print_next_block(par_num++, "MCP UMP TX");
3384 break;
3385 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3386 _print_next_block(par_num++, "MCP SCPAD");
3387 break;
3388 }
3389
3390 /* Clear the bit */
3391 sig &= ~cur_bit;
3392 }
3393 }
3394
3395 return par_num;
3396}
3397
3398static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3399 u32 sig2, u32 sig3)
3400{
3401 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3402 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3403 int par_num = 0;
3404 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3405 "[0]:0x%08x [1]:0x%08x "
3406 "[2]:0x%08x [3]:0x%08x\n",
3407 sig0 & HW_PRTY_ASSERT_SET_0,
3408 sig1 & HW_PRTY_ASSERT_SET_1,
3409 sig2 & HW_PRTY_ASSERT_SET_2,
3410 sig3 & HW_PRTY_ASSERT_SET_3);
3411 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3412 bp->dev->name);
3413 par_num = bnx2x_print_blocks_with_parity0(
3414 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3415 par_num = bnx2x_print_blocks_with_parity1(
3416 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3417 par_num = bnx2x_print_blocks_with_parity2(
3418 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3419 par_num = bnx2x_print_blocks_with_parity3(
3420 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3421 printk("\n");
3422 return true;
3423 } else
3424 return false;
3425}
3426
9f6c9258 3427bool bnx2x_chk_parity_attn(struct bnx2x *bp)
877e9aa4 3428{
a2fbb9ea 3429 struct attn_route attn;
72fd0718
VZ		 3430 int port = BP_PORT(bp);
3431
3432 attn.sig[0] = REG_RD(bp,
3433 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3434 port*4);
3435 attn.sig[1] = REG_RD(bp,
3436 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3437 port*4);
3438 attn.sig[2] = REG_RD(bp,
3439 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3440 port*4);
3441 attn.sig[3] = REG_RD(bp,
3442 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3443 port*4);
3444
3445 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3446 attn.sig[3]);
3447}
3448
f2e0899f
DK		 3449
3450static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3451{
3452 u32 val;
3453 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3454
3455 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3456 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3457 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3458 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3459 "ADDRESS_ERROR\n");
3460 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3461 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3462 "INCORRECT_RCV_BEHAVIOR\n");
3463 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3464 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3465 "WAS_ERROR_ATTN\n");
3466 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3467 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3468 "VF_LENGTH_VIOLATION_ATTN\n");
3469 if (val &
3470 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3471 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3472 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3473 if (val &
3474 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3475 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3476 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3477 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3478 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3479 "TCPL_ERROR_ATTN\n");
3480 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3481 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3482 "TCPL_IN_TWO_RCBS_ATTN\n");
3483 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3484 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3485 "CSSNOOP_FIFO_OVERFLOW\n");
3486 }
3487 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3488 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3489 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3490 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3491 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3492 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3493 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3494 "_ATC_TCPL_TO_NOT_PEND\n");
3495 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3496 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3497 "ATC_GPA_MULTIPLE_HITS\n");
3498 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3499 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3500 "ATC_RCPL_TO_EMPTY_CNT\n");
3501 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3502 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3503 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3504 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3505 "ATC_IREQ_LESS_THAN_STU\n");
3506 }
3507
3508 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3509 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3510 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3511 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3512 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3513 }
3514
3515}
3516
72fd0718
VZ		 3517static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3518{
3519 struct attn_route attn, *group_mask;
34f80b04 3520 int port = BP_PORT(bp);
877e9aa4 3521 int index;
a2fbb9ea
ET		 3522 u32 reg_addr;
3523 u32 val;
3fcaf2e5 3524 u32 aeu_mask;
a2fbb9ea
ET		 3525
3526 /* need to take HW lock because MCP or other port might also
3527 try to handle this event */
4a37fb66 3528 bnx2x_acquire_alr(bp);
a2fbb9ea 3529
4a33bc03 3530 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
72fd0718
VZ		 3531 bp->recovery_state = BNX2X_RECOVERY_INIT;
3532 bnx2x_set_reset_in_progress(bp);
3533 schedule_delayed_work(&bp->reset_task, 0);
3534 /* Disable HW interrupts */
3535 bnx2x_int_disable(bp);
3536 bnx2x_release_alr(bp);
3537 /* In case of parity errors don't handle attentions so that
3538 * other function would "see" parity errors.
3539 */
3540 return;
3541 }
3542
a2fbb9ea
ET		 3543 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3544 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3545 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3546 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
f2e0899f
DK		 3547 if (CHIP_IS_E2(bp))
3548 attn.sig[4] =
3549 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3550 else
3551 attn.sig[4] = 0;
3552
3553 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3554 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 3555
3556 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3557 if (deasserted & (1 << index)) {
72fd0718 3558 group_mask = &bp->attn_group[index];
a2fbb9ea 3559
f2e0899f
DK		 3560 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3561 "%08x %08x %08x\n",
3562 index,
3563 group_mask->sig[0], group_mask->sig[1],
3564 group_mask->sig[2], group_mask->sig[3],
3565 group_mask->sig[4]);
a2fbb9ea 3566
f2e0899f
DK		 3567 bnx2x_attn_int_deasserted4(bp,
3568 attn.sig[4] & group_mask->sig[4]);
877e9aa4 3569 bnx2x_attn_int_deasserted3(bp,
72fd0718 3570 attn.sig[3] & group_mask->sig[3]);
877e9aa4 3571 bnx2x_attn_int_deasserted1(bp,
72fd0718 3572 attn.sig[1] & group_mask->sig[1]);
877e9aa4 3573 bnx2x_attn_int_deasserted2(bp,
72fd0718 3574 attn.sig[2] & group_mask->sig[2]);
877e9aa4 3575 bnx2x_attn_int_deasserted0(bp,
72fd0718 3576 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 3577 }
3578 }
3579
4a37fb66 3580 bnx2x_release_alr(bp);
a2fbb9ea 3581
f2e0899f
DK		 3582 if (bp->common.int_block == INT_BLOCK_HC)
3583 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3584 COMMAND_REG_ATTN_BITS_CLR);
3585 else
3586 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 3587
3588 val = ~deasserted;
f2e0899f
DK		 3589 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3590 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 3591 REG_WR(bp, reg_addr, val);
a2fbb9ea 3592
a2fbb9ea 3593 if (~bp->attn_state & deasserted)
3fcaf2e5 3594 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 3595
3596 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3597 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3598
3fcaf2e5
EG		 3599 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3600 aeu_mask = REG_RD(bp, reg_addr);
3601
3602 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3603 aeu_mask, deasserted);
72fd0718 3604 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 3605 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3606
3fcaf2e5
EG		 3607 REG_WR(bp, reg_addr, aeu_mask);
3608 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 3609
3610 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3611 bp->attn_state &= ~deasserted;
3612 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3613}
3614
3615static void bnx2x_attn_int(struct bnx2x *bp)
3616{
3617 /* read local copy of bits */
68d59484
EG		 3618 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3619 attn_bits);
3620 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3621 attn_bits_ack);
a2fbb9ea
ET		 3622 u32 attn_state = bp->attn_state;
3623
3624 /* look for changed bits */
3625 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3626 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3627
3628 DP(NETIF_MSG_HW,
3629 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3630 attn_bits, attn_ack, asserted, deasserted);
3631
3632 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 3633 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 3634
3635 /* handle bits that were raised */
3636 if (asserted)
3637 bnx2x_attn_int_asserted(bp, asserted);
3638
3639 if (deasserted)
3640 bnx2x_attn_int_deasserted(bp, deasserted);
3641}
3642
523224a3
DK		 3643static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3644{
3645 /* No memory barriers */
3646 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3647 mmiowb(); /* keep prod updates ordered */
3648}
3649
3650#ifdef BCM_CNIC
3651static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3652 union event_ring_elem *elem)
3653{
3654 if (!bp->cnic_eth_dev.starting_cid ||
3655 cid < bp->cnic_eth_dev.starting_cid)
3656 return 1;
3657
3658 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3659
3660 if (unlikely(elem->message.data.cfc_del_event.error)) {
3661 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3662 cid);
3663 bnx2x_panic_dump(bp);
3664 }
3665 bnx2x_cnic_cfc_comp(bp, cid);
3666 return 0;
3667}
3668#endif
3669
3670static void bnx2x_eq_int(struct bnx2x *bp)
3671{
3672 u16 hw_cons, sw_cons, sw_prod;
3673 union event_ring_elem *elem;
3674 u32 cid;
3675 u8 opcode;
3676 int spqe_cnt = 0;
3677
3678 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3679
3680 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3681 * when we get the the next-page we nned to adjust so the loop
3682 * condition below will be met. The next element is the size of a
3683 * regular element and hence incrementing by 1
3684 */
3685 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3686 hw_cons++;
3687
3688 /* This function may never run in parralel with itself for a
3689 * specific bp, thus there is no need in "paired" read memory
3690 * barrier here.
3691 */
3692 sw_cons = bp->eq_cons;
3693 sw_prod = bp->eq_prod;
3694
3695 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->spq_left %u\n",
8fe23fbd 3696 hw_cons, sw_cons, atomic_read(&bp->spq_left));
523224a3
DK		 3697
3698 for (; sw_cons != hw_cons;
3699 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3700
3701
3702 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3703
3704 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3705 opcode = elem->message.opcode;
3706
3707
3708 /* handle eq element */
3709 switch (opcode) {
3710 case EVENT_RING_OPCODE_STAT_QUERY:
3711 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3712 /* nothing to do with stats comp */
3713 continue;
3714
3715 case EVENT_RING_OPCODE_CFC_DEL:
3716 /* handle according to cid range */
3717 /*
3718 * we may want to verify here that the bp state is
3719 * HALTING
3720 */
3721 DP(NETIF_MSG_IFDOWN,
3722 "got delete ramrod for MULTI[%d]\n", cid);
3723#ifdef BCM_CNIC
3724 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3725 goto next_spqe;
ec6ba945
VZ		 3726 if (cid == BNX2X_FCOE_ETH_CID)
3727 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3728 else
523224a3 3729#endif
ec6ba945 3730 bnx2x_fp(bp, cid, state) =
523224a3
DK		 3731 BNX2X_FP_STATE_CLOSED;
3732
3733 goto next_spqe;
e4901dde
VZ		 3734
3735 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3736 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3737 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3738 goto next_spqe;
3739 case EVENT_RING_OPCODE_START_TRAFFIC:
3740 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3741 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3742 goto next_spqe;
523224a3
DK		 3743 }
3744
3745 switch (opcode | bp->state) {
3746 case (EVENT_RING_OPCODE_FUNCTION_START |
3747 BNX2X_STATE_OPENING_WAIT4_PORT):
3748 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3749 bp->state = BNX2X_STATE_FUNC_STARTED;
3750 break;
3751
3752 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3753 BNX2X_STATE_CLOSING_WAIT4_HALT):
3754 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3755 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3756 break;
3757
3758 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3759 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3760 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3761 bp->set_mac_pending = 0;
3762 break;
3763
3764 case (EVENT_RING_OPCODE_SET_MAC |
3765 BNX2X_STATE_CLOSING_WAIT4_HALT):
3766 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3767 bp->set_mac_pending = 0;
3768 break;
3769 default:
3770 /* unknown event log error and continue */
3771 BNX2X_ERR("Unknown EQ event %d\n",
3772 elem->message.opcode);
3773 }
3774next_spqe:
3775 spqe_cnt++;
3776 } /* for */
3777
8fe23fbd
DK		 3778 smp_mb__before_atomic_inc();
3779 atomic_add(spqe_cnt, &bp->spq_left);
523224a3
DK		 3780
3781 bp->eq_cons = sw_cons;
3782 bp->eq_prod = sw_prod;
3783 /* Make sure that above mem writes were issued towards the memory */
3784 smp_wmb();
3785
3786 /* update producer */
3787 bnx2x_update_eq_prod(bp, bp->eq_prod);
3788}
3789
a2fbb9ea
ET		 3790static void bnx2x_sp_task(struct work_struct *work)
3791{
1cf167f2 3792 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 3793 u16 status;
3794
3795 /* Return here if interrupt is disabled */
3796 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3797 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3798 return;
3799 }
3800
3801 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 3802/* if (status == 0) */
3803/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 3804
cdaa7cb8 3805 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 3806
877e9aa4 3807 /* HW attentions */
523224a3 3808 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 3809 bnx2x_attn_int(bp);
523224a3 3810 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 3811 }
3812
523224a3
DK		 3813 /* SP events: STAT_QUERY and others */
3814 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 3815#ifdef BCM_CNIC
3816 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 3817
ec6ba945
VZ		 3818 if ((!NO_FCOE(bp)) &&
3819 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3820 napi_schedule(&bnx2x_fcoe(bp, napi));
3821#endif
523224a3
DK		 3822 /* Handle EQ completions */
3823 bnx2x_eq_int(bp);
3824
3825 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3826 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3827
3828 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 3829 }
3830
3831 if (unlikely(status))
3832 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3833 status);
a2fbb9ea 3834
523224a3
DK		 3835 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3836 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 3837}
3838
9f6c9258 3839irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 3840{
3841 struct net_device *dev = dev_instance;
3842 struct bnx2x *bp = netdev_priv(dev);
3843
3844 /* Return here if interrupt is disabled */
3845 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3846 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3847 return IRQ_HANDLED;
3848 }
3849
523224a3
DK		 3850 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3851 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 3852
3853#ifdef BNX2X_STOP_ON_ERROR
3854 if (unlikely(bp->panic))
3855 return IRQ_HANDLED;
3856#endif
3857
993ac7b5
MC		 3858#ifdef BCM_CNIC
3859 {
3860 struct cnic_ops *c_ops;
3861
3862 rcu_read_lock();
3863 c_ops = rcu_dereference(bp->cnic_ops);
3864 if (c_ops)
3865 c_ops->cnic_handler(bp->cnic_data, NULL);
3866 rcu_read_unlock();
3867 }
3868#endif
1cf167f2 3869 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 3870
3871 return IRQ_HANDLED;
3872}
3873
3874/* end of slow path */
3875
a2fbb9ea
ET		 3876static void bnx2x_timer(unsigned long data)
3877{
3878 struct bnx2x *bp = (struct bnx2x *) data;
3879
3880 if (!netif_running(bp->dev))
3881 return;
3882
3883 if (atomic_read(&bp->intr_sem) != 0)
f1410647 3884 goto timer_restart;
a2fbb9ea
ET		 3885
3886 if (poll) {
3887 struct bnx2x_fastpath *fp = &bp->fp[0];
3888 int rc;
3889
7961f791 3890 bnx2x_tx_int(fp);
a2fbb9ea
ET		 3891 rc = bnx2x_rx_int(fp, 1000);
3892 }
3893
34f80b04 3894 if (!BP_NOMCP(bp)) {
f2e0899f 3895 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 3896 u32 drv_pulse;
3897 u32 mcp_pulse;
3898
3899 ++bp->fw_drv_pulse_wr_seq;
3900 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3901 /* TBD - add SYSTEM_TIME */
3902 drv_pulse = bp->fw_drv_pulse_wr_seq;
f2e0899f 3903 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
a2fbb9ea 3904
f2e0899f 3905 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 3906 MCP_PULSE_SEQ_MASK);
3907 /* The delta between driver pulse and mcp response
3908 * should be 1 (before mcp response) or 0 (after mcp response)
3909 */
3910 if ((drv_pulse != mcp_pulse) &&
3911 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3912 /* someone lost a heartbeat... */
3913 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3914 drv_pulse, mcp_pulse);
3915 }
3916 }
3917
f34d28ea 3918 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 3919 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 3920
f1410647 3921timer_restart:
a2fbb9ea
ET		 3922 mod_timer(&bp->timer, jiffies + bp->current_interval);
3923}
3924
3925/* end of Statistics */
3926
3927/* nic init */
3928
3929/*
3930 * nic init service functions
3931 */
3932
523224a3 3933static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 3934{
523224a3
DK		 3935 u32 i;
3936 if (!(len%4) && !(addr%4))
3937 for (i = 0; i < len; i += 4)
3938 REG_WR(bp, addr + i, fill);
3939 else
3940 for (i = 0; i < len; i++)
3941 REG_WR8(bp, addr + i, fill);
34f80b04 3942
34f80b04
EG		 3943}
3944
523224a3
DK		 3945/* helper: writes FP SP data to FW - data_size in dwords */
3946static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3947 int fw_sb_id,
3948 u32 *sb_data_p,
3949 u32 data_size)
34f80b04 3950{
a2fbb9ea 3951 int index;
523224a3
DK		 3952 for (index = 0; index < data_size; index++)
3953 REG_WR(bp, BAR_CSTRORM_INTMEM +
3954 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3955 sizeof(u32)*index,
3956 *(sb_data_p + index));
3957}
a2fbb9ea 3958
523224a3
DK		 3959static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3960{
3961 u32 *sb_data_p;
3962 u32 data_size = 0;
f2e0899f 3963 struct hc_status_block_data_e2 sb_data_e2;
523224a3 3964 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 3965
523224a3 3966 /* disable the function first */
f2e0899f
DK		 3967 if (CHIP_IS_E2(bp)) {
3968 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3969 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3970 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3971 sb_data_e2.common.p_func.vf_valid = false;
3972 sb_data_p = (u32 *)&sb_data_e2;
3973 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3974 } else {
3975 memset(&sb_data_e1x, 0,
3976 sizeof(struct hc_status_block_data_e1x));
3977 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3978 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3979 sb_data_e1x.common.p_func.vf_valid = false;
3980 sb_data_p = (u32 *)&sb_data_e1x;
3981 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3982 }
523224a3 3983 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 3984
523224a3
DK		 3985 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3986 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
3987 CSTORM_STATUS_BLOCK_SIZE);
3988 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3989 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
3990 CSTORM_SYNC_BLOCK_SIZE);
3991}
34f80b04 3992
523224a3
DK		 3993/* helper: writes SP SB data to FW */
3994static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
3995 struct hc_sp_status_block_data *sp_sb_data)
3996{
3997 int func = BP_FUNC(bp);
3998 int i;
3999 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4000 REG_WR(bp, BAR_CSTRORM_INTMEM +
4001 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4002 i*sizeof(u32),
4003 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4004}
4005
523224a3 4006static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4007{
4008 int func = BP_FUNC(bp);
523224a3
DK		 4009 struct hc_sp_status_block_data sp_sb_data;
4010 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4011
523224a3
DK		 4012 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4013 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4014 sp_sb_data.p_func.vf_valid = false;
4015
4016 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4017
4018 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4019 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4020 CSTORM_SP_STATUS_BLOCK_SIZE);
4021 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4022 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4023 CSTORM_SP_SYNC_BLOCK_SIZE);
4024
4025}
4026
4027
4028static inline
4029void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4030 int igu_sb_id, int igu_seg_id)
4031{
4032 hc_sm->igu_sb_id = igu_sb_id;
4033 hc_sm->igu_seg_id = igu_seg_id;
4034 hc_sm->timer_value = 0xFF;
4035 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4036}
4037
8d96286a 4038static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4039 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4040{
523224a3
DK		 4041 int igu_seg_id;
4042
f2e0899f 4043 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4044 struct hc_status_block_data_e1x sb_data_e1x;
4045 struct hc_status_block_sm *hc_sm_p;
4046 struct hc_index_data *hc_index_p;
4047 int data_size;
4048 u32 *sb_data_p;
4049
f2e0899f
DK		 4050 if (CHIP_INT_MODE_IS_BC(bp))
4051 igu_seg_id = HC_SEG_ACCESS_NORM;
4052 else
4053 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4054
4055 bnx2x_zero_fp_sb(bp, fw_sb_id);
4056
f2e0899f
DK		 4057 if (CHIP_IS_E2(bp)) {
4058 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4059 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4060 sb_data_e2.common.p_func.vf_id = vfid;
4061 sb_data_e2.common.p_func.vf_valid = vf_valid;
4062 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4063 sb_data_e2.common.same_igu_sb_1b = true;
4064 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4065 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4066 hc_sm_p = sb_data_e2.common.state_machine;
4067 hc_index_p = sb_data_e2.index_data;
4068 sb_data_p = (u32 *)&sb_data_e2;
4069 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4070 } else {
4071 memset(&sb_data_e1x, 0,
4072 sizeof(struct hc_status_block_data_e1x));
4073 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4074 sb_data_e1x.common.p_func.vf_id = 0xff;
4075 sb_data_e1x.common.p_func.vf_valid = false;
4076 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4077 sb_data_e1x.common.same_igu_sb_1b = true;
4078 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4079 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4080 hc_sm_p = sb_data_e1x.common.state_machine;
4081 hc_index_p = sb_data_e1x.index_data;
4082 sb_data_p = (u32 *)&sb_data_e1x;
4083 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4084 }
523224a3
DK		 4085
4086 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4087 igu_sb_id, igu_seg_id);
4088 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4089 igu_sb_id, igu_seg_id);
4090
4091 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4092
4093 /* write indecies to HW */
4094 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4095}
4096
4097static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4098 u8 sb_index, u8 disable, u16 usec)
4099{
4100 int port = BP_PORT(bp);
4101 u8 ticks = usec / BNX2X_BTR;
4102
4103 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4104
4105 disable = disable ? 1 : (usec ? 0 : 1);
4106 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4107}
4108
4109static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4110 u16 tx_usec, u16 rx_usec)
4111{
4112 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4113 false, rx_usec);
4114 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4115 false, tx_usec);
4116}
f2e0899f 4117
523224a3
DK		 4118static void bnx2x_init_def_sb(struct bnx2x *bp)
4119{
4120 struct host_sp_status_block *def_sb = bp->def_status_blk;
4121 dma_addr_t mapping = bp->def_status_blk_mapping;
4122 int igu_sp_sb_index;
4123 int igu_seg_id;
34f80b04
EG		 4124 int port = BP_PORT(bp);
4125 int func = BP_FUNC(bp);
523224a3 4126 int reg_offset;
a2fbb9ea 4127 u64 section;
523224a3
DK		 4128 int index;
4129 struct hc_sp_status_block_data sp_sb_data;
4130 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4131
f2e0899f
DK		 4132 if (CHIP_INT_MODE_IS_BC(bp)) {
4133 igu_sp_sb_index = DEF_SB_IGU_ID;
4134 igu_seg_id = HC_SEG_ACCESS_DEF;
4135 } else {
4136 igu_sp_sb_index = bp->igu_dsb_id;
4137 igu_seg_id = IGU_SEG_ACCESS_DEF;
4138 }
a2fbb9ea
ET		 4139
4140 /* ATTN */
523224a3 4141 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4142 atten_status_block);
523224a3 4143 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4144
49d66772
ET		 4145 bp->attn_state = 0;
4146
a2fbb9ea
ET		 4147 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4148 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4149 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4150 int sindex;
4151 /* take care of sig[0]..sig[4] */
4152 for (sindex = 0; sindex < 4; sindex++)
4153 bp->attn_group[index].sig[sindex] =
4154 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f
DK		 4155
4156 if (CHIP_IS_E2(bp))
4157 /*
4158 * enable5 is separate from the rest of the registers,
4159 * and therefore the address skip is 4
4160 * and not 16 between the different groups
4161 */
4162 bp->attn_group[index].sig[4] = REG_RD(bp,
4163 reg_offset + 0x10 + 0x4*index);
4164 else
4165 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4166 }
4167
f2e0899f
DK		 4168 if (bp->common.int_block == INT_BLOCK_HC) {
4169 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4170 HC_REG_ATTN_MSG0_ADDR_L);
4171
4172 REG_WR(bp, reg_offset, U64_LO(section));
4173 REG_WR(bp, reg_offset + 4, U64_HI(section));
4174 } else if (CHIP_IS_E2(bp)) {
4175 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4176 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4177 }
a2fbb9ea 4178
523224a3
DK		 4179 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4180 sp_sb);
a2fbb9ea 4181
523224a3 4182 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4183
523224a3
DK		 4184 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4185 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4186 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4187 sp_sb_data.igu_seg_id = igu_seg_id;
4188 sp_sb_data.p_func.pf_id = func;
f2e0899f 4189 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4190 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4191
523224a3 4192 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4193
bb2a0f7a 4194 bp->stats_pending = 0;
66e855f3 4195 bp->set_mac_pending = 0;
bb2a0f7a 4196
523224a3 4197 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4198}
4199
9f6c9258 4200void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4201{
a2fbb9ea
ET		 4202 int i;
4203
ec6ba945 4204 for_each_eth_queue(bp, i)
523224a3
DK		 4205 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4206 bp->rx_ticks, bp->tx_ticks);
a2fbb9ea
ET		 4207}
4208
a2fbb9ea
ET		 4209static void bnx2x_init_sp_ring(struct bnx2x *bp)
4210{
a2fbb9ea 4211 spin_lock_init(&bp->spq_lock);
8fe23fbd 4212 atomic_set(&bp->spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4213
a2fbb9ea 4214 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4215 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4216 bp->spq_prod_bd = bp->spq;
4217 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4218}
4219
523224a3 4220static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4221{
4222 int i;
523224a3
DK		 4223 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4224 union event_ring_elem *elem =
4225 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4226
523224a3
DK		 4227 elem->next_page.addr.hi =
4228 cpu_to_le32(U64_HI(bp->eq_mapping +
4229 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4230 elem->next_page.addr.lo =
4231 cpu_to_le32(U64_LO(bp->eq_mapping +
4232 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4233 }
523224a3
DK		 4234 bp->eq_cons = 0;
4235 bp->eq_prod = NUM_EQ_DESC;
4236 bp->eq_cons_sb = BNX2X_EQ_INDEX;
a2fbb9ea
ET		 4237}
4238
4239static void bnx2x_init_ind_table(struct bnx2x *bp)
4240{
26c8fa4d 4241 int func = BP_FUNC(bp);
a2fbb9ea
ET		 4242 int i;
4243
555f6c78 4244 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
a2fbb9ea
ET		 4245 return;
4246
555f6c78
EG		 4247 DP(NETIF_MSG_IFUP,
4248 "Initializing indirection table multi_mode %d\n", bp->multi_mode);
a2fbb9ea 4249 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
34f80b04 4250 REG_WR8(bp, BAR_TSTRORM_INTMEM +
26c8fa4d 4251 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
ec6ba945
VZ		 4252 bp->fp->cl_id + (i % (bp->num_queues -
4253 NONE_ETH_CONTEXT_USE)));
a2fbb9ea
ET		 4254}
4255
9f6c9258 4256void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
a2fbb9ea 4257{
34f80b04 4258 int mode = bp->rx_mode;
ec6ba945 4259 int port = BP_PORT(bp);
523224a3 4260 u16 cl_id;
ec6ba945 4261 u32 def_q_filters = 0;
523224a3 4262
581ce43d
EG		 4263 /* All but management unicast packets should pass to the host as well */
4264 u32 llh_mask =
4265 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4266 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4267 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4268 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
a2fbb9ea 4269
a2fbb9ea
ET		 4270 switch (mode) {
4271 case BNX2X_RX_MODE_NONE: /* no Rx */
ec6ba945
VZ		 4272 def_q_filters = BNX2X_ACCEPT_NONE;
4273#ifdef BCM_CNIC
4274 if (!NO_FCOE(bp)) {
4275 cl_id = bnx2x_fcoe(bp, cl_id);
4276 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4277 }
4278#endif
a2fbb9ea 4279 break;
356e2385 4280
a2fbb9ea 4281 case BNX2X_RX_MODE_NORMAL:
ec6ba945
VZ		 4282 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4283 BNX2X_ACCEPT_MULTICAST;
4284#ifdef BCM_CNIC
4285 cl_id = bnx2x_fcoe(bp, cl_id);
4286 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4287 BNX2X_ACCEPT_MULTICAST);
4288#endif
a2fbb9ea 4289 break;
356e2385 4290
a2fbb9ea 4291 case BNX2X_RX_MODE_ALLMULTI:
ec6ba945
VZ		 4292 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4293 BNX2X_ACCEPT_ALL_MULTICAST;
4294#ifdef BCM_CNIC
4295 cl_id = bnx2x_fcoe(bp, cl_id);
4296 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4297 BNX2X_ACCEPT_MULTICAST);
4298#endif
a2fbb9ea 4299 break;
356e2385 4300
a2fbb9ea 4301 case BNX2X_RX_MODE_PROMISC:
ec6ba945
VZ		 4302 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4303#ifdef BCM_CNIC
4304 cl_id = bnx2x_fcoe(bp, cl_id);
4305 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4306 BNX2X_ACCEPT_MULTICAST);
4307#endif
581ce43d
EG		 4308 /* pass management unicast packets as well */
4309 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
a2fbb9ea 4310 break;
356e2385 4311
a2fbb9ea 4312 default:
34f80b04
EG		 4313 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4314 break;
a2fbb9ea
ET		 4315 }
4316
ec6ba945
VZ		 4317 cl_id = BP_L_ID(bp);
4318 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4319
581ce43d 4320 REG_WR(bp,
ec6ba945
VZ		 4321 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4322 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
581ce43d 4323
523224a3
DK		 4324 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4325 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
ec6ba945
VZ		 4326 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4327 "unmatched_ucast 0x%x\n", mode,
523224a3
DK		 4328 bp->mac_filters.ucast_drop_all,
4329 bp->mac_filters.mcast_drop_all,
4330 bp->mac_filters.bcast_drop_all,
4331 bp->mac_filters.ucast_accept_all,
4332 bp->mac_filters.mcast_accept_all,
ec6ba945
VZ		 4333 bp->mac_filters.bcast_accept_all,
4334 bp->mac_filters.unmatched_unicast
523224a3 4335 );
a2fbb9ea 4336
523224a3 4337 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
a2fbb9ea
ET		 4338}
4339
471de716
EG		 4340static void bnx2x_init_internal_common(struct bnx2x *bp)
4341{
4342 int i;
4343
523224a3 4344 if (!CHIP_IS_E1(bp)) {
de832a55 4345
523224a3
DK		 4346 /* xstorm needs to know whether to add ovlan to packets or not,
4347 * in switch-independent we'll write 0 to here... */
34f80b04 4348 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4349 bp->mf_mode);
34f80b04 4350 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4351 bp->mf_mode);
34f80b04 4352 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4353 bp->mf_mode);
34f80b04 4354 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4355 bp->mf_mode);
34f80b04
EG		 4356 }
4357
0793f83f
DK		 4358 if (IS_MF_SI(bp))
4359 /*
4360 * In switch independent mode, the TSTORM needs to accept
4361 * packets that failed classification, since approximate match
4362 * mac addresses aren't written to NIG LLH
4363 */
4364 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4365 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4366
523224a3
DK		 4367 /* Zero this manually as its initialization is
4368 currently missing in the initTool */
4369 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 4370 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 4371 USTORM_AGG_DATA_OFFSET + i * 4, 0);
f2e0899f
DK		 4372 if (CHIP_IS_E2(bp)) {
4373 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4374 CHIP_INT_MODE_IS_BC(bp) ?
4375 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4376 }
523224a3 4377}
8a1c38d1 4378
523224a3
DK		 4379static void bnx2x_init_internal_port(struct bnx2x *bp)
4380{
4381 /* port */
e4901dde 4382 bnx2x_dcb_init_intmem_pfc(bp);
a2fbb9ea
ET		 4383}
4384
471de716
EG		 4385static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4386{
4387 switch (load_code) {
4388 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 4389 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 4390 bnx2x_init_internal_common(bp);
4391 /* no break */
4392
4393 case FW_MSG_CODE_DRV_LOAD_PORT:
4394 bnx2x_init_internal_port(bp);
4395 /* no break */
4396
4397 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 4398 /* internal memory per function is
4399 initialized inside bnx2x_pf_init */
471de716
EG		 4400 break;
4401
4402 default:
4403 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4404 break;
4405 }
4406}
4407
523224a3
DK		 4408static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4409{
4410 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4411
4412 fp->state = BNX2X_FP_STATE_CLOSED;
4413
4414 fp->index = fp->cid = fp_idx;
4415 fp->cl_id = BP_L_ID(bp) + fp_idx;
4416 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4417 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4418 /* qZone id equals to FW (per path) client id */
4419 fp->cl_qzone_id = fp->cl_id +
f2e0899f
DK		 4420 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4421 ETH_MAX_RX_CLIENTS_E1H);
523224a3 4422 /* init shortcut */
f2e0899f
DK		 4423 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4424 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
523224a3
DK		 4425 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4426 /* Setup SB indicies */
4427 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4428 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4429
4430 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4431 "cl_id %d fw_sb %d igu_sb %d\n",
4432 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4433 fp->igu_sb_id);
4434 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4435 fp->fw_sb_id, fp->igu_sb_id);
4436
4437 bnx2x_update_fpsb_idx(fp);
4438}
4439
9f6c9258 4440void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 4441{
4442 int i;
4443
ec6ba945 4444 for_each_eth_queue(bp, i)
523224a3 4445 bnx2x_init_fp_sb(bp, i);
37b091ba 4446#ifdef BCM_CNIC
ec6ba945
VZ		 4447 if (!NO_FCOE(bp))
4448 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 4449
4450 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4451 BNX2X_VF_ID_INVALID, false,
4452 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4453
37b091ba 4454#endif
a2fbb9ea 4455
16119785
EG		 4456 /* ensure status block indices were read */
4457 rmb();
4458
523224a3 4459 bnx2x_init_def_sb(bp);
5c862848 4460 bnx2x_update_dsb_idx(bp);
a2fbb9ea 4461 bnx2x_init_rx_rings(bp);
523224a3 4462 bnx2x_init_tx_rings(bp);
a2fbb9ea 4463 bnx2x_init_sp_ring(bp);
523224a3 4464 bnx2x_init_eq_ring(bp);
471de716 4465 bnx2x_init_internal(bp, load_code);
523224a3 4466 bnx2x_pf_init(bp);
a2fbb9ea 4467 bnx2x_init_ind_table(bp);
0ef00459
EG		 4468 bnx2x_stats_init(bp);
4469
4470 /* At this point, we are ready for interrupts */
4471 atomic_set(&bp->intr_sem, 0);
4472
4473 /* flush all before enabling interrupts */
4474 mb();
4475 mmiowb();
4476
615f8fd9 4477 bnx2x_int_enable(bp);
eb8da205
EG		 4478
4479 /* Check for SPIO5 */
4480 bnx2x_attn_int_deasserted0(bp,
4481 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4482 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 4483}
4484
4485/* end of nic init */
4486
4487/*
4488 * gzip service functions
4489 */
4490
4491static int bnx2x_gunzip_init(struct bnx2x *bp)
4492{
1a983142
FT		 4493 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4494 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 4495 if (bp->gunzip_buf == NULL)
4496 goto gunzip_nomem1;
4497
4498 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4499 if (bp->strm == NULL)
4500 goto gunzip_nomem2;
4501
4502 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4503 GFP_KERNEL);
4504 if (bp->strm->workspace == NULL)
4505 goto gunzip_nomem3;
4506
4507 return 0;
4508
4509gunzip_nomem3:
4510 kfree(bp->strm);
4511 bp->strm = NULL;
4512
4513gunzip_nomem2:
1a983142
FT		 4514 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4515 bp->gunzip_mapping);
a2fbb9ea
ET		 4516 bp->gunzip_buf = NULL;
4517
4518gunzip_nomem1:
cdaa7cb8
VZ		 4519 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4520 " un-compression\n");
a2fbb9ea
ET		 4521 return -ENOMEM;
4522}
4523
4524static void bnx2x_gunzip_end(struct bnx2x *bp)
4525{
4526 kfree(bp->strm->workspace);
a2fbb9ea
ET		 4527 kfree(bp->strm);
4528 bp->strm = NULL;
4529
4530 if (bp->gunzip_buf) {
1a983142
FT		 4531 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4532 bp->gunzip_mapping);
a2fbb9ea
ET		 4533 bp->gunzip_buf = NULL;
4534 }
4535}
4536
94a78b79 4537static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 4538{
4539 int n, rc;
4540
4541 /* check gzip header */
94a78b79
VZ		 4542 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4543 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 4544 return -EINVAL;
94a78b79 4545 }
a2fbb9ea
ET		 4546
4547 n = 10;
4548
34f80b04 4549#define FNAME 0x8
a2fbb9ea
ET		 4550
4551 if (zbuf[3] & FNAME)
4552 while ((zbuf[n++] != 0) && (n < len));
4553
94a78b79 4554 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 4555 bp->strm->avail_in = len - n;
4556 bp->strm->next_out = bp->gunzip_buf;
4557 bp->strm->avail_out = FW_BUF_SIZE;
4558
4559 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4560 if (rc != Z_OK)
4561 return rc;
4562
4563 rc = zlib_inflate(bp->strm, Z_FINISH);
4564 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 4565 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4566 bp->strm->msg);
a2fbb9ea
ET		 4567
4568 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4569 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 4570 netdev_err(bp->dev, "Firmware decompression error:"
4571 " gunzip_outlen (%d) not aligned\n",
4572 bp->gunzip_outlen);
a2fbb9ea
ET		 4573 bp->gunzip_outlen >>= 2;
4574
4575 zlib_inflateEnd(bp->strm);
4576
4577 if (rc == Z_STREAM_END)
4578 return 0;
4579
4580 return rc;
4581}
4582
4583/* nic load/unload */
4584
4585/*
34f80b04 4586 * General service functions
a2fbb9ea
ET		 4587 */
4588
4589/* send a NIG loopback debug packet */
4590static void bnx2x_lb_pckt(struct bnx2x *bp)
4591{
a2fbb9ea 4592 u32 wb_write[3];
a2fbb9ea
ET		 4593
4594 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 4595 wb_write[0] = 0x55555555;
4596 wb_write[1] = 0x55555555;
34f80b04 4597 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 4598 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4599
4600 /* NON-IP protocol */
a2fbb9ea
ET		 4601 wb_write[0] = 0x09000000;
4602 wb_write[1] = 0x55555555;
34f80b04 4603 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 4604 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4605}
4606
4607/* some of the internal memories
4608 * are not directly readable from the driver
4609 * to test them we send debug packets
4610 */
4611static int bnx2x_int_mem_test(struct bnx2x *bp)
4612{
4613 int factor;
4614 int count, i;
4615 u32 val = 0;
4616
ad8d3948 4617 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 4618 factor = 120;
ad8d3948
EG		 4619 else if (CHIP_REV_IS_EMUL(bp))
4620 factor = 200;
4621 else
a2fbb9ea 4622 factor = 1;
a2fbb9ea 4623
a2fbb9ea
ET		 4624 /* Disable inputs of parser neighbor blocks */
4625 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4626 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4627 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4628 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4629
4630 /* Write 0 to parser credits for CFC search request */
4631 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4632
4633 /* send Ethernet packet */
4634 bnx2x_lb_pckt(bp);
4635
4636 /* TODO do i reset NIG statistic? */
4637 /* Wait until NIG register shows 1 packet of size 0x10 */
4638 count = 1000 * factor;
4639 while (count) {
34f80b04 4640
a2fbb9ea
ET		 4641 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4642 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4643 if (val == 0x10)
4644 break;
4645
4646 msleep(10);
4647 count--;
4648 }
4649 if (val != 0x10) {
4650 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4651 return -1;
4652 }
4653
4654 /* Wait until PRS register shows 1 packet */
4655 count = 1000 * factor;
4656 while (count) {
4657 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 4658 if (val == 1)
4659 break;
4660
4661 msleep(10);
4662 count--;
4663 }
4664 if (val != 0x1) {
4665 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4666 return -2;
4667 }
4668
4669 /* Reset and init BRB, PRS */
34f80b04 4670 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 4671 msleep(50);
34f80b04 4672 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 4673 msleep(50);
94a78b79
VZ		 4674 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4675 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
a2fbb9ea
ET		 4676
4677 DP(NETIF_MSG_HW, "part2\n");
4678
4679 /* Disable inputs of parser neighbor blocks */
4680 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4681 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4682 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4683 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4684
4685 /* Write 0 to parser credits for CFC search request */
4686 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4687
4688 /* send 10 Ethernet packets */
4689 for (i = 0; i < 10; i++)
4690 bnx2x_lb_pckt(bp);
4691
4692 /* Wait until NIG register shows 10 + 1
4693 packets of size 11*0x10 = 0xb0 */
4694 count = 1000 * factor;
4695 while (count) {
34f80b04 4696
a2fbb9ea
ET		 4697 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4698 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4699 if (val == 0xb0)
4700 break;
4701
4702 msleep(10);
4703 count--;
4704 }
4705 if (val != 0xb0) {
4706 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4707 return -3;
4708 }
4709
4710 /* Wait until PRS register shows 2 packets */
4711 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4712 if (val != 2)
4713 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4714
4715 /* Write 1 to parser credits for CFC search request */
4716 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4717
4718 /* Wait until PRS register shows 3 packets */
4719 msleep(10 * factor);
4720 /* Wait until NIG register shows 1 packet of size 0x10 */
4721 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4722 if (val != 3)
4723 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4724
4725 /* clear NIG EOP FIFO */
4726 for (i = 0; i < 11; i++)
4727 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4728 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4729 if (val != 1) {
4730 BNX2X_ERR("clear of NIG failed\n");
4731 return -4;
4732 }
4733
4734 /* Reset and init BRB, PRS, NIG */
4735 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4736 msleep(50);
4737 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4738 msleep(50);
94a78b79
VZ		 4739 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4740 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
37b091ba 4741#ifndef BCM_CNIC
a2fbb9ea
ET		 4742 /* set NIC mode */
4743 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4744#endif
4745
4746 /* Enable inputs of parser neighbor blocks */
4747 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4748 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4749 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 4750 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 4751
4752 DP(NETIF_MSG_HW, "done\n");
4753
4754 return 0; /* OK */
4755}
4756
4a33bc03 4757static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 4758{
4759 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
f2e0899f
DK		 4760 if (CHIP_IS_E2(bp))
4761 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4762 else
4763 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 4764 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4765 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 4766 /*
4767 * mask read length error interrupts in brb for parser
4768 * (parsing unit and 'checksum and crc' unit)
4769 * these errors are legal (PU reads fixed length and CAC can cause
4770 * read length error on truncated packets)
4771 */
4772 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 4773 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4774 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4775 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4776 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4777 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 4778/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4779/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4780 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4781 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4782 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 4783/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4784/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4785 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4786 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4787 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4788 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 4789/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4790/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 4791
34f80b04
EG		 4792 if (CHIP_REV_IS_FPGA(bp))
4793 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
f2e0899f
DK		 4794 else if (CHIP_IS_E2(bp))
4795 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4796 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4797 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4798 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4799 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4800 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 4801 else
4802 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 4803 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4804 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4805 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04
EG		 4806/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4807/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4808 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4809 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 4810/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 4811 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 4812}
4813
81f75bbf
EG		 4814static void bnx2x_reset_common(struct bnx2x *bp)
4815{
4816 /* reset_common */
4817 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4818 0xd3ffff7f);
4819 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4820}
4821
573f2035
EG		 4822static void bnx2x_init_pxp(struct bnx2x *bp)
4823{
4824 u16 devctl;
4825 int r_order, w_order;
4826
4827 pci_read_config_word(bp->pdev,
4828 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4829 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4830 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4831 if (bp->mrrs == -1)
4832 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4833 else {
4834 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4835 r_order = bp->mrrs;
4836 }
4837
4838 bnx2x_init_pxp_arb(bp, r_order, w_order);
4839}
fd4ef40d
EG		 4840
4841static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4842{
2145a920 4843 int is_required;
fd4ef40d 4844 u32 val;
2145a920 4845 int port;
fd4ef40d 4846
2145a920
VZ		 4847 if (BP_NOMCP(bp))
4848 return;
4849
4850 is_required = 0;
fd4ef40d
EG		 4851 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4852 SHARED_HW_CFG_FAN_FAILURE_MASK;
4853
4854 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4855 is_required = 1;
4856
4857 /*
4858 * The fan failure mechanism is usually related to the PHY type since
4859 * the power consumption of the board is affected by the PHY. Currently,
4860 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4861 */
4862 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4863 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 4864 is_required |=
d90d96ba
YR		 4865 bnx2x_fan_failure_det_req(
4866 bp,
4867 bp->common.shmem_base,
a22f0788 4868 bp->common.shmem2_base,
d90d96ba 4869 port);
fd4ef40d
EG		 4870 }
4871
4872 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4873
4874 if (is_required == 0)
4875 return;
4876
4877 /* Fan failure is indicated by SPIO 5 */
4878 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4879 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4880
4881 /* set to active low mode */
4882 val = REG_RD(bp, MISC_REG_SPIO_INT);
4883 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 4884 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 4885 REG_WR(bp, MISC_REG_SPIO_INT, val);
4886
4887 /* enable interrupt to signal the IGU */
4888 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4889 val |= (1 << MISC_REGISTERS_SPIO_5);
4890 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4891}
4892
f2e0899f
DK		 4893static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4894{
4895 u32 offset = 0;
4896
4897 if (CHIP_IS_E1(bp))
4898 return;
4899 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4900 return;
4901
4902 switch (BP_ABS_FUNC(bp)) {
4903 case 0:
4904 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4905 break;
4906 case 1:
4907 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4908 break;
4909 case 2:
4910 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4911 break;
4912 case 3:
4913 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4914 break;
4915 case 4:
4916 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4917 break;
4918 case 5:
4919 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4920 break;
4921 case 6:
4922 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4923 break;
4924 case 7:
4925 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4926 break;
4927 default:
4928 return;
4929 }
4930
4931 REG_WR(bp, offset, pretend_func_num);
4932 REG_RD(bp, offset);
4933 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4934}
4935
4936static void bnx2x_pf_disable(struct bnx2x *bp)
4937{
4938 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4939 val &= ~IGU_PF_CONF_FUNC_EN;
4940
4941 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4942 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4943 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4944}
4945
523224a3 4946static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
a2fbb9ea 4947{
a2fbb9ea 4948 u32 val, i;
a2fbb9ea 4949
f2e0899f 4950 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 4951
81f75bbf 4952 bnx2x_reset_common(bp);
34f80b04
EG		 4953 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4954 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
a2fbb9ea 4955
94a78b79 4956 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
f2e0899f 4957 if (!CHIP_IS_E1(bp))
fb3bff17 4958 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
a2fbb9ea 4959
f2e0899f
DK		 4960 if (CHIP_IS_E2(bp)) {
4961 u8 fid;
4962
4963 /**
4964 * 4-port mode or 2-port mode we need to turn of master-enable
4965 * for everyone, after that, turn it back on for self.
4966 * so, we disregard multi-function or not, and always disable
4967 * for all functions on the given path, this means 0,2,4,6 for
4968 * path 0 and 1,3,5,7 for path 1
4969 */
4970 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
4971 if (fid == BP_ABS_FUNC(bp)) {
4972 REG_WR(bp,
4973 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
4974 1);
4975 continue;
4976 }
4977
4978 bnx2x_pretend_func(bp, fid);
4979 /* clear pf enable */
4980 bnx2x_pf_disable(bp);
4981 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
4982 }
4983 }
a2fbb9ea 4984
94a78b79 4985 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
34f80b04
EG		 4986 if (CHIP_IS_E1(bp)) {
4987 /* enable HW interrupt from PXP on USDM overflow
4988 bit 16 on INT_MASK_0 */
4989 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4990 }
a2fbb9ea 4991
94a78b79 4992 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
34f80b04 4993 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 4994
4995#ifdef __BIG_ENDIAN
34f80b04
EG		 4996 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
4997 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
4998 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
4999 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5000 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5001 /* make sure this value is 0 */
5002 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5003
5004/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5005 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5006 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5007 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5008 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5009#endif
5010
523224a3
DK		 5011 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5012
34f80b04
EG		 5013 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5014 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5015
34f80b04
EG		 5016 /* let the HW do it's magic ... */
5017 msleep(100);
5018 /* finish PXP init */
5019 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5020 if (val != 1) {
5021 BNX2X_ERR("PXP2 CFG failed\n");
5022 return -EBUSY;
5023 }
5024 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5025 if (val != 1) {
5026 BNX2X_ERR("PXP2 RD_INIT failed\n");
5027 return -EBUSY;
5028 }
a2fbb9ea 5029
f2e0899f
DK		 5030 /* Timers bug workaround E2 only. We need to set the entire ILT to
5031 * have entries with value "0" and valid bit on.
5032 * This needs to be done by the first PF that is loaded in a path
5033 * (i.e. common phase)
5034 */
5035 if (CHIP_IS_E2(bp)) {
5036 struct ilt_client_info ilt_cli;
5037 struct bnx2x_ilt ilt;
5038 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5039 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5040
b595076a 5041 /* initialize dummy TM client */
f2e0899f
DK		 5042 ilt_cli.start = 0;
5043 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5044 ilt_cli.client_num = ILT_CLIENT_TM;
5045
5046 /* Step 1: set zeroes to all ilt page entries with valid bit on
5047 * Step 2: set the timers first/last ilt entry to point
5048 * to the entire range to prevent ILT range error for 3rd/4th
5049 * vnic (this code assumes existance of the vnic)
5050 *
5051 * both steps performed by call to bnx2x_ilt_client_init_op()
5052 * with dummy TM client
5053 *
5054 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5055 * and his brother are split registers
5056 */
5057 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5058 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5059 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5060
5061 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5062 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5063 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5064 }
5065
5066
34f80b04
EG		 5067 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5068 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5069
f2e0899f
DK		 5070 if (CHIP_IS_E2(bp)) {
5071 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5072 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5073 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5074
5075 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5076
5077 /* let the HW do it's magic ... */
5078 do {
5079 msleep(200);
5080 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5081 } while (factor-- && (val != 1));
5082
5083 if (val != 1) {
5084 BNX2X_ERR("ATC_INIT failed\n");
5085 return -EBUSY;
5086 }
5087 }
5088
94a78b79 5089 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
a2fbb9ea 5090
34f80b04
EG		 5091 /* clean the DMAE memory */
5092 bp->dmae_ready = 1;
5093 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
a2fbb9ea 5094
94a78b79
VZ		 5095 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5096 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5097 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5098 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
a2fbb9ea 5099
34f80b04
EG		 5100 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5101 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5102 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5103 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5104
94a78b79 5105 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
37b091ba 5106
f2e0899f
DK		 5107 if (CHIP_MODE_IS_4_PORT(bp))
5108 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
f85582f8 5109
523224a3
DK		 5110 /* QM queues pointers table */
5111 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5112
34f80b04
EG		 5113 /* soft reset pulse */
5114 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5115 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 5116
37b091ba 5117#ifdef BCM_CNIC
94a78b79 5118 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
a2fbb9ea 5119#endif
a2fbb9ea 5120
94a78b79 5121 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
523224a3
DK		 5122 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5123
34f80b04
EG		 5124 if (!CHIP_REV_IS_SLOW(bp)) {
5125 /* enable hw interrupt from doorbell Q */
5126 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5127 }
a2fbb9ea 5128
94a78b79 5129 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5130 if (CHIP_MODE_IS_4_PORT(bp)) {
5131 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5132 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5133 }
5134
94a78b79 5135 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
26c8fa4d 5136 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
37b091ba 5137#ifndef BCM_CNIC
3196a88a
EG		 5138 /* set NIC mode */
5139 REG_WR(bp, PRS_REG_NIC_MODE, 1);
37b091ba 5140#endif
f2e0899f 5141 if (!CHIP_IS_E1(bp))
0793f83f 5142 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
f85582f8 5143
f2e0899f
DK		 5144 if (CHIP_IS_E2(bp)) {
5145 /* Bit-map indicating which L2 hdrs may appear after the
5146 basic Ethernet header */
0793f83f 5147 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5148 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5149 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5150 }
a2fbb9ea 5151
94a78b79
VZ		 5152 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5153 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5154 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5155 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
a2fbb9ea 5156
ca00392c
EG		 5157 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5158 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5159 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5160 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
a2fbb9ea 5161
94a78b79
VZ		 5162 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5163 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5164 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5165 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
a2fbb9ea 5166
f2e0899f
DK		 5167 if (CHIP_MODE_IS_4_PORT(bp))
5168 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5169
34f80b04
EG		 5170 /* sync semi rtc */
5171 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5172 0x80000000);
5173 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5174 0x80000000);
a2fbb9ea 5175
94a78b79
VZ		 5176 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5177 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5178 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
a2fbb9ea 5179
f2e0899f 5180 if (CHIP_IS_E2(bp)) {
0793f83f 5181 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5182 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5183 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5184 }
5185
34f80b04 5186 REG_WR(bp, SRC_REG_SOFT_RST, 1);
c68ed255
TH		 5187 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5188 REG_WR(bp, i, random32());
f85582f8 5189
94a78b79 5190 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
37b091ba
MC		 5191#ifdef BCM_CNIC
5192 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5193 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5194 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5195 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5196 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5197 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5198 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5199 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5200 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5201 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5202#endif
34f80b04 5203 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 5204
34f80b04
EG		 5205 if (sizeof(union cdu_context) != 1024)
5206 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 5207 dev_alert(&bp->pdev->dev, "please adjust the size "
5208 "of cdu_context(%ld)\n",
7995c64e 5209 (long)sizeof(union cdu_context));
a2fbb9ea 5210
94a78b79 5211 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
34f80b04
EG		 5212 val = (4 << 24) + (0 << 12) + 1024;
5213 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 5214
94a78b79 5215 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
34f80b04 5216 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 5217 /* enable context validation interrupt from CFC */
5218 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5219
5220 /* set the thresholds to prevent CFC/CDU race */
5221 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 5222
94a78b79 5223 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5224
5225 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5226 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5227
5228 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
94a78b79 5229 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
a2fbb9ea 5230
94a78b79 5231 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
34f80b04
EG		 5232 /* Reset PCIE errors for debug */
5233 REG_WR(bp, 0x2814, 0xffffffff);
5234 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 5235
f2e0899f
DK		 5236 if (CHIP_IS_E2(bp)) {
5237 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5238 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5239 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5240 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5241 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5242 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5243 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5244 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5245 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5246 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5247 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5248 }
5249
94a78b79 5250 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
94a78b79 5251 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
94a78b79 5252 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
94a78b79 5253 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
34f80b04 5254
94a78b79 5255 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
f2e0899f 5256 if (!CHIP_IS_E1(bp)) {
fb3bff17 5257 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
0793f83f 5258 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04 5259 }
f2e0899f
DK		 5260 if (CHIP_IS_E2(bp)) {
5261 /* Bit-map indicating which L2 hdrs may appear after the
5262 basic Ethernet header */
0793f83f 5263 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
f2e0899f 5264 }
34f80b04
EG		 5265
5266 if (CHIP_REV_IS_SLOW(bp))
5267 msleep(200);
5268
5269 /* finish CFC init */
5270 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5271 if (val != 1) {
5272 BNX2X_ERR("CFC LL_INIT failed\n");
5273 return -EBUSY;
5274 }
5275 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5276 if (val != 1) {
5277 BNX2X_ERR("CFC AC_INIT failed\n");
5278 return -EBUSY;
5279 }
5280 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5281 if (val != 1) {
5282 BNX2X_ERR("CFC CAM_INIT failed\n");
5283 return -EBUSY;
5284 }
5285 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 5286
f2e0899f
DK		 5287 if (CHIP_IS_E1(bp)) {
5288 /* read NIG statistic
5289 to see if this is our first up since powerup */
5290 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5291 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 5292
f2e0899f
DK		 5293 /* do internal memory self test */
5294 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5295 BNX2X_ERR("internal mem self test failed\n");
5296 return -EBUSY;
5297 }
34f80b04
EG		 5298 }
5299
fd4ef40d
EG		 5300 bnx2x_setup_fan_failure_detection(bp);
5301
34f80b04
EG		 5302 /* clear PXP2 attentions */
5303 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 5304
4a33bc03
VZ		 5305 bnx2x_enable_blocks_attention(bp);
5306 if (CHIP_PARITY_ENABLED(bp))
5307 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 5308
6bbca910 5309 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 5310 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5311 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5312 CHIP_IS_E1x(bp)) {
5313 u32 shmem_base[2], shmem2_base[2];
5314 shmem_base[0] = bp->common.shmem_base;
5315 shmem2_base[0] = bp->common.shmem2_base;
5316 if (CHIP_IS_E2(bp)) {
5317 shmem_base[1] =
5318 SHMEM2_RD(bp, other_shmem_base_addr);
5319 shmem2_base[1] =
5320 SHMEM2_RD(bp, other_shmem2_base_addr);
5321 }
5322 bnx2x_acquire_phy_lock(bp);
5323 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5324 bp->common.chip_id);
5325 bnx2x_release_phy_lock(bp);
5326 }
6bbca910
YR		 5327 } else
5328 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5329
34f80b04
EG		 5330 return 0;
5331}
a2fbb9ea 5332
523224a3 5333static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 5334{
5335 int port = BP_PORT(bp);
94a78b79 5336 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
1c06328c 5337 u32 low, high;
34f80b04 5338 u32 val;
a2fbb9ea 5339
cdaa7cb8 5340 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 5341
5342 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 5343
94a78b79 5344 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
94a78b79 5345 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
ca00392c 5346
f2e0899f
DK		 5347 /* Timers bug workaround: disables the pf_master bit in pglue at
5348 * common phase, we need to enable it here before any dmae access are
5349 * attempted. Therefore we manually added the enable-master to the
5350 * port phase (it also happens in the function phase)
5351 */
5352 if (CHIP_IS_E2(bp))
5353 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5354
ca00392c
EG		 5355 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5356 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5357 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
94a78b79 5358 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
a2fbb9ea 5359
523224a3
DK		 5360 /* QM cid (connection) count */
5361 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 5362
523224a3 5363#ifdef BCM_CNIC
94a78b79 5364 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
37b091ba
MC		 5365 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5366 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 5367#endif
cdaa7cb8 5368
94a78b79 5369 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
1c06328c 5370
f2e0899f
DK		 5371 if (CHIP_MODE_IS_4_PORT(bp))
5372 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5373
5374 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5375 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5376 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5377 /* no pause for emulation and FPGA */
5378 low = 0;
5379 high = 513;
5380 } else {
5381 if (IS_MF(bp))
5382 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5383 else if (bp->dev->mtu > 4096) {
5384 if (bp->flags & ONE_PORT_FLAG)
5385 low = 160;
5386 else {
5387 val = bp->dev->mtu;
5388 /* (24*1024 + val*4)/256 */
5389 low = 96 + (val/64) +
5390 ((val % 64) ? 1 : 0);
5391 }
5392 } else
5393 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5394 high = low + 56; /* 14*1024/256 */
5395 }
5396 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5397 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 5398 }
1c06328c 5399
f2e0899f
DK		 5400 if (CHIP_MODE_IS_4_PORT(bp)) {
5401 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5402 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5403 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5404 BRB1_REG_MAC_GUARANTIED_0), 40);
5405 }
1c06328c 5406
94a78b79 5407 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
ca00392c 5408
94a78b79 5409 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
94a78b79 5410 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
94a78b79 5411 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
94a78b79 5412 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
356e2385 5413
94a78b79
VZ		 5414 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5415 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5416 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5417 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
f2e0899f
DK		 5418 if (CHIP_MODE_IS_4_PORT(bp))
5419 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
356e2385 5420
94a78b79 5421 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
94a78b79 5422 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
34f80b04 5423
94a78b79 5424 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
a2fbb9ea 5425
f2e0899f
DK		 5426 if (!CHIP_IS_E2(bp)) {
5427 /* configure PBF to work without PAUSE mtu 9000 */
5428 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 5429
f2e0899f
DK		 5430 /* update threshold */
5431 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5432 /* update init credit */
5433 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 5434
f2e0899f
DK		 5435 /* probe changes */
5436 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5437 udelay(50);
5438 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5439 }
a2fbb9ea 5440
37b091ba
MC		 5441#ifdef BCM_CNIC
5442 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
a2fbb9ea 5443#endif
94a78b79 5444 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
94a78b79 5445 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
34f80b04
EG		 5446
5447 if (CHIP_IS_E1(bp)) {
5448 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5449 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5450 }
94a78b79 5451 bnx2x_init_block(bp, HC_BLOCK, init_stage);
34f80b04 5452
f2e0899f
DK		 5453 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5454
94a78b79 5455 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
34f80b04
EG		 5456 /* init aeu_mask_attn_func_0/1:
5457 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5458 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5459 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 5460 val = IS_MF(bp) ? 0xF7 : 0x7;
5461 /* Enable DCBX attention for all but E1 */
5462 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5463 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 5464
94a78b79 5465 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
94a78b79 5466 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
94a78b79 5467 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
94a78b79 5468 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
94a78b79 5469 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
356e2385 5470
94a78b79 5471 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
34f80b04
EG		 5472
5473 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5474
f2e0899f 5475 if (!CHIP_IS_E1(bp)) {
fb3bff17 5476 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 5477 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 5478 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 5479
f2e0899f
DK		 5480 if (CHIP_IS_E2(bp)) {
5481 val = 0;
5482 switch (bp->mf_mode) {
5483 case MULTI_FUNCTION_SD:
5484 val = 1;
5485 break;
5486 case MULTI_FUNCTION_SI:
5487 val = 2;
5488 break;
5489 }
5490
5491 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5492 NIG_REG_LLH0_CLS_TYPE), val);
5493 }
1c06328c
EG		 5494 {
5495 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5496 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5497 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5498 }
34f80b04
EG		 5499 }
5500
94a78b79 5501 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
94a78b79 5502 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
d90d96ba 5503 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
a22f0788 5504 bp->common.shmem2_base, port)) {
4d295db0
EG		 5505 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5506 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5507 val = REG_RD(bp, reg_addr);
f1410647 5508 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 5509 REG_WR(bp, reg_addr, val);
f1410647 5510 }
c18487ee 5511 bnx2x__link_reset(bp);
a2fbb9ea 5512
34f80b04
EG		 5513 return 0;
5514}
5515
34f80b04
EG		 5516static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5517{
5518 int reg;
5519
f2e0899f 5520 if (CHIP_IS_E1(bp))
34f80b04 5521 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 5522 else
5523 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 5524
5525 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5526}
5527
f2e0899f
DK		 5528static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5529{
5530 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5531}
5532
5533static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5534{
5535 u32 i, base = FUNC_ILT_BASE(func);
5536 for (i = base; i < base + ILT_PER_FUNC; i++)
5537 bnx2x_ilt_wr(bp, i, 0);
5538}
5539
523224a3 5540static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 5541{
5542 int port = BP_PORT(bp);
5543 int func = BP_FUNC(bp);
523224a3
DK		 5544 struct bnx2x_ilt *ilt = BP_ILT(bp);
5545 u16 cdu_ilt_start;
8badd27a 5546 u32 addr, val;
f4a66897
VZ		 5547 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5548 int i, main_mem_width;
34f80b04 5549
cdaa7cb8 5550 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 5551
8badd27a 5552 /* set MSI reconfigure capability */
f2e0899f
DK		 5553 if (bp->common.int_block == INT_BLOCK_HC) {
5554 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5555 val = REG_RD(bp, addr);
5556 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5557 REG_WR(bp, addr, val);
5558 }
8badd27a 5559
523224a3
DK		 5560 ilt = BP_ILT(bp);
5561 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 5562
523224a3
DK		 5563 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5564 ilt->lines[cdu_ilt_start + i].page =
5565 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5566 ilt->lines[cdu_ilt_start + i].page_mapping =
5567 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5568 /* cdu ilt pages are allocated manually so there's no need to
5569 set the size */
37b091ba 5570 }
523224a3 5571 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 5572
523224a3
DK		 5573#ifdef BCM_CNIC
5574 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 5575
523224a3
DK		 5576 /* T1 hash bits value determines the T1 number of entries */
5577 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5578#endif
37b091ba 5579
523224a3
DK		 5580#ifndef BCM_CNIC
5581 /* set NIC mode */
5582 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5583#endif /* BCM_CNIC */
37b091ba 5584
f2e0899f
DK		 5585 if (CHIP_IS_E2(bp)) {
5586 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5587
5588 /* Turn on a single ISR mode in IGU if driver is going to use
5589 * INT#x or MSI
5590 */
5591 if (!(bp->flags & USING_MSIX_FLAG))
5592 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5593 /*
5594 * Timers workaround bug: function init part.
5595 * Need to wait 20msec after initializing ILT,
5596 * needed to make sure there are no requests in
5597 * one of the PXP internal queues with "old" ILT addresses
5598 */
5599 msleep(20);
5600 /*
5601 * Master enable - Due to WB DMAE writes performed before this
5602 * register is re-initialized as part of the regular function
5603 * init
5604 */
5605 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5606 /* Enable the function in IGU */
5607 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5608 }
5609
523224a3 5610 bp->dmae_ready = 1;
34f80b04 5611
523224a3
DK		 5612 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5613
f2e0899f
DK		 5614 if (CHIP_IS_E2(bp))
5615 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5616
523224a3
DK		 5617 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5618 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5619 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5620 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5621 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5622 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5623 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5624 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5625 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5626
f2e0899f
DK		 5627 if (CHIP_IS_E2(bp)) {
5628 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5629 BP_PATH(bp));
5630 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5631 BP_PATH(bp));
5632 }
5633
5634 if (CHIP_MODE_IS_4_PORT(bp))
5635 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5636
5637 if (CHIP_IS_E2(bp))
5638 REG_WR(bp, QM_REG_PF_EN, 1);
5639
523224a3 5640 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5641
5642 if (CHIP_MODE_IS_4_PORT(bp))
5643 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5644
523224a3
DK		 5645 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5646 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5647 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5648 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5649 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5650 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5651 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5652 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5653 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5654 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5655 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5656 if (CHIP_IS_E2(bp))
5657 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5658
523224a3
DK		 5659 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5660
5661 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
34f80b04 5662
f2e0899f
DK		 5663 if (CHIP_IS_E2(bp))
5664 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5665
fb3bff17 5666 if (IS_MF(bp)) {
34f80b04 5667 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 5668 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 5669 }
5670
523224a3
DK		 5671 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5672
34f80b04 5673 /* HC init per function */
f2e0899f
DK		 5674 if (bp->common.int_block == INT_BLOCK_HC) {
5675 if (CHIP_IS_E1H(bp)) {
5676 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5677
5678 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5679 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5680 }
5681 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5682
5683 } else {
5684 int num_segs, sb_idx, prod_offset;
5685
34f80b04
EG		 5686 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5687
f2e0899f
DK		 5688 if (CHIP_IS_E2(bp)) {
5689 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5690 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5691 }
5692
5693 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5694
5695 if (CHIP_IS_E2(bp)) {
5696 int dsb_idx = 0;
5697 /**
5698 * Producer memory:
5699 * E2 mode: address 0-135 match to the mapping memory;
5700 * 136 - PF0 default prod; 137 - PF1 default prod;
5701 * 138 - PF2 default prod; 139 - PF3 default prod;
5702 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5703 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5704 * 144-147 reserved.
5705 *
5706 * E1.5 mode - In backward compatible mode;
5707 * for non default SB; each even line in the memory
5708 * holds the U producer and each odd line hold
5709 * the C producer. The first 128 producers are for
5710 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5711 * producers are for the DSB for each PF.
5712 * Each PF has five segments: (the order inside each
5713 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5714 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5715 * 144-147 attn prods;
5716 */
5717 /* non-default-status-blocks */
5718 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5719 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5720 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5721 prod_offset = (bp->igu_base_sb + sb_idx) *
5722 num_segs;
5723
5724 for (i = 0; i < num_segs; i++) {
5725 addr = IGU_REG_PROD_CONS_MEMORY +
5726 (prod_offset + i) * 4;
5727 REG_WR(bp, addr, 0);
5728 }
5729 /* send consumer update with value 0 */
5730 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5731 USTORM_ID, 0, IGU_INT_NOP, 1);
5732 bnx2x_igu_clear_sb(bp,
5733 bp->igu_base_sb + sb_idx);
5734 }
5735
5736 /* default-status-blocks */
5737 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5738 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5739
5740 if (CHIP_MODE_IS_4_PORT(bp))
5741 dsb_idx = BP_FUNC(bp);
5742 else
5743 dsb_idx = BP_E1HVN(bp);
5744
5745 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5746 IGU_BC_BASE_DSB_PROD + dsb_idx :
5747 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5748
5749 for (i = 0; i < (num_segs * E1HVN_MAX);
5750 i += E1HVN_MAX) {
5751 addr = IGU_REG_PROD_CONS_MEMORY +
5752 (prod_offset + i)*4;
5753 REG_WR(bp, addr, 0);
5754 }
5755 /* send consumer update with 0 */
5756 if (CHIP_INT_MODE_IS_BC(bp)) {
5757 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5758 USTORM_ID, 0, IGU_INT_NOP, 1);
5759 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5760 CSTORM_ID, 0, IGU_INT_NOP, 1);
5761 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5762 XSTORM_ID, 0, IGU_INT_NOP, 1);
5763 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5764 TSTORM_ID, 0, IGU_INT_NOP, 1);
5765 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5766 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5767 } else {
5768 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5769 USTORM_ID, 0, IGU_INT_NOP, 1);
5770 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5771 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5772 }
5773 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5774
5775 /* !!! these should become driver const once
5776 rf-tool supports split-68 const */
5777 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5778 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5779 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5780 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5781 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5782 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5783 }
34f80b04 5784 }
34f80b04 5785
c14423fe 5786 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 5787 REG_WR(bp, 0x2114, 0xffffffff);
5788 REG_WR(bp, 0x2120, 0xffffffff);
523224a3
DK		 5789
5790 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5791 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5792 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5793 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5794 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5795 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5796
f4a66897
VZ		 5797 if (CHIP_IS_E1x(bp)) {
5798 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5799 main_mem_base = HC_REG_MAIN_MEMORY +
5800 BP_PORT(bp) * (main_mem_size * 4);
5801 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5802 main_mem_width = 8;
5803
5804 val = REG_RD(bp, main_mem_prty_clr);
5805 if (val)
5806 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5807 "block during "
5808 "function init (0x%x)!\n", val);
5809
5810 /* Clear "false" parity errors in MSI-X table */
5811 for (i = main_mem_base;
5812 i < main_mem_base + main_mem_size * 4;
5813 i += main_mem_width) {
5814 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5815 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5816 i, main_mem_width / 4);
5817 }
5818 /* Clear HC parity attention */
5819 REG_RD(bp, main_mem_prty_clr);
5820 }
5821
b7737c9b 5822 bnx2x_phy_probe(&bp->link_params);
f85582f8 5823
34f80b04
EG		 5824 return 0;
5825}
5826
9f6c9258 5827int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
34f80b04 5828{
523224a3 5829 int rc = 0;
a2fbb9ea 5830
34f80b04 5831 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
f2e0899f 5832 BP_ABS_FUNC(bp), load_code);
a2fbb9ea 5833
34f80b04
EG		 5834 bp->dmae_ready = 0;
5835 mutex_init(&bp->dmae_mutex);
54016b26
EG		 5836 rc = bnx2x_gunzip_init(bp);
5837 if (rc)
5838 return rc;
a2fbb9ea 5839
34f80b04
EG		 5840 switch (load_code) {
5841 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5842 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
523224a3 5843 rc = bnx2x_init_hw_common(bp, load_code);
34f80b04
EG		 5844 if (rc)
5845 goto init_hw_err;
5846 /* no break */
5847
5848 case FW_MSG_CODE_DRV_LOAD_PORT:
523224a3 5849 rc = bnx2x_init_hw_port(bp);
34f80b04
EG		 5850 if (rc)
5851 goto init_hw_err;
5852 /* no break */
5853
5854 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3 5855 rc = bnx2x_init_hw_func(bp);
34f80b04
EG		 5856 if (rc)
5857 goto init_hw_err;
5858 break;
5859
5860 default:
5861 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5862 break;
5863 }
5864
5865 if (!BP_NOMCP(bp)) {
f2e0899f 5866 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 5867
5868 bp->fw_drv_pulse_wr_seq =
f2e0899f 5869 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
a2fbb9ea 5870 DRV_PULSE_SEQ_MASK);
6fe49bb9
EG		 5871 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5872 }
a2fbb9ea 5873
34f80b04
EG		 5874init_hw_err:
5875 bnx2x_gunzip_end(bp);
5876
5877 return rc;
a2fbb9ea
ET		 5878}
5879
9f6c9258 5880void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea
ET		 5881{
5882
5883#define BNX2X_PCI_FREE(x, y, size) \
5884 do { \
5885 if (x) { \
523224a3 5886 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
a2fbb9ea
ET		 5887 x = NULL; \
5888 y = 0; \
5889 } \
5890 } while (0)
5891
5892#define BNX2X_FREE(x) \
5893 do { \
5894 if (x) { \
523224a3 5895 kfree((void *)x); \
a2fbb9ea
ET		 5896 x = NULL; \
5897 } \
5898 } while (0)
5899
5900 int i;
5901
5902 /* fastpath */
555f6c78 5903 /* Common */
a2fbb9ea 5904 for_each_queue(bp, i) {
ec6ba945
VZ		 5905#ifdef BCM_CNIC
5906 /* FCoE client uses default status block */
5907 if (IS_FCOE_IDX(i)) {
5908 union host_hc_status_block *sb =
5909 &bnx2x_fp(bp, i, status_blk);
5910 memset(sb, 0, sizeof(union host_hc_status_block));
5911 bnx2x_fp(bp, i, status_blk_mapping) = 0;
5912 } else {
5913#endif
555f6c78 5914 /* status blocks */
f2e0899f
DK		 5915 if (CHIP_IS_E2(bp))
5916 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
5917 bnx2x_fp(bp, i, status_blk_mapping),
5918 sizeof(struct host_hc_status_block_e2));
5919 else
5920 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
5921 bnx2x_fp(bp, i, status_blk_mapping),
5922 sizeof(struct host_hc_status_block_e1x));
ec6ba945
VZ		 5923#ifdef BCM_CNIC
5924 }
5925#endif
555f6c78
EG		 5926 }
5927 /* Rx */
ec6ba945 5928 for_each_rx_queue(bp, i) {
a2fbb9ea 5929
555f6c78 5930 /* fastpath rx rings: rx_buf rx_desc rx_comp */
a2fbb9ea
ET		 5931 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5932 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5933 bnx2x_fp(bp, i, rx_desc_mapping),
5934 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5935
5936 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5937 bnx2x_fp(bp, i, rx_comp_mapping),
5938 sizeof(struct eth_fast_path_rx_cqe) *
5939 NUM_RCQ_BD);
a2fbb9ea 5940
7a9b2557 5941 /* SGE ring */
32626230 5942 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
7a9b2557
VZ		 5943 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5944 bnx2x_fp(bp, i, rx_sge_mapping),
5945 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5946 }
555f6c78 5947 /* Tx */
ec6ba945 5948 for_each_tx_queue(bp, i) {
555f6c78
EG		 5949
5950 /* fastpath tx rings: tx_buf tx_desc */
5951 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5952 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5953 bnx2x_fp(bp, i, tx_desc_mapping),
ca00392c 5954 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
555f6c78 5955 }
a2fbb9ea
ET		 5956 /* end of fastpath */
5957
5958 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 5959 sizeof(struct host_sp_status_block));
a2fbb9ea
ET		 5960
5961 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 5962 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5963
523224a3
DK		 5964 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5965 bp->context.size);
5966
5967 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5968
5969 BNX2X_FREE(bp->ilt->lines);
f85582f8 5970
37b091ba 5971#ifdef BCM_CNIC
f2e0899f
DK		 5972 if (CHIP_IS_E2(bp))
5973 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5974 sizeof(struct host_hc_status_block_e2));
5975 else
5976 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5977 sizeof(struct host_hc_status_block_e1x));
f85582f8 5978
523224a3 5979 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 5980#endif
f85582f8 5981
7a9b2557 5982 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 5983
523224a3
DK		 5984 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5985 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5986
a2fbb9ea
ET		 5987#undef BNX2X_PCI_FREE
5988#undef BNX2X_KFREE
5989}
5990
f2e0899f
DK		 5991static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
5992{
5993 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
5994 if (CHIP_IS_E2(bp)) {
5995 bnx2x_fp(bp, index, sb_index_values) =
5996 (__le16 *)status_blk.e2_sb->sb.index_values;
5997 bnx2x_fp(bp, index, sb_running_index) =
5998 (__le16 *)status_blk.e2_sb->sb.running_index;
5999 } else {
6000 bnx2x_fp(bp, index, sb_index_values) =
6001 (__le16 *)status_blk.e1x_sb->sb.index_values;
6002 bnx2x_fp(bp, index, sb_running_index) =
6003 (__le16 *)status_blk.e1x_sb->sb.running_index;
6004 }
6005}
6006
9f6c9258 6007int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6008{
a2fbb9ea
ET		 6009#define BNX2X_PCI_ALLOC(x, y, size) \
6010 do { \
1a983142 6011 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
9f6c9258
DK		 6012 if (x == NULL) \
6013 goto alloc_mem_err; \
6014 memset(x, 0, size); \
6015 } while (0)
a2fbb9ea 6016
9f6c9258
DK		 6017#define BNX2X_ALLOC(x, size) \
6018 do { \
523224a3 6019 x = kzalloc(size, GFP_KERNEL); \
9f6c9258
DK		 6020 if (x == NULL) \
6021 goto alloc_mem_err; \
9f6c9258 6022 } while (0)
a2fbb9ea 6023
9f6c9258 6024 int i;
a2fbb9ea 6025
9f6c9258
DK		 6026 /* fastpath */
6027 /* Common */
a2fbb9ea 6028 for_each_queue(bp, i) {
f2e0899f 6029 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
9f6c9258 6030 bnx2x_fp(bp, i, bp) = bp;
9f6c9258 6031 /* status blocks */
ec6ba945
VZ		 6032#ifdef BCM_CNIC
6033 if (!IS_FCOE_IDX(i)) {
6034#endif
6035 if (CHIP_IS_E2(bp))
6036 BNX2X_PCI_ALLOC(sb->e2_sb,
6037 &bnx2x_fp(bp, i, status_blk_mapping),
6038 sizeof(struct host_hc_status_block_e2));
6039 else
6040 BNX2X_PCI_ALLOC(sb->e1x_sb,
6041 &bnx2x_fp(bp, i, status_blk_mapping),
6042 sizeof(struct host_hc_status_block_e1x));
6043#ifdef BCM_CNIC
6044 }
6045#endif
f2e0899f 6046 set_sb_shortcuts(bp, i);
a2fbb9ea 6047 }
9f6c9258
DK		 6048 /* Rx */
6049 for_each_queue(bp, i) {
a2fbb9ea 6050
9f6c9258
DK		 6051 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6052 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6053 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6054 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6055 &bnx2x_fp(bp, i, rx_desc_mapping),
6056 sizeof(struct eth_rx_bd) * NUM_RX_BD);
555f6c78 6057
9f6c9258
DK		 6058 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6059 &bnx2x_fp(bp, i, rx_comp_mapping),
6060 sizeof(struct eth_fast_path_rx_cqe) *
6061 NUM_RCQ_BD);
a2fbb9ea 6062
9f6c9258
DK		 6063 /* SGE ring */
6064 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6065 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6066 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6067 &bnx2x_fp(bp, i, rx_sge_mapping),
6068 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6069 }
6070 /* Tx */
6071 for_each_queue(bp, i) {
8badd27a 6072
9f6c9258
DK		 6073 /* fastpath tx rings: tx_buf tx_desc */
6074 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6075 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6076 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6077 &bnx2x_fp(bp, i, tx_desc_mapping),
6078 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
8badd27a 6079 }
9f6c9258 6080 /* end of fastpath */
8badd27a 6081
523224a3 6082#ifdef BCM_CNIC
f2e0899f
DK		 6083 if (CHIP_IS_E2(bp))
6084 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6085 sizeof(struct host_hc_status_block_e2));
6086 else
6087 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6088 sizeof(struct host_hc_status_block_e1x));
8badd27a 6089
523224a3
DK		 6090 /* allocate searcher T2 table */
6091 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6092#endif
a2fbb9ea 6093
8badd27a 6094
523224a3
DK		 6095 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6096 sizeof(struct host_sp_status_block));
a2fbb9ea 6097
523224a3
DK		 6098 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6099 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6100
523224a3 6101 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
f85582f8 6102
523224a3
DK		 6103 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6104 bp->context.size);
65abd74d 6105
523224a3 6106 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6107
523224a3
DK		 6108 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6109 goto alloc_mem_err;
65abd74d 6110
9f6c9258
DK		 6111 /* Slow path ring */
6112 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6113
523224a3
DK		 6114 /* EQ */
6115 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6116 BCM_PAGE_SIZE * NUM_EQ_PAGES);
9f6c9258 6117 return 0;
e1510706 6118
9f6c9258
DK		 6119alloc_mem_err:
6120 bnx2x_free_mem(bp);
6121 return -ENOMEM;
e1510706 6122
9f6c9258
DK		 6123#undef BNX2X_PCI_ALLOC
6124#undef BNX2X_ALLOC
65abd74d
YG		 6125}
6126
a2fbb9ea
ET		 6127/*
6128 * Init service functions
6129 */
8d96286a 6130static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6131 int *state_p, int flags);
6132
523224a3 6133int bnx2x_func_start(struct bnx2x *bp)
a2fbb9ea 6134{
523224a3 6135 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
a2fbb9ea 6136
523224a3
DK		 6137 /* Wait for completion */
6138 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6139 WAIT_RAMROD_COMMON);
6140}
a2fbb9ea 6141
8d96286a 6142static int bnx2x_func_stop(struct bnx2x *bp)
523224a3
DK		 6143{
6144 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
a2fbb9ea 6145
523224a3
DK		 6146 /* Wait for completion */
6147 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6148 0, &(bp->state), WAIT_RAMROD_COMMON);
a2fbb9ea
ET		 6149}
6150
e665bfda 6151/**
f85582f8 6152 * Sets a MAC in a CAM for a few L2 Clients for E1x chips
e665bfda
MC		 6153 *
6154 * @param bp driver descriptor
6155 * @param set set or clear an entry (1 or 0)
6156 * @param mac pointer to a buffer containing a MAC
6157 * @param cl_bit_vec bit vector of clients to register a MAC for
6158 * @param cam_offset offset in a CAM to use
523224a3 6159 * @param is_bcast is the set MAC a broadcast address (for E1 only)
e665bfda 6160 */
215faf9c 6161static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
f85582f8
DK		 6162 u32 cl_bit_vec, u8 cam_offset,
6163 u8 is_bcast)
34f80b04 6164{
523224a3
DK		 6165 struct mac_configuration_cmd *config =
6166 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6167 int ramrod_flags = WAIT_RAMROD_COMMON;
6168
6169 bp->set_mac_pending = 1;
6170 smp_wmb();
6171
8d9c5f34 6172 config->hdr.length = 1;
e665bfda
MC		 6173 config->hdr.offset = cam_offset;
6174 config->hdr.client_id = 0xff;
34f80b04
EG		 6175 config->hdr.reserved1 = 0;
6176
6177 /* primary MAC */
6178 config->config_table[0].msb_mac_addr =
e665bfda 6179 swab16(*(u16 *)&mac[0]);
34f80b04 6180 config->config_table[0].middle_mac_addr =
e665bfda 6181 swab16(*(u16 *)&mac[2]);
34f80b04 6182 config->config_table[0].lsb_mac_addr =
e665bfda 6183 swab16(*(u16 *)&mac[4]);
ca00392c 6184 config->config_table[0].clients_bit_vector =
e665bfda 6185 cpu_to_le32(cl_bit_vec);
34f80b04 6186 config->config_table[0].vlan_id = 0;
523224a3 6187 config->config_table[0].pf_id = BP_FUNC(bp);
3101c2bc 6188 if (set)
523224a3
DK		 6189 SET_FLAG(config->config_table[0].flags,
6190 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6191 T_ETH_MAC_COMMAND_SET);
3101c2bc 6192 else
523224a3
DK		 6193 SET_FLAG(config->config_table[0].flags,
6194 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6195 T_ETH_MAC_COMMAND_INVALIDATE);
34f80b04 6196
523224a3
DK		 6197 if (is_bcast)
6198 SET_FLAG(config->config_table[0].flags,
6199 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6200
6201 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
3101c2bc 6202 (set ? "setting" : "clearing"),
34f80b04
EG		 6203 config->config_table[0].msb_mac_addr,
6204 config->config_table[0].middle_mac_addr,
523224a3 6205 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
34f80b04 6206
523224a3 6207 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
34f80b04 6208 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3
DK		 6209 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6210
6211 /* Wait for a completion */
6212 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
34f80b04
EG		 6213}
6214
8d96286a 6215static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6216 int *state_p, int flags)
a2fbb9ea
ET		 6217{
6218 /* can take a while if any port is running */
8b3a0f0b 6219 int cnt = 5000;
523224a3
DK		 6220 u8 poll = flags & WAIT_RAMROD_POLL;
6221 u8 common = flags & WAIT_RAMROD_COMMON;
a2fbb9ea 6222
c14423fe
ET		 6223 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6224 poll ? "polling" : "waiting", state, idx);
a2fbb9ea
ET		 6225
6226 might_sleep();
34f80b04 6227 while (cnt--) {
a2fbb9ea 6228 if (poll) {
523224a3
DK		 6229 if (common)
6230 bnx2x_eq_int(bp);
6231 else {
6232 bnx2x_rx_int(bp->fp, 10);
6233 /* if index is different from 0
6234 * the reply for some commands will
6235 * be on the non default queue
6236 */
6237 if (idx)
6238 bnx2x_rx_int(&bp->fp[idx], 10);
6239 }
a2fbb9ea 6240 }
a2fbb9ea 6241
3101c2bc 6242 mb(); /* state is changed by bnx2x_sp_event() */
8b3a0f0b
EG		 6243 if (*state_p == state) {
6244#ifdef BNX2X_STOP_ON_ERROR
6245 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6246#endif
a2fbb9ea 6247 return 0;
8b3a0f0b 6248 }
a2fbb9ea 6249
a2fbb9ea 6250 msleep(1);
e3553b29
EG		 6251
6252 if (bp->panic)
6253 return -EIO;
a2fbb9ea
ET		 6254 }
6255
a2fbb9ea 6256 /* timeout! */
49d66772
ET		 6257 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6258 poll ? "polling" : "waiting", state, idx);
34f80b04
EG		 6259#ifdef BNX2X_STOP_ON_ERROR
6260 bnx2x_panic();
6261#endif
a2fbb9ea 6262
49d66772 6263 return -EBUSY;
a2fbb9ea
ET		 6264}
6265
8d96286a 6266static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
e665bfda 6267{
f2e0899f
DK		 6268 if (CHIP_IS_E1H(bp))
6269 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6270 else if (CHIP_MODE_IS_4_PORT(bp))
6271 return BP_FUNC(bp) * 32 + rel_offset;
6272 else
6273 return BP_VN(bp) * 32 + rel_offset;
523224a3
DK		 6274}
6275
0793f83f
DK		 6276/**
6277 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6278 * relevant. In addition, current implementation is tuned for a
6279 * single ETH MAC.
6280 *
6281 * When multiple unicast ETH MACs PF configuration in switch
6282 * independent mode is required (NetQ, multiple netdev MACs,
6283 * etc.), consider better utilisation of 16 per function MAC
6284 * entries in the LLH memory.
6285 */
6286enum {
6287 LLH_CAM_ISCSI_ETH_LINE = 0,
6288 LLH_CAM_ETH_LINE,
6289 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6290};
6291
6292static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6293 int set,
6294 unsigned char *dev_addr,
6295 int index)
6296{
6297 u32 wb_data[2];
6298 u32 mem_offset, ena_offset, mem_index;
6299 /**
6300 * indexes mapping:
6301 * 0..7 - goes to MEM
6302 * 8..15 - goes to MEM2
6303 */
6304
6305 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6306 return;
6307
6308 /* calculate memory start offset according to the mapping
6309 * and index in the memory */
6310 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6311 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6312 NIG_REG_LLH0_FUNC_MEM;
6313 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6314 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6315 mem_index = index;
6316 } else {
6317 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6318 NIG_REG_P0_LLH_FUNC_MEM2;
6319 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6320 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6321 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6322 }
6323
6324 if (set) {
6325 /* LLH_FUNC_MEM is a u64 WB register */
6326 mem_offset += 8*mem_index;
6327
6328 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6329 (dev_addr[4] << 8) | dev_addr[5]);
6330 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6331
6332 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6333 }
6334
6335 /* enable/disable the entry */
6336 REG_WR(bp, ena_offset + 4*mem_index, set);
6337
6338}
6339
523224a3
DK		 6340void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6341{
6342 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6343 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
e665bfda 6344
523224a3
DK		 6345 /* networking MAC */
6346 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6347 (1 << bp->fp->cl_id), cam_offset , 0);
e665bfda 6348
0793f83f
DK		 6349 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6350
523224a3
DK		 6351 if (CHIP_IS_E1(bp)) {
6352 /* broadcast MAC */
215faf9c
JP		 6353 static const u8 bcast[ETH_ALEN] = {
6354 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6355 };
523224a3
DK		 6356 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6357 }
e665bfda 6358}
523224a3
DK		 6359static void bnx2x_set_e1_mc_list(struct bnx2x *bp, u8 offset)
6360{
6361 int i = 0, old;
6362 struct net_device *dev = bp->dev;
6363 struct netdev_hw_addr *ha;
6364 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6365 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6366
6367 netdev_for_each_mc_addr(ha, dev) {
6368 /* copy mac */
6369 config_cmd->config_table[i].msb_mac_addr =
6370 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6371 config_cmd->config_table[i].middle_mac_addr =
6372 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6373 config_cmd->config_table[i].lsb_mac_addr =
6374 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
e665bfda 6375
523224a3
DK		 6376 config_cmd->config_table[i].vlan_id = 0;
6377 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6378 config_cmd->config_table[i].clients_bit_vector =
6379 cpu_to_le32(1 << BP_L_ID(bp));
6380
6381 SET_FLAG(config_cmd->config_table[i].flags,
6382 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6383 T_ETH_MAC_COMMAND_SET);
6384
6385 DP(NETIF_MSG_IFUP,
6386 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6387 config_cmd->config_table[i].msb_mac_addr,
6388 config_cmd->config_table[i].middle_mac_addr,
6389 config_cmd->config_table[i].lsb_mac_addr);
6390 i++;
6391 }
6392 old = config_cmd->hdr.length;
6393 if (old > i) {
6394 for (; i < old; i++) {
6395 if (CAM_IS_INVALID(config_cmd->
6396 config_table[i])) {
6397 /* already invalidated */
6398 break;
6399 }
6400 /* invalidate */
6401 SET_FLAG(config_cmd->config_table[i].flags,
6402 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6403 T_ETH_MAC_COMMAND_INVALIDATE);
6404 }
6405 }
6406
6407 config_cmd->hdr.length = i;
6408 config_cmd->hdr.offset = offset;
6409 config_cmd->hdr.client_id = 0xff;
6410 config_cmd->hdr.reserved1 = 0;
6411
6412 bp->set_mac_pending = 1;
6413 smp_wmb();
6414
6415 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6416 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6417}
6418static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)
e665bfda 6419{
523224a3
DK		 6420 int i;
6421 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6422 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6423 int ramrod_flags = WAIT_RAMROD_COMMON;
6424
6425 bp->set_mac_pending = 1;
e665bfda
MC		 6426 smp_wmb();
6427
523224a3
DK		 6428 for (i = 0; i < config_cmd->hdr.length; i++)
6429 SET_FLAG(config_cmd->config_table[i].flags,
6430 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6431 T_ETH_MAC_COMMAND_INVALIDATE);
6432
6433 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6434 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
e665bfda
MC		 6435
6436 /* Wait for a completion */
523224a3
DK		 6437 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6438 ramrod_flags);
6439
e665bfda
MC		 6440}
6441
993ac7b5
MC		 6442#ifdef BCM_CNIC
6443/**
6444 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
6445 * MAC(s). This function will wait until the ramdord completion
6446 * returns.
6447 *
6448 * @param bp driver handle
6449 * @param set set or clear the CAM entry
6450 *
6451 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6452 */
8d96286a 6453static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
993ac7b5 6454{
523224a3
DK		 6455 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6456 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
ec6ba945
VZ		 6457 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6458 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
523224a3 6459 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
2ba45142 6460 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
993ac7b5
MC		 6461
6462 /* Send a SET_MAC ramrod */
2ba45142 6463 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
523224a3 6464 cam_offset, 0);
0793f83f 6465
2ba45142 6466 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
ec6ba945
VZ		 6467
6468 return 0;
6469}
6470
6471/**
6472 * Set FCoE L2 MAC(s) at the next enties in the CAM after the
6473 * ETH MAC(s). This function will wait until the ramdord
6474 * completion returns.
6475 *
6476 * @param bp driver handle
6477 * @param set set or clear the CAM entry
6478 *
6479 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6480 */
6481int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6482{
6483 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6484 /**
6485 * CAM allocation for E1H
6486 * eth unicasts: by func number
6487 * iscsi: by func number
6488 * fip unicast: by func number
6489 * fip multicast: by func number
6490 */
6491 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6492 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6493
6494 return 0;
6495}
6496
6497int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6498{
6499 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6500
6501 /**
6502 * CAM allocation for E1H
6503 * eth unicasts: by func number
6504 * iscsi: by func number
6505 * fip unicast: by func number
6506 * fip multicast: by func number
6507 */
6508 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6509 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6510
993ac7b5
MC		 6511 return 0;
6512}
6513#endif
6514
523224a3
DK		 6515static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6516 struct bnx2x_client_init_params *params,
6517 u8 activate,
6518 struct client_init_ramrod_data *data)
6519{
6520 /* Clear the buffer */
6521 memset(data, 0, sizeof(*data));
6522
6523 /* general */
6524 data->general.client_id = params->rxq_params.cl_id;
6525 data->general.statistics_counter_id = params->rxq_params.stat_id;
6526 data->general.statistics_en_flg =
6527 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
ec6ba945
VZ		 6528 data->general.is_fcoe_flg =
6529 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
523224a3
DK		 6530 data->general.activate_flg = activate;
6531 data->general.sp_client_id = params->rxq_params.spcl_id;
6532
6533 /* Rx data */
6534 data->rx.tpa_en_flg =
6535 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6536 data->rx.vmqueue_mode_en_flg = 0;
6537 data->rx.cache_line_alignment_log_size =
6538 params->rxq_params.cache_line_log;
6539 data->rx.enable_dynamic_hc =
6540 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6541 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6542 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6543 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6544
6545 /* We don't set drop flags */
6546 data->rx.drop_ip_cs_err_flg = 0;
6547 data->rx.drop_tcp_cs_err_flg = 0;
6548 data->rx.drop_ttl0_flg = 0;
6549 data->rx.drop_udp_cs_err_flg = 0;
6550
6551 data->rx.inner_vlan_removal_enable_flg =
6552 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6553 data->rx.outer_vlan_removal_enable_flg =
6554 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6555 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6556 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6557 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6558 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6559 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6560 data->rx.bd_page_base.lo =
6561 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6562 data->rx.bd_page_base.hi =
6563 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6564 data->rx.sge_page_base.lo =
6565 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6566 data->rx.sge_page_base.hi =
6567 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6568 data->rx.cqe_page_base.lo =
6569 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6570 data->rx.cqe_page_base.hi =
6571 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6572 data->rx.is_leading_rss =
6573 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6574 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6575
6576 /* Tx data */
6577 data->tx.enforce_security_flg = 0; /* VF specific */
6578 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6579 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6580 data->tx.mtu = 0; /* VF specific */
6581 data->tx.tx_bd_page_base.lo =
6582 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6583 data->tx.tx_bd_page_base.hi =
6584 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6585
6586 /* flow control data */
6587 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6588 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6589 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6590 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6591 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6592 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6593 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6594
6595 data->fc.safc_group_num = params->txq_params.cos;
6596 data->fc.safc_group_en_flg =
6597 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
ec6ba945
VZ		 6598 data->fc.traffic_type =
6599 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6600 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
523224a3
DK		 6601}
6602
6603static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6604{
6605 /* ustorm cxt validation */
6606 cxt->ustorm_ag_context.cdu_usage =
6607 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6608 ETH_CONNECTION_TYPE);
6609 /* xcontext validation */
6610 cxt->xstorm_ag_context.cdu_reserved =
6611 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6612 ETH_CONNECTION_TYPE);
6613}
6614
8d96286a 6615static int bnx2x_setup_fw_client(struct bnx2x *bp,
6616 struct bnx2x_client_init_params *params,
6617 u8 activate,
6618 struct client_init_ramrod_data *data,
6619 dma_addr_t data_mapping)
523224a3
DK		 6620{
6621 u16 hc_usec;
6622 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6623 int ramrod_flags = 0, rc;
6624
6625 /* HC and context validation values */
6626 hc_usec = params->txq_params.hc_rate ?
6627 1000000 / params->txq_params.hc_rate : 0;
6628 bnx2x_update_coalesce_sb_index(bp,
6629 params->txq_params.fw_sb_id,
6630 params->txq_params.sb_cq_index,
6631 !(params->txq_params.flags & QUEUE_FLG_HC),
6632 hc_usec);
6633
6634 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6635
6636 hc_usec = params->rxq_params.hc_rate ?
6637 1000000 / params->rxq_params.hc_rate : 0;
6638 bnx2x_update_coalesce_sb_index(bp,
6639 params->rxq_params.fw_sb_id,
6640 params->rxq_params.sb_cq_index,
6641 !(params->rxq_params.flags & QUEUE_FLG_HC),
6642 hc_usec);
6643
6644 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6645 params->rxq_params.cid);
6646
6647 /* zero stats */
6648 if (params->txq_params.flags & QUEUE_FLG_STATS)
6649 storm_memset_xstats_zero(bp, BP_PORT(bp),
6650 params->txq_params.stat_id);
6651
6652 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6653 storm_memset_ustats_zero(bp, BP_PORT(bp),
6654 params->rxq_params.stat_id);
6655 storm_memset_tstats_zero(bp, BP_PORT(bp),
6656 params->rxq_params.stat_id);
6657 }
6658
6659 /* Fill the ramrod data */
6660 bnx2x_fill_cl_init_data(bp, params, activate, data);
6661
6662 /* SETUP ramrod.
6663 *
6664 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6665 * barrier except from mmiowb() is needed to impose a
6666 * proper ordering of memory operations.
6667 */
6668 mmiowb();
a2fbb9ea 6669
a2fbb9ea 6670
523224a3
DK		 6671 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6672 U64_HI(data_mapping), U64_LO(data_mapping), 0);
a2fbb9ea 6673
34f80b04 6674 /* Wait for completion */
523224a3
DK		 6675 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6676 params->ramrod_params.index,
6677 params->ramrod_params.pstate,
6678 ramrod_flags);
34f80b04 6679 return rc;
a2fbb9ea
ET		 6680}
6681
d6214d7a
DK		 6682/**
6683 * Configure interrupt mode according to current configuration.
6684 * In case of MSI-X it will also try to enable MSI-X.
6685 *
6686 * @param bp
6687 *
6688 * @return int
6689 */
6690static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6691{
d6214d7a 6692 int rc = 0;
ca00392c 6693
d6214d7a
DK		 6694 switch (bp->int_mode) {
6695 case INT_MODE_MSI:
6696 bnx2x_enable_msi(bp);
6697 /* falling through... */
6698 case INT_MODE_INTx:
ec6ba945 6699 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a 6700 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6701 break;
d6214d7a
DK		 6702 default:
6703 /* Set number of queues according to bp->multi_mode value */
6704 bnx2x_set_num_queues(bp);
ca00392c 6705
d6214d7a
DK		 6706 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6707 bp->num_queues);
ca00392c 6708
d6214d7a
DK		 6709 /* if we can't use MSI-X we only need one fp,
6710 * so try to enable MSI-X with the requested number of fp's
6711 * and fallback to MSI or legacy INTx with one fp
6712 */
6713 rc = bnx2x_enable_msix(bp);
6714 if (rc) {
6715 /* failed to enable MSI-X */
6716 if (bp->multi_mode)
6717 DP(NETIF_MSG_IFUP,
6718 "Multi requested but failed to "
6719 "enable MSI-X (%d), "
6720 "set number of queues to %d\n",
6721 bp->num_queues,
ec6ba945
VZ		 6722 1 + NONE_ETH_CONTEXT_USE);
6723 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a
DK		 6724
6725 if (!(bp->flags & DISABLE_MSI_FLAG))
6726 bnx2x_enable_msi(bp);
6727 }
ca00392c 6728
9f6c9258
DK		 6729 break;
6730 }
d6214d7a
DK		 6731
6732 return rc;
a2fbb9ea
ET		 6733}
6734
c2bff63f
DK		 6735/* must be called prioir to any HW initializations */
6736static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6737{
6738 return L2_ILT_LINES(bp);
6739}
6740
523224a3
DK		 6741void bnx2x_ilt_set_info(struct bnx2x *bp)
6742{
6743 struct ilt_client_info *ilt_client;
6744 struct bnx2x_ilt *ilt = BP_ILT(bp);
6745 u16 line = 0;
6746
6747 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6748 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6749
6750 /* CDU */
6751 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6752 ilt_client->client_num = ILT_CLIENT_CDU;
6753 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6754 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6755 ilt_client->start = line;
6756 line += L2_ILT_LINES(bp);
6757#ifdef BCM_CNIC
6758 line += CNIC_ILT_LINES;
6759#endif
6760 ilt_client->end = line - 1;
6761
6762 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6763 "flags 0x%x, hw psz %d\n",
6764 ilt_client->start,
6765 ilt_client->end,
6766 ilt_client->page_size,
6767 ilt_client->flags,
6768 ilog2(ilt_client->page_size >> 12));
6769
6770 /* QM */
6771 if (QM_INIT(bp->qm_cid_count)) {
6772 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6773 ilt_client->client_num = ILT_CLIENT_QM;
6774 ilt_client->page_size = QM_ILT_PAGE_SZ;
6775 ilt_client->flags = 0;
6776 ilt_client->start = line;
6777
6778 /* 4 bytes for each cid */
6779 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6780 QM_ILT_PAGE_SZ);
6781
6782 ilt_client->end = line - 1;
6783
6784 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6785 "flags 0x%x, hw psz %d\n",
6786 ilt_client->start,
6787 ilt_client->end,
6788 ilt_client->page_size,
6789 ilt_client->flags,
6790 ilog2(ilt_client->page_size >> 12));
6791
6792 }
6793 /* SRC */
6794 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6795#ifdef BCM_CNIC
6796 ilt_client->client_num = ILT_CLIENT_SRC;
6797 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6798 ilt_client->flags = 0;
6799 ilt_client->start = line;
6800 line += SRC_ILT_LINES;
6801 ilt_client->end = line - 1;
6802
6803 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6804 "flags 0x%x, hw psz %d\n",
6805 ilt_client->start,
6806 ilt_client->end,
6807 ilt_client->page_size,
6808 ilt_client->flags,
6809 ilog2(ilt_client->page_size >> 12));
6810
6811#else
6812 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6813#endif
9f6c9258 6814
523224a3
DK		 6815 /* TM */
6816 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6817#ifdef BCM_CNIC
6818 ilt_client->client_num = ILT_CLIENT_TM;
6819 ilt_client->page_size = TM_ILT_PAGE_SZ;
6820 ilt_client->flags = 0;
6821 ilt_client->start = line;
6822 line += TM_ILT_LINES;
6823 ilt_client->end = line - 1;
6824
6825 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6826 "flags 0x%x, hw psz %d\n",
6827 ilt_client->start,
6828 ilt_client->end,
6829 ilt_client->page_size,
6830 ilt_client->flags,
6831 ilog2(ilt_client->page_size >> 12));
9f6c9258 6832
523224a3
DK		 6833#else
6834 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6835#endif
6836}
f85582f8 6837
523224a3
DK		 6838int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6839 int is_leading)
a2fbb9ea 6840{
523224a3 6841 struct bnx2x_client_init_params params = { {0} };
a2fbb9ea
ET		 6842 int rc;
6843
ec6ba945
VZ		 6844 /* reset IGU state skip FCoE L2 queue */
6845 if (!IS_FCOE_FP(fp))
6846 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 6847 IGU_INT_ENABLE, 0);
a2fbb9ea 6848
523224a3
DK		 6849 params.ramrod_params.pstate = &fp->state;
6850 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6851 params.ramrod_params.index = fp->index;
6852 params.ramrod_params.cid = fp->cid;
a2fbb9ea 6853
ec6ba945
VZ		 6854#ifdef BCM_CNIC
6855 if (IS_FCOE_FP(fp))
6856 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6857
6858#endif
6859
523224a3
DK		 6860 if (is_leading)
6861 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
a2fbb9ea 6862
523224a3
DK		 6863 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6864
6865 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6866
6867 rc = bnx2x_setup_fw_client(bp, &params, 1,
6868 bnx2x_sp(bp, client_init_data),
6869 bnx2x_sp_mapping(bp, client_init_data));
34f80b04 6870 return rc;
a2fbb9ea
ET		 6871}
6872
8d96286a 6873static int bnx2x_stop_fw_client(struct bnx2x *bp,
6874 struct bnx2x_client_ramrod_params *p)
a2fbb9ea 6875{
34f80b04 6876 int rc;
a2fbb9ea 6877
523224a3 6878 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
a2fbb9ea 6879
523224a3
DK		 6880 /* halt the connection */
6881 *p->pstate = BNX2X_FP_STATE_HALTING;
6882 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6883 p->cl_id, 0);
a2fbb9ea 6884
34f80b04 6885 /* Wait for completion */
523224a3
DK		 6886 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6887 p->pstate, poll_flag);
34f80b04 6888 if (rc) /* timeout */
da5a662a 6889 return rc;
a2fbb9ea 6890
523224a3
DK		 6891 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6892 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6893 p->cl_id, 0);
6894 /* Wait for completion */
6895 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6896 p->pstate, poll_flag);
6897 if (rc) /* timeout */
6898 return rc;
a2fbb9ea 6899
a2fbb9ea 6900
523224a3
DK		 6901 /* delete cfc entry */
6902 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
da5a662a 6903
523224a3
DK		 6904 /* Wait for completion */
6905 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6906 p->pstate, WAIT_RAMROD_COMMON);
da5a662a 6907 return rc;
a2fbb9ea
ET		 6908}
6909
523224a3
DK		 6910static int bnx2x_stop_client(struct bnx2x *bp, int index)
6911{
6912 struct bnx2x_client_ramrod_params client_stop = {0};
6913 struct bnx2x_fastpath *fp = &bp->fp[index];
6914
6915 client_stop.index = index;
6916 client_stop.cid = fp->cid;
6917 client_stop.cl_id = fp->cl_id;
6918 client_stop.pstate = &(fp->state);
6919 client_stop.poll = 0;
6920
6921 return bnx2x_stop_fw_client(bp, &client_stop);
6922}
6923
6924
34f80b04
EG		 6925static void bnx2x_reset_func(struct bnx2x *bp)
6926{
6927 int port = BP_PORT(bp);
6928 int func = BP_FUNC(bp);
f2e0899f 6929 int i;
523224a3 6930 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
f2e0899f
DK		 6931 (CHIP_IS_E2(bp) ?
6932 offsetof(struct hc_status_block_data_e2, common) :
6933 offsetof(struct hc_status_block_data_e1x, common));
523224a3
DK		 6934 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6935 int pfid_offset = offsetof(struct pci_entity, pf_id);
6936
6937 /* Disable the function in the FW */
6938 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6939 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6940 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6941 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6942
6943 /* FP SBs */
ec6ba945 6944 for_each_eth_queue(bp, i) {
523224a3
DK		 6945 struct bnx2x_fastpath *fp = &bp->fp[i];
6946 REG_WR8(bp,
6947 BAR_CSTRORM_INTMEM +
6948 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6949 + pfunc_offset_fp + pfid_offset,
6950 HC_FUNCTION_DISABLED);
6951 }
6952
6953 /* SP SB */
6954 REG_WR8(bp,
6955 BAR_CSTRORM_INTMEM +
6956 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6957 pfunc_offset_sp + pfid_offset,
6958 HC_FUNCTION_DISABLED);
6959
6960
6961 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6962 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6963 0);
34f80b04
EG		 6964
6965 /* Configure IGU */
f2e0899f
DK		 6966 if (bp->common.int_block == INT_BLOCK_HC) {
6967 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6968 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6969 } else {
6970 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6971 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6972 }
34f80b04 6973
37b091ba
MC		 6974#ifdef BCM_CNIC
6975 /* Disable Timer scan */
6976 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6977 /*
6978 * Wait for at least 10ms and up to 2 second for the timers scan to
6979 * complete
6980 */
6981 for (i = 0; i < 200; i++) {
6982 msleep(10);
6983 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6984 break;
6985 }
6986#endif
34f80b04 6987 /* Clear ILT */
f2e0899f
DK		 6988 bnx2x_clear_func_ilt(bp, func);
6989
6990 /* Timers workaround bug for E2: if this is vnic-3,
6991 * we need to set the entire ilt range for this timers.
6992 */
6993 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6994 struct ilt_client_info ilt_cli;
6995 /* use dummy TM client */
6996 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6997 ilt_cli.start = 0;
6998 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6999 ilt_cli.client_num = ILT_CLIENT_TM;
7000
7001 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7002 }
7003
7004 /* this assumes that reset_port() called before reset_func()*/
7005 if (CHIP_IS_E2(bp))
7006 bnx2x_pf_disable(bp);
523224a3
DK		 7007
7008 bp->dmae_ready = 0;
34f80b04
EG		 7009}
7010
7011static void bnx2x_reset_port(struct bnx2x *bp)
7012{
7013 int port = BP_PORT(bp);
7014 u32 val;
7015
7016 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7017
7018 /* Do not rcv packets to BRB */
7019 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7020 /* Do not direct rcv packets that are not for MCP to the BRB */
7021 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7022 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7023
7024 /* Configure AEU */
7025 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7026
7027 msleep(100);
7028 /* Check for BRB port occupancy */
7029 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7030 if (val)
7031 DP(NETIF_MSG_IFDOWN,
33471629 7032 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7033
7034 /* TODO: Close Doorbell port? */
7035}
7036
34f80b04
EG		 7037static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7038{
7039 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
f2e0899f 7040 BP_ABS_FUNC(bp), reset_code);
34f80b04
EG		 7041
7042 switch (reset_code) {
7043 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7044 bnx2x_reset_port(bp);
7045 bnx2x_reset_func(bp);
7046 bnx2x_reset_common(bp);
7047 break;
7048
7049 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7050 bnx2x_reset_port(bp);
7051 bnx2x_reset_func(bp);
7052 break;
7053
7054 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7055 bnx2x_reset_func(bp);
7056 break;
49d66772 7057
34f80b04
EG		 7058 default:
7059 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7060 break;
7061 }
7062}
7063
ec6ba945
VZ		 7064#ifdef BCM_CNIC
7065static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7066{
7067 if (bp->flags & FCOE_MACS_SET) {
7068 if (!IS_MF_SD(bp))
7069 bnx2x_set_fip_eth_mac_addr(bp, 0);
7070
7071 bnx2x_set_all_enode_macs(bp, 0);
7072
7073 bp->flags &= ~FCOE_MACS_SET;
7074 }
7075}
7076#endif
7077
9f6c9258 7078void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
a2fbb9ea 7079{
da5a662a 7080 int port = BP_PORT(bp);
a2fbb9ea 7081 u32 reset_code = 0;
da5a662a 7082 int i, cnt, rc;
a2fbb9ea 7083
555f6c78 7084 /* Wait until tx fastpath tasks complete */
ec6ba945 7085 for_each_tx_queue(bp, i) {
228241eb
ET		 7086 struct bnx2x_fastpath *fp = &bp->fp[i];
7087
34f80b04 7088 cnt = 1000;
e8b5fc51 7089 while (bnx2x_has_tx_work_unload(fp)) {
da5a662a 7090
34f80b04
EG		 7091 if (!cnt) {
7092 BNX2X_ERR("timeout waiting for queue[%d]\n",
7093 i);
7094#ifdef BNX2X_STOP_ON_ERROR
7095 bnx2x_panic();
7096 return -EBUSY;
7097#else
7098 break;
7099#endif
7100 }
7101 cnt--;
da5a662a 7102 msleep(1);
34f80b04 7103 }
228241eb 7104 }
da5a662a
VZ		 7105 /* Give HW time to discard old tx messages */
7106 msleep(1);
a2fbb9ea 7107
3101c2bc 7108 if (CHIP_IS_E1(bp)) {
523224a3
DK		 7109 /* invalidate mc list,
7110 * wait and poll (interrupts are off)
7111 */
7112 bnx2x_invlidate_e1_mc_list(bp);
7113 bnx2x_set_eth_mac(bp, 0);
3101c2bc 7114
523224a3 7115 } else {
65abd74d
YG		 7116 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7117
523224a3 7118 bnx2x_set_eth_mac(bp, 0);
3101c2bc
YG		 7119
7120 for (i = 0; i < MC_HASH_SIZE; i++)
7121 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
7122 }
523224a3 7123
993ac7b5 7124#ifdef BCM_CNIC
ec6ba945 7125 bnx2x_del_fcoe_eth_macs(bp);
993ac7b5 7126#endif
3101c2bc 7127
65abd74d
YG		 7128 if (unload_mode == UNLOAD_NORMAL)
7129 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7130
7d0446c2 7131 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7132 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7133
7d0446c2 7134 else if (bp->wol) {
65abd74d
YG		 7135 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7136 u8 *mac_addr = bp->dev->dev_addr;
7137 u32 val;
7138 /* The mac address is written to entries 1-4 to
7139 preserve entry 0 which is used by the PMF */
7140 u8 entry = (BP_E1HVN(bp) + 1)*8;
7141
7142 val = (mac_addr[0] << 8) | mac_addr[1];
7143 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7144
7145 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7146 (mac_addr[4] << 8) | mac_addr[5];
7147 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7148
7149 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7150
7151 } else
7152 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7153
34f80b04
EG		 7154 /* Close multi and leading connections
7155 Completions for ramrods are collected in a synchronous way */
523224a3
DK		 7156 for_each_queue(bp, i)
7157
7158 if (bnx2x_stop_client(bp, i))
7159#ifdef BNX2X_STOP_ON_ERROR
7160 return;
7161#else
228241eb 7162 goto unload_error;
523224a3 7163#endif
a2fbb9ea 7164
523224a3 7165 rc = bnx2x_func_stop(bp);
da5a662a 7166 if (rc) {
523224a3 7167 BNX2X_ERR("Function stop failed!\n");
da5a662a 7168#ifdef BNX2X_STOP_ON_ERROR
523224a3 7169 return;
da5a662a
VZ		 7170#else
7171 goto unload_error;
34f80b04 7172#endif
228241eb 7173 }
523224a3 7174#ifndef BNX2X_STOP_ON_ERROR
228241eb 7175unload_error:
523224a3 7176#endif
34f80b04 7177 if (!BP_NOMCP(bp))
a22f0788 7178 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04 7179 else {
f2e0899f
DK		 7180 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7181 "%d, %d, %d\n", BP_PATH(bp),
7182 load_count[BP_PATH(bp)][0],
7183 load_count[BP_PATH(bp)][1],
7184 load_count[BP_PATH(bp)][2]);
7185 load_count[BP_PATH(bp)][0]--;
7186 load_count[BP_PATH(bp)][1 + port]--;
7187 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7188 "%d, %d, %d\n", BP_PATH(bp),
7189 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7190 load_count[BP_PATH(bp)][2]);
7191 if (load_count[BP_PATH(bp)][0] == 0)
34f80b04 7192 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
f2e0899f 7193 else if (load_count[BP_PATH(bp)][1 + port] == 0)
34f80b04
EG		 7194 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7195 else
7196 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7197 }
a2fbb9ea 7198
34f80b04
EG		 7199 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7200 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7201 bnx2x__link_reset(bp);
a2fbb9ea 7202
523224a3
DK		 7203 /* Disable HW interrupts, NAPI */
7204 bnx2x_netif_stop(bp, 1);
7205
7206 /* Release IRQs */
d6214d7a 7207 bnx2x_free_irq(bp);
523224a3 7208
a2fbb9ea 7209 /* Reset the chip */
228241eb 7210 bnx2x_reset_chip(bp, reset_code);
a2fbb9ea
ET		 7211
7212 /* Report UNLOAD_DONE to MCP */
34f80b04 7213 if (!BP_NOMCP(bp))
a22f0788 7214 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
356e2385 7215
72fd0718
VZ		 7216}
7217
9f6c9258 7218void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7219{
7220 u32 val;
7221
7222 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7223
7224 if (CHIP_IS_E1(bp)) {
7225 int port = BP_PORT(bp);
7226 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7227 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7228
7229 val = REG_RD(bp, addr);
7230 val &= ~(0x300);
7231 REG_WR(bp, addr, val);
7232 } else if (CHIP_IS_E1H(bp)) {
7233 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7234 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7235 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7236 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7237 }
7238}
7239
72fd0718
VZ		 7240/* Close gates #2, #3 and #4: */
7241static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7242{
7243 u32 val, addr;
7244
7245 /* Gates #2 and #4a are closed/opened for "not E1" only */
7246 if (!CHIP_IS_E1(bp)) {
7247 /* #4 */
7248 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7249 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7250 close ? (val | 0x1) : (val & (~(u32)1)));
7251 /* #2 */
7252 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7253 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7254 close ? (val | 0x1) : (val & (~(u32)1)));
7255 }
7256
7257 /* #3 */
7258 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7259 val = REG_RD(bp, addr);
7260 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7261
7262 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7263 close ? "closing" : "opening");
7264 mmiowb();
7265}
7266
7267#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7268
7269static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7270{
7271 /* Do some magic... */
7272 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7273 *magic_val = val & SHARED_MF_CLP_MAGIC;
7274 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7275}
7276
7277/* Restore the value of the `magic' bit.
7278 *
7279 * @param pdev Device handle.
7280 * @param magic_val Old value of the `magic' bit.
7281 */
7282static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7283{
7284 /* Restore the `magic' bit value... */
72fd0718
VZ		 7285 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7286 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7287 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7288}
7289
f85582f8
DK		 7290/**
7291 * Prepares for MCP reset: takes care of CLP configurations.
72fd0718
VZ		 7292 *
7293 * @param bp
7294 * @param magic_val Old value of 'magic' bit.
7295 */
7296static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7297{
7298 u32 shmem;
7299 u32 validity_offset;
7300
7301 DP(NETIF_MSG_HW, "Starting\n");
7302
7303 /* Set `magic' bit in order to save MF config */
7304 if (!CHIP_IS_E1(bp))
7305 bnx2x_clp_reset_prep(bp, magic_val);
7306
7307 /* Get shmem offset */
7308 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7309 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7310
7311 /* Clear validity map flags */
7312 if (shmem > 0)
7313 REG_WR(bp, shmem + validity_offset, 0);
7314}
7315
7316#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7317#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7318
7319/* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
7320 * depending on the HW type.
7321 *
7322 * @param bp
7323 */
7324static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7325{
7326 /* special handling for emulation and FPGA,
7327 wait 10 times longer */
7328 if (CHIP_REV_IS_SLOW(bp))
7329 msleep(MCP_ONE_TIMEOUT*10);
7330 else
7331 msleep(MCP_ONE_TIMEOUT);
7332}
7333
7334static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7335{
7336 u32 shmem, cnt, validity_offset, val;
7337 int rc = 0;
7338
7339 msleep(100);
7340
7341 /* Get shmem offset */
7342 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7343 if (shmem == 0) {
7344 BNX2X_ERR("Shmem 0 return failure\n");
7345 rc = -ENOTTY;
7346 goto exit_lbl;
7347 }
7348
7349 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7350
7351 /* Wait for MCP to come up */
7352 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7353 /* TBD: its best to check validity map of last port.
7354 * currently checks on port 0.
7355 */
7356 val = REG_RD(bp, shmem + validity_offset);
7357 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7358 shmem + validity_offset, val);
7359
7360 /* check that shared memory is valid. */
7361 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7362 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7363 break;
7364
7365 bnx2x_mcp_wait_one(bp);
7366 }
7367
7368 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7369
7370 /* Check that shared memory is valid. This indicates that MCP is up. */
7371 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7372 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7373 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7374 rc = -ENOTTY;
7375 goto exit_lbl;
7376 }
7377
7378exit_lbl:
7379 /* Restore the `magic' bit value */
7380 if (!CHIP_IS_E1(bp))
7381 bnx2x_clp_reset_done(bp, magic_val);
7382
7383 return rc;
7384}
7385
7386static void bnx2x_pxp_prep(struct bnx2x *bp)
7387{
7388 if (!CHIP_IS_E1(bp)) {
7389 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7390 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7391 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7392 mmiowb();
7393 }
7394}
7395
7396/*
7397 * Reset the whole chip except for:
7398 * - PCIE core
7399 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7400 * one reset bit)
7401 * - IGU
7402 * - MISC (including AEU)
7403 * - GRC
7404 * - RBCN, RBCP
7405 */
7406static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7407{
7408 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7409
7410 not_reset_mask1 =
7411 MISC_REGISTERS_RESET_REG_1_RST_HC |
7412 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7413 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7414
7415 not_reset_mask2 =
7416 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7417 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7418 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7419 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7420 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7421 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7422 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7423 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7424
7425 reset_mask1 = 0xffffffff;
7426
7427 if (CHIP_IS_E1(bp))
7428 reset_mask2 = 0xffff;
7429 else
7430 reset_mask2 = 0x1ffff;
7431
7432 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7433 reset_mask1 & (~not_reset_mask1));
7434 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7435 reset_mask2 & (~not_reset_mask2));
7436
7437 barrier();
7438 mmiowb();
7439
7440 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7441 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7442 mmiowb();
7443}
7444
7445static int bnx2x_process_kill(struct bnx2x *bp)
7446{
7447 int cnt = 1000;
7448 u32 val = 0;
7449 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7450
7451
7452 /* Empty the Tetris buffer, wait for 1s */
7453 do {
7454 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7455 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7456 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7457 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7458 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7459 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7460 ((port_is_idle_0 & 0x1) == 0x1) &&
7461 ((port_is_idle_1 & 0x1) == 0x1) &&
7462 (pgl_exp_rom2 == 0xffffffff))
7463 break;
7464 msleep(1);
7465 } while (cnt-- > 0);
7466
7467 if (cnt <= 0) {
7468 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7469 " are still"
7470 " outstanding read requests after 1s!\n");
7471 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7472 " port_is_idle_0=0x%08x,"
7473 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7474 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7475 pgl_exp_rom2);
7476 return -EAGAIN;
7477 }
7478
7479 barrier();
7480
7481 /* Close gates #2, #3 and #4 */
7482 bnx2x_set_234_gates(bp, true);
7483
7484 /* TBD: Indicate that "process kill" is in progress to MCP */
7485
7486 /* Clear "unprepared" bit */
7487 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7488 barrier();
7489
7490 /* Make sure all is written to the chip before the reset */
7491 mmiowb();
7492
7493 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7494 * PSWHST, GRC and PSWRD Tetris buffer.
7495 */
7496 msleep(1);
7497
7498 /* Prepare to chip reset: */
7499 /* MCP */
7500 bnx2x_reset_mcp_prep(bp, &val);
7501
7502 /* PXP */
7503 bnx2x_pxp_prep(bp);
7504 barrier();
7505
7506 /* reset the chip */
7507 bnx2x_process_kill_chip_reset(bp);
7508 barrier();
7509
7510 /* Recover after reset: */
7511 /* MCP */
7512 if (bnx2x_reset_mcp_comp(bp, val))
7513 return -EAGAIN;
7514
7515 /* PXP */
7516 bnx2x_pxp_prep(bp);
7517
7518 /* Open the gates #2, #3 and #4 */
7519 bnx2x_set_234_gates(bp, false);
7520
7521 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7522 * reset state, re-enable attentions. */
7523
a2fbb9ea
ET		 7524 return 0;
7525}
7526
72fd0718
VZ		 7527static int bnx2x_leader_reset(struct bnx2x *bp)
7528{
7529 int rc = 0;
7530 /* Try to recover after the failure */
7531 if (bnx2x_process_kill(bp)) {
7532 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7533 bp->dev->name);
7534 rc = -EAGAIN;
7535 goto exit_leader_reset;
7536 }
7537
7538 /* Clear "reset is in progress" bit and update the driver state */
7539 bnx2x_set_reset_done(bp);
7540 bp->recovery_state = BNX2X_RECOVERY_DONE;
7541
7542exit_leader_reset:
7543 bp->is_leader = 0;
7544 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7545 smp_wmb();
7546 return rc;
7547}
7548
72fd0718
VZ		 7549/* Assumption: runs under rtnl lock. This together with the fact
7550 * that it's called only from bnx2x_reset_task() ensure that it
7551 * will never be called when netif_running(bp->dev) is false.
7552 */
7553static void bnx2x_parity_recover(struct bnx2x *bp)
7554{
7555 DP(NETIF_MSG_HW, "Handling parity\n");
7556 while (1) {
7557 switch (bp->recovery_state) {
7558 case BNX2X_RECOVERY_INIT:
7559 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7560 /* Try to get a LEADER_LOCK HW lock */
7561 if (bnx2x_trylock_hw_lock(bp,
7562 HW_LOCK_RESOURCE_RESERVED_08))
7563 bp->is_leader = 1;
7564
7565 /* Stop the driver */
7566 /* If interface has been removed - break */
7567 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7568 return;
7569
7570 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7571 /* Ensure "is_leader" and "recovery_state"
7572 * update values are seen on other CPUs
7573 */
7574 smp_wmb();
7575 break;
7576
7577 case BNX2X_RECOVERY_WAIT:
7578 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7579 if (bp->is_leader) {
7580 u32 load_counter = bnx2x_get_load_cnt(bp);
7581 if (load_counter) {
7582 /* Wait until all other functions get
7583 * down.
7584 */
7585 schedule_delayed_work(&bp->reset_task,
7586 HZ/10);
7587 return;
7588 } else {
7589 /* If all other functions got down -
7590 * try to bring the chip back to
7591 * normal. In any case it's an exit
7592 * point for a leader.
7593 */
7594 if (bnx2x_leader_reset(bp) ||
7595 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7596 printk(KERN_ERR"%s: Recovery "
7597 "has failed. Power cycle is "
7598 "needed.\n", bp->dev->name);
7599 /* Disconnect this device */
7600 netif_device_detach(bp->dev);
7601 /* Block ifup for all function
7602 * of this ASIC until
7603 * "process kill" or power
7604 * cycle.
7605 */
7606 bnx2x_set_reset_in_progress(bp);
7607 /* Shut down the power */
7608 bnx2x_set_power_state(bp,
7609 PCI_D3hot);
7610 return;
7611 }
7612
7613 return;
7614 }
7615 } else { /* non-leader */
7616 if (!bnx2x_reset_is_done(bp)) {
7617 /* Try to get a LEADER_LOCK HW lock as
7618 * long as a former leader may have
7619 * been unloaded by the user or
7620 * released a leadership by another
7621 * reason.
7622 */
7623 if (bnx2x_trylock_hw_lock(bp,
7624 HW_LOCK_RESOURCE_RESERVED_08)) {
7625 /* I'm a leader now! Restart a
7626 * switch case.
7627 */
7628 bp->is_leader = 1;
7629 break;
7630 }
7631
7632 schedule_delayed_work(&bp->reset_task,
7633 HZ/10);
7634 return;
7635
7636 } else { /* A leader has completed
7637 * the "process kill". It's an exit
7638 * point for a non-leader.
7639 */
7640 bnx2x_nic_load(bp, LOAD_NORMAL);
7641 bp->recovery_state =
7642 BNX2X_RECOVERY_DONE;
7643 smp_wmb();
7644 return;
7645 }
7646 }
7647 default:
7648 return;
7649 }
7650 }
7651}
7652
7653/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7654 * scheduled on a general queue in order to prevent a dead lock.
7655 */
34f80b04
EG		 7656static void bnx2x_reset_task(struct work_struct *work)
7657{
72fd0718 7658 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
34f80b04
EG		 7659
7660#ifdef BNX2X_STOP_ON_ERROR
7661 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7662 " so reset not done to allow debug dump,\n"
72fd0718 7663 KERN_ERR " you will need to reboot when done\n");
34f80b04
EG		 7664 return;
7665#endif
7666
7667 rtnl_lock();
7668
7669 if (!netif_running(bp->dev))
7670 goto reset_task_exit;
7671
72fd0718
VZ		 7672 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7673 bnx2x_parity_recover(bp);
7674 else {
7675 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7676 bnx2x_nic_load(bp, LOAD_NORMAL);
7677 }
34f80b04
EG		 7678
7679reset_task_exit:
7680 rtnl_unlock();
7681}
7682
a2fbb9ea
ET		 7683/* end of nic load/unload */
7684
a2fbb9ea
ET		 7685/*
7686 * Init service functions
7687 */
7688
8d96286a 7689static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 7690{
7691 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7692 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7693 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 7694}
7695
f2e0899f 7696static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 7697{
f2e0899f 7698 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 7699
7700 /* Flush all outstanding writes */
7701 mmiowb();
7702
7703 /* Pretend to be function 0 */
7704 REG_WR(bp, reg, 0);
f2e0899f 7705 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 7706
7707 /* From now we are in the "like-E1" mode */
7708 bnx2x_int_disable(bp);
7709
7710 /* Flush all outstanding writes */
7711 mmiowb();
7712
f2e0899f
DK		 7713 /* Restore the original function */
7714 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7715 REG_RD(bp, reg);
f1ef27ef
EG		 7716}
7717
f2e0899f 7718static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 7719{
f2e0899f 7720 if (CHIP_IS_E1(bp))
f1ef27ef 7721 bnx2x_int_disable(bp);
f2e0899f
DK		 7722 else
7723 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 7724}
7725
34f80b04
EG		 7726static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7727{
7728 u32 val;
7729
7730 /* Check if there is any driver already loaded */
7731 val = REG_RD(bp, MISC_REG_UNPREPARED);
7732 if (val == 0x1) {
7733 /* Check if it is the UNDI driver
7734 * UNDI driver initializes CID offset for normal bell to 0x7
7735 */
4a37fb66 7736 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7737 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7738 if (val == 0x7) {
7739 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 7740 /* save our pf_num */
7741 int orig_pf_num = bp->pf_num;
da5a662a
VZ		 7742 u32 swap_en;
7743 u32 swap_val;
34f80b04 7744
b4661739
EG		 7745 /* clear the UNDI indication */
7746 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7747
34f80b04
EG		 7748 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7749
7750 /* try unload UNDI on port 0 */
f2e0899f 7751 bp->pf_num = 0;
da5a662a 7752 bp->fw_seq =
f2e0899f 7753 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7754 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 7755 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7756
7757 /* if UNDI is loaded on the other port */
7758 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7759
da5a662a 7760 /* send "DONE" for previous unload */
a22f0788
YR		 7761 bnx2x_fw_command(bp,
7762 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7763
7764 /* unload UNDI on port 1 */
f2e0899f 7765 bp->pf_num = 1;
da5a662a 7766 bp->fw_seq =
f2e0899f 7767 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 7768 DRV_MSG_SEQ_NUMBER_MASK);
7769 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7770
a22f0788 7771 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7772 }
7773
b4661739
EG		 7774 /* now it's safe to release the lock */
7775 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7776
f2e0899f 7777 bnx2x_undi_int_disable(bp);
da5a662a
VZ		 7778
7779 /* close input traffic and wait for it */
7780 /* Do not rcv packets to BRB */
7781 REG_WR(bp,
7782 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7783 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7784 /* Do not direct rcv packets that are not for MCP to
7785 * the BRB */
7786 REG_WR(bp,
7787 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7788 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7789 /* clear AEU */
7790 REG_WR(bp,
7791 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7792 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7793 msleep(10);
7794
7795 /* save NIG port swap info */
7796 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7797 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 7798 /* reset device */
7799 REG_WR(bp,
7800 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 7801 0xd3ffffff);
34f80b04
EG		 7802 REG_WR(bp,
7803 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7804 0x1403);
da5a662a
VZ		 7805 /* take the NIG out of reset and restore swap values */
7806 REG_WR(bp,
7807 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7808 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7809 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7810 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7811
7812 /* send unload done to the MCP */
a22f0788 7813 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7814
7815 /* restore our func and fw_seq */
f2e0899f 7816 bp->pf_num = orig_pf_num;
da5a662a 7817 bp->fw_seq =
f2e0899f 7818 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7819 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 7820 } else
7821 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7822 }
7823}
7824
7825static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7826{
7827 u32 val, val2, val3, val4, id;
72ce58c3 7828 u16 pmc;
34f80b04
EG		 7829
7830 /* Get the chip revision id and number. */
7831 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7832 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7833 id = ((val & 0xffff) << 16);
7834 val = REG_RD(bp, MISC_REG_CHIP_REV);
7835 id |= ((val & 0xf) << 12);
7836 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7837 id |= ((val & 0xff) << 4);
5a40e08e 7838 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 7839 id |= (val & 0xf);
7840 bp->common.chip_id = id;
523224a3
DK		 7841
7842 /* Set doorbell size */
7843 bp->db_size = (1 << BNX2X_DB_SHIFT);
7844
f2e0899f
DK		 7845 if (CHIP_IS_E2(bp)) {
7846 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7847 if ((val & 1) == 0)
7848 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7849 else
7850 val = (val >> 1) & 1;
7851 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7852 "2_PORT_MODE");
7853 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7854 CHIP_2_PORT_MODE;
7855
7856 if (CHIP_MODE_IS_4_PORT(bp))
7857 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7858 else
7859 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7860 } else {
7861 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7862 bp->pfid = bp->pf_num; /* 0..7 */
7863 }
7864
523224a3
DK		 7865 /*
7866 * set base FW non-default (fast path) status block id, this value is
7867 * used to initialize the fw_sb_id saved on the fp/queue structure to
7868 * determine the id used by the FW.
7869 */
f2e0899f
DK		 7870 if (CHIP_IS_E1x(bp))
7871 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7872 else /* E2 */
7873 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7874
7875 bp->link_params.chip_id = bp->common.chip_id;
7876 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 7877
1c06328c
EG		 7878 val = (REG_RD(bp, 0x2874) & 0x55);
7879 if ((bp->common.chip_id & 0x1) ||
7880 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7881 bp->flags |= ONE_PORT_FLAG;
7882 BNX2X_DEV_INFO("single port device\n");
7883 }
7884
34f80b04
EG		 7885 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7886 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7887 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7888 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7889 bp->common.flash_size, bp->common.flash_size);
7890
7891 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
f2e0899f
DK		 7892 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7893 MISC_REG_GENERIC_CR_1 :
7894 MISC_REG_GENERIC_CR_0));
34f80b04 7895 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 7896 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 7897 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7898 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 7899
f2e0899f 7900 if (!bp->common.shmem_base) {
34f80b04
EG		 7901 BNX2X_DEV_INFO("MCP not active\n");
7902 bp->flags |= NO_MCP_FLAG;
7903 return;
7904 }
7905
7906 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7907 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7908 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
f2e0899f 7909 BNX2X_ERR("BAD MCP validity signature\n");
34f80b04
EG		 7910
7911 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 7912 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 7913
7914 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7915 SHARED_HW_CFG_LED_MODE_MASK) >>
7916 SHARED_HW_CFG_LED_MODE_SHIFT);
7917
c2c8b03e
EG		 7918 bp->link_params.feature_config_flags = 0;
7919 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7920 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7921 bp->link_params.feature_config_flags |=
7922 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7923 else
7924 bp->link_params.feature_config_flags &=
7925 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7926
34f80b04
EG		 7927 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7928 bp->common.bc_ver = val;
7929 BNX2X_DEV_INFO("bc_ver %X\n", val);
7930 if (val < BNX2X_BC_VER) {
7931 /* for now only warn
7932 * later we might need to enforce this */
f2e0899f
DK		 7933 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7934 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 7935 }
4d295db0 7936 bp->link_params.feature_config_flags |=
a22f0788 7937 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 7938 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7939
a22f0788
YR		 7940 bp->link_params.feature_config_flags |=
7941 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7942 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3
EG		 7943
7944 if (BP_E1HVN(bp) == 0) {
7945 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7946 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7947 } else {
7948 /* no WOL capability for E1HVN != 0 */
7949 bp->flags |= NO_WOL_FLAG;
7950 }
7951 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 7952 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 7953
7954 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7955 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7956 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7957 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7958
cdaa7cb8
VZ		 7959 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7960 val, val2, val3, val4);
34f80b04
EG		 7961}
7962
f2e0899f
DK		 7963#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7964#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7965
7966static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7967{
7968 int pfid = BP_FUNC(bp);
7969 int vn = BP_E1HVN(bp);
7970 int igu_sb_id;
7971 u32 val;
7972 u8 fid;
7973
7974 bp->igu_base_sb = 0xff;
7975 bp->igu_sb_cnt = 0;
7976 if (CHIP_INT_MODE_IS_BC(bp)) {
7977 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
ec6ba945 7978 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7979
7980 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7981 FP_SB_MAX_E1x;
7982
7983 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7984 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7985
7986 return;
7987 }
7988
7989 /* IGU in normal mode - read CAM */
7990 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7991 igu_sb_id++) {
7992 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7993 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7994 continue;
7995 fid = IGU_FID(val);
7996 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7997 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7998 continue;
7999 if (IGU_VEC(val) == 0)
8000 /* default status block */
8001 bp->igu_dsb_id = igu_sb_id;
8002 else {
8003 if (bp->igu_base_sb == 0xff)
8004 bp->igu_base_sb = igu_sb_id;
8005 bp->igu_sb_cnt++;
8006 }
8007 }
8008 }
ec6ba945
VZ		 8009 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8010 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8011 if (bp->igu_sb_cnt == 0)
8012 BNX2X_ERR("CAM configuration error\n");
8013}
8014
34f80b04
EG		 8015static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8016 u32 switch_cfg)
a2fbb9ea 8017{
a22f0788
YR		 8018 int cfg_size = 0, idx, port = BP_PORT(bp);
8019
8020 /* Aggregation of supported attributes of all external phys */
8021 bp->port.supported[0] = 0;
8022 bp->port.supported[1] = 0;
b7737c9b
YR		 8023 switch (bp->link_params.num_phys) {
8024 case 1:
a22f0788
YR		 8025 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8026 cfg_size = 1;
8027 break;
b7737c9b 8028 case 2:
a22f0788
YR		 8029 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8030 cfg_size = 1;
8031 break;
8032 case 3:
8033 if (bp->link_params.multi_phy_config &
8034 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8035 bp->port.supported[1] =
8036 bp->link_params.phy[EXT_PHY1].supported;
8037 bp->port.supported[0] =
8038 bp->link_params.phy[EXT_PHY2].supported;
8039 } else {
8040 bp->port.supported[0] =
8041 bp->link_params.phy[EXT_PHY1].supported;
8042 bp->port.supported[1] =
8043 bp->link_params.phy[EXT_PHY2].supported;
8044 }
8045 cfg_size = 2;
8046 break;
b7737c9b 8047 }
a2fbb9ea 8048
a22f0788 8049 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8050 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8051 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8052 SHMEM_RD(bp,
a22f0788
YR		 8053 dev_info.port_hw_config[port].external_phy_config),
8054 SHMEM_RD(bp,
8055 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8056 return;
f85582f8 8057 }
a2fbb9ea 8058
b7737c9b
YR		 8059 switch (switch_cfg) {
8060 case SWITCH_CFG_1G:
34f80b04
EG		 8061 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8062 port*0x10);
8063 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8064 break;
8065
8066 case SWITCH_CFG_10G:
34f80b04
EG		 8067 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8068 port*0x18);
8069 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8070 break;
8071
8072 default:
8073 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
a22f0788 8074 bp->port.link_config[0]);
a2fbb9ea
ET		 8075 return;
8076 }
a22f0788
YR		 8077 /* mask what we support according to speed_cap_mask per configuration */
8078 for (idx = 0; idx < cfg_size; idx++) {
8079 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8080 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8081 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8082
a22f0788 8083 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8084 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8085 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8086
a22f0788 8087 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8088 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8089 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8090
a22f0788 8091 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8092 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8093 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8094
a22f0788 8095 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8096 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8097 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8098 SUPPORTED_1000baseT_Full);
a2fbb9ea 8099
a22f0788 8100 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8101 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8102 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8103
a22f0788 8104 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8105 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8106 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8107
8108 }
a2fbb9ea 8109
a22f0788
YR		 8110 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8111 bp->port.supported[1]);
a2fbb9ea
ET		 8112}
8113
34f80b04 8114static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8115{
a22f0788
YR		 8116 u32 link_config, idx, cfg_size = 0;
8117 bp->port.advertising[0] = 0;
8118 bp->port.advertising[1] = 0;
8119 switch (bp->link_params.num_phys) {
8120 case 1:
8121 case 2:
8122 cfg_size = 1;
8123 break;
8124 case 3:
8125 cfg_size = 2;
8126 break;
8127 }
8128 for (idx = 0; idx < cfg_size; idx++) {
8129 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8130 link_config = bp->port.link_config[idx];
8131 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8132 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8133 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8134 bp->link_params.req_line_speed[idx] =
8135 SPEED_AUTO_NEG;
8136 bp->port.advertising[idx] |=
8137 bp->port.supported[idx];
f85582f8
DK		 8138 } else {
8139 /* force 10G, no AN */
a22f0788
YR		 8140 bp->link_params.req_line_speed[idx] =
8141 SPEED_10000;
8142 bp->port.advertising[idx] |=
8143 (ADVERTISED_10000baseT_Full |
f85582f8 8144 ADVERTISED_FIBRE);
a22f0788 8145 continue;
f85582f8
DK		 8146 }
8147 break;
a2fbb9ea 8148
f85582f8 8149 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8150 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8151 bp->link_params.req_line_speed[idx] =
8152 SPEED_10;
8153 bp->port.advertising[idx] |=
8154 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8155 ADVERTISED_TP);
8156 } else {
8157 BNX2X_ERROR("NVRAM config error. "
8158 "Invalid link_config 0x%x"
8159 " speed_cap_mask 0x%x\n",
8160 link_config,
a22f0788 8161 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8162 return;
8163 }
8164 break;
a2fbb9ea 8165
f85582f8 8166 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8167 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8168 bp->link_params.req_line_speed[idx] =
8169 SPEED_10;
8170 bp->link_params.req_duplex[idx] =
8171 DUPLEX_HALF;
8172 bp->port.advertising[idx] |=
8173 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8174 ADVERTISED_TP);
8175 } else {
8176 BNX2X_ERROR("NVRAM config error. "
8177 "Invalid link_config 0x%x"
8178 " speed_cap_mask 0x%x\n",
8179 link_config,
8180 bp->link_params.speed_cap_mask[idx]);
8181 return;
8182 }
8183 break;
a2fbb9ea 8184
f85582f8
DK		 8185 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8186 if (bp->port.supported[idx] &
8187 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8188 bp->link_params.req_line_speed[idx] =
8189 SPEED_100;
8190 bp->port.advertising[idx] |=
8191 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8192 ADVERTISED_TP);
8193 } else {
8194 BNX2X_ERROR("NVRAM config error. "
8195 "Invalid link_config 0x%x"
8196 " speed_cap_mask 0x%x\n",
8197 link_config,
8198 bp->link_params.speed_cap_mask[idx]);
8199 return;
8200 }
8201 break;
a2fbb9ea 8202
f85582f8
DK		 8203 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8204 if (bp->port.supported[idx] &
8205 SUPPORTED_100baseT_Half) {
8206 bp->link_params.req_line_speed[idx] =
8207 SPEED_100;
8208 bp->link_params.req_duplex[idx] =
8209 DUPLEX_HALF;
a22f0788
YR		 8210 bp->port.advertising[idx] |=
8211 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8212 ADVERTISED_TP);
8213 } else {
8214 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8215 "Invalid link_config 0x%x"
8216 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8217 link_config,
8218 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8219 return;
8220 }
8221 break;
a2fbb9ea 8222
f85582f8 8223 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 8224 if (bp->port.supported[idx] &
8225 SUPPORTED_1000baseT_Full) {
8226 bp->link_params.req_line_speed[idx] =
8227 SPEED_1000;
8228 bp->port.advertising[idx] |=
8229 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 8230 ADVERTISED_TP);
8231 } else {
8232 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8233 "Invalid link_config 0x%x"
8234 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8235 link_config,
8236 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8237 return;
8238 }
8239 break;
a2fbb9ea 8240
f85582f8 8241 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 8242 if (bp->port.supported[idx] &
8243 SUPPORTED_2500baseX_Full) {
8244 bp->link_params.req_line_speed[idx] =
8245 SPEED_2500;
8246 bp->port.advertising[idx] |=
8247 (ADVERTISED_2500baseX_Full |
34f80b04 8248 ADVERTISED_TP);
f85582f8
DK		 8249 } else {
8250 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8251 "Invalid link_config 0x%x"
8252 " speed_cap_mask 0x%x\n",
a22f0788 8253 link_config,
f85582f8
DK		 8254 bp->link_params.speed_cap_mask[idx]);
8255 return;
8256 }
8257 break;
a2fbb9ea 8258
f85582f8
DK		 8259 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8260 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8261 case PORT_FEATURE_LINK_SPEED_10G_KR:
a22f0788
YR		 8262 if (bp->port.supported[idx] &
8263 SUPPORTED_10000baseT_Full) {
8264 bp->link_params.req_line_speed[idx] =
8265 SPEED_10000;
8266 bp->port.advertising[idx] |=
8267 (ADVERTISED_10000baseT_Full |
34f80b04 8268 ADVERTISED_FIBRE);
f85582f8
DK		 8269 } else {
8270 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8271 "Invalid link_config 0x%x"
8272 " speed_cap_mask 0x%x\n",
a22f0788 8273 link_config,
f85582f8
DK		 8274 bp->link_params.speed_cap_mask[idx]);
8275 return;
8276 }
8277 break;
a2fbb9ea 8278
f85582f8
DK		 8279 default:
8280 BNX2X_ERROR("NVRAM config error. "
8281 "BAD link speed link_config 0x%x\n",
8282 link_config);
8283 bp->link_params.req_line_speed[idx] =
8284 SPEED_AUTO_NEG;
8285 bp->port.advertising[idx] =
8286 bp->port.supported[idx];
8287 break;
8288 }
a2fbb9ea 8289
a22f0788 8290 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 8291 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 8292 if ((bp->link_params.req_flow_ctrl[idx] ==
8293 BNX2X_FLOW_CTRL_AUTO) &&
8294 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8295 bp->link_params.req_flow_ctrl[idx] =
8296 BNX2X_FLOW_CTRL_NONE;
8297 }
a2fbb9ea 8298
a22f0788
YR		 8299 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8300 " 0x%x advertising 0x%x\n",
8301 bp->link_params.req_line_speed[idx],
8302 bp->link_params.req_duplex[idx],
8303 bp->link_params.req_flow_ctrl[idx],
8304 bp->port.advertising[idx]);
8305 }
a2fbb9ea
ET		 8306}
8307
e665bfda
MC		 8308static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8309{
8310 mac_hi = cpu_to_be16(mac_hi);
8311 mac_lo = cpu_to_be32(mac_lo);
8312 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8313 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8314}
8315
34f80b04 8316static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 8317{
34f80b04 8318 int port = BP_PORT(bp);
589abe3a 8319 u32 config;
6f38ad93 8320 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 8321
c18487ee 8322 bp->link_params.bp = bp;
34f80b04 8323 bp->link_params.port = port;
c18487ee 8324
c18487ee 8325 bp->link_params.lane_config =
a2fbb9ea 8326 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 8327
a22f0788 8328 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 8329 SHMEM_RD(bp,
8330 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 8331 bp->link_params.speed_cap_mask[1] =
8332 SHMEM_RD(bp,
8333 dev_info.port_hw_config[port].speed_capability_mask2);
8334 bp->port.link_config[0] =
a2fbb9ea
ET		 8335 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8336
a22f0788
YR		 8337 bp->port.link_config[1] =
8338 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 8339
a22f0788
YR		 8340 bp->link_params.multi_phy_config =
8341 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 8342 /* If the device is capable of WoL, set the default state according
8343 * to the HW
8344 */
4d295db0 8345 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 8346 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8347 (config & PORT_FEATURE_WOL_ENABLED));
8348
f85582f8 8349 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 8350 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 8351 bp->link_params.lane_config,
a22f0788
YR		 8352 bp->link_params.speed_cap_mask[0],
8353 bp->port.link_config[0]);
a2fbb9ea 8354
a22f0788 8355 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 8356 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 8357 bnx2x_phy_probe(&bp->link_params);
c18487ee 8358 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 8359
8360 bnx2x_link_settings_requested(bp);
8361
01cd4528
EG		 8362 /*
8363 * If connected directly, work with the internal PHY, otherwise, work
8364 * with the external PHY
8365 */
b7737c9b
YR		 8366 ext_phy_config =
8367 SHMEM_RD(bp,
8368 dev_info.port_hw_config[port].external_phy_config);
8369 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 8370 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 8371 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 8372
8373 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8374 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8375 bp->mdio.prtad =
b7737c9b 8376 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 8377
8378 /*
8379 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8380 * In MF mode, it is set to cover self test cases
8381 */
8382 if (IS_MF(bp))
8383 bp->port.need_hw_lock = 1;
8384 else
8385 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8386 bp->common.shmem_base,
8387 bp->common.shmem2_base);
0793f83f 8388}
01cd4528 8389
2ba45142
VZ		 8390#ifdef BCM_CNIC
8391static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8392{
8393 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8394 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8395 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8396 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8397
8398 /* Get the number of maximum allowed iSCSI and FCoE connections */
8399 bp->cnic_eth_dev.max_iscsi_conn =
8400 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8401 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8402
8403 bp->cnic_eth_dev.max_fcoe_conn =
8404 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8405 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8406
8407 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8408 bp->cnic_eth_dev.max_iscsi_conn,
8409 bp->cnic_eth_dev.max_fcoe_conn);
8410
8411 /* If mamimum allowed number of connections is zero -
8412 * disable the feature.
8413 */
8414 if (!bp->cnic_eth_dev.max_iscsi_conn)
8415 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8416
8417 if (!bp->cnic_eth_dev.max_fcoe_conn)
8418 bp->flags |= NO_FCOE_FLAG;
8419}
8420#endif
8421
0793f83f
DK		 8422static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8423{
8424 u32 val, val2;
8425 int func = BP_ABS_FUNC(bp);
8426 int port = BP_PORT(bp);
2ba45142
VZ		 8427#ifdef BCM_CNIC
8428 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8429 u8 *fip_mac = bp->fip_mac;
8430#endif
0793f83f
DK		 8431
8432 if (BP_NOMCP(bp)) {
8433 BNX2X_ERROR("warning: random MAC workaround active\n");
8434 random_ether_addr(bp->dev->dev_addr);
8435 } else if (IS_MF(bp)) {
8436 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8437 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8438 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8439 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8440 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 8441
8442#ifdef BCM_CNIC
2ba45142
VZ		 8443 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8444 * FCoE MAC then the appropriate feature should be disabled.
8445 */
0793f83f
DK		 8446 if (IS_MF_SI(bp)) {
8447 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8448 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8449 val2 = MF_CFG_RD(bp, func_ext_config[func].
8450 iscsi_mac_addr_upper);
8451 val = MF_CFG_RD(bp, func_ext_config[func].
8452 iscsi_mac_addr_lower);
2ba45142
VZ		 8453 BNX2X_DEV_INFO("Read iSCSI MAC: "
8454 "0x%x:0x%04x\n", val2, val);
8455 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8456
8457 /* Disable iSCSI OOO if MAC configuration is
8458 * invalid.
8459 */
8460 if (!is_valid_ether_addr(iscsi_mac)) {
8461 bp->flags |= NO_ISCSI_OOO_FLAG |
8462 NO_ISCSI_FLAG;
8463 memset(iscsi_mac, 0, ETH_ALEN);
8464 }
8465 } else
8466 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8467
8468 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8469 val2 = MF_CFG_RD(bp, func_ext_config[func].
8470 fcoe_mac_addr_upper);
8471 val = MF_CFG_RD(bp, func_ext_config[func].
8472 fcoe_mac_addr_lower);
8473 BNX2X_DEV_INFO("Read FCoE MAC to "
8474 "0x%x:0x%04x\n", val2, val);
8475 bnx2x_set_mac_buf(fip_mac, val, val2);
8476
8477 /* Disable FCoE if MAC configuration is
8478 * invalid.
8479 */
8480 if (!is_valid_ether_addr(fip_mac)) {
8481 bp->flags |= NO_FCOE_FLAG;
8482 memset(bp->fip_mac, 0, ETH_ALEN);
8483 }
8484 } else
8485 bp->flags |= NO_FCOE_FLAG;
0793f83f 8486 }
37b091ba 8487#endif
0793f83f
DK		 8488 } else {
8489 /* in SF read MACs from port configuration */
8490 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8491 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8492 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8493
8494#ifdef BCM_CNIC
8495 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8496 iscsi_mac_upper);
8497 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8498 iscsi_mac_lower);
2ba45142 8499 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0793f83f
DK		 8500#endif
8501 }
8502
8503 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8504 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8505
ec6ba945 8506#ifdef BCM_CNIC
2ba45142 8507 /* Set the FCoE MAC in modes other then MF_SI */
ec6ba945
VZ		 8508 if (!CHIP_IS_E1x(bp)) {
8509 if (IS_MF_SD(bp))
2ba45142
VZ		 8510 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8511 else if (!IS_MF(bp))
8512 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
ec6ba945
VZ		 8513 }
8514#endif
34f80b04
EG		 8515}
8516
8517static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8518{
0793f83f
DK		 8519 int /*abs*/func = BP_ABS_FUNC(bp);
8520 int vn, port;
8521 u32 val = 0;
34f80b04 8522 int rc = 0;
a2fbb9ea 8523
34f80b04 8524 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 8525
f2e0899f
DK		 8526 if (CHIP_IS_E1x(bp)) {
8527 bp->common.int_block = INT_BLOCK_HC;
8528
8529 bp->igu_dsb_id = DEF_SB_IGU_ID;
8530 bp->igu_base_sb = 0;
ec6ba945
VZ		 8531 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8532 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8533 } else {
8534 bp->common.int_block = INT_BLOCK_IGU;
8535 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8536 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8537 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8538 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8539 } else
8540 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
523224a3 8541
f2e0899f
DK		 8542 bnx2x_get_igu_cam_info(bp);
8543
8544 }
8545 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8546 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8547
8548 /*
8549 * Initialize MF configuration
8550 */
523224a3 8551
fb3bff17
DK		 8552 bp->mf_ov = 0;
8553 bp->mf_mode = 0;
f2e0899f 8554 vn = BP_E1HVN(bp);
0793f83f
DK		 8555 port = BP_PORT(bp);
8556
f2e0899f 8557 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
0793f83f
DK		 8558 DP(NETIF_MSG_PROBE,
8559 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8560 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8561 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
f2e0899f
DK		 8562 if (SHMEM2_HAS(bp, mf_cfg_addr))
8563 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8564 else
8565 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 8566 offsetof(struct shmem_region, func_mb) +
8567 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 8568 /*
8569 * get mf configuration:
8570 * 1. existance of MF configuration
8571 * 2. MAC address must be legal (check only upper bytes)
8572 * for Switch-Independent mode;
8573 * OVLAN must be legal for Switch-Dependent mode
8574 * 3. SF_MODE configures specific MF mode
8575 */
8576 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8577 /* get mf configuration */
8578 val = SHMEM_RD(bp,
8579 dev_info.shared_feature_config.config);
8580 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8581
8582 switch (val) {
8583 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8584 val = MF_CFG_RD(bp, func_mf_config[func].
8585 mac_upper);
8586 /* check for legal mac (upper bytes)*/
8587 if (val != 0xffff) {
8588 bp->mf_mode = MULTI_FUNCTION_SI;
8589 bp->mf_config[vn] = MF_CFG_RD(bp,
8590 func_mf_config[func].config);
8591 } else
8592 DP(NETIF_MSG_PROBE, "illegal MAC "
8593 "address for SI\n");
8594 break;
8595 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8596 /* get OV configuration */
8597 val = MF_CFG_RD(bp,
8598 func_mf_config[FUNC_0].e1hov_tag);
8599 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8600
8601 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8602 bp->mf_mode = MULTI_FUNCTION_SD;
8603 bp->mf_config[vn] = MF_CFG_RD(bp,
8604 func_mf_config[func].config);
8605 } else
8606 DP(NETIF_MSG_PROBE, "illegal OV for "
8607 "SD\n");
8608 break;
8609 default:
8610 /* Unknown configuration: reset mf_config */
8611 bp->mf_config[vn] = 0;
8612 DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
8613 val);
8614 }
8615 }
a2fbb9ea 8616
2691d51d 8617 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 8618 IS_MF(bp) ? "multi" : "single");
2691d51d 8619
0793f83f
DK		 8620 switch (bp->mf_mode) {
8621 case MULTI_FUNCTION_SD:
8622 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8623 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 8624 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 8625 bp->mf_ov = val;
0793f83f
DK		 8626 BNX2X_DEV_INFO("MF OV for func %d is %d"
8627 " (0x%04x)\n", func,
8628 bp->mf_ov, bp->mf_ov);
2691d51d 8629 } else {
0793f83f
DK		 8630 BNX2X_ERR("No valid MF OV for func %d,"
8631 " aborting\n", func);
34f80b04
EG		 8632 rc = -EPERM;
8633 }
0793f83f
DK		 8634 break;
8635 case MULTI_FUNCTION_SI:
8636 BNX2X_DEV_INFO("func %d is in MF "
8637 "switch-independent mode\n", func);
8638 break;
8639 default:
8640 if (vn) {
8641 BNX2X_ERR("VN %d in single function mode,"
8642 " aborting\n", vn);
2691d51d
EG		 8643 rc = -EPERM;
8644 }
0793f83f 8645 break;
34f80b04 8646 }
0793f83f 8647
34f80b04 8648 }
a2fbb9ea 8649
f2e0899f
DK		 8650 /* adjust igu_sb_cnt to MF for E1x */
8651 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 8652 bp->igu_sb_cnt /= E1HVN_MAX;
8653
f2e0899f
DK		 8654 /*
8655 * adjust E2 sb count: to be removed when FW will support
8656 * more then 16 L2 clients
8657 */
8658#define MAX_L2_CLIENTS 16
8659 if (CHIP_IS_E2(bp))
8660 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8661 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8662
34f80b04
EG		 8663 if (!BP_NOMCP(bp)) {
8664 bnx2x_get_port_hwinfo(bp);
8665
f2e0899f
DK		 8666 bp->fw_seq =
8667 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8668 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 8669 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8670 }
8671
0793f83f
DK		 8672 /* Get MAC addresses */
8673 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 8674
2ba45142
VZ		 8675#ifdef BCM_CNIC
8676 bnx2x_get_cnic_info(bp);
8677#endif
8678
34f80b04
EG		 8679 return rc;
8680}
8681
34f24c7f
VZ		 8682static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8683{
8684 int cnt, i, block_end, rodi;
8685 char vpd_data[BNX2X_VPD_LEN+1];
8686 char str_id_reg[VENDOR_ID_LEN+1];
8687 char str_id_cap[VENDOR_ID_LEN+1];
8688 u8 len;
8689
8690 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8691 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8692
8693 if (cnt < BNX2X_VPD_LEN)
8694 goto out_not_found;
8695
8696 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8697 PCI_VPD_LRDT_RO_DATA);
8698 if (i < 0)
8699 goto out_not_found;
8700
8701
8702 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8703 pci_vpd_lrdt_size(&vpd_data[i]);
8704
8705 i += PCI_VPD_LRDT_TAG_SIZE;
8706
8707 if (block_end > BNX2X_VPD_LEN)
8708 goto out_not_found;
8709
8710 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8711 PCI_VPD_RO_KEYWORD_MFR_ID);
8712 if (rodi < 0)
8713 goto out_not_found;
8714
8715 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8716
8717 if (len != VENDOR_ID_LEN)
8718 goto out_not_found;
8719
8720 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8721
8722 /* vendor specific info */
8723 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8724 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8725 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8726 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8727
8728 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8729 PCI_VPD_RO_KEYWORD_VENDOR0);
8730 if (rodi >= 0) {
8731 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8732
8733 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8734
8735 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8736 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8737 bp->fw_ver[len] = ' ';
8738 }
8739 }
8740 return;
8741 }
8742out_not_found:
8743 return;
8744}
8745
34f80b04
EG		 8746static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8747{
f2e0899f 8748 int func;
87942b46 8749 int timer_interval;
34f80b04
EG		 8750 int rc;
8751
da5a662a
VZ		 8752 /* Disable interrupt handling until HW is initialized */
8753 atomic_set(&bp->intr_sem, 1);
e1510706 8754 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
da5a662a 8755
34f80b04 8756 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 8757 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 8758 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 8759#ifdef BCM_CNIC
8760 mutex_init(&bp->cnic_mutex);
8761#endif
a2fbb9ea 8762
1cf167f2 8763 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
72fd0718 8764 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
34f80b04
EG		 8765
8766 rc = bnx2x_get_hwinfo(bp);
8767
523224a3
DK		 8768 if (!rc)
8769 rc = bnx2x_alloc_mem_bp(bp);
8770
34f24c7f 8771 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 8772
8773 func = BP_FUNC(bp);
8774
34f80b04
EG		 8775 /* need to reset chip if undi was active */
8776 if (!BP_NOMCP(bp))
8777 bnx2x_undi_unload(bp);
8778
8779 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 8780 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 8781
8782 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 8783 dev_err(&bp->pdev->dev, "MCP disabled, "
8784 "must load devices in order!\n");
34f80b04 8785
555f6c78 8786 bp->multi_mode = multi_mode;
5d7cd496 8787 bp->int_mode = int_mode;
555f6c78 8788
4fd89b7a
DK		 8789 bp->dev->features |= NETIF_F_GRO;
8790
7a9b2557
VZ		 8791 /* Set TPA flags */
8792 if (disable_tpa) {
8793 bp->flags &= ~TPA_ENABLE_FLAG;
8794 bp->dev->features &= ~NETIF_F_LRO;
8795 } else {
8796 bp->flags |= TPA_ENABLE_FLAG;
8797 bp->dev->features |= NETIF_F_LRO;
8798 }
5d7cd496 8799 bp->disable_tpa = disable_tpa;
7a9b2557 8800
a18f5128
EG		 8801 if (CHIP_IS_E1(bp))
8802 bp->dropless_fc = 0;
8803 else
8804 bp->dropless_fc = dropless_fc;
8805
8d5726c4 8806 bp->mrrs = mrrs;
7a9b2557 8807
34f80b04 8808 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04
EG		 8809
8810 bp->rx_csum = 1;
34f80b04 8811
7d323bfd 8812 /* make sure that the numbers are in the right granularity */
523224a3
DK		 8813 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8814 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 8815
87942b46
EG		 8816 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8817 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 8818
8819 init_timer(&bp->timer);
8820 bp->timer.expires = jiffies + bp->current_interval;
8821 bp->timer.data = (unsigned long) bp;
8822 bp->timer.function = bnx2x_timer;
8823
785b9b1a 8824 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 8825 bnx2x_dcbx_init_params(bp);
8826
34f80b04 8827 return rc;
a2fbb9ea
ET		 8828}
8829
a2fbb9ea 8830
de0c62db
DK		 8831/****************************************************************************
8832* General service functions
8833****************************************************************************/
a2fbb9ea 8834
bb2a0f7a 8835/* called with rtnl_lock */
a2fbb9ea
ET		 8836static int bnx2x_open(struct net_device *dev)
8837{
8838 struct bnx2x *bp = netdev_priv(dev);
8839
6eccabb3
EG		 8840 netif_carrier_off(dev);
8841
a2fbb9ea
ET		 8842 bnx2x_set_power_state(bp, PCI_D0);
8843
72fd0718
VZ		 8844 if (!bnx2x_reset_is_done(bp)) {
8845 do {
8846 /* Reset MCP mail box sequence if there is on going
8847 * recovery
8848 */
8849 bp->fw_seq = 0;
8850
8851 /* If it's the first function to load and reset done
8852 * is still not cleared it may mean that. We don't
8853 * check the attention state here because it may have
8854 * already been cleared by a "common" reset but we
8855 * shell proceed with "process kill" anyway.
8856 */
8857 if ((bnx2x_get_load_cnt(bp) == 0) &&
8858 bnx2x_trylock_hw_lock(bp,
8859 HW_LOCK_RESOURCE_RESERVED_08) &&
8860 (!bnx2x_leader_reset(bp))) {
8861 DP(NETIF_MSG_HW, "Recovered in open\n");
8862 break;
8863 }
8864
8865 bnx2x_set_power_state(bp, PCI_D3hot);
8866
8867 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8868 " completed yet. Try again later. If u still see this"
8869 " message after a few retries then power cycle is"
8870 " required.\n", bp->dev->name);
8871
8872 return -EAGAIN;
8873 } while (0);
8874 }
8875
8876 bp->recovery_state = BNX2X_RECOVERY_DONE;
8877
bb2a0f7a 8878 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 8879}
8880
bb2a0f7a 8881/* called with rtnl_lock */
a2fbb9ea
ET		 8882static int bnx2x_close(struct net_device *dev)
8883{
a2fbb9ea
ET		 8884 struct bnx2x *bp = netdev_priv(dev);
8885
8886 /* Unload the driver, release IRQs */
bb2a0f7a 8887 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
d3dbfee0 8888 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 8889
8890 return 0;
8891}
8892
f5372251 8893/* called with netif_tx_lock from dev_mcast.c */
9f6c9258 8894void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 8895{
8896 struct bnx2x *bp = netdev_priv(dev);
8897 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
8898 int port = BP_PORT(bp);
8899
8900 if (bp->state != BNX2X_STATE_OPEN) {
8901 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
8902 return;
8903 }
8904
8905 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
8906
8907 if (dev->flags & IFF_PROMISC)
8908 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04 8909 else if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf
JP		 8910 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
8911 CHIP_IS_E1(bp)))
34f80b04 8912 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04
EG		 8913 else { /* some multicasts */
8914 if (CHIP_IS_E1(bp)) {
523224a3
DK		 8915 /*
8916 * set mc list, do not wait as wait implies sleep
8917 * and set_rx_mode can be invoked from non-sleepable
8918 * context
8919 */
8920 u8 offset = (CHIP_REV_IS_SLOW(bp) ?
8921 BNX2X_MAX_EMUL_MULTI*(1 + port) :
8922 BNX2X_MAX_MULTICAST*(1 + port));
e665bfda 8923
523224a3 8924 bnx2x_set_e1_mc_list(bp, offset);
34f80b04
EG		 8925 } else { /* E1H */
8926 /* Accept one or more multicasts */
22bedad3 8927 struct netdev_hw_addr *ha;
34f80b04
EG		 8928 u32 mc_filter[MC_HASH_SIZE];
8929 u32 crc, bit, regidx;
8930 int i;
8931
8932 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
8933
22bedad3 8934 netdev_for_each_mc_addr(ha, dev) {
7c510e4b 8935 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
523224a3 8936 bnx2x_mc_addr(ha));
34f80b04 8937
523224a3
DK		 8938 crc = crc32c_le(0, bnx2x_mc_addr(ha),
8939 ETH_ALEN);
34f80b04
EG		 8940 bit = (crc >> 24) & 0xff;
8941 regidx = bit >> 5;
8942 bit &= 0x1f;
8943 mc_filter[regidx] |= (1 << bit);
8944 }
8945
8946 for (i = 0; i < MC_HASH_SIZE; i++)
8947 REG_WR(bp, MC_HASH_OFFSET(bp, i),
8948 mc_filter[i]);
8949 }
8950 }
8951
8952 bp->rx_mode = rx_mode;
8953 bnx2x_set_storm_rx_mode(bp);
8954}
8955
c18487ee 8956/* called with rtnl_lock */
01cd4528
EG		 8957static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
8958 int devad, u16 addr)
a2fbb9ea 8959{
01cd4528
EG		 8960 struct bnx2x *bp = netdev_priv(netdev);
8961 u16 value;
8962 int rc;
a2fbb9ea 8963
01cd4528
EG		 8964 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
8965 prtad, devad, addr);
a2fbb9ea 8966
01cd4528
EG		 8967 /* The HW expects different devad if CL22 is used */
8968 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 8969
01cd4528 8970 bnx2x_acquire_phy_lock(bp);
e10bc84d 8971 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 8972 bnx2x_release_phy_lock(bp);
8973 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 8974
01cd4528
EG		 8975 if (!rc)
8976 rc = value;
8977 return rc;
8978}
a2fbb9ea 8979
01cd4528
EG		 8980/* called with rtnl_lock */
8981static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
8982 u16 addr, u16 value)
8983{
8984 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 8985 int rc;
8986
8987 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
8988 " value 0x%x\n", prtad, devad, addr, value);
8989
01cd4528
EG		 8990 /* The HW expects different devad if CL22 is used */
8991 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 8992
01cd4528 8993 bnx2x_acquire_phy_lock(bp);
e10bc84d 8994 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 8995 bnx2x_release_phy_lock(bp);
8996 return rc;
8997}
c18487ee 8998
01cd4528
EG		 8999/* called with rtnl_lock */
9000static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9001{
9002 struct bnx2x *bp = netdev_priv(dev);
9003 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 9004
01cd4528
EG		 9005 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9006 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 9007
01cd4528
EG		 9008 if (!netif_running(dev))
9009 return -EAGAIN;
9010
9011 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 9012}
9013
257ddbda 9014#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 9015static void poll_bnx2x(struct net_device *dev)
9016{
9017 struct bnx2x *bp = netdev_priv(dev);
9018
9019 disable_irq(bp->pdev->irq);
9020 bnx2x_interrupt(bp->pdev->irq, dev);
9021 enable_irq(bp->pdev->irq);
9022}
9023#endif
9024
c64213cd
SH		 9025static const struct net_device_ops bnx2x_netdev_ops = {
9026 .ndo_open = bnx2x_open,
9027 .ndo_stop = bnx2x_close,
9028 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 9029 .ndo_select_queue = bnx2x_select_queue,
356e2385 9030 .ndo_set_multicast_list = bnx2x_set_rx_mode,
c64213cd
SH		 9031 .ndo_set_mac_address = bnx2x_change_mac_addr,
9032 .ndo_validate_addr = eth_validate_addr,
9033 .ndo_do_ioctl = bnx2x_ioctl,
9034 .ndo_change_mtu = bnx2x_change_mtu,
9035 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 9036#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 9037 .ndo_poll_controller = poll_bnx2x,
9038#endif
9039};
9040
34f80b04
EG		 9041static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9042 struct net_device *dev)
a2fbb9ea
ET		 9043{
9044 struct bnx2x *bp;
9045 int rc;
9046
9047 SET_NETDEV_DEV(dev, &pdev->dev);
9048 bp = netdev_priv(dev);
9049
34f80b04
EG		 9050 bp->dev = dev;
9051 bp->pdev = pdev;
a2fbb9ea 9052 bp->flags = 0;
f2e0899f 9053 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 9054
9055 rc = pci_enable_device(pdev);
9056 if (rc) {
cdaa7cb8
VZ		 9057 dev_err(&bp->pdev->dev,
9058 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 9059 goto err_out;
9060 }
9061
9062 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9063 dev_err(&bp->pdev->dev,
9064 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 9065 rc = -ENODEV;
9066 goto err_out_disable;
9067 }
9068
9069 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 9070 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9071 " base address, aborting\n");
a2fbb9ea
ET		 9072 rc = -ENODEV;
9073 goto err_out_disable;
9074 }
9075
34f80b04
EG		 9076 if (atomic_read(&pdev->enable_cnt) == 1) {
9077 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9078 if (rc) {
cdaa7cb8
VZ		 9079 dev_err(&bp->pdev->dev,
9080 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 9081 goto err_out_disable;
9082 }
a2fbb9ea 9083
34f80b04
EG		 9084 pci_set_master(pdev);
9085 pci_save_state(pdev);
9086 }
a2fbb9ea
ET		 9087
9088 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9089 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 9090 dev_err(&bp->pdev->dev,
9091 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 9092 rc = -EIO;
9093 goto err_out_release;
9094 }
9095
9096 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9097 if (bp->pcie_cap == 0) {
cdaa7cb8
VZ		 9098 dev_err(&bp->pdev->dev,
9099 "Cannot find PCI Express capability, aborting\n");
a2fbb9ea
ET		 9100 rc = -EIO;
9101 goto err_out_release;
9102 }
9103
1a983142 9104 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
a2fbb9ea 9105 bp->flags |= USING_DAC_FLAG;
1a983142 9106 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
cdaa7cb8
VZ		 9107 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9108 " failed, aborting\n");
a2fbb9ea
ET		 9109 rc = -EIO;
9110 goto err_out_release;
9111 }
9112
1a983142 9113 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
cdaa7cb8
VZ		 9114 dev_err(&bp->pdev->dev,
9115 "System does not support DMA, aborting\n");
a2fbb9ea
ET		 9116 rc = -EIO;
9117 goto err_out_release;
9118 }
9119
34f80b04
EG		 9120 dev->mem_start = pci_resource_start(pdev, 0);
9121 dev->base_addr = dev->mem_start;
9122 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 9123
9124 dev->irq = pdev->irq;
9125
275f165f 9126 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 9127 if (!bp->regview) {
cdaa7cb8
VZ		 9128 dev_err(&bp->pdev->dev,
9129 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 9130 rc = -ENOMEM;
9131 goto err_out_release;
9132 }
9133
34f80b04 9134 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
523224a3 9135 min_t(u64, BNX2X_DB_SIZE(bp),
34f80b04 9136 pci_resource_len(pdev, 2)));
a2fbb9ea 9137 if (!bp->doorbells) {
cdaa7cb8
VZ		 9138 dev_err(&bp->pdev->dev,
9139 "Cannot map doorbell space, aborting\n");
a2fbb9ea
ET		 9140 rc = -ENOMEM;
9141 goto err_out_unmap;
9142 }
9143
9144 bnx2x_set_power_state(bp, PCI_D0);
9145
34f80b04
EG		 9146 /* clean indirect addresses */
9147 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9148 PCICFG_VENDOR_ID_OFFSET);
9149 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9150 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9151 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9152 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 9153
72fd0718
VZ		 9154 /* Reset the load counter */
9155 bnx2x_clear_load_cnt(bp);
9156
34f80b04 9157 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 9158
c64213cd 9159 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 9160 bnx2x_set_ethtool_ops(dev);
34f80b04 9161 dev->features |= NETIF_F_SG;
79032644 9162 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
34f80b04
EG		 9163 if (bp->flags & USING_DAC_FLAG)
9164 dev->features |= NETIF_F_HIGHDMA;
5316bc0b
EG		 9165 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9166 dev->features |= NETIF_F_TSO6;
34f80b04 9167 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
5316bc0b
EG		 9168
9169 dev->vlan_features |= NETIF_F_SG;
79032644 9170 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
5316bc0b
EG		 9171 if (bp->flags & USING_DAC_FLAG)
9172 dev->vlan_features |= NETIF_F_HIGHDMA;
9173 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9174 dev->vlan_features |= NETIF_F_TSO6;
a2fbb9ea 9175
785b9b1a
SR		 9176#ifdef BCM_DCB
9177 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9178#endif
9179
01cd4528
EG		 9180 /* get_port_hwinfo() will set prtad and mmds properly */
9181 bp->mdio.prtad = MDIO_PRTAD_NONE;
9182 bp->mdio.mmds = 0;
9183 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9184 bp->mdio.dev = dev;
9185 bp->mdio.mdio_read = bnx2x_mdio_read;
9186 bp->mdio.mdio_write = bnx2x_mdio_write;
9187
a2fbb9ea
ET		 9188 return 0;
9189
9190err_out_unmap:
9191 if (bp->regview) {
9192 iounmap(bp->regview);
9193 bp->regview = NULL;
9194 }
a2fbb9ea
ET		 9195 if (bp->doorbells) {
9196 iounmap(bp->doorbells);
9197 bp->doorbells = NULL;
9198 }
9199
9200err_out_release:
34f80b04
EG		 9201 if (atomic_read(&pdev->enable_cnt) == 1)
9202 pci_release_regions(pdev);
a2fbb9ea
ET		 9203
9204err_out_disable:
9205 pci_disable_device(pdev);
9206 pci_set_drvdata(pdev, NULL);
9207
9208err_out:
9209 return rc;
9210}
9211
37f9ce62
EG		 9212static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9213 int *width, int *speed)
25047950
ET		 9214{
9215 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9216
37f9ce62 9217 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 9218
37f9ce62
EG		 9219 /* return value of 1=2.5GHz 2=5GHz */
9220 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 9221}
37f9ce62 9222
6891dd25 9223static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 9224{
37f9ce62 9225 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 9226 struct bnx2x_fw_file_hdr *fw_hdr;
9227 struct bnx2x_fw_file_section *sections;
94a78b79 9228 u32 offset, len, num_ops;
37f9ce62 9229 u16 *ops_offsets;
94a78b79 9230 int i;
37f9ce62 9231 const u8 *fw_ver;
94a78b79
VZ		 9232
9233 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9234 return -EINVAL;
9235
9236 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9237 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9238
9239 /* Make sure none of the offsets and sizes make us read beyond
9240 * the end of the firmware data */
9241 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9242 offset = be32_to_cpu(sections[i].offset);
9243 len = be32_to_cpu(sections[i].len);
9244 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 9245 dev_err(&bp->pdev->dev,
9246 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 9247 return -EINVAL;
9248 }
9249 }
9250
9251 /* Likewise for the init_ops offsets */
9252 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9253 ops_offsets = (u16 *)(firmware->data + offset);
9254 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9255
9256 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9257 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 9258 dev_err(&bp->pdev->dev,
9259 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 9260 return -EINVAL;
9261 }
9262 }
9263
9264 /* Check FW version */
9265 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9266 fw_ver = firmware->data + offset;
9267 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9268 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9269 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9270 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 9271 dev_err(&bp->pdev->dev,
9272 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 9273 fw_ver[0], fw_ver[1], fw_ver[2],
9274 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9275 BCM_5710_FW_MINOR_VERSION,
9276 BCM_5710_FW_REVISION_VERSION,
9277 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 9278 return -EINVAL;
94a78b79
VZ		 9279 }
9280
9281 return 0;
9282}
9283
ab6ad5a4 9284static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9285{
ab6ad5a4
EG		 9286 const __be32 *source = (const __be32 *)_source;
9287 u32 *target = (u32 *)_target;
94a78b79 9288 u32 i;
94a78b79
VZ		 9289
9290 for (i = 0; i < n/4; i++)
9291 target[i] = be32_to_cpu(source[i]);
9292}
9293
9294/*
9295 Ops array is stored in the following format:
9296 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9297 */
ab6ad5a4 9298static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 9299{
ab6ad5a4
EG		 9300 const __be32 *source = (const __be32 *)_source;
9301 struct raw_op *target = (struct raw_op *)_target;
94a78b79 9302 u32 i, j, tmp;
94a78b79 9303
ab6ad5a4 9304 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 9305 tmp = be32_to_cpu(source[j]);
9306 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 9307 target[i].offset = tmp & 0xffffff;
9308 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 9309 }
9310}
ab6ad5a4 9311
523224a3
DK		 9312/**
9313 * IRO array is stored in the following format:
9314 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9315 */
9316static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9317{
9318 const __be32 *source = (const __be32 *)_source;
9319 struct iro *target = (struct iro *)_target;
9320 u32 i, j, tmp;
9321
9322 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9323 target[i].base = be32_to_cpu(source[j]);
9324 j++;
9325 tmp = be32_to_cpu(source[j]);
9326 target[i].m1 = (tmp >> 16) & 0xffff;
9327 target[i].m2 = tmp & 0xffff;
9328 j++;
9329 tmp = be32_to_cpu(source[j]);
9330 target[i].m3 = (tmp >> 16) & 0xffff;
9331 target[i].size = tmp & 0xffff;
9332 j++;
9333 }
9334}
9335
ab6ad5a4 9336static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9337{
ab6ad5a4
EG		 9338 const __be16 *source = (const __be16 *)_source;
9339 u16 *target = (u16 *)_target;
94a78b79 9340 u32 i;
94a78b79
VZ		 9341
9342 for (i = 0; i < n/2; i++)
9343 target[i] = be16_to_cpu(source[i]);
9344}
9345
7995c64e
JP		 9346#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9347do { \
9348 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9349 bp->arr = kmalloc(len, GFP_KERNEL); \
9350 if (!bp->arr) { \
9351 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9352 goto lbl; \
9353 } \
9354 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9355 (u8 *)bp->arr, len); \
9356} while (0)
94a78b79 9357
6891dd25 9358int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 9359{
45229b42 9360 const char *fw_file_name;
94a78b79 9361 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 9362 int rc;
94a78b79 9363
94a78b79 9364 if (CHIP_IS_E1(bp))
45229b42 9365 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 9366 else if (CHIP_IS_E1H(bp))
45229b42 9367 fw_file_name = FW_FILE_NAME_E1H;
f2e0899f
DK		 9368 else if (CHIP_IS_E2(bp))
9369 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 9370 else {
6891dd25 9371 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 9372 return -EINVAL;
9373 }
94a78b79 9374
6891dd25 9375 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 9376
6891dd25 9377 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 9378 if (rc) {
6891dd25 9379 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 9380 goto request_firmware_exit;
9381 }
9382
9383 rc = bnx2x_check_firmware(bp);
9384 if (rc) {
6891dd25 9385 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 9386 goto request_firmware_exit;
9387 }
9388
9389 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9390
9391 /* Initialize the pointers to the init arrays */
9392 /* Blob */
9393 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9394
9395 /* Opcodes */
9396 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9397
9398 /* Offsets */
ab6ad5a4
EG		 9399 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9400 be16_to_cpu_n);
94a78b79
VZ		 9401
9402 /* STORMs firmware */
573f2035
EG		 9403 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9404 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9405 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9406 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9407 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9408 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9409 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9410 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9411 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9412 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9413 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9414 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9415 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9416 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9417 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9418 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 9419 /* IRO */
9420 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 9421
9422 return 0;
ab6ad5a4 9423
523224a3
DK		 9424iro_alloc_err:
9425 kfree(bp->init_ops_offsets);
94a78b79
VZ		 9426init_offsets_alloc_err:
9427 kfree(bp->init_ops);
9428init_ops_alloc_err:
9429 kfree(bp->init_data);
9430request_firmware_exit:
9431 release_firmware(bp->firmware);
9432
9433 return rc;
9434}
9435
523224a3
DK		 9436static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9437{
9438 int cid_count = L2_FP_COUNT(l2_cid_count);
94a78b79 9439
523224a3
DK		 9440#ifdef BCM_CNIC
9441 cid_count += CNIC_CID_MAX;
9442#endif
9443 return roundup(cid_count, QM_CID_ROUND);
9444}
f85582f8 9445
a2fbb9ea
ET		 9446static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9447 const struct pci_device_id *ent)
9448{
a2fbb9ea
ET		 9449 struct net_device *dev = NULL;
9450 struct bnx2x *bp;
37f9ce62 9451 int pcie_width, pcie_speed;
523224a3
DK		 9452 int rc, cid_count;
9453
f2e0899f
DK		 9454 switch (ent->driver_data) {
9455 case BCM57710:
9456 case BCM57711:
9457 case BCM57711E:
9458 cid_count = FP_SB_MAX_E1x;
9459 break;
9460
9461 case BCM57712:
9462 case BCM57712E:
9463 cid_count = FP_SB_MAX_E2;
9464 break;
a2fbb9ea 9465
f2e0899f
DK		 9466 default:
9467 pr_err("Unknown board_type (%ld), aborting\n",
9468 ent->driver_data);
870634b0 9469 return -ENODEV;
f2e0899f
DK		 9470 }
9471
ec6ba945 9472 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
f85582f8 9473
a2fbb9ea 9474 /* dev zeroed in init_etherdev */
523224a3 9475 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
34f80b04 9476 if (!dev) {
cdaa7cb8 9477 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 9478 return -ENOMEM;
34f80b04 9479 }
a2fbb9ea 9480
a2fbb9ea 9481 bp = netdev_priv(dev);
7995c64e 9482 bp->msg_enable = debug;
a2fbb9ea 9483
df4770de
EG		 9484 pci_set_drvdata(pdev, dev);
9485
523224a3
DK		 9486 bp->l2_cid_count = cid_count;
9487
34f80b04 9488 rc = bnx2x_init_dev(pdev, dev);
a2fbb9ea
ET		 9489 if (rc < 0) {
9490 free_netdev(dev);
9491 return rc;
9492 }
9493
34f80b04 9494 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 9495 if (rc)
9496 goto init_one_exit;
9497
523224a3
DK		 9498 /* calc qm_cid_count */
9499 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9500
ec6ba945
VZ		 9501#ifdef BCM_CNIC
9502 /* disable FCOE L2 queue for E1x*/
9503 if (CHIP_IS_E1x(bp))
9504 bp->flags |= NO_FCOE_FLAG;
9505
9506#endif
9507
d6214d7a
DK		 9508 /* Configure interupt mode: try to enable MSI-X/MSI if
9509 * needed, set bp->num_queues appropriately.
9510 */
9511 bnx2x_set_int_mode(bp);
9512
9513 /* Add all NAPI objects */
9514 bnx2x_add_all_napi(bp);
9515
b340007f
VZ		 9516 rc = register_netdev(dev);
9517 if (rc) {
9518 dev_err(&pdev->dev, "Cannot register net device\n");
9519 goto init_one_exit;
9520 }
9521
ec6ba945
VZ		 9522#ifdef BCM_CNIC
9523 if (!NO_FCOE(bp)) {
9524 /* Add storage MAC address */
9525 rtnl_lock();
9526 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9527 rtnl_unlock();
9528 }
9529#endif
9530
37f9ce62 9531 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 9532
cdaa7cb8
VZ		 9533 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9534 " IRQ %d, ", board_info[ent->driver_data].name,
9535 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 9536 pcie_width,
9537 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9538 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9539 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 9540 dev->base_addr, bp->pdev->irq);
9541 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 9542
a2fbb9ea 9543 return 0;
34f80b04
EG		 9544
9545init_one_exit:
9546 if (bp->regview)
9547 iounmap(bp->regview);
9548
9549 if (bp->doorbells)
9550 iounmap(bp->doorbells);
9551
9552 free_netdev(dev);
9553
9554 if (atomic_read(&pdev->enable_cnt) == 1)
9555 pci_release_regions(pdev);
9556
9557 pci_disable_device(pdev);
9558 pci_set_drvdata(pdev, NULL);
9559
9560 return rc;
a2fbb9ea
ET		 9561}
9562
9563static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9564{
9565 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 9566 struct bnx2x *bp;
9567
9568 if (!dev) {
cdaa7cb8 9569 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 9570 return;
9571 }
228241eb 9572 bp = netdev_priv(dev);
a2fbb9ea 9573
ec6ba945
VZ		 9574#ifdef BCM_CNIC
9575 /* Delete storage MAC address */
9576 if (!NO_FCOE(bp)) {
9577 rtnl_lock();
9578 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9579 rtnl_unlock();
9580 }
9581#endif
9582
a2fbb9ea
ET		 9583 unregister_netdev(dev);
9584
d6214d7a
DK		 9585 /* Delete all NAPI objects */
9586 bnx2x_del_all_napi(bp);
9587
084d6cbb
VZ		 9588 /* Power on: we can't let PCI layer write to us while we are in D3 */
9589 bnx2x_set_power_state(bp, PCI_D0);
9590
d6214d7a
DK		 9591 /* Disable MSI/MSI-X */
9592 bnx2x_disable_msi(bp);
f85582f8 9593
084d6cbb
VZ		 9594 /* Power off */
9595 bnx2x_set_power_state(bp, PCI_D3hot);
9596
72fd0718
VZ		 9597 /* Make sure RESET task is not scheduled before continuing */
9598 cancel_delayed_work_sync(&bp->reset_task);
9599
a2fbb9ea
ET		 9600 if (bp->regview)
9601 iounmap(bp->regview);
9602
9603 if (bp->doorbells)
9604 iounmap(bp->doorbells);
9605
523224a3
DK		 9606 bnx2x_free_mem_bp(bp);
9607
a2fbb9ea 9608 free_netdev(dev);
34f80b04
EG		 9609
9610 if (atomic_read(&pdev->enable_cnt) == 1)
9611 pci_release_regions(pdev);
9612
a2fbb9ea
ET		 9613 pci_disable_device(pdev);
9614 pci_set_drvdata(pdev, NULL);
9615}
9616
f8ef6e44
YG		 9617static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9618{
9619 int i;
9620
9621 bp->state = BNX2X_STATE_ERROR;
9622
9623 bp->rx_mode = BNX2X_RX_MODE_NONE;
9624
9625 bnx2x_netif_stop(bp, 0);
c89af1a3 9626 netif_carrier_off(bp->dev);
f8ef6e44
YG		 9627
9628 del_timer_sync(&bp->timer);
9629 bp->stats_state = STATS_STATE_DISABLED;
9630 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9631
9632 /* Release IRQs */
d6214d7a 9633 bnx2x_free_irq(bp);
f8ef6e44 9634
f8ef6e44
YG		 9635 /* Free SKBs, SGEs, TPA pool and driver internals */
9636 bnx2x_free_skbs(bp);
523224a3 9637
ec6ba945 9638 for_each_rx_queue(bp, i)
f8ef6e44 9639 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 9640
f8ef6e44
YG		 9641 bnx2x_free_mem(bp);
9642
9643 bp->state = BNX2X_STATE_CLOSED;
9644
f8ef6e44
YG		 9645 return 0;
9646}
9647
9648static void bnx2x_eeh_recover(struct bnx2x *bp)
9649{
9650 u32 val;
9651
9652 mutex_init(&bp->port.phy_mutex);
9653
9654 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9655 bp->link_params.shmem_base = bp->common.shmem_base;
9656 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9657
9658 if (!bp->common.shmem_base ||
9659 (bp->common.shmem_base < 0xA0000) ||
9660 (bp->common.shmem_base >= 0xC0000)) {
9661 BNX2X_DEV_INFO("MCP not active\n");
9662 bp->flags |= NO_MCP_FLAG;
9663 return;
9664 }
9665
9666 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9667 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9668 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9669 BNX2X_ERR("BAD MCP validity signature\n");
9670
9671 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9672 bp->fw_seq =
9673 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9674 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 9675 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9676 }
9677}
9678
493adb1f
WX		 9679/**
9680 * bnx2x_io_error_detected - called when PCI error is detected
9681 * @pdev: Pointer to PCI device
9682 * @state: The current pci connection state
9683 *
9684 * This function is called after a PCI bus error affecting
9685 * this device has been detected.
9686 */
9687static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9688 pci_channel_state_t state)
9689{
9690 struct net_device *dev = pci_get_drvdata(pdev);
9691 struct bnx2x *bp = netdev_priv(dev);
9692
9693 rtnl_lock();
9694
9695 netif_device_detach(dev);
9696
07ce50e4
DN		 9697 if (state == pci_channel_io_perm_failure) {
9698 rtnl_unlock();
9699 return PCI_ERS_RESULT_DISCONNECT;
9700 }
9701
493adb1f 9702 if (netif_running(dev))
f8ef6e44 9703 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 9704
9705 pci_disable_device(pdev);
9706
9707 rtnl_unlock();
9708
9709 /* Request a slot reset */
9710 return PCI_ERS_RESULT_NEED_RESET;
9711}
9712
9713/**
9714 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9715 * @pdev: Pointer to PCI device
9716 *
9717 * Restart the card from scratch, as if from a cold-boot.
9718 */
9719static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9720{
9721 struct net_device *dev = pci_get_drvdata(pdev);
9722 struct bnx2x *bp = netdev_priv(dev);
9723
9724 rtnl_lock();
9725
9726 if (pci_enable_device(pdev)) {
9727 dev_err(&pdev->dev,
9728 "Cannot re-enable PCI device after reset\n");
9729 rtnl_unlock();
9730 return PCI_ERS_RESULT_DISCONNECT;
9731 }
9732
9733 pci_set_master(pdev);
9734 pci_restore_state(pdev);
9735
9736 if (netif_running(dev))
9737 bnx2x_set_power_state(bp, PCI_D0);
9738
9739 rtnl_unlock();
9740
9741 return PCI_ERS_RESULT_RECOVERED;
9742}
9743
9744/**
9745 * bnx2x_io_resume - called when traffic can start flowing again
9746 * @pdev: Pointer to PCI device
9747 *
9748 * This callback is called when the error recovery driver tells us that
9749 * its OK to resume normal operation.
9750 */
9751static void bnx2x_io_resume(struct pci_dev *pdev)
9752{
9753 struct net_device *dev = pci_get_drvdata(pdev);
9754 struct bnx2x *bp = netdev_priv(dev);
9755
72fd0718 9756 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f2e0899f
DK		 9757 printk(KERN_ERR "Handling parity error recovery. "
9758 "Try again later\n");
72fd0718
VZ		 9759 return;
9760 }
9761
493adb1f
WX		 9762 rtnl_lock();
9763
f8ef6e44
YG		 9764 bnx2x_eeh_recover(bp);
9765
493adb1f 9766 if (netif_running(dev))
f8ef6e44 9767 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 9768
9769 netif_device_attach(dev);
9770
9771 rtnl_unlock();
9772}
9773
9774static struct pci_error_handlers bnx2x_err_handler = {
9775 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 9776 .slot_reset = bnx2x_io_slot_reset,
9777 .resume = bnx2x_io_resume,
493adb1f
WX		 9778};
9779
a2fbb9ea 9780static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 9781 .name = DRV_MODULE_NAME,
9782 .id_table = bnx2x_pci_tbl,
9783 .probe = bnx2x_init_one,
9784 .remove = __devexit_p(bnx2x_remove_one),
9785 .suspend = bnx2x_suspend,
9786 .resume = bnx2x_resume,
9787 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 9788};
9789
9790static int __init bnx2x_init(void)
9791{
dd21ca6d
SG		 9792 int ret;
9793
7995c64e 9794 pr_info("%s", version);
938cf541 9795
1cf167f2
EG		 9796 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9797 if (bnx2x_wq == NULL) {
7995c64e 9798 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 9799 return -ENOMEM;
9800 }
9801
dd21ca6d
SG		 9802 ret = pci_register_driver(&bnx2x_pci_driver);
9803 if (ret) {
7995c64e 9804 pr_err("Cannot register driver\n");
dd21ca6d
SG		 9805 destroy_workqueue(bnx2x_wq);
9806 }
9807 return ret;
a2fbb9ea
ET		 9808}
9809
9810static void __exit bnx2x_cleanup(void)
9811{
9812 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 9813
9814 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 9815}
9816
9817module_init(bnx2x_init);
9818module_exit(bnx2x_cleanup);
9819
993ac7b5
MC		 9820#ifdef BCM_CNIC
9821
9822/* count denotes the number of new completions we have seen */
9823static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9824{
9825 struct eth_spe *spe;
9826
9827#ifdef BNX2X_STOP_ON_ERROR
9828 if (unlikely(bp->panic))
9829 return;
9830#endif
9831
9832 spin_lock_bh(&bp->spq_lock);
c2bff63f 9833 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 9834 bp->cnic_spq_pending -= count;
9835
993ac7b5 9836
c2bff63f
DK		 9837 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9838 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9839 & SPE_HDR_CONN_TYPE) >>
9840 SPE_HDR_CONN_TYPE_SHIFT;
9841
9842 /* Set validation for iSCSI L2 client before sending SETUP
9843 * ramrod
9844 */
9845 if (type == ETH_CONNECTION_TYPE) {
9846 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9847 hdr.conn_and_cmd_data) >>
9848 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9849
9850 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9851 bnx2x_set_ctx_validation(&bp->context.
9852 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9853 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9854 }
9855
9856 /* There may be not more than 8 L2 and COMMON SPEs and not more
9857 * than 8 L5 SPEs in the air.
9858 */
9859 if ((type == NONE_CONNECTION_TYPE) ||
9860 (type == ETH_CONNECTION_TYPE)) {
9861 if (!atomic_read(&bp->spq_left))
9862 break;
9863 else
9864 atomic_dec(&bp->spq_left);
ec6ba945
VZ		 9865 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9866 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 9867 if (bp->cnic_spq_pending >=
9868 bp->cnic_eth_dev.max_kwqe_pending)
9869 break;
9870 else
9871 bp->cnic_spq_pending++;
9872 } else {
9873 BNX2X_ERR("Unknown SPE type: %d\n", type);
9874 bnx2x_panic();
993ac7b5 9875 break;
c2bff63f 9876 }
993ac7b5
MC		 9877
9878 spe = bnx2x_sp_get_next(bp);
9879 *spe = *bp->cnic_kwq_cons;
9880
993ac7b5
MC		 9881 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9882 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9883
9884 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9885 bp->cnic_kwq_cons = bp->cnic_kwq;
9886 else
9887 bp->cnic_kwq_cons++;
9888 }
9889 bnx2x_sp_prod_update(bp);
9890 spin_unlock_bh(&bp->spq_lock);
9891}
9892
9893static int bnx2x_cnic_sp_queue(struct net_device *dev,
9894 struct kwqe_16 *kwqes[], u32 count)
9895{
9896 struct bnx2x *bp = netdev_priv(dev);
9897 int i;
9898
9899#ifdef BNX2X_STOP_ON_ERROR
9900 if (unlikely(bp->panic))
9901 return -EIO;
9902#endif
9903
9904 spin_lock_bh(&bp->spq_lock);
9905
9906 for (i = 0; i < count; i++) {
9907 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
9908
9909 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
9910 break;
9911
9912 *bp->cnic_kwq_prod = *spe;
9913
9914 bp->cnic_kwq_pending++;
9915
9916 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
9917 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 9918 spe->data.update_data_addr.hi,
9919 spe->data.update_data_addr.lo,
993ac7b5
MC		 9920 bp->cnic_kwq_pending);
9921
9922 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
9923 bp->cnic_kwq_prod = bp->cnic_kwq;
9924 else
9925 bp->cnic_kwq_prod++;
9926 }
9927
9928 spin_unlock_bh(&bp->spq_lock);
9929
9930 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
9931 bnx2x_cnic_sp_post(bp, 0);
9932
9933 return i;
9934}
9935
9936static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9937{
9938 struct cnic_ops *c_ops;
9939 int rc = 0;
9940
9941 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 9942 c_ops = rcu_dereference_protected(bp->cnic_ops,
9943 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 9944 if (c_ops)
9945 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9946 mutex_unlock(&bp->cnic_mutex);
9947
9948 return rc;
9949}
9950
9951static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9952{
9953 struct cnic_ops *c_ops;
9954 int rc = 0;
9955
9956 rcu_read_lock();
9957 c_ops = rcu_dereference(bp->cnic_ops);
9958 if (c_ops)
9959 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9960 rcu_read_unlock();
9961
9962 return rc;
9963}
9964
9965/*
9966 * for commands that have no data
9967 */
9f6c9258 9968int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 9969{
9970 struct cnic_ctl_info ctl = {0};
9971
9972 ctl.cmd = cmd;
9973
9974 return bnx2x_cnic_ctl_send(bp, &ctl);
9975}
9976
9977static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
9978{
9979 struct cnic_ctl_info ctl;
9980
9981 /* first we tell CNIC and only then we count this as a completion */
9982 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
9983 ctl.data.comp.cid = cid;
9984
9985 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 9986 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 9987}
9988
9989static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
9990{
9991 struct bnx2x *bp = netdev_priv(dev);
9992 int rc = 0;
9993
9994 switch (ctl->cmd) {
9995 case DRV_CTL_CTXTBL_WR_CMD: {
9996 u32 index = ctl->data.io.offset;
9997 dma_addr_t addr = ctl->data.io.dma_addr;
9998
9999 bnx2x_ilt_wr(bp, index, addr);
10000 break;
10001 }
10002
c2bff63f
DK		 10003 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10004 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 10005
10006 bnx2x_cnic_sp_post(bp, count);
10007 break;
10008 }
10009
10010 /* rtnl_lock is held. */
10011 case DRV_CTL_START_L2_CMD: {
10012 u32 cli = ctl->data.ring.client_id;
10013
ec6ba945
VZ		 10014 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
10015 bnx2x_del_fcoe_eth_macs(bp);
10016
523224a3
DK		 10017 /* Set iSCSI MAC address */
10018 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10019
10020 mmiowb();
10021 barrier();
10022
10023 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10024 * because it's the only way for UIO Client to accept
10025 * multicasts (in non-promiscuous mode only one Client per
10026 * function will receive multicast packets (leading in our
10027 * case).
10028 */
10029 bnx2x_rxq_set_mac_filters(bp, cli,
10030 BNX2X_ACCEPT_UNICAST |
10031 BNX2X_ACCEPT_BROADCAST |
10032 BNX2X_ACCEPT_ALL_MULTICAST);
10033 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10034
993ac7b5
MC		 10035 break;
10036 }
10037
10038 /* rtnl_lock is held. */
10039 case DRV_CTL_STOP_L2_CMD: {
10040 u32 cli = ctl->data.ring.client_id;
10041
523224a3
DK		 10042 /* Stop accepting on iSCSI L2 ring */
10043 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10044 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10045
10046 mmiowb();
10047 barrier();
10048
10049 /* Unset iSCSI L2 MAC */
10050 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
993ac7b5
MC		 10051 break;
10052 }
c2bff63f
DK		 10053 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10054 int count = ctl->data.credit.credit_count;
10055
10056 smp_mb__before_atomic_inc();
10057 atomic_add(count, &bp->spq_left);
10058 smp_mb__after_atomic_inc();
10059 break;
10060 }
993ac7b5
MC		 10061
10062 default:
10063 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10064 rc = -EINVAL;
10065 }
10066
10067 return rc;
10068}
10069
9f6c9258 10070void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 10071{
10072 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10073
10074 if (bp->flags & USING_MSIX_FLAG) {
10075 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10076 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10077 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10078 } else {
10079 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10080 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10081 }
f2e0899f
DK		 10082 if (CHIP_IS_E2(bp))
10083 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10084 else
10085 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10086
993ac7b5 10087 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
523224a3 10088 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
993ac7b5
MC		 10089 cp->irq_arr[1].status_blk = bp->def_status_blk;
10090 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 10091 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 10092
10093 cp->num_irq = 2;
10094}
10095
10096static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10097 void *data)
10098{
10099 struct bnx2x *bp = netdev_priv(dev);
10100 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10101
10102 if (ops == NULL)
10103 return -EINVAL;
10104
10105 if (atomic_read(&bp->intr_sem) != 0)
10106 return -EBUSY;
10107
10108 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10109 if (!bp->cnic_kwq)
10110 return -ENOMEM;
10111
10112 bp->cnic_kwq_cons = bp->cnic_kwq;
10113 bp->cnic_kwq_prod = bp->cnic_kwq;
10114 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10115
10116 bp->cnic_spq_pending = 0;
10117 bp->cnic_kwq_pending = 0;
10118
10119 bp->cnic_data = data;
10120
10121 cp->num_irq = 0;
10122 cp->drv_state = CNIC_DRV_STATE_REGD;
523224a3 10123 cp->iro_arr = bp->iro_arr;
993ac7b5 10124
993ac7b5 10125 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 10126
993ac7b5
MC		 10127 rcu_assign_pointer(bp->cnic_ops, ops);
10128
10129 return 0;
10130}
10131
10132static int bnx2x_unregister_cnic(struct net_device *dev)
10133{
10134 struct bnx2x *bp = netdev_priv(dev);
10135 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10136
10137 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 10138 cp->drv_state = 0;
10139 rcu_assign_pointer(bp->cnic_ops, NULL);
10140 mutex_unlock(&bp->cnic_mutex);
10141 synchronize_rcu();
10142 kfree(bp->cnic_kwq);
10143 bp->cnic_kwq = NULL;
10144
10145 return 0;
10146}
10147
10148struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10149{
10150 struct bnx2x *bp = netdev_priv(dev);
10151 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10152
2ba45142
VZ		 10153 /* If both iSCSI and FCoE are disabled - return NULL in
10154 * order to indicate CNIC that it should not try to work
10155 * with this device.
10156 */
10157 if (NO_ISCSI(bp) && NO_FCOE(bp))
10158 return NULL;
10159
993ac7b5
MC		 10160 cp->drv_owner = THIS_MODULE;
10161 cp->chip_id = CHIP_ID(bp);
10162 cp->pdev = bp->pdev;
10163 cp->io_base = bp->regview;
10164 cp->io_base2 = bp->doorbells;
10165 cp->max_kwqe_pending = 8;
523224a3 10166 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 10167 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10168 bnx2x_cid_ilt_lines(bp);
993ac7b5 10169 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 10170 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 10171 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10172 cp->drv_ctl = bnx2x_drv_ctl;
10173 cp->drv_register_cnic = bnx2x_register_cnic;
10174 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945
VZ		 10175 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10176 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10177 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
c2bff63f
DK		 10178 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10179
2ba45142
VZ		 10180 if (NO_ISCSI_OOO(bp))
10181 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10182
10183 if (NO_ISCSI(bp))
10184 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10185
10186 if (NO_FCOE(bp))
10187 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10188
c2bff63f
DK		 10189 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10190 "starting cid %d\n",
10191 cp->ctx_blk_size,
10192 cp->ctx_tbl_offset,
10193 cp->ctx_tbl_len,
10194 cp->starting_cid);
993ac7b5
MC		 10195 return cp;
10196}
10197EXPORT_SYMBOL(bnx2x_cnic_probe);
10198
10199#endif /* BCM_CNIC */
94a78b79 10200
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