]>
Commit | Line | Data |
---|---|---|
a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
49d66772 | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
16 | ||
34f80b04 EG |
17 | /* compilation time flags */ |
18 | ||
19 | /* define this to make the driver freeze on error to allow getting debug info | |
20 | * (you will need to reboot afterwards) */ | |
21 | /* #define BNX2X_STOP_ON_ERROR */ | |
22 | ||
a2fbb9ea ET |
23 | /* error/debug prints */ |
24 | ||
34f80b04 EG |
25 | #define DRV_MODULE_NAME "bnx2x" |
26 | #define PFX DRV_MODULE_NAME ": " | |
a2fbb9ea ET |
27 | |
28 | /* for messages that are currently off */ | |
34f80b04 EG |
29 | #define BNX2X_MSG_OFF 0 |
30 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
31 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
32 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
33 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
34 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
35 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 36 | |
34f80b04 | 37 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
a2fbb9ea ET |
38 | |
39 | /* regular debug print */ | |
40 | #define DP(__mask, __fmt, __args...) do { \ | |
41 | if (bp->msglevel & (__mask)) \ | |
34f80b04 EG |
42 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
43 | bp->dev?(bp->dev->name):"?", ##__args); \ | |
a2fbb9ea ET |
44 | } while (0) |
45 | ||
34f80b04 EG |
46 | /* errors debug print */ |
47 | #define BNX2X_DBG_ERR(__fmt, __args...) do { \ | |
48 | if (bp->msglevel & NETIF_MSG_PROBE) \ | |
49 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ | |
50 | bp->dev?(bp->dev->name):"?", ##__args); \ | |
a2fbb9ea ET |
51 | } while (0) |
52 | ||
34f80b04 EG |
53 | /* for errors (never masked) */ |
54 | #define BNX2X_ERR(__fmt, __args...) do { \ | |
55 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ | |
56 | bp->dev?(bp->dev->name):"?", ##__args); \ | |
f1410647 ET |
57 | } while (0) |
58 | ||
a2fbb9ea ET |
59 | /* before we have a dev->name use dev_info() */ |
60 | #define BNX2X_DEV_INFO(__fmt, __args...) do { \ | |
61 | if (bp->msglevel & NETIF_MSG_PROBE) \ | |
62 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
63 | } while (0) | |
64 | ||
65 | ||
66 | #ifdef BNX2X_STOP_ON_ERROR | |
67 | #define bnx2x_panic() do { \ | |
68 | bp->panic = 1; \ | |
69 | BNX2X_ERR("driver assert\n"); \ | |
34f80b04 | 70 | bnx2x_int_disable(bp); \ |
a2fbb9ea ET |
71 | bnx2x_panic_dump(bp); \ |
72 | } while (0) | |
73 | #else | |
74 | #define bnx2x_panic() do { \ | |
75 | BNX2X_ERR("driver assert\n"); \ | |
76 | bnx2x_panic_dump(bp); \ | |
77 | } while (0) | |
78 | #endif | |
79 | ||
80 | ||
34f80b04 EG |
81 | #ifdef NETIF_F_HW_VLAN_TX |
82 | #define BCM_VLAN 1 | |
83 | #endif | |
84 | ||
a2fbb9ea | 85 | |
34f80b04 EG |
86 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
87 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
88 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 89 | |
a2fbb9ea | 90 | |
34f80b04 | 91 | #define REG_ADDR(bp, offset) (bp->regview + offset) |
a2fbb9ea | 92 | |
34f80b04 EG |
93 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
94 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
95 | #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) | |
96 | ||
97 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 98 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 EG |
99 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
100 | #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) | |
a2fbb9ea | 101 | |
34f80b04 EG |
102 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
103 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 104 | |
c18487ee YR |
105 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
106 | do { \ | |
107 | bnx2x_read_dmae(bp, offset, len32);\ | |
108 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \ | |
109 | } while (0) | |
110 | ||
34f80b04 | 111 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 112 | do { \ |
34f80b04 | 113 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \ |
a2fbb9ea ET |
114 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
115 | offset, len32); \ | |
116 | } while (0) | |
117 | ||
34f80b04 EG |
118 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
119 | offsetof(struct shmem_region, field)) | |
120 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
121 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea ET |
122 | |
123 | #define NIG_WR(reg, val) REG_WR(bp, reg, val) | |
34f80b04 EG |
124 | #define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) |
125 | #define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) | |
a2fbb9ea ET |
126 | |
127 | ||
34f80b04 | 128 | #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) |
a2fbb9ea ET |
129 | |
130 | #define for_each_nondefault_queue(bp, var) \ | |
131 | for (var = 1; var < bp->num_queues; var++) | |
34f80b04 | 132 | #define is_multi(bp) (bp->num_queues > 1) |
a2fbb9ea ET |
133 | |
134 | ||
7a9b2557 | 135 | /* fast path */ |
a2fbb9ea | 136 | |
a2fbb9ea | 137 | struct sw_rx_bd { |
34f80b04 | 138 | struct sk_buff *skb; |
a2fbb9ea ET |
139 | DECLARE_PCI_UNMAP_ADDR(mapping) |
140 | }; | |
141 | ||
142 | struct sw_tx_bd { | |
34f80b04 EG |
143 | struct sk_buff *skb; |
144 | u16 first_bd; | |
a2fbb9ea ET |
145 | }; |
146 | ||
7a9b2557 VZ |
147 | struct sw_rx_page { |
148 | struct page *page; | |
149 | DECLARE_PCI_UNMAP_ADDR(mapping) | |
150 | }; | |
151 | ||
152 | ||
153 | /* MC hsi */ | |
154 | #define BCM_PAGE_SHIFT 12 | |
155 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
156 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
157 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | |
158 | ||
159 | #define PAGES_PER_SGE_SHIFT 0 | |
160 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
161 | ||
162 | /* SGE ring related macros */ | |
163 | #define NUM_RX_SGE_PAGES 2 | |
164 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) | |
165 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) | |
166 | /* RX_SGE_CNT is promissed to be a power of 2 */ | |
167 | #define RX_SGE_MASK (RX_SGE_CNT - 1) | |
168 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
169 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
170 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ | |
171 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | |
172 | #define RX_SGE(x) ((x) & MAX_RX_SGE) | |
173 | ||
174 | /* SGE producer mask related macros */ | |
175 | /* Number of bits in one sge_mask array element */ | |
176 | #define RX_SGE_MASK_ELEM_SZ 64 | |
177 | #define RX_SGE_MASK_ELEM_SHIFT 6 | |
178 | #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1) | |
179 | ||
180 | /* Creates a bitmask of all ones in less significant bits. | |
181 | idx - index of the most significant bit in the created mask */ | |
182 | #define RX_SGE_ONES_MASK(idx) \ | |
183 | (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) | |
184 | #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0)) | |
185 | ||
186 | /* Number of u64 elements in SGE mask array */ | |
187 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ | |
188 | RX_SGE_MASK_ELEM_SZ) | |
189 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) | |
190 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
191 | ||
192 | ||
a2fbb9ea ET |
193 | struct bnx2x_fastpath { |
194 | ||
34f80b04 | 195 | struct napi_struct napi; |
a2fbb9ea ET |
196 | |
197 | struct host_status_block *status_blk; | |
34f80b04 | 198 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 199 | |
34f80b04 EG |
200 | struct eth_tx_db_data *hw_tx_prods; |
201 | dma_addr_t tx_prods_mapping; | |
a2fbb9ea | 202 | |
34f80b04 | 203 | struct sw_tx_bd *tx_buf_ring; |
a2fbb9ea ET |
204 | |
205 | struct eth_tx_bd *tx_desc_ring; | |
34f80b04 | 206 | dma_addr_t tx_desc_mapping; |
a2fbb9ea | 207 | |
7a9b2557 VZ |
208 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
209 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
210 | |
211 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 212 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
213 | |
214 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
215 | dma_addr_t rx_comp_mapping; |
216 | ||
7a9b2557 VZ |
217 | /* SGE ring */ |
218 | struct eth_rx_sge *rx_sge_ring; | |
219 | dma_addr_t rx_sge_mapping; | |
220 | ||
221 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
222 | ||
34f80b04 EG |
223 | int state; |
224 | #define BNX2X_FP_STATE_CLOSED 0 | |
225 | #define BNX2X_FP_STATE_IRQ 0x80000 | |
226 | #define BNX2X_FP_STATE_OPENING 0x90000 | |
227 | #define BNX2X_FP_STATE_OPEN 0xa0000 | |
228 | #define BNX2X_FP_STATE_HALTING 0xb0000 | |
229 | #define BNX2X_FP_STATE_HALTED 0xc0000 | |
230 | ||
231 | u8 index; /* number in fp array */ | |
232 | u8 cl_id; /* eth client id */ | |
233 | u8 sb_id; /* status block number in HW */ | |
234 | #define FP_IDX(fp) (fp->index) | |
235 | #define FP_CL_ID(fp) (fp->cl_id) | |
236 | #define BP_CL_ID(bp) (bp->fp[0].cl_id) | |
237 | #define FP_SB_ID(fp) (fp->sb_id) | |
238 | #define CNIC_SB_ID 0 | |
239 | ||
240 | u16 tx_pkt_prod; | |
241 | u16 tx_pkt_cons; | |
242 | u16 tx_bd_prod; | |
243 | u16 tx_bd_cons; | |
244 | u16 *tx_cons_sb; | |
245 | ||
246 | u16 fp_c_idx; | |
247 | u16 fp_u_idx; | |
248 | ||
249 | u16 rx_bd_prod; | |
250 | u16 rx_bd_cons; | |
251 | u16 rx_comp_prod; | |
252 | u16 rx_comp_cons; | |
7a9b2557 VZ |
253 | u16 rx_sge_prod; |
254 | /* The last maximal completed SGE */ | |
255 | u16 last_max_sge; | |
34f80b04 | 256 | u16 *rx_cons_sb; |
7a9b2557 | 257 | u16 *rx_bd_cons_sb; |
34f80b04 EG |
258 | |
259 | unsigned long tx_pkt, | |
a2fbb9ea | 260 | rx_pkt, |
66e855f3 | 261 | rx_calls; |
7a9b2557 VZ |
262 | /* TPA related */ |
263 | struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
264 | u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
265 | #define BNX2X_TPA_START 1 | |
266 | #define BNX2X_TPA_STOP 2 | |
267 | u8 disable_tpa; | |
268 | #ifdef BNX2X_STOP_ON_ERROR | |
269 | u64 tpa_queue_used; | |
270 | #endif | |
a2fbb9ea | 271 | |
34f80b04 | 272 | struct bnx2x *bp; /* parent */ |
a2fbb9ea ET |
273 | }; |
274 | ||
34f80b04 | 275 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
7a9b2557 | 276 | |
da5a662a VZ |
277 | #define BNX2X_HAS_TX_WORK(fp) \ |
278 | ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \ | |
279 | (fp->tx_pkt_prod != fp->tx_pkt_cons)) | |
280 | ||
281 | #define BNX2X_HAS_RX_WORK(fp) \ | |
282 | (fp->rx_comp_cons != le16_to_cpu(*fp->rx_cons_sb)) | |
283 | ||
284 | #define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp)) | |
285 | ||
7a9b2557 VZ |
286 | |
287 | /* MC hsi */ | |
288 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ | |
289 | #define RX_COPY_THRESH 92 | |
290 | ||
291 | #define NUM_TX_RINGS 16 | |
292 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) | |
293 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) | |
294 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
295 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
296 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
297 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ | |
298 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
299 | #define TX_BD(x) ((x) & MAX_TX_BD) | |
300 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
301 | ||
302 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
303 | #define NUM_RX_RINGS 8 | |
304 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | |
305 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | |
306 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
307 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
308 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
309 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
310 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ | |
311 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
312 | #define RX_BD(x) ((x) & MAX_RX_BD) | |
313 | ||
314 | /* As long as CQE is 4 times bigger than BD entry we have to allocate | |
315 | 4 times more pages for CQ ring in order to keep it balanced with | |
316 | BD ring */ | |
317 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4) | |
318 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | |
319 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | |
320 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
321 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
322 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
323 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | |
324 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
325 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | |
326 | ||
327 | ||
34f80b04 EG |
328 | /* This is needed for determening of last_max */ |
329 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) | |
a2fbb9ea | 330 | |
7a9b2557 VZ |
331 | #define __SGE_MASK_SET_BIT(el, bit) \ |
332 | do { \ | |
333 | el = ((el) | ((u64)0x1 << (bit))); \ | |
334 | } while (0) | |
335 | ||
336 | #define __SGE_MASK_CLEAR_BIT(el, bit) \ | |
337 | do { \ | |
338 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
339 | } while (0) | |
340 | ||
341 | #define SGE_MASK_SET_BIT(fp, idx) \ | |
342 | __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
343 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
344 | ||
345 | #define SGE_MASK_CLEAR_BIT(fp, idx) \ | |
346 | __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
347 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
348 | ||
349 | ||
350 | /* used on a CID received from the HW */ | |
351 | #define SW_CID(x) (le32_to_cpu(x) & \ | |
352 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 7)) | |
353 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ | |
354 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
355 | ||
bb2a0f7a YG |
356 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
357 | le32_to_cpu((bd)->addr_lo)) | |
358 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
359 | ||
7a9b2557 VZ |
360 | |
361 | #define DPM_TRIGER_TYPE 0x40 | |
362 | #define DOORBELL(bp, cid, val) \ | |
363 | do { \ | |
364 | writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \ | |
365 | DPM_TRIGER_TYPE); \ | |
366 | } while (0) | |
367 | ||
368 | ||
369 | /* TX CSUM helpers */ | |
370 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
371 | skb->csum_offset) | |
372 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
373 | skb->csum_offset)) | |
374 | ||
375 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
376 | ||
377 | #define XMIT_PLAIN 0 | |
378 | #define XMIT_CSUM_V4 0x1 | |
379 | #define XMIT_CSUM_V6 0x2 | |
380 | #define XMIT_CSUM_TCP 0x4 | |
381 | #define XMIT_GSO_V4 0x8 | |
382 | #define XMIT_GSO_V6 0x10 | |
383 | ||
384 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
385 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
386 | ||
387 | ||
34f80b04 | 388 | /* stuff added to make the code fit 80Col */ |
a2fbb9ea | 389 | |
34f80b04 | 390 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
a2fbb9ea | 391 | |
7a9b2557 VZ |
392 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
393 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG | |
394 | #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ | |
395 | (TPA_TYPE_START | TPA_TYPE_END)) | |
396 | ||
1adcd8be EG |
397 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
398 | ||
399 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
400 | (!((cqe)->fast_path_cqe.status_flags & \ | |
401 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
402 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
403 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
404 | ||
405 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
406 | (!((cqe)->fast_path_cqe.status_flags & \ | |
407 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
408 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
409 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
410 | ||
411 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
412 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 VZ |
413 | |
414 | #define BNX2X_RX_SUM_FIX(cqe) \ | |
415 | ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ | |
416 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ | |
417 | (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) | |
418 | ||
a2fbb9ea | 419 | |
bb2a0f7a YG |
420 | #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) |
421 | #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) | |
422 | ||
34f80b04 EG |
423 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS |
424 | #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS | |
425 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS | |
a2fbb9ea | 426 | |
34f80b04 EG |
427 | #define BNX2X_RX_SB_INDEX \ |
428 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]) | |
a2fbb9ea | 429 | |
34f80b04 EG |
430 | #define BNX2X_RX_SB_BD_INDEX \ |
431 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX]) | |
a2fbb9ea | 432 | |
34f80b04 EG |
433 | #define BNX2X_RX_SB_INDEX_NUM \ |
434 | (((U_SB_ETH_RX_CQ_INDEX << \ | |
435 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \ | |
436 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \ | |
437 | ((U_SB_ETH_RX_BD_INDEX << \ | |
438 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \ | |
439 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER)) | |
a2fbb9ea | 440 | |
34f80b04 EG |
441 | #define BNX2X_TX_SB_INDEX \ |
442 | (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]) | |
a2fbb9ea | 443 | |
7a9b2557 VZ |
444 | |
445 | /* end of fast path */ | |
446 | ||
34f80b04 | 447 | /* common */ |
a2fbb9ea | 448 | |
34f80b04 | 449 | struct bnx2x_common { |
a2fbb9ea | 450 | |
ad8d3948 | 451 | u32 chip_id; |
a2fbb9ea | 452 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 453 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 454 | |
34f80b04 | 455 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
456 | #define CHIP_NUM_57710 0x164e |
457 | #define CHIP_NUM_57711 0x164f | |
458 | #define CHIP_NUM_57711E 0x1650 | |
459 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) | |
460 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
461 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
462 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ | |
463 | CHIP_IS_57711E(bp)) | |
464 | #define IS_E1H_OFFSET CHIP_IS_E1H(bp) | |
465 | ||
34f80b04 | 466 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
ad8d3948 EG |
467 | #define CHIP_REV_Ax 0x00000000 |
468 | /* assume maximum 5 revisions */ | |
469 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | |
470 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ | |
471 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
472 | !(CHIP_REV(bp) & 0x00001000)) | |
473 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ | |
474 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
475 | (CHIP_REV(bp) & 0x00001000)) | |
476 | ||
477 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
478 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
479 | ||
34f80b04 EG |
480 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
481 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
a2fbb9ea | 482 | |
34f80b04 EG |
483 | int flash_size; |
484 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | |
485 | #define NVRAM_TIMEOUT_COUNT 30000 | |
486 | #define NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 487 | |
34f80b04 EG |
488 | u32 shmem_base; |
489 | ||
490 | u32 hw_config; | |
f1410647 | 491 | u32 board; |
c18487ee | 492 | |
34f80b04 EG |
493 | u32 bc_ver; |
494 | ||
495 | char *name; | |
496 | }; | |
c18487ee | 497 | |
34f80b04 EG |
498 | |
499 | /* end of common */ | |
500 | ||
501 | /* port */ | |
502 | ||
bb2a0f7a YG |
503 | struct nig_stats { |
504 | u32 brb_discard; | |
505 | u32 brb_packet; | |
506 | u32 brb_truncate; | |
507 | u32 flow_ctrl_discard; | |
508 | u32 flow_ctrl_octets; | |
509 | u32 flow_ctrl_packet; | |
510 | u32 mng_discard; | |
511 | u32 mng_octet_inp; | |
512 | u32 mng_octet_out; | |
513 | u32 mng_packet_inp; | |
514 | u32 mng_packet_out; | |
515 | u32 pbf_octets; | |
516 | u32 pbf_packet; | |
517 | u32 safc_inp; | |
518 | u32 egress_mac_pkt0_lo; | |
519 | u32 egress_mac_pkt0_hi; | |
520 | u32 egress_mac_pkt1_lo; | |
521 | u32 egress_mac_pkt1_hi; | |
522 | }; | |
523 | ||
34f80b04 EG |
524 | struct bnx2x_port { |
525 | u32 pmf; | |
c18487ee YR |
526 | |
527 | u32 link_config; | |
a2fbb9ea | 528 | |
34f80b04 EG |
529 | u32 supported; |
530 | /* link settings - missing defines */ | |
531 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
532 | ||
533 | u32 advertising; | |
a2fbb9ea | 534 | /* link settings - missing defines */ |
34f80b04 | 535 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 536 | |
34f80b04 | 537 | u32 phy_addr; |
c18487ee YR |
538 | |
539 | /* used to synchronize phy accesses */ | |
540 | struct mutex phy_mutex; | |
541 | ||
34f80b04 | 542 | u32 port_stx; |
a2fbb9ea | 543 | |
34f80b04 EG |
544 | struct nig_stats old_nig_stats; |
545 | }; | |
a2fbb9ea | 546 | |
34f80b04 EG |
547 | /* end of port */ |
548 | ||
bb2a0f7a YG |
549 | |
550 | enum bnx2x_stats_event { | |
551 | STATS_EVENT_PMF = 0, | |
552 | STATS_EVENT_LINK_UP, | |
553 | STATS_EVENT_UPDATE, | |
554 | STATS_EVENT_STOP, | |
555 | STATS_EVENT_MAX | |
556 | }; | |
557 | ||
558 | enum bnx2x_stats_state { | |
559 | STATS_STATE_DISABLED = 0, | |
560 | STATS_STATE_ENABLED, | |
561 | STATS_STATE_MAX | |
562 | }; | |
563 | ||
564 | struct bnx2x_eth_stats { | |
565 | u32 total_bytes_received_hi; | |
566 | u32 total_bytes_received_lo; | |
567 | u32 total_bytes_transmitted_hi; | |
568 | u32 total_bytes_transmitted_lo; | |
569 | u32 total_unicast_packets_received_hi; | |
570 | u32 total_unicast_packets_received_lo; | |
571 | u32 total_multicast_packets_received_hi; | |
572 | u32 total_multicast_packets_received_lo; | |
573 | u32 total_broadcast_packets_received_hi; | |
574 | u32 total_broadcast_packets_received_lo; | |
575 | u32 total_unicast_packets_transmitted_hi; | |
576 | u32 total_unicast_packets_transmitted_lo; | |
577 | u32 total_multicast_packets_transmitted_hi; | |
578 | u32 total_multicast_packets_transmitted_lo; | |
579 | u32 total_broadcast_packets_transmitted_hi; | |
580 | u32 total_broadcast_packets_transmitted_lo; | |
581 | u32 valid_bytes_received_hi; | |
582 | u32 valid_bytes_received_lo; | |
583 | ||
584 | u32 error_bytes_received_hi; | |
585 | u32 error_bytes_received_lo; | |
586 | ||
587 | u32 rx_stat_ifhcinbadoctets_hi; | |
588 | u32 rx_stat_ifhcinbadoctets_lo; | |
589 | u32 tx_stat_ifhcoutbadoctets_hi; | |
590 | u32 tx_stat_ifhcoutbadoctets_lo; | |
591 | u32 rx_stat_dot3statsfcserrors_hi; | |
592 | u32 rx_stat_dot3statsfcserrors_lo; | |
593 | u32 rx_stat_dot3statsalignmenterrors_hi; | |
594 | u32 rx_stat_dot3statsalignmenterrors_lo; | |
595 | u32 rx_stat_dot3statscarriersenseerrors_hi; | |
596 | u32 rx_stat_dot3statscarriersenseerrors_lo; | |
597 | u32 rx_stat_falsecarriererrors_hi; | |
598 | u32 rx_stat_falsecarriererrors_lo; | |
599 | u32 rx_stat_etherstatsundersizepkts_hi; | |
600 | u32 rx_stat_etherstatsundersizepkts_lo; | |
601 | u32 rx_stat_dot3statsframestoolong_hi; | |
602 | u32 rx_stat_dot3statsframestoolong_lo; | |
603 | u32 rx_stat_etherstatsfragments_hi; | |
604 | u32 rx_stat_etherstatsfragments_lo; | |
605 | u32 rx_stat_etherstatsjabbers_hi; | |
606 | u32 rx_stat_etherstatsjabbers_lo; | |
607 | u32 rx_stat_maccontrolframesreceived_hi; | |
608 | u32 rx_stat_maccontrolframesreceived_lo; | |
609 | u32 rx_stat_bmac_xpf_hi; | |
610 | u32 rx_stat_bmac_xpf_lo; | |
611 | u32 rx_stat_bmac_xcf_hi; | |
612 | u32 rx_stat_bmac_xcf_lo; | |
613 | u32 rx_stat_xoffstateentered_hi; | |
614 | u32 rx_stat_xoffstateentered_lo; | |
615 | u32 rx_stat_xonpauseframesreceived_hi; | |
616 | u32 rx_stat_xonpauseframesreceived_lo; | |
617 | u32 rx_stat_xoffpauseframesreceived_hi; | |
618 | u32 rx_stat_xoffpauseframesreceived_lo; | |
619 | u32 tx_stat_outxonsent_hi; | |
620 | u32 tx_stat_outxonsent_lo; | |
621 | u32 tx_stat_outxoffsent_hi; | |
622 | u32 tx_stat_outxoffsent_lo; | |
623 | u32 tx_stat_flowcontroldone_hi; | |
624 | u32 tx_stat_flowcontroldone_lo; | |
625 | u32 tx_stat_etherstatscollisions_hi; | |
626 | u32 tx_stat_etherstatscollisions_lo; | |
627 | u32 tx_stat_dot3statssinglecollisionframes_hi; | |
628 | u32 tx_stat_dot3statssinglecollisionframes_lo; | |
629 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; | |
630 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; | |
631 | u32 tx_stat_dot3statsdeferredtransmissions_hi; | |
632 | u32 tx_stat_dot3statsdeferredtransmissions_lo; | |
633 | u32 tx_stat_dot3statsexcessivecollisions_hi; | |
634 | u32 tx_stat_dot3statsexcessivecollisions_lo; | |
635 | u32 tx_stat_dot3statslatecollisions_hi; | |
636 | u32 tx_stat_dot3statslatecollisions_lo; | |
637 | u32 tx_stat_etherstatspkts64octets_hi; | |
638 | u32 tx_stat_etherstatspkts64octets_lo; | |
639 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; | |
640 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; | |
641 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; | |
642 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; | |
643 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; | |
644 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; | |
645 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; | |
646 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; | |
647 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; | |
648 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; | |
649 | u32 tx_stat_etherstatspktsover1522octets_hi; | |
650 | u32 tx_stat_etherstatspktsover1522octets_lo; | |
651 | u32 tx_stat_bmac_2047_hi; | |
652 | u32 tx_stat_bmac_2047_lo; | |
653 | u32 tx_stat_bmac_4095_hi; | |
654 | u32 tx_stat_bmac_4095_lo; | |
655 | u32 tx_stat_bmac_9216_hi; | |
656 | u32 tx_stat_bmac_9216_lo; | |
657 | u32 tx_stat_bmac_16383_hi; | |
658 | u32 tx_stat_bmac_16383_lo; | |
659 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; | |
660 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; | |
661 | u32 tx_stat_bmac_ufl_hi; | |
662 | u32 tx_stat_bmac_ufl_lo; | |
663 | ||
664 | u32 brb_drop_hi; | |
665 | u32 brb_drop_lo; | |
66e855f3 YG |
666 | u32 brb_truncate_hi; |
667 | u32 brb_truncate_lo; | |
bb2a0f7a YG |
668 | |
669 | u32 jabber_packets_received; | |
670 | ||
671 | u32 etherstatspkts1024octetsto1522octets_hi; | |
672 | u32 etherstatspkts1024octetsto1522octets_lo; | |
673 | u32 etherstatspktsover1522octets_hi; | |
674 | u32 etherstatspktsover1522octets_lo; | |
675 | ||
676 | u32 no_buff_discard; | |
677 | ||
678 | u32 mac_filter_discard; | |
679 | u32 xxoverflow_discard; | |
680 | u32 brb_truncate_discard; | |
681 | u32 mac_discard; | |
682 | ||
683 | u32 driver_xoff; | |
66e855f3 YG |
684 | u32 rx_err_discard_pkt; |
685 | u32 rx_skb_alloc_failed; | |
686 | u32 hw_csum_err; | |
bb2a0f7a YG |
687 | }; |
688 | ||
689 | #define STATS_OFFSET32(stat_name) \ | |
690 | (offsetof(struct bnx2x_eth_stats, stat_name) / 4) | |
691 | ||
34f80b04 EG |
692 | |
693 | #ifdef BNX2X_MULTI | |
694 | #define MAX_CONTEXT 16 | |
695 | #else | |
696 | #define MAX_CONTEXT 1 | |
697 | #endif | |
698 | ||
699 | union cdu_context { | |
700 | struct eth_context eth; | |
701 | char pad[1024]; | |
702 | }; | |
703 | ||
bb2a0f7a | 704 | #define MAX_DMAE_C 8 |
34f80b04 EG |
705 | |
706 | /* DMA memory not used in fastpath */ | |
707 | struct bnx2x_slowpath { | |
708 | union cdu_context context[MAX_CONTEXT]; | |
709 | struct eth_stats_query fw_stats; | |
710 | struct mac_configuration_cmd mac_config; | |
711 | struct mac_configuration_cmd mcast_config; | |
712 | ||
713 | /* used by dmae command executer */ | |
714 | struct dmae_command dmae[MAX_DMAE_C]; | |
715 | ||
bb2a0f7a YG |
716 | u32 stats_comp; |
717 | union mac_stats mac_stats; | |
718 | struct nig_stats nig_stats; | |
719 | struct host_port_stats port_stats; | |
720 | struct host_func_stats func_stats; | |
34f80b04 EG |
721 | |
722 | u32 wb_comp; | |
34f80b04 EG |
723 | u32 wb_data[4]; |
724 | }; | |
725 | ||
726 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
727 | #define bnx2x_sp_mapping(bp, var) \ | |
728 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
729 | ||
730 | ||
731 | /* attn group wiring */ | |
732 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
733 | ||
734 | struct attn_route { | |
735 | u32 sig[4]; | |
736 | }; | |
737 | ||
738 | struct bnx2x { | |
739 | /* Fields used in the tx and intr/napi performance paths | |
740 | * are grouped together in the beginning of the structure | |
741 | */ | |
742 | struct bnx2x_fastpath fp[MAX_CONTEXT]; | |
743 | void __iomem *regview; | |
744 | void __iomem *doorbells; | |
745 | #define BNX2X_DB_SIZE (16*2048) | |
746 | ||
747 | struct net_device *dev; | |
748 | struct pci_dev *pdev; | |
749 | ||
750 | atomic_t intr_sem; | |
7a9b2557 | 751 | struct msix_entry msix_table[MAX_CONTEXT+1]; |
34f80b04 EG |
752 | |
753 | int tx_ring_size; | |
754 | ||
755 | #ifdef BCM_VLAN | |
756 | struct vlan_group *vlgrp; | |
757 | #endif | |
a2fbb9ea | 758 | |
34f80b04 EG |
759 | u32 rx_csum; |
760 | u32 rx_offset; | |
761 | u32 rx_buf_use_size; /* useable size */ | |
762 | u32 rx_buf_size; /* with alignment */ | |
763 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ | |
764 | #define ETH_MIN_PACKET_SIZE 60 | |
765 | #define ETH_MAX_PACKET_SIZE 1500 | |
766 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 767 | |
34f80b04 EG |
768 | struct host_def_status_block *def_status_blk; |
769 | #define DEF_SB_ID 16 | |
770 | u16 def_c_idx; | |
771 | u16 def_u_idx; | |
772 | u16 def_x_idx; | |
773 | u16 def_t_idx; | |
774 | u16 def_att_idx; | |
775 | u32 attn_state; | |
776 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
777 | u32 nig_mask; |
778 | ||
779 | /* slow path ring */ | |
780 | struct eth_spe *spq; | |
781 | dma_addr_t spq_mapping; | |
782 | u16 spq_prod_idx; | |
783 | struct eth_spe *spq_prod_bd; | |
784 | struct eth_spe *spq_last_bd; | |
785 | u16 *dsb_sp_prod; | |
786 | u16 spq_left; /* serialize spq */ | |
787 | /* used to synchronize spq accesses */ | |
788 | spinlock_t spq_lock; | |
789 | ||
bb2a0f7a YG |
790 | /* Flags for marking that there is a STAT_QUERY or |
791 | SET_MAC ramrod pending */ | |
792 | u8 stats_pending; | |
793 | u8 set_mac_pending; | |
34f80b04 EG |
794 | |
795 | /* End of fileds used in the performance code paths */ | |
796 | ||
797 | int panic; | |
798 | int msglevel; | |
799 | ||
800 | u32 flags; | |
801 | #define PCIX_FLAG 1 | |
802 | #define PCI_32BIT_FLAG 2 | |
803 | #define ONE_TDMA_FLAG 4 /* no longer used */ | |
804 | #define NO_WOL_FLAG 8 | |
805 | #define USING_DAC_FLAG 0x10 | |
806 | #define USING_MSIX_FLAG 0x20 | |
807 | #define ASF_ENABLE_FLAG 0x40 | |
7a9b2557 | 808 | #define TPA_ENABLE_FLAG 0x80 |
34f80b04 EG |
809 | #define NO_MCP_FLAG 0x100 |
810 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) | |
811 | ||
812 | int func; | |
813 | #define BP_PORT(bp) (bp->func % PORT_MAX) | |
814 | #define BP_FUNC(bp) (bp->func) | |
815 | #define BP_E1HVN(bp) (bp->func >> 1) | |
816 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) | |
817 | /* assorted E1HVN */ | |
818 | #define IS_E1HMF(bp) (bp->e1hmf != 0) | |
819 | #define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16) | |
820 | ||
821 | int pm_cap; | |
822 | int pcie_cap; | |
823 | ||
824 | struct work_struct sp_task; | |
825 | struct work_struct reset_task; | |
826 | ||
827 | struct timer_list timer; | |
828 | int timer_interval; | |
829 | int current_interval; | |
830 | ||
831 | u16 fw_seq; | |
832 | u16 fw_drv_pulse_wr_seq; | |
833 | u32 func_stx; | |
834 | ||
835 | struct link_params link_params; | |
836 | struct link_vars link_vars; | |
a2fbb9ea | 837 | |
34f80b04 EG |
838 | struct bnx2x_common common; |
839 | struct bnx2x_port port; | |
840 | ||
841 | u32 mf_config; | |
842 | u16 e1hov; | |
843 | u8 e1hmf; | |
a2fbb9ea | 844 | |
f1410647 ET |
845 | u8 wol; |
846 | ||
34f80b04 | 847 | int rx_ring_size; |
a2fbb9ea | 848 | |
34f80b04 EG |
849 | u16 tx_quick_cons_trip_int; |
850 | u16 tx_quick_cons_trip; | |
851 | u16 tx_ticks_int; | |
852 | u16 tx_ticks; | |
a2fbb9ea | 853 | |
34f80b04 EG |
854 | u16 rx_quick_cons_trip_int; |
855 | u16 rx_quick_cons_trip; | |
856 | u16 rx_ticks_int; | |
857 | u16 rx_ticks; | |
a2fbb9ea | 858 | |
34f80b04 | 859 | u32 lin_cnt; |
a2fbb9ea | 860 | |
34f80b04 EG |
861 | int state; |
862 | #define BNX2X_STATE_CLOSED 0x0 | |
863 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 | |
864 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 865 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 866 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea ET |
867 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
868 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | |
34f80b04 EG |
869 | #define BNX2X_STATE_DISABLED 0xd000 |
870 | #define BNX2X_STATE_DIAG 0xe000 | |
871 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 872 | |
34f80b04 | 873 | int num_queues; |
a2fbb9ea | 874 | |
34f80b04 EG |
875 | u32 rx_mode; |
876 | #define BNX2X_RX_MODE_NONE 0 | |
877 | #define BNX2X_RX_MODE_NORMAL 1 | |
878 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
879 | #define BNX2X_RX_MODE_PROMISC 3 | |
880 | #define BNX2X_MAX_MULTICAST 64 | |
881 | #define BNX2X_MAX_EMUL_MULTI 16 | |
a2fbb9ea | 882 | |
34f80b04 | 883 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 884 | |
34f80b04 EG |
885 | struct bnx2x_slowpath *slowpath; |
886 | dma_addr_t slowpath_mapping; | |
a2fbb9ea ET |
887 | |
888 | #ifdef BCM_ISCSI | |
889 | void *t1; | |
890 | dma_addr_t t1_mapping; | |
891 | void *t2; | |
892 | dma_addr_t t2_mapping; | |
893 | void *timers; | |
894 | dma_addr_t timers_mapping; | |
895 | void *qm; | |
896 | dma_addr_t qm_mapping; | |
897 | #endif | |
898 | ||
ad8d3948 EG |
899 | int dmae_ready; |
900 | /* used to synchronize dmae accesses */ | |
901 | struct mutex dmae_mutex; | |
902 | struct dmae_command init_dmae; | |
903 | ||
bb2a0f7a YG |
904 | /* used to synchronize stats collecting */ |
905 | int stats_state; | |
906 | /* used by dmae command loader */ | |
907 | struct dmae_command stats_dmae; | |
908 | int executer_idx; | |
ad8d3948 | 909 | |
bb2a0f7a | 910 | u16 stats_counter; |
a2fbb9ea | 911 | struct tstorm_per_client_stats old_tclient; |
bb2a0f7a YG |
912 | struct xstorm_per_client_stats old_xclient; |
913 | struct bnx2x_eth_stats eth_stats; | |
914 | ||
915 | struct z_stream_s *strm; | |
916 | void *gunzip_buf; | |
917 | dma_addr_t gunzip_mapping; | |
918 | int gunzip_outlen; | |
ad8d3948 | 919 | #define FW_BUF_SIZE 0x8000 |
a2fbb9ea ET |
920 | |
921 | }; | |
922 | ||
923 | ||
c18487ee YR |
924 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
925 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
926 | u32 len32); | |
17de50b7 | 927 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
c18487ee | 928 | |
34f80b04 EG |
929 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
930 | int wait) | |
931 | { | |
932 | u32 val; | |
933 | ||
934 | do { | |
935 | val = REG_RD(bp, reg); | |
936 | if (val == expected) | |
937 | break; | |
938 | ms -= wait; | |
939 | msleep(wait); | |
940 | ||
941 | } while (ms > 0); | |
942 | ||
943 | return val; | |
944 | } | |
945 | ||
946 | ||
947 | /* load/unload mode */ | |
948 | #define LOAD_NORMAL 0 | |
949 | #define LOAD_OPEN 1 | |
950 | #define LOAD_DIAG 2 | |
951 | #define UNLOAD_NORMAL 0 | |
952 | #define UNLOAD_CLOSE 1 | |
953 | ||
bb2a0f7a | 954 | |
ad8d3948 EG |
955 | /* DMAE command defines */ |
956 | #define DMAE_CMD_SRC_PCI 0 | |
957 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC | |
958 | ||
959 | #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT) | |
960 | #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT) | |
961 | ||
962 | #define DMAE_CMD_C_DST_PCI 0 | |
963 | #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) | |
964 | ||
965 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
966 | ||
967 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
968 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
969 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
970 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
971 | ||
972 | #define DMAE_CMD_PORT_0 0 | |
973 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
974 | ||
975 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
976 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
977 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
978 | ||
979 | #define DMAE_LEN32_RD_MAX 0x80 | |
980 | #define DMAE_LEN32_WR_MAX 0x400 | |
981 | ||
982 | #define DMAE_COMP_VAL 0xe0d0d0ae | |
983 | ||
984 | #define MAX_DMAE_C_PER_PORT 8 | |
985 | #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ | |
986 | BP_E1HVN(bp)) | |
987 | #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ | |
988 | E1HVN_MAX) | |
989 | ||
990 | ||
25047950 ET |
991 | /* PCIE link and speed */ |
992 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
993 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
994 | #define PCICFG_LINK_SPEED 0xf0000 | |
995 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 996 | |
bb2a0f7a | 997 | |
66e855f3 | 998 | #define BNX2X_NUM_STATS 42 |
bb2a0f7a YG |
999 | #define BNX2X_NUM_TESTS 8 |
1000 | ||
1001 | #define BNX2X_MAC_LOOPBACK 0 | |
1002 | #define BNX2X_PHY_LOOPBACK 1 | |
1003 | #define BNX2X_MAC_LOOPBACK_FAILED 1 | |
1004 | #define BNX2X_PHY_LOOPBACK_FAILED 2 | |
1005 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ | |
1006 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1007 | |
7a9b2557 VZ |
1008 | |
1009 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1010 | ||
96fc1784 | 1011 | |
34f80b04 | 1012 | /* must be used on a CID before placing it on a HW ring */ |
7a9b2557 VZ |
1013 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x) |
1014 | ||
1015 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1016 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1017 | ||
1018 | ||
1019 | #define BNX2X_BTR 3 | |
1020 | #define MAX_SPQ_PENDING 8 | |
a2fbb9ea | 1021 | |
a2fbb9ea | 1022 | |
34f80b04 EG |
1023 | /* CMNG constants |
1024 | derived from lab experiments, and not from system spec calculations !!! */ | |
1025 | #define DEF_MIN_RATE 100 | |
1026 | /* resolution of the rate shaping timer - 100 usec */ | |
1027 | #define RS_PERIODIC_TIMEOUT_USEC 100 | |
1028 | /* resolution of fairness algorithm in usecs - | |
1029 | coefficient for clauclating the actuall t fair */ | |
1030 | #define T_FAIR_COEF 10000000 | |
1031 | /* number of bytes in single QM arbitration cycle - | |
1032 | coeffiecnt for calculating the fairness timer */ | |
1033 | #define QM_ARB_BYTES 40000 | |
1034 | #define FAIR_MEM 2 | |
1035 | ||
1036 | ||
1037 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1038 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1039 | #define GPIO_2_FUNC (1L << 10) | |
1040 | #define GPIO_3_FUNC (1L << 11) | |
1041 | #define GPIO_4_FUNC (1L << 12) | |
1042 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1043 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1044 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1045 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1046 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1047 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1048 | ||
1049 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1050 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1051 | |
1052 | ||
34f80b04 EG |
1053 | /* stuff added to make the code fit 80Col */ |
1054 | ||
1055 | #define BNX2X_PMF_LINK_ASSERT \ | |
1056 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1057 | ||
a2fbb9ea ET |
1058 | #define BNX2X_MC_ASSERT_BITS \ |
1059 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1060 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1061 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1062 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1063 | ||
1064 | #define BNX2X_MCP_ASSERT \ | |
1065 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1066 | ||
1067 | #define BNX2X_DOORQ_ASSERT \ | |
1068 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT | |
1069 | ||
34f80b04 EG |
1070 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1071 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1072 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1073 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1074 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1075 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1076 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1077 | ||
a2fbb9ea ET |
1078 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1079 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1080 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1081 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1082 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | |
34f80b04 | 1083 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1084 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1085 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1086 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1087 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) | |
1088 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1089 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1090 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1091 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1092 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1093 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1094 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1095 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1096 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1097 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1098 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1099 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
34f80b04 | 1100 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
a2fbb9ea ET |
1101 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
1102 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1103 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
1104 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ | |
1105 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
1106 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ | |
1107 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1108 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1109 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1110 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) | |
1111 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1112 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1113 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1114 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1115 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1116 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1117 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1118 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1119 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1120 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1121 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1122 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1123 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1124 | ||
1125 | ||
a2fbb9ea | 1126 | #define MULTI_FLAGS \ |
34f80b04 EG |
1127 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
1128 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1129 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1130 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
1131 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) | |
a2fbb9ea | 1132 | |
34f80b04 | 1133 | #define MULTI_MASK 0x7f |
a2fbb9ea ET |
1134 | |
1135 | ||
34f80b04 EG |
1136 | #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES) |
1137 | #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES) | |
1138 | #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES) | |
1139 | #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES) | |
a2fbb9ea | 1140 | |
34f80b04 | 1141 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH |
a2fbb9ea ET |
1142 | |
1143 | #define BNX2X_SP_DSB_INDEX \ | |
34f80b04 | 1144 | (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]) |
a2fbb9ea ET |
1145 | |
1146 | ||
1147 | #define CAM_IS_INVALID(x) \ | |
1148 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) | |
1149 | ||
1150 | #define CAM_INVALIDATE(x) \ | |
34f80b04 EG |
1151 | (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
1152 | ||
1153 | ||
1154 | /* Number of u32 elements in MC hash array */ | |
1155 | #define MC_HASH_SIZE 8 | |
1156 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1157 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
1158 | |
1159 | ||
34f80b04 EG |
1160 | #ifndef PXP2_REG_PXP2_INT_STS |
1161 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1162 | #endif | |
1163 | ||
a2fbb9ea ET |
1164 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ |
1165 | ||
1166 | #endif /* bnx2x.h */ |