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bbb84619 BS |
1 | /* |
2 | * Blackfin On-Chip CAN Driver | |
3 | * | |
4 | * Copyright 2004-2009 Analog Devices Inc. | |
5 | * | |
6 | * Enter bugs at http://blackfin.uclinux.org/ | |
7 | * | |
8 | * Licensed under the GPL-2 or later. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/bitops.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/skbuff.h> | |
19 | #include <linux/platform_device.h> | |
20 | ||
bbb84619 BS |
21 | #include <linux/can/dev.h> |
22 | #include <linux/can/error.h> | |
23 | ||
21afc27c | 24 | #include <asm/bfin_can.h> |
bbb84619 BS |
25 | #include <asm/portmux.h> |
26 | ||
27 | #define DRV_NAME "bfin_can" | |
28 | #define BFIN_CAN_TIMEOUT 100 | |
e9dcd161 | 29 | #define TX_ECHO_SKB_MAX 1 |
bbb84619 | 30 | |
bbb84619 BS |
31 | /* |
32 | * bfin can private data | |
33 | */ | |
34 | struct bfin_can_priv { | |
35 | struct can_priv can; /* must be the first member */ | |
36 | struct net_device *dev; | |
37 | void __iomem *membase; | |
38 | int rx_irq; | |
39 | int tx_irq; | |
40 | int err_irq; | |
41 | unsigned short *pin_list; | |
42 | }; | |
43 | ||
44 | /* | |
45 | * bfin can timing parameters | |
46 | */ | |
194b9a4c | 47 | static const struct can_bittiming_const bfin_can_bittiming_const = { |
bbb84619 BS |
48 | .name = DRV_NAME, |
49 | .tseg1_min = 1, | |
50 | .tseg1_max = 16, | |
51 | .tseg2_min = 1, | |
52 | .tseg2_max = 8, | |
53 | .sjw_max = 4, | |
54 | /* | |
55 | * Although the BRP field can be set to any value, it is recommended | |
56 | * that the value be greater than or equal to 4, as restrictions | |
57 | * apply to the bit timing configuration when BRP is less than 4. | |
58 | */ | |
59 | .brp_min = 4, | |
60 | .brp_max = 1024, | |
61 | .brp_inc = 1, | |
62 | }; | |
63 | ||
64 | static int bfin_can_set_bittiming(struct net_device *dev) | |
65 | { | |
66 | struct bfin_can_priv *priv = netdev_priv(dev); | |
67 | struct bfin_can_regs __iomem *reg = priv->membase; | |
68 | struct can_bittiming *bt = &priv->can.bittiming; | |
69 | u16 clk, timing; | |
70 | ||
71 | clk = bt->brp - 1; | |
72 | timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) | | |
73 | ((bt->phase_seg2 - 1) << 4); | |
74 | ||
75 | /* | |
76 | * If the SAM bit is set, the input signal is oversampled three times | |
77 | * at the SCLK rate. | |
78 | */ | |
79 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | |
80 | timing |= SAM; | |
81 | ||
cfbf7586 MF |
82 | bfin_write(®->clock, clk); |
83 | bfin_write(®->timing, timing); | |
bbb84619 | 84 | |
aabdfd6a | 85 | netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing); |
bbb84619 BS |
86 | |
87 | return 0; | |
88 | } | |
89 | ||
90 | static void bfin_can_set_reset_mode(struct net_device *dev) | |
91 | { | |
92 | struct bfin_can_priv *priv = netdev_priv(dev); | |
93 | struct bfin_can_regs __iomem *reg = priv->membase; | |
94 | int timeout = BFIN_CAN_TIMEOUT; | |
95 | int i; | |
96 | ||
97 | /* disable interrupts */ | |
cfbf7586 MF |
98 | bfin_write(®->mbim1, 0); |
99 | bfin_write(®->mbim2, 0); | |
100 | bfin_write(®->gim, 0); | |
bbb84619 BS |
101 | |
102 | /* reset can and enter configuration mode */ | |
cfbf7586 | 103 | bfin_write(®->control, SRS | CCR); |
bbb84619 | 104 | SSYNC(); |
cfbf7586 | 105 | bfin_write(®->control, CCR); |
bbb84619 | 106 | SSYNC(); |
cfbf7586 | 107 | while (!(bfin_read(®->control) & CCA)) { |
bbb84619 BS |
108 | udelay(10); |
109 | if (--timeout == 0) { | |
aabdfd6a | 110 | netdev_err(dev, "fail to enter configuration mode\n"); |
bbb84619 BS |
111 | BUG(); |
112 | } | |
113 | } | |
114 | ||
115 | /* | |
116 | * All mailbox configurations are marked as inactive | |
117 | * by writing to CAN Mailbox Configuration Registers 1 and 2 | |
118 | * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled | |
119 | */ | |
cfbf7586 MF |
120 | bfin_write(®->mc1, 0); |
121 | bfin_write(®->mc2, 0); | |
bbb84619 BS |
122 | |
123 | /* Set Mailbox Direction */ | |
cfbf7586 MF |
124 | bfin_write(®->md1, 0xFFFF); /* mailbox 1-16 are RX */ |
125 | bfin_write(®->md2, 0); /* mailbox 17-32 are TX */ | |
bbb84619 BS |
126 | |
127 | /* RECEIVE_STD_CHL */ | |
128 | for (i = 0; i < 2; i++) { | |
cfbf7586 MF |
129 | bfin_write(®->chl[RECEIVE_STD_CHL + i].id0, 0); |
130 | bfin_write(®->chl[RECEIVE_STD_CHL + i].id1, AME); | |
131 | bfin_write(®->chl[RECEIVE_STD_CHL + i].dlc, 0); | |
132 | bfin_write(®->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF); | |
133 | bfin_write(®->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF); | |
bbb84619 BS |
134 | } |
135 | ||
136 | /* RECEIVE_EXT_CHL */ | |
137 | for (i = 0; i < 2; i++) { | |
cfbf7586 MF |
138 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].id0, 0); |
139 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE); | |
140 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].dlc, 0); | |
141 | bfin_write(®->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF); | |
142 | bfin_write(®->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF); | |
bbb84619 BS |
143 | } |
144 | ||
cfbf7586 MF |
145 | bfin_write(®->mc2, BIT(TRANSMIT_CHL - 16)); |
146 | bfin_write(®->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); | |
bbb84619 BS |
147 | SSYNC(); |
148 | ||
149 | priv->can.state = CAN_STATE_STOPPED; | |
150 | } | |
151 | ||
152 | static void bfin_can_set_normal_mode(struct net_device *dev) | |
153 | { | |
154 | struct bfin_can_priv *priv = netdev_priv(dev); | |
155 | struct bfin_can_regs __iomem *reg = priv->membase; | |
156 | int timeout = BFIN_CAN_TIMEOUT; | |
157 | ||
158 | /* | |
159 | * leave configuration mode | |
160 | */ | |
cfbf7586 | 161 | bfin_write(®->control, bfin_read(®->control) & ~CCR); |
bbb84619 | 162 | |
cfbf7586 | 163 | while (bfin_read(®->status) & CCA) { |
bbb84619 BS |
164 | udelay(10); |
165 | if (--timeout == 0) { | |
aabdfd6a | 166 | netdev_err(dev, "fail to leave configuration mode\n"); |
bbb84619 BS |
167 | BUG(); |
168 | } | |
169 | } | |
170 | ||
171 | /* | |
172 | * clear _All_ tx and rx interrupts | |
173 | */ | |
cfbf7586 MF |
174 | bfin_write(®->mbtif1, 0xFFFF); |
175 | bfin_write(®->mbtif2, 0xFFFF); | |
176 | bfin_write(®->mbrif1, 0xFFFF); | |
177 | bfin_write(®->mbrif2, 0xFFFF); | |
bbb84619 BS |
178 | |
179 | /* | |
180 | * clear global interrupt status register | |
181 | */ | |
cfbf7586 | 182 | bfin_write(®->gis, 0x7FF); /* overwrites with '1' */ |
bbb84619 BS |
183 | |
184 | /* | |
185 | * Initialize Interrupts | |
186 | * - set bits in the mailbox interrupt mask register | |
187 | * - global interrupt mask | |
188 | */ | |
cfbf7586 MF |
189 | bfin_write(®->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); |
190 | bfin_write(®->mbim2, BIT(TRANSMIT_CHL - 16)); | |
bbb84619 | 191 | |
cfbf7586 | 192 | bfin_write(®->gim, EPIM | BOIM | RMLIM); |
bbb84619 BS |
193 | SSYNC(); |
194 | } | |
195 | ||
196 | static void bfin_can_start(struct net_device *dev) | |
197 | { | |
198 | struct bfin_can_priv *priv = netdev_priv(dev); | |
199 | ||
200 | /* enter reset mode */ | |
201 | if (priv->can.state != CAN_STATE_STOPPED) | |
202 | bfin_can_set_reset_mode(dev); | |
203 | ||
204 | /* leave reset mode */ | |
205 | bfin_can_set_normal_mode(dev); | |
206 | } | |
207 | ||
208 | static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode) | |
209 | { | |
210 | switch (mode) { | |
211 | case CAN_MODE_START: | |
212 | bfin_can_start(dev); | |
213 | if (netif_queue_stopped(dev)) | |
214 | netif_wake_queue(dev); | |
215 | break; | |
216 | ||
217 | default: | |
218 | return -EOPNOTSUPP; | |
219 | } | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
79d0d8a7 WG |
224 | static int bfin_can_get_berr_counter(const struct net_device *dev, |
225 | struct can_berr_counter *bec) | |
226 | { | |
227 | struct bfin_can_priv *priv = netdev_priv(dev); | |
228 | struct bfin_can_regs __iomem *reg = priv->membase; | |
229 | ||
230 | u16 cec = bfin_read(®->cec); | |
231 | ||
232 | bec->txerr = cec >> 8; | |
233 | bec->rxerr = cec; | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
bbb84619 BS |
238 | static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev) |
239 | { | |
240 | struct bfin_can_priv *priv = netdev_priv(dev); | |
241 | struct bfin_can_regs __iomem *reg = priv->membase; | |
242 | struct can_frame *cf = (struct can_frame *)skb->data; | |
243 | u8 dlc = cf->can_dlc; | |
244 | canid_t id = cf->can_id; | |
245 | u8 *data = cf->data; | |
246 | u16 val; | |
247 | int i; | |
248 | ||
3ccd4c61 OH |
249 | if (can_dropped_invalid_skb(dev, skb)) |
250 | return NETDEV_TX_OK; | |
251 | ||
bbb84619 BS |
252 | netif_stop_queue(dev); |
253 | ||
254 | /* fill id */ | |
255 | if (id & CAN_EFF_FLAG) { | |
cfbf7586 | 256 | bfin_write(®->chl[TRANSMIT_CHL].id0, id); |
9118f08a MF |
257 | val = ((id & 0x1FFF0000) >> 16) | IDE; |
258 | } else | |
259 | val = (id << 2); | |
260 | if (id & CAN_RTR_FLAG) | |
261 | val |= RTR; | |
cfbf7586 | 262 | bfin_write(®->chl[TRANSMIT_CHL].id1, val | AME); |
bbb84619 BS |
263 | |
264 | /* fill payload */ | |
265 | for (i = 0; i < 8; i += 2) { | |
266 | val = ((7 - i) < dlc ? (data[7 - i]) : 0) + | |
267 | ((6 - i) < dlc ? (data[6 - i] << 8) : 0); | |
cfbf7586 | 268 | bfin_write(®->chl[TRANSMIT_CHL].data[i], val); |
bbb84619 BS |
269 | } |
270 | ||
271 | /* fill data length code */ | |
cfbf7586 | 272 | bfin_write(®->chl[TRANSMIT_CHL].dlc, dlc); |
bbb84619 | 273 | |
bbb84619 BS |
274 | can_put_echo_skb(skb, dev, 0); |
275 | ||
276 | /* set transmit request */ | |
cfbf7586 | 277 | bfin_write(®->trs2, BIT(TRANSMIT_CHL - 16)); |
bbb84619 BS |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
282 | static void bfin_can_rx(struct net_device *dev, u16 isrc) | |
283 | { | |
284 | struct bfin_can_priv *priv = netdev_priv(dev); | |
285 | struct net_device_stats *stats = &dev->stats; | |
286 | struct bfin_can_regs __iomem *reg = priv->membase; | |
287 | struct can_frame *cf; | |
288 | struct sk_buff *skb; | |
289 | int obj; | |
290 | int i; | |
291 | u16 val; | |
292 | ||
293 | skb = alloc_can_skb(dev, &cf); | |
294 | if (skb == NULL) | |
295 | return; | |
296 | ||
297 | /* get id */ | |
298 | if (isrc & BIT(RECEIVE_EXT_CHL)) { | |
299 | /* extended frame format (EFF) */ | |
cfbf7586 | 300 | cf->can_id = ((bfin_read(®->chl[RECEIVE_EXT_CHL].id1) |
bbb84619 | 301 | & 0x1FFF) << 16) |
cfbf7586 | 302 | + bfin_read(®->chl[RECEIVE_EXT_CHL].id0); |
bbb84619 BS |
303 | cf->can_id |= CAN_EFF_FLAG; |
304 | obj = RECEIVE_EXT_CHL; | |
305 | } else { | |
306 | /* standard frame format (SFF) */ | |
cfbf7586 | 307 | cf->can_id = (bfin_read(®->chl[RECEIVE_STD_CHL].id1) |
bbb84619 BS |
308 | & 0x1ffc) >> 2; |
309 | obj = RECEIVE_STD_CHL; | |
310 | } | |
cfbf7586 | 311 | if (bfin_read(®->chl[obj].id1) & RTR) |
bbb84619 BS |
312 | cf->can_id |= CAN_RTR_FLAG; |
313 | ||
314 | /* get data length code */ | |
cfbf7586 | 315 | cf->can_dlc = get_can_dlc(bfin_read(®->chl[obj].dlc) & 0xF); |
bbb84619 BS |
316 | |
317 | /* get payload */ | |
318 | for (i = 0; i < 8; i += 2) { | |
cfbf7586 | 319 | val = bfin_read(®->chl[obj].data[i]); |
bbb84619 BS |
320 | cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0; |
321 | cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0; | |
322 | } | |
323 | ||
324 | netif_rx(skb); | |
325 | ||
326 | stats->rx_packets++; | |
327 | stats->rx_bytes += cf->can_dlc; | |
328 | } | |
329 | ||
330 | static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status) | |
331 | { | |
332 | struct bfin_can_priv *priv = netdev_priv(dev); | |
333 | struct bfin_can_regs __iomem *reg = priv->membase; | |
334 | struct net_device_stats *stats = &dev->stats; | |
335 | struct can_frame *cf; | |
336 | struct sk_buff *skb; | |
337 | enum can_state state = priv->can.state; | |
338 | ||
339 | skb = alloc_can_err_skb(dev, &cf); | |
340 | if (skb == NULL) | |
341 | return -ENOMEM; | |
342 | ||
343 | if (isrc & RMLIS) { | |
344 | /* data overrun interrupt */ | |
aabdfd6a | 345 | netdev_dbg(dev, "data overrun interrupt\n"); |
bbb84619 BS |
346 | cf->can_id |= CAN_ERR_CRTL; |
347 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
348 | stats->rx_over_errors++; | |
349 | stats->rx_errors++; | |
350 | } | |
351 | ||
352 | if (isrc & BOIS) { | |
aabdfd6a | 353 | netdev_dbg(dev, "bus-off mode interrupt\n"); |
bbb84619 BS |
354 | state = CAN_STATE_BUS_OFF; |
355 | cf->can_id |= CAN_ERR_BUSOFF; | |
356 | can_bus_off(dev); | |
357 | } | |
358 | ||
359 | if (isrc & EPIS) { | |
360 | /* error passive interrupt */ | |
aabdfd6a | 361 | netdev_dbg(dev, "error passive interrupt\n"); |
bbb84619 BS |
362 | state = CAN_STATE_ERROR_PASSIVE; |
363 | } | |
364 | ||
365 | if ((isrc & EWTIS) || (isrc & EWRIS)) { | |
aabdfd6a | 366 | netdev_dbg(dev, "Error Warning Transmit/Receive Interrupt\n"); |
bbb84619 BS |
367 | state = CAN_STATE_ERROR_WARNING; |
368 | } | |
369 | ||
370 | if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || | |
371 | state == CAN_STATE_ERROR_PASSIVE)) { | |
cfbf7586 | 372 | u16 cec = bfin_read(®->cec); |
bbb84619 BS |
373 | u8 rxerr = cec; |
374 | u8 txerr = cec >> 8; | |
375 | ||
376 | cf->can_id |= CAN_ERR_CRTL; | |
377 | if (state == CAN_STATE_ERROR_WARNING) { | |
378 | priv->can.can_stats.error_warning++; | |
379 | cf->data[1] = (txerr > rxerr) ? | |
380 | CAN_ERR_CRTL_TX_WARNING : | |
381 | CAN_ERR_CRTL_RX_WARNING; | |
382 | } else { | |
383 | priv->can.can_stats.error_passive++; | |
384 | cf->data[1] = (txerr > rxerr) ? | |
385 | CAN_ERR_CRTL_TX_PASSIVE : | |
386 | CAN_ERR_CRTL_RX_PASSIVE; | |
387 | } | |
388 | } | |
389 | ||
390 | if (status) { | |
391 | priv->can.can_stats.bus_error++; | |
392 | ||
393 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
394 | ||
395 | if (status & BEF) | |
396 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
397 | else if (status & FER) | |
398 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
399 | else if (status & SER) | |
400 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
401 | else | |
402 | cf->data[2] |= CAN_ERR_PROT_UNSPEC; | |
403 | } | |
404 | ||
405 | priv->can.state = state; | |
406 | ||
407 | netif_rx(skb); | |
408 | ||
409 | stats->rx_packets++; | |
410 | stats->rx_bytes += cf->can_dlc; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | irqreturn_t bfin_can_interrupt(int irq, void *dev_id) | |
416 | { | |
417 | struct net_device *dev = dev_id; | |
418 | struct bfin_can_priv *priv = netdev_priv(dev); | |
419 | struct bfin_can_regs __iomem *reg = priv->membase; | |
420 | struct net_device_stats *stats = &dev->stats; | |
421 | u16 status, isrc; | |
422 | ||
cfbf7586 | 423 | if ((irq == priv->tx_irq) && bfin_read(®->mbtif2)) { |
bbb84619 | 424 | /* transmission complete interrupt */ |
cfbf7586 | 425 | bfin_write(®->mbtif2, 0xFFFF); |
bbb84619 | 426 | stats->tx_packets++; |
cfbf7586 | 427 | stats->tx_bytes += bfin_read(®->chl[TRANSMIT_CHL].dlc); |
bbb84619 BS |
428 | can_get_echo_skb(dev, 0); |
429 | netif_wake_queue(dev); | |
cfbf7586 | 430 | } else if ((irq == priv->rx_irq) && bfin_read(®->mbrif1)) { |
bbb84619 | 431 | /* receive interrupt */ |
cfbf7586 MF |
432 | isrc = bfin_read(®->mbrif1); |
433 | bfin_write(®->mbrif1, 0xFFFF); | |
bbb84619 | 434 | bfin_can_rx(dev, isrc); |
cfbf7586 | 435 | } else if ((irq == priv->err_irq) && bfin_read(®->gis)) { |
bbb84619 | 436 | /* error interrupt */ |
cfbf7586 MF |
437 | isrc = bfin_read(®->gis); |
438 | status = bfin_read(®->esr); | |
439 | bfin_write(®->gis, 0x7FF); | |
bbb84619 BS |
440 | bfin_can_err(dev, isrc, status); |
441 | } else { | |
442 | return IRQ_NONE; | |
443 | } | |
444 | ||
445 | return IRQ_HANDLED; | |
446 | } | |
447 | ||
448 | static int bfin_can_open(struct net_device *dev) | |
449 | { | |
450 | struct bfin_can_priv *priv = netdev_priv(dev); | |
451 | int err; | |
452 | ||
453 | /* set chip into reset mode */ | |
454 | bfin_can_set_reset_mode(dev); | |
455 | ||
456 | /* common open */ | |
457 | err = open_candev(dev); | |
458 | if (err) | |
459 | goto exit_open; | |
460 | ||
461 | /* register interrupt handler */ | |
462 | err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0, | |
463 | "bfin-can-rx", dev); | |
464 | if (err) | |
465 | goto exit_rx_irq; | |
466 | err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0, | |
467 | "bfin-can-tx", dev); | |
468 | if (err) | |
469 | goto exit_tx_irq; | |
470 | err = request_irq(priv->err_irq, &bfin_can_interrupt, 0, | |
471 | "bfin-can-err", dev); | |
472 | if (err) | |
473 | goto exit_err_irq; | |
474 | ||
475 | bfin_can_start(dev); | |
476 | ||
477 | netif_start_queue(dev); | |
478 | ||
479 | return 0; | |
480 | ||
481 | exit_err_irq: | |
482 | free_irq(priv->tx_irq, dev); | |
483 | exit_tx_irq: | |
484 | free_irq(priv->rx_irq, dev); | |
485 | exit_rx_irq: | |
486 | close_candev(dev); | |
487 | exit_open: | |
488 | return err; | |
489 | } | |
490 | ||
491 | static int bfin_can_close(struct net_device *dev) | |
492 | { | |
493 | struct bfin_can_priv *priv = netdev_priv(dev); | |
494 | ||
495 | netif_stop_queue(dev); | |
496 | bfin_can_set_reset_mode(dev); | |
497 | ||
498 | close_candev(dev); | |
499 | ||
500 | free_irq(priv->rx_irq, dev); | |
501 | free_irq(priv->tx_irq, dev); | |
502 | free_irq(priv->err_irq, dev); | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | struct net_device *alloc_bfin_candev(void) | |
508 | { | |
509 | struct net_device *dev; | |
510 | struct bfin_can_priv *priv; | |
511 | ||
e9dcd161 | 512 | dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX); |
bbb84619 BS |
513 | if (!dev) |
514 | return NULL; | |
515 | ||
516 | priv = netdev_priv(dev); | |
517 | ||
518 | priv->dev = dev; | |
519 | priv->can.bittiming_const = &bfin_can_bittiming_const; | |
520 | priv->can.do_set_bittiming = bfin_can_set_bittiming; | |
521 | priv->can.do_set_mode = bfin_can_set_mode; | |
79d0d8a7 | 522 | priv->can.do_get_berr_counter = bfin_can_get_berr_counter; |
ad72c347 | 523 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; |
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524 | |
525 | return dev; | |
526 | } | |
527 | ||
528 | static const struct net_device_ops bfin_can_netdev_ops = { | |
529 | .ndo_open = bfin_can_open, | |
530 | .ndo_stop = bfin_can_close, | |
531 | .ndo_start_xmit = bfin_can_start_xmit, | |
532 | }; | |
533 | ||
534 | static int __devinit bfin_can_probe(struct platform_device *pdev) | |
535 | { | |
536 | int err; | |
537 | struct net_device *dev; | |
538 | struct bfin_can_priv *priv; | |
539 | struct resource *res_mem, *rx_irq, *tx_irq, *err_irq; | |
540 | unsigned short *pdata; | |
541 | ||
542 | pdata = pdev->dev.platform_data; | |
543 | if (!pdata) { | |
544 | dev_err(&pdev->dev, "No platform data provided!\n"); | |
545 | err = -EINVAL; | |
546 | goto exit; | |
547 | } | |
548 | ||
549 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
550 | rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
551 | tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
552 | err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2); | |
553 | if (!res_mem || !rx_irq || !tx_irq || !err_irq) { | |
554 | err = -EINVAL; | |
555 | goto exit; | |
556 | } | |
557 | ||
558 | if (!request_mem_region(res_mem->start, resource_size(res_mem), | |
559 | dev_name(&pdev->dev))) { | |
560 | err = -EBUSY; | |
561 | goto exit; | |
562 | } | |
563 | ||
564 | /* request peripheral pins */ | |
565 | err = peripheral_request_list(pdata, dev_name(&pdev->dev)); | |
566 | if (err) | |
567 | goto exit_mem_release; | |
568 | ||
569 | dev = alloc_bfin_candev(); | |
570 | if (!dev) { | |
571 | err = -ENOMEM; | |
572 | goto exit_peri_pin_free; | |
573 | } | |
574 | ||
575 | priv = netdev_priv(dev); | |
576 | priv->membase = (void __iomem *)res_mem->start; | |
577 | priv->rx_irq = rx_irq->start; | |
578 | priv->tx_irq = tx_irq->start; | |
579 | priv->err_irq = err_irq->start; | |
580 | priv->pin_list = pdata; | |
581 | priv->can.clock.freq = get_sclk(); | |
582 | ||
583 | dev_set_drvdata(&pdev->dev, dev); | |
584 | SET_NETDEV_DEV(dev, &pdev->dev); | |
585 | ||
586 | dev->flags |= IFF_ECHO; /* we support local echo */ | |
587 | dev->netdev_ops = &bfin_can_netdev_ops; | |
588 | ||
589 | bfin_can_set_reset_mode(dev); | |
590 | ||
591 | err = register_candev(dev); | |
592 | if (err) { | |
593 | dev_err(&pdev->dev, "registering failed (err=%d)\n", err); | |
594 | goto exit_candev_free; | |
595 | } | |
596 | ||
597 | dev_info(&pdev->dev, | |
598 | "%s device registered" | |
599 | "(®_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n", | |
c2fd03a0 | 600 | DRV_NAME, priv->membase, priv->rx_irq, |
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601 | priv->tx_irq, priv->err_irq, priv->can.clock.freq); |
602 | return 0; | |
603 | ||
604 | exit_candev_free: | |
605 | free_candev(dev); | |
606 | exit_peri_pin_free: | |
607 | peripheral_free_list(pdata); | |
608 | exit_mem_release: | |
609 | release_mem_region(res_mem->start, resource_size(res_mem)); | |
610 | exit: | |
611 | return err; | |
612 | } | |
613 | ||
614 | static int __devexit bfin_can_remove(struct platform_device *pdev) | |
615 | { | |
616 | struct net_device *dev = dev_get_drvdata(&pdev->dev); | |
617 | struct bfin_can_priv *priv = netdev_priv(dev); | |
618 | struct resource *res; | |
619 | ||
620 | bfin_can_set_reset_mode(dev); | |
621 | ||
622 | unregister_candev(dev); | |
623 | ||
624 | dev_set_drvdata(&pdev->dev, NULL); | |
625 | ||
626 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
627 | release_mem_region(res->start, resource_size(res)); | |
628 | ||
629 | peripheral_free_list(priv->pin_list); | |
630 | ||
631 | free_candev(dev); | |
632 | return 0; | |
633 | } | |
634 | ||
635 | #ifdef CONFIG_PM | |
636 | static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg) | |
637 | { | |
638 | struct net_device *dev = dev_get_drvdata(&pdev->dev); | |
639 | struct bfin_can_priv *priv = netdev_priv(dev); | |
640 | struct bfin_can_regs __iomem *reg = priv->membase; | |
641 | int timeout = BFIN_CAN_TIMEOUT; | |
642 | ||
643 | if (netif_running(dev)) { | |
644 | /* enter sleep mode */ | |
cfbf7586 | 645 | bfin_write(®->control, bfin_read(®->control) | SMR); |
bbb84619 | 646 | SSYNC(); |
cfbf7586 | 647 | while (!(bfin_read(®->intr) & SMACK)) { |
bbb84619 BS |
648 | udelay(10); |
649 | if (--timeout == 0) { | |
aabdfd6a | 650 | netdev_err(dev, "fail to enter sleep mode\n"); |
bbb84619 BS |
651 | BUG(); |
652 | } | |
653 | } | |
654 | } | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
659 | static int bfin_can_resume(struct platform_device *pdev) | |
660 | { | |
661 | struct net_device *dev = dev_get_drvdata(&pdev->dev); | |
662 | struct bfin_can_priv *priv = netdev_priv(dev); | |
663 | struct bfin_can_regs __iomem *reg = priv->membase; | |
664 | ||
665 | if (netif_running(dev)) { | |
666 | /* leave sleep mode */ | |
cfbf7586 | 667 | bfin_write(®->intr, 0); |
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668 | SSYNC(); |
669 | } | |
670 | ||
671 | return 0; | |
672 | } | |
673 | #else | |
674 | #define bfin_can_suspend NULL | |
675 | #define bfin_can_resume NULL | |
676 | #endif /* CONFIG_PM */ | |
677 | ||
678 | static struct platform_driver bfin_can_driver = { | |
679 | .probe = bfin_can_probe, | |
680 | .remove = __devexit_p(bfin_can_remove), | |
681 | .suspend = bfin_can_suspend, | |
682 | .resume = bfin_can_resume, | |
683 | .driver = { | |
684 | .name = DRV_NAME, | |
685 | .owner = THIS_MODULE, | |
686 | }, | |
687 | }; | |
688 | ||
871d3372 | 689 | module_platform_driver(bfin_can_driver); |
bbb84619 BS |
690 | |
691 | MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); | |
692 | MODULE_LICENSE("GPL"); | |
693 | MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver"); |