]>
Commit | Line | Data |
---|---|---|
881ff67a BS |
1 | /* |
2 | * CAN bus driver for Bosch C_CAN controller | |
3 | * | |
4 | * Copyright (C) 2010 ST Microelectronics | |
5 | * Bhupesh Sharma <bhupesh.sharma@st.com> | |
6 | * | |
7 | * Borrowed heavily from the C_CAN driver originally written by: | |
8 | * Copyright (C) 2007 | |
9 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> | |
10 | * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> | |
11 | * | |
12 | * TX and RX NAPI implementation has been borrowed from at91 CAN driver | |
13 | * written by: | |
14 | * Copyright | |
15 | * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> | |
16 | * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> | |
17 | * | |
18 | * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. | |
19 | * Bosch C_CAN user manual can be obtained from: | |
20 | * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ | |
21 | * users_manual_c_can.pdf | |
22 | * | |
23 | * This file is licensed under the terms of the GNU General Public | |
24 | * License version 2. This program is licensed "as is" without any | |
25 | * warranty of any kind, whether express or implied. | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
881ff67a BS |
29 | #include <linux/module.h> |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/if_arp.h> | |
34 | #include <linux/if_ether.h> | |
35 | #include <linux/list.h> | |
881ff67a | 36 | #include <linux/io.h> |
4cdd34b2 | 37 | #include <linux/pm_runtime.h> |
881ff67a BS |
38 | |
39 | #include <linux/can.h> | |
40 | #include <linux/can/dev.h> | |
41 | #include <linux/can/error.h> | |
5090f805 | 42 | #include <linux/can/led.h> |
881ff67a BS |
43 | |
44 | #include "c_can.h" | |
45 | ||
33f81009 AC |
46 | /* Number of interface registers */ |
47 | #define IF_ENUM_REG_LEN 11 | |
48 | #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) | |
49 | ||
82120032 AC |
50 | /* control extension register D_CAN specific */ |
51 | #define CONTROL_EX_PDR BIT(8) | |
52 | ||
881ff67a BS |
53 | /* control register */ |
54 | #define CONTROL_TEST BIT(7) | |
55 | #define CONTROL_CCE BIT(6) | |
56 | #define CONTROL_DISABLE_AR BIT(5) | |
57 | #define CONTROL_ENABLE_AR (0 << 5) | |
58 | #define CONTROL_EIE BIT(3) | |
59 | #define CONTROL_SIE BIT(2) | |
60 | #define CONTROL_IE BIT(1) | |
61 | #define CONTROL_INIT BIT(0) | |
62 | ||
63 | /* test register */ | |
64 | #define TEST_RX BIT(7) | |
65 | #define TEST_TX1 BIT(6) | |
66 | #define TEST_TX2 BIT(5) | |
67 | #define TEST_LBACK BIT(4) | |
68 | #define TEST_SILENT BIT(3) | |
69 | #define TEST_BASIC BIT(2) | |
70 | ||
71 | /* status register */ | |
82120032 | 72 | #define STATUS_PDA BIT(10) |
881ff67a BS |
73 | #define STATUS_BOFF BIT(7) |
74 | #define STATUS_EWARN BIT(6) | |
75 | #define STATUS_EPASS BIT(5) | |
76 | #define STATUS_RXOK BIT(4) | |
77 | #define STATUS_TXOK BIT(3) | |
78 | ||
79 | /* error counter register */ | |
80 | #define ERR_CNT_TEC_MASK 0xff | |
81 | #define ERR_CNT_TEC_SHIFT 0 | |
82 | #define ERR_CNT_REC_SHIFT 8 | |
83 | #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) | |
84 | #define ERR_CNT_RP_SHIFT 15 | |
85 | #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) | |
86 | ||
87 | /* bit-timing register */ | |
88 | #define BTR_BRP_MASK 0x3f | |
89 | #define BTR_BRP_SHIFT 0 | |
90 | #define BTR_SJW_SHIFT 6 | |
91 | #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) | |
92 | #define BTR_TSEG1_SHIFT 8 | |
93 | #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) | |
94 | #define BTR_TSEG2_SHIFT 12 | |
95 | #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) | |
96 | ||
97 | /* brp extension register */ | |
98 | #define BRP_EXT_BRPE_MASK 0x0f | |
99 | #define BRP_EXT_BRPE_SHIFT 0 | |
100 | ||
101 | /* IFx command request */ | |
102 | #define IF_COMR_BUSY BIT(15) | |
103 | ||
104 | /* IFx command mask */ | |
105 | #define IF_COMM_WR BIT(7) | |
106 | #define IF_COMM_MASK BIT(6) | |
107 | #define IF_COMM_ARB BIT(5) | |
108 | #define IF_COMM_CONTROL BIT(4) | |
109 | #define IF_COMM_CLR_INT_PND BIT(3) | |
110 | #define IF_COMM_TXRQST BIT(2) | |
111 | #define IF_COMM_DATAA BIT(1) | |
112 | #define IF_COMM_DATAB BIT(0) | |
113 | #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ | |
114 | IF_COMM_CONTROL | IF_COMM_TXRQST | \ | |
115 | IF_COMM_DATAA | IF_COMM_DATAB) | |
116 | ||
117 | /* IFx arbitration */ | |
118 | #define IF_ARB_MSGVAL BIT(15) | |
119 | #define IF_ARB_MSGXTD BIT(14) | |
120 | #define IF_ARB_TRANSMIT BIT(13) | |
121 | ||
122 | /* IFx message control */ | |
123 | #define IF_MCONT_NEWDAT BIT(15) | |
124 | #define IF_MCONT_MSGLST BIT(14) | |
881ff67a BS |
125 | #define IF_MCONT_INTPND BIT(13) |
126 | #define IF_MCONT_UMASK BIT(12) | |
127 | #define IF_MCONT_TXIE BIT(11) | |
128 | #define IF_MCONT_RXIE BIT(10) | |
129 | #define IF_MCONT_RMTEN BIT(9) | |
130 | #define IF_MCONT_TXRQST BIT(8) | |
131 | #define IF_MCONT_EOB BIT(7) | |
132 | #define IF_MCONT_DLC_MASK 0xf | |
133 | ||
640916db TG |
134 | /* |
135 | * Use IF1 for RX and IF2 for TX | |
136 | */ | |
137 | #define IF_RX 0 | |
138 | #define IF_TX 1 | |
139 | ||
881ff67a BS |
140 | /* |
141 | * IFx register masks: | |
142 | * allow easy operation on 16-bit registers when the | |
143 | * argument is 32-bit instead | |
144 | */ | |
145 | #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) | |
146 | #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) | |
147 | ||
148 | /* message object split */ | |
149 | #define C_CAN_NO_OF_OBJECTS 32 | |
150 | #define C_CAN_MSG_OBJ_RX_NUM 16 | |
151 | #define C_CAN_MSG_OBJ_TX_NUM 16 | |
152 | ||
153 | #define C_CAN_MSG_OBJ_RX_FIRST 1 | |
154 | #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ | |
155 | C_CAN_MSG_OBJ_RX_NUM - 1) | |
156 | ||
157 | #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) | |
158 | #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ | |
159 | C_CAN_MSG_OBJ_TX_NUM - 1) | |
160 | ||
161 | #define C_CAN_MSG_OBJ_RX_SPLIT 9 | |
162 | #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) | |
163 | ||
164 | #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) | |
165 | #define RECEIVE_OBJECT_BITS 0x0000ffff | |
166 | ||
167 | /* status interrupt */ | |
168 | #define STATUS_INTERRUPT 0x8000 | |
169 | ||
170 | /* global interrupt masks */ | |
171 | #define ENABLE_ALL_INTERRUPTS 1 | |
172 | #define DISABLE_ALL_INTERRUPTS 0 | |
173 | ||
174 | /* minimum timeout for checking BUSY status */ | |
175 | #define MIN_TIMEOUT_VALUE 6 | |
176 | ||
82120032 AC |
177 | /* Wait for ~1 sec for INIT bit */ |
178 | #define INIT_WAIT_MS 1000 | |
179 | ||
881ff67a BS |
180 | /* napi related */ |
181 | #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM | |
182 | ||
183 | /* c_can lec values */ | |
184 | enum c_can_lec_type { | |
185 | LEC_NO_ERROR = 0, | |
186 | LEC_STUFF_ERROR, | |
187 | LEC_FORM_ERROR, | |
188 | LEC_ACK_ERROR, | |
189 | LEC_BIT1_ERROR, | |
190 | LEC_BIT0_ERROR, | |
191 | LEC_CRC_ERROR, | |
192 | LEC_UNUSED, | |
193 | }; | |
194 | ||
195 | /* | |
196 | * c_can error types: | |
197 | * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported | |
198 | */ | |
199 | enum c_can_bus_error_types { | |
200 | C_CAN_NO_ERROR = 0, | |
201 | C_CAN_BUS_OFF, | |
202 | C_CAN_ERROR_WARNING, | |
203 | C_CAN_ERROR_PASSIVE, | |
204 | }; | |
205 | ||
194b9a4c | 206 | static const struct can_bittiming_const c_can_bittiming_const = { |
881ff67a BS |
207 | .name = KBUILD_MODNAME, |
208 | .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ | |
209 | .tseg1_max = 16, | |
210 | .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ | |
211 | .tseg2_max = 8, | |
212 | .sjw_max = 4, | |
213 | .brp_min = 1, | |
214 | .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ | |
215 | .brp_inc = 1, | |
216 | }; | |
217 | ||
4cdd34b2 AC |
218 | static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) |
219 | { | |
220 | if (priv->device) | |
221 | pm_runtime_enable(priv->device); | |
222 | } | |
223 | ||
224 | static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) | |
225 | { | |
226 | if (priv->device) | |
227 | pm_runtime_disable(priv->device); | |
228 | } | |
229 | ||
230 | static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) | |
231 | { | |
232 | if (priv->device) | |
233 | pm_runtime_get_sync(priv->device); | |
234 | } | |
235 | ||
236 | static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) | |
237 | { | |
238 | if (priv->device) | |
239 | pm_runtime_put_sync(priv->device); | |
240 | } | |
241 | ||
52cde85a AC |
242 | static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) |
243 | { | |
244 | if (priv->raminit) | |
245 | priv->raminit(priv, enable); | |
246 | } | |
247 | ||
881ff67a BS |
248 | static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) |
249 | { | |
250 | return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + | |
251 | C_CAN_MSG_OBJ_TX_FIRST; | |
252 | } | |
253 | ||
254 | static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) | |
255 | { | |
256 | return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + | |
257 | C_CAN_MSG_OBJ_TX_FIRST; | |
258 | } | |
259 | ||
33f81009 | 260 | static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) |
881ff67a | 261 | { |
33f81009 AC |
262 | u32 val = priv->read_reg(priv, index); |
263 | val |= ((u32) priv->read_reg(priv, index + 1)) << 16; | |
881ff67a BS |
264 | return val; |
265 | } | |
266 | ||
267 | static void c_can_enable_all_interrupts(struct c_can_priv *priv, | |
268 | int enable) | |
269 | { | |
270 | unsigned int cntrl_save = priv->read_reg(priv, | |
33f81009 | 271 | C_CAN_CTRL_REG); |
881ff67a BS |
272 | |
273 | if (enable) | |
274 | cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); | |
275 | else | |
276 | cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); | |
277 | ||
33f81009 | 278 | priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); |
881ff67a BS |
279 | } |
280 | ||
281 | static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) | |
282 | { | |
283 | int count = MIN_TIMEOUT_VALUE; | |
284 | ||
285 | while (count && priv->read_reg(priv, | |
33f81009 | 286 | C_CAN_IFACE(COMREQ_REG, iface)) & |
881ff67a BS |
287 | IF_COMR_BUSY) { |
288 | count--; | |
289 | udelay(1); | |
290 | } | |
291 | ||
292 | if (!count) | |
293 | return 1; | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static inline void c_can_object_get(struct net_device *dev, | |
299 | int iface, int objno, int mask) | |
300 | { | |
301 | struct c_can_priv *priv = netdev_priv(dev); | |
302 | ||
303 | /* | |
304 | * As per specs, after writting the message object number in the | |
305 | * IF command request register the transfer b/w interface | |
306 | * register and message RAM must be complete in 6 CAN-CLK | |
307 | * period. | |
308 | */ | |
33f81009 | 309 | priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), |
881ff67a | 310 | IFX_WRITE_LOW_16BIT(mask)); |
33f81009 | 311 | priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), |
881ff67a BS |
312 | IFX_WRITE_LOW_16BIT(objno)); |
313 | ||
314 | if (c_can_msg_obj_is_busy(priv, iface)) | |
315 | netdev_err(dev, "timed out in object get\n"); | |
316 | } | |
317 | ||
318 | static inline void c_can_object_put(struct net_device *dev, | |
319 | int iface, int objno, int mask) | |
320 | { | |
321 | struct c_can_priv *priv = netdev_priv(dev); | |
322 | ||
323 | /* | |
324 | * As per specs, after writting the message object number in the | |
325 | * IF command request register the transfer b/w interface | |
326 | * register and message RAM must be complete in 6 CAN-CLK | |
327 | * period. | |
328 | */ | |
33f81009 | 329 | priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), |
881ff67a | 330 | (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); |
33f81009 | 331 | priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), |
881ff67a BS |
332 | IFX_WRITE_LOW_16BIT(objno)); |
333 | ||
334 | if (c_can_msg_obj_is_busy(priv, iface)) | |
335 | netdev_err(dev, "timed out in object put\n"); | |
336 | } | |
337 | ||
338 | static void c_can_write_msg_object(struct net_device *dev, | |
339 | int iface, struct can_frame *frame, int objno) | |
340 | { | |
341 | int i; | |
342 | u16 flags = 0; | |
343 | unsigned int id; | |
344 | struct c_can_priv *priv = netdev_priv(dev); | |
345 | ||
346 | if (!(frame->can_id & CAN_RTR_FLAG)) | |
347 | flags |= IF_ARB_TRANSMIT; | |
348 | ||
349 | if (frame->can_id & CAN_EFF_FLAG) { | |
350 | id = frame->can_id & CAN_EFF_MASK; | |
351 | flags |= IF_ARB_MSGXTD; | |
352 | } else | |
353 | id = ((frame->can_id & CAN_SFF_MASK) << 18); | |
354 | ||
355 | flags |= IF_ARB_MSGVAL; | |
356 | ||
33f81009 | 357 | priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), |
881ff67a | 358 | IFX_WRITE_LOW_16BIT(id)); |
33f81009 | 359 | priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | |
881ff67a BS |
360 | IFX_WRITE_HIGH_16BIT(id)); |
361 | ||
362 | for (i = 0; i < frame->can_dlc; i += 2) { | |
33f81009 | 363 | priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, |
881ff67a BS |
364 | frame->data[i] | (frame->data[i + 1] << 8)); |
365 | } | |
366 | ||
367 | /* enable interrupt for this message object */ | |
33f81009 | 368 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
369 | IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | |
370 | frame->can_dlc); | |
371 | c_can_object_put(dev, iface, objno, IF_COMM_ALL); | |
372 | } | |
373 | ||
374 | static inline void c_can_mark_rx_msg_obj(struct net_device *dev, | |
375 | int iface, int ctrl_mask, | |
376 | int obj) | |
377 | { | |
378 | struct c_can_priv *priv = netdev_priv(dev); | |
379 | ||
33f81009 | 380 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
381 | ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); |
382 | c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); | |
383 | ||
384 | } | |
385 | ||
386 | static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, | |
387 | int iface, | |
388 | int ctrl_mask) | |
389 | { | |
390 | int i; | |
391 | struct c_can_priv *priv = netdev_priv(dev); | |
392 | ||
393 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { | |
33f81009 | 394 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
395 | ctrl_mask & ~(IF_MCONT_MSGLST | |
396 | IF_MCONT_INTPND | IF_MCONT_NEWDAT)); | |
397 | c_can_object_put(dev, iface, i, IF_COMM_CONTROL); | |
398 | } | |
399 | } | |
400 | ||
401 | static inline void c_can_activate_rx_msg_obj(struct net_device *dev, | |
402 | int iface, int ctrl_mask, | |
403 | int obj) | |
404 | { | |
405 | struct c_can_priv *priv = netdev_priv(dev); | |
406 | ||
33f81009 | 407 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), |
881ff67a BS |
408 | ctrl_mask & ~(IF_MCONT_MSGLST | |
409 | IF_MCONT_INTPND | IF_MCONT_NEWDAT)); | |
410 | c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); | |
411 | } | |
412 | ||
07c7b6f6 TG |
413 | static int c_can_handle_lost_msg_obj(struct net_device *dev, |
414 | int iface, int objno, u32 ctrl) | |
881ff67a | 415 | { |
881ff67a | 416 | struct net_device_stats *stats = &dev->stats; |
07c7b6f6 | 417 | struct c_can_priv *priv = netdev_priv(dev); |
881ff67a | 418 | struct can_frame *frame; |
07c7b6f6 | 419 | struct sk_buff *skb; |
881ff67a | 420 | |
07c7b6f6 TG |
421 | ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); |
422 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); | |
640916db | 423 | c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); |
881ff67a BS |
424 | |
425 | /* create an error msg */ | |
426 | skb = alloc_can_err_skb(dev, &frame); | |
427 | if (unlikely(!skb)) | |
07c7b6f6 | 428 | return 0; |
881ff67a BS |
429 | |
430 | frame->can_id |= CAN_ERR_CRTL; | |
431 | frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
432 | stats->rx_errors++; | |
433 | stats->rx_over_errors++; | |
434 | ||
435 | netif_receive_skb(skb); | |
07c7b6f6 | 436 | return 1; |
881ff67a BS |
437 | } |
438 | ||
439 | static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) | |
440 | { | |
441 | u16 flags, data; | |
442 | int i; | |
443 | unsigned int val; | |
444 | struct c_can_priv *priv = netdev_priv(dev); | |
445 | struct net_device_stats *stats = &dev->stats; | |
446 | struct sk_buff *skb; | |
447 | struct can_frame *frame; | |
448 | ||
449 | skb = alloc_can_skb(dev, &frame); | |
450 | if (!skb) { | |
451 | stats->rx_dropped++; | |
452 | return -ENOMEM; | |
453 | } | |
454 | ||
455 | frame->can_dlc = get_can_dlc(ctrl & 0x0F); | |
456 | ||
33f81009 AC |
457 | flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); |
458 | val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | | |
881ff67a BS |
459 | (flags << 16); |
460 | ||
461 | if (flags & IF_ARB_MSGXTD) | |
462 | frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
463 | else | |
464 | frame->can_id = (val >> 18) & CAN_SFF_MASK; | |
465 | ||
466 | if (flags & IF_ARB_TRANSMIT) | |
467 | frame->can_id |= CAN_RTR_FLAG; | |
468 | else { | |
469 | for (i = 0; i < frame->can_dlc; i += 2) { | |
470 | data = priv->read_reg(priv, | |
33f81009 | 471 | C_CAN_IFACE(DATA1_REG, iface) + i / 2); |
881ff67a BS |
472 | frame->data[i] = data; |
473 | frame->data[i + 1] = data >> 8; | |
474 | } | |
475 | } | |
476 | ||
477 | netif_receive_skb(skb); | |
478 | ||
479 | stats->rx_packets++; | |
480 | stats->rx_bytes += frame->can_dlc; | |
481 | ||
5090f805 FB |
482 | can_led_event(dev, CAN_LED_EVENT_RX); |
483 | ||
881ff67a BS |
484 | return 0; |
485 | } | |
486 | ||
487 | static void c_can_setup_receive_object(struct net_device *dev, int iface, | |
488 | int objno, unsigned int mask, | |
489 | unsigned int id, unsigned int mcont) | |
490 | { | |
491 | struct c_can_priv *priv = netdev_priv(dev); | |
492 | ||
33f81009 | 493 | priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), |
881ff67a | 494 | IFX_WRITE_LOW_16BIT(mask)); |
2bd3bc4e AS |
495 | |
496 | /* According to C_CAN documentation, the reserved bit | |
497 | * in IFx_MASK2 register is fixed 1 | |
498 | */ | |
33f81009 | 499 | priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), |
2bd3bc4e | 500 | IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); |
881ff67a | 501 | |
33f81009 | 502 | priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), |
881ff67a | 503 | IFX_WRITE_LOW_16BIT(id)); |
33f81009 | 504 | priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), |
881ff67a BS |
505 | (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); |
506 | ||
33f81009 | 507 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); |
881ff67a BS |
508 | c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); |
509 | ||
510 | netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, | |
33f81009 | 511 | c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); |
881ff67a BS |
512 | } |
513 | ||
514 | static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) | |
515 | { | |
516 | struct c_can_priv *priv = netdev_priv(dev); | |
517 | ||
33f81009 AC |
518 | priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); |
519 | priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); | |
520 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); | |
881ff67a BS |
521 | |
522 | c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); | |
523 | ||
524 | netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, | |
33f81009 | 525 | c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); |
881ff67a BS |
526 | } |
527 | ||
528 | static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) | |
529 | { | |
33f81009 | 530 | int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); |
881ff67a BS |
531 | |
532 | /* | |
533 | * as transmission request register's bit n-1 corresponds to | |
534 | * message object n, we need to handle the same properly. | |
535 | */ | |
536 | if (val & (1 << (objno - 1))) | |
537 | return 1; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, | |
543 | struct net_device *dev) | |
544 | { | |
545 | u32 msg_obj_no; | |
546 | struct c_can_priv *priv = netdev_priv(dev); | |
547 | struct can_frame *frame = (struct can_frame *)skb->data; | |
548 | ||
549 | if (can_dropped_invalid_skb(dev, skb)) | |
550 | return NETDEV_TX_OK; | |
551 | ||
552 | msg_obj_no = get_tx_next_msg_obj(priv); | |
553 | ||
554 | /* prepare message object for transmission */ | |
640916db | 555 | c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); |
881ff67a BS |
556 | can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); |
557 | ||
558 | /* | |
559 | * we have to stop the queue in case of a wrap around or | |
560 | * if the next TX message object is still in use | |
561 | */ | |
562 | priv->tx_next++; | |
563 | if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || | |
564 | (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) | |
565 | netif_stop_queue(dev); | |
566 | ||
567 | return NETDEV_TX_OK; | |
568 | } | |
569 | ||
9fac1d1a TG |
570 | static int c_can_wait_for_ctrl_init(struct net_device *dev, |
571 | struct c_can_priv *priv, u32 init) | |
572 | { | |
573 | int retry = 0; | |
574 | ||
575 | while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { | |
576 | udelay(10); | |
577 | if (retry++ > 1000) { | |
578 | netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); | |
579 | return -EIO; | |
580 | } | |
581 | } | |
582 | return 0; | |
583 | } | |
584 | ||
881ff67a BS |
585 | static int c_can_set_bittiming(struct net_device *dev) |
586 | { | |
587 | unsigned int reg_btr, reg_brpe, ctrl_save; | |
588 | u8 brp, brpe, sjw, tseg1, tseg2; | |
589 | u32 ten_bit_brp; | |
590 | struct c_can_priv *priv = netdev_priv(dev); | |
591 | const struct can_bittiming *bt = &priv->can.bittiming; | |
9fac1d1a | 592 | int res; |
881ff67a BS |
593 | |
594 | /* c_can provides a 6-bit brp and 4-bit brpe fields */ | |
595 | ten_bit_brp = bt->brp - 1; | |
596 | brp = ten_bit_brp & BTR_BRP_MASK; | |
597 | brpe = ten_bit_brp >> 6; | |
598 | ||
599 | sjw = bt->sjw - 1; | |
600 | tseg1 = bt->prop_seg + bt->phase_seg1 - 1; | |
601 | tseg2 = bt->phase_seg2 - 1; | |
602 | reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | | |
603 | (tseg2 << BTR_TSEG2_SHIFT); | |
604 | reg_brpe = brpe & BRP_EXT_BRPE_MASK; | |
605 | ||
606 | netdev_info(dev, | |
607 | "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); | |
608 | ||
33f81009 | 609 | ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); |
9fac1d1a TG |
610 | ctrl_save &= ~CONTROL_INIT; |
611 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); | |
612 | res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); | |
613 | if (res) | |
614 | return res; | |
615 | ||
33f81009 AC |
616 | priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); |
617 | priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); | |
618 | priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); | |
881ff67a | 619 | |
9fac1d1a | 620 | return c_can_wait_for_ctrl_init(dev, priv, 0); |
881ff67a BS |
621 | } |
622 | ||
623 | /* | |
624 | * Configure C_CAN message objects for Tx and Rx purposes: | |
625 | * C_CAN provides a total of 32 message objects that can be configured | |
626 | * either for Tx or Rx purposes. Here the first 16 message objects are used as | |
627 | * a reception FIFO. The end of reception FIFO is signified by the EoB bit | |
628 | * being SET. The remaining 16 message objects are kept aside for Tx purposes. | |
629 | * See user guide document for further details on configuring message | |
630 | * objects. | |
631 | */ | |
632 | static void c_can_configure_msg_objects(struct net_device *dev) | |
633 | { | |
634 | int i; | |
635 | ||
636 | /* first invalidate all message objects */ | |
637 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) | |
640916db | 638 | c_can_inval_msg_object(dev, IF_RX, i); |
881ff67a BS |
639 | |
640 | /* setup receive message objects */ | |
641 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) | |
640916db | 642 | c_can_setup_receive_object(dev, IF_RX, i, 0, 0, |
881ff67a BS |
643 | (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); |
644 | ||
640916db | 645 | c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, |
881ff67a BS |
646 | IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); |
647 | } | |
648 | ||
649 | /* | |
650 | * Configure C_CAN chip: | |
651 | * - enable/disable auto-retransmission | |
652 | * - set operating mode | |
653 | * - configure message objects | |
654 | */ | |
130a5171 | 655 | static int c_can_chip_config(struct net_device *dev) |
881ff67a BS |
656 | { |
657 | struct c_can_priv *priv = netdev_priv(dev); | |
658 | ||
ee6f0988 | 659 | /* enable automatic retransmission */ |
33f81009 | 660 | priv->write_reg(priv, C_CAN_CTRL_REG, |
ee6f0988 | 661 | CONTROL_ENABLE_AR); |
881ff67a | 662 | |
d9cb9bd6 DC |
663 | if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && |
664 | (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { | |
881ff67a | 665 | /* loopback + silent mode : useful for hot self-test */ |
33f81009 | 666 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | |
881ff67a | 667 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
33f81009 | 668 | priv->write_reg(priv, C_CAN_TEST_REG, |
881ff67a BS |
669 | TEST_LBACK | TEST_SILENT); |
670 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
671 | /* loopback mode : useful for self-test function */ | |
33f81009 | 672 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | |
881ff67a | 673 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
33f81009 | 674 | priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); |
881ff67a BS |
675 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { |
676 | /* silent mode : bus-monitoring mode */ | |
33f81009 | 677 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | |
881ff67a | 678 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
33f81009 | 679 | priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); |
881ff67a BS |
680 | } else |
681 | /* normal mode*/ | |
33f81009 | 682 | priv->write_reg(priv, C_CAN_CTRL_REG, |
881ff67a BS |
683 | CONTROL_EIE | CONTROL_SIE | CONTROL_IE); |
684 | ||
685 | /* configure message objects */ | |
686 | c_can_configure_msg_objects(dev); | |
687 | ||
688 | /* set a `lec` value so that we can check for updates later */ | |
33f81009 | 689 | priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); |
881ff67a BS |
690 | |
691 | /* set bittiming params */ | |
130a5171 | 692 | return c_can_set_bittiming(dev); |
881ff67a BS |
693 | } |
694 | ||
130a5171 | 695 | static int c_can_start(struct net_device *dev) |
881ff67a BS |
696 | { |
697 | struct c_can_priv *priv = netdev_priv(dev); | |
130a5171 | 698 | int err; |
881ff67a | 699 | |
881ff67a | 700 | /* basic c_can configuration */ |
130a5171 MKB |
701 | err = c_can_chip_config(dev); |
702 | if (err) | |
703 | return err; | |
881ff67a BS |
704 | |
705 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
706 | ||
707 | /* reset tx helper pointers */ | |
708 | priv->tx_next = priv->tx_echo = 0; | |
4f2d56c4 JA |
709 | |
710 | /* enable status change, error and module interrupts */ | |
711 | c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); | |
130a5171 MKB |
712 | |
713 | return 0; | |
881ff67a BS |
714 | } |
715 | ||
716 | static void c_can_stop(struct net_device *dev) | |
717 | { | |
718 | struct c_can_priv *priv = netdev_priv(dev); | |
719 | ||
720 | /* disable all interrupts */ | |
721 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); | |
722 | ||
723 | /* set the state as STOPPED */ | |
724 | priv->can.state = CAN_STATE_STOPPED; | |
725 | } | |
726 | ||
727 | static int c_can_set_mode(struct net_device *dev, enum can_mode mode) | |
728 | { | |
130a5171 MKB |
729 | int err; |
730 | ||
881ff67a BS |
731 | switch (mode) { |
732 | case CAN_MODE_START: | |
130a5171 MKB |
733 | err = c_can_start(dev); |
734 | if (err) | |
735 | return err; | |
881ff67a BS |
736 | netif_wake_queue(dev); |
737 | break; | |
738 | default: | |
739 | return -EOPNOTSUPP; | |
740 | } | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
e35d46ad MKB |
745 | static int __c_can_get_berr_counter(const struct net_device *dev, |
746 | struct can_berr_counter *bec) | |
881ff67a BS |
747 | { |
748 | unsigned int reg_err_counter; | |
749 | struct c_can_priv *priv = netdev_priv(dev); | |
750 | ||
33f81009 | 751 | reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); |
881ff67a BS |
752 | bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> |
753 | ERR_CNT_REC_SHIFT; | |
754 | bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; | |
755 | ||
e35d46ad MKB |
756 | return 0; |
757 | } | |
758 | ||
759 | static int c_can_get_berr_counter(const struct net_device *dev, | |
760 | struct can_berr_counter *bec) | |
761 | { | |
762 | struct c_can_priv *priv = netdev_priv(dev); | |
763 | int err; | |
764 | ||
765 | c_can_pm_runtime_get_sync(priv); | |
766 | err = __c_can_get_berr_counter(dev, bec); | |
4cdd34b2 AC |
767 | c_can_pm_runtime_put_sync(priv); |
768 | ||
e35d46ad | 769 | return err; |
881ff67a BS |
770 | } |
771 | ||
772 | /* | |
773 | * theory of operation: | |
774 | * | |
775 | * priv->tx_echo holds the number of the oldest can_frame put for | |
776 | * transmission into the hardware, but not yet ACKed by the CAN tx | |
777 | * complete IRQ. | |
778 | * | |
779 | * We iterate from priv->tx_echo to priv->tx_next and check if the | |
780 | * packet has been transmitted, echo it back to the CAN framework. | |
617cacce | 781 | * If we discover a not yet transmitted packet, stop looking for more. |
881ff67a BS |
782 | */ |
783 | static void c_can_do_tx(struct net_device *dev) | |
784 | { | |
785 | u32 val; | |
786 | u32 msg_obj_no; | |
787 | struct c_can_priv *priv = netdev_priv(dev); | |
788 | struct net_device_stats *stats = &dev->stats; | |
789 | ||
790 | for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { | |
791 | msg_obj_no = get_tx_echo_msg_obj(priv); | |
33f81009 | 792 | val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); |
617cacce | 793 | if (!(val & (1 << (msg_obj_no - 1)))) { |
881ff67a BS |
794 | can_get_echo_skb(dev, |
795 | msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); | |
640916db | 796 | c_can_object_get(dev, IF_TX, msg_obj_no, IF_COMM_ALL); |
881ff67a | 797 | stats->tx_bytes += priv->read_reg(priv, |
640916db | 798 | C_CAN_IFACE(MSGCTRL_REG, IF_TX)) |
881ff67a BS |
799 | & IF_MCONT_DLC_MASK; |
800 | stats->tx_packets++; | |
5090f805 | 801 | can_led_event(dev, CAN_LED_EVENT_TX); |
640916db | 802 | c_can_inval_msg_object(dev, IF_TX, msg_obj_no); |
617cacce AC |
803 | } else { |
804 | break; | |
881ff67a BS |
805 | } |
806 | } | |
807 | ||
808 | /* restart queue if wrap-up or if queue stalled on last pkt */ | |
809 | if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || | |
810 | ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) | |
811 | netif_wake_queue(dev); | |
812 | } | |
813 | ||
64f08f2f TG |
814 | /* |
815 | * If we have a gap in the pending bits, that means we either | |
816 | * raced with the hardware or failed to readout all upper | |
817 | * objects in the last run due to quota limit. | |
818 | */ | |
819 | static u32 c_can_adjust_pending(u32 pend) | |
820 | { | |
821 | u32 weight, lasts; | |
822 | ||
823 | if (pend == RECEIVE_OBJECT_BITS) | |
824 | return pend; | |
825 | ||
826 | /* | |
827 | * If the last set bit is larger than the number of pending | |
828 | * bits we have a gap. | |
829 | */ | |
830 | weight = hweight32(pend); | |
831 | lasts = fls(pend); | |
832 | ||
833 | /* If the bits are linear, nothing to do */ | |
834 | if (lasts == weight) | |
835 | return pend; | |
836 | ||
837 | /* | |
838 | * Find the first set bit after the gap. We walk backwards | |
839 | * from the last set bit. | |
840 | */ | |
841 | for (lasts--; pend & (1 << (lasts - 1)); lasts--); | |
842 | ||
843 | return pend & ~((1 << lasts) - 1); | |
844 | } | |
845 | ||
881ff67a BS |
846 | /* |
847 | * theory of operation: | |
848 | * | |
849 | * c_can core saves a received CAN message into the first free message | |
850 | * object it finds free (starting with the lowest). Bits NEWDAT and | |
851 | * INTPND are set for this message object indicating that a new message | |
852 | * has arrived. To work-around this issue, we keep two groups of message | |
853 | * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. | |
854 | * | |
855 | * To ensure in-order frame reception we use the following | |
856 | * approach while re-activating a message object to receive further | |
857 | * frames: | |
858 | * - if the current message object number is lower than | |
859 | * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing | |
860 | * the INTPND bit. | |
861 | * - if the current message object number is equal to | |
862 | * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower | |
863 | * receive message objects. | |
864 | * - if the current message object number is greater than | |
865 | * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of | |
866 | * only this message object. | |
867 | */ | |
868 | static int c_can_do_rx_poll(struct net_device *dev, int quota) | |
869 | { | |
870 | u32 num_rx_pkts = 0; | |
871 | unsigned int msg_obj, msg_ctrl_save; | |
872 | struct c_can_priv *priv = netdev_priv(dev); | |
64f08f2f | 873 | u32 val, pend = 0; |
4ce78a83 MP |
874 | |
875 | /* | |
876 | * It is faster to read only one 16bit register. This is only possible | |
877 | * for a maximum number of 16 objects. | |
878 | */ | |
879 | BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, | |
880 | "Implementation does not support more message objects than 16"); | |
881 | ||
64f08f2f TG |
882 | while (quota > 0) { |
883 | ||
884 | if (!pend) { | |
885 | pend = priv->read_reg(priv, C_CAN_INTPND1_REG); | |
886 | if (!pend) | |
887 | return num_rx_pkts; | |
888 | /* | |
889 | * If the pending field has a gap, handle the | |
890 | * bits above the gap first. | |
891 | */ | |
892 | val = c_can_adjust_pending(pend); | |
893 | } else { | |
894 | val = pend; | |
895 | } | |
896 | /* Remove the bits from pend */ | |
897 | pend &= ~val; | |
898 | ||
4ce78a83 MP |
899 | while ((msg_obj = ffs(val)) && quota > 0) { |
900 | val &= ~BIT(msg_obj - 1); | |
901 | ||
640916db | 902 | c_can_object_get(dev, IF_RX, msg_obj, IF_COMM_ALL & |
881ff67a BS |
903 | ~IF_COMM_TXRQST); |
904 | msg_ctrl_save = priv->read_reg(priv, | |
640916db | 905 | C_CAN_IFACE(MSGCTRL_REG, IF_RX)); |
881ff67a | 906 | |
881ff67a | 907 | if (msg_ctrl_save & IF_MCONT_MSGLST) { |
07c7b6f6 TG |
908 | int n; |
909 | ||
910 | n = c_can_handle_lost_msg_obj(dev, IF_RX, | |
911 | msg_obj, | |
912 | msg_ctrl_save); | |
913 | num_rx_pkts += n; | |
914 | quota -=n; | |
881ff67a BS |
915 | continue; |
916 | } | |
917 | ||
918 | if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) | |
919 | continue; | |
920 | ||
921 | /* read the data from the message object */ | |
640916db | 922 | c_can_read_msg_object(dev, IF_RX, msg_ctrl_save); |
881ff67a BS |
923 | |
924 | if (msg_obj < C_CAN_MSG_RX_LOW_LAST) | |
640916db | 925 | c_can_mark_rx_msg_obj(dev, IF_RX, |
881ff67a BS |
926 | msg_ctrl_save, msg_obj); |
927 | else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) | |
928 | /* activate this msg obj */ | |
640916db | 929 | c_can_activate_rx_msg_obj(dev, IF_RX, |
881ff67a BS |
930 | msg_ctrl_save, msg_obj); |
931 | else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) | |
932 | /* activate all lower message objects */ | |
933 | c_can_activate_all_lower_rx_msg_obj(dev, | |
640916db | 934 | IF_RX, msg_ctrl_save); |
881ff67a BS |
935 | |
936 | num_rx_pkts++; | |
937 | quota--; | |
938 | } | |
939 | } | |
940 | ||
941 | return num_rx_pkts; | |
942 | } | |
943 | ||
944 | static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) | |
945 | { | |
946 | return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && | |
947 | (priv->current_status & LEC_UNUSED); | |
948 | } | |
949 | ||
950 | static int c_can_handle_state_change(struct net_device *dev, | |
951 | enum c_can_bus_error_types error_type) | |
952 | { | |
953 | unsigned int reg_err_counter; | |
954 | unsigned int rx_err_passive; | |
955 | struct c_can_priv *priv = netdev_priv(dev); | |
956 | struct net_device_stats *stats = &dev->stats; | |
957 | struct can_frame *cf; | |
958 | struct sk_buff *skb; | |
959 | struct can_berr_counter bec; | |
960 | ||
25985edc | 961 | /* propagate the error condition to the CAN stack */ |
881ff67a BS |
962 | skb = alloc_can_err_skb(dev, &cf); |
963 | if (unlikely(!skb)) | |
964 | return 0; | |
965 | ||
e35d46ad | 966 | __c_can_get_berr_counter(dev, &bec); |
33f81009 | 967 | reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); |
881ff67a BS |
968 | rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> |
969 | ERR_CNT_RP_SHIFT; | |
970 | ||
971 | switch (error_type) { | |
972 | case C_CAN_ERROR_WARNING: | |
973 | /* error warning state */ | |
974 | priv->can.can_stats.error_warning++; | |
975 | priv->can.state = CAN_STATE_ERROR_WARNING; | |
976 | cf->can_id |= CAN_ERR_CRTL; | |
977 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
978 | CAN_ERR_CRTL_TX_WARNING : | |
979 | CAN_ERR_CRTL_RX_WARNING; | |
980 | cf->data[6] = bec.txerr; | |
981 | cf->data[7] = bec.rxerr; | |
982 | ||
983 | break; | |
984 | case C_CAN_ERROR_PASSIVE: | |
985 | /* error passive state */ | |
986 | priv->can.can_stats.error_passive++; | |
987 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
988 | cf->can_id |= CAN_ERR_CRTL; | |
989 | if (rx_err_passive) | |
990 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | |
991 | if (bec.txerr > 127) | |
992 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; | |
993 | ||
994 | cf->data[6] = bec.txerr; | |
995 | cf->data[7] = bec.rxerr; | |
996 | break; | |
997 | case C_CAN_BUS_OFF: | |
998 | /* bus-off state */ | |
999 | priv->can.state = CAN_STATE_BUS_OFF; | |
1000 | cf->can_id |= CAN_ERR_BUSOFF; | |
1001 | /* | |
1002 | * disable all interrupts in bus-off mode to ensure that | |
1003 | * the CPU is not hogged down | |
1004 | */ | |
1005 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); | |
1006 | can_bus_off(dev); | |
1007 | break; | |
1008 | default: | |
1009 | break; | |
1010 | } | |
1011 | ||
1012 | netif_receive_skb(skb); | |
1013 | stats->rx_packets++; | |
1014 | stats->rx_bytes += cf->can_dlc; | |
1015 | ||
1016 | return 1; | |
1017 | } | |
1018 | ||
1019 | static int c_can_handle_bus_err(struct net_device *dev, | |
1020 | enum c_can_lec_type lec_type) | |
1021 | { | |
1022 | struct c_can_priv *priv = netdev_priv(dev); | |
1023 | struct net_device_stats *stats = &dev->stats; | |
1024 | struct can_frame *cf; | |
1025 | struct sk_buff *skb; | |
1026 | ||
1027 | /* | |
1028 | * early exit if no lec update or no error. | |
1029 | * no lec update means that no CAN bus event has been detected | |
1030 | * since CPU wrote 0x7 value to status reg. | |
1031 | */ | |
1032 | if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) | |
1033 | return 0; | |
1034 | ||
25985edc | 1035 | /* propagate the error condition to the CAN stack */ |
881ff67a BS |
1036 | skb = alloc_can_err_skb(dev, &cf); |
1037 | if (unlikely(!skb)) | |
1038 | return 0; | |
1039 | ||
1040 | /* | |
1041 | * check for 'last error code' which tells us the | |
1042 | * type of the last error to occur on the CAN bus | |
1043 | */ | |
1044 | ||
1045 | /* common for all type of bus errors */ | |
1046 | priv->can.can_stats.bus_error++; | |
1047 | stats->rx_errors++; | |
1048 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
1049 | cf->data[2] |= CAN_ERR_PROT_UNSPEC; | |
1050 | ||
1051 | switch (lec_type) { | |
1052 | case LEC_STUFF_ERROR: | |
1053 | netdev_dbg(dev, "stuff error\n"); | |
1054 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
1055 | break; | |
1056 | case LEC_FORM_ERROR: | |
1057 | netdev_dbg(dev, "form error\n"); | |
1058 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
1059 | break; | |
1060 | case LEC_ACK_ERROR: | |
1061 | netdev_dbg(dev, "ack error\n"); | |
6ea45886 | 1062 | cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | |
881ff67a BS |
1063 | CAN_ERR_PROT_LOC_ACK_DEL); |
1064 | break; | |
1065 | case LEC_BIT1_ERROR: | |
1066 | netdev_dbg(dev, "bit1 error\n"); | |
1067 | cf->data[2] |= CAN_ERR_PROT_BIT1; | |
1068 | break; | |
1069 | case LEC_BIT0_ERROR: | |
1070 | netdev_dbg(dev, "bit0 error\n"); | |
1071 | cf->data[2] |= CAN_ERR_PROT_BIT0; | |
1072 | break; | |
1073 | case LEC_CRC_ERROR: | |
1074 | netdev_dbg(dev, "CRC error\n"); | |
6ea45886 | 1075 | cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | |
881ff67a BS |
1076 | CAN_ERR_PROT_LOC_CRC_DEL); |
1077 | break; | |
1078 | default: | |
1079 | break; | |
1080 | } | |
1081 | ||
1082 | /* set a `lec` value so that we can check for updates later */ | |
33f81009 | 1083 | priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); |
881ff67a BS |
1084 | |
1085 | netif_receive_skb(skb); | |
1086 | stats->rx_packets++; | |
1087 | stats->rx_bytes += cf->can_dlc; | |
1088 | ||
1089 | return 1; | |
1090 | } | |
1091 | ||
1092 | static int c_can_poll(struct napi_struct *napi, int quota) | |
1093 | { | |
1094 | u16 irqstatus; | |
1095 | int lec_type = 0; | |
1096 | int work_done = 0; | |
1097 | struct net_device *dev = napi->dev; | |
1098 | struct c_can_priv *priv = netdev_priv(dev); | |
1099 | ||
148c87c8 | 1100 | irqstatus = priv->irqstatus; |
881ff67a BS |
1101 | if (!irqstatus) |
1102 | goto end; | |
1103 | ||
1104 | /* status events have the highest priority */ | |
1105 | if (irqstatus == STATUS_INTERRUPT) { | |
1106 | priv->current_status = priv->read_reg(priv, | |
33f81009 | 1107 | C_CAN_STS_REG); |
881ff67a BS |
1108 | |
1109 | /* handle Tx/Rx events */ | |
1110 | if (priv->current_status & STATUS_TXOK) | |
33f81009 | 1111 | priv->write_reg(priv, C_CAN_STS_REG, |
881ff67a BS |
1112 | priv->current_status & ~STATUS_TXOK); |
1113 | ||
1114 | if (priv->current_status & STATUS_RXOK) | |
33f81009 | 1115 | priv->write_reg(priv, C_CAN_STS_REG, |
881ff67a BS |
1116 | priv->current_status & ~STATUS_RXOK); |
1117 | ||
1118 | /* handle state changes */ | |
1119 | if ((priv->current_status & STATUS_EWARN) && | |
1120 | (!(priv->last_status & STATUS_EWARN))) { | |
1121 | netdev_dbg(dev, "entered error warning state\n"); | |
1122 | work_done += c_can_handle_state_change(dev, | |
1123 | C_CAN_ERROR_WARNING); | |
1124 | } | |
1125 | if ((priv->current_status & STATUS_EPASS) && | |
1126 | (!(priv->last_status & STATUS_EPASS))) { | |
1127 | netdev_dbg(dev, "entered error passive state\n"); | |
1128 | work_done += c_can_handle_state_change(dev, | |
1129 | C_CAN_ERROR_PASSIVE); | |
1130 | } | |
1131 | if ((priv->current_status & STATUS_BOFF) && | |
1132 | (!(priv->last_status & STATUS_BOFF))) { | |
1133 | netdev_dbg(dev, "entered bus off state\n"); | |
1134 | work_done += c_can_handle_state_change(dev, | |
1135 | C_CAN_BUS_OFF); | |
1136 | } | |
1137 | ||
1138 | /* handle bus recovery events */ | |
1139 | if ((!(priv->current_status & STATUS_BOFF)) && | |
1140 | (priv->last_status & STATUS_BOFF)) { | |
1141 | netdev_dbg(dev, "left bus off state\n"); | |
1142 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1143 | } | |
1144 | if ((!(priv->current_status & STATUS_EPASS)) && | |
1145 | (priv->last_status & STATUS_EPASS)) { | |
1146 | netdev_dbg(dev, "left error passive state\n"); | |
1147 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1148 | } | |
1149 | ||
1150 | priv->last_status = priv->current_status; | |
1151 | ||
1152 | /* handle lec errors on the bus */ | |
1153 | lec_type = c_can_has_and_handle_berr(priv); | |
1154 | if (lec_type) | |
1155 | work_done += c_can_handle_bus_err(dev, lec_type); | |
1156 | } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && | |
1157 | (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { | |
1158 | /* handle events corresponding to receive message objects */ | |
1159 | work_done += c_can_do_rx_poll(dev, (quota - work_done)); | |
1160 | } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && | |
1161 | (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { | |
1162 | /* handle events corresponding to transmit message objects */ | |
1163 | c_can_do_tx(dev); | |
1164 | } | |
1165 | ||
1166 | end: | |
1167 | if (work_done < quota) { | |
1168 | napi_complete(napi); | |
1169 | /* enable all IRQs */ | |
1170 | c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); | |
1171 | } | |
1172 | ||
1173 | return work_done; | |
1174 | } | |
1175 | ||
1176 | static irqreturn_t c_can_isr(int irq, void *dev_id) | |
1177 | { | |
881ff67a BS |
1178 | struct net_device *dev = (struct net_device *)dev_id; |
1179 | struct c_can_priv *priv = netdev_priv(dev); | |
1180 | ||
33f81009 | 1181 | priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); |
148c87c8 | 1182 | if (!priv->irqstatus) |
881ff67a BS |
1183 | return IRQ_NONE; |
1184 | ||
1185 | /* disable all interrupts and schedule the NAPI */ | |
1186 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); | |
1187 | napi_schedule(&priv->napi); | |
1188 | ||
1189 | return IRQ_HANDLED; | |
1190 | } | |
1191 | ||
1192 | static int c_can_open(struct net_device *dev) | |
1193 | { | |
1194 | int err; | |
1195 | struct c_can_priv *priv = netdev_priv(dev); | |
1196 | ||
4cdd34b2 | 1197 | c_can_pm_runtime_get_sync(priv); |
52cde85a | 1198 | c_can_reset_ram(priv, true); |
4cdd34b2 | 1199 | |
881ff67a BS |
1200 | /* open the can device */ |
1201 | err = open_candev(dev); | |
1202 | if (err) { | |
1203 | netdev_err(dev, "failed to open can device\n"); | |
4cdd34b2 | 1204 | goto exit_open_fail; |
881ff67a BS |
1205 | } |
1206 | ||
1207 | /* register interrupt handler */ | |
1208 | err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, | |
1209 | dev); | |
1210 | if (err < 0) { | |
1211 | netdev_err(dev, "failed to request interrupt\n"); | |
1212 | goto exit_irq_fail; | |
1213 | } | |
1214 | ||
130a5171 MKB |
1215 | /* start the c_can controller */ |
1216 | err = c_can_start(dev); | |
1217 | if (err) | |
1218 | goto exit_start_fail; | |
f461f27a | 1219 | |
5090f805 FB |
1220 | can_led_event(dev, CAN_LED_EVENT_OPEN); |
1221 | ||
130a5171 | 1222 | napi_enable(&priv->napi); |
881ff67a BS |
1223 | netif_start_queue(dev); |
1224 | ||
1225 | return 0; | |
1226 | ||
130a5171 MKB |
1227 | exit_start_fail: |
1228 | free_irq(dev->irq, dev); | |
881ff67a BS |
1229 | exit_irq_fail: |
1230 | close_candev(dev); | |
4cdd34b2 | 1231 | exit_open_fail: |
52cde85a | 1232 | c_can_reset_ram(priv, false); |
4cdd34b2 | 1233 | c_can_pm_runtime_put_sync(priv); |
881ff67a BS |
1234 | return err; |
1235 | } | |
1236 | ||
1237 | static int c_can_close(struct net_device *dev) | |
1238 | { | |
1239 | struct c_can_priv *priv = netdev_priv(dev); | |
1240 | ||
1241 | netif_stop_queue(dev); | |
1242 | napi_disable(&priv->napi); | |
1243 | c_can_stop(dev); | |
1244 | free_irq(dev->irq, dev); | |
1245 | close_candev(dev); | |
52cde85a AC |
1246 | |
1247 | c_can_reset_ram(priv, false); | |
4cdd34b2 | 1248 | c_can_pm_runtime_put_sync(priv); |
881ff67a | 1249 | |
5090f805 FB |
1250 | can_led_event(dev, CAN_LED_EVENT_STOP); |
1251 | ||
881ff67a BS |
1252 | return 0; |
1253 | } | |
1254 | ||
1255 | struct net_device *alloc_c_can_dev(void) | |
1256 | { | |
1257 | struct net_device *dev; | |
1258 | struct c_can_priv *priv; | |
1259 | ||
1260 | dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); | |
1261 | if (!dev) | |
1262 | return NULL; | |
1263 | ||
1264 | priv = netdev_priv(dev); | |
1265 | netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); | |
1266 | ||
1267 | priv->dev = dev; | |
1268 | priv->can.bittiming_const = &c_can_bittiming_const; | |
1269 | priv->can.do_set_mode = c_can_set_mode; | |
1270 | priv->can.do_get_berr_counter = c_can_get_berr_counter; | |
ee6f0988 | 1271 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | |
881ff67a BS |
1272 | CAN_CTRLMODE_LISTENONLY | |
1273 | CAN_CTRLMODE_BERR_REPORTING; | |
1274 | ||
1275 | return dev; | |
1276 | } | |
1277 | EXPORT_SYMBOL_GPL(alloc_c_can_dev); | |
1278 | ||
82120032 AC |
1279 | #ifdef CONFIG_PM |
1280 | int c_can_power_down(struct net_device *dev) | |
1281 | { | |
1282 | u32 val; | |
1283 | unsigned long time_out; | |
1284 | struct c_can_priv *priv = netdev_priv(dev); | |
1285 | ||
1286 | if (!(dev->flags & IFF_UP)) | |
1287 | return 0; | |
1288 | ||
1289 | WARN_ON(priv->type != BOSCH_D_CAN); | |
1290 | ||
1291 | /* set PDR value so the device goes to power down mode */ | |
1292 | val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); | |
1293 | val |= CONTROL_EX_PDR; | |
1294 | priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); | |
1295 | ||
1296 | /* Wait for the PDA bit to get set */ | |
1297 | time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); | |
1298 | while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && | |
1299 | time_after(time_out, jiffies)) | |
1300 | cpu_relax(); | |
1301 | ||
1302 | if (time_after(jiffies, time_out)) | |
1303 | return -ETIMEDOUT; | |
1304 | ||
1305 | c_can_stop(dev); | |
1306 | ||
52cde85a | 1307 | c_can_reset_ram(priv, false); |
82120032 AC |
1308 | c_can_pm_runtime_put_sync(priv); |
1309 | ||
1310 | return 0; | |
1311 | } | |
1312 | EXPORT_SYMBOL_GPL(c_can_power_down); | |
1313 | ||
1314 | int c_can_power_up(struct net_device *dev) | |
1315 | { | |
1316 | u32 val; | |
1317 | unsigned long time_out; | |
1318 | struct c_can_priv *priv = netdev_priv(dev); | |
1319 | ||
1320 | if (!(dev->flags & IFF_UP)) | |
1321 | return 0; | |
1322 | ||
1323 | WARN_ON(priv->type != BOSCH_D_CAN); | |
1324 | ||
1325 | c_can_pm_runtime_get_sync(priv); | |
52cde85a | 1326 | c_can_reset_ram(priv, true); |
82120032 AC |
1327 | |
1328 | /* Clear PDR and INIT bits */ | |
1329 | val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); | |
1330 | val &= ~CONTROL_EX_PDR; | |
1331 | priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); | |
1332 | val = priv->read_reg(priv, C_CAN_CTRL_REG); | |
1333 | val &= ~CONTROL_INIT; | |
1334 | priv->write_reg(priv, C_CAN_CTRL_REG, val); | |
1335 | ||
1336 | /* Wait for the PDA bit to get clear */ | |
1337 | time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); | |
1338 | while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && | |
1339 | time_after(time_out, jiffies)) | |
1340 | cpu_relax(); | |
1341 | ||
1342 | if (time_after(jiffies, time_out)) | |
1343 | return -ETIMEDOUT; | |
1344 | ||
130a5171 | 1345 | return c_can_start(dev); |
82120032 AC |
1346 | } |
1347 | EXPORT_SYMBOL_GPL(c_can_power_up); | |
1348 | #endif | |
1349 | ||
881ff67a BS |
1350 | void free_c_can_dev(struct net_device *dev) |
1351 | { | |
f29b4238 MKB |
1352 | struct c_can_priv *priv = netdev_priv(dev); |
1353 | ||
1354 | netif_napi_del(&priv->napi); | |
881ff67a BS |
1355 | free_candev(dev); |
1356 | } | |
1357 | EXPORT_SYMBOL_GPL(free_c_can_dev); | |
1358 | ||
1359 | static const struct net_device_ops c_can_netdev_ops = { | |
1360 | .ndo_open = c_can_open, | |
1361 | .ndo_stop = c_can_close, | |
1362 | .ndo_start_xmit = c_can_start_xmit, | |
1363 | }; | |
1364 | ||
1365 | int register_c_can_dev(struct net_device *dev) | |
1366 | { | |
4cdd34b2 AC |
1367 | struct c_can_priv *priv = netdev_priv(dev); |
1368 | int err; | |
1369 | ||
1370 | c_can_pm_runtime_enable(priv); | |
1371 | ||
881ff67a BS |
1372 | dev->flags |= IFF_ECHO; /* we support local echo */ |
1373 | dev->netdev_ops = &c_can_netdev_ops; | |
1374 | ||
4cdd34b2 AC |
1375 | err = register_candev(dev); |
1376 | if (err) | |
1377 | c_can_pm_runtime_disable(priv); | |
5090f805 FB |
1378 | else |
1379 | devm_can_led_init(dev); | |
4cdd34b2 AC |
1380 | |
1381 | return err; | |
881ff67a BS |
1382 | } |
1383 | EXPORT_SYMBOL_GPL(register_c_can_dev); | |
1384 | ||
1385 | void unregister_c_can_dev(struct net_device *dev) | |
1386 | { | |
1387 | struct c_can_priv *priv = netdev_priv(dev); | |
1388 | ||
881ff67a | 1389 | unregister_candev(dev); |
4cdd34b2 AC |
1390 | |
1391 | c_can_pm_runtime_disable(priv); | |
881ff67a BS |
1392 | } |
1393 | EXPORT_SYMBOL_GPL(unregister_c_can_dev); | |
1394 | ||
1395 | MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); | |
1396 | MODULE_LICENSE("GPL v2"); | |
1397 | MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); |