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e955cead MKB |
1 | /* |
2 | * flexcan.c - FLEXCAN CAN controller driver | |
3 | * | |
4 | * Copyright (c) 2005-2006 Varma Electronics Oy | |
5 | * Copyright (c) 2009 Sascha Hauer, Pengutronix | |
6 | * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix | |
7 | * | |
8 | * Based on code originally by Andrey Volkov <avolkov@varma-el.com> | |
9 | * | |
10 | * LICENCE: | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation version 2. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/netdevice.h> | |
23 | #include <linux/can.h> | |
24 | #include <linux/can/dev.h> | |
25 | #include <linux/can/error.h> | |
adccadb9 | 26 | #include <linux/can/led.h> |
e955cead MKB |
27 | #include <linux/clk.h> |
28 | #include <linux/delay.h> | |
29 | #include <linux/if_arp.h> | |
30 | #include <linux/if_ether.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/module.h> | |
97efe9ae | 36 | #include <linux/of.h> |
30c1e672 | 37 | #include <linux/of_device.h> |
e955cead | 38 | #include <linux/platform_device.h> |
b7c4114b | 39 | #include <linux/regulator/consumer.h> |
e955cead | 40 | |
e955cead MKB |
41 | #define DRV_NAME "flexcan" |
42 | ||
43 | /* 8 for RX fifo and 2 error handling */ | |
44 | #define FLEXCAN_NAPI_WEIGHT (8 + 2) | |
45 | ||
46 | /* FLEXCAN module configuration register (CANMCR) bits */ | |
47 | #define FLEXCAN_MCR_MDIS BIT(31) | |
48 | #define FLEXCAN_MCR_FRZ BIT(30) | |
49 | #define FLEXCAN_MCR_FEN BIT(29) | |
50 | #define FLEXCAN_MCR_HALT BIT(28) | |
51 | #define FLEXCAN_MCR_NOT_RDY BIT(27) | |
52 | #define FLEXCAN_MCR_WAK_MSK BIT(26) | |
53 | #define FLEXCAN_MCR_SOFTRST BIT(25) | |
54 | #define FLEXCAN_MCR_FRZ_ACK BIT(24) | |
55 | #define FLEXCAN_MCR_SUPV BIT(23) | |
56 | #define FLEXCAN_MCR_SLF_WAK BIT(22) | |
57 | #define FLEXCAN_MCR_WRN_EN BIT(21) | |
58 | #define FLEXCAN_MCR_LPM_ACK BIT(20) | |
59 | #define FLEXCAN_MCR_WAK_SRC BIT(19) | |
60 | #define FLEXCAN_MCR_DOZE BIT(18) | |
61 | #define FLEXCAN_MCR_SRX_DIS BIT(17) | |
62 | #define FLEXCAN_MCR_BCC BIT(16) | |
63 | #define FLEXCAN_MCR_LPRIO_EN BIT(13) | |
64 | #define FLEXCAN_MCR_AEN BIT(12) | |
4c728d80 | 65 | #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) |
e955cead MKB |
66 | #define FLEXCAN_MCR_IDAM_A (0 << 8) |
67 | #define FLEXCAN_MCR_IDAM_B (1 << 8) | |
68 | #define FLEXCAN_MCR_IDAM_C (2 << 8) | |
69 | #define FLEXCAN_MCR_IDAM_D (3 << 8) | |
70 | ||
71 | /* FLEXCAN control register (CANCTRL) bits */ | |
72 | #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) | |
73 | #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) | |
74 | #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) | |
75 | #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) | |
76 | #define FLEXCAN_CTRL_BOFF_MSK BIT(15) | |
77 | #define FLEXCAN_CTRL_ERR_MSK BIT(14) | |
78 | #define FLEXCAN_CTRL_CLK_SRC BIT(13) | |
79 | #define FLEXCAN_CTRL_LPB BIT(12) | |
80 | #define FLEXCAN_CTRL_TWRN_MSK BIT(11) | |
81 | #define FLEXCAN_CTRL_RWRN_MSK BIT(10) | |
82 | #define FLEXCAN_CTRL_SMP BIT(7) | |
83 | #define FLEXCAN_CTRL_BOFF_REC BIT(6) | |
84 | #define FLEXCAN_CTRL_TSYN BIT(5) | |
85 | #define FLEXCAN_CTRL_LBUF BIT(4) | |
86 | #define FLEXCAN_CTRL_LOM BIT(3) | |
87 | #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) | |
88 | #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) | |
89 | #define FLEXCAN_CTRL_ERR_STATE \ | |
90 | (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ | |
91 | FLEXCAN_CTRL_BOFF_MSK) | |
92 | #define FLEXCAN_CTRL_ERR_ALL \ | |
93 | (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) | |
94 | ||
95 | /* FLEXCAN error and status register (ESR) bits */ | |
96 | #define FLEXCAN_ESR_TWRN_INT BIT(17) | |
97 | #define FLEXCAN_ESR_RWRN_INT BIT(16) | |
98 | #define FLEXCAN_ESR_BIT1_ERR BIT(15) | |
99 | #define FLEXCAN_ESR_BIT0_ERR BIT(14) | |
100 | #define FLEXCAN_ESR_ACK_ERR BIT(13) | |
101 | #define FLEXCAN_ESR_CRC_ERR BIT(12) | |
102 | #define FLEXCAN_ESR_FRM_ERR BIT(11) | |
103 | #define FLEXCAN_ESR_STF_ERR BIT(10) | |
104 | #define FLEXCAN_ESR_TX_WRN BIT(9) | |
105 | #define FLEXCAN_ESR_RX_WRN BIT(8) | |
106 | #define FLEXCAN_ESR_IDLE BIT(7) | |
107 | #define FLEXCAN_ESR_TXRX BIT(6) | |
108 | #define FLEXCAN_EST_FLT_CONF_SHIFT (4) | |
109 | #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
110 | #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
111 | #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
112 | #define FLEXCAN_ESR_BOFF_INT BIT(2) | |
113 | #define FLEXCAN_ESR_ERR_INT BIT(1) | |
114 | #define FLEXCAN_ESR_WAK_INT BIT(0) | |
115 | #define FLEXCAN_ESR_ERR_BUS \ | |
116 | (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ | |
117 | FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ | |
118 | FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) | |
119 | #define FLEXCAN_ESR_ERR_STATE \ | |
120 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) | |
121 | #define FLEXCAN_ESR_ERR_ALL \ | |
122 | (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) | |
6e9d554f WG |
123 | #define FLEXCAN_ESR_ALL_INT \ |
124 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ | |
125 | FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) | |
e955cead MKB |
126 | |
127 | /* FLEXCAN interrupt flag register (IFLAG) bits */ | |
25e92445 DJ |
128 | /* Errata ERR005829 step7: Reserve first valid MB */ |
129 | #define FLEXCAN_TX_BUF_RESERVED 8 | |
130 | #define FLEXCAN_TX_BUF_ID 9 | |
e955cead MKB |
131 | #define FLEXCAN_IFLAG_BUF(x) BIT(x) |
132 | #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) | |
133 | #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) | |
134 | #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) | |
135 | #define FLEXCAN_IFLAG_DEFAULT \ | |
136 | (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ | |
137 | FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) | |
138 | ||
139 | /* FLEXCAN message buffers */ | |
140 | #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) | |
c32fe4ad MKB |
141 | #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) |
142 | #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) | |
143 | #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) | |
144 | #define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24) | |
145 | #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) | |
146 | ||
147 | #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) | |
148 | #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) | |
149 | #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) | |
150 | #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) | |
151 | ||
e955cead MKB |
152 | #define FLEXCAN_MB_CNT_SRR BIT(22) |
153 | #define FLEXCAN_MB_CNT_IDE BIT(21) | |
154 | #define FLEXCAN_MB_CNT_RTR BIT(20) | |
155 | #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) | |
156 | #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) | |
157 | ||
158 | #define FLEXCAN_MB_CODE_MASK (0xf0ffffff) | |
159 | ||
9b00b300 MKB |
160 | #define FLEXCAN_TIMEOUT_US (50) |
161 | ||
bb698ca4 WG |
162 | /* |
163 | * FLEXCAN hardware feature flags | |
164 | * | |
165 | * Below is some version info we got: | |
166 | * SOC Version IP-Version Glitch- [TR]WRN_INT | |
167 | * Filter? connected? | |
168 | * MX25 FlexCAN2 03.00.00.00 no no | |
169 | * MX28 FlexCAN2 03.00.04.00 yes yes | |
170 | * MX35 FlexCAN2 03.00.00.00 no no | |
171 | * MX53 FlexCAN2 03.00.00.00 yes no | |
172 | * MX6s FlexCAN3 10.00.12.00 yes yes | |
173 | * | |
174 | * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. | |
175 | */ | |
4f72e5f0 | 176 | #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ |
bb698ca4 | 177 | #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ |
4f72e5f0 | 178 | |
e955cead MKB |
179 | /* Structure of the message buffer */ |
180 | struct flexcan_mb { | |
181 | u32 can_ctrl; | |
182 | u32 can_id; | |
183 | u32 data[2]; | |
184 | }; | |
185 | ||
186 | /* Structure of the hardware registers */ | |
187 | struct flexcan_regs { | |
188 | u32 mcr; /* 0x00 */ | |
189 | u32 ctrl; /* 0x04 */ | |
190 | u32 timer; /* 0x08 */ | |
191 | u32 _reserved1; /* 0x0c */ | |
192 | u32 rxgmask; /* 0x10 */ | |
193 | u32 rx14mask; /* 0x14 */ | |
194 | u32 rx15mask; /* 0x18 */ | |
195 | u32 ecr; /* 0x1c */ | |
196 | u32 esr; /* 0x20 */ | |
197 | u32 imask2; /* 0x24 */ | |
198 | u32 imask1; /* 0x28 */ | |
199 | u32 iflag2; /* 0x2c */ | |
200 | u32 iflag1; /* 0x30 */ | |
30c1e672 HW |
201 | u32 crl2; /* 0x34 */ |
202 | u32 esr2; /* 0x38 */ | |
203 | u32 imeur; /* 0x3c */ | |
204 | u32 lrfr; /* 0x40 */ | |
205 | u32 crcr; /* 0x44 */ | |
206 | u32 rxfgmask; /* 0x48 */ | |
207 | u32 rxfir; /* 0x4c */ | |
208 | u32 _reserved3[12]; | |
e955cead MKB |
209 | struct flexcan_mb cantxfg[64]; |
210 | }; | |
211 | ||
30c1e672 | 212 | struct flexcan_devtype_data { |
4f72e5f0 | 213 | u32 features; /* hardware controller features */ |
30c1e672 HW |
214 | }; |
215 | ||
e955cead MKB |
216 | struct flexcan_priv { |
217 | struct can_priv can; | |
218 | struct net_device *dev; | |
219 | struct napi_struct napi; | |
220 | ||
221 | void __iomem *base; | |
222 | u32 reg_esr; | |
223 | u32 reg_ctrl_default; | |
224 | ||
3d42a379 ST |
225 | struct clk *clk_ipg; |
226 | struct clk *clk_per; | |
e955cead | 227 | struct flexcan_platform_data *pdata; |
dda0b3bd | 228 | const struct flexcan_devtype_data *devtype_data; |
b7c4114b | 229 | struct regulator *reg_xceiver; |
30c1e672 HW |
230 | }; |
231 | ||
232 | static struct flexcan_devtype_data fsl_p1010_devtype_data = { | |
4f72e5f0 | 233 | .features = FLEXCAN_HAS_BROKEN_ERR_STATE, |
30c1e672 | 234 | }; |
4f72e5f0 | 235 | static struct flexcan_devtype_data fsl_imx28_devtype_data; |
30c1e672 | 236 | static struct flexcan_devtype_data fsl_imx6q_devtype_data = { |
bb698ca4 | 237 | .features = FLEXCAN_HAS_V10_FEATURES, |
e955cead MKB |
238 | }; |
239 | ||
194b9a4c | 240 | static const struct can_bittiming_const flexcan_bittiming_const = { |
e955cead MKB |
241 | .name = DRV_NAME, |
242 | .tseg1_min = 4, | |
243 | .tseg1_max = 16, | |
244 | .tseg2_min = 2, | |
245 | .tseg2_max = 8, | |
246 | .sjw_max = 4, | |
247 | .brp_min = 1, | |
248 | .brp_max = 256, | |
249 | .brp_inc = 1, | |
250 | }; | |
251 | ||
61e271ee | 252 | /* |
0e4b949e AB |
253 | * Abstract off the read/write for arm versus ppc. This |
254 | * assumes that PPC uses big-endian registers and everything | |
255 | * else uses little-endian registers, independent of CPU | |
256 | * endianess. | |
61e271ee | 257 | */ |
0e4b949e | 258 | #if defined(CONFIG_PPC) |
61e271ee | 259 | static inline u32 flexcan_read(void __iomem *addr) |
260 | { | |
261 | return in_be32(addr); | |
262 | } | |
263 | ||
264 | static inline void flexcan_write(u32 val, void __iomem *addr) | |
265 | { | |
266 | out_be32(addr, val); | |
267 | } | |
268 | #else | |
269 | static inline u32 flexcan_read(void __iomem *addr) | |
270 | { | |
271 | return readl(addr); | |
272 | } | |
273 | ||
274 | static inline void flexcan_write(u32 val, void __iomem *addr) | |
275 | { | |
276 | writel(val, addr); | |
277 | } | |
278 | #endif | |
279 | ||
f003698e MKB |
280 | static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) |
281 | { | |
282 | if (!priv->reg_xceiver) | |
283 | return 0; | |
284 | ||
285 | return regulator_enable(priv->reg_xceiver); | |
286 | } | |
287 | ||
288 | static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) | |
289 | { | |
290 | if (!priv->reg_xceiver) | |
291 | return 0; | |
292 | ||
293 | return regulator_disable(priv->reg_xceiver); | |
294 | } | |
295 | ||
e955cead MKB |
296 | static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, |
297 | u32 reg_esr) | |
298 | { | |
299 | return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && | |
300 | (reg_esr & FLEXCAN_ESR_ERR_BUS); | |
301 | } | |
302 | ||
9b00b300 | 303 | static int flexcan_chip_enable(struct flexcan_priv *priv) |
e955cead MKB |
304 | { |
305 | struct flexcan_regs __iomem *regs = priv->base; | |
9b00b300 | 306 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
e955cead MKB |
307 | u32 reg; |
308 | ||
61e271ee | 309 | reg = flexcan_read(®s->mcr); |
e955cead | 310 | reg &= ~FLEXCAN_MCR_MDIS; |
61e271ee | 311 | flexcan_write(reg, ®s->mcr); |
e955cead | 312 | |
9b00b300 | 313 | while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) |
8badd65e | 314 | udelay(10); |
9b00b300 MKB |
315 | |
316 | if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) | |
317 | return -ETIMEDOUT; | |
318 | ||
319 | return 0; | |
e955cead MKB |
320 | } |
321 | ||
9b00b300 | 322 | static int flexcan_chip_disable(struct flexcan_priv *priv) |
e955cead MKB |
323 | { |
324 | struct flexcan_regs __iomem *regs = priv->base; | |
9b00b300 | 325 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
e955cead MKB |
326 | u32 reg; |
327 | ||
61e271ee | 328 | reg = flexcan_read(®s->mcr); |
e955cead | 329 | reg |= FLEXCAN_MCR_MDIS; |
61e271ee | 330 | flexcan_write(reg, ®s->mcr); |
9b00b300 MKB |
331 | |
332 | while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) | |
8badd65e | 333 | udelay(10); |
9b00b300 MKB |
334 | |
335 | if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) | |
336 | return -ETIMEDOUT; | |
337 | ||
338 | return 0; | |
e955cead MKB |
339 | } |
340 | ||
b1aa1c7a MKB |
341 | static int flexcan_chip_freeze(struct flexcan_priv *priv) |
342 | { | |
343 | struct flexcan_regs __iomem *regs = priv->base; | |
344 | unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate; | |
345 | u32 reg; | |
346 | ||
347 | reg = flexcan_read(®s->mcr); | |
348 | reg |= FLEXCAN_MCR_HALT; | |
349 | flexcan_write(reg, ®s->mcr); | |
350 | ||
351 | while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) | |
8badd65e | 352 | udelay(100); |
b1aa1c7a MKB |
353 | |
354 | if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) | |
355 | return -ETIMEDOUT; | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | static int flexcan_chip_unfreeze(struct flexcan_priv *priv) | |
361 | { | |
362 | struct flexcan_regs __iomem *regs = priv->base; | |
363 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; | |
364 | u32 reg; | |
365 | ||
366 | reg = flexcan_read(®s->mcr); | |
367 | reg &= ~FLEXCAN_MCR_HALT; | |
368 | flexcan_write(reg, ®s->mcr); | |
369 | ||
370 | while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) | |
8badd65e | 371 | udelay(10); |
b1aa1c7a MKB |
372 | |
373 | if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) | |
374 | return -ETIMEDOUT; | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
4b5b8227 MKB |
379 | static int flexcan_chip_softreset(struct flexcan_priv *priv) |
380 | { | |
381 | struct flexcan_regs __iomem *regs = priv->base; | |
382 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; | |
383 | ||
384 | flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); | |
385 | while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) | |
8badd65e | 386 | udelay(10); |
4b5b8227 MKB |
387 | |
388 | if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST) | |
389 | return -ETIMEDOUT; | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
e955cead MKB |
394 | static int flexcan_get_berr_counter(const struct net_device *dev, |
395 | struct can_berr_counter *bec) | |
396 | { | |
397 | const struct flexcan_priv *priv = netdev_priv(dev); | |
398 | struct flexcan_regs __iomem *regs = priv->base; | |
61e271ee | 399 | u32 reg = flexcan_read(®s->ecr); |
e955cead MKB |
400 | |
401 | bec->txerr = (reg >> 0) & 0xff; | |
402 | bec->rxerr = (reg >> 8) & 0xff; | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
408 | { | |
409 | const struct flexcan_priv *priv = netdev_priv(dev); | |
e955cead MKB |
410 | struct flexcan_regs __iomem *regs = priv->base; |
411 | struct can_frame *cf = (struct can_frame *)skb->data; | |
412 | u32 can_id; | |
413 | u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); | |
414 | ||
415 | if (can_dropped_invalid_skb(dev, skb)) | |
416 | return NETDEV_TX_OK; | |
417 | ||
418 | netif_stop_queue(dev); | |
419 | ||
420 | if (cf->can_id & CAN_EFF_FLAG) { | |
421 | can_id = cf->can_id & CAN_EFF_MASK; | |
422 | ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; | |
423 | } else { | |
424 | can_id = (cf->can_id & CAN_SFF_MASK) << 18; | |
425 | } | |
426 | ||
427 | if (cf->can_id & CAN_RTR_FLAG) | |
428 | ctrl |= FLEXCAN_MB_CNT_RTR; | |
429 | ||
430 | if (cf->can_dlc > 0) { | |
431 | u32 data = be32_to_cpup((__be32 *)&cf->data[0]); | |
61e271ee | 432 | flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); |
e955cead MKB |
433 | } |
434 | if (cf->can_dlc > 3) { | |
435 | u32 data = be32_to_cpup((__be32 *)&cf->data[4]); | |
61e271ee | 436 | flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); |
e955cead MKB |
437 | } |
438 | ||
9a123496 RD |
439 | can_put_echo_skb(skb, dev, 0); |
440 | ||
61e271ee | 441 | flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); |
442 | flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); | |
e955cead | 443 | |
25e92445 DJ |
444 | /* Errata ERR005829 step8: |
445 | * Write twice INACTIVE(0x8) code to first MB. | |
446 | */ | |
447 | flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, | |
448 | ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); | |
449 | flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, | |
450 | ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); | |
451 | ||
e955cead MKB |
452 | return NETDEV_TX_OK; |
453 | } | |
454 | ||
455 | static void do_bus_err(struct net_device *dev, | |
456 | struct can_frame *cf, u32 reg_esr) | |
457 | { | |
458 | struct flexcan_priv *priv = netdev_priv(dev); | |
459 | int rx_errors = 0, tx_errors = 0; | |
460 | ||
461 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
462 | ||
463 | if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { | |
aabdfd6a | 464 | netdev_dbg(dev, "BIT1_ERR irq\n"); |
e955cead MKB |
465 | cf->data[2] |= CAN_ERR_PROT_BIT1; |
466 | tx_errors = 1; | |
467 | } | |
468 | if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { | |
aabdfd6a | 469 | netdev_dbg(dev, "BIT0_ERR irq\n"); |
e955cead MKB |
470 | cf->data[2] |= CAN_ERR_PROT_BIT0; |
471 | tx_errors = 1; | |
472 | } | |
473 | if (reg_esr & FLEXCAN_ESR_ACK_ERR) { | |
aabdfd6a | 474 | netdev_dbg(dev, "ACK_ERR irq\n"); |
e955cead MKB |
475 | cf->can_id |= CAN_ERR_ACK; |
476 | cf->data[3] |= CAN_ERR_PROT_LOC_ACK; | |
477 | tx_errors = 1; | |
478 | } | |
479 | if (reg_esr & FLEXCAN_ESR_CRC_ERR) { | |
aabdfd6a | 480 | netdev_dbg(dev, "CRC_ERR irq\n"); |
e955cead MKB |
481 | cf->data[2] |= CAN_ERR_PROT_BIT; |
482 | cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; | |
483 | rx_errors = 1; | |
484 | } | |
485 | if (reg_esr & FLEXCAN_ESR_FRM_ERR) { | |
aabdfd6a | 486 | netdev_dbg(dev, "FRM_ERR irq\n"); |
e955cead MKB |
487 | cf->data[2] |= CAN_ERR_PROT_FORM; |
488 | rx_errors = 1; | |
489 | } | |
490 | if (reg_esr & FLEXCAN_ESR_STF_ERR) { | |
aabdfd6a | 491 | netdev_dbg(dev, "STF_ERR irq\n"); |
e955cead MKB |
492 | cf->data[2] |= CAN_ERR_PROT_STUFF; |
493 | rx_errors = 1; | |
494 | } | |
495 | ||
496 | priv->can.can_stats.bus_error++; | |
497 | if (rx_errors) | |
498 | dev->stats.rx_errors++; | |
499 | if (tx_errors) | |
500 | dev->stats.tx_errors++; | |
501 | } | |
502 | ||
503 | static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) | |
504 | { | |
505 | struct sk_buff *skb; | |
506 | struct can_frame *cf; | |
507 | ||
508 | skb = alloc_can_err_skb(dev, &cf); | |
509 | if (unlikely(!skb)) | |
510 | return 0; | |
511 | ||
512 | do_bus_err(dev, cf, reg_esr); | |
513 | netif_receive_skb(skb); | |
514 | ||
515 | dev->stats.rx_packets++; | |
516 | dev->stats.rx_bytes += cf->can_dlc; | |
517 | ||
518 | return 1; | |
519 | } | |
520 | ||
521 | static void do_state(struct net_device *dev, | |
522 | struct can_frame *cf, enum can_state new_state) | |
523 | { | |
524 | struct flexcan_priv *priv = netdev_priv(dev); | |
525 | struct can_berr_counter bec; | |
526 | ||
527 | flexcan_get_berr_counter(dev, &bec); | |
528 | ||
529 | switch (priv->can.state) { | |
530 | case CAN_STATE_ERROR_ACTIVE: | |
531 | /* | |
532 | * from: ERROR_ACTIVE | |
533 | * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF | |
534 | * => : there was a warning int | |
535 | */ | |
536 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
537 | new_state <= CAN_STATE_BUS_OFF) { | |
aabdfd6a | 538 | netdev_dbg(dev, "Error Warning IRQ\n"); |
e955cead MKB |
539 | priv->can.can_stats.error_warning++; |
540 | ||
541 | cf->can_id |= CAN_ERR_CRTL; | |
542 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
543 | CAN_ERR_CRTL_TX_WARNING : | |
544 | CAN_ERR_CRTL_RX_WARNING; | |
545 | } | |
546 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
547 | /* | |
548 | * from: ERROR_ACTIVE, ERROR_WARNING | |
549 | * to : ERROR_PASSIVE, BUS_OFF | |
550 | * => : error passive int | |
551 | */ | |
552 | if (new_state >= CAN_STATE_ERROR_PASSIVE && | |
553 | new_state <= CAN_STATE_BUS_OFF) { | |
aabdfd6a | 554 | netdev_dbg(dev, "Error Passive IRQ\n"); |
e955cead MKB |
555 | priv->can.can_stats.error_passive++; |
556 | ||
557 | cf->can_id |= CAN_ERR_CRTL; | |
558 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
559 | CAN_ERR_CRTL_TX_PASSIVE : | |
560 | CAN_ERR_CRTL_RX_PASSIVE; | |
561 | } | |
562 | break; | |
563 | case CAN_STATE_BUS_OFF: | |
aabdfd6a WG |
564 | netdev_err(dev, "BUG! " |
565 | "hardware recovered automatically from BUS_OFF\n"); | |
e955cead MKB |
566 | break; |
567 | default: | |
568 | break; | |
569 | } | |
570 | ||
571 | /* process state changes depending on the new state */ | |
572 | switch (new_state) { | |
8ce261d0 SAS |
573 | case CAN_STATE_ERROR_WARNING: |
574 | netdev_dbg(dev, "Error Warning\n"); | |
575 | cf->can_id |= CAN_ERR_CRTL; | |
576 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
577 | CAN_ERR_CRTL_TX_WARNING : | |
578 | CAN_ERR_CRTL_RX_WARNING; | |
579 | break; | |
e955cead | 580 | case CAN_STATE_ERROR_ACTIVE: |
aabdfd6a | 581 | netdev_dbg(dev, "Error Active\n"); |
e955cead MKB |
582 | cf->can_id |= CAN_ERR_PROT; |
583 | cf->data[2] = CAN_ERR_PROT_ACTIVE; | |
584 | break; | |
585 | case CAN_STATE_BUS_OFF: | |
586 | cf->can_id |= CAN_ERR_BUSOFF; | |
587 | can_bus_off(dev); | |
588 | break; | |
589 | default: | |
590 | break; | |
591 | } | |
592 | } | |
593 | ||
594 | static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) | |
595 | { | |
596 | struct flexcan_priv *priv = netdev_priv(dev); | |
597 | struct sk_buff *skb; | |
598 | struct can_frame *cf; | |
599 | enum can_state new_state; | |
600 | int flt; | |
601 | ||
602 | flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; | |
603 | if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { | |
604 | if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | | |
605 | FLEXCAN_ESR_RX_WRN)))) | |
606 | new_state = CAN_STATE_ERROR_ACTIVE; | |
607 | else | |
608 | new_state = CAN_STATE_ERROR_WARNING; | |
609 | } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) | |
610 | new_state = CAN_STATE_ERROR_PASSIVE; | |
611 | else | |
612 | new_state = CAN_STATE_BUS_OFF; | |
613 | ||
614 | /* state hasn't changed */ | |
615 | if (likely(new_state == priv->can.state)) | |
616 | return 0; | |
617 | ||
618 | skb = alloc_can_err_skb(dev, &cf); | |
619 | if (unlikely(!skb)) | |
620 | return 0; | |
621 | ||
622 | do_state(dev, cf, new_state); | |
623 | priv->can.state = new_state; | |
624 | netif_receive_skb(skb); | |
625 | ||
626 | dev->stats.rx_packets++; | |
627 | dev->stats.rx_bytes += cf->can_dlc; | |
628 | ||
629 | return 1; | |
630 | } | |
631 | ||
632 | static void flexcan_read_fifo(const struct net_device *dev, | |
633 | struct can_frame *cf) | |
634 | { | |
635 | const struct flexcan_priv *priv = netdev_priv(dev); | |
636 | struct flexcan_regs __iomem *regs = priv->base; | |
637 | struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; | |
638 | u32 reg_ctrl, reg_id; | |
639 | ||
61e271ee | 640 | reg_ctrl = flexcan_read(&mb->can_ctrl); |
641 | reg_id = flexcan_read(&mb->can_id); | |
e955cead MKB |
642 | if (reg_ctrl & FLEXCAN_MB_CNT_IDE) |
643 | cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
644 | else | |
645 | cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; | |
646 | ||
647 | if (reg_ctrl & FLEXCAN_MB_CNT_RTR) | |
648 | cf->can_id |= CAN_RTR_FLAG; | |
649 | cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); | |
650 | ||
61e271ee | 651 | *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); |
652 | *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); | |
e955cead MKB |
653 | |
654 | /* mark as read */ | |
61e271ee | 655 | flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); |
656 | flexcan_read(®s->timer); | |
e955cead MKB |
657 | } |
658 | ||
659 | static int flexcan_read_frame(struct net_device *dev) | |
660 | { | |
661 | struct net_device_stats *stats = &dev->stats; | |
662 | struct can_frame *cf; | |
663 | struct sk_buff *skb; | |
664 | ||
665 | skb = alloc_can_skb(dev, &cf); | |
666 | if (unlikely(!skb)) { | |
667 | stats->rx_dropped++; | |
668 | return 0; | |
669 | } | |
670 | ||
671 | flexcan_read_fifo(dev, cf); | |
672 | netif_receive_skb(skb); | |
673 | ||
674 | stats->rx_packets++; | |
675 | stats->rx_bytes += cf->can_dlc; | |
676 | ||
adccadb9 FB |
677 | can_led_event(dev, CAN_LED_EVENT_RX); |
678 | ||
e955cead MKB |
679 | return 1; |
680 | } | |
681 | ||
682 | static int flexcan_poll(struct napi_struct *napi, int quota) | |
683 | { | |
684 | struct net_device *dev = napi->dev; | |
685 | const struct flexcan_priv *priv = netdev_priv(dev); | |
686 | struct flexcan_regs __iomem *regs = priv->base; | |
687 | u32 reg_iflag1, reg_esr; | |
688 | int work_done = 0; | |
689 | ||
690 | /* | |
691 | * The error bits are cleared on read, | |
692 | * use saved value from irq handler. | |
693 | */ | |
61e271ee | 694 | reg_esr = flexcan_read(®s->esr) | priv->reg_esr; |
e955cead MKB |
695 | |
696 | /* handle state changes */ | |
697 | work_done += flexcan_poll_state(dev, reg_esr); | |
698 | ||
699 | /* handle RX-FIFO */ | |
61e271ee | 700 | reg_iflag1 = flexcan_read(®s->iflag1); |
e955cead MKB |
701 | while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && |
702 | work_done < quota) { | |
703 | work_done += flexcan_read_frame(dev); | |
61e271ee | 704 | reg_iflag1 = flexcan_read(®s->iflag1); |
e955cead MKB |
705 | } |
706 | ||
707 | /* report bus errors */ | |
708 | if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) | |
709 | work_done += flexcan_poll_bus_err(dev, reg_esr); | |
710 | ||
711 | if (work_done < quota) { | |
712 | napi_complete(napi); | |
713 | /* enable IRQs */ | |
61e271ee | 714 | flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); |
715 | flexcan_write(priv->reg_ctrl_default, ®s->ctrl); | |
e955cead MKB |
716 | } |
717 | ||
718 | return work_done; | |
719 | } | |
720 | ||
721 | static irqreturn_t flexcan_irq(int irq, void *dev_id) | |
722 | { | |
723 | struct net_device *dev = dev_id; | |
724 | struct net_device_stats *stats = &dev->stats; | |
725 | struct flexcan_priv *priv = netdev_priv(dev); | |
726 | struct flexcan_regs __iomem *regs = priv->base; | |
727 | u32 reg_iflag1, reg_esr; | |
728 | ||
61e271ee | 729 | reg_iflag1 = flexcan_read(®s->iflag1); |
730 | reg_esr = flexcan_read(®s->esr); | |
6e9d554f WG |
731 | /* ACK all bus error and state change IRQ sources */ |
732 | if (reg_esr & FLEXCAN_ESR_ALL_INT) | |
733 | flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); | |
e955cead MKB |
734 | |
735 | /* | |
736 | * schedule NAPI in case of: | |
737 | * - rx IRQ | |
738 | * - state change IRQ | |
739 | * - bus error IRQ and bus error reporting is activated | |
740 | */ | |
741 | if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || | |
742 | (reg_esr & FLEXCAN_ESR_ERR_STATE) || | |
743 | flexcan_has_and_handle_berr(priv, reg_esr)) { | |
744 | /* | |
745 | * The error bits are cleared on read, | |
746 | * save them for later use. | |
747 | */ | |
748 | priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; | |
61e271ee | 749 | flexcan_write(FLEXCAN_IFLAG_DEFAULT & |
750 | ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); | |
751 | flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, | |
e955cead MKB |
752 | ®s->ctrl); |
753 | napi_schedule(&priv->napi); | |
754 | } | |
755 | ||
756 | /* FIFO overflow */ | |
757 | if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { | |
61e271ee | 758 | flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); |
e955cead MKB |
759 | dev->stats.rx_over_errors++; |
760 | dev->stats.rx_errors++; | |
761 | } | |
762 | ||
763 | /* transmission complete interrupt */ | |
764 | if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { | |
9a123496 | 765 | stats->tx_bytes += can_get_echo_skb(dev, 0); |
e955cead | 766 | stats->tx_packets++; |
adccadb9 | 767 | can_led_event(dev, CAN_LED_EVENT_TX); |
de594488 MKB |
768 | /* after sending a RTR frame mailbox is in RX mode */ |
769 | flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, | |
770 | ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); | |
61e271ee | 771 | flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); |
e955cead MKB |
772 | netif_wake_queue(dev); |
773 | } | |
774 | ||
775 | return IRQ_HANDLED; | |
776 | } | |
777 | ||
778 | static void flexcan_set_bittiming(struct net_device *dev) | |
779 | { | |
780 | const struct flexcan_priv *priv = netdev_priv(dev); | |
781 | const struct can_bittiming *bt = &priv->can.bittiming; | |
782 | struct flexcan_regs __iomem *regs = priv->base; | |
783 | u32 reg; | |
784 | ||
61e271ee | 785 | reg = flexcan_read(®s->ctrl); |
e955cead MKB |
786 | reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | |
787 | FLEXCAN_CTRL_RJW(0x3) | | |
788 | FLEXCAN_CTRL_PSEG1(0x7) | | |
789 | FLEXCAN_CTRL_PSEG2(0x7) | | |
790 | FLEXCAN_CTRL_PROPSEG(0x7) | | |
791 | FLEXCAN_CTRL_LPB | | |
792 | FLEXCAN_CTRL_SMP | | |
793 | FLEXCAN_CTRL_LOM); | |
794 | ||
795 | reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | | |
796 | FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | | |
797 | FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | | |
798 | FLEXCAN_CTRL_RJW(bt->sjw - 1) | | |
799 | FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); | |
800 | ||
801 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
802 | reg |= FLEXCAN_CTRL_LPB; | |
803 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
804 | reg |= FLEXCAN_CTRL_LOM; | |
805 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | |
806 | reg |= FLEXCAN_CTRL_SMP; | |
807 | ||
aabdfd6a | 808 | netdev_info(dev, "writing ctrl=0x%08x\n", reg); |
61e271ee | 809 | flexcan_write(reg, ®s->ctrl); |
e955cead MKB |
810 | |
811 | /* print chip status */ | |
aabdfd6a WG |
812 | netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, |
813 | flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); | |
e955cead MKB |
814 | } |
815 | ||
816 | /* | |
817 | * flexcan_chip_start | |
818 | * | |
819 | * this functions is entered with clocks enabled | |
820 | * | |
821 | */ | |
822 | static int flexcan_chip_start(struct net_device *dev) | |
823 | { | |
824 | struct flexcan_priv *priv = netdev_priv(dev); | |
825 | struct flexcan_regs __iomem *regs = priv->base; | |
e955cead MKB |
826 | int err; |
827 | u32 reg_mcr, reg_ctrl; | |
fc05b884 | 828 | int i; |
e955cead MKB |
829 | |
830 | /* enable module */ | |
9b00b300 MKB |
831 | err = flexcan_chip_enable(priv); |
832 | if (err) | |
833 | return err; | |
e955cead MKB |
834 | |
835 | /* soft reset */ | |
4b5b8227 MKB |
836 | err = flexcan_chip_softreset(priv); |
837 | if (err) | |
b1aa1c7a | 838 | goto out_chip_disable; |
e955cead MKB |
839 | |
840 | flexcan_set_bittiming(dev); | |
841 | ||
842 | /* | |
843 | * MCR | |
844 | * | |
845 | * enable freeze | |
846 | * enable fifo | |
847 | * halt now | |
848 | * only supervisor access | |
849 | * enable warning int | |
850 | * choose format C | |
9a123496 | 851 | * disable local echo |
e955cead MKB |
852 | * |
853 | */ | |
61e271ee | 854 | reg_mcr = flexcan_read(®s->mcr); |
d5a7b406 | 855 | reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); |
e955cead MKB |
856 | reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | |
857 | FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | | |
d5a7b406 MKB |
858 | FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | |
859 | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); | |
aabdfd6a | 860 | netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); |
61e271ee | 861 | flexcan_write(reg_mcr, ®s->mcr); |
e955cead MKB |
862 | |
863 | /* | |
864 | * CTRL | |
865 | * | |
866 | * disable timer sync feature | |
867 | * | |
868 | * disable auto busoff recovery | |
869 | * transmit lowest buffer first | |
870 | * | |
871 | * enable tx and rx warning interrupt | |
872 | * enable bus off interrupt | |
873 | * (== FLEXCAN_CTRL_ERR_STATE) | |
e955cead | 874 | */ |
61e271ee | 875 | reg_ctrl = flexcan_read(®s->ctrl); |
e955cead MKB |
876 | reg_ctrl &= ~FLEXCAN_CTRL_TSYN; |
877 | reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | | |
4f72e5f0 WG |
878 | FLEXCAN_CTRL_ERR_STATE; |
879 | /* | |
880 | * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), | |
881 | * on most Flexcan cores, too. Otherwise we don't get | |
882 | * any error warning or passive interrupts. | |
883 | */ | |
884 | if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || | |
885 | priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) | |
886 | reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; | |
bc03a541 AS |
887 | else |
888 | reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; | |
e955cead MKB |
889 | |
890 | /* save for later use */ | |
891 | priv->reg_ctrl_default = reg_ctrl; | |
aabdfd6a | 892 | netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); |
61e271ee | 893 | flexcan_write(reg_ctrl, ®s->ctrl); |
e955cead | 894 | |
fc05b884 DJ |
895 | /* clear and invalidate all mailboxes first */ |
896 | for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) { | |
897 | flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE, | |
898 | ®s->cantxfg[i].can_ctrl); | |
899 | } | |
900 | ||
25e92445 DJ |
901 | /* Errata ERR005829: mark first TX mailbox as INACTIVE */ |
902 | flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, | |
903 | ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); | |
904 | ||
c32fe4ad MKB |
905 | /* mark TX mailbox as INACTIVE */ |
906 | flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, | |
d5a7b406 MKB |
907 | ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); |
908 | ||
e955cead | 909 | /* acceptance mask/acceptance code (accept everything) */ |
61e271ee | 910 | flexcan_write(0x0, ®s->rxgmask); |
911 | flexcan_write(0x0, ®s->rx14mask); | |
912 | flexcan_write(0x0, ®s->rx15mask); | |
e955cead | 913 | |
4f72e5f0 | 914 | if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) |
30c1e672 HW |
915 | flexcan_write(0x0, ®s->rxfgmask); |
916 | ||
f003698e MKB |
917 | err = flexcan_transceiver_enable(priv); |
918 | if (err) | |
b1aa1c7a | 919 | goto out_chip_disable; |
e955cead MKB |
920 | |
921 | /* synchronize with the can bus */ | |
b1aa1c7a MKB |
922 | err = flexcan_chip_unfreeze(priv); |
923 | if (err) | |
924 | goto out_transceiver_disable; | |
e955cead MKB |
925 | |
926 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
927 | ||
928 | /* enable FIFO interrupts */ | |
61e271ee | 929 | flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); |
e955cead MKB |
930 | |
931 | /* print chip status */ | |
aabdfd6a WG |
932 | netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, |
933 | flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); | |
e955cead MKB |
934 | |
935 | return 0; | |
936 | ||
b1aa1c7a MKB |
937 | out_transceiver_disable: |
938 | flexcan_transceiver_disable(priv); | |
939 | out_chip_disable: | |
e955cead MKB |
940 | flexcan_chip_disable(priv); |
941 | return err; | |
942 | } | |
943 | ||
944 | /* | |
945 | * flexcan_chip_stop | |
946 | * | |
947 | * this functions is entered with clocks enabled | |
948 | * | |
949 | */ | |
950 | static void flexcan_chip_stop(struct net_device *dev) | |
951 | { | |
952 | struct flexcan_priv *priv = netdev_priv(dev); | |
953 | struct flexcan_regs __iomem *regs = priv->base; | |
e955cead | 954 | |
b1aa1c7a MKB |
955 | /* freeze + disable module */ |
956 | flexcan_chip_freeze(priv); | |
957 | flexcan_chip_disable(priv); | |
e955cead | 958 | |
5be93bdd MKB |
959 | /* Disable all interrupts */ |
960 | flexcan_write(0, ®s->imask1); | |
961 | flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, | |
962 | ®s->ctrl); | |
963 | ||
f003698e | 964 | flexcan_transceiver_disable(priv); |
e955cead MKB |
965 | priv->can.state = CAN_STATE_STOPPED; |
966 | ||
967 | return; | |
968 | } | |
969 | ||
970 | static int flexcan_open(struct net_device *dev) | |
971 | { | |
972 | struct flexcan_priv *priv = netdev_priv(dev); | |
973 | int err; | |
974 | ||
aa10181b FE |
975 | err = clk_prepare_enable(priv->clk_ipg); |
976 | if (err) | |
977 | return err; | |
978 | ||
979 | err = clk_prepare_enable(priv->clk_per); | |
980 | if (err) | |
981 | goto out_disable_ipg; | |
e955cead MKB |
982 | |
983 | err = open_candev(dev); | |
984 | if (err) | |
aa10181b | 985 | goto out_disable_per; |
e955cead MKB |
986 | |
987 | err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); | |
988 | if (err) | |
989 | goto out_close; | |
990 | ||
991 | /* start chip and queuing */ | |
992 | err = flexcan_chip_start(dev); | |
993 | if (err) | |
7e9e148a | 994 | goto out_free_irq; |
adccadb9 FB |
995 | |
996 | can_led_event(dev, CAN_LED_EVENT_OPEN); | |
997 | ||
e955cead MKB |
998 | napi_enable(&priv->napi); |
999 | netif_start_queue(dev); | |
1000 | ||
1001 | return 0; | |
1002 | ||
7e9e148a MKB |
1003 | out_free_irq: |
1004 | free_irq(dev->irq, dev); | |
e955cead MKB |
1005 | out_close: |
1006 | close_candev(dev); | |
aa10181b | 1007 | out_disable_per: |
3d42a379 | 1008 | clk_disable_unprepare(priv->clk_per); |
aa10181b | 1009 | out_disable_ipg: |
3d42a379 | 1010 | clk_disable_unprepare(priv->clk_ipg); |
e955cead MKB |
1011 | |
1012 | return err; | |
1013 | } | |
1014 | ||
1015 | static int flexcan_close(struct net_device *dev) | |
1016 | { | |
1017 | struct flexcan_priv *priv = netdev_priv(dev); | |
1018 | ||
1019 | netif_stop_queue(dev); | |
1020 | napi_disable(&priv->napi); | |
1021 | flexcan_chip_stop(dev); | |
1022 | ||
1023 | free_irq(dev->irq, dev); | |
3d42a379 ST |
1024 | clk_disable_unprepare(priv->clk_per); |
1025 | clk_disable_unprepare(priv->clk_ipg); | |
e955cead MKB |
1026 | |
1027 | close_candev(dev); | |
1028 | ||
adccadb9 FB |
1029 | can_led_event(dev, CAN_LED_EVENT_STOP); |
1030 | ||
e955cead MKB |
1031 | return 0; |
1032 | } | |
1033 | ||
1034 | static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) | |
1035 | { | |
1036 | int err; | |
1037 | ||
1038 | switch (mode) { | |
1039 | case CAN_MODE_START: | |
1040 | err = flexcan_chip_start(dev); | |
1041 | if (err) | |
1042 | return err; | |
1043 | ||
1044 | netif_wake_queue(dev); | |
1045 | break; | |
1046 | ||
1047 | default: | |
1048 | return -EOPNOTSUPP; | |
1049 | } | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | static const struct net_device_ops flexcan_netdev_ops = { | |
1055 | .ndo_open = flexcan_open, | |
1056 | .ndo_stop = flexcan_close, | |
1057 | .ndo_start_xmit = flexcan_start_xmit, | |
c971fa2a | 1058 | .ndo_change_mtu = can_change_mtu, |
e955cead MKB |
1059 | }; |
1060 | ||
3c8ac0f2 | 1061 | static int register_flexcandev(struct net_device *dev) |
e955cead MKB |
1062 | { |
1063 | struct flexcan_priv *priv = netdev_priv(dev); | |
1064 | struct flexcan_regs __iomem *regs = priv->base; | |
1065 | u32 reg, err; | |
1066 | ||
aa10181b FE |
1067 | err = clk_prepare_enable(priv->clk_ipg); |
1068 | if (err) | |
1069 | return err; | |
1070 | ||
1071 | err = clk_prepare_enable(priv->clk_per); | |
1072 | if (err) | |
1073 | goto out_disable_ipg; | |
e955cead MKB |
1074 | |
1075 | /* select "bus clock", chip must be disabled */ | |
9b00b300 MKB |
1076 | err = flexcan_chip_disable(priv); |
1077 | if (err) | |
1078 | goto out_disable_per; | |
61e271ee | 1079 | reg = flexcan_read(®s->ctrl); |
e955cead | 1080 | reg |= FLEXCAN_CTRL_CLK_SRC; |
61e271ee | 1081 | flexcan_write(reg, ®s->ctrl); |
e955cead | 1082 | |
9b00b300 MKB |
1083 | err = flexcan_chip_enable(priv); |
1084 | if (err) | |
1085 | goto out_chip_disable; | |
e955cead MKB |
1086 | |
1087 | /* set freeze, halt and activate FIFO, restrict register access */ | |
61e271ee | 1088 | reg = flexcan_read(®s->mcr); |
e955cead MKB |
1089 | reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | |
1090 | FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; | |
61e271ee | 1091 | flexcan_write(reg, ®s->mcr); |
e955cead MKB |
1092 | |
1093 | /* | |
1094 | * Currently we only support newer versions of this core | |
1095 | * featuring a RX FIFO. Older cores found on some Coldfire | |
1096 | * derivates are not yet supported. | |
1097 | */ | |
61e271ee | 1098 | reg = flexcan_read(®s->mcr); |
e955cead | 1099 | if (!(reg & FLEXCAN_MCR_FEN)) { |
aabdfd6a | 1100 | netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); |
e955cead | 1101 | err = -ENODEV; |
9b00b300 | 1102 | goto out_chip_disable; |
e955cead MKB |
1103 | } |
1104 | ||
1105 | err = register_candev(dev); | |
1106 | ||
e955cead | 1107 | /* disable core and turn off clocks */ |
9b00b300 | 1108 | out_chip_disable: |
e955cead | 1109 | flexcan_chip_disable(priv); |
9b00b300 | 1110 | out_disable_per: |
3d42a379 | 1111 | clk_disable_unprepare(priv->clk_per); |
aa10181b | 1112 | out_disable_ipg: |
3d42a379 | 1113 | clk_disable_unprepare(priv->clk_ipg); |
e955cead MKB |
1114 | |
1115 | return err; | |
1116 | } | |
1117 | ||
3c8ac0f2 | 1118 | static void unregister_flexcandev(struct net_device *dev) |
e955cead MKB |
1119 | { |
1120 | unregister_candev(dev); | |
1121 | } | |
1122 | ||
30c1e672 | 1123 | static const struct of_device_id flexcan_of_match[] = { |
30c1e672 | 1124 | { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, |
e3587842 MKB |
1125 | { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, |
1126 | { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, | |
30c1e672 HW |
1127 | { /* sentinel */ }, |
1128 | }; | |
4358a9dc | 1129 | MODULE_DEVICE_TABLE(of, flexcan_of_match); |
30c1e672 HW |
1130 | |
1131 | static const struct platform_device_id flexcan_id_table[] = { | |
1132 | { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, | |
1133 | { /* sentinel */ }, | |
1134 | }; | |
4358a9dc | 1135 | MODULE_DEVICE_TABLE(platform, flexcan_id_table); |
30c1e672 | 1136 | |
3c8ac0f2 | 1137 | static int flexcan_probe(struct platform_device *pdev) |
e955cead | 1138 | { |
30c1e672 | 1139 | const struct of_device_id *of_id; |
dda0b3bd | 1140 | const struct flexcan_devtype_data *devtype_data; |
e955cead MKB |
1141 | struct net_device *dev; |
1142 | struct flexcan_priv *priv; | |
1143 | struct resource *mem; | |
3d42a379 | 1144 | struct clk *clk_ipg = NULL, *clk_per = NULL; |
e955cead | 1145 | void __iomem *base; |
e955cead | 1146 | int err, irq; |
97efe9ae | 1147 | u32 clock_freq = 0; |
1148 | ||
afc016d8 HW |
1149 | if (pdev->dev.of_node) |
1150 | of_property_read_u32(pdev->dev.of_node, | |
1151 | "clock-frequency", &clock_freq); | |
97efe9ae | 1152 | |
1153 | if (!clock_freq) { | |
3d42a379 ST |
1154 | clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1155 | if (IS_ERR(clk_ipg)) { | |
1156 | dev_err(&pdev->dev, "no ipg clock defined\n"); | |
933e4af4 | 1157 | return PTR_ERR(clk_ipg); |
3d42a379 | 1158 | } |
3d42a379 ST |
1159 | |
1160 | clk_per = devm_clk_get(&pdev->dev, "per"); | |
1161 | if (IS_ERR(clk_per)) { | |
1162 | dev_err(&pdev->dev, "no per clock defined\n"); | |
933e4af4 | 1163 | return PTR_ERR(clk_per); |
97efe9ae | 1164 | } |
1a3e5173 | 1165 | clock_freq = clk_get_rate(clk_per); |
e955cead MKB |
1166 | } |
1167 | ||
1168 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1169 | irq = platform_get_irq(pdev, 0); | |
933e4af4 FE |
1170 | if (irq <= 0) |
1171 | return -ENODEV; | |
e955cead | 1172 | |
933e4af4 FE |
1173 | base = devm_ioremap_resource(&pdev->dev, mem); |
1174 | if (IS_ERR(base)) | |
1175 | return PTR_ERR(base); | |
e955cead | 1176 | |
30c1e672 HW |
1177 | of_id = of_match_device(flexcan_of_match, &pdev->dev); |
1178 | if (of_id) { | |
1179 | devtype_data = of_id->data; | |
d0873e6f | 1180 | } else if (platform_get_device_id(pdev)->driver_data) { |
30c1e672 | 1181 | devtype_data = (struct flexcan_devtype_data *) |
d0873e6f | 1182 | platform_get_device_id(pdev)->driver_data; |
30c1e672 | 1183 | } else { |
933e4af4 | 1184 | return -ENODEV; |
30c1e672 HW |
1185 | } |
1186 | ||
933e4af4 FE |
1187 | dev = alloc_candev(sizeof(struct flexcan_priv), 1); |
1188 | if (!dev) | |
1189 | return -ENOMEM; | |
1190 | ||
e955cead MKB |
1191 | dev->netdev_ops = &flexcan_netdev_ops; |
1192 | dev->irq = irq; | |
9a123496 | 1193 | dev->flags |= IFF_ECHO; |
e955cead MKB |
1194 | |
1195 | priv = netdev_priv(dev); | |
97efe9ae | 1196 | priv->can.clock.freq = clock_freq; |
e955cead MKB |
1197 | priv->can.bittiming_const = &flexcan_bittiming_const; |
1198 | priv->can.do_set_mode = flexcan_set_mode; | |
1199 | priv->can.do_get_berr_counter = flexcan_get_berr_counter; | |
1200 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | | |
1201 | CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | | |
1202 | CAN_CTRLMODE_BERR_REPORTING; | |
1203 | priv->base = base; | |
1204 | priv->dev = dev; | |
3d42a379 ST |
1205 | priv->clk_ipg = clk_ipg; |
1206 | priv->clk_per = clk_per; | |
84ae6643 | 1207 | priv->pdata = dev_get_platdata(&pdev->dev); |
30c1e672 | 1208 | priv->devtype_data = devtype_data; |
e955cead | 1209 | |
b7c4114b FE |
1210 | priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); |
1211 | if (IS_ERR(priv->reg_xceiver)) | |
1212 | priv->reg_xceiver = NULL; | |
1213 | ||
e955cead MKB |
1214 | netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); |
1215 | ||
d75ea942 | 1216 | platform_set_drvdata(pdev, dev); |
e955cead MKB |
1217 | SET_NETDEV_DEV(dev, &pdev->dev); |
1218 | ||
1219 | err = register_flexcandev(dev); | |
1220 | if (err) { | |
1221 | dev_err(&pdev->dev, "registering netdev failed\n"); | |
1222 | goto failed_register; | |
1223 | } | |
1224 | ||
adccadb9 FB |
1225 | devm_can_led_init(dev); |
1226 | ||
e955cead MKB |
1227 | dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", |
1228 | priv->base, dev->irq); | |
1229 | ||
1230 | return 0; | |
1231 | ||
1232 | failed_register: | |
1233 | free_candev(dev); | |
e955cead MKB |
1234 | return err; |
1235 | } | |
1236 | ||
3c8ac0f2 | 1237 | static int flexcan_remove(struct platform_device *pdev) |
e955cead MKB |
1238 | { |
1239 | struct net_device *dev = platform_get_drvdata(pdev); | |
d96e43e8 | 1240 | struct flexcan_priv *priv = netdev_priv(dev); |
e955cead MKB |
1241 | |
1242 | unregister_flexcandev(dev); | |
d96e43e8 | 1243 | netif_napi_del(&priv->napi); |
9a27586d MKB |
1244 | free_candev(dev); |
1245 | ||
e955cead MKB |
1246 | return 0; |
1247 | } | |
1248 | ||
08c6d351 | 1249 | static int __maybe_unused flexcan_suspend(struct device *device) |
8b5e218d | 1250 | { |
588e7a8e | 1251 | struct net_device *dev = dev_get_drvdata(device); |
8b5e218d | 1252 | struct flexcan_priv *priv = netdev_priv(dev); |
9b00b300 | 1253 | int err; |
8b5e218d | 1254 | |
9b00b300 MKB |
1255 | err = flexcan_chip_disable(priv); |
1256 | if (err) | |
1257 | return err; | |
8b5e218d EB |
1258 | |
1259 | if (netif_running(dev)) { | |
1260 | netif_stop_queue(dev); | |
1261 | netif_device_detach(dev); | |
1262 | } | |
1263 | priv->can.state = CAN_STATE_SLEEPING; | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
08c6d351 | 1268 | static int __maybe_unused flexcan_resume(struct device *device) |
8b5e218d | 1269 | { |
588e7a8e | 1270 | struct net_device *dev = dev_get_drvdata(device); |
8b5e218d EB |
1271 | struct flexcan_priv *priv = netdev_priv(dev); |
1272 | ||
1273 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1274 | if (netif_running(dev)) { | |
1275 | netif_device_attach(dev); | |
1276 | netif_start_queue(dev); | |
1277 | } | |
9b00b300 | 1278 | return flexcan_chip_enable(priv); |
8b5e218d | 1279 | } |
588e7a8e FE |
1280 | |
1281 | static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); | |
8b5e218d | 1282 | |
e955cead | 1283 | static struct platform_driver flexcan_driver = { |
c8aef4cb | 1284 | .driver = { |
1285 | .name = DRV_NAME, | |
1286 | .owner = THIS_MODULE, | |
588e7a8e | 1287 | .pm = &flexcan_pm_ops, |
c8aef4cb | 1288 | .of_match_table = flexcan_of_match, |
1289 | }, | |
e955cead | 1290 | .probe = flexcan_probe, |
3c8ac0f2 | 1291 | .remove = flexcan_remove, |
30c1e672 | 1292 | .id_table = flexcan_id_table, |
e955cead MKB |
1293 | }; |
1294 | ||
871d3372 | 1295 | module_platform_driver(flexcan_driver); |
e955cead MKB |
1296 | |
1297 | MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " | |
1298 | "Marc Kleine-Budde <kernel@pengutronix.de>"); | |
1299 | MODULE_LICENSE("GPL v2"); | |
1300 | MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); |