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e0d1f481 DA |
1 | /* |
2 | * CAN bus driver for Bosch M_CAN controller | |
3 | * | |
4 | * Copyright (C) 2014 Freescale Semiconductor, Inc. | |
5 | * Dong Aisheng <b29396@freescale.com> | |
6 | * | |
7 | * Bosch M_CAN user manual can be obtained from: | |
8 | * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/ | |
9 | * mcan_users_manual_v302.pdf | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_device.h> | |
25 | #include <linux/platform_device.h> | |
26 | ||
27 | #include <linux/can/dev.h> | |
28 | ||
29 | /* napi related */ | |
30 | #define M_CAN_NAPI_WEIGHT 64 | |
31 | ||
32 | /* message ram configuration data length */ | |
33 | #define MRAM_CFG_LEN 8 | |
34 | ||
35 | /* registers definition */ | |
36 | enum m_can_reg { | |
37 | M_CAN_CREL = 0x0, | |
38 | M_CAN_ENDN = 0x4, | |
39 | M_CAN_CUST = 0x8, | |
40 | M_CAN_FBTP = 0xc, | |
41 | M_CAN_TEST = 0x10, | |
42 | M_CAN_RWD = 0x14, | |
43 | M_CAN_CCCR = 0x18, | |
44 | M_CAN_BTP = 0x1c, | |
45 | M_CAN_TSCC = 0x20, | |
46 | M_CAN_TSCV = 0x24, | |
47 | M_CAN_TOCC = 0x28, | |
48 | M_CAN_TOCV = 0x2c, | |
49 | M_CAN_ECR = 0x40, | |
50 | M_CAN_PSR = 0x44, | |
51 | M_CAN_IR = 0x50, | |
52 | M_CAN_IE = 0x54, | |
53 | M_CAN_ILS = 0x58, | |
54 | M_CAN_ILE = 0x5c, | |
55 | M_CAN_GFC = 0x80, | |
56 | M_CAN_SIDFC = 0x84, | |
57 | M_CAN_XIDFC = 0x88, | |
58 | M_CAN_XIDAM = 0x90, | |
59 | M_CAN_HPMS = 0x94, | |
60 | M_CAN_NDAT1 = 0x98, | |
61 | M_CAN_NDAT2 = 0x9c, | |
62 | M_CAN_RXF0C = 0xa0, | |
63 | M_CAN_RXF0S = 0xa4, | |
64 | M_CAN_RXF0A = 0xa8, | |
65 | M_CAN_RXBC = 0xac, | |
66 | M_CAN_RXF1C = 0xb0, | |
67 | M_CAN_RXF1S = 0xb4, | |
68 | M_CAN_RXF1A = 0xb8, | |
69 | M_CAN_RXESC = 0xbc, | |
70 | M_CAN_TXBC = 0xc0, | |
71 | M_CAN_TXFQS = 0xc4, | |
72 | M_CAN_TXESC = 0xc8, | |
73 | M_CAN_TXBRP = 0xcc, | |
74 | M_CAN_TXBAR = 0xd0, | |
75 | M_CAN_TXBCR = 0xd4, | |
76 | M_CAN_TXBTO = 0xd8, | |
77 | M_CAN_TXBCF = 0xdc, | |
78 | M_CAN_TXBTIE = 0xe0, | |
79 | M_CAN_TXBCIE = 0xe4, | |
80 | M_CAN_TXEFC = 0xf0, | |
81 | M_CAN_TXEFS = 0xf4, | |
82 | M_CAN_TXEFA = 0xf8, | |
83 | }; | |
84 | ||
85 | /* m_can lec values */ | |
86 | enum m_can_lec_type { | |
87 | LEC_NO_ERROR = 0, | |
88 | LEC_STUFF_ERROR, | |
89 | LEC_FORM_ERROR, | |
90 | LEC_ACK_ERROR, | |
91 | LEC_BIT1_ERROR, | |
92 | LEC_BIT0_ERROR, | |
93 | LEC_CRC_ERROR, | |
94 | LEC_UNUSED, | |
95 | }; | |
96 | ||
97 | enum m_can_mram_cfg { | |
98 | MRAM_SIDF = 0, | |
99 | MRAM_XIDF, | |
100 | MRAM_RXF0, | |
101 | MRAM_RXF1, | |
102 | MRAM_RXB, | |
103 | MRAM_TXE, | |
104 | MRAM_TXB, | |
105 | MRAM_CFG_NUM, | |
106 | }; | |
107 | ||
80646733 DA |
108 | /* Fast Bit Timing & Prescaler Register (FBTP) */ |
109 | #define FBTR_FBRP_MASK 0x1f | |
110 | #define FBTR_FBRP_SHIFT 16 | |
111 | #define FBTR_FTSEG1_SHIFT 8 | |
112 | #define FBTR_FTSEG1_MASK (0xf << FBTR_FTSEG1_SHIFT) | |
113 | #define FBTR_FTSEG2_SHIFT 4 | |
114 | #define FBTR_FTSEG2_MASK (0x7 << FBTR_FTSEG2_SHIFT) | |
115 | #define FBTR_FSJW_SHIFT 0 | |
116 | #define FBTR_FSJW_MASK 0x3 | |
117 | ||
e0d1f481 DA |
118 | /* Test Register (TEST) */ |
119 | #define TEST_LBCK BIT(4) | |
120 | ||
121 | /* CC Control Register(CCCR) */ | |
80646733 DA |
122 | #define CCCR_TEST BIT(7) |
123 | #define CCCR_CMR_MASK 0x3 | |
124 | #define CCCR_CMR_SHIFT 10 | |
125 | #define CCCR_CMR_CANFD 0x1 | |
126 | #define CCCR_CMR_CANFD_BRS 0x2 | |
127 | #define CCCR_CMR_CAN 0x3 | |
128 | #define CCCR_CME_MASK 0x3 | |
129 | #define CCCR_CME_SHIFT 8 | |
130 | #define CCCR_CME_CAN 0 | |
131 | #define CCCR_CME_CANFD 0x1 | |
132 | #define CCCR_CME_CANFD_BRS 0x2 | |
133 | #define CCCR_TEST BIT(7) | |
134 | #define CCCR_MON BIT(5) | |
135 | #define CCCR_CCE BIT(1) | |
136 | #define CCCR_INIT BIT(0) | |
137 | #define CCCR_CANFD 0x10 | |
e0d1f481 DA |
138 | |
139 | /* Bit Timing & Prescaler Register (BTP) */ | |
140 | #define BTR_BRP_MASK 0x3ff | |
141 | #define BTR_BRP_SHIFT 16 | |
142 | #define BTR_TSEG1_SHIFT 8 | |
143 | #define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT) | |
144 | #define BTR_TSEG2_SHIFT 4 | |
145 | #define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT) | |
146 | #define BTR_SJW_SHIFT 0 | |
147 | #define BTR_SJW_MASK 0xf | |
148 | ||
149 | /* Error Counter Register(ECR) */ | |
150 | #define ECR_RP BIT(15) | |
151 | #define ECR_REC_SHIFT 8 | |
152 | #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) | |
153 | #define ECR_TEC_SHIFT 0 | |
154 | #define ECR_TEC_MASK 0xff | |
155 | ||
156 | /* Protocol Status Register(PSR) */ | |
157 | #define PSR_BO BIT(7) | |
158 | #define PSR_EW BIT(6) | |
159 | #define PSR_EP BIT(5) | |
160 | #define PSR_LEC_MASK 0x7 | |
161 | ||
162 | /* Interrupt Register(IR) */ | |
163 | #define IR_ALL_INT 0xffffffff | |
164 | #define IR_STE BIT(31) | |
165 | #define IR_FOE BIT(30) | |
166 | #define IR_ACKE BIT(29) | |
167 | #define IR_BE BIT(28) | |
168 | #define IR_CRCE BIT(27) | |
169 | #define IR_WDI BIT(26) | |
170 | #define IR_BO BIT(25) | |
171 | #define IR_EW BIT(24) | |
172 | #define IR_EP BIT(23) | |
173 | #define IR_ELO BIT(22) | |
174 | #define IR_BEU BIT(21) | |
175 | #define IR_BEC BIT(20) | |
176 | #define IR_DRX BIT(19) | |
177 | #define IR_TOO BIT(18) | |
178 | #define IR_MRAF BIT(17) | |
179 | #define IR_TSW BIT(16) | |
180 | #define IR_TEFL BIT(15) | |
181 | #define IR_TEFF BIT(14) | |
182 | #define IR_TEFW BIT(13) | |
183 | #define IR_TEFN BIT(12) | |
184 | #define IR_TFE BIT(11) | |
185 | #define IR_TCF BIT(10) | |
186 | #define IR_TC BIT(9) | |
187 | #define IR_HPM BIT(8) | |
188 | #define IR_RF1L BIT(7) | |
189 | #define IR_RF1F BIT(6) | |
190 | #define IR_RF1W BIT(5) | |
191 | #define IR_RF1N BIT(4) | |
192 | #define IR_RF0L BIT(3) | |
193 | #define IR_RF0F BIT(2) | |
194 | #define IR_RF0W BIT(1) | |
195 | #define IR_RF0N BIT(0) | |
196 | #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) | |
197 | #define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) | |
198 | #define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \ | |
199 | IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ | |
200 | IR_RF1L | IR_RF0L) | |
201 | #define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS) | |
202 | ||
203 | /* Interrupt Line Select (ILS) */ | |
204 | #define ILS_ALL_INT0 0x0 | |
205 | #define ILS_ALL_INT1 0xFFFFFFFF | |
206 | ||
207 | /* Interrupt Line Enable (ILE) */ | |
208 | #define ILE_EINT0 BIT(0) | |
209 | #define ILE_EINT1 BIT(1) | |
210 | ||
211 | /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ | |
212 | #define RXFC_FWM_OFF 24 | |
213 | #define RXFC_FWM_MASK 0x7f | |
214 | #define RXFC_FWM_1 (1 << RXFC_FWM_OFF) | |
215 | #define RXFC_FS_OFF 16 | |
216 | #define RXFC_FS_MASK 0x7f | |
217 | ||
218 | /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ | |
219 | #define RXFS_RFL BIT(25) | |
220 | #define RXFS_FF BIT(24) | |
221 | #define RXFS_FPI_OFF 16 | |
222 | #define RXFS_FPI_MASK 0x3f0000 | |
223 | #define RXFS_FGI_OFF 8 | |
224 | #define RXFS_FGI_MASK 0x3f00 | |
225 | #define RXFS_FFL_MASK 0x7f | |
226 | ||
227 | /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ | |
228 | #define M_CAN_RXESC_8BYTES 0x0 | |
80646733 | 229 | #define M_CAN_RXESC_64BYTES 0x777 |
e0d1f481 DA |
230 | |
231 | /* Tx Buffer Configuration(TXBC) */ | |
232 | #define TXBC_NDTB_OFF 16 | |
233 | #define TXBC_NDTB_MASK 0x3f | |
234 | ||
235 | /* Tx Buffer Element Size Configuration(TXESC) */ | |
236 | #define TXESC_TBDS_8BYTES 0x0 | |
80646733 | 237 | #define TXESC_TBDS_64BYTES 0x7 |
e0d1f481 DA |
238 | |
239 | /* Tx Event FIFO Con.guration (TXEFC) */ | |
240 | #define TXEFC_EFS_OFF 16 | |
241 | #define TXEFC_EFS_MASK 0x3f | |
242 | ||
243 | /* Message RAM Configuration (in bytes) */ | |
244 | #define SIDF_ELEMENT_SIZE 4 | |
245 | #define XIDF_ELEMENT_SIZE 8 | |
80646733 DA |
246 | #define RXF0_ELEMENT_SIZE 72 |
247 | #define RXF1_ELEMENT_SIZE 72 | |
e0d1f481 DA |
248 | #define RXB_ELEMENT_SIZE 16 |
249 | #define TXE_ELEMENT_SIZE 8 | |
80646733 | 250 | #define TXB_ELEMENT_SIZE 72 |
e0d1f481 DA |
251 | |
252 | /* Message RAM Elements */ | |
253 | #define M_CAN_FIFO_ID 0x0 | |
254 | #define M_CAN_FIFO_DLC 0x4 | |
255 | #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) | |
256 | ||
257 | /* Rx Buffer Element */ | |
80646733 | 258 | /* R0 */ |
e0d1f481 DA |
259 | #define RX_BUF_ESI BIT(31) |
260 | #define RX_BUF_XTD BIT(30) | |
261 | #define RX_BUF_RTR BIT(29) | |
80646733 DA |
262 | /* R1 */ |
263 | #define RX_BUF_ANMF BIT(31) | |
264 | #define RX_BUF_EDL BIT(21) | |
265 | #define RX_BUF_BRS BIT(20) | |
e0d1f481 DA |
266 | |
267 | /* Tx Buffer Element */ | |
80646733 | 268 | /* R0 */ |
e0d1f481 DA |
269 | #define TX_BUF_XTD BIT(30) |
270 | #define TX_BUF_RTR BIT(29) | |
271 | ||
272 | /* address offset and element number for each FIFO/Buffer in the Message RAM */ | |
273 | struct mram_cfg { | |
274 | u16 off; | |
275 | u8 num; | |
276 | }; | |
277 | ||
278 | /* m_can private data structure */ | |
279 | struct m_can_priv { | |
280 | struct can_priv can; /* must be the first member */ | |
281 | struct napi_struct napi; | |
282 | struct net_device *dev; | |
283 | struct device *device; | |
284 | struct clk *hclk; | |
285 | struct clk *cclk; | |
286 | void __iomem *base; | |
287 | u32 irqstatus; | |
288 | ||
289 | /* message ram configuration */ | |
290 | void __iomem *mram_base; | |
291 | struct mram_cfg mcfg[MRAM_CFG_NUM]; | |
292 | }; | |
293 | ||
294 | static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg) | |
295 | { | |
296 | return readl(priv->base + reg); | |
297 | } | |
298 | ||
299 | static inline void m_can_write(const struct m_can_priv *priv, | |
300 | enum m_can_reg reg, u32 val) | |
301 | { | |
302 | writel(val, priv->base + reg); | |
303 | } | |
304 | ||
305 | static inline u32 m_can_fifo_read(const struct m_can_priv *priv, | |
306 | u32 fgi, unsigned int offset) | |
307 | { | |
308 | return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off + | |
309 | fgi * RXF0_ELEMENT_SIZE + offset); | |
310 | } | |
311 | ||
312 | static inline void m_can_fifo_write(const struct m_can_priv *priv, | |
313 | u32 fpi, unsigned int offset, u32 val) | |
314 | { | |
fba6f911 MKB |
315 | writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off + |
316 | fpi * TXB_ELEMENT_SIZE + offset); | |
e0d1f481 DA |
317 | } |
318 | ||
319 | static inline void m_can_config_endisable(const struct m_can_priv *priv, | |
320 | bool enable) | |
321 | { | |
322 | u32 cccr = m_can_read(priv, M_CAN_CCCR); | |
323 | u32 timeout = 10; | |
324 | u32 val = 0; | |
325 | ||
326 | if (enable) { | |
327 | /* enable m_can configuration */ | |
328 | m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); | |
7660f633 | 329 | udelay(5); |
e0d1f481 DA |
330 | /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ |
331 | m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); | |
332 | } else { | |
333 | m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); | |
334 | } | |
335 | ||
336 | /* there's a delay for module initialization */ | |
337 | if (enable) | |
338 | val = CCCR_INIT | CCCR_CCE; | |
339 | ||
340 | while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { | |
341 | if (timeout == 0) { | |
342 | netdev_warn(priv->dev, "Failed to init module\n"); | |
343 | return; | |
344 | } | |
345 | timeout--; | |
346 | udelay(1); | |
347 | } | |
348 | } | |
349 | ||
350 | static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) | |
351 | { | |
352 | m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1); | |
353 | } | |
354 | ||
355 | static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv) | |
356 | { | |
357 | m_can_write(priv, M_CAN_ILE, 0x0); | |
358 | } | |
359 | ||
80646733 | 360 | static void m_can_read_fifo(struct net_device *dev, u32 rxfs) |
e0d1f481 | 361 | { |
80646733 | 362 | struct net_device_stats *stats = &dev->stats; |
e0d1f481 | 363 | struct m_can_priv *priv = netdev_priv(dev); |
80646733 DA |
364 | struct canfd_frame *cf; |
365 | struct sk_buff *skb; | |
921f1681 | 366 | u32 id, fgi, dlc; |
80646733 | 367 | int i; |
e0d1f481 DA |
368 | |
369 | /* calculate the fifo get index for where to read data */ | |
370 | fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF; | |
80646733 DA |
371 | dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC); |
372 | if (dlc & RX_BUF_EDL) | |
373 | skb = alloc_canfd_skb(dev, &cf); | |
374 | else | |
375 | skb = alloc_can_skb(dev, (struct can_frame **)&cf); | |
376 | if (!skb) { | |
377 | stats->rx_dropped++; | |
378 | return; | |
379 | } | |
380 | ||
381 | if (dlc & RX_BUF_EDL) | |
382 | cf->len = can_dlc2len((dlc >> 16) & 0x0F); | |
383 | else | |
384 | cf->len = get_can_dlc((dlc >> 16) & 0x0F); | |
385 | ||
e0d1f481 DA |
386 | id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID); |
387 | if (id & RX_BUF_XTD) | |
388 | cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
389 | else | |
390 | cf->can_id = (id >> 18) & CAN_SFF_MASK; | |
391 | ||
80646733 DA |
392 | if (id & RX_BUF_ESI) { |
393 | cf->flags |= CANFD_ESI; | |
394 | netdev_dbg(dev, "ESI Error\n"); | |
395 | } | |
921f1681 | 396 | |
80646733 | 397 | if (!(dlc & RX_BUF_EDL) && (id & RX_BUF_RTR)) { |
e0d1f481 DA |
398 | cf->can_id |= CAN_RTR_FLAG; |
399 | } else { | |
80646733 DA |
400 | if (dlc & RX_BUF_BRS) |
401 | cf->flags |= CANFD_BRS; | |
402 | ||
403 | for (i = 0; i < cf->len; i += 4) | |
404 | *(u32 *)(cf->data + i) = | |
405 | m_can_fifo_read(priv, fgi, | |
406 | M_CAN_FIFO_DATA(i / 4)); | |
e0d1f481 DA |
407 | } |
408 | ||
409 | /* acknowledge rx fifo 0 */ | |
410 | m_can_write(priv, M_CAN_RXF0A, fgi); | |
80646733 DA |
411 | |
412 | stats->rx_packets++; | |
413 | stats->rx_bytes += cf->len; | |
414 | ||
415 | netif_receive_skb(skb); | |
e0d1f481 DA |
416 | } |
417 | ||
418 | static int m_can_do_rx_poll(struct net_device *dev, int quota) | |
419 | { | |
420 | struct m_can_priv *priv = netdev_priv(dev); | |
e0d1f481 DA |
421 | u32 pkts = 0; |
422 | u32 rxfs; | |
423 | ||
424 | rxfs = m_can_read(priv, M_CAN_RXF0S); | |
425 | if (!(rxfs & RXFS_FFL_MASK)) { | |
426 | netdev_dbg(dev, "no messages in fifo0\n"); | |
427 | return 0; | |
428 | } | |
429 | ||
430 | while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { | |
431 | if (rxfs & RXFS_RFL) | |
432 | netdev_warn(dev, "Rx FIFO 0 Message Lost\n"); | |
433 | ||
80646733 | 434 | m_can_read_fifo(dev, rxfs); |
e0d1f481 DA |
435 | |
436 | quota--; | |
437 | pkts++; | |
438 | rxfs = m_can_read(priv, M_CAN_RXF0S); | |
439 | } | |
440 | ||
441 | if (pkts) | |
442 | can_led_event(dev, CAN_LED_EVENT_RX); | |
443 | ||
444 | return pkts; | |
445 | } | |
446 | ||
447 | static int m_can_handle_lost_msg(struct net_device *dev) | |
448 | { | |
449 | struct net_device_stats *stats = &dev->stats; | |
450 | struct sk_buff *skb; | |
451 | struct can_frame *frame; | |
452 | ||
453 | netdev_err(dev, "msg lost in rxf0\n"); | |
454 | ||
455 | stats->rx_errors++; | |
456 | stats->rx_over_errors++; | |
457 | ||
458 | skb = alloc_can_err_skb(dev, &frame); | |
459 | if (unlikely(!skb)) | |
460 | return 0; | |
461 | ||
462 | frame->can_id |= CAN_ERR_CRTL; | |
463 | frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
464 | ||
465 | netif_receive_skb(skb); | |
466 | ||
467 | return 1; | |
468 | } | |
469 | ||
470 | static int m_can_handle_lec_err(struct net_device *dev, | |
471 | enum m_can_lec_type lec_type) | |
472 | { | |
473 | struct m_can_priv *priv = netdev_priv(dev); | |
474 | struct net_device_stats *stats = &dev->stats; | |
475 | struct can_frame *cf; | |
476 | struct sk_buff *skb; | |
477 | ||
478 | priv->can.can_stats.bus_error++; | |
479 | stats->rx_errors++; | |
480 | ||
481 | /* propagate the error condition to the CAN stack */ | |
482 | skb = alloc_can_err_skb(dev, &cf); | |
483 | if (unlikely(!skb)) | |
484 | return 0; | |
485 | ||
486 | /* check for 'last error code' which tells us the | |
487 | * type of the last error to occur on the CAN bus | |
488 | */ | |
489 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
e0d1f481 DA |
490 | |
491 | switch (lec_type) { | |
492 | case LEC_STUFF_ERROR: | |
493 | netdev_dbg(dev, "stuff error\n"); | |
494 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
495 | break; | |
496 | case LEC_FORM_ERROR: | |
497 | netdev_dbg(dev, "form error\n"); | |
498 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
499 | break; | |
500 | case LEC_ACK_ERROR: | |
501 | netdev_dbg(dev, "ack error\n"); | |
ffd461f8 | 502 | cf->data[3] = CAN_ERR_PROT_LOC_ACK; |
e0d1f481 DA |
503 | break; |
504 | case LEC_BIT1_ERROR: | |
505 | netdev_dbg(dev, "bit1 error\n"); | |
506 | cf->data[2] |= CAN_ERR_PROT_BIT1; | |
507 | break; | |
508 | case LEC_BIT0_ERROR: | |
509 | netdev_dbg(dev, "bit0 error\n"); | |
510 | cf->data[2] |= CAN_ERR_PROT_BIT0; | |
511 | break; | |
512 | case LEC_CRC_ERROR: | |
513 | netdev_dbg(dev, "CRC error\n"); | |
ffd461f8 | 514 | cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; |
e0d1f481 DA |
515 | break; |
516 | default: | |
517 | break; | |
518 | } | |
519 | ||
520 | stats->rx_packets++; | |
521 | stats->rx_bytes += cf->can_dlc; | |
522 | netif_receive_skb(skb); | |
523 | ||
524 | return 1; | |
525 | } | |
526 | ||
f6a99649 DA |
527 | static int __m_can_get_berr_counter(const struct net_device *dev, |
528 | struct can_berr_counter *bec) | |
529 | { | |
530 | struct m_can_priv *priv = netdev_priv(dev); | |
531 | unsigned int ecr; | |
532 | ||
533 | ecr = m_can_read(priv, M_CAN_ECR); | |
534 | bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; | |
535 | bec->txerr = ecr & ECR_TEC_MASK; | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
e0d1f481 DA |
540 | static int m_can_get_berr_counter(const struct net_device *dev, |
541 | struct can_berr_counter *bec) | |
542 | { | |
543 | struct m_can_priv *priv = netdev_priv(dev); | |
e0d1f481 DA |
544 | int err; |
545 | ||
546 | err = clk_prepare_enable(priv->hclk); | |
547 | if (err) | |
548 | return err; | |
549 | ||
550 | err = clk_prepare_enable(priv->cclk); | |
551 | if (err) { | |
552 | clk_disable_unprepare(priv->hclk); | |
553 | return err; | |
554 | } | |
555 | ||
f6a99649 | 556 | __m_can_get_berr_counter(dev, bec); |
e0d1f481 DA |
557 | |
558 | clk_disable_unprepare(priv->cclk); | |
559 | clk_disable_unprepare(priv->hclk); | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static int m_can_handle_state_change(struct net_device *dev, | |
565 | enum can_state new_state) | |
566 | { | |
567 | struct m_can_priv *priv = netdev_priv(dev); | |
568 | struct net_device_stats *stats = &dev->stats; | |
569 | struct can_frame *cf; | |
570 | struct sk_buff *skb; | |
571 | struct can_berr_counter bec; | |
572 | unsigned int ecr; | |
573 | ||
574 | switch (new_state) { | |
575 | case CAN_STATE_ERROR_ACTIVE: | |
576 | /* error warning state */ | |
577 | priv->can.can_stats.error_warning++; | |
578 | priv->can.state = CAN_STATE_ERROR_WARNING; | |
579 | break; | |
580 | case CAN_STATE_ERROR_PASSIVE: | |
581 | /* error passive state */ | |
582 | priv->can.can_stats.error_passive++; | |
583 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
584 | break; | |
585 | case CAN_STATE_BUS_OFF: | |
586 | /* bus-off state */ | |
587 | priv->can.state = CAN_STATE_BUS_OFF; | |
588 | m_can_disable_all_interrupts(priv); | |
be38a6f9 | 589 | priv->can.can_stats.bus_off++; |
e0d1f481 DA |
590 | can_bus_off(dev); |
591 | break; | |
592 | default: | |
593 | break; | |
594 | } | |
595 | ||
596 | /* propagate the error condition to the CAN stack */ | |
597 | skb = alloc_can_err_skb(dev, &cf); | |
598 | if (unlikely(!skb)) | |
599 | return 0; | |
600 | ||
f6a99649 | 601 | __m_can_get_berr_counter(dev, &bec); |
e0d1f481 DA |
602 | |
603 | switch (new_state) { | |
604 | case CAN_STATE_ERROR_ACTIVE: | |
605 | /* error warning state */ | |
606 | cf->can_id |= CAN_ERR_CRTL; | |
607 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
608 | CAN_ERR_CRTL_TX_WARNING : | |
609 | CAN_ERR_CRTL_RX_WARNING; | |
610 | cf->data[6] = bec.txerr; | |
611 | cf->data[7] = bec.rxerr; | |
612 | break; | |
613 | case CAN_STATE_ERROR_PASSIVE: | |
614 | /* error passive state */ | |
615 | cf->can_id |= CAN_ERR_CRTL; | |
616 | ecr = m_can_read(priv, M_CAN_ECR); | |
617 | if (ecr & ECR_RP) | |
618 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | |
619 | if (bec.txerr > 127) | |
620 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; | |
621 | cf->data[6] = bec.txerr; | |
622 | cf->data[7] = bec.rxerr; | |
623 | break; | |
624 | case CAN_STATE_BUS_OFF: | |
625 | /* bus-off state */ | |
626 | cf->can_id |= CAN_ERR_BUSOFF; | |
627 | break; | |
628 | default: | |
629 | break; | |
630 | } | |
631 | ||
632 | stats->rx_packets++; | |
633 | stats->rx_bytes += cf->can_dlc; | |
634 | netif_receive_skb(skb); | |
635 | ||
636 | return 1; | |
637 | } | |
638 | ||
639 | static int m_can_handle_state_errors(struct net_device *dev, u32 psr) | |
640 | { | |
641 | struct m_can_priv *priv = netdev_priv(dev); | |
642 | int work_done = 0; | |
643 | ||
644 | if ((psr & PSR_EW) && | |
645 | (priv->can.state != CAN_STATE_ERROR_WARNING)) { | |
646 | netdev_dbg(dev, "entered error warning state\n"); | |
647 | work_done += m_can_handle_state_change(dev, | |
648 | CAN_STATE_ERROR_WARNING); | |
649 | } | |
650 | ||
651 | if ((psr & PSR_EP) && | |
652 | (priv->can.state != CAN_STATE_ERROR_PASSIVE)) { | |
a93f5cae | 653 | netdev_dbg(dev, "entered error passive state\n"); |
e0d1f481 DA |
654 | work_done += m_can_handle_state_change(dev, |
655 | CAN_STATE_ERROR_PASSIVE); | |
656 | } | |
657 | ||
658 | if ((psr & PSR_BO) && | |
659 | (priv->can.state != CAN_STATE_BUS_OFF)) { | |
a93f5cae | 660 | netdev_dbg(dev, "entered error bus off state\n"); |
e0d1f481 DA |
661 | work_done += m_can_handle_state_change(dev, |
662 | CAN_STATE_BUS_OFF); | |
663 | } | |
664 | ||
665 | return work_done; | |
666 | } | |
667 | ||
668 | static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) | |
669 | { | |
670 | if (irqstatus & IR_WDI) | |
671 | netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); | |
a93f5cae | 672 | if (irqstatus & IR_ELO) |
e0d1f481 DA |
673 | netdev_err(dev, "Error Logging Overflow\n"); |
674 | if (irqstatus & IR_BEU) | |
675 | netdev_err(dev, "Bit Error Uncorrected\n"); | |
676 | if (irqstatus & IR_BEC) | |
677 | netdev_err(dev, "Bit Error Corrected\n"); | |
678 | if (irqstatus & IR_TOO) | |
679 | netdev_err(dev, "Timeout reached\n"); | |
680 | if (irqstatus & IR_MRAF) | |
681 | netdev_err(dev, "Message RAM access failure occurred\n"); | |
682 | } | |
683 | ||
684 | static inline bool is_lec_err(u32 psr) | |
685 | { | |
686 | psr &= LEC_UNUSED; | |
687 | ||
688 | return psr && (psr != LEC_UNUSED); | |
689 | } | |
690 | ||
691 | static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, | |
692 | u32 psr) | |
693 | { | |
694 | struct m_can_priv *priv = netdev_priv(dev); | |
695 | int work_done = 0; | |
696 | ||
697 | if (irqstatus & IR_RF0L) | |
698 | work_done += m_can_handle_lost_msg(dev); | |
699 | ||
700 | /* handle lec errors on the bus */ | |
701 | if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && | |
702 | is_lec_err(psr)) | |
703 | work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); | |
704 | ||
705 | /* other unproccessed error interrupts */ | |
706 | m_can_handle_other_err(dev, irqstatus); | |
707 | ||
708 | return work_done; | |
709 | } | |
710 | ||
711 | static int m_can_poll(struct napi_struct *napi, int quota) | |
712 | { | |
713 | struct net_device *dev = napi->dev; | |
714 | struct m_can_priv *priv = netdev_priv(dev); | |
715 | int work_done = 0; | |
716 | u32 irqstatus, psr; | |
717 | ||
718 | irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR); | |
719 | if (!irqstatus) | |
720 | goto end; | |
721 | ||
722 | psr = m_can_read(priv, M_CAN_PSR); | |
723 | if (irqstatus & IR_ERR_STATE) | |
724 | work_done += m_can_handle_state_errors(dev, psr); | |
725 | ||
726 | if (irqstatus & IR_ERR_BUS) | |
727 | work_done += m_can_handle_bus_errors(dev, irqstatus, psr); | |
728 | ||
729 | if (irqstatus & IR_RF0N) | |
730 | work_done += m_can_do_rx_poll(dev, (quota - work_done)); | |
731 | ||
732 | if (work_done < quota) { | |
733 | napi_complete(napi); | |
734 | m_can_enable_all_interrupts(priv); | |
735 | } | |
736 | ||
737 | end: | |
738 | return work_done; | |
739 | } | |
740 | ||
741 | static irqreturn_t m_can_isr(int irq, void *dev_id) | |
742 | { | |
743 | struct net_device *dev = (struct net_device *)dev_id; | |
744 | struct m_can_priv *priv = netdev_priv(dev); | |
745 | struct net_device_stats *stats = &dev->stats; | |
746 | u32 ir; | |
747 | ||
748 | ir = m_can_read(priv, M_CAN_IR); | |
749 | if (!ir) | |
750 | return IRQ_NONE; | |
751 | ||
752 | /* ACK all irqs */ | |
753 | if (ir & IR_ALL_INT) | |
754 | m_can_write(priv, M_CAN_IR, ir); | |
755 | ||
756 | /* schedule NAPI in case of | |
757 | * - rx IRQ | |
758 | * - state change IRQ | |
759 | * - bus error IRQ and bus error reporting | |
760 | */ | |
761 | if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) { | |
762 | priv->irqstatus = ir; | |
763 | m_can_disable_all_interrupts(priv); | |
764 | napi_schedule(&priv->napi); | |
765 | } | |
766 | ||
767 | /* transmission complete interrupt */ | |
768 | if (ir & IR_TC) { | |
769 | stats->tx_bytes += can_get_echo_skb(dev, 0); | |
770 | stats->tx_packets++; | |
771 | can_led_event(dev, CAN_LED_EVENT_TX); | |
772 | netif_wake_queue(dev); | |
773 | } | |
774 | ||
775 | return IRQ_HANDLED; | |
776 | } | |
777 | ||
778 | static const struct can_bittiming_const m_can_bittiming_const = { | |
779 | .name = KBUILD_MODNAME, | |
780 | .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ | |
781 | .tseg1_max = 64, | |
782 | .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ | |
783 | .tseg2_max = 16, | |
784 | .sjw_max = 16, | |
785 | .brp_min = 1, | |
786 | .brp_max = 1024, | |
787 | .brp_inc = 1, | |
788 | }; | |
789 | ||
80646733 DA |
790 | static const struct can_bittiming_const m_can_data_bittiming_const = { |
791 | .name = KBUILD_MODNAME, | |
792 | .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ | |
793 | .tseg1_max = 16, | |
794 | .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ | |
795 | .tseg2_max = 8, | |
796 | .sjw_max = 4, | |
797 | .brp_min = 1, | |
798 | .brp_max = 32, | |
799 | .brp_inc = 1, | |
800 | }; | |
801 | ||
e0d1f481 DA |
802 | static int m_can_set_bittiming(struct net_device *dev) |
803 | { | |
804 | struct m_can_priv *priv = netdev_priv(dev); | |
805 | const struct can_bittiming *bt = &priv->can.bittiming; | |
80646733 | 806 | const struct can_bittiming *dbt = &priv->can.data_bittiming; |
e0d1f481 DA |
807 | u16 brp, sjw, tseg1, tseg2; |
808 | u32 reg_btp; | |
809 | ||
810 | brp = bt->brp - 1; | |
811 | sjw = bt->sjw - 1; | |
812 | tseg1 = bt->prop_seg + bt->phase_seg1 - 1; | |
813 | tseg2 = bt->phase_seg2 - 1; | |
814 | reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) | | |
815 | (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT); | |
816 | m_can_write(priv, M_CAN_BTP, reg_btp); | |
80646733 DA |
817 | |
818 | if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { | |
819 | brp = dbt->brp - 1; | |
820 | sjw = dbt->sjw - 1; | |
821 | tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; | |
822 | tseg2 = dbt->phase_seg2 - 1; | |
823 | reg_btp = (brp << FBTR_FBRP_SHIFT) | (sjw << FBTR_FSJW_SHIFT) | | |
824 | (tseg1 << FBTR_FTSEG1_SHIFT) | | |
825 | (tseg2 << FBTR_FTSEG2_SHIFT); | |
826 | m_can_write(priv, M_CAN_FBTP, reg_btp); | |
827 | } | |
e0d1f481 DA |
828 | |
829 | return 0; | |
830 | } | |
831 | ||
832 | /* Configure M_CAN chip: | |
833 | * - set rx buffer/fifo element size | |
834 | * - configure rx fifo | |
835 | * - accept non-matching frame into fifo 0 | |
836 | * - configure tx buffer | |
837 | * - configure mode | |
838 | * - setup bittiming | |
839 | */ | |
840 | static void m_can_chip_config(struct net_device *dev) | |
841 | { | |
842 | struct m_can_priv *priv = netdev_priv(dev); | |
843 | u32 cccr, test; | |
844 | ||
845 | m_can_config_endisable(priv, true); | |
846 | ||
80646733 DA |
847 | /* RX Buffer/FIFO Element Size 64 bytes data field */ |
848 | m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES); | |
e0d1f481 DA |
849 | |
850 | /* Accept Non-matching Frames Into FIFO 0 */ | |
851 | m_can_write(priv, M_CAN_GFC, 0x0); | |
852 | ||
853 | /* only support one Tx Buffer currently */ | |
854 | m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) | | |
855 | priv->mcfg[MRAM_TXB].off); | |
856 | ||
80646733 DA |
857 | /* support 64 bytes payload */ |
858 | m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES); | |
e0d1f481 DA |
859 | |
860 | m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) | | |
861 | priv->mcfg[MRAM_TXE].off); | |
862 | ||
863 | /* rx fifo configuration, blocking mode, fifo size 1 */ | |
864 | m_can_write(priv, M_CAN_RXF0C, | |
865 | (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) | | |
866 | RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off); | |
867 | ||
868 | m_can_write(priv, M_CAN_RXF1C, | |
869 | (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) | | |
870 | RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off); | |
871 | ||
872 | cccr = m_can_read(priv, M_CAN_CCCR); | |
80646733 DA |
873 | cccr &= ~(CCCR_TEST | CCCR_MON | (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | |
874 | (CCCR_CME_MASK << CCCR_CME_SHIFT)); | |
e0d1f481 DA |
875 | test = m_can_read(priv, M_CAN_TEST); |
876 | test &= ~TEST_LBCK; | |
877 | ||
878 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
879 | cccr |= CCCR_MON; | |
880 | ||
881 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
882 | cccr |= CCCR_TEST; | |
883 | test |= TEST_LBCK; | |
884 | } | |
885 | ||
80646733 DA |
886 | if (priv->can.ctrlmode & CAN_CTRLMODE_FD) |
887 | cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; | |
888 | ||
e0d1f481 DA |
889 | m_can_write(priv, M_CAN_CCCR, cccr); |
890 | m_can_write(priv, M_CAN_TEST, test); | |
891 | ||
892 | /* enable interrupts */ | |
893 | m_can_write(priv, M_CAN_IR, IR_ALL_INT); | |
894 | if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) | |
895 | m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC); | |
896 | else | |
897 | m_can_write(priv, M_CAN_IE, IR_ALL_INT); | |
898 | ||
899 | /* route all interrupts to INT0 */ | |
900 | m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0); | |
901 | ||
902 | /* set bittiming params */ | |
903 | m_can_set_bittiming(dev); | |
904 | ||
905 | m_can_config_endisable(priv, false); | |
906 | } | |
907 | ||
908 | static void m_can_start(struct net_device *dev) | |
909 | { | |
910 | struct m_can_priv *priv = netdev_priv(dev); | |
911 | ||
912 | /* basic m_can configuration */ | |
913 | m_can_chip_config(dev); | |
914 | ||
915 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
916 | ||
917 | m_can_enable_all_interrupts(priv); | |
918 | } | |
919 | ||
920 | static int m_can_set_mode(struct net_device *dev, enum can_mode mode) | |
921 | { | |
922 | switch (mode) { | |
923 | case CAN_MODE_START: | |
924 | m_can_start(dev); | |
925 | netif_wake_queue(dev); | |
926 | break; | |
927 | default: | |
928 | return -EOPNOTSUPP; | |
929 | } | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | static void free_m_can_dev(struct net_device *dev) | |
935 | { | |
936 | free_candev(dev); | |
937 | } | |
938 | ||
939 | static struct net_device *alloc_m_can_dev(void) | |
940 | { | |
941 | struct net_device *dev; | |
942 | struct m_can_priv *priv; | |
943 | ||
944 | dev = alloc_candev(sizeof(*priv), 1); | |
945 | if (!dev) | |
946 | return NULL; | |
947 | ||
948 | priv = netdev_priv(dev); | |
949 | netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT); | |
950 | ||
951 | priv->dev = dev; | |
952 | priv->can.bittiming_const = &m_can_bittiming_const; | |
80646733 | 953 | priv->can.data_bittiming_const = &m_can_data_bittiming_const; |
e0d1f481 DA |
954 | priv->can.do_set_mode = m_can_set_mode; |
955 | priv->can.do_get_berr_counter = m_can_get_berr_counter; | |
6cfda7fb OH |
956 | |
957 | /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.1 */ | |
958 | priv->can.ctrlmode = CAN_CTRLMODE_FD_NON_ISO; | |
959 | ||
960 | /* CAN_CTRLMODE_FD_NON_ISO can not be changed with M_CAN IP v3.0.1 */ | |
e0d1f481 DA |
961 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | |
962 | CAN_CTRLMODE_LISTENONLY | | |
80646733 DA |
963 | CAN_CTRLMODE_BERR_REPORTING | |
964 | CAN_CTRLMODE_FD; | |
e0d1f481 DA |
965 | |
966 | return dev; | |
967 | } | |
968 | ||
969 | static int m_can_open(struct net_device *dev) | |
970 | { | |
971 | struct m_can_priv *priv = netdev_priv(dev); | |
972 | int err; | |
973 | ||
974 | err = clk_prepare_enable(priv->hclk); | |
975 | if (err) | |
976 | return err; | |
977 | ||
978 | err = clk_prepare_enable(priv->cclk); | |
979 | if (err) | |
980 | goto exit_disable_hclk; | |
981 | ||
982 | /* open the can device */ | |
983 | err = open_candev(dev); | |
984 | if (err) { | |
985 | netdev_err(dev, "failed to open can device\n"); | |
986 | goto exit_disable_cclk; | |
987 | } | |
988 | ||
989 | /* register interrupt handler */ | |
990 | err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, | |
991 | dev); | |
992 | if (err < 0) { | |
993 | netdev_err(dev, "failed to request interrupt\n"); | |
994 | goto exit_irq_fail; | |
995 | } | |
996 | ||
997 | /* start the m_can controller */ | |
998 | m_can_start(dev); | |
999 | ||
1000 | can_led_event(dev, CAN_LED_EVENT_OPEN); | |
1001 | napi_enable(&priv->napi); | |
1002 | netif_start_queue(dev); | |
1003 | ||
1004 | return 0; | |
1005 | ||
1006 | exit_irq_fail: | |
1007 | close_candev(dev); | |
1008 | exit_disable_cclk: | |
1009 | clk_disable_unprepare(priv->cclk); | |
1010 | exit_disable_hclk: | |
1011 | clk_disable_unprepare(priv->hclk); | |
1012 | return err; | |
1013 | } | |
1014 | ||
1015 | static void m_can_stop(struct net_device *dev) | |
1016 | { | |
1017 | struct m_can_priv *priv = netdev_priv(dev); | |
1018 | ||
1019 | /* disable all interrupts */ | |
1020 | m_can_disable_all_interrupts(priv); | |
1021 | ||
1022 | clk_disable_unprepare(priv->hclk); | |
1023 | clk_disable_unprepare(priv->cclk); | |
1024 | ||
1025 | /* set the state as STOPPED */ | |
1026 | priv->can.state = CAN_STATE_STOPPED; | |
1027 | } | |
1028 | ||
1029 | static int m_can_close(struct net_device *dev) | |
1030 | { | |
1031 | struct m_can_priv *priv = netdev_priv(dev); | |
1032 | ||
1033 | netif_stop_queue(dev); | |
1034 | napi_disable(&priv->napi); | |
1035 | m_can_stop(dev); | |
1036 | free_irq(dev->irq, dev); | |
1037 | close_candev(dev); | |
1038 | can_led_event(dev, CAN_LED_EVENT_STOP); | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
1043 | static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, | |
1044 | struct net_device *dev) | |
1045 | { | |
1046 | struct m_can_priv *priv = netdev_priv(dev); | |
80646733 DA |
1047 | struct canfd_frame *cf = (struct canfd_frame *)skb->data; |
1048 | u32 id, cccr; | |
1049 | int i; | |
e0d1f481 DA |
1050 | |
1051 | if (can_dropped_invalid_skb(dev, skb)) | |
1052 | return NETDEV_TX_OK; | |
1053 | ||
1054 | netif_stop_queue(dev); | |
1055 | ||
1056 | if (cf->can_id & CAN_EFF_FLAG) { | |
1057 | id = cf->can_id & CAN_EFF_MASK; | |
1058 | id |= TX_BUF_XTD; | |
1059 | } else { | |
1060 | id = ((cf->can_id & CAN_SFF_MASK) << 18); | |
1061 | } | |
1062 | ||
1063 | if (cf->can_id & CAN_RTR_FLAG) | |
1064 | id |= TX_BUF_RTR; | |
1065 | ||
1066 | /* message ram configuration */ | |
1067 | m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id); | |
80646733 DA |
1068 | m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16); |
1069 | ||
1070 | for (i = 0; i < cf->len; i += 4) | |
1071 | m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4), | |
1072 | *(u32 *)(cf->data + i)); | |
1073 | ||
e0d1f481 DA |
1074 | can_put_echo_skb(skb, dev, 0); |
1075 | ||
80646733 DA |
1076 | if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { |
1077 | cccr = m_can_read(priv, M_CAN_CCCR); | |
1078 | cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); | |
1079 | if (can_is_canfd_skb(skb)) { | |
1080 | if (cf->flags & CANFD_BRS) | |
1081 | cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT; | |
1082 | else | |
1083 | cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT; | |
1084 | } else { | |
1085 | cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; | |
1086 | } | |
1087 | m_can_write(priv, M_CAN_CCCR, cccr); | |
1088 | } | |
1089 | ||
e0d1f481 DA |
1090 | /* enable first TX buffer to start transfer */ |
1091 | m_can_write(priv, M_CAN_TXBTIE, 0x1); | |
1092 | m_can_write(priv, M_CAN_TXBAR, 0x1); | |
1093 | ||
1094 | return NETDEV_TX_OK; | |
1095 | } | |
1096 | ||
1097 | static const struct net_device_ops m_can_netdev_ops = { | |
1098 | .ndo_open = m_can_open, | |
1099 | .ndo_stop = m_can_close, | |
1100 | .ndo_start_xmit = m_can_start_xmit, | |
d6fdb38b | 1101 | .ndo_change_mtu = can_change_mtu, |
e0d1f481 DA |
1102 | }; |
1103 | ||
1104 | static int register_m_can_dev(struct net_device *dev) | |
1105 | { | |
1106 | dev->flags |= IFF_ECHO; /* we support local echo */ | |
1107 | dev->netdev_ops = &m_can_netdev_ops; | |
1108 | ||
1109 | return register_candev(dev); | |
1110 | } | |
1111 | ||
1112 | static int m_can_of_parse_mram(struct platform_device *pdev, | |
1113 | struct m_can_priv *priv) | |
1114 | { | |
1115 | struct device_node *np = pdev->dev.of_node; | |
1116 | struct resource *res; | |
1117 | void __iomem *addr; | |
1118 | u32 out_val[MRAM_CFG_LEN]; | |
962845da | 1119 | int i, start, end, ret; |
e0d1f481 DA |
1120 | |
1121 | /* message ram could be shared */ | |
1122 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram"); | |
1123 | if (!res) | |
1124 | return -ENODEV; | |
1125 | ||
1126 | addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | |
1127 | if (!addr) | |
1128 | return -ENOMEM; | |
1129 | ||
1130 | /* get message ram configuration */ | |
1131 | ret = of_property_read_u32_array(np, "bosch,mram-cfg", | |
1132 | out_val, sizeof(out_val) / 4); | |
1133 | if (ret) { | |
1134 | dev_err(&pdev->dev, "can not get message ram configuration\n"); | |
1135 | return -ENODEV; | |
1136 | } | |
1137 | ||
1138 | priv->mram_base = addr; | |
1139 | priv->mcfg[MRAM_SIDF].off = out_val[0]; | |
1140 | priv->mcfg[MRAM_SIDF].num = out_val[1]; | |
1141 | priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off + | |
1142 | priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; | |
1143 | priv->mcfg[MRAM_XIDF].num = out_val[2]; | |
1144 | priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off + | |
1145 | priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; | |
1146 | priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK; | |
1147 | priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off + | |
1148 | priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; | |
1149 | priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK; | |
1150 | priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off + | |
1151 | priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; | |
1152 | priv->mcfg[MRAM_RXB].num = out_val[5]; | |
1153 | priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off + | |
1154 | priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; | |
1155 | priv->mcfg[MRAM_TXE].num = out_val[6]; | |
1156 | priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off + | |
1157 | priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; | |
1158 | priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK; | |
1159 | ||
1160 | dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", | |
1161 | priv->mram_base, | |
1162 | priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num, | |
1163 | priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num, | |
1164 | priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num, | |
1165 | priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num, | |
1166 | priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num, | |
1167 | priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num, | |
1168 | priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num); | |
1169 | ||
962845da DA |
1170 | /* initialize the entire Message RAM in use to avoid possible |
1171 | * ECC/parity checksum errors when reading an uninitialized buffer | |
1172 | */ | |
1173 | start = priv->mcfg[MRAM_SIDF].off; | |
1174 | end = priv->mcfg[MRAM_TXB].off + | |
1175 | priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; | |
1176 | for (i = start; i < end; i += 4) | |
1177 | writel(0x0, priv->mram_base + i); | |
1178 | ||
e0d1f481 DA |
1179 | return 0; |
1180 | } | |
1181 | ||
1182 | static int m_can_plat_probe(struct platform_device *pdev) | |
1183 | { | |
1184 | struct net_device *dev; | |
1185 | struct m_can_priv *priv; | |
1186 | struct resource *res; | |
1187 | void __iomem *addr; | |
1188 | struct clk *hclk, *cclk; | |
1189 | int irq, ret; | |
1190 | ||
1191 | hclk = devm_clk_get(&pdev->dev, "hclk"); | |
1192 | cclk = devm_clk_get(&pdev->dev, "cclk"); | |
1193 | if (IS_ERR(hclk) || IS_ERR(cclk)) { | |
1194 | dev_err(&pdev->dev, "no clock find\n"); | |
1195 | return -ENODEV; | |
1196 | } | |
1197 | ||
1198 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can"); | |
1199 | addr = devm_ioremap_resource(&pdev->dev, res); | |
1200 | irq = platform_get_irq_byname(pdev, "int0"); | |
1201 | if (IS_ERR(addr) || irq < 0) | |
1202 | return -EINVAL; | |
1203 | ||
1204 | /* allocate the m_can device */ | |
1205 | dev = alloc_m_can_dev(); | |
1206 | if (!dev) | |
1207 | return -ENOMEM; | |
1208 | ||
1209 | priv = netdev_priv(dev); | |
1210 | dev->irq = irq; | |
1211 | priv->base = addr; | |
1212 | priv->device = &pdev->dev; | |
1213 | priv->hclk = hclk; | |
1214 | priv->cclk = cclk; | |
1215 | priv->can.clock.freq = clk_get_rate(cclk); | |
1216 | ||
1217 | ret = m_can_of_parse_mram(pdev, priv); | |
1218 | if (ret) | |
1219 | goto failed_free_dev; | |
1220 | ||
1221 | platform_set_drvdata(pdev, dev); | |
1222 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1223 | ||
1224 | ret = register_m_can_dev(dev); | |
1225 | if (ret) { | |
1226 | dev_err(&pdev->dev, "registering %s failed (err=%d)\n", | |
1227 | KBUILD_MODNAME, ret); | |
1228 | goto failed_free_dev; | |
1229 | } | |
1230 | ||
1231 | devm_can_led_init(dev); | |
1232 | ||
1233 | dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", | |
1234 | KBUILD_MODNAME, priv->base, dev->irq); | |
1235 | ||
1236 | return 0; | |
1237 | ||
1238 | failed_free_dev: | |
1239 | free_m_can_dev(dev); | |
1240 | return ret; | |
1241 | } | |
1242 | ||
1243 | static __maybe_unused int m_can_suspend(struct device *dev) | |
1244 | { | |
1245 | struct net_device *ndev = dev_get_drvdata(dev); | |
1246 | struct m_can_priv *priv = netdev_priv(ndev); | |
1247 | ||
1248 | if (netif_running(ndev)) { | |
1249 | netif_stop_queue(ndev); | |
1250 | netif_device_detach(ndev); | |
1251 | } | |
1252 | ||
1253 | /* TODO: enter low power */ | |
1254 | ||
1255 | priv->can.state = CAN_STATE_SLEEPING; | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | static __maybe_unused int m_can_resume(struct device *dev) | |
1261 | { | |
1262 | struct net_device *ndev = dev_get_drvdata(dev); | |
1263 | struct m_can_priv *priv = netdev_priv(ndev); | |
1264 | ||
1265 | /* TODO: exit low power */ | |
1266 | ||
1267 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1268 | ||
1269 | if (netif_running(ndev)) { | |
1270 | netif_device_attach(ndev); | |
1271 | netif_start_queue(ndev); | |
1272 | } | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | static void unregister_m_can_dev(struct net_device *dev) | |
1278 | { | |
1279 | unregister_candev(dev); | |
1280 | } | |
1281 | ||
1282 | static int m_can_plat_remove(struct platform_device *pdev) | |
1283 | { | |
1284 | struct net_device *dev = platform_get_drvdata(pdev); | |
1285 | ||
1286 | unregister_m_can_dev(dev); | |
1287 | platform_set_drvdata(pdev, NULL); | |
1288 | ||
1289 | free_m_can_dev(dev); | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static const struct dev_pm_ops m_can_pmops = { | |
1295 | SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume) | |
1296 | }; | |
1297 | ||
1298 | static const struct of_device_id m_can_of_table[] = { | |
1299 | { .compatible = "bosch,m_can", .data = NULL }, | |
1300 | { /* sentinel */ }, | |
1301 | }; | |
1302 | MODULE_DEVICE_TABLE(of, m_can_of_table); | |
1303 | ||
1304 | static struct platform_driver m_can_plat_driver = { | |
1305 | .driver = { | |
1306 | .name = KBUILD_MODNAME, | |
1307 | .of_match_table = m_can_of_table, | |
1308 | .pm = &m_can_pmops, | |
1309 | }, | |
1310 | .probe = m_can_plat_probe, | |
1311 | .remove = m_can_plat_remove, | |
1312 | }; | |
1313 | ||
1314 | module_platform_driver(m_can_plat_driver); | |
1315 | ||
1316 | MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); | |
1317 | MODULE_LICENSE("GPL v2"); | |
1318 | MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); |