[mirror_ubuntu-jammy-kernel.git] / drivers / net / can / m_can / m_can_pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCI Specific M_CAN Glue
 *
 * Copyright (C) 2018-2020 Intel Corporation
 * Author: Felipe Balbi (Intel)
 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
 * Author: Raymond Tan <raymond.tan@intel.com>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>

#include "m_can.h"

#define M_CAN_PCI_MMIO_BAR		0

#define M_CAN_CLOCK_FREQ_EHL		200000000
#define CTL_CSR_INT_CTL_OFFSET		0x508

struct m_can_pci_priv {
	struct m_can_classdev cdev;

	void __iomem *base;
};

static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev)
{
	return container_of(cdev, struct m_can_pci_priv, cdev);
}

static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
{
	struct m_can_pci_priv *priv = cdev_to_priv(cdev);

	return readl(priv->base + reg);
}

static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
{
	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
	void __iomem *src = priv->base + offset;

	while (val_count--) {
		*(unsigned int *)val = ioread32(src);
		val += 4;
		src += 4;
	}

	return 0;
}

static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
{
	struct m_can_pci_priv *priv = cdev_to_priv(cdev);

	writel(val, priv->base + reg);

	return 0;
}

static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
			    const void *val, size_t val_count)
{
	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
	void __iomem *dst = priv->base + offset;

	while (val_count--) {
		iowrite32(*(unsigned int *)val, dst);
		val += 4;
		dst += 4;
	}

	return 0;
}

static struct m_can_ops m_can_pci_ops = {
	.read_reg = iomap_read_reg,
	.write_reg = iomap_write_reg,
	.write_fifo = iomap_write_fifo,
	.read_fifo = iomap_read_fifo,
};

static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
{
	struct device *dev = &pci->dev;
	struct m_can_classdev *mcan_class;
	struct m_can_pci_priv *priv;
	void __iomem *base;
	int ret;

	ret = pcim_enable_device(pci);
	if (ret)
		return ret;

	pci_set_master(pci);

	ret = pcim_iomap_regions(pci, BIT(M_CAN_PCI_MMIO_BAR), pci_name(pci));
	if (ret)
		return ret;

	base = pcim_iomap_table(pci)[M_CAN_PCI_MMIO_BAR];

	if (!base) {
		dev_err(dev, "failed to map BARs\n");
		return -ENOMEM;
	}

	mcan_class = m_can_class_allocate_dev(&pci->dev,
					      sizeof(struct m_can_pci_priv));
	if (!mcan_class)
		return -ENOMEM;

	priv = cdev_to_priv(mcan_class);

	priv->base = base;

	ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);
	if (ret < 0)
		return ret;

	mcan_class->dev = &pci->dev;
	mcan_class->net->irq = pci_irq_vector(pci, 0);
	mcan_class->pm_clock_support = 1;
	mcan_class->can.clock.freq = id->driver_data;
	mcan_class->ops = &m_can_pci_ops;

	pci_set_drvdata(pci, mcan_class);

	ret = m_can_class_register(mcan_class);
	if (ret)
		goto err;

	/* Enable interrupt control at CAN wrapper IP */
	writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);

	pm_runtime_set_autosuspend_delay(dev, 1000);
	pm_runtime_use_autosuspend(dev);
	pm_runtime_put_noidle(dev);
	pm_runtime_allow(dev);

	return 0;

err:
	pci_free_irq_vectors(pci);
	return ret;
}

static void m_can_pci_remove(struct pci_dev *pci)
{
	struct m_can_classdev *mcan_class = pci_get_drvdata(pci);
	struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);

	pm_runtime_forbid(&pci->dev);
	pm_runtime_get_noresume(&pci->dev);

	/* Disable interrupt control at CAN wrapper IP */
	writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);

	m_can_class_unregister(mcan_class);
	pci_free_irq_vectors(pci);
}

static __maybe_unused int m_can_pci_suspend(struct device *dev)
{
	return m_can_class_suspend(dev);
}

static __maybe_unused int m_can_pci_resume(struct device *dev)
{
	return m_can_class_resume(dev);
}

static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,
			 m_can_pci_suspend, m_can_pci_resume);

static const struct pci_device_id m_can_pci_id_table[] = {
	{ PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
	{ PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
	{  }	/* Terminating Entry */
};
MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);

static struct pci_driver m_can_pci_driver = {
	.name = "m_can_pci",
	.probe = m_can_pci_probe,
	.remove = m_can_pci_remove,
	.id_table = m_can_pci_id_table,
	.driver = {
		.pm = &m_can_pci_pm_ops,
	},
};

module_pci_driver(m_can_pci_driver);

MODULE_AUTHOR("Felipe Balbi (Intel)");
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller on PCI bus");
Commit	Line	Data
cab7ffc0 JN	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* PCI Specific M_CAN Glue
	4	*
	5	* Copyright (C) 2018-2020 Intel Corporation
	6	* Author: Felipe Balbi (Intel)
	7	* Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
	8	* Author: Raymond Tan <raymond.tan@intel.com>
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/netdevice.h>
	14	#include <linux/pci.h>
	15	#include <linux/pm_runtime.h>
	16
	17	#include "m_can.h"
	18
	19	#define M_CAN_PCI_MMIO_BAR 0
	20
61f9fd79	21	#define M_CAN_CLOCK_FREQ_EHL 200000000
cab7ffc0 JN	22	#define CTL_CSR_INT_CTL_OFFSET 0x508
	23
	24	struct m_can_pci_priv {
ac33ffd3 MKB	25	struct m_can_classdev cdev;
ac33ffd3 MKB	26
cab7ffc0 JN	27	void __iomem *base;
	28	};
	29
ac33ffd3 MKB	30	static inline struct m_can_pci_priv cdev_to_priv(struct m_can_classdev cdev)
	31	{
	32	return container_of(cdev, struct m_can_pci_priv, cdev);
	33	}
	34
cab7ffc0 JN	35	static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
cab7ffc0 JN	36	{
ac33ffd3	37	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
cab7ffc0 JN	38
	39	return readl(priv->base + reg);
	40	}
	41
e3938177	42	static int iomap_read_fifo(struct m_can_classdev cdev, int offset, void val, size_t val_count)
cab7ffc0	43	{
ac33ffd3	44	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
af045ddd	45	void __iomem *src = priv->base + offset;
cab7ffc0	46
af045ddd MS	47	while (val_count--) {
	48	(unsigned int )val = ioread32(src);
	49	val += 4;
	50	src += 4;
	51	}
e3938177 MK	52
e3938177 MK	53	return 0;
cab7ffc0 JN	54	}
	55
	56	static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
	57	{
ac33ffd3	58	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
cab7ffc0 JN	59
	60	writel(val, priv->base + reg);
	61
	62	return 0;
	63	}
	64
e3938177 MK	65	static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
e3938177 MK	66	const void *val, size_t val_count)
cab7ffc0	67	{
ac33ffd3	68	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
af045ddd	69	void __iomem *dst = priv->base + offset;
cab7ffc0	70
af045ddd MS	71	while (val_count--) {
	72	iowrite32((unsigned int )val, dst);
	73	val += 4;
	74	dst += 4;
	75	}
cab7ffc0 JN	76
	77	return 0;
	78	}
	79
	80	static struct m_can_ops m_can_pci_ops = {
	81	.read_reg = iomap_read_reg,
	82	.write_reg = iomap_write_reg,
	83	.write_fifo = iomap_write_fifo,
	84	.read_fifo = iomap_read_fifo,
	85	};
	86
	87	static int m_can_pci_probe(struct pci_dev pci, const struct pci_device_id id)
	88	{
	89	struct device *dev = &pci->dev;
	90	struct m_can_classdev *mcan_class;
	91	struct m_can_pci_priv *priv;
	92	void __iomem *base;
	93	int ret;
	94
	95	ret = pcim_enable_device(pci);
	96	if (ret)
	97	return ret;
	98
	99	pci_set_master(pci);
	100
	101	ret = pcim_iomap_regions(pci, BIT(M_CAN_PCI_MMIO_BAR), pci_name(pci));
	102	if (ret)
	103	return ret;
	104
	105	base = pcim_iomap_table(pci)[M_CAN_PCI_MMIO_BAR];
	106
	107	if (!base) {
	108	dev_err(dev, "failed to map BARs\n");
	109	return -ENOMEM;
	110	}
	111
ac33ffd3 MKB	112	mcan_class = m_can_class_allocate_dev(&pci->dev,
ac33ffd3 MKB	113	sizeof(struct m_can_pci_priv));
cab7ffc0 JN	114	if (!mcan_class)
	115	return -ENOMEM;
	116
ac33ffd3 MKB	117	priv = cdev_to_priv(mcan_class);
ac33ffd3 MKB	118
cab7ffc0 JN	119	priv->base = base;
	120
	121	ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);
	122	if (ret < 0)
	123	return ret;
	124
cab7ffc0 JN	125	mcan_class->dev = &pci->dev;
	126	mcan_class->net->irq = pci_irq_vector(pci, 0);
	127	mcan_class->pm_clock_support = 1;
	128	mcan_class->can.clock.freq = id->driver_data;
	129	mcan_class->ops = &m_can_pci_ops;
	130
c6b73489	131	pci_set_drvdata(pci, mcan_class);
cab7ffc0 JN	132
	133	ret = m_can_class_register(mcan_class);
	134	if (ret)
	135	goto err;
	136
	137	/* Enable interrupt control at CAN wrapper IP */
	138	writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);
	139
	140	pm_runtime_set_autosuspend_delay(dev, 1000);
	141	pm_runtime_use_autosuspend(dev);
	142	pm_runtime_put_noidle(dev);
	143	pm_runtime_allow(dev);
	144
	145	return 0;
	146
	147	err:
	148	pci_free_irq_vectors(pci);
	149	return ret;
	150	}
	151
	152	static void m_can_pci_remove(struct pci_dev *pci)
	153	{
c6b73489	154	struct m_can_classdev *mcan_class = pci_get_drvdata(pci);
ac33ffd3	155	struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);
cab7ffc0 JN	156
	157	pm_runtime_forbid(&pci->dev);
	158	pm_runtime_get_noresume(&pci->dev);
	159
	160	/* Disable interrupt control at CAN wrapper IP */
	161	writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);
	162
	163	m_can_class_unregister(mcan_class);
	164	pci_free_irq_vectors(pci);
	165	}
	166
	167	static __maybe_unused int m_can_pci_suspend(struct device *dev)
	168	{
	169	return m_can_class_suspend(dev);
	170	}
	171
	172	static __maybe_unused int m_can_pci_resume(struct device *dev)
	173	{
	174	return m_can_class_resume(dev);
	175	}
	176
	177	static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,
	178	m_can_pci_suspend, m_can_pci_resume);
	179
	180	static const struct pci_device_id m_can_pci_id_table[] = {
	181	{ PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
	182	{ PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
	183	{ } /* Terminating Entry */
	184	};
	185	MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);
	186
	187	static struct pci_driver m_can_pci_driver = {
	188	.name = "m_can_pci",
	189	.probe = m_can_pci_probe,
	190	.remove = m_can_pci_remove,
	191	.id_table = m_can_pci_id_table,
	192	.driver = {
	193	.pm = &m_can_pci_pm_ops,
	194	},
	195	};
	196
	197	module_pci_driver(m_can_pci_driver);
	198
	199	MODULE_AUTHOR("Felipe Balbi (Intel)");
	200	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
	201	MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
	202	MODULE_LICENSE("GPL");
	203	MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller on PCI bus");