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pch_can: Fix warnings
[mirror_ubuntu-artful-kernel.git] / drivers / net / can / pch_can.c
CommitLineData
b21d18b5
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/netdevice.h>
30#include <linux/skbuff.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34
086b5650
T		 35#define PCH_ENABLE 1 /* The enable flag */
36#define PCH_DISABLE 0 /* The disable flag */
0a80410d
T		 37#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
38#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
39#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
40#define PCH_CTRL_CCE BIT(6)
41#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
42#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
43#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
44
086b5650
T		 45#define PCH_CMASK_RX_TX_SET 0x00f3
46#define PCH_CMASK_RX_TX_GET 0x0073
47#define PCH_CMASK_ALL 0xff
0a80410d
T		 48#define PCH_CMASK_NEWDAT BIT(2)
49#define PCH_CMASK_CLRINTPND BIT(3)
50#define PCH_CMASK_CTRL BIT(4)
51#define PCH_CMASK_ARB BIT(5)
52#define PCH_CMASK_MASK BIT(6)
53#define PCH_CMASK_RDWR BIT(7)
54#define PCH_IF_MCONT_NEWDAT BIT(15)
55#define PCH_IF_MCONT_MSGLOST BIT(14)
56#define PCH_IF_MCONT_INTPND BIT(13)
57#define PCH_IF_MCONT_UMASK BIT(12)
58#define PCH_IF_MCONT_TXIE BIT(11)
59#define PCH_IF_MCONT_RXIE BIT(10)
60#define PCH_IF_MCONT_RMTEN BIT(9)
61#define PCH_IF_MCONT_TXRQXT BIT(8)
62#define PCH_IF_MCONT_EOB BIT(7)
63#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
64#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
65#define PCH_ID2_DIR BIT(13)
66#define PCH_ID2_XTD BIT(14)
67#define PCH_ID_MSGVAL BIT(15)
68#define PCH_IF_CREQ_BUSY BIT(15)
086b5650
T		 69
70#define PCH_STATUS_INT 0x8000
71#define PCH_REC 0x00007f00
72#define PCH_TEC 0x000000ff
b21d18b5 73
0a80410d
T		 74#define PCH_TX_OK BIT(3)
75#define PCH_RX_OK BIT(4)
76#define PCH_EPASSIV BIT(5)
77#define PCH_EWARN BIT(6)
78#define PCH_BUS_OFF BIT(7)
b21d18b5
MO		 79
80/* bit position of certain controller bits. */
086b5650
T		 81#define PCH_BIT_BRP 0
82#define PCH_BIT_SJW 6
83#define PCH_BIT_TSEG1 8
84#define PCH_BIT_TSEG2 12
85#define PCH_BIT_BRPE_BRPE 6
86#define PCH_MSK_BITT_BRP 0x3f
87#define PCH_MSK_BRPE_BRPE 0x3c0
88#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
89#define PCH_COUNTER_LIMIT 10
b21d18b5
MO		 90
91#define PCH_CAN_CLK 50000000 /* 50MHz */
92
93/* Define the number of message object.
94 * PCH CAN communications are done via Message RAM.
95 * The Message RAM consists of 32 message objects. */
15ffc8fd
T		 96#define PCH_RX_OBJ_NUM 26
97#define PCH_TX_OBJ_NUM 6
98#define PCH_RX_OBJ_START 1
99#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
100#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
101#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
b21d18b5
MO		 102
103#define PCH_FIFO_THRESH 16
104
76d94b23
T		 105/* TxRqst2 show status of MsgObjNo.17~32 */
106#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
107 (PCH_RX_OBJ_END - 16))
108
8339a7ed
T		 109enum pch_ifreg {
110 PCH_RX_IFREG,
111 PCH_TX_IFREG,
112};
113
d68f6837
T		 114enum pch_can_err {
115 PCH_STUF_ERR = 1,
116 PCH_FORM_ERR,
117 PCH_ACK_ERR,
118 PCH_BIT1_ERR,
119 PCH_BIT0_ERR,
120 PCH_CRC_ERR,
121 PCH_LEC_ALL,
122};
123
b21d18b5
MO		 124enum pch_can_mode {
125 PCH_CAN_ENABLE,
126 PCH_CAN_DISABLE,
127 PCH_CAN_ALL,
128 PCH_CAN_NONE,
129 PCH_CAN_STOP,
130 PCH_CAN_RUN
131};
132
8339a7ed
T		 133struct pch_can_if_regs {
134 u32 creq;
135 u32 cmask;
136 u32 mask1;
137 u32 mask2;
138 u32 id1;
139 u32 id2;
140 u32 mcont;
8ac9702b 141 u32 data[4];
8339a7ed
T		 142 u32 rsv[13];
143};
144
b21d18b5
MO		 145struct pch_can_regs {
146 u32 cont;
147 u32 stat;
148 u32 errc;
149 u32 bitt;
150 u32 intr;
151 u32 opt;
152 u32 brpe;
8339a7ed
T		 153 u32 reserve;
154 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
155 u32 reserve1[8];
b21d18b5
MO		 156 u32 treq1;
157 u32 treq2;
8339a7ed
T		 158 u32 reserve2[6];
159 u32 data1;
160 u32 data2;
161 u32 reserve3[6];
162 u32 canipend1;
163 u32 canipend2;
164 u32 reserve4[6];
165 u32 canmval1;
166 u32 canmval2;
167 u32 reserve5[37];
b21d18b5
MO		 168 u32 srst;
169};
170
171struct pch_can_priv {
172 struct can_priv can;
173 unsigned int can_num;
174 struct pci_dev *dev;
15ffc8fd
T		 175 int tx_enable[PCH_TX_OBJ_END];
176 int rx_enable[PCH_TX_OBJ_END];
177 int rx_link[PCH_TX_OBJ_END];
b21d18b5
MO		 178 unsigned int int_enables;
179 unsigned int int_stat;
180 struct net_device *ndev;
15ffc8fd 181 unsigned int msg_obj[PCH_TX_OBJ_END];
b21d18b5
MO		 182 struct pch_can_regs __iomem *regs;
183 struct napi_struct napi;
184 unsigned int tx_obj; /* Point next Tx Obj index */
185 unsigned int use_msi;
186};
187
188static struct can_bittiming_const pch_can_bittiming_const = {
189 .name = KBUILD_MODNAME,
190 .tseg1_min = 1,
191 .tseg1_max = 16,
192 .tseg2_min = 1,
193 .tseg2_max = 8,
194 .sjw_max = 4,
195 .brp_min = 1,
196 .brp_max = 1024, /* 6bit + extended 4bit */
197 .brp_inc = 1,
198};
199
200static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
201 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
202 {0,}
203};
204MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
205
526de53c 206static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
b21d18b5
MO		 207{
208 iowrite32(ioread32(addr) | mask, addr);
209}
210
526de53c 211static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
b21d18b5
MO		 212{
213 iowrite32(ioread32(addr) & ~mask, addr);
214}
215
216static void pch_can_set_run_mode(struct pch_can_priv *priv,
217 enum pch_can_mode mode)
218{
219 switch (mode) {
220 case PCH_CAN_RUN:
086b5650 221 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 222 break;
223
224 case PCH_CAN_STOP:
086b5650 225 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 226 break;
227
228 default:
229 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
230 break;
231 }
232}
233
234static void pch_can_set_optmode(struct pch_can_priv *priv)
235{
236 u32 reg_val = ioread32(&priv->regs->opt);
237
238 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
086b5650 239 reg_val |= PCH_OPT_SILENT;
b21d18b5
MO		 240
241 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
086b5650 242 reg_val |= PCH_OPT_LBACK;
b21d18b5 243
086b5650 244 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
b21d18b5
MO		 245 iowrite32(reg_val, &priv->regs->opt);
246}
247
b21d18b5
MO		 248static void pch_can_set_int_enables(struct pch_can_priv *priv,
249 enum pch_can_mode interrupt_no)
250{
251 switch (interrupt_no) {
252 case PCH_CAN_ENABLE:
086b5650 253 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 254 break;
255
256 case PCH_CAN_DISABLE:
086b5650 257 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 258 break;
259
260 case PCH_CAN_ALL:
086b5650 261 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 262 break;
263
264 case PCH_CAN_NONE:
086b5650 265 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 266 break;
267
268 default:
269 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
270 break;
271 }
272}
273
274static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
275{
086b5650 276 u32 counter = PCH_COUNTER_LIMIT;
b21d18b5
MO		 277 u32 ifx_creq;
278
279 iowrite32(num, creq_addr);
280 while (counter) {
086b5650 281 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
b21d18b5
MO		 282 if (!ifx_creq)
283 break;
284 counter--;
285 udelay(1);
286 }
287 if (!counter)
288 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
289}
290
8339a7ed
T		 291static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
292 u32 set, enum pch_ifreg dir)
b21d18b5 293{
8339a7ed
T		 294 u32 ie;
295
296 if (dir)
297 ie = PCH_IF_MCONT_TXIE;
298 else
299 ie = PCH_IF_MCONT_RXIE;
b21d18b5 300
b21d18b5 301 /* Reading the receive buffer data from RAM to Interface1 registers */
8339a7ed
T		 302 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
303 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 304
305 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
086b5650 306 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 307 &priv->regs->ifregs[dir].cmask);
b21d18b5 308
086b5650 309 if (set == PCH_ENABLE) {
b21d18b5 310 /* Setting the MsgVal and RxIE bits */
8339a7ed
T		 311 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
312 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5 313
086b5650 314 } else if (set == PCH_DISABLE) {
b21d18b5 315 /* Resetting the MsgVal and RxIE bits */
8339a7ed
T		 316 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
317 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5
MO		 318 }
319
8339a7ed 320 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 321}
322
8339a7ed 323static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set)
b21d18b5
MO		 324{
325 int i;
326
327 /* Traversing to obtain the object configured as receivers. */
15ffc8fd
T		 328 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
329 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
b21d18b5
MO		 330}
331
8339a7ed 332static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
b21d18b5
MO		 333{
334 int i;
335
336 /* Traversing to obtain the object configured as transmit object. */
15ffc8fd
T		 337 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
338 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
b21d18b5
MO		 339}
340
b21d18b5
MO		 341static int pch_can_int_pending(struct pch_can_priv *priv)
342{
343 return ioread32(&priv->regs->intr) & 0xffff;
344}
345
b21d18b5
MO		 346static void pch_can_clear_buffers(struct pch_can_priv *priv)
347{
348 int i;
349
15ffc8fd 350 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
8339a7ed
T		 351 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
352 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
353 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
354 iowrite32(0x0, &priv->regs->ifregs[0].id1);
355 iowrite32(0x0, &priv->regs->ifregs[0].id2);
356 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
8ac9702b
T		 357 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
358 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
359 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
360 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
086b5650
T		 361 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
362 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 363 &priv->regs->ifregs[0].cmask);
15ffc8fd 364 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
b21d18b5
MO		 365 }
366
15ffc8fd 367 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
8339a7ed
T		 368 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask);
369 iowrite32(0xffff, &priv->regs->ifregs[1].mask1);
370 iowrite32(0xffff, &priv->regs->ifregs[1].mask2);
371 iowrite32(0x0, &priv->regs->ifregs[1].id1);
372 iowrite32(0x0, &priv->regs->ifregs[1].id2);
373 iowrite32(0x0, &priv->regs->ifregs[1].mcont);
8ac9702b
T		 374 iowrite32(0x0, &priv->regs->ifregs[1].data[0]);
375 iowrite32(0x0, &priv->regs->ifregs[1].data[1]);
376 iowrite32(0x0, &priv->regs->ifregs[1].data[2]);
377 iowrite32(0x0, &priv->regs->ifregs[1].data[3]);
086b5650
T		 378 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
379 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 380 &priv->regs->ifregs[1].cmask);
15ffc8fd 381 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
b21d18b5
MO		 382 }
383}
384
385static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
386{
387 int i;
b21d18b5 388
15ffc8fd
T		 389 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
390 iowrite32(PCH_CMASK_RX_TX_GET,
391 &priv->regs->ifregs[0].cmask);
392 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
b21d18b5 393
15ffc8fd
T		 394 iowrite32(0x0, &priv->regs->ifregs[0].id1);
395 iowrite32(0x0, &priv->regs->ifregs[0].id2);
b21d18b5 396
15ffc8fd
T		 397 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
398 PCH_IF_MCONT_UMASK);
b21d18b5 399
15ffc8fd
T		 400 /* Set FIFO mode set to 0 except last Rx Obj*/
401 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
402 PCH_IF_MCONT_EOB);
403 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
404 if (i == PCH_RX_OBJ_END)
405 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
086b5650 406 PCH_IF_MCONT_EOB);
b21d18b5 407
15ffc8fd
T		 408 iowrite32(0, &priv->regs->ifregs[0].mask1);
409 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
410 0x1fff | PCH_MASK2_MDIR_MXTD);
b21d18b5 411
15ffc8fd
T		 412 /* Setting CMASK for writing */
413 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
414 PCH_CMASK_ARB | PCH_CMASK_CTRL,
415 &priv->regs->ifregs[0].cmask);
b21d18b5 416
15ffc8fd
T		 417 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
418 }
b21d18b5 419
15ffc8fd
T		 420 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
421 iowrite32(PCH_CMASK_RX_TX_GET,
422 &priv->regs->ifregs[1].cmask);
423 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
b21d18b5 424
15ffc8fd
T		 425 /* Resetting DIR bit for reception */
426 iowrite32(0x0, &priv->regs->ifregs[1].id1);
427 iowrite32(0x0, &priv->regs->ifregs[1].id2);
428 pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR);
b21d18b5 429
15ffc8fd
T		 430 /* Setting EOB bit for transmitter */
431 iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont);
b21d18b5 432
15ffc8fd
T		 433 pch_can_bit_set(&priv->regs->ifregs[1].mcont,
434 PCH_IF_MCONT_UMASK);
435
436 iowrite32(0, &priv->regs->ifregs[1].mask1);
437 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
438
439 /* Setting CMASK for writing */
440 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
441 PCH_CMASK_ARB | PCH_CMASK_CTRL,
442 &priv->regs->ifregs[1].cmask);
443
444 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
b21d18b5 445 }
b21d18b5
MO		 446}
447
448static void pch_can_init(struct pch_can_priv *priv)
449{
450 /* Stopping the Can device. */
451 pch_can_set_run_mode(priv, PCH_CAN_STOP);
452
453 /* Clearing all the message object buffers. */
454 pch_can_clear_buffers(priv);
455
456 /* Configuring the respective message object as either rx/tx object. */
457 pch_can_config_rx_tx_buffers(priv);
458
459 /* Enabling the interrupts. */
460 pch_can_set_int_enables(priv, PCH_CAN_ALL);
461}
462
463static void pch_can_release(struct pch_can_priv *priv)
464{
465 /* Stooping the CAN device. */
466 pch_can_set_run_mode(priv, PCH_CAN_STOP);
467
468 /* Disabling the interrupts. */
469 pch_can_set_int_enables(priv, PCH_CAN_NONE);
470
471 /* Disabling all the receive object. */
8339a7ed 472 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 473
474 /* Disabling all the transmit object. */
8339a7ed 475 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 476}
477
478/* This function clears interrupt(s) from the CAN device. */
479static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
480{
086b5650 481 if (mask == PCH_STATUS_INT) {
b21d18b5
MO		 482 ioread32(&priv->regs->stat);
483 return;
484 }
485
486 /* Clear interrupt for transmit object */
15ffc8fd
T		 487 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
488 /* Setting CMASK for clearing the reception interrupts. */
489 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
490 &priv->regs->ifregs[0].cmask);
491
492 /* Clearing the Dir bit. */
493 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
494
495 /* Clearing NewDat & IntPnd */
496 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
497 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
498
499 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask);
500 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
b21d18b5
MO		 501 /* Setting CMASK for clearing interrupts for
502 frame transmission. */
086b5650 503 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
8339a7ed 504 &priv->regs->ifregs[1].cmask);
b21d18b5
MO		 505
506 /* Resetting the ID registers. */
8339a7ed 507 pch_can_bit_set(&priv->regs->ifregs[1].id2,
086b5650 508 PCH_ID2_DIR | (0x7ff << 2));
8339a7ed 509 iowrite32(0x0, &priv->regs->ifregs[1].id1);
b21d18b5
MO		 510
511 /* Claring NewDat, TxRqst & IntPnd */
8339a7ed 512 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
086b5650
T		 513 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
514 PCH_IF_MCONT_TXRQXT);
8339a7ed 515 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask);
b21d18b5
MO		 516 }
517}
518
b21d18b5
MO		 519static void pch_can_reset(struct pch_can_priv *priv)
520{
521 /* write to sw reset register */
522 iowrite32(1, &priv->regs->srst);
523 iowrite32(0, &priv->regs->srst);
524}
525
526static void pch_can_error(struct net_device *ndev, u32 status)
527{
528 struct sk_buff *skb;
529 struct pch_can_priv *priv = netdev_priv(ndev);
530 struct can_frame *cf;
d68f6837 531 u32 errc, lec;
b21d18b5
MO		 532 struct net_device_stats *stats = &(priv->ndev->stats);
533 enum can_state state = priv->can.state;
534
535 skb = alloc_can_err_skb(ndev, &cf);
536 if (!skb)
537 return;
538
539 if (status & PCH_BUS_OFF) {
8339a7ed
T		 540 pch_can_set_tx_all(priv, 0);
541 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 542 state = CAN_STATE_BUS_OFF;
543 cf->can_id |= CAN_ERR_BUSOFF;
544 can_bus_off(ndev);
545 pch_can_set_run_mode(priv, PCH_CAN_RUN);
546 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
547 }
548
549 /* Warning interrupt. */
550 if (status & PCH_EWARN) {
551 state = CAN_STATE_ERROR_WARNING;
552 priv->can.can_stats.error_warning++;
553 cf->can_id |= CAN_ERR_CRTL;
554 errc = ioread32(&priv->regs->errc);
086b5650 555 if (((errc & PCH_REC) >> 8) > 96)
b21d18b5 556 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
086b5650 557 if ((errc & PCH_TEC) > 96)
b21d18b5
MO		 558 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
559 dev_warn(&ndev->dev,
560 "%s -> Error Counter is more than 96.\n", __func__);
561 }
562 /* Error passive interrupt. */
563 if (status & PCH_EPASSIV) {
564 priv->can.can_stats.error_passive++;
565 state = CAN_STATE_ERROR_PASSIVE;
566 cf->can_id |= CAN_ERR_CRTL;
567 errc = ioread32(&priv->regs->errc);
086b5650 568 if (((errc & PCH_REC) >> 8) > 127)
b21d18b5 569 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
086b5650 570 if ((errc & PCH_TEC) > 127)
b21d18b5
MO		 571 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
572 dev_err(&ndev->dev,
573 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
574 }
575
d68f6837
T		 576 lec = status & PCH_LEC_ALL;
577 switch (lec) {
578 case PCH_STUF_ERR:
579 cf->data[2] |= CAN_ERR_PROT_STUFF;
b21d18b5
MO		 580 priv->can.can_stats.bus_error++;
581 stats->rx_errors++;
d68f6837
T		 582 break;
583 case PCH_FORM_ERR:
584 cf->data[2] |= CAN_ERR_PROT_FORM;
585 priv->can.can_stats.bus_error++;
586 stats->rx_errors++;
587 break;
588 case PCH_ACK_ERR:
589 cf->can_id |= CAN_ERR_ACK;
590 priv->can.can_stats.bus_error++;
591 stats->rx_errors++;
592 break;
593 case PCH_BIT1_ERR:
594 case PCH_BIT0_ERR:
595 cf->data[2] |= CAN_ERR_PROT_BIT;
596 priv->can.can_stats.bus_error++;
597 stats->rx_errors++;
598 break;
599 case PCH_CRC_ERR:
600 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
601 CAN_ERR_PROT_LOC_CRC_DEL;
602 priv->can.can_stats.bus_error++;
603 stats->rx_errors++;
604 break;
605 case PCH_LEC_ALL: /* Written by CPU. No error status */
606 break;
b21d18b5
MO		 607 }
608
609 priv->can.state = state;
610 netif_rx(skb);
611
612 stats->rx_packets++;
613 stats->rx_bytes += cf->can_dlc;
614}
615
616static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
617{
618 struct net_device *ndev = (struct net_device *)dev_id;
619 struct pch_can_priv *priv = netdev_priv(ndev);
620
621 pch_can_set_int_enables(priv, PCH_CAN_NONE);
622
623 napi_schedule(&priv->napi);
624
625 return IRQ_HANDLED;
626}
627
1d5b4b27
T		 628static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
629{
630 if (obj_id < PCH_FIFO_THRESH) {
631 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
632 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
633
634 /* Clearing the Dir bit. */
635 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
636
637 /* Clearing NewDat & IntPnd */
638 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
639 PCH_IF_MCONT_INTPND);
640 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
641 } else if (obj_id > PCH_FIFO_THRESH) {
642 pch_can_int_clr(priv, obj_id);
643 } else if (obj_id == PCH_FIFO_THRESH) {
644 int cnt;
645 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
646 pch_can_int_clr(priv, cnt + 1);
647 }
648}
649
650static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
651{
652 struct pch_can_priv *priv = netdev_priv(ndev);
653 struct net_device_stats *stats = &(priv->ndev->stats);
654 struct sk_buff *skb;
655 struct can_frame *cf;
656
657 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
658 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
659 PCH_IF_MCONT_MSGLOST);
660 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
661 &priv->regs->ifregs[0].cmask);
662 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
663
664 skb = alloc_can_err_skb(ndev, &cf);
665 if (!skb)
666 return;
667
668 cf->can_id |= CAN_ERR_CRTL;
669 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
670 stats->rx_over_errors++;
671 stats->rx_errors++;
672
673 netif_receive_skb(skb);
674}
675
676static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
b21d18b5
MO		 677{
678 u32 reg;
679 canid_t id;
b21d18b5
MO		 680 int rcv_pkts = 0;
681 struct sk_buff *skb;
682 struct can_frame *cf;
683 struct pch_can_priv *priv = netdev_priv(ndev);
684 struct net_device_stats *stats = &(priv->ndev->stats);
1d5b4b27
T		 685 int i;
686 u32 id2;
8ac9702b 687 u16 data_reg;
b21d18b5 688
1d5b4b27
T		 689 do {
690 /* Reading the messsage object from the Message RAM */
691 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
692 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_num);
b21d18b5 693
1d5b4b27
T		 694 /* Reading the MCONT register. */
695 reg = ioread32(&priv->regs->ifregs[0].mcont);
696
697 if (reg & PCH_IF_MCONT_EOB)
698 break;
b21d18b5 699
b21d18b5 700 /* If MsgLost bit set. */
086b5650 701 if (reg & PCH_IF_MCONT_MSGLOST) {
1d5b4b27 702 pch_can_rx_msg_lost(ndev, obj_num);
b21d18b5 703 rcv_pkts++;
1d5b4b27
T		 704 quota--;
705 obj_num++;
706 continue;
707 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
708 obj_num++;
709 continue;
b21d18b5 710 }
b21d18b5
MO		 711
712 skb = alloc_can_skb(priv->ndev, &cf);
713 if (!skb)
714 return -ENOMEM;
715
716 /* Get Received data */
1d5b4b27
T		 717 id2 = ioread32(&priv->regs->ifregs[0].id2);
718 if (id2 & PCH_ID2_XTD) {
8339a7ed 719 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
1d5b4b27
T		 720 id |= (((id2) & 0x1fff) << 16);
721 cf->can_id = id | CAN_EFF_FLAG;
b21d18b5 722 } else {
1d5b4b27
T		 723 id = (id2 >> 2) & CAN_SFF_MASK;
724 cf->can_id = id;
b21d18b5
MO		 725 }
726
1d5b4b27 727 if (id2 & PCH_ID2_DIR)
b21d18b5 728 cf->can_id |= CAN_RTR_FLAG;
1d5b4b27
T		 729
730 cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
731 ifregs[0].mcont)) & 0xF);
b21d18b5 732
8ac9702b
T		 733 for (i = 0; i < cf->can_dlc; i += 2) {
734 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
735 cf->data[i] = data_reg;
736 cf->data[i + 1] = data_reg >> 8;
b21d18b5
MO		 737 }
738
739 netif_receive_skb(skb);
740 rcv_pkts++;
741 stats->rx_packets++;
1d5b4b27 742 quota--;
b21d18b5
MO		 743 stats->rx_bytes += cf->can_dlc;
744
1d5b4b27
T		 745 pch_fifo_thresh(priv, obj_num);
746 obj_num++;
747 } while (quota > 0);
b21d18b5
MO		 748
749 return rcv_pkts;
750}
e489cceb
T		 751
752static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
b21d18b5 753{
b21d18b5
MO		 754 struct pch_can_priv *priv = netdev_priv(ndev);
755 struct net_device_stats *stats = &(priv->ndev->stats);
756 u32 dlc;
e489cceb
T		 757
758 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
759 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
760 &priv->regs->ifregs[1].cmask);
761 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat);
762 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
763 PCH_IF_MCONT_DLC);
764 stats->tx_bytes += dlc;
765 stats->tx_packets++;
766 if (int_stat == PCH_TX_OBJ_END)
767 netif_wake_queue(ndev);
768}
769
770static int pch_can_rx_poll(struct napi_struct *napi, int quota)
771{
772 struct net_device *ndev = napi->dev;
773 struct pch_can_priv *priv = netdev_priv(ndev);
b21d18b5
MO		 774 u32 int_stat;
775 int rcv_pkts = 0;
776 u32 reg_stat;
b21d18b5
MO		 777
778 int_stat = pch_can_int_pending(priv);
779 if (!int_stat)
e489cceb 780 goto end;
b21d18b5 781
e489cceb 782 if ((int_stat == PCH_STATUS_INT) && (quota > 0)) {
b21d18b5
MO		 783 reg_stat = ioread32(&priv->regs->stat);
784 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
e489cceb
T		 785 if (reg_stat & PCH_BUS_OFF ||
786 (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
b21d18b5 787 pch_can_error(ndev, reg_stat);
e489cceb
T		 788 quota--;
789 }
b21d18b5
MO		 790 }
791
e489cceb 792 if (reg_stat & PCH_TX_OK)
b21d18b5 793 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
b21d18b5
MO		 794
795 if (reg_stat & PCH_RX_OK)
796 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
797
798 int_stat = pch_can_int_pending(priv);
b21d18b5
MO		 799 }
800
e489cceb
T		 801 if (quota == 0)
802 goto end;
803
15ffc8fd 804 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
1d5b4b27 805 rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
e489cceb
T		 806 quota -= rcv_pkts;
807 if (quota < 0)
808 goto end;
15ffc8fd
T		 809 } else if ((int_stat >= PCH_TX_OBJ_START) &&
810 (int_stat <= PCH_TX_OBJ_END)) {
811 /* Handle transmission interrupt */
e489cceb 812 pch_can_tx_complete(ndev, int_stat);
b21d18b5
MO		 813 }
814
e489cceb 815end:
b21d18b5
MO		 816 napi_complete(napi);
817 pch_can_set_int_enables(priv, PCH_CAN_ALL);
818
819 return rcv_pkts;
820}
821
822static int pch_set_bittiming(struct net_device *ndev)
823{
824 struct pch_can_priv *priv = netdev_priv(ndev);
825 const struct can_bittiming *bt = &priv->can.bittiming;
826 u32 canbit;
827 u32 bepe;
828 u32 brp;
829
830 /* Setting the CCE bit for accessing the Can Timing register. */
086b5650 831 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 832
833 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
086b5650
T		 834 canbit = brp & PCH_MSK_BITT_BRP;
835 canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
836 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
837 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
838 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
b21d18b5
MO		 839 iowrite32(canbit, &priv->regs->bitt);
840 iowrite32(bepe, &priv->regs->brpe);
086b5650 841 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 842
843 return 0;
844}
845
846static void pch_can_start(struct net_device *ndev)
847{
848 struct pch_can_priv *priv = netdev_priv(ndev);
849
850 if (priv->can.state != CAN_STATE_STOPPED)
851 pch_can_reset(priv);
852
853 pch_set_bittiming(ndev);
854 pch_can_set_optmode(priv);
855
8339a7ed
T		 856 pch_can_set_tx_all(priv, 1);
857 pch_can_set_rx_all(priv, 1);
b21d18b5
MO		 858
859 /* Setting the CAN to run mode. */
860 pch_can_set_run_mode(priv, PCH_CAN_RUN);
861
862 priv->can.state = CAN_STATE_ERROR_ACTIVE;
863
864 return;
865}
866
867static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
868{
869 int ret = 0;
870
871 switch (mode) {
872 case CAN_MODE_START:
873 pch_can_start(ndev);
874 netif_wake_queue(ndev);
875 break;
876 default:
877 ret = -EOPNOTSUPP;
878 break;
879 }
880
881 return ret;
882}
883
884static int pch_can_open(struct net_device *ndev)
885{
886 struct pch_can_priv *priv = netdev_priv(ndev);
887 int retval;
888
889 retval = pci_enable_msi(priv->dev);
890 if (retval) {
891 dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
892 priv->use_msi = 0;
893 } else {
894 dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
895 priv->use_msi = 1;
896 }
897
898 /* Regsitering the interrupt. */
899 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
900 ndev->name, ndev);
901 if (retval) {
902 dev_err(&ndev->dev, "request_irq failed.\n");
903 goto req_irq_err;
904 }
905
906 /* Open common can device */
907 retval = open_candev(ndev);
908 if (retval) {
909 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
910 goto err_open_candev;
911 }
912
913 pch_can_init(priv);
914 pch_can_start(ndev);
915 napi_enable(&priv->napi);
916 netif_start_queue(ndev);
917
918 return 0;
919
920err_open_candev:
921 free_irq(priv->dev->irq, ndev);
922req_irq_err:
923 if (priv->use_msi)
924 pci_disable_msi(priv->dev);
925
926 pch_can_release(priv);
927
928 return retval;
929}
930
931static int pch_close(struct net_device *ndev)
932{
933 struct pch_can_priv *priv = netdev_priv(ndev);
934
935 netif_stop_queue(ndev);
936 napi_disable(&priv->napi);
937 pch_can_release(priv);
938 free_irq(priv->dev->irq, ndev);
939 if (priv->use_msi)
940 pci_disable_msi(priv->dev);
941 close_candev(ndev);
942 priv->can.state = CAN_STATE_STOPPED;
943 return 0;
944}
945
b21d18b5
MO		 946static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
947{
b21d18b5
MO		 948 struct pch_can_priv *priv = netdev_priv(ndev);
949 struct can_frame *cf = (struct can_frame *)skb->data;
950 int tx_buffer_avail = 0;
8ac9702b 951 int i;
b21d18b5
MO		 952
953 if (can_dropped_invalid_skb(ndev, skb))
954 return NETDEV_TX_OK;
955
76d94b23
T		 956 if (priv->tx_obj == PCH_TX_OBJ_END) {
957 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
958 netif_stop_queue(ndev);
b21d18b5 959
76d94b23
T		 960 tx_buffer_avail = priv->tx_obj;
961 priv->tx_obj = PCH_TX_OBJ_START;
b21d18b5
MO		 962 } else {
963 tx_buffer_avail = priv->tx_obj;
76d94b23 964 priv->tx_obj++;
b21d18b5 965 }
b21d18b5 966
b21d18b5 967 /* Reading the Msg Obj from the Msg RAM to the Interface register. */
8339a7ed
T		 968 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
969 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
b21d18b5
MO		 970
971 /* Setting the CMASK register. */
8339a7ed 972 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
b21d18b5
MO		 973
974 /* If ID extended is set. */
8339a7ed
T		 975 pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff);
976 pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD);
b21d18b5 977 if (cf->can_id & CAN_EFF_FLAG) {
8339a7ed
T		 978 pch_can_bit_set(&priv->regs->ifregs[1].id1,
979 cf->can_id & 0xffff);
980 pch_can_bit_set(&priv->regs->ifregs[1].id2,
086b5650 981 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD);
b21d18b5 982 } else {
8339a7ed
T		 983 pch_can_bit_set(&priv->regs->ifregs[1].id1, 0);
984 pch_can_bit_set(&priv->regs->ifregs[1].id2,
b21d18b5
MO		 985 (cf->can_id & CAN_SFF_MASK) << 2);
986 }
987
988 /* If remote frame has to be transmitted.. */
989 if (cf->can_id & CAN_RTR_FLAG)
8339a7ed 990 pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR);
b21d18b5 991
8ac9702b
T		 992 /* Copy data to register */
993 for (i = 0; i < cf->can_dlc; i += 2) {
994 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
995 &priv->regs->ifregs[1].data[i / 2]);
b21d18b5
MO		 996 }
997
15ffc8fd 998 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1);
b21d18b5
MO		 999
1000 /* Updating the size of the data. */
8339a7ed
T		 1001 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f);
1002 pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc);
b21d18b5
MO		 1003
1004 /* Clearing IntPend, NewDat & TxRqst */
8339a7ed 1005 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
086b5650
T		 1006 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
1007 PCH_IF_MCONT_TXRQXT);
b21d18b5
MO		 1008
1009 /* Setting NewDat, TxRqst bits */
8339a7ed 1010 pch_can_bit_set(&priv->regs->ifregs[1].mcont,
086b5650 1011 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
b21d18b5 1012
8339a7ed 1013 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
b21d18b5 1014
b21d18b5
MO		 1015 return NETDEV_TX_OK;
1016}
1017
1018static const struct net_device_ops pch_can_netdev_ops = {
1019 .ndo_open = pch_can_open,
1020 .ndo_stop = pch_close,
1021 .ndo_start_xmit = pch_xmit,
1022};
1023
1024static void __devexit pch_can_remove(struct pci_dev *pdev)
1025{
1026 struct net_device *ndev = pci_get_drvdata(pdev);
1027 struct pch_can_priv *priv = netdev_priv(ndev);
1028
1029 unregister_candev(priv->ndev);
1030 free_candev(priv->ndev);
1031 pci_iounmap(pdev, priv->regs);
1032 pci_release_regions(pdev);
1033 pci_disable_device(pdev);
1034 pci_set_drvdata(pdev, NULL);
1035 pch_can_reset(priv);
1036}
1037
1038#ifdef CONFIG_PM
7f2bc50e
T		 1039static void pch_can_set_int_custom(struct pch_can_priv *priv)
1040{
1041 /* Clearing the IE, SIE and EIE bits of Can control register. */
1042 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
1043
1044 /* Appropriately setting them. */
1045 pch_can_bit_set(&priv->regs->cont,
1046 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
1047}
1048
1049/* This function retrieves interrupt enabled for the CAN device. */
1050static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
1051{
1052 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
1053 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
1054}
1055
1056static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
1057 enum pch_ifreg dir)
1058{
1059 u32 ie, enable;
1060
1061 if (dir)
1062 ie = PCH_IF_MCONT_RXIE;
1063 else
1064 ie = PCH_IF_MCONT_TXIE;
1065
1066 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
1067 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
1068
1069 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
1070 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
1071 enable = 1;
1072 } else {
1073 enable = 0;
1074 }
1075 return enable;
1076}
1077
1078static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
1079 u32 buffer_num, u32 set)
1080{
1081 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1082 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
1083 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1084 &priv->regs->ifregs[0].cmask);
1085 if (set == PCH_ENABLE)
1086 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1087 PCH_IF_MCONT_EOB);
1088 else
1089 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1090
1091 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
1092}
1093
1094static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
1095 u32 buffer_num, u32 *link)
1096{
1097 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1098 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
1099
1100 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
1101 *link = PCH_DISABLE;
1102 else
1103 *link = PCH_ENABLE;
1104}
1105
1106static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1107{
1108 return (ioread32(&priv->regs->treq1) & 0xffff) |
1109 ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
1110}
1111
b21d18b5
MO		 1112static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1113{
1114 int i; /* Counter variable. */
1115 int retval; /* Return value. */
1116 u32 buf_stat; /* Variable for reading the transmit buffer status. */
1117 u32 counter = 0xFFFFFF;
1118
1119 struct net_device *dev = pci_get_drvdata(pdev);
1120 struct pch_can_priv *priv = netdev_priv(dev);
1121
1122 /* Stop the CAN controller */
1123 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1124
1125 /* Indicate that we are aboutto/in suspend */
1126 priv->can.state = CAN_STATE_SLEEPING;
1127
1128 /* Waiting for all transmission to complete. */
1129 while (counter) {
1130 buf_stat = pch_can_get_buffer_status(priv);
1131 if (!buf_stat)
1132 break;
1133 counter--;
1134 udelay(1);
1135 }
1136 if (!counter)
1137 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1138
1139 /* Save interrupt configuration and then disable them */
1140 pch_can_get_int_enables(priv, &(priv->int_enables));
1141 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1142
1143 /* Save Tx buffer enable state */
15ffc8fd
T		 1144 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1145 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG);
b21d18b5
MO		 1146
1147 /* Disable all Transmit buffers */
8339a7ed 1148 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 1149
1150 /* Save Rx buffer enable state */
15ffc8fd
T		 1151 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1152 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG);
1153 pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]);
b21d18b5
MO		 1154 }
1155
1156 /* Disable all Receive buffers */
8339a7ed 1157 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 1158 retval = pci_save_state(pdev);
1159 if (retval) {
1160 dev_err(&pdev->dev, "pci_save_state failed.\n");
1161 } else {
1162 pci_enable_wake(pdev, PCI_D3hot, 0);
1163 pci_disable_device(pdev);
1164 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1165 }
1166
1167 return retval;
1168}
1169
1170static int pch_can_resume(struct pci_dev *pdev)
1171{
1172 int i; /* Counter variable. */
1173 int retval; /* Return variable. */
1174 struct net_device *dev = pci_get_drvdata(pdev);
1175 struct pch_can_priv *priv = netdev_priv(dev);
1176
1177 pci_set_power_state(pdev, PCI_D0);
1178 pci_restore_state(pdev);
1179 retval = pci_enable_device(pdev);
1180 if (retval) {
1181 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1182 return retval;
1183 }
1184
1185 pci_enable_wake(pdev, PCI_D3hot, 0);
1186
1187 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1188
1189 /* Disabling all interrupts. */
1190 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1191
1192 /* Setting the CAN device in Stop Mode. */
1193 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1194
1195 /* Configuring the transmit and receive buffers. */
1196 pch_can_config_rx_tx_buffers(priv);
1197
1198 /* Restore the CAN state */
1199 pch_set_bittiming(dev);
1200
1201 /* Listen/Active */
1202 pch_can_set_optmode(priv);
1203
1204 /* Enabling the transmit buffer. */
15ffc8fd
T		 1205 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1206 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG);
b21d18b5
MO		 1207
1208 /* Configuring the receive buffer and enabling them. */
15ffc8fd
T		 1209 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1210 /* Restore buffer link */
1211 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
b21d18b5 1212
15ffc8fd
T		 1213 /* Restore buffer enables */
1214 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG);
b21d18b5
MO		 1215 }
1216
1217 /* Enable CAN Interrupts */
1218 pch_can_set_int_custom(priv);
1219
1220 /* Restore Run Mode */
1221 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1222
1223 return retval;
1224}
1225#else
1226#define pch_can_suspend NULL
1227#define pch_can_resume NULL
1228#endif
1229
1230static int pch_can_get_berr_counter(const struct net_device *dev,
1231 struct can_berr_counter *bec)
1232{
1233 struct pch_can_priv *priv = netdev_priv(dev);
1234
086b5650
T		 1235 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC;
1236 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8;
b21d18b5
MO		 1237
1238 return 0;
1239}
1240
1241static int __devinit pch_can_probe(struct pci_dev *pdev,
1242 const struct pci_device_id *id)
1243{
1244 struct net_device *ndev;
1245 struct pch_can_priv *priv;
1246 int rc;
b21d18b5
MO		 1247 void __iomem *addr;
1248
1249 rc = pci_enable_device(pdev);
1250 if (rc) {
1251 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1252 goto probe_exit_endev;
1253 }
1254
1255 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1256 if (rc) {
1257 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1258 goto probe_exit_pcireq;
1259 }
1260
1261 addr = pci_iomap(pdev, 1, 0);
1262 if (!addr) {
1263 rc = -EIO;
1264 dev_err(&pdev->dev, "Failed pci_iomap\n");
1265 goto probe_exit_ipmap;
1266 }
1267
15ffc8fd 1268 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
b21d18b5
MO		 1269 if (!ndev) {
1270 rc = -ENOMEM;
1271 dev_err(&pdev->dev, "Failed alloc_candev\n");
1272 goto probe_exit_alloc_candev;
1273 }
1274
1275 priv = netdev_priv(ndev);
1276 priv->ndev = ndev;
1277 priv->regs = addr;
1278 priv->dev = pdev;
1279 priv->can.bittiming_const = &pch_can_bittiming_const;
1280 priv->can.do_set_mode = pch_can_do_set_mode;
1281 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1282 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1283 CAN_CTRLMODE_LOOPBACK;
15ffc8fd 1284 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
b21d18b5
MO		 1285
1286 ndev->irq = pdev->irq;
1287 ndev->flags |= IFF_ECHO;
1288
1289 pci_set_drvdata(pdev, ndev);
1290 SET_NETDEV_DEV(ndev, &pdev->dev);
1291 ndev->netdev_ops = &pch_can_netdev_ops;
b21d18b5 1292 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
b21d18b5 1293
15ffc8fd 1294 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END);
b21d18b5
MO		 1295
1296 rc = register_candev(ndev);
1297 if (rc) {
1298 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1299 goto probe_exit_reg_candev;
1300 }
1301
1302 return 0;
1303
1304probe_exit_reg_candev:
1305 free_candev(ndev);
1306probe_exit_alloc_candev:
1307 pci_iounmap(pdev, addr);
1308probe_exit_ipmap:
1309 pci_release_regions(pdev);
1310probe_exit_pcireq:
1311 pci_disable_device(pdev);
1312probe_exit_endev:
1313 return rc;
1314}
1315
bdfa3d8f 1316static struct pci_driver pch_can_pci_driver = {
b21d18b5
MO		 1317 .name = "pch_can",
1318 .id_table = pch_pci_tbl,
1319 .probe = pch_can_probe,
1320 .remove = __devexit_p(pch_can_remove),
1321 .suspend = pch_can_suspend,
1322 .resume = pch_can_resume,
1323};
1324
1325static int __init pch_can_pci_init(void)
1326{
bdfa3d8f 1327 return pci_register_driver(&pch_can_pci_driver);
b21d18b5
MO		 1328}
1329module_init(pch_can_pci_init);
1330
1331static void __exit pch_can_pci_exit(void)
1332{
bdfa3d8f 1333 pci_unregister_driver(&pch_can_pci_driver);
b21d18b5
MO		 1334}
1335module_exit(pch_can_pci_exit);
1336
1337MODULE_DESCRIPTION("Controller Area Network Driver");
1338MODULE_LICENSE("GPL v2");
1339MODULE_VERSION("0.94");
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