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b21d18b5 MO |
1 | /* |
2 | * Copyright (C) 1999 - 2010 Intel Corporation. | |
74b51278 | 3 | * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD. |
b21d18b5 MO |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
05780d98 | 15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
b21d18b5 MO |
16 | */ |
17 | ||
18 | #include <linux/interrupt.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/pci.h> | |
b21d18b5 MO |
24 | #include <linux/kernel.h> |
25 | #include <linux/types.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/netdevice.h> | |
28 | #include <linux/skbuff.h> | |
29 | #include <linux/can.h> | |
30 | #include <linux/can/dev.h> | |
31 | #include <linux/can/error.h> | |
32 | ||
0a80410d T |
33 | #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ |
34 | #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ | |
35 | #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) | |
36 | #define PCH_CTRL_CCE BIT(6) | |
37 | #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ | |
38 | #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ | |
39 | #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ | |
40 | ||
086b5650 T |
41 | #define PCH_CMASK_RX_TX_SET 0x00f3 |
42 | #define PCH_CMASK_RX_TX_GET 0x0073 | |
43 | #define PCH_CMASK_ALL 0xff | |
0a80410d T |
44 | #define PCH_CMASK_NEWDAT BIT(2) |
45 | #define PCH_CMASK_CLRINTPND BIT(3) | |
46 | #define PCH_CMASK_CTRL BIT(4) | |
47 | #define PCH_CMASK_ARB BIT(5) | |
48 | #define PCH_CMASK_MASK BIT(6) | |
49 | #define PCH_CMASK_RDWR BIT(7) | |
50 | #define PCH_IF_MCONT_NEWDAT BIT(15) | |
51 | #define PCH_IF_MCONT_MSGLOST BIT(14) | |
52 | #define PCH_IF_MCONT_INTPND BIT(13) | |
53 | #define PCH_IF_MCONT_UMASK BIT(12) | |
54 | #define PCH_IF_MCONT_TXIE BIT(11) | |
55 | #define PCH_IF_MCONT_RXIE BIT(10) | |
56 | #define PCH_IF_MCONT_RMTEN BIT(9) | |
57 | #define PCH_IF_MCONT_TXRQXT BIT(8) | |
58 | #define PCH_IF_MCONT_EOB BIT(7) | |
59 | #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) | |
60 | #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) | |
61 | #define PCH_ID2_DIR BIT(13) | |
62 | #define PCH_ID2_XTD BIT(14) | |
63 | #define PCH_ID_MSGVAL BIT(15) | |
64 | #define PCH_IF_CREQ_BUSY BIT(15) | |
086b5650 T |
65 | |
66 | #define PCH_STATUS_INT 0x8000 | |
44b0052c | 67 | #define PCH_RP 0x00008000 |
086b5650 T |
68 | #define PCH_REC 0x00007f00 |
69 | #define PCH_TEC 0x000000ff | |
b21d18b5 | 70 | |
0a80410d T |
71 | #define PCH_TX_OK BIT(3) |
72 | #define PCH_RX_OK BIT(4) | |
73 | #define PCH_EPASSIV BIT(5) | |
74 | #define PCH_EWARN BIT(6) | |
75 | #define PCH_BUS_OFF BIT(7) | |
b21d18b5 MO |
76 | |
77 | /* bit position of certain controller bits. */ | |
bd58cbc3 T |
78 | #define PCH_BIT_BRP_SHIFT 0 |
79 | #define PCH_BIT_SJW_SHIFT 6 | |
80 | #define PCH_BIT_TSEG1_SHIFT 8 | |
81 | #define PCH_BIT_TSEG2_SHIFT 12 | |
82 | #define PCH_BIT_BRPE_BRPE_SHIFT 6 | |
83 | ||
086b5650 T |
84 | #define PCH_MSK_BITT_BRP 0x3f |
85 | #define PCH_MSK_BRPE_BRPE 0x3c0 | |
86 | #define PCH_MSK_CTRL_IE_SIE_EIE 0x07 | |
87 | #define PCH_COUNTER_LIMIT 10 | |
b21d18b5 MO |
88 | |
89 | #define PCH_CAN_CLK 50000000 /* 50MHz */ | |
90 | ||
9388b166 T |
91 | /* |
92 | * Define the number of message object. | |
b21d18b5 | 93 | * PCH CAN communications are done via Message RAM. |
9388b166 T |
94 | * The Message RAM consists of 32 message objects. |
95 | */ | |
15ffc8fd T |
96 | #define PCH_RX_OBJ_NUM 26 |
97 | #define PCH_TX_OBJ_NUM 6 | |
98 | #define PCH_RX_OBJ_START 1 | |
99 | #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM | |
100 | #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) | |
101 | #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) | |
b21d18b5 MO |
102 | |
103 | #define PCH_FIFO_THRESH 16 | |
104 | ||
76d94b23 T |
105 | /* TxRqst2 show status of MsgObjNo.17~32 */ |
106 | #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\ | |
107 | (PCH_RX_OBJ_END - 16)) | |
108 | ||
8339a7ed T |
109 | enum pch_ifreg { |
110 | PCH_RX_IFREG, | |
111 | PCH_TX_IFREG, | |
112 | }; | |
113 | ||
d68f6837 T |
114 | enum pch_can_err { |
115 | PCH_STUF_ERR = 1, | |
116 | PCH_FORM_ERR, | |
117 | PCH_ACK_ERR, | |
118 | PCH_BIT1_ERR, | |
119 | PCH_BIT0_ERR, | |
120 | PCH_CRC_ERR, | |
121 | PCH_LEC_ALL, | |
122 | }; | |
123 | ||
b21d18b5 MO |
124 | enum pch_can_mode { |
125 | PCH_CAN_ENABLE, | |
126 | PCH_CAN_DISABLE, | |
127 | PCH_CAN_ALL, | |
128 | PCH_CAN_NONE, | |
129 | PCH_CAN_STOP, | |
9388b166 | 130 | PCH_CAN_RUN, |
b21d18b5 MO |
131 | }; |
132 | ||
8339a7ed T |
133 | struct pch_can_if_regs { |
134 | u32 creq; | |
135 | u32 cmask; | |
136 | u32 mask1; | |
137 | u32 mask2; | |
138 | u32 id1; | |
139 | u32 id2; | |
140 | u32 mcont; | |
8ac9702b | 141 | u32 data[4]; |
8339a7ed T |
142 | u32 rsv[13]; |
143 | }; | |
144 | ||
b21d18b5 MO |
145 | struct pch_can_regs { |
146 | u32 cont; | |
147 | u32 stat; | |
148 | u32 errc; | |
149 | u32 bitt; | |
150 | u32 intr; | |
151 | u32 opt; | |
152 | u32 brpe; | |
8339a7ed T |
153 | u32 reserve; |
154 | struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ | |
155 | u32 reserve1[8]; | |
b21d18b5 MO |
156 | u32 treq1; |
157 | u32 treq2; | |
8339a7ed T |
158 | u32 reserve2[6]; |
159 | u32 data1; | |
160 | u32 data2; | |
161 | u32 reserve3[6]; | |
162 | u32 canipend1; | |
163 | u32 canipend2; | |
164 | u32 reserve4[6]; | |
165 | u32 canmval1; | |
166 | u32 canmval2; | |
167 | u32 reserve5[37]; | |
b21d18b5 MO |
168 | u32 srst; |
169 | }; | |
170 | ||
171 | struct pch_can_priv { | |
172 | struct can_priv can; | |
b21d18b5 | 173 | struct pci_dev *dev; |
bd58cbc3 T |
174 | u32 tx_enable[PCH_TX_OBJ_END]; |
175 | u32 rx_enable[PCH_TX_OBJ_END]; | |
176 | u32 rx_link[PCH_TX_OBJ_END]; | |
177 | u32 int_enables; | |
b21d18b5 | 178 | struct net_device *ndev; |
b21d18b5 MO |
179 | struct pch_can_regs __iomem *regs; |
180 | struct napi_struct napi; | |
bd58cbc3 T |
181 | int tx_obj; /* Point next Tx Obj index */ |
182 | int use_msi; | |
b21d18b5 MO |
183 | }; |
184 | ||
194b9a4c | 185 | static const struct can_bittiming_const pch_can_bittiming_const = { |
b21d18b5 | 186 | .name = KBUILD_MODNAME, |
ebc02e9c | 187 | .tseg1_min = 2, |
b21d18b5 | 188 | .tseg1_max = 16, |
ebc02e9c | 189 | .tseg2_min = 1, |
b21d18b5 MO |
190 | .tseg2_max = 8, |
191 | .sjw_max = 4, | |
192 | .brp_min = 1, | |
193 | .brp_max = 1024, /* 6bit + extended 4bit */ | |
194 | .brp_inc = 1, | |
195 | }; | |
196 | ||
9baa3c34 | 197 | static const struct pci_device_id pch_pci_tbl[] = { |
b21d18b5 MO |
198 | {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, |
199 | {0,} | |
200 | }; | |
201 | MODULE_DEVICE_TABLE(pci, pch_pci_tbl); | |
202 | ||
526de53c | 203 | static inline void pch_can_bit_set(void __iomem *addr, u32 mask) |
b21d18b5 MO |
204 | { |
205 | iowrite32(ioread32(addr) | mask, addr); | |
206 | } | |
207 | ||
526de53c | 208 | static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) |
b21d18b5 MO |
209 | { |
210 | iowrite32(ioread32(addr) & ~mask, addr); | |
211 | } | |
212 | ||
213 | static void pch_can_set_run_mode(struct pch_can_priv *priv, | |
214 | enum pch_can_mode mode) | |
215 | { | |
216 | switch (mode) { | |
217 | case PCH_CAN_RUN: | |
086b5650 | 218 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); |
b21d18b5 MO |
219 | break; |
220 | ||
221 | case PCH_CAN_STOP: | |
086b5650 | 222 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); |
b21d18b5 MO |
223 | break; |
224 | ||
225 | default: | |
435b4efe | 226 | netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__); |
b21d18b5 MO |
227 | break; |
228 | } | |
229 | } | |
230 | ||
231 | static void pch_can_set_optmode(struct pch_can_priv *priv) | |
232 | { | |
233 | u32 reg_val = ioread32(&priv->regs->opt); | |
234 | ||
235 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
086b5650 | 236 | reg_val |= PCH_OPT_SILENT; |
b21d18b5 MO |
237 | |
238 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
086b5650 | 239 | reg_val |= PCH_OPT_LBACK; |
b21d18b5 | 240 | |
086b5650 | 241 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); |
b21d18b5 MO |
242 | iowrite32(reg_val, &priv->regs->opt); |
243 | } | |
244 | ||
bd58cbc3 T |
245 | static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num) |
246 | { | |
247 | int counter = PCH_COUNTER_LIMIT; | |
248 | u32 ifx_creq; | |
249 | ||
250 | iowrite32(num, creq_addr); | |
251 | while (counter) { | |
252 | ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; | |
253 | if (!ifx_creq) | |
254 | break; | |
255 | counter--; | |
256 | udelay(1); | |
257 | } | |
258 | if (!counter) | |
259 | pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); | |
260 | } | |
261 | ||
b21d18b5 MO |
262 | static void pch_can_set_int_enables(struct pch_can_priv *priv, |
263 | enum pch_can_mode interrupt_no) | |
264 | { | |
265 | switch (interrupt_no) { | |
b21d18b5 | 266 | case PCH_CAN_DISABLE: |
086b5650 | 267 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); |
b21d18b5 MO |
268 | break; |
269 | ||
270 | case PCH_CAN_ALL: | |
086b5650 | 271 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
b21d18b5 MO |
272 | break; |
273 | ||
274 | case PCH_CAN_NONE: | |
086b5650 | 275 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
b21d18b5 MO |
276 | break; |
277 | ||
278 | default: | |
435b4efe | 279 | netdev_err(priv->ndev, "Invalid interrupt number.\n"); |
b21d18b5 MO |
280 | break; |
281 | } | |
282 | } | |
283 | ||
8339a7ed | 284 | static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, |
bd58cbc3 | 285 | int set, enum pch_ifreg dir) |
b21d18b5 | 286 | { |
8339a7ed T |
287 | u32 ie; |
288 | ||
289 | if (dir) | |
290 | ie = PCH_IF_MCONT_TXIE; | |
291 | else | |
292 | ie = PCH_IF_MCONT_RXIE; | |
b21d18b5 | 293 | |
c7551456 | 294 | /* Reading the Msg buffer from Message RAM to IF1/2 registers. */ |
8339a7ed | 295 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
bd58cbc3 | 296 | pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); |
b21d18b5 | 297 | |
9388b166 | 298 | /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */ |
086b5650 | 299 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
8339a7ed | 300 | &priv->regs->ifregs[dir].cmask); |
b21d18b5 | 301 | |
bd58cbc3 | 302 | if (set) { |
9388b166 | 303 | /* Setting the MsgVal and RxIE/TxIE bits */ |
8339a7ed T |
304 | pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); |
305 | pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); | |
bd58cbc3 | 306 | } else { |
9388b166 | 307 | /* Clearing the MsgVal and RxIE/TxIE bits */ |
8339a7ed T |
308 | pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); |
309 | pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); | |
b21d18b5 MO |
310 | } |
311 | ||
bd58cbc3 | 312 | pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); |
b21d18b5 MO |
313 | } |
314 | ||
bd58cbc3 | 315 | static void pch_can_set_rx_all(struct pch_can_priv *priv, int set) |
b21d18b5 MO |
316 | { |
317 | int i; | |
318 | ||
319 | /* Traversing to obtain the object configured as receivers. */ | |
15ffc8fd T |
320 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) |
321 | pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); | |
b21d18b5 MO |
322 | } |
323 | ||
bd58cbc3 | 324 | static void pch_can_set_tx_all(struct pch_can_priv *priv, int set) |
b21d18b5 MO |
325 | { |
326 | int i; | |
327 | ||
328 | /* Traversing to obtain the object configured as transmit object. */ | |
15ffc8fd T |
329 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
330 | pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); | |
b21d18b5 MO |
331 | } |
332 | ||
bd58cbc3 | 333 | static u32 pch_can_int_pending(struct pch_can_priv *priv) |
b21d18b5 MO |
334 | { |
335 | return ioread32(&priv->regs->intr) & 0xffff; | |
336 | } | |
337 | ||
bd58cbc3 | 338 | static void pch_can_clear_if_buffers(struct pch_can_priv *priv) |
b21d18b5 | 339 | { |
bd58cbc3 | 340 | int i; /* Msg Obj ID (1~32) */ |
b21d18b5 | 341 | |
bd58cbc3 | 342 | for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
8339a7ed T |
343 | iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); |
344 | iowrite32(0xffff, &priv->regs->ifregs[0].mask1); | |
345 | iowrite32(0xffff, &priv->regs->ifregs[0].mask2); | |
346 | iowrite32(0x0, &priv->regs->ifregs[0].id1); | |
347 | iowrite32(0x0, &priv->regs->ifregs[0].id2); | |
348 | iowrite32(0x0, &priv->regs->ifregs[0].mcont); | |
8ac9702b T |
349 | iowrite32(0x0, &priv->regs->ifregs[0].data[0]); |
350 | iowrite32(0x0, &priv->regs->ifregs[0].data[1]); | |
351 | iowrite32(0x0, &priv->regs->ifregs[0].data[2]); | |
352 | iowrite32(0x0, &priv->regs->ifregs[0].data[3]); | |
086b5650 T |
353 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
354 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
8339a7ed | 355 | &priv->regs->ifregs[0].cmask); |
bd58cbc3 | 356 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); |
b21d18b5 MO |
357 | } |
358 | } | |
359 | ||
360 | static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) | |
361 | { | |
362 | int i; | |
b21d18b5 | 363 | |
15ffc8fd | 364 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
9388b166 | 365 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
bd58cbc3 | 366 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); |
b21d18b5 | 367 | |
15ffc8fd T |
368 | iowrite32(0x0, &priv->regs->ifregs[0].id1); |
369 | iowrite32(0x0, &priv->regs->ifregs[0].id2); | |
b21d18b5 | 370 | |
15ffc8fd T |
371 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, |
372 | PCH_IF_MCONT_UMASK); | |
b21d18b5 | 373 | |
15ffc8fd T |
374 | /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ |
375 | if (i == PCH_RX_OBJ_END) | |
376 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, | |
bd58cbc3 T |
377 | PCH_IF_MCONT_EOB); |
378 | else | |
379 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
086b5650 | 380 | PCH_IF_MCONT_EOB); |
b21d18b5 | 381 | |
15ffc8fd T |
382 | iowrite32(0, &priv->regs->ifregs[0].mask1); |
383 | pch_can_bit_clear(&priv->regs->ifregs[0].mask2, | |
384 | 0x1fff | PCH_MASK2_MDIR_MXTD); | |
b21d18b5 | 385 | |
15ffc8fd | 386 | /* Setting CMASK for writing */ |
9388b166 T |
387 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB | |
388 | PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask); | |
b21d18b5 | 389 | |
bd58cbc3 | 390 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); |
15ffc8fd | 391 | } |
b21d18b5 | 392 | |
15ffc8fd | 393 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
9388b166 | 394 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); |
bd58cbc3 | 395 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); |
b21d18b5 | 396 | |
15ffc8fd T |
397 | /* Resetting DIR bit for reception */ |
398 | iowrite32(0x0, &priv->regs->ifregs[1].id1); | |
44c9aa89 | 399 | iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2); |
b21d18b5 | 400 | |
15ffc8fd | 401 | /* Setting EOB bit for transmitter */ |
44c9aa89 T |
402 | iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK, |
403 | &priv->regs->ifregs[1].mcont); | |
15ffc8fd T |
404 | |
405 | iowrite32(0, &priv->regs->ifregs[1].mask1); | |
406 | pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); | |
407 | ||
408 | /* Setting CMASK for writing */ | |
9388b166 T |
409 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB | |
410 | PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask); | |
15ffc8fd | 411 | |
bd58cbc3 | 412 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); |
b21d18b5 | 413 | } |
b21d18b5 MO |
414 | } |
415 | ||
416 | static void pch_can_init(struct pch_can_priv *priv) | |
417 | { | |
418 | /* Stopping the Can device. */ | |
419 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
420 | ||
421 | /* Clearing all the message object buffers. */ | |
bd58cbc3 | 422 | pch_can_clear_if_buffers(priv); |
b21d18b5 MO |
423 | |
424 | /* Configuring the respective message object as either rx/tx object. */ | |
425 | pch_can_config_rx_tx_buffers(priv); | |
426 | ||
427 | /* Enabling the interrupts. */ | |
428 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
429 | } | |
430 | ||
431 | static void pch_can_release(struct pch_can_priv *priv) | |
432 | { | |
433 | /* Stooping the CAN device. */ | |
434 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
435 | ||
436 | /* Disabling the interrupts. */ | |
437 | pch_can_set_int_enables(priv, PCH_CAN_NONE); | |
438 | ||
439 | /* Disabling all the receive object. */ | |
8339a7ed | 440 | pch_can_set_rx_all(priv, 0); |
b21d18b5 MO |
441 | |
442 | /* Disabling all the transmit object. */ | |
8339a7ed | 443 | pch_can_set_tx_all(priv, 0); |
b21d18b5 MO |
444 | } |
445 | ||
446 | /* This function clears interrupt(s) from the CAN device. */ | |
447 | static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) | |
448 | { | |
b21d18b5 | 449 | /* Clear interrupt for transmit object */ |
15ffc8fd T |
450 | if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { |
451 | /* Setting CMASK for clearing the reception interrupts. */ | |
452 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, | |
453 | &priv->regs->ifregs[0].cmask); | |
454 | ||
455 | /* Clearing the Dir bit. */ | |
456 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); | |
457 | ||
458 | /* Clearing NewDat & IntPnd */ | |
459 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
460 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); | |
461 | ||
bd58cbc3 | 462 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask); |
15ffc8fd | 463 | } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { |
9388b166 T |
464 | /* |
465 | * Setting CMASK for clearing interrupts for frame transmission. | |
466 | */ | |
086b5650 | 467 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, |
8339a7ed | 468 | &priv->regs->ifregs[1].cmask); |
b21d18b5 MO |
469 | |
470 | /* Resetting the ID registers. */ | |
8339a7ed | 471 | pch_can_bit_set(&priv->regs->ifregs[1].id2, |
086b5650 | 472 | PCH_ID2_DIR | (0x7ff << 2)); |
8339a7ed | 473 | iowrite32(0x0, &priv->regs->ifregs[1].id1); |
b21d18b5 MO |
474 | |
475 | /* Claring NewDat, TxRqst & IntPnd */ | |
8339a7ed | 476 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
086b5650 T |
477 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
478 | PCH_IF_MCONT_TXRQXT); | |
bd58cbc3 | 479 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask); |
b21d18b5 MO |
480 | } |
481 | } | |
482 | ||
b21d18b5 MO |
483 | static void pch_can_reset(struct pch_can_priv *priv) |
484 | { | |
485 | /* write to sw reset register */ | |
486 | iowrite32(1, &priv->regs->srst); | |
487 | iowrite32(0, &priv->regs->srst); | |
488 | } | |
489 | ||
490 | static void pch_can_error(struct net_device *ndev, u32 status) | |
491 | { | |
492 | struct sk_buff *skb; | |
493 | struct pch_can_priv *priv = netdev_priv(ndev); | |
494 | struct can_frame *cf; | |
d68f6837 | 495 | u32 errc, lec; |
b21d18b5 MO |
496 | struct net_device_stats *stats = &(priv->ndev->stats); |
497 | enum can_state state = priv->can.state; | |
498 | ||
499 | skb = alloc_can_err_skb(ndev, &cf); | |
500 | if (!skb) | |
501 | return; | |
502 | ||
503 | if (status & PCH_BUS_OFF) { | |
8339a7ed T |
504 | pch_can_set_tx_all(priv, 0); |
505 | pch_can_set_rx_all(priv, 0); | |
b21d18b5 MO |
506 | state = CAN_STATE_BUS_OFF; |
507 | cf->can_id |= CAN_ERR_BUSOFF; | |
508 | can_bus_off(ndev); | |
b21d18b5 MO |
509 | } |
510 | ||
44c9aa89 | 511 | errc = ioread32(&priv->regs->errc); |
b21d18b5 MO |
512 | /* Warning interrupt. */ |
513 | if (status & PCH_EWARN) { | |
514 | state = CAN_STATE_ERROR_WARNING; | |
515 | priv->can.can_stats.error_warning++; | |
516 | cf->can_id |= CAN_ERR_CRTL; | |
086b5650 | 517 | if (((errc & PCH_REC) >> 8) > 96) |
b21d18b5 | 518 | cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; |
086b5650 | 519 | if ((errc & PCH_TEC) > 96) |
b21d18b5 | 520 | cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; |
435b4efe | 521 | netdev_dbg(ndev, |
b21d18b5 MO |
522 | "%s -> Error Counter is more than 96.\n", __func__); |
523 | } | |
524 | /* Error passive interrupt. */ | |
525 | if (status & PCH_EPASSIV) { | |
526 | priv->can.can_stats.error_passive++; | |
527 | state = CAN_STATE_ERROR_PASSIVE; | |
528 | cf->can_id |= CAN_ERR_CRTL; | |
44b0052c | 529 | if (errc & PCH_RP) |
b21d18b5 | 530 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; |
086b5650 | 531 | if ((errc & PCH_TEC) > 127) |
b21d18b5 | 532 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; |
435b4efe | 533 | netdev_dbg(ndev, |
b21d18b5 MO |
534 | "%s -> CAN controller is ERROR PASSIVE .\n", __func__); |
535 | } | |
536 | ||
d68f6837 T |
537 | lec = status & PCH_LEC_ALL; |
538 | switch (lec) { | |
539 | case PCH_STUF_ERR: | |
540 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
b21d18b5 MO |
541 | priv->can.can_stats.bus_error++; |
542 | stats->rx_errors++; | |
d68f6837 T |
543 | break; |
544 | case PCH_FORM_ERR: | |
545 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
546 | priv->can.can_stats.bus_error++; | |
547 | stats->rx_errors++; | |
548 | break; | |
549 | case PCH_ACK_ERR: | |
550 | cf->can_id |= CAN_ERR_ACK; | |
551 | priv->can.can_stats.bus_error++; | |
552 | stats->rx_errors++; | |
553 | break; | |
554 | case PCH_BIT1_ERR: | |
555 | case PCH_BIT0_ERR: | |
556 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
557 | priv->can.can_stats.bus_error++; | |
558 | stats->rx_errors++; | |
559 | break; | |
560 | case PCH_CRC_ERR: | |
ee50e135 | 561 | cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ | |
d68f6837 T |
562 | CAN_ERR_PROT_LOC_CRC_DEL; |
563 | priv->can.can_stats.bus_error++; | |
564 | stats->rx_errors++; | |
565 | break; | |
566 | case PCH_LEC_ALL: /* Written by CPU. No error status */ | |
567 | break; | |
b21d18b5 MO |
568 | } |
569 | ||
0c78ab76 T |
570 | cf->data[6] = errc & PCH_TEC; |
571 | cf->data[7] = (errc & PCH_REC) >> 8; | |
572 | ||
b21d18b5 | 573 | priv->can.state = state; |
cfb7e5f1 | 574 | netif_receive_skb(skb); |
b21d18b5 MO |
575 | |
576 | stats->rx_packets++; | |
577 | stats->rx_bytes += cf->can_dlc; | |
578 | } | |
579 | ||
580 | static irqreturn_t pch_can_interrupt(int irq, void *dev_id) | |
581 | { | |
582 | struct net_device *ndev = (struct net_device *)dev_id; | |
583 | struct pch_can_priv *priv = netdev_priv(ndev); | |
584 | ||
3332bc54 T |
585 | if (!pch_can_int_pending(priv)) |
586 | return IRQ_NONE; | |
587 | ||
b21d18b5 | 588 | pch_can_set_int_enables(priv, PCH_CAN_NONE); |
b21d18b5 | 589 | napi_schedule(&priv->napi); |
b21d18b5 MO |
590 | return IRQ_HANDLED; |
591 | } | |
592 | ||
1d5b4b27 T |
593 | static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id) |
594 | { | |
595 | if (obj_id < PCH_FIFO_THRESH) { | |
596 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | | |
597 | PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); | |
598 | ||
599 | /* Clearing the Dir bit. */ | |
600 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); | |
601 | ||
602 | /* Clearing NewDat & IntPnd */ | |
603 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
604 | PCH_IF_MCONT_INTPND); | |
bd58cbc3 | 605 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); |
1d5b4b27 T |
606 | } else if (obj_id > PCH_FIFO_THRESH) { |
607 | pch_can_int_clr(priv, obj_id); | |
608 | } else if (obj_id == PCH_FIFO_THRESH) { | |
609 | int cnt; | |
610 | for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) | |
611 | pch_can_int_clr(priv, cnt + 1); | |
612 | } | |
613 | } | |
614 | ||
615 | static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id) | |
616 | { | |
617 | struct pch_can_priv *priv = netdev_priv(ndev); | |
618 | struct net_device_stats *stats = &(priv->ndev->stats); | |
619 | struct sk_buff *skb; | |
620 | struct can_frame *cf; | |
621 | ||
622 | netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n"); | |
623 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
624 | PCH_IF_MCONT_MSGLOST); | |
625 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, | |
626 | &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 627 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); |
1d5b4b27 T |
628 | |
629 | skb = alloc_can_err_skb(ndev, &cf); | |
630 | if (!skb) | |
631 | return; | |
632 | ||
633 | cf->can_id |= CAN_ERR_CRTL; | |
634 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
635 | stats->rx_over_errors++; | |
636 | stats->rx_errors++; | |
637 | ||
638 | netif_receive_skb(skb); | |
639 | } | |
640 | ||
641 | static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota) | |
b21d18b5 MO |
642 | { |
643 | u32 reg; | |
644 | canid_t id; | |
b21d18b5 MO |
645 | int rcv_pkts = 0; |
646 | struct sk_buff *skb; | |
647 | struct can_frame *cf; | |
648 | struct pch_can_priv *priv = netdev_priv(ndev); | |
649 | struct net_device_stats *stats = &(priv->ndev->stats); | |
1d5b4b27 T |
650 | int i; |
651 | u32 id2; | |
8ac9702b | 652 | u16 data_reg; |
b21d18b5 | 653 | |
1d5b4b27 | 654 | do { |
70f23fd6 | 655 | /* Reading the message object from the Message RAM */ |
1d5b4b27 | 656 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
bd58cbc3 | 657 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num); |
b21d18b5 | 658 | |
1d5b4b27 T |
659 | /* Reading the MCONT register. */ |
660 | reg = ioread32(&priv->regs->ifregs[0].mcont); | |
661 | ||
662 | if (reg & PCH_IF_MCONT_EOB) | |
663 | break; | |
b21d18b5 | 664 | |
b21d18b5 | 665 | /* If MsgLost bit set. */ |
086b5650 | 666 | if (reg & PCH_IF_MCONT_MSGLOST) { |
1d5b4b27 | 667 | pch_can_rx_msg_lost(ndev, obj_num); |
b21d18b5 | 668 | rcv_pkts++; |
1d5b4b27 T |
669 | quota--; |
670 | obj_num++; | |
671 | continue; | |
672 | } else if (!(reg & PCH_IF_MCONT_NEWDAT)) { | |
673 | obj_num++; | |
674 | continue; | |
b21d18b5 | 675 | } |
b21d18b5 MO |
676 | |
677 | skb = alloc_can_skb(priv->ndev, &cf); | |
3332bc54 T |
678 | if (!skb) { |
679 | netdev_err(ndev, "alloc_can_skb Failed\n"); | |
680 | return rcv_pkts; | |
681 | } | |
b21d18b5 MO |
682 | |
683 | /* Get Received data */ | |
1d5b4b27 T |
684 | id2 = ioread32(&priv->regs->ifregs[0].id2); |
685 | if (id2 & PCH_ID2_XTD) { | |
8339a7ed | 686 | id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); |
1d5b4b27 T |
687 | id |= (((id2) & 0x1fff) << 16); |
688 | cf->can_id = id | CAN_EFF_FLAG; | |
b21d18b5 | 689 | } else { |
1d5b4b27 T |
690 | id = (id2 >> 2) & CAN_SFF_MASK; |
691 | cf->can_id = id; | |
b21d18b5 MO |
692 | } |
693 | ||
1d5b4b27 | 694 | if (id2 & PCH_ID2_DIR) |
b21d18b5 | 695 | cf->can_id |= CAN_RTR_FLAG; |
1d5b4b27 T |
696 | |
697 | cf->can_dlc = get_can_dlc((ioread32(&priv->regs-> | |
698 | ifregs[0].mcont)) & 0xF); | |
b21d18b5 | 699 | |
8ac9702b T |
700 | for (i = 0; i < cf->can_dlc; i += 2) { |
701 | data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]); | |
702 | cf->data[i] = data_reg; | |
703 | cf->data[i + 1] = data_reg >> 8; | |
b21d18b5 MO |
704 | } |
705 | ||
706 | netif_receive_skb(skb); | |
707 | rcv_pkts++; | |
708 | stats->rx_packets++; | |
1d5b4b27 | 709 | quota--; |
b21d18b5 MO |
710 | stats->rx_bytes += cf->can_dlc; |
711 | ||
1d5b4b27 T |
712 | pch_fifo_thresh(priv, obj_num); |
713 | obj_num++; | |
714 | } while (quota > 0); | |
b21d18b5 MO |
715 | |
716 | return rcv_pkts; | |
717 | } | |
e489cceb T |
718 | |
719 | static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat) | |
b21d18b5 | 720 | { |
b21d18b5 MO |
721 | struct pch_can_priv *priv = netdev_priv(ndev); |
722 | struct net_device_stats *stats = &(priv->ndev->stats); | |
723 | u32 dlc; | |
e489cceb T |
724 | |
725 | can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); | |
726 | iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, | |
727 | &priv->regs->ifregs[1].cmask); | |
bd58cbc3 | 728 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat); |
e489cceb T |
729 | dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) & |
730 | PCH_IF_MCONT_DLC); | |
731 | stats->tx_bytes += dlc; | |
732 | stats->tx_packets++; | |
733 | if (int_stat == PCH_TX_OBJ_END) | |
734 | netif_wake_queue(ndev); | |
735 | } | |
736 | ||
bd58cbc3 | 737 | static int pch_can_poll(struct napi_struct *napi, int quota) |
e489cceb T |
738 | { |
739 | struct net_device *ndev = napi->dev; | |
740 | struct pch_can_priv *priv = netdev_priv(ndev); | |
b21d18b5 | 741 | u32 int_stat; |
b21d18b5 | 742 | u32 reg_stat; |
3332bc54 | 743 | int quota_save = quota; |
b21d18b5 MO |
744 | |
745 | int_stat = pch_can_int_pending(priv); | |
746 | if (!int_stat) | |
e489cceb | 747 | goto end; |
b21d18b5 | 748 | |
8714fcac | 749 | if (int_stat == PCH_STATUS_INT) { |
b21d18b5 | 750 | reg_stat = ioread32(&priv->regs->stat); |
b21d18b5 | 751 | |
fea9294c T |
752 | if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) && |
753 | ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) { | |
754 | pch_can_error(ndev, reg_stat); | |
755 | quota--; | |
756 | } | |
b21d18b5 | 757 | |
fea9294c T |
758 | if (reg_stat & (PCH_TX_OK | PCH_RX_OK)) |
759 | pch_can_bit_clear(&priv->regs->stat, | |
760 | reg_stat & (PCH_TX_OK | PCH_RX_OK)); | |
b21d18b5 MO |
761 | |
762 | int_stat = pch_can_int_pending(priv); | |
b21d18b5 MO |
763 | } |
764 | ||
e489cceb T |
765 | if (quota == 0) |
766 | goto end; | |
767 | ||
15ffc8fd | 768 | if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { |
3332bc54 | 769 | quota -= pch_can_rx_normal(ndev, int_stat, quota); |
15ffc8fd T |
770 | } else if ((int_stat >= PCH_TX_OBJ_START) && |
771 | (int_stat <= PCH_TX_OBJ_END)) { | |
772 | /* Handle transmission interrupt */ | |
e489cceb | 773 | pch_can_tx_complete(ndev, int_stat); |
b21d18b5 MO |
774 | } |
775 | ||
e489cceb | 776 | end: |
b21d18b5 MO |
777 | napi_complete(napi); |
778 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
779 | ||
3332bc54 | 780 | return quota_save - quota; |
b21d18b5 MO |
781 | } |
782 | ||
783 | static int pch_set_bittiming(struct net_device *ndev) | |
784 | { | |
785 | struct pch_can_priv *priv = netdev_priv(ndev); | |
786 | const struct can_bittiming *bt = &priv->can.bittiming; | |
787 | u32 canbit; | |
788 | u32 bepe; | |
b21d18b5 MO |
789 | |
790 | /* Setting the CCE bit for accessing the Can Timing register. */ | |
086b5650 | 791 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); |
b21d18b5 | 792 | |
0e0805c4 | 793 | canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP; |
bd58cbc3 T |
794 | canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT; |
795 | canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT; | |
796 | canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT; | |
0e0805c4 | 797 | bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT; |
b21d18b5 MO |
798 | iowrite32(canbit, &priv->regs->bitt); |
799 | iowrite32(bepe, &priv->regs->brpe); | |
086b5650 | 800 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); |
b21d18b5 MO |
801 | |
802 | return 0; | |
803 | } | |
804 | ||
805 | static void pch_can_start(struct net_device *ndev) | |
806 | { | |
807 | struct pch_can_priv *priv = netdev_priv(ndev); | |
808 | ||
809 | if (priv->can.state != CAN_STATE_STOPPED) | |
810 | pch_can_reset(priv); | |
811 | ||
812 | pch_set_bittiming(ndev); | |
813 | pch_can_set_optmode(priv); | |
814 | ||
8339a7ed T |
815 | pch_can_set_tx_all(priv, 1); |
816 | pch_can_set_rx_all(priv, 1); | |
b21d18b5 MO |
817 | |
818 | /* Setting the CAN to run mode. */ | |
819 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
820 | ||
821 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
822 | ||
823 | return; | |
824 | } | |
825 | ||
826 | static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) | |
827 | { | |
828 | int ret = 0; | |
829 | ||
830 | switch (mode) { | |
831 | case CAN_MODE_START: | |
832 | pch_can_start(ndev); | |
833 | netif_wake_queue(ndev); | |
834 | break; | |
835 | default: | |
836 | ret = -EOPNOTSUPP; | |
837 | break; | |
838 | } | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
843 | static int pch_can_open(struct net_device *ndev) | |
844 | { | |
845 | struct pch_can_priv *priv = netdev_priv(ndev); | |
846 | int retval; | |
847 | ||
c7551456 | 848 | /* Regstering the interrupt. */ |
b21d18b5 MO |
849 | retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, |
850 | ndev->name, ndev); | |
851 | if (retval) { | |
435b4efe | 852 | netdev_err(ndev, "request_irq failed.\n"); |
b21d18b5 MO |
853 | goto req_irq_err; |
854 | } | |
855 | ||
856 | /* Open common can device */ | |
857 | retval = open_candev(ndev); | |
858 | if (retval) { | |
435b4efe | 859 | netdev_err(ndev, "open_candev() failed %d\n", retval); |
b21d18b5 MO |
860 | goto err_open_candev; |
861 | } | |
862 | ||
863 | pch_can_init(priv); | |
864 | pch_can_start(ndev); | |
865 | napi_enable(&priv->napi); | |
866 | netif_start_queue(ndev); | |
867 | ||
868 | return 0; | |
869 | ||
870 | err_open_candev: | |
871 | free_irq(priv->dev->irq, ndev); | |
872 | req_irq_err: | |
b21d18b5 MO |
873 | pch_can_release(priv); |
874 | ||
875 | return retval; | |
876 | } | |
877 | ||
878 | static int pch_close(struct net_device *ndev) | |
879 | { | |
880 | struct pch_can_priv *priv = netdev_priv(ndev); | |
881 | ||
882 | netif_stop_queue(ndev); | |
883 | napi_disable(&priv->napi); | |
884 | pch_can_release(priv); | |
885 | free_irq(priv->dev->irq, ndev); | |
b21d18b5 MO |
886 | close_candev(ndev); |
887 | priv->can.state = CAN_STATE_STOPPED; | |
888 | return 0; | |
889 | } | |
890 | ||
b21d18b5 MO |
891 | static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) |
892 | { | |
b21d18b5 MO |
893 | struct pch_can_priv *priv = netdev_priv(ndev); |
894 | struct can_frame *cf = (struct can_frame *)skb->data; | |
bd58cbc3 | 895 | int tx_obj_no; |
8ac9702b | 896 | int i; |
44c9aa89 | 897 | u32 id2; |
b21d18b5 MO |
898 | |
899 | if (can_dropped_invalid_skb(ndev, skb)) | |
900 | return NETDEV_TX_OK; | |
901 | ||
fea9294c | 902 | tx_obj_no = priv->tx_obj; |
76d94b23 T |
903 | if (priv->tx_obj == PCH_TX_OBJ_END) { |
904 | if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) | |
905 | netif_stop_queue(ndev); | |
b21d18b5 | 906 | |
76d94b23 | 907 | priv->tx_obj = PCH_TX_OBJ_START; |
b21d18b5 | 908 | } else { |
76d94b23 | 909 | priv->tx_obj++; |
b21d18b5 | 910 | } |
b21d18b5 | 911 | |
b21d18b5 | 912 | /* Setting the CMASK register. */ |
8339a7ed | 913 | pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); |
b21d18b5 MO |
914 | |
915 | /* If ID extended is set. */ | |
b21d18b5 | 916 | if (cf->can_id & CAN_EFF_FLAG) { |
44c9aa89 T |
917 | iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1); |
918 | id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD; | |
b21d18b5 | 919 | } else { |
44c9aa89 T |
920 | iowrite32(0, &priv->regs->ifregs[1].id1); |
921 | id2 = (cf->can_id & CAN_SFF_MASK) << 2; | |
b21d18b5 MO |
922 | } |
923 | ||
44c9aa89 T |
924 | id2 |= PCH_ID_MSGVAL; |
925 | ||
b21d18b5 | 926 | /* If remote frame has to be transmitted.. */ |
fea9294c | 927 | if (!(cf->can_id & CAN_RTR_FLAG)) |
44c9aa89 T |
928 | id2 |= PCH_ID2_DIR; |
929 | ||
930 | iowrite32(id2, &priv->regs->ifregs[1].id2); | |
b21d18b5 | 931 | |
8ac9702b T |
932 | /* Copy data to register */ |
933 | for (i = 0; i < cf->can_dlc; i += 2) { | |
934 | iowrite16(cf->data[i] | (cf->data[i + 1] << 8), | |
935 | &priv->regs->ifregs[1].data[i / 2]); | |
b21d18b5 MO |
936 | } |
937 | ||
bd58cbc3 | 938 | can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1); |
b21d18b5 | 939 | |
c7551456 | 940 | /* Set the size of the data. Update if2_mcont */ |
44c9aa89 T |
941 | iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT | |
942 | PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont); | |
b21d18b5 | 943 | |
bd58cbc3 | 944 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no); |
b21d18b5 | 945 | |
b21d18b5 MO |
946 | return NETDEV_TX_OK; |
947 | } | |
948 | ||
949 | static const struct net_device_ops pch_can_netdev_ops = { | |
950 | .ndo_open = pch_can_open, | |
951 | .ndo_stop = pch_close, | |
952 | .ndo_start_xmit = pch_xmit, | |
c971fa2a | 953 | .ndo_change_mtu = can_change_mtu, |
b21d18b5 MO |
954 | }; |
955 | ||
3c8ac0f2 | 956 | static void pch_can_remove(struct pci_dev *pdev) |
b21d18b5 MO |
957 | { |
958 | struct net_device *ndev = pci_get_drvdata(pdev); | |
959 | struct pch_can_priv *priv = netdev_priv(ndev); | |
960 | ||
961 | unregister_candev(priv->ndev); | |
a6f6d6b5 T |
962 | if (priv->use_msi) |
963 | pci_disable_msi(priv->dev); | |
b21d18b5 MO |
964 | pci_release_regions(pdev); |
965 | pci_disable_device(pdev); | |
b21d18b5 | 966 | pch_can_reset(priv); |
ce9736d4 | 967 | pci_iounmap(pdev, priv->regs); |
a6f6d6b5 | 968 | free_candev(priv->ndev); |
b21d18b5 MO |
969 | } |
970 | ||
971 | #ifdef CONFIG_PM | |
7f2bc50e T |
972 | static void pch_can_set_int_custom(struct pch_can_priv *priv) |
973 | { | |
974 | /* Clearing the IE, SIE and EIE bits of Can control register. */ | |
975 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); | |
976 | ||
977 | /* Appropriately setting them. */ | |
978 | pch_can_bit_set(&priv->regs->cont, | |
979 | ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); | |
980 | } | |
981 | ||
982 | /* This function retrieves interrupt enabled for the CAN device. */ | |
ca2b004e | 983 | static u32 pch_can_get_int_enables(struct pch_can_priv *priv) |
7f2bc50e T |
984 | { |
985 | /* Obtaining the status of IE, SIE and EIE interrupt bits. */ | |
ca2b004e | 986 | return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1; |
7f2bc50e T |
987 | } |
988 | ||
989 | static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, | |
990 | enum pch_ifreg dir) | |
991 | { | |
992 | u32 ie, enable; | |
993 | ||
994 | if (dir) | |
995 | ie = PCH_IF_MCONT_RXIE; | |
996 | else | |
997 | ie = PCH_IF_MCONT_TXIE; | |
998 | ||
999 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); | |
bd58cbc3 | 1000 | pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); |
7f2bc50e T |
1001 | |
1002 | if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && | |
9388b166 | 1003 | ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) |
7f2bc50e | 1004 | enable = 1; |
9388b166 | 1005 | else |
7f2bc50e | 1006 | enable = 0; |
9388b166 | 1007 | |
7f2bc50e T |
1008 | return enable; |
1009 | } | |
1010 | ||
1011 | static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, | |
bd58cbc3 | 1012 | u32 buffer_num, int set) |
7f2bc50e T |
1013 | { |
1014 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 1015 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
7f2bc50e T |
1016 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, |
1017 | &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 1018 | if (set) |
7f2bc50e T |
1019 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
1020 | PCH_IF_MCONT_EOB); | |
1021 | else | |
1022 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); | |
1023 | ||
bd58cbc3 | 1024 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
7f2bc50e T |
1025 | } |
1026 | ||
ca2b004e | 1027 | static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num) |
7f2bc50e | 1028 | { |
ca2b004e T |
1029 | u32 link; |
1030 | ||
7f2bc50e | 1031 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
bd58cbc3 | 1032 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
7f2bc50e T |
1033 | |
1034 | if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) | |
ca2b004e | 1035 | link = 0; |
7f2bc50e | 1036 | else |
ca2b004e T |
1037 | link = 1; |
1038 | return link; | |
7f2bc50e T |
1039 | } |
1040 | ||
1041 | static int pch_can_get_buffer_status(struct pch_can_priv *priv) | |
1042 | { | |
1043 | return (ioread32(&priv->regs->treq1) & 0xffff) | | |
bd58cbc3 | 1044 | (ioread32(&priv->regs->treq2) << 16); |
7f2bc50e T |
1045 | } |
1046 | ||
b21d18b5 MO |
1047 | static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) |
1048 | { | |
c7551456 T |
1049 | int i; |
1050 | int retval; | |
b21d18b5 | 1051 | u32 buf_stat; /* Variable for reading the transmit buffer status. */ |
bd58cbc3 | 1052 | int counter = PCH_COUNTER_LIMIT; |
b21d18b5 MO |
1053 | |
1054 | struct net_device *dev = pci_get_drvdata(pdev); | |
1055 | struct pch_can_priv *priv = netdev_priv(dev); | |
1056 | ||
1057 | /* Stop the CAN controller */ | |
1058 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1059 | ||
1060 | /* Indicate that we are aboutto/in suspend */ | |
d06848be | 1061 | priv->can.state = CAN_STATE_STOPPED; |
b21d18b5 MO |
1062 | |
1063 | /* Waiting for all transmission to complete. */ | |
1064 | while (counter) { | |
1065 | buf_stat = pch_can_get_buffer_status(priv); | |
1066 | if (!buf_stat) | |
1067 | break; | |
1068 | counter--; | |
1069 | udelay(1); | |
1070 | } | |
1071 | if (!counter) | |
1072 | dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); | |
1073 | ||
1074 | /* Save interrupt configuration and then disable them */ | |
ca2b004e | 1075 | priv->int_enables = pch_can_get_int_enables(priv); |
b21d18b5 MO |
1076 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); |
1077 | ||
1078 | /* Save Tx buffer enable state */ | |
15ffc8fd | 1079 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
f622691c T |
1080 | priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i, |
1081 | PCH_TX_IFREG); | |
b21d18b5 MO |
1082 | |
1083 | /* Disable all Transmit buffers */ | |
8339a7ed | 1084 | pch_can_set_tx_all(priv, 0); |
b21d18b5 MO |
1085 | |
1086 | /* Save Rx buffer enable state */ | |
15ffc8fd | 1087 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
f622691c T |
1088 | priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i, |
1089 | PCH_RX_IFREG); | |
1090 | priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i); | |
b21d18b5 MO |
1091 | } |
1092 | ||
1093 | /* Disable all Receive buffers */ | |
8339a7ed | 1094 | pch_can_set_rx_all(priv, 0); |
b21d18b5 MO |
1095 | retval = pci_save_state(pdev); |
1096 | if (retval) { | |
1097 | dev_err(&pdev->dev, "pci_save_state failed.\n"); | |
1098 | } else { | |
1099 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1100 | pci_disable_device(pdev); | |
1101 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1102 | } | |
1103 | ||
1104 | return retval; | |
1105 | } | |
1106 | ||
1107 | static int pch_can_resume(struct pci_dev *pdev) | |
1108 | { | |
c7551456 T |
1109 | int i; |
1110 | int retval; | |
b21d18b5 MO |
1111 | struct net_device *dev = pci_get_drvdata(pdev); |
1112 | struct pch_can_priv *priv = netdev_priv(dev); | |
1113 | ||
1114 | pci_set_power_state(pdev, PCI_D0); | |
1115 | pci_restore_state(pdev); | |
1116 | retval = pci_enable_device(pdev); | |
1117 | if (retval) { | |
1118 | dev_err(&pdev->dev, "pci_enable_device failed.\n"); | |
1119 | return retval; | |
1120 | } | |
1121 | ||
1122 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1123 | ||
1124 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1125 | ||
1126 | /* Disabling all interrupts. */ | |
1127 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); | |
1128 | ||
1129 | /* Setting the CAN device in Stop Mode. */ | |
1130 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1131 | ||
1132 | /* Configuring the transmit and receive buffers. */ | |
1133 | pch_can_config_rx_tx_buffers(priv); | |
1134 | ||
1135 | /* Restore the CAN state */ | |
1136 | pch_set_bittiming(dev); | |
1137 | ||
1138 | /* Listen/Active */ | |
1139 | pch_can_set_optmode(priv); | |
1140 | ||
1141 | /* Enabling the transmit buffer. */ | |
15ffc8fd | 1142 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
f622691c | 1143 | pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG); |
b21d18b5 MO |
1144 | |
1145 | /* Configuring the receive buffer and enabling them. */ | |
15ffc8fd T |
1146 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
1147 | /* Restore buffer link */ | |
f622691c | 1148 | pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]); |
b21d18b5 | 1149 | |
15ffc8fd | 1150 | /* Restore buffer enables */ |
f622691c | 1151 | pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG); |
b21d18b5 MO |
1152 | } |
1153 | ||
1154 | /* Enable CAN Interrupts */ | |
1155 | pch_can_set_int_custom(priv); | |
1156 | ||
1157 | /* Restore Run Mode */ | |
1158 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
1159 | ||
1160 | return retval; | |
1161 | } | |
1162 | #else | |
1163 | #define pch_can_suspend NULL | |
1164 | #define pch_can_resume NULL | |
1165 | #endif | |
1166 | ||
1167 | static int pch_can_get_berr_counter(const struct net_device *dev, | |
1168 | struct can_berr_counter *bec) | |
1169 | { | |
1170 | struct pch_can_priv *priv = netdev_priv(dev); | |
44c9aa89 | 1171 | u32 errc = ioread32(&priv->regs->errc); |
b21d18b5 | 1172 | |
44c9aa89 T |
1173 | bec->txerr = errc & PCH_TEC; |
1174 | bec->rxerr = (errc & PCH_REC) >> 8; | |
b21d18b5 MO |
1175 | |
1176 | return 0; | |
1177 | } | |
1178 | ||
3c8ac0f2 | 1179 | static int pch_can_probe(struct pci_dev *pdev, |
b21d18b5 MO |
1180 | const struct pci_device_id *id) |
1181 | { | |
1182 | struct net_device *ndev; | |
1183 | struct pch_can_priv *priv; | |
1184 | int rc; | |
b21d18b5 MO |
1185 | void __iomem *addr; |
1186 | ||
1187 | rc = pci_enable_device(pdev); | |
1188 | if (rc) { | |
1189 | dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); | |
1190 | goto probe_exit_endev; | |
1191 | } | |
1192 | ||
1193 | rc = pci_request_regions(pdev, KBUILD_MODNAME); | |
1194 | if (rc) { | |
1195 | dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); | |
1196 | goto probe_exit_pcireq; | |
1197 | } | |
1198 | ||
1199 | addr = pci_iomap(pdev, 1, 0); | |
1200 | if (!addr) { | |
1201 | rc = -EIO; | |
1202 | dev_err(&pdev->dev, "Failed pci_iomap\n"); | |
1203 | goto probe_exit_ipmap; | |
1204 | } | |
1205 | ||
15ffc8fd | 1206 | ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); |
b21d18b5 MO |
1207 | if (!ndev) { |
1208 | rc = -ENOMEM; | |
1209 | dev_err(&pdev->dev, "Failed alloc_candev\n"); | |
1210 | goto probe_exit_alloc_candev; | |
1211 | } | |
1212 | ||
1213 | priv = netdev_priv(ndev); | |
1214 | priv->ndev = ndev; | |
1215 | priv->regs = addr; | |
1216 | priv->dev = pdev; | |
1217 | priv->can.bittiming_const = &pch_can_bittiming_const; | |
1218 | priv->can.do_set_mode = pch_can_do_set_mode; | |
1219 | priv->can.do_get_berr_counter = pch_can_get_berr_counter; | |
1220 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | | |
1221 | CAN_CTRLMODE_LOOPBACK; | |
15ffc8fd | 1222 | priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ |
b21d18b5 MO |
1223 | |
1224 | ndev->irq = pdev->irq; | |
1225 | ndev->flags |= IFF_ECHO; | |
1226 | ||
1227 | pci_set_drvdata(pdev, ndev); | |
1228 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1229 | ndev->netdev_ops = &pch_can_netdev_ops; | |
b21d18b5 | 1230 | priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ |
b21d18b5 | 1231 | |
bd58cbc3 | 1232 | netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END); |
b21d18b5 | 1233 | |
a6f6d6b5 T |
1234 | rc = pci_enable_msi(priv->dev); |
1235 | if (rc) { | |
1236 | netdev_err(ndev, "PCH CAN opened without MSI\n"); | |
1237 | priv->use_msi = 0; | |
1238 | } else { | |
1239 | netdev_err(ndev, "PCH CAN opened with MSI\n"); | |
c69b9092 | 1240 | pci_set_master(pdev); |
a6f6d6b5 T |
1241 | priv->use_msi = 1; |
1242 | } | |
1243 | ||
b21d18b5 MO |
1244 | rc = register_candev(ndev); |
1245 | if (rc) { | |
1246 | dev_err(&pdev->dev, "Failed register_candev %d\n", rc); | |
1247 | goto probe_exit_reg_candev; | |
1248 | } | |
1249 | ||
1250 | return 0; | |
1251 | ||
1252 | probe_exit_reg_candev: | |
a6f6d6b5 T |
1253 | if (priv->use_msi) |
1254 | pci_disable_msi(priv->dev); | |
b21d18b5 MO |
1255 | free_candev(ndev); |
1256 | probe_exit_alloc_candev: | |
1257 | pci_iounmap(pdev, addr); | |
1258 | probe_exit_ipmap: | |
1259 | pci_release_regions(pdev); | |
1260 | probe_exit_pcireq: | |
1261 | pci_disable_device(pdev); | |
1262 | probe_exit_endev: | |
1263 | return rc; | |
1264 | } | |
1265 | ||
bdfa3d8f | 1266 | static struct pci_driver pch_can_pci_driver = { |
b21d18b5 MO |
1267 | .name = "pch_can", |
1268 | .id_table = pch_pci_tbl, | |
1269 | .probe = pch_can_probe, | |
3c8ac0f2 | 1270 | .remove = pch_can_remove, |
b21d18b5 MO |
1271 | .suspend = pch_can_suspend, |
1272 | .resume = pch_can_resume, | |
1273 | }; | |
1274 | ||
fb7944b3 | 1275 | module_pci_driver(pch_can_pci_driver); |
b21d18b5 | 1276 | |
e91530ea | 1277 | MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver"); |
b21d18b5 MO |
1278 | MODULE_LICENSE("GPL v2"); |
1279 | MODULE_VERSION("0.94"); |