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b21d18b5 MO |
1 | /* |
2 | * Copyright (C) 1999 - 2010 Intel Corporation. | |
3 | * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/skbuff.h> | |
31 | #include <linux/can.h> | |
32 | #include <linux/can/dev.h> | |
33 | #include <linux/can/error.h> | |
34 | ||
0a80410d T |
35 | #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ |
36 | #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ | |
37 | #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) | |
38 | #define PCH_CTRL_CCE BIT(6) | |
39 | #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ | |
40 | #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ | |
41 | #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ | |
42 | ||
086b5650 T |
43 | #define PCH_CMASK_RX_TX_SET 0x00f3 |
44 | #define PCH_CMASK_RX_TX_GET 0x0073 | |
45 | #define PCH_CMASK_ALL 0xff | |
0a80410d T |
46 | #define PCH_CMASK_NEWDAT BIT(2) |
47 | #define PCH_CMASK_CLRINTPND BIT(3) | |
48 | #define PCH_CMASK_CTRL BIT(4) | |
49 | #define PCH_CMASK_ARB BIT(5) | |
50 | #define PCH_CMASK_MASK BIT(6) | |
51 | #define PCH_CMASK_RDWR BIT(7) | |
52 | #define PCH_IF_MCONT_NEWDAT BIT(15) | |
53 | #define PCH_IF_MCONT_MSGLOST BIT(14) | |
54 | #define PCH_IF_MCONT_INTPND BIT(13) | |
55 | #define PCH_IF_MCONT_UMASK BIT(12) | |
56 | #define PCH_IF_MCONT_TXIE BIT(11) | |
57 | #define PCH_IF_MCONT_RXIE BIT(10) | |
58 | #define PCH_IF_MCONT_RMTEN BIT(9) | |
59 | #define PCH_IF_MCONT_TXRQXT BIT(8) | |
60 | #define PCH_IF_MCONT_EOB BIT(7) | |
61 | #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) | |
62 | #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) | |
63 | #define PCH_ID2_DIR BIT(13) | |
64 | #define PCH_ID2_XTD BIT(14) | |
65 | #define PCH_ID_MSGVAL BIT(15) | |
66 | #define PCH_IF_CREQ_BUSY BIT(15) | |
086b5650 T |
67 | |
68 | #define PCH_STATUS_INT 0x8000 | |
69 | #define PCH_REC 0x00007f00 | |
70 | #define PCH_TEC 0x000000ff | |
b21d18b5 | 71 | |
0a80410d T |
72 | #define PCH_TX_OK BIT(3) |
73 | #define PCH_RX_OK BIT(4) | |
74 | #define PCH_EPASSIV BIT(5) | |
75 | #define PCH_EWARN BIT(6) | |
76 | #define PCH_BUS_OFF BIT(7) | |
b21d18b5 MO |
77 | |
78 | /* bit position of certain controller bits. */ | |
bd58cbc3 T |
79 | #define PCH_BIT_BRP_SHIFT 0 |
80 | #define PCH_BIT_SJW_SHIFT 6 | |
81 | #define PCH_BIT_TSEG1_SHIFT 8 | |
82 | #define PCH_BIT_TSEG2_SHIFT 12 | |
83 | #define PCH_BIT_BRPE_BRPE_SHIFT 6 | |
84 | ||
086b5650 T |
85 | #define PCH_MSK_BITT_BRP 0x3f |
86 | #define PCH_MSK_BRPE_BRPE 0x3c0 | |
87 | #define PCH_MSK_CTRL_IE_SIE_EIE 0x07 | |
88 | #define PCH_COUNTER_LIMIT 10 | |
b21d18b5 MO |
89 | |
90 | #define PCH_CAN_CLK 50000000 /* 50MHz */ | |
91 | ||
92 | /* Define the number of message object. | |
93 | * PCH CAN communications are done via Message RAM. | |
94 | * The Message RAM consists of 32 message objects. */ | |
15ffc8fd T |
95 | #define PCH_RX_OBJ_NUM 26 |
96 | #define PCH_TX_OBJ_NUM 6 | |
97 | #define PCH_RX_OBJ_START 1 | |
98 | #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM | |
99 | #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) | |
100 | #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) | |
b21d18b5 MO |
101 | |
102 | #define PCH_FIFO_THRESH 16 | |
103 | ||
76d94b23 T |
104 | /* TxRqst2 show status of MsgObjNo.17~32 */ |
105 | #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\ | |
106 | (PCH_RX_OBJ_END - 16)) | |
107 | ||
8339a7ed T |
108 | enum pch_ifreg { |
109 | PCH_RX_IFREG, | |
110 | PCH_TX_IFREG, | |
111 | }; | |
112 | ||
d68f6837 T |
113 | enum pch_can_err { |
114 | PCH_STUF_ERR = 1, | |
115 | PCH_FORM_ERR, | |
116 | PCH_ACK_ERR, | |
117 | PCH_BIT1_ERR, | |
118 | PCH_BIT0_ERR, | |
119 | PCH_CRC_ERR, | |
120 | PCH_LEC_ALL, | |
121 | }; | |
122 | ||
b21d18b5 MO |
123 | enum pch_can_mode { |
124 | PCH_CAN_ENABLE, | |
125 | PCH_CAN_DISABLE, | |
126 | PCH_CAN_ALL, | |
127 | PCH_CAN_NONE, | |
128 | PCH_CAN_STOP, | |
129 | PCH_CAN_RUN | |
130 | }; | |
131 | ||
8339a7ed T |
132 | struct pch_can_if_regs { |
133 | u32 creq; | |
134 | u32 cmask; | |
135 | u32 mask1; | |
136 | u32 mask2; | |
137 | u32 id1; | |
138 | u32 id2; | |
139 | u32 mcont; | |
8ac9702b | 140 | u32 data[4]; |
8339a7ed T |
141 | u32 rsv[13]; |
142 | }; | |
143 | ||
b21d18b5 MO |
144 | struct pch_can_regs { |
145 | u32 cont; | |
146 | u32 stat; | |
147 | u32 errc; | |
148 | u32 bitt; | |
149 | u32 intr; | |
150 | u32 opt; | |
151 | u32 brpe; | |
8339a7ed T |
152 | u32 reserve; |
153 | struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ | |
154 | u32 reserve1[8]; | |
b21d18b5 MO |
155 | u32 treq1; |
156 | u32 treq2; | |
8339a7ed T |
157 | u32 reserve2[6]; |
158 | u32 data1; | |
159 | u32 data2; | |
160 | u32 reserve3[6]; | |
161 | u32 canipend1; | |
162 | u32 canipend2; | |
163 | u32 reserve4[6]; | |
164 | u32 canmval1; | |
165 | u32 canmval2; | |
166 | u32 reserve5[37]; | |
b21d18b5 MO |
167 | u32 srst; |
168 | }; | |
169 | ||
170 | struct pch_can_priv { | |
171 | struct can_priv can; | |
b21d18b5 | 172 | struct pci_dev *dev; |
bd58cbc3 T |
173 | u32 tx_enable[PCH_TX_OBJ_END]; |
174 | u32 rx_enable[PCH_TX_OBJ_END]; | |
175 | u32 rx_link[PCH_TX_OBJ_END]; | |
176 | u32 int_enables; | |
b21d18b5 | 177 | struct net_device *ndev; |
b21d18b5 MO |
178 | struct pch_can_regs __iomem *regs; |
179 | struct napi_struct napi; | |
bd58cbc3 T |
180 | int tx_obj; /* Point next Tx Obj index */ |
181 | int use_msi; | |
b21d18b5 MO |
182 | }; |
183 | ||
184 | static struct can_bittiming_const pch_can_bittiming_const = { | |
185 | .name = KBUILD_MODNAME, | |
186 | .tseg1_min = 1, | |
187 | .tseg1_max = 16, | |
188 | .tseg2_min = 1, | |
189 | .tseg2_max = 8, | |
190 | .sjw_max = 4, | |
191 | .brp_min = 1, | |
192 | .brp_max = 1024, /* 6bit + extended 4bit */ | |
193 | .brp_inc = 1, | |
194 | }; | |
195 | ||
196 | static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { | |
197 | {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, | |
198 | {0,} | |
199 | }; | |
200 | MODULE_DEVICE_TABLE(pci, pch_pci_tbl); | |
201 | ||
526de53c | 202 | static inline void pch_can_bit_set(void __iomem *addr, u32 mask) |
b21d18b5 MO |
203 | { |
204 | iowrite32(ioread32(addr) | mask, addr); | |
205 | } | |
206 | ||
526de53c | 207 | static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) |
b21d18b5 MO |
208 | { |
209 | iowrite32(ioread32(addr) & ~mask, addr); | |
210 | } | |
211 | ||
212 | static void pch_can_set_run_mode(struct pch_can_priv *priv, | |
213 | enum pch_can_mode mode) | |
214 | { | |
215 | switch (mode) { | |
216 | case PCH_CAN_RUN: | |
086b5650 | 217 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); |
b21d18b5 MO |
218 | break; |
219 | ||
220 | case PCH_CAN_STOP: | |
086b5650 | 221 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); |
b21d18b5 MO |
222 | break; |
223 | ||
224 | default: | |
225 | dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); | |
226 | break; | |
227 | } | |
228 | } | |
229 | ||
230 | static void pch_can_set_optmode(struct pch_can_priv *priv) | |
231 | { | |
232 | u32 reg_val = ioread32(&priv->regs->opt); | |
233 | ||
234 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
086b5650 | 235 | reg_val |= PCH_OPT_SILENT; |
b21d18b5 MO |
236 | |
237 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
086b5650 | 238 | reg_val |= PCH_OPT_LBACK; |
b21d18b5 | 239 | |
086b5650 | 240 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); |
b21d18b5 MO |
241 | iowrite32(reg_val, &priv->regs->opt); |
242 | } | |
243 | ||
bd58cbc3 T |
244 | static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num) |
245 | { | |
246 | int counter = PCH_COUNTER_LIMIT; | |
247 | u32 ifx_creq; | |
248 | ||
249 | iowrite32(num, creq_addr); | |
250 | while (counter) { | |
251 | ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; | |
252 | if (!ifx_creq) | |
253 | break; | |
254 | counter--; | |
255 | udelay(1); | |
256 | } | |
257 | if (!counter) | |
258 | pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); | |
259 | } | |
260 | ||
b21d18b5 MO |
261 | static void pch_can_set_int_enables(struct pch_can_priv *priv, |
262 | enum pch_can_mode interrupt_no) | |
263 | { | |
264 | switch (interrupt_no) { | |
b21d18b5 | 265 | case PCH_CAN_DISABLE: |
086b5650 | 266 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); |
b21d18b5 MO |
267 | break; |
268 | ||
269 | case PCH_CAN_ALL: | |
086b5650 | 270 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
b21d18b5 MO |
271 | break; |
272 | ||
273 | case PCH_CAN_NONE: | |
086b5650 | 274 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
b21d18b5 MO |
275 | break; |
276 | ||
277 | default: | |
278 | dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); | |
279 | break; | |
280 | } | |
281 | } | |
282 | ||
8339a7ed | 283 | static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, |
bd58cbc3 | 284 | int set, enum pch_ifreg dir) |
b21d18b5 | 285 | { |
8339a7ed T |
286 | u32 ie; |
287 | ||
288 | if (dir) | |
289 | ie = PCH_IF_MCONT_TXIE; | |
290 | else | |
291 | ie = PCH_IF_MCONT_RXIE; | |
b21d18b5 | 292 | |
b21d18b5 | 293 | /* Reading the receive buffer data from RAM to Interface1 registers */ |
8339a7ed | 294 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
bd58cbc3 | 295 | pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); |
b21d18b5 MO |
296 | |
297 | /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ | |
086b5650 | 298 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
8339a7ed | 299 | &priv->regs->ifregs[dir].cmask); |
b21d18b5 | 300 | |
bd58cbc3 | 301 | if (set) { |
b21d18b5 | 302 | /* Setting the MsgVal and RxIE bits */ |
8339a7ed T |
303 | pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); |
304 | pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); | |
b21d18b5 | 305 | |
bd58cbc3 | 306 | } else { |
b21d18b5 | 307 | /* Resetting the MsgVal and RxIE bits */ |
8339a7ed T |
308 | pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); |
309 | pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); | |
b21d18b5 MO |
310 | } |
311 | ||
bd58cbc3 | 312 | pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); |
b21d18b5 MO |
313 | } |
314 | ||
bd58cbc3 | 315 | static void pch_can_set_rx_all(struct pch_can_priv *priv, int set) |
b21d18b5 MO |
316 | { |
317 | int i; | |
318 | ||
319 | /* Traversing to obtain the object configured as receivers. */ | |
15ffc8fd T |
320 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) |
321 | pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); | |
b21d18b5 MO |
322 | } |
323 | ||
bd58cbc3 | 324 | static void pch_can_set_tx_all(struct pch_can_priv *priv, int set) |
b21d18b5 MO |
325 | { |
326 | int i; | |
327 | ||
328 | /* Traversing to obtain the object configured as transmit object. */ | |
15ffc8fd T |
329 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
330 | pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); | |
b21d18b5 MO |
331 | } |
332 | ||
bd58cbc3 | 333 | static u32 pch_can_int_pending(struct pch_can_priv *priv) |
b21d18b5 MO |
334 | { |
335 | return ioread32(&priv->regs->intr) & 0xffff; | |
336 | } | |
337 | ||
bd58cbc3 | 338 | static void pch_can_clear_if_buffers(struct pch_can_priv *priv) |
b21d18b5 | 339 | { |
bd58cbc3 | 340 | int i; /* Msg Obj ID (1~32) */ |
b21d18b5 | 341 | |
bd58cbc3 | 342 | for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
8339a7ed T |
343 | iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); |
344 | iowrite32(0xffff, &priv->regs->ifregs[0].mask1); | |
345 | iowrite32(0xffff, &priv->regs->ifregs[0].mask2); | |
346 | iowrite32(0x0, &priv->regs->ifregs[0].id1); | |
347 | iowrite32(0x0, &priv->regs->ifregs[0].id2); | |
348 | iowrite32(0x0, &priv->regs->ifregs[0].mcont); | |
8ac9702b T |
349 | iowrite32(0x0, &priv->regs->ifregs[0].data[0]); |
350 | iowrite32(0x0, &priv->regs->ifregs[0].data[1]); | |
351 | iowrite32(0x0, &priv->regs->ifregs[0].data[2]); | |
352 | iowrite32(0x0, &priv->regs->ifregs[0].data[3]); | |
086b5650 T |
353 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
354 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
8339a7ed | 355 | &priv->regs->ifregs[0].cmask); |
bd58cbc3 | 356 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); |
b21d18b5 MO |
357 | } |
358 | } | |
359 | ||
360 | static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) | |
361 | { | |
362 | int i; | |
b21d18b5 | 363 | |
15ffc8fd T |
364 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
365 | iowrite32(PCH_CMASK_RX_TX_GET, | |
366 | &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 367 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); |
b21d18b5 | 368 | |
15ffc8fd T |
369 | iowrite32(0x0, &priv->regs->ifregs[0].id1); |
370 | iowrite32(0x0, &priv->regs->ifregs[0].id2); | |
b21d18b5 | 371 | |
15ffc8fd T |
372 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, |
373 | PCH_IF_MCONT_UMASK); | |
b21d18b5 | 374 | |
15ffc8fd T |
375 | /* Set FIFO mode set to 0 except last Rx Obj*/ |
376 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
377 | PCH_IF_MCONT_EOB); | |
378 | /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ | |
379 | if (i == PCH_RX_OBJ_END) | |
380 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, | |
bd58cbc3 T |
381 | PCH_IF_MCONT_EOB); |
382 | else | |
383 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
086b5650 | 384 | PCH_IF_MCONT_EOB); |
b21d18b5 | 385 | |
15ffc8fd T |
386 | iowrite32(0, &priv->regs->ifregs[0].mask1); |
387 | pch_can_bit_clear(&priv->regs->ifregs[0].mask2, | |
388 | 0x1fff | PCH_MASK2_MDIR_MXTD); | |
b21d18b5 | 389 | |
15ffc8fd T |
390 | /* Setting CMASK for writing */ |
391 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | | |
392 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
393 | &priv->regs->ifregs[0].cmask); | |
b21d18b5 | 394 | |
bd58cbc3 | 395 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); |
15ffc8fd | 396 | } |
b21d18b5 | 397 | |
15ffc8fd T |
398 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
399 | iowrite32(PCH_CMASK_RX_TX_GET, | |
400 | &priv->regs->ifregs[1].cmask); | |
bd58cbc3 | 401 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); |
b21d18b5 | 402 | |
15ffc8fd T |
403 | /* Resetting DIR bit for reception */ |
404 | iowrite32(0x0, &priv->regs->ifregs[1].id1); | |
405 | iowrite32(0x0, &priv->regs->ifregs[1].id2); | |
406 | pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); | |
b21d18b5 | 407 | |
15ffc8fd T |
408 | /* Setting EOB bit for transmitter */ |
409 | iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); | |
b21d18b5 | 410 | |
15ffc8fd T |
411 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, |
412 | PCH_IF_MCONT_UMASK); | |
413 | ||
414 | iowrite32(0, &priv->regs->ifregs[1].mask1); | |
415 | pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); | |
416 | ||
417 | /* Setting CMASK for writing */ | |
418 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | | |
419 | PCH_CMASK_ARB | PCH_CMASK_CTRL, | |
420 | &priv->regs->ifregs[1].cmask); | |
421 | ||
bd58cbc3 | 422 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); |
b21d18b5 | 423 | } |
b21d18b5 MO |
424 | } |
425 | ||
426 | static void pch_can_init(struct pch_can_priv *priv) | |
427 | { | |
428 | /* Stopping the Can device. */ | |
429 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
430 | ||
431 | /* Clearing all the message object buffers. */ | |
bd58cbc3 | 432 | pch_can_clear_if_buffers(priv); |
b21d18b5 MO |
433 | |
434 | /* Configuring the respective message object as either rx/tx object. */ | |
435 | pch_can_config_rx_tx_buffers(priv); | |
436 | ||
437 | /* Enabling the interrupts. */ | |
438 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
439 | } | |
440 | ||
441 | static void pch_can_release(struct pch_can_priv *priv) | |
442 | { | |
443 | /* Stooping the CAN device. */ | |
444 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
445 | ||
446 | /* Disabling the interrupts. */ | |
447 | pch_can_set_int_enables(priv, PCH_CAN_NONE); | |
448 | ||
449 | /* Disabling all the receive object. */ | |
8339a7ed | 450 | pch_can_set_rx_all(priv, 0); |
b21d18b5 MO |
451 | |
452 | /* Disabling all the transmit object. */ | |
8339a7ed | 453 | pch_can_set_tx_all(priv, 0); |
b21d18b5 MO |
454 | } |
455 | ||
456 | /* This function clears interrupt(s) from the CAN device. */ | |
457 | static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) | |
458 | { | |
086b5650 | 459 | if (mask == PCH_STATUS_INT) { |
b21d18b5 MO |
460 | ioread32(&priv->regs->stat); |
461 | return; | |
462 | } | |
463 | ||
464 | /* Clear interrupt for transmit object */ | |
15ffc8fd T |
465 | if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { |
466 | /* Setting CMASK for clearing the reception interrupts. */ | |
467 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, | |
468 | &priv->regs->ifregs[0].cmask); | |
469 | ||
470 | /* Clearing the Dir bit. */ | |
471 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); | |
472 | ||
473 | /* Clearing NewDat & IntPnd */ | |
474 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
475 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); | |
476 | ||
bd58cbc3 | 477 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask); |
15ffc8fd | 478 | } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { |
b21d18b5 MO |
479 | /* Setting CMASK for clearing interrupts for |
480 | frame transmission. */ | |
086b5650 | 481 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, |
8339a7ed | 482 | &priv->regs->ifregs[1].cmask); |
b21d18b5 MO |
483 | |
484 | /* Resetting the ID registers. */ | |
8339a7ed | 485 | pch_can_bit_set(&priv->regs->ifregs[1].id2, |
086b5650 | 486 | PCH_ID2_DIR | (0x7ff << 2)); |
8339a7ed | 487 | iowrite32(0x0, &priv->regs->ifregs[1].id1); |
b21d18b5 MO |
488 | |
489 | /* Claring NewDat, TxRqst & IntPnd */ | |
8339a7ed | 490 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
086b5650 T |
491 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
492 | PCH_IF_MCONT_TXRQXT); | |
bd58cbc3 | 493 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask); |
b21d18b5 MO |
494 | } |
495 | } | |
496 | ||
b21d18b5 MO |
497 | static void pch_can_reset(struct pch_can_priv *priv) |
498 | { | |
499 | /* write to sw reset register */ | |
500 | iowrite32(1, &priv->regs->srst); | |
501 | iowrite32(0, &priv->regs->srst); | |
502 | } | |
503 | ||
504 | static void pch_can_error(struct net_device *ndev, u32 status) | |
505 | { | |
506 | struct sk_buff *skb; | |
507 | struct pch_can_priv *priv = netdev_priv(ndev); | |
508 | struct can_frame *cf; | |
d68f6837 | 509 | u32 errc, lec; |
b21d18b5 MO |
510 | struct net_device_stats *stats = &(priv->ndev->stats); |
511 | enum can_state state = priv->can.state; | |
512 | ||
513 | skb = alloc_can_err_skb(ndev, &cf); | |
514 | if (!skb) | |
515 | return; | |
516 | ||
517 | if (status & PCH_BUS_OFF) { | |
8339a7ed T |
518 | pch_can_set_tx_all(priv, 0); |
519 | pch_can_set_rx_all(priv, 0); | |
b21d18b5 MO |
520 | state = CAN_STATE_BUS_OFF; |
521 | cf->can_id |= CAN_ERR_BUSOFF; | |
522 | can_bus_off(ndev); | |
523 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
524 | dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); | |
525 | } | |
526 | ||
527 | /* Warning interrupt. */ | |
528 | if (status & PCH_EWARN) { | |
529 | state = CAN_STATE_ERROR_WARNING; | |
530 | priv->can.can_stats.error_warning++; | |
531 | cf->can_id |= CAN_ERR_CRTL; | |
532 | errc = ioread32(&priv->regs->errc); | |
086b5650 | 533 | if (((errc & PCH_REC) >> 8) > 96) |
b21d18b5 | 534 | cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; |
086b5650 | 535 | if ((errc & PCH_TEC) > 96) |
b21d18b5 MO |
536 | cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; |
537 | dev_warn(&ndev->dev, | |
538 | "%s -> Error Counter is more than 96.\n", __func__); | |
539 | } | |
540 | /* Error passive interrupt. */ | |
541 | if (status & PCH_EPASSIV) { | |
542 | priv->can.can_stats.error_passive++; | |
543 | state = CAN_STATE_ERROR_PASSIVE; | |
544 | cf->can_id |= CAN_ERR_CRTL; | |
545 | errc = ioread32(&priv->regs->errc); | |
086b5650 | 546 | if (((errc & PCH_REC) >> 8) > 127) |
b21d18b5 | 547 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; |
086b5650 | 548 | if ((errc & PCH_TEC) > 127) |
b21d18b5 MO |
549 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; |
550 | dev_err(&ndev->dev, | |
551 | "%s -> CAN controller is ERROR PASSIVE .\n", __func__); | |
552 | } | |
553 | ||
d68f6837 T |
554 | lec = status & PCH_LEC_ALL; |
555 | switch (lec) { | |
556 | case PCH_STUF_ERR: | |
557 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
b21d18b5 MO |
558 | priv->can.can_stats.bus_error++; |
559 | stats->rx_errors++; | |
d68f6837 T |
560 | break; |
561 | case PCH_FORM_ERR: | |
562 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
563 | priv->can.can_stats.bus_error++; | |
564 | stats->rx_errors++; | |
565 | break; | |
566 | case PCH_ACK_ERR: | |
567 | cf->can_id |= CAN_ERR_ACK; | |
568 | priv->can.can_stats.bus_error++; | |
569 | stats->rx_errors++; | |
570 | break; | |
571 | case PCH_BIT1_ERR: | |
572 | case PCH_BIT0_ERR: | |
573 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
574 | priv->can.can_stats.bus_error++; | |
575 | stats->rx_errors++; | |
576 | break; | |
577 | case PCH_CRC_ERR: | |
578 | cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | | |
579 | CAN_ERR_PROT_LOC_CRC_DEL; | |
580 | priv->can.can_stats.bus_error++; | |
581 | stats->rx_errors++; | |
582 | break; | |
583 | case PCH_LEC_ALL: /* Written by CPU. No error status */ | |
584 | break; | |
b21d18b5 MO |
585 | } |
586 | ||
587 | priv->can.state = state; | |
588 | netif_rx(skb); | |
589 | ||
590 | stats->rx_packets++; | |
591 | stats->rx_bytes += cf->can_dlc; | |
592 | } | |
593 | ||
594 | static irqreturn_t pch_can_interrupt(int irq, void *dev_id) | |
595 | { | |
596 | struct net_device *ndev = (struct net_device *)dev_id; | |
597 | struct pch_can_priv *priv = netdev_priv(ndev); | |
598 | ||
599 | pch_can_set_int_enables(priv, PCH_CAN_NONE); | |
600 | ||
601 | napi_schedule(&priv->napi); | |
602 | ||
603 | return IRQ_HANDLED; | |
604 | } | |
605 | ||
1d5b4b27 T |
606 | static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id) |
607 | { | |
608 | if (obj_id < PCH_FIFO_THRESH) { | |
609 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | | |
610 | PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); | |
611 | ||
612 | /* Clearing the Dir bit. */ | |
613 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); | |
614 | ||
615 | /* Clearing NewDat & IntPnd */ | |
616 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
617 | PCH_IF_MCONT_INTPND); | |
bd58cbc3 | 618 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); |
1d5b4b27 T |
619 | } else if (obj_id > PCH_FIFO_THRESH) { |
620 | pch_can_int_clr(priv, obj_id); | |
621 | } else if (obj_id == PCH_FIFO_THRESH) { | |
622 | int cnt; | |
623 | for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) | |
624 | pch_can_int_clr(priv, cnt + 1); | |
625 | } | |
626 | } | |
627 | ||
628 | static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id) | |
629 | { | |
630 | struct pch_can_priv *priv = netdev_priv(ndev); | |
631 | struct net_device_stats *stats = &(priv->ndev->stats); | |
632 | struct sk_buff *skb; | |
633 | struct can_frame *cf; | |
634 | ||
635 | netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n"); | |
636 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, | |
637 | PCH_IF_MCONT_MSGLOST); | |
638 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, | |
639 | &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 640 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); |
1d5b4b27 T |
641 | |
642 | skb = alloc_can_err_skb(ndev, &cf); | |
643 | if (!skb) | |
644 | return; | |
645 | ||
646 | cf->can_id |= CAN_ERR_CRTL; | |
647 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
648 | stats->rx_over_errors++; | |
649 | stats->rx_errors++; | |
650 | ||
651 | netif_receive_skb(skb); | |
652 | } | |
653 | ||
654 | static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota) | |
b21d18b5 MO |
655 | { |
656 | u32 reg; | |
657 | canid_t id; | |
b21d18b5 MO |
658 | int rcv_pkts = 0; |
659 | struct sk_buff *skb; | |
660 | struct can_frame *cf; | |
661 | struct pch_can_priv *priv = netdev_priv(ndev); | |
662 | struct net_device_stats *stats = &(priv->ndev->stats); | |
1d5b4b27 T |
663 | int i; |
664 | u32 id2; | |
8ac9702b | 665 | u16 data_reg; |
b21d18b5 | 666 | |
1d5b4b27 T |
667 | do { |
668 | /* Reading the messsage object from the Message RAM */ | |
669 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 670 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num); |
b21d18b5 | 671 | |
1d5b4b27 T |
672 | /* Reading the MCONT register. */ |
673 | reg = ioread32(&priv->regs->ifregs[0].mcont); | |
674 | ||
675 | if (reg & PCH_IF_MCONT_EOB) | |
676 | break; | |
b21d18b5 | 677 | |
b21d18b5 | 678 | /* If MsgLost bit set. */ |
086b5650 | 679 | if (reg & PCH_IF_MCONT_MSGLOST) { |
1d5b4b27 | 680 | pch_can_rx_msg_lost(ndev, obj_num); |
b21d18b5 | 681 | rcv_pkts++; |
1d5b4b27 T |
682 | quota--; |
683 | obj_num++; | |
684 | continue; | |
685 | } else if (!(reg & PCH_IF_MCONT_NEWDAT)) { | |
686 | obj_num++; | |
687 | continue; | |
b21d18b5 | 688 | } |
b21d18b5 MO |
689 | |
690 | skb = alloc_can_skb(priv->ndev, &cf); | |
691 | if (!skb) | |
692 | return -ENOMEM; | |
693 | ||
694 | /* Get Received data */ | |
1d5b4b27 T |
695 | id2 = ioread32(&priv->regs->ifregs[0].id2); |
696 | if (id2 & PCH_ID2_XTD) { | |
8339a7ed | 697 | id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); |
1d5b4b27 T |
698 | id |= (((id2) & 0x1fff) << 16); |
699 | cf->can_id = id | CAN_EFF_FLAG; | |
b21d18b5 | 700 | } else { |
1d5b4b27 T |
701 | id = (id2 >> 2) & CAN_SFF_MASK; |
702 | cf->can_id = id; | |
b21d18b5 MO |
703 | } |
704 | ||
1d5b4b27 | 705 | if (id2 & PCH_ID2_DIR) |
b21d18b5 | 706 | cf->can_id |= CAN_RTR_FLAG; |
1d5b4b27 T |
707 | |
708 | cf->can_dlc = get_can_dlc((ioread32(&priv->regs-> | |
709 | ifregs[0].mcont)) & 0xF); | |
b21d18b5 | 710 | |
8ac9702b T |
711 | for (i = 0; i < cf->can_dlc; i += 2) { |
712 | data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]); | |
713 | cf->data[i] = data_reg; | |
714 | cf->data[i + 1] = data_reg >> 8; | |
b21d18b5 MO |
715 | } |
716 | ||
717 | netif_receive_skb(skb); | |
718 | rcv_pkts++; | |
719 | stats->rx_packets++; | |
1d5b4b27 | 720 | quota--; |
b21d18b5 MO |
721 | stats->rx_bytes += cf->can_dlc; |
722 | ||
1d5b4b27 T |
723 | pch_fifo_thresh(priv, obj_num); |
724 | obj_num++; | |
725 | } while (quota > 0); | |
b21d18b5 MO |
726 | |
727 | return rcv_pkts; | |
728 | } | |
e489cceb T |
729 | |
730 | static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat) | |
b21d18b5 | 731 | { |
b21d18b5 MO |
732 | struct pch_can_priv *priv = netdev_priv(ndev); |
733 | struct net_device_stats *stats = &(priv->ndev->stats); | |
734 | u32 dlc; | |
e489cceb T |
735 | |
736 | can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); | |
737 | iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, | |
738 | &priv->regs->ifregs[1].cmask); | |
bd58cbc3 | 739 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat); |
e489cceb T |
740 | dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) & |
741 | PCH_IF_MCONT_DLC); | |
742 | stats->tx_bytes += dlc; | |
743 | stats->tx_packets++; | |
744 | if (int_stat == PCH_TX_OBJ_END) | |
745 | netif_wake_queue(ndev); | |
746 | } | |
747 | ||
bd58cbc3 | 748 | static int pch_can_poll(struct napi_struct *napi, int quota) |
e489cceb T |
749 | { |
750 | struct net_device *ndev = napi->dev; | |
751 | struct pch_can_priv *priv = netdev_priv(ndev); | |
b21d18b5 MO |
752 | u32 int_stat; |
753 | int rcv_pkts = 0; | |
754 | u32 reg_stat; | |
b21d18b5 MO |
755 | |
756 | int_stat = pch_can_int_pending(priv); | |
757 | if (!int_stat) | |
e489cceb | 758 | goto end; |
b21d18b5 | 759 | |
e489cceb | 760 | if ((int_stat == PCH_STATUS_INT) && (quota > 0)) { |
b21d18b5 MO |
761 | reg_stat = ioread32(&priv->regs->stat); |
762 | if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { | |
e489cceb T |
763 | if (reg_stat & PCH_BUS_OFF || |
764 | (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) { | |
b21d18b5 | 765 | pch_can_error(ndev, reg_stat); |
e489cceb T |
766 | quota--; |
767 | } | |
b21d18b5 MO |
768 | } |
769 | ||
e489cceb | 770 | if (reg_stat & PCH_TX_OK) |
b21d18b5 | 771 | pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); |
b21d18b5 MO |
772 | |
773 | if (reg_stat & PCH_RX_OK) | |
774 | pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); | |
775 | ||
776 | int_stat = pch_can_int_pending(priv); | |
b21d18b5 MO |
777 | } |
778 | ||
e489cceb T |
779 | if (quota == 0) |
780 | goto end; | |
781 | ||
15ffc8fd | 782 | if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { |
1d5b4b27 | 783 | rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota); |
e489cceb T |
784 | quota -= rcv_pkts; |
785 | if (quota < 0) | |
786 | goto end; | |
15ffc8fd T |
787 | } else if ((int_stat >= PCH_TX_OBJ_START) && |
788 | (int_stat <= PCH_TX_OBJ_END)) { | |
789 | /* Handle transmission interrupt */ | |
e489cceb | 790 | pch_can_tx_complete(ndev, int_stat); |
b21d18b5 MO |
791 | } |
792 | ||
e489cceb | 793 | end: |
b21d18b5 MO |
794 | napi_complete(napi); |
795 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
796 | ||
797 | return rcv_pkts; | |
798 | } | |
799 | ||
800 | static int pch_set_bittiming(struct net_device *ndev) | |
801 | { | |
802 | struct pch_can_priv *priv = netdev_priv(ndev); | |
803 | const struct can_bittiming *bt = &priv->can.bittiming; | |
804 | u32 canbit; | |
805 | u32 bepe; | |
806 | u32 brp; | |
807 | ||
808 | /* Setting the CCE bit for accessing the Can Timing register. */ | |
086b5650 | 809 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); |
b21d18b5 MO |
810 | |
811 | brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; | |
086b5650 | 812 | canbit = brp & PCH_MSK_BITT_BRP; |
bd58cbc3 T |
813 | canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT; |
814 | canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT; | |
815 | canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT; | |
816 | bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT; | |
b21d18b5 MO |
817 | iowrite32(canbit, &priv->regs->bitt); |
818 | iowrite32(bepe, &priv->regs->brpe); | |
086b5650 | 819 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); |
b21d18b5 MO |
820 | |
821 | return 0; | |
822 | } | |
823 | ||
824 | static void pch_can_start(struct net_device *ndev) | |
825 | { | |
826 | struct pch_can_priv *priv = netdev_priv(ndev); | |
827 | ||
828 | if (priv->can.state != CAN_STATE_STOPPED) | |
829 | pch_can_reset(priv); | |
830 | ||
831 | pch_set_bittiming(ndev); | |
832 | pch_can_set_optmode(priv); | |
833 | ||
8339a7ed T |
834 | pch_can_set_tx_all(priv, 1); |
835 | pch_can_set_rx_all(priv, 1); | |
b21d18b5 MO |
836 | |
837 | /* Setting the CAN to run mode. */ | |
838 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
839 | ||
840 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
841 | ||
842 | return; | |
843 | } | |
844 | ||
845 | static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) | |
846 | { | |
847 | int ret = 0; | |
848 | ||
849 | switch (mode) { | |
850 | case CAN_MODE_START: | |
851 | pch_can_start(ndev); | |
852 | netif_wake_queue(ndev); | |
853 | break; | |
854 | default: | |
855 | ret = -EOPNOTSUPP; | |
856 | break; | |
857 | } | |
858 | ||
859 | return ret; | |
860 | } | |
861 | ||
862 | static int pch_can_open(struct net_device *ndev) | |
863 | { | |
864 | struct pch_can_priv *priv = netdev_priv(ndev); | |
865 | int retval; | |
866 | ||
867 | retval = pci_enable_msi(priv->dev); | |
868 | if (retval) { | |
869 | dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); | |
870 | priv->use_msi = 0; | |
871 | } else { | |
872 | dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); | |
873 | priv->use_msi = 1; | |
874 | } | |
875 | ||
876 | /* Regsitering the interrupt. */ | |
877 | retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, | |
878 | ndev->name, ndev); | |
879 | if (retval) { | |
880 | dev_err(&ndev->dev, "request_irq failed.\n"); | |
881 | goto req_irq_err; | |
882 | } | |
883 | ||
884 | /* Open common can device */ | |
885 | retval = open_candev(ndev); | |
886 | if (retval) { | |
887 | dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); | |
888 | goto err_open_candev; | |
889 | } | |
890 | ||
891 | pch_can_init(priv); | |
892 | pch_can_start(ndev); | |
893 | napi_enable(&priv->napi); | |
894 | netif_start_queue(ndev); | |
895 | ||
896 | return 0; | |
897 | ||
898 | err_open_candev: | |
899 | free_irq(priv->dev->irq, ndev); | |
900 | req_irq_err: | |
901 | if (priv->use_msi) | |
902 | pci_disable_msi(priv->dev); | |
903 | ||
904 | pch_can_release(priv); | |
905 | ||
906 | return retval; | |
907 | } | |
908 | ||
909 | static int pch_close(struct net_device *ndev) | |
910 | { | |
911 | struct pch_can_priv *priv = netdev_priv(ndev); | |
912 | ||
913 | netif_stop_queue(ndev); | |
914 | napi_disable(&priv->napi); | |
915 | pch_can_release(priv); | |
916 | free_irq(priv->dev->irq, ndev); | |
917 | if (priv->use_msi) | |
918 | pci_disable_msi(priv->dev); | |
919 | close_candev(ndev); | |
920 | priv->can.state = CAN_STATE_STOPPED; | |
921 | return 0; | |
922 | } | |
923 | ||
b21d18b5 MO |
924 | static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) |
925 | { | |
b21d18b5 MO |
926 | struct pch_can_priv *priv = netdev_priv(ndev); |
927 | struct can_frame *cf = (struct can_frame *)skb->data; | |
bd58cbc3 | 928 | int tx_obj_no; |
8ac9702b | 929 | int i; |
b21d18b5 MO |
930 | |
931 | if (can_dropped_invalid_skb(ndev, skb)) | |
932 | return NETDEV_TX_OK; | |
933 | ||
76d94b23 T |
934 | if (priv->tx_obj == PCH_TX_OBJ_END) { |
935 | if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) | |
936 | netif_stop_queue(ndev); | |
b21d18b5 | 937 | |
bd58cbc3 | 938 | tx_obj_no = priv->tx_obj; |
76d94b23 | 939 | priv->tx_obj = PCH_TX_OBJ_START; |
b21d18b5 | 940 | } else { |
bd58cbc3 | 941 | tx_obj_no = priv->tx_obj; |
76d94b23 | 942 | priv->tx_obj++; |
b21d18b5 | 943 | } |
b21d18b5 | 944 | |
b21d18b5 | 945 | /* Reading the Msg Obj from the Msg RAM to the Interface register. */ |
8339a7ed | 946 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); |
bd58cbc3 | 947 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no); |
b21d18b5 MO |
948 | |
949 | /* Setting the CMASK register. */ | |
8339a7ed | 950 | pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); |
b21d18b5 MO |
951 | |
952 | /* If ID extended is set. */ | |
8339a7ed T |
953 | pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); |
954 | pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); | |
b21d18b5 | 955 | if (cf->can_id & CAN_EFF_FLAG) { |
8339a7ed T |
956 | pch_can_bit_set(&priv->regs->ifregs[1].id1, |
957 | cf->can_id & 0xffff); | |
958 | pch_can_bit_set(&priv->regs->ifregs[1].id2, | |
086b5650 | 959 | ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); |
b21d18b5 | 960 | } else { |
8339a7ed T |
961 | pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); |
962 | pch_can_bit_set(&priv->regs->ifregs[1].id2, | |
b21d18b5 MO |
963 | (cf->can_id & CAN_SFF_MASK) << 2); |
964 | } | |
965 | ||
966 | /* If remote frame has to be transmitted.. */ | |
967 | if (cf->can_id & CAN_RTR_FLAG) | |
8339a7ed | 968 | pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); |
b21d18b5 | 969 | |
8ac9702b T |
970 | /* Copy data to register */ |
971 | for (i = 0; i < cf->can_dlc; i += 2) { | |
972 | iowrite16(cf->data[i] | (cf->data[i + 1] << 8), | |
973 | &priv->regs->ifregs[1].data[i / 2]); | |
b21d18b5 MO |
974 | } |
975 | ||
bd58cbc3 | 976 | can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1); |
b21d18b5 MO |
977 | |
978 | /* Updating the size of the data. */ | |
8339a7ed T |
979 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); |
980 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); | |
b21d18b5 MO |
981 | |
982 | /* Clearing IntPend, NewDat & TxRqst */ | |
8339a7ed | 983 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
086b5650 T |
984 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
985 | PCH_IF_MCONT_TXRQXT); | |
b21d18b5 MO |
986 | |
987 | /* Setting NewDat, TxRqst bits */ | |
8339a7ed | 988 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, |
086b5650 | 989 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); |
b21d18b5 | 990 | |
bd58cbc3 | 991 | pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no); |
b21d18b5 | 992 | |
b21d18b5 MO |
993 | return NETDEV_TX_OK; |
994 | } | |
995 | ||
996 | static const struct net_device_ops pch_can_netdev_ops = { | |
997 | .ndo_open = pch_can_open, | |
998 | .ndo_stop = pch_close, | |
999 | .ndo_start_xmit = pch_xmit, | |
1000 | }; | |
1001 | ||
1002 | static void __devexit pch_can_remove(struct pci_dev *pdev) | |
1003 | { | |
1004 | struct net_device *ndev = pci_get_drvdata(pdev); | |
1005 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1006 | ||
1007 | unregister_candev(priv->ndev); | |
1008 | free_candev(priv->ndev); | |
1009 | pci_iounmap(pdev, priv->regs); | |
1010 | pci_release_regions(pdev); | |
1011 | pci_disable_device(pdev); | |
1012 | pci_set_drvdata(pdev, NULL); | |
1013 | pch_can_reset(priv); | |
1014 | } | |
1015 | ||
1016 | #ifdef CONFIG_PM | |
7f2bc50e T |
1017 | static void pch_can_set_int_custom(struct pch_can_priv *priv) |
1018 | { | |
1019 | /* Clearing the IE, SIE and EIE bits of Can control register. */ | |
1020 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); | |
1021 | ||
1022 | /* Appropriately setting them. */ | |
1023 | pch_can_bit_set(&priv->regs->cont, | |
1024 | ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); | |
1025 | } | |
1026 | ||
1027 | /* This function retrieves interrupt enabled for the CAN device. */ | |
1028 | static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) | |
1029 | { | |
1030 | /* Obtaining the status of IE, SIE and EIE interrupt bits. */ | |
1031 | *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); | |
1032 | } | |
1033 | ||
1034 | static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, | |
1035 | enum pch_ifreg dir) | |
1036 | { | |
1037 | u32 ie, enable; | |
1038 | ||
1039 | if (dir) | |
1040 | ie = PCH_IF_MCONT_RXIE; | |
1041 | else | |
1042 | ie = PCH_IF_MCONT_TXIE; | |
1043 | ||
1044 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); | |
bd58cbc3 | 1045 | pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); |
7f2bc50e T |
1046 | |
1047 | if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && | |
1048 | ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { | |
1049 | enable = 1; | |
1050 | } else { | |
1051 | enable = 0; | |
1052 | } | |
1053 | return enable; | |
1054 | } | |
1055 | ||
1056 | static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, | |
bd58cbc3 | 1057 | u32 buffer_num, int set) |
7f2bc50e T |
1058 | { |
1059 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 1060 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
7f2bc50e T |
1061 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, |
1062 | &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 1063 | if (set) |
7f2bc50e T |
1064 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
1065 | PCH_IF_MCONT_EOB); | |
1066 | else | |
1067 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); | |
1068 | ||
bd58cbc3 | 1069 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
7f2bc50e T |
1070 | } |
1071 | ||
1072 | static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, | |
1073 | u32 buffer_num, u32 *link) | |
1074 | { | |
1075 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); | |
bd58cbc3 | 1076 | pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); |
7f2bc50e T |
1077 | |
1078 | if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) | |
bd58cbc3 | 1079 | *link = 0; |
7f2bc50e | 1080 | else |
bd58cbc3 | 1081 | *link = 1; |
7f2bc50e T |
1082 | } |
1083 | ||
1084 | static int pch_can_get_buffer_status(struct pch_can_priv *priv) | |
1085 | { | |
1086 | return (ioread32(&priv->regs->treq1) & 0xffff) | | |
bd58cbc3 | 1087 | (ioread32(&priv->regs->treq2) << 16); |
7f2bc50e T |
1088 | } |
1089 | ||
b21d18b5 MO |
1090 | static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) |
1091 | { | |
1092 | int i; /* Counter variable. */ | |
1093 | int retval; /* Return value. */ | |
1094 | u32 buf_stat; /* Variable for reading the transmit buffer status. */ | |
bd58cbc3 | 1095 | int counter = PCH_COUNTER_LIMIT; |
b21d18b5 MO |
1096 | |
1097 | struct net_device *dev = pci_get_drvdata(pdev); | |
1098 | struct pch_can_priv *priv = netdev_priv(dev); | |
1099 | ||
1100 | /* Stop the CAN controller */ | |
1101 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1102 | ||
1103 | /* Indicate that we are aboutto/in suspend */ | |
1104 | priv->can.state = CAN_STATE_SLEEPING; | |
1105 | ||
1106 | /* Waiting for all transmission to complete. */ | |
1107 | while (counter) { | |
1108 | buf_stat = pch_can_get_buffer_status(priv); | |
1109 | if (!buf_stat) | |
1110 | break; | |
1111 | counter--; | |
1112 | udelay(1); | |
1113 | } | |
1114 | if (!counter) | |
1115 | dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); | |
1116 | ||
1117 | /* Save interrupt configuration and then disable them */ | |
1118 | pch_can_get_int_enables(priv, &(priv->int_enables)); | |
1119 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); | |
1120 | ||
1121 | /* Save Tx buffer enable state */ | |
15ffc8fd T |
1122 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
1123 | priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); | |
b21d18b5 MO |
1124 | |
1125 | /* Disable all Transmit buffers */ | |
8339a7ed | 1126 | pch_can_set_tx_all(priv, 0); |
b21d18b5 MO |
1127 | |
1128 | /* Save Rx buffer enable state */ | |
15ffc8fd T |
1129 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
1130 | priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); | |
1131 | pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); | |
b21d18b5 MO |
1132 | } |
1133 | ||
1134 | /* Disable all Receive buffers */ | |
8339a7ed | 1135 | pch_can_set_rx_all(priv, 0); |
b21d18b5 MO |
1136 | retval = pci_save_state(pdev); |
1137 | if (retval) { | |
1138 | dev_err(&pdev->dev, "pci_save_state failed.\n"); | |
1139 | } else { | |
1140 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1141 | pci_disable_device(pdev); | |
1142 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1143 | } | |
1144 | ||
1145 | return retval; | |
1146 | } | |
1147 | ||
1148 | static int pch_can_resume(struct pci_dev *pdev) | |
1149 | { | |
1150 | int i; /* Counter variable. */ | |
1151 | int retval; /* Return variable. */ | |
1152 | struct net_device *dev = pci_get_drvdata(pdev); | |
1153 | struct pch_can_priv *priv = netdev_priv(dev); | |
1154 | ||
1155 | pci_set_power_state(pdev, PCI_D0); | |
1156 | pci_restore_state(pdev); | |
1157 | retval = pci_enable_device(pdev); | |
1158 | if (retval) { | |
1159 | dev_err(&pdev->dev, "pci_enable_device failed.\n"); | |
1160 | return retval; | |
1161 | } | |
1162 | ||
1163 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1164 | ||
1165 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1166 | ||
1167 | /* Disabling all interrupts. */ | |
1168 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); | |
1169 | ||
1170 | /* Setting the CAN device in Stop Mode. */ | |
1171 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1172 | ||
1173 | /* Configuring the transmit and receive buffers. */ | |
1174 | pch_can_config_rx_tx_buffers(priv); | |
1175 | ||
1176 | /* Restore the CAN state */ | |
1177 | pch_set_bittiming(dev); | |
1178 | ||
1179 | /* Listen/Active */ | |
1180 | pch_can_set_optmode(priv); | |
1181 | ||
1182 | /* Enabling the transmit buffer. */ | |
15ffc8fd T |
1183 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
1184 | pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); | |
b21d18b5 MO |
1185 | |
1186 | /* Configuring the receive buffer and enabling them. */ | |
15ffc8fd T |
1187 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
1188 | /* Restore buffer link */ | |
1189 | pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); | |
b21d18b5 | 1190 | |
15ffc8fd T |
1191 | /* Restore buffer enables */ |
1192 | pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); | |
b21d18b5 MO |
1193 | } |
1194 | ||
1195 | /* Enable CAN Interrupts */ | |
1196 | pch_can_set_int_custom(priv); | |
1197 | ||
1198 | /* Restore Run Mode */ | |
1199 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
1200 | ||
1201 | return retval; | |
1202 | } | |
1203 | #else | |
1204 | #define pch_can_suspend NULL | |
1205 | #define pch_can_resume NULL | |
1206 | #endif | |
1207 | ||
1208 | static int pch_can_get_berr_counter(const struct net_device *dev, | |
1209 | struct can_berr_counter *bec) | |
1210 | { | |
1211 | struct pch_can_priv *priv = netdev_priv(dev); | |
1212 | ||
086b5650 T |
1213 | bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; |
1214 | bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; | |
b21d18b5 MO |
1215 | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int __devinit pch_can_probe(struct pci_dev *pdev, | |
1220 | const struct pci_device_id *id) | |
1221 | { | |
1222 | struct net_device *ndev; | |
1223 | struct pch_can_priv *priv; | |
1224 | int rc; | |
b21d18b5 MO |
1225 | void __iomem *addr; |
1226 | ||
1227 | rc = pci_enable_device(pdev); | |
1228 | if (rc) { | |
1229 | dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); | |
1230 | goto probe_exit_endev; | |
1231 | } | |
1232 | ||
1233 | rc = pci_request_regions(pdev, KBUILD_MODNAME); | |
1234 | if (rc) { | |
1235 | dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); | |
1236 | goto probe_exit_pcireq; | |
1237 | } | |
1238 | ||
1239 | addr = pci_iomap(pdev, 1, 0); | |
1240 | if (!addr) { | |
1241 | rc = -EIO; | |
1242 | dev_err(&pdev->dev, "Failed pci_iomap\n"); | |
1243 | goto probe_exit_ipmap; | |
1244 | } | |
1245 | ||
15ffc8fd | 1246 | ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); |
b21d18b5 MO |
1247 | if (!ndev) { |
1248 | rc = -ENOMEM; | |
1249 | dev_err(&pdev->dev, "Failed alloc_candev\n"); | |
1250 | goto probe_exit_alloc_candev; | |
1251 | } | |
1252 | ||
1253 | priv = netdev_priv(ndev); | |
1254 | priv->ndev = ndev; | |
1255 | priv->regs = addr; | |
1256 | priv->dev = pdev; | |
1257 | priv->can.bittiming_const = &pch_can_bittiming_const; | |
1258 | priv->can.do_set_mode = pch_can_do_set_mode; | |
1259 | priv->can.do_get_berr_counter = pch_can_get_berr_counter; | |
1260 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | | |
1261 | CAN_CTRLMODE_LOOPBACK; | |
15ffc8fd | 1262 | priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ |
b21d18b5 MO |
1263 | |
1264 | ndev->irq = pdev->irq; | |
1265 | ndev->flags |= IFF_ECHO; | |
1266 | ||
1267 | pci_set_drvdata(pdev, ndev); | |
1268 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1269 | ndev->netdev_ops = &pch_can_netdev_ops; | |
b21d18b5 | 1270 | priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ |
b21d18b5 | 1271 | |
bd58cbc3 | 1272 | netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END); |
b21d18b5 MO |
1273 | |
1274 | rc = register_candev(ndev); | |
1275 | if (rc) { | |
1276 | dev_err(&pdev->dev, "Failed register_candev %d\n", rc); | |
1277 | goto probe_exit_reg_candev; | |
1278 | } | |
1279 | ||
1280 | return 0; | |
1281 | ||
1282 | probe_exit_reg_candev: | |
1283 | free_candev(ndev); | |
1284 | probe_exit_alloc_candev: | |
1285 | pci_iounmap(pdev, addr); | |
1286 | probe_exit_ipmap: | |
1287 | pci_release_regions(pdev); | |
1288 | probe_exit_pcireq: | |
1289 | pci_disable_device(pdev); | |
1290 | probe_exit_endev: | |
1291 | return rc; | |
1292 | } | |
1293 | ||
bdfa3d8f | 1294 | static struct pci_driver pch_can_pci_driver = { |
b21d18b5 MO |
1295 | .name = "pch_can", |
1296 | .id_table = pch_pci_tbl, | |
1297 | .probe = pch_can_probe, | |
1298 | .remove = __devexit_p(pch_can_remove), | |
1299 | .suspend = pch_can_suspend, | |
1300 | .resume = pch_can_resume, | |
1301 | }; | |
1302 | ||
1303 | static int __init pch_can_pci_init(void) | |
1304 | { | |
bdfa3d8f | 1305 | return pci_register_driver(&pch_can_pci_driver); |
b21d18b5 MO |
1306 | } |
1307 | module_init(pch_can_pci_init); | |
1308 | ||
1309 | static void __exit pch_can_pci_exit(void) | |
1310 | { | |
bdfa3d8f | 1311 | pci_unregister_driver(&pch_can_pci_driver); |
b21d18b5 MO |
1312 | } |
1313 | module_exit(pch_can_pci_exit); | |
1314 | ||
1315 | MODULE_DESCRIPTION("Controller Area Network Driver"); | |
1316 | MODULE_LICENSE("GPL v2"); | |
1317 | MODULE_VERSION("0.94"); |