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fd115931 SS |
1 | /* Renesas R-Car CAN device driver |
2 | * | |
3 | * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/can/led.h> | |
20 | #include <linux/can/dev.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/can/platform/rcar_can.h> | |
a268de6c | 23 | #include <linux/of.h> |
fd115931 SS |
24 | |
25 | #define RCAR_CAN_DRV_NAME "rcar_can" | |
26 | ||
27 | /* Mailbox configuration: | |
28 | * mailbox 60 - 63 - Rx FIFO mailboxes | |
29 | * mailbox 56 - 59 - Tx FIFO mailboxes | |
30 | * non-FIFO mailboxes are not used | |
31 | */ | |
32 | #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ | |
33 | #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ | |
34 | #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ | |
35 | #define RCAR_CAN_FIFO_DEPTH 4 | |
36 | ||
37 | /* Mailbox registers structure */ | |
38 | struct rcar_can_mbox_regs { | |
39 | u32 id; /* IDE and RTR bits, SID and EID */ | |
40 | u8 stub; /* Not used */ | |
41 | u8 dlc; /* Data Length Code - bits [0..3] */ | |
42 | u8 data[8]; /* Data Bytes */ | |
43 | u8 tsh; /* Time Stamp Higher Byte */ | |
44 | u8 tsl; /* Time Stamp Lower Byte */ | |
45 | }; | |
46 | ||
47 | struct rcar_can_regs { | |
48 | struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ | |
49 | u32 mkr_2_9[8]; /* Mask Registers 2-9 */ | |
50 | u32 fidcr[2]; /* FIFO Received ID Compare Register */ | |
51 | u32 mkivlr1; /* Mask Invalid Register 1 */ | |
52 | u32 mier1; /* Mailbox Interrupt Enable Register 1 */ | |
53 | u32 mkr_0_1[2]; /* Mask Registers 0-1 */ | |
54 | u32 mkivlr0; /* Mask Invalid Register 0*/ | |
55 | u32 mier0; /* Mailbox Interrupt Enable Register 0 */ | |
56 | u8 pad_440[0x3c0]; | |
57 | u8 mctl[64]; /* Message Control Registers */ | |
58 | u16 ctlr; /* Control Register */ | |
59 | u16 str; /* Status register */ | |
60 | u8 bcr[3]; /* Bit Configuration Register */ | |
61 | u8 clkr; /* Clock Select Register */ | |
62 | u8 rfcr; /* Receive FIFO Control Register */ | |
63 | u8 rfpcr; /* Receive FIFO Pointer Control Register */ | |
64 | u8 tfcr; /* Transmit FIFO Control Register */ | |
65 | u8 tfpcr; /* Transmit FIFO Pointer Control Register */ | |
66 | u8 eier; /* Error Interrupt Enable Register */ | |
67 | u8 eifr; /* Error Interrupt Factor Judge Register */ | |
68 | u8 recr; /* Receive Error Count Register */ | |
69 | u8 tecr; /* Transmit Error Count Register */ | |
70 | u8 ecsr; /* Error Code Store Register */ | |
71 | u8 cssr; /* Channel Search Support Register */ | |
72 | u8 mssr; /* Mailbox Search Status Register */ | |
73 | u8 msmr; /* Mailbox Search Mode Register */ | |
74 | u16 tsr; /* Time Stamp Register */ | |
75 | u8 afsr; /* Acceptance Filter Support Register */ | |
76 | u8 pad_857; | |
77 | u8 tcr; /* Test Control Register */ | |
78 | u8 pad_859[7]; | |
79 | u8 ier; /* Interrupt Enable Register */ | |
80 | u8 isr; /* Interrupt Status Register */ | |
81 | u8 pad_862; | |
82 | u8 mbsmr; /* Mailbox Search Mask Register */ | |
83 | }; | |
84 | ||
85 | struct rcar_can_priv { | |
86 | struct can_priv can; /* Must be the first member! */ | |
87 | struct net_device *ndev; | |
88 | struct napi_struct napi; | |
89 | struct rcar_can_regs __iomem *regs; | |
90 | struct clk *clk; | |
862e2b6a | 91 | struct clk *can_clk; |
fd115931 SS |
92 | u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; |
93 | u32 tx_head; | |
94 | u32 tx_tail; | |
95 | u8 clock_select; | |
96 | u8 ier; | |
97 | }; | |
98 | ||
99 | static const struct can_bittiming_const rcar_can_bittiming_const = { | |
100 | .name = RCAR_CAN_DRV_NAME, | |
101 | .tseg1_min = 4, | |
102 | .tseg1_max = 16, | |
103 | .tseg2_min = 2, | |
104 | .tseg2_max = 8, | |
105 | .sjw_max = 4, | |
106 | .brp_min = 1, | |
107 | .brp_max = 1024, | |
108 | .brp_inc = 1, | |
109 | }; | |
110 | ||
111 | /* Control Register bits */ | |
112 | #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ | |
113 | #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ | |
114 | /* at bus-off entry */ | |
115 | #define RCAR_CAN_CTLR_SLPM (1 << 10) | |
116 | #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ | |
117 | #define RCAR_CAN_CTLR_CANM_HALT (1 << 9) | |
118 | #define RCAR_CAN_CTLR_CANM_RESET (1 << 8) | |
119 | #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) | |
120 | #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ | |
121 | #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ | |
122 | #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ | |
123 | #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ | |
124 | ||
125 | /* Status Register bits */ | |
126 | #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ | |
127 | ||
128 | /* FIFO Received ID Compare Registers 0 and 1 bits */ | |
129 | #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ | |
130 | #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ | |
131 | ||
132 | /* Receive FIFO Control Register bits */ | |
133 | #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ | |
134 | #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ | |
135 | ||
136 | /* Transmit FIFO Control Register bits */ | |
137 | #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ | |
138 | /* Number Status Bits */ | |
139 | #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ | |
140 | /* Message Number Status Bits */ | |
141 | #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ | |
142 | ||
143 | #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ | |
144 | /* for Rx mailboxes 0-31 */ | |
145 | #define RCAR_CAN_N_RX_MKREGS2 8 | |
146 | ||
147 | /* Bit Configuration Register settings */ | |
148 | #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) | |
149 | #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) | |
150 | #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) | |
151 | #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) | |
152 | ||
153 | /* Mailbox and Mask Registers bits */ | |
154 | #define RCAR_CAN_IDE (1 << 31) | |
155 | #define RCAR_CAN_RTR (1 << 30) | |
156 | #define RCAR_CAN_SID_SHIFT 18 | |
157 | ||
158 | /* Mailbox Interrupt Enable Register 1 bits */ | |
159 | #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ | |
160 | #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ | |
161 | ||
162 | /* Interrupt Enable Register bits */ | |
163 | #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ | |
164 | #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ | |
165 | /* Enable Bit */ | |
166 | #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ | |
167 | /* Enable Bit */ | |
168 | /* Interrupt Status Register bits */ | |
169 | #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ | |
170 | #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ | |
171 | /* Status Bit */ | |
172 | #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ | |
173 | /* Status Bit */ | |
174 | ||
175 | /* Error Interrupt Enable Register bits */ | |
176 | #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ | |
177 | #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ | |
178 | /* Interrupt Enable */ | |
179 | #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ | |
180 | #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ | |
181 | #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ | |
182 | #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ | |
183 | #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ | |
184 | #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ | |
185 | ||
186 | /* Error Interrupt Factor Judge Register bits */ | |
187 | #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ | |
188 | #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ | |
189 | /* Detect Flag */ | |
190 | #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ | |
191 | #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ | |
192 | #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ | |
193 | #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ | |
194 | #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ | |
195 | #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ | |
196 | ||
197 | /* Error Code Store Register bits */ | |
198 | #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ | |
199 | #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ | |
200 | #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ | |
201 | #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ | |
202 | #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ | |
203 | #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ | |
204 | #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ | |
205 | #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ | |
206 | ||
207 | #define RCAR_CAN_NAPI_WEIGHT 4 | |
208 | #define MAX_STR_READS 0x100 | |
209 | ||
210 | static void tx_failure_cleanup(struct net_device *ndev) | |
211 | { | |
212 | int i; | |
213 | ||
214 | for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) | |
215 | can_free_echo_skb(ndev, i); | |
216 | } | |
217 | ||
218 | static void rcar_can_error(struct net_device *ndev) | |
219 | { | |
220 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
221 | struct net_device_stats *stats = &ndev->stats; | |
222 | struct can_frame *cf; | |
223 | struct sk_buff *skb; | |
224 | u8 eifr, txerr = 0, rxerr = 0; | |
225 | ||
226 | /* Propagate the error condition to the CAN stack */ | |
227 | skb = alloc_can_err_skb(ndev, &cf); | |
228 | ||
229 | eifr = readb(&priv->regs->eifr); | |
230 | if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { | |
231 | txerr = readb(&priv->regs->tecr); | |
232 | rxerr = readb(&priv->regs->recr); | |
233 | if (skb) { | |
234 | cf->can_id |= CAN_ERR_CRTL; | |
235 | cf->data[6] = txerr; | |
236 | cf->data[7] = rxerr; | |
237 | } | |
238 | } | |
239 | if (eifr & RCAR_CAN_EIFR_BEIF) { | |
240 | int rx_errors = 0, tx_errors = 0; | |
241 | u8 ecsr; | |
242 | ||
243 | netdev_dbg(priv->ndev, "Bus error interrupt:\n"); | |
a2ec19f8 | 244 | if (skb) |
fd115931 | 245 | cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; |
a2ec19f8 | 246 | |
fd115931 SS |
247 | ecsr = readb(&priv->regs->ecsr); |
248 | if (ecsr & RCAR_CAN_ECSR_ADEF) { | |
249 | netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); | |
250 | tx_errors++; | |
251 | writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); | |
252 | if (skb) | |
ffd461f8 | 253 | cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; |
fd115931 SS |
254 | } |
255 | if (ecsr & RCAR_CAN_ECSR_BE0F) { | |
256 | netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); | |
257 | tx_errors++; | |
258 | writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); | |
259 | if (skb) | |
260 | cf->data[2] |= CAN_ERR_PROT_BIT0; | |
261 | } | |
262 | if (ecsr & RCAR_CAN_ECSR_BE1F) { | |
263 | netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); | |
264 | tx_errors++; | |
265 | writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); | |
266 | if (skb) | |
267 | cf->data[2] |= CAN_ERR_PROT_BIT1; | |
268 | } | |
269 | if (ecsr & RCAR_CAN_ECSR_CEF) { | |
270 | netdev_dbg(priv->ndev, "CRC Error\n"); | |
271 | rx_errors++; | |
272 | writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); | |
273 | if (skb) | |
ffd461f8 | 274 | cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; |
fd115931 SS |
275 | } |
276 | if (ecsr & RCAR_CAN_ECSR_AEF) { | |
277 | netdev_dbg(priv->ndev, "ACK Error\n"); | |
278 | tx_errors++; | |
279 | writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); | |
280 | if (skb) { | |
281 | cf->can_id |= CAN_ERR_ACK; | |
ffd461f8 | 282 | cf->data[3] = CAN_ERR_PROT_LOC_ACK; |
fd115931 SS |
283 | } |
284 | } | |
285 | if (ecsr & RCAR_CAN_ECSR_FEF) { | |
286 | netdev_dbg(priv->ndev, "Form Error\n"); | |
287 | rx_errors++; | |
288 | writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); | |
289 | if (skb) | |
290 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
291 | } | |
292 | if (ecsr & RCAR_CAN_ECSR_SEF) { | |
293 | netdev_dbg(priv->ndev, "Stuff Error\n"); | |
294 | rx_errors++; | |
295 | writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); | |
296 | if (skb) | |
297 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
298 | } | |
299 | ||
300 | priv->can.can_stats.bus_error++; | |
301 | ndev->stats.rx_errors += rx_errors; | |
302 | ndev->stats.tx_errors += tx_errors; | |
303 | writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); | |
304 | } | |
305 | if (eifr & RCAR_CAN_EIFR_EWIF) { | |
306 | netdev_dbg(priv->ndev, "Error warning interrupt\n"); | |
307 | priv->can.state = CAN_STATE_ERROR_WARNING; | |
308 | priv->can.can_stats.error_warning++; | |
309 | /* Clear interrupt condition */ | |
310 | writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); | |
311 | if (skb) | |
312 | cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : | |
313 | CAN_ERR_CRTL_RX_WARNING; | |
314 | } | |
315 | if (eifr & RCAR_CAN_EIFR_EPIF) { | |
316 | netdev_dbg(priv->ndev, "Error passive interrupt\n"); | |
317 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
318 | priv->can.can_stats.error_passive++; | |
319 | /* Clear interrupt condition */ | |
320 | writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); | |
321 | if (skb) | |
322 | cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : | |
323 | CAN_ERR_CRTL_RX_PASSIVE; | |
324 | } | |
325 | if (eifr & RCAR_CAN_EIFR_BOEIF) { | |
326 | netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); | |
327 | tx_failure_cleanup(ndev); | |
328 | priv->ier = RCAR_CAN_IER_ERSIE; | |
329 | writeb(priv->ier, &priv->regs->ier); | |
330 | priv->can.state = CAN_STATE_BUS_OFF; | |
331 | /* Clear interrupt condition */ | |
332 | writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); | |
be38a6f9 | 333 | priv->can.can_stats.bus_off++; |
fd115931 SS |
334 | can_bus_off(ndev); |
335 | if (skb) | |
336 | cf->can_id |= CAN_ERR_BUSOFF; | |
337 | } | |
338 | if (eifr & RCAR_CAN_EIFR_ORIF) { | |
339 | netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); | |
340 | ndev->stats.rx_over_errors++; | |
341 | ndev->stats.rx_errors++; | |
342 | writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); | |
343 | if (skb) { | |
344 | cf->can_id |= CAN_ERR_CRTL; | |
345 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
346 | } | |
347 | } | |
348 | if (eifr & RCAR_CAN_EIFR_OLIF) { | |
349 | netdev_dbg(priv->ndev, | |
350 | "Overload Frame Transmission error interrupt\n"); | |
351 | ndev->stats.rx_over_errors++; | |
352 | ndev->stats.rx_errors++; | |
353 | writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); | |
354 | if (skb) { | |
355 | cf->can_id |= CAN_ERR_PROT; | |
356 | cf->data[2] |= CAN_ERR_PROT_OVERLOAD; | |
357 | } | |
358 | } | |
359 | ||
360 | if (skb) { | |
361 | stats->rx_packets++; | |
362 | stats->rx_bytes += cf->can_dlc; | |
363 | netif_rx(skb); | |
364 | } | |
365 | } | |
366 | ||
367 | static void rcar_can_tx_done(struct net_device *ndev) | |
368 | { | |
369 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
370 | struct net_device_stats *stats = &ndev->stats; | |
371 | u8 isr; | |
372 | ||
373 | while (1) { | |
374 | u8 unsent = readb(&priv->regs->tfcr); | |
375 | ||
376 | unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> | |
377 | RCAR_CAN_TFCR_TFUST_SHIFT; | |
378 | if (priv->tx_head - priv->tx_tail <= unsent) | |
379 | break; | |
380 | stats->tx_packets++; | |
381 | stats->tx_bytes += priv->tx_dlc[priv->tx_tail % | |
382 | RCAR_CAN_FIFO_DEPTH]; | |
383 | priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; | |
384 | can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); | |
385 | priv->tx_tail++; | |
386 | netif_wake_queue(ndev); | |
387 | } | |
388 | /* Clear interrupt */ | |
389 | isr = readb(&priv->regs->isr); | |
390 | writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); | |
391 | can_led_event(ndev, CAN_LED_EVENT_TX); | |
392 | } | |
393 | ||
394 | static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) | |
395 | { | |
396 | struct net_device *ndev = dev_id; | |
397 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
398 | u8 isr; | |
399 | ||
400 | isr = readb(&priv->regs->isr); | |
401 | if (!(isr & priv->ier)) | |
402 | return IRQ_NONE; | |
403 | ||
404 | if (isr & RCAR_CAN_ISR_ERSF) | |
405 | rcar_can_error(ndev); | |
406 | ||
407 | if (isr & RCAR_CAN_ISR_TXFF) | |
408 | rcar_can_tx_done(ndev); | |
409 | ||
410 | if (isr & RCAR_CAN_ISR_RXFF) { | |
411 | if (napi_schedule_prep(&priv->napi)) { | |
412 | /* Disable Rx FIFO interrupts */ | |
413 | priv->ier &= ~RCAR_CAN_IER_RXFIE; | |
414 | writeb(priv->ier, &priv->regs->ier); | |
415 | __napi_schedule(&priv->napi); | |
416 | } | |
417 | } | |
418 | ||
419 | return IRQ_HANDLED; | |
420 | } | |
421 | ||
422 | static void rcar_can_set_bittiming(struct net_device *dev) | |
423 | { | |
424 | struct rcar_can_priv *priv = netdev_priv(dev); | |
425 | struct can_bittiming *bt = &priv->can.bittiming; | |
426 | u32 bcr; | |
427 | ||
428 | bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | | |
429 | RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | | |
430 | RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); | |
431 | /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. | |
432 | * All the registers are big-endian but they get byte-swapped on 32-bit | |
433 | * read/write (but not on 8-bit, contrary to the manuals)... | |
434 | */ | |
435 | writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); | |
436 | } | |
437 | ||
438 | static void rcar_can_start(struct net_device *ndev) | |
439 | { | |
440 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
441 | u16 ctlr; | |
442 | int i; | |
443 | ||
444 | /* Set controller to known mode: | |
445 | * - FIFO mailbox mode | |
446 | * - accept all messages | |
447 | * - overrun mode | |
448 | * CAN is in sleep mode after MCU hardware or software reset. | |
449 | */ | |
450 | ctlr = readw(&priv->regs->ctlr); | |
451 | ctlr &= ~RCAR_CAN_CTLR_SLPM; | |
452 | writew(ctlr, &priv->regs->ctlr); | |
453 | /* Go to reset mode */ | |
454 | ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; | |
455 | writew(ctlr, &priv->regs->ctlr); | |
456 | for (i = 0; i < MAX_STR_READS; i++) { | |
457 | if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) | |
458 | break; | |
459 | } | |
460 | rcar_can_set_bittiming(ndev); | |
461 | ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ | |
462 | ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ | |
463 | /* at bus-off */ | |
464 | ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ | |
465 | ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ | |
466 | writew(ctlr, &priv->regs->ctlr); | |
467 | ||
468 | /* Accept all SID and EID */ | |
469 | writel(0, &priv->regs->mkr_2_9[6]); | |
470 | writel(0, &priv->regs->mkr_2_9[7]); | |
471 | /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ | |
472 | writel(0, &priv->regs->mkivlr1); | |
473 | /* Accept all frames */ | |
474 | writel(0, &priv->regs->fidcr[0]); | |
475 | writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); | |
476 | /* Enable and configure FIFO mailbox interrupts */ | |
477 | writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); | |
478 | ||
479 | priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | | |
480 | RCAR_CAN_IER_TXFIE; | |
481 | writeb(priv->ier, &priv->regs->ier); | |
482 | ||
483 | /* Accumulate error codes */ | |
484 | writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); | |
485 | /* Enable error interrupts */ | |
486 | writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | | |
487 | (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? | |
488 | RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | | |
489 | RCAR_CAN_EIER_OLIE, &priv->regs->eier); | |
490 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
491 | ||
492 | /* Go to operation mode */ | |
493 | writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); | |
494 | for (i = 0; i < MAX_STR_READS; i++) { | |
495 | if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) | |
496 | break; | |
497 | } | |
498 | /* Enable Rx and Tx FIFO */ | |
499 | writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); | |
500 | writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); | |
501 | } | |
502 | ||
503 | static int rcar_can_open(struct net_device *ndev) | |
504 | { | |
505 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
506 | int err; | |
507 | ||
508 | err = clk_prepare_enable(priv->clk); | |
509 | if (err) { | |
3255f68c SS |
510 | netdev_err(ndev, |
511 | "failed to enable peripheral clock, error %d\n", | |
fd115931 SS |
512 | err); |
513 | goto out; | |
514 | } | |
862e2b6a SS |
515 | err = clk_prepare_enable(priv->can_clk); |
516 | if (err) { | |
517 | netdev_err(ndev, "failed to enable CAN clock, error %d\n", | |
518 | err); | |
519 | goto out_clock; | |
520 | } | |
fd115931 SS |
521 | err = open_candev(ndev); |
522 | if (err) { | |
523 | netdev_err(ndev, "open_candev() failed, error %d\n", err); | |
862e2b6a | 524 | goto out_can_clock; |
fd115931 SS |
525 | } |
526 | napi_enable(&priv->napi); | |
527 | err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); | |
528 | if (err) { | |
ae185f19 SS |
529 | netdev_err(ndev, "request_irq(%d) failed, error %d\n", |
530 | ndev->irq, err); | |
fd115931 SS |
531 | goto out_close; |
532 | } | |
533 | can_led_event(ndev, CAN_LED_EVENT_OPEN); | |
534 | rcar_can_start(ndev); | |
535 | netif_start_queue(ndev); | |
536 | return 0; | |
537 | out_close: | |
538 | napi_disable(&priv->napi); | |
539 | close_candev(ndev); | |
862e2b6a SS |
540 | out_can_clock: |
541 | clk_disable_unprepare(priv->can_clk); | |
fd115931 SS |
542 | out_clock: |
543 | clk_disable_unprepare(priv->clk); | |
544 | out: | |
545 | return err; | |
546 | } | |
547 | ||
548 | static void rcar_can_stop(struct net_device *ndev) | |
549 | { | |
550 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
551 | u16 ctlr; | |
552 | int i; | |
553 | ||
554 | /* Go to (force) reset mode */ | |
555 | ctlr = readw(&priv->regs->ctlr); | |
556 | ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; | |
557 | writew(ctlr, &priv->regs->ctlr); | |
558 | for (i = 0; i < MAX_STR_READS; i++) { | |
559 | if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) | |
560 | break; | |
561 | } | |
562 | writel(0, &priv->regs->mier0); | |
563 | writel(0, &priv->regs->mier1); | |
564 | writeb(0, &priv->regs->ier); | |
565 | writeb(0, &priv->regs->eier); | |
566 | /* Go to sleep mode */ | |
567 | ctlr |= RCAR_CAN_CTLR_SLPM; | |
568 | writew(ctlr, &priv->regs->ctlr); | |
569 | priv->can.state = CAN_STATE_STOPPED; | |
570 | } | |
571 | ||
572 | static int rcar_can_close(struct net_device *ndev) | |
573 | { | |
574 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
575 | ||
576 | netif_stop_queue(ndev); | |
577 | rcar_can_stop(ndev); | |
578 | free_irq(ndev->irq, ndev); | |
579 | napi_disable(&priv->napi); | |
862e2b6a | 580 | clk_disable_unprepare(priv->can_clk); |
fd115931 SS |
581 | clk_disable_unprepare(priv->clk); |
582 | close_candev(ndev); | |
583 | can_led_event(ndev, CAN_LED_EVENT_STOP); | |
584 | return 0; | |
585 | } | |
586 | ||
587 | static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, | |
588 | struct net_device *ndev) | |
589 | { | |
590 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
591 | struct can_frame *cf = (struct can_frame *)skb->data; | |
592 | u32 data, i; | |
593 | ||
594 | if (can_dropped_invalid_skb(ndev, skb)) | |
595 | return NETDEV_TX_OK; | |
596 | ||
597 | if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ | |
598 | data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; | |
599 | else /* Standard frame format */ | |
600 | data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; | |
601 | ||
602 | if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ | |
603 | data |= RCAR_CAN_RTR; | |
604 | } else { | |
605 | for (i = 0; i < cf->can_dlc; i++) | |
606 | writeb(cf->data[i], | |
607 | &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); | |
608 | } | |
609 | ||
610 | writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); | |
611 | ||
612 | writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); | |
613 | ||
614 | priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc; | |
615 | can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); | |
616 | priv->tx_head++; | |
617 | /* Start Tx: write 0xff to the TFPCR register to increment | |
618 | * the CPU-side pointer for the transmit FIFO to the next | |
619 | * mailbox location | |
620 | */ | |
621 | writeb(0xff, &priv->regs->tfpcr); | |
622 | /* Stop the queue if we've filled all FIFO entries */ | |
623 | if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) | |
624 | netif_stop_queue(ndev); | |
625 | ||
626 | return NETDEV_TX_OK; | |
627 | } | |
628 | ||
629 | static const struct net_device_ops rcar_can_netdev_ops = { | |
630 | .ndo_open = rcar_can_open, | |
631 | .ndo_stop = rcar_can_close, | |
632 | .ndo_start_xmit = rcar_can_start_xmit, | |
ca976d6a | 633 | .ndo_change_mtu = can_change_mtu, |
fd115931 SS |
634 | }; |
635 | ||
636 | static void rcar_can_rx_pkt(struct rcar_can_priv *priv) | |
637 | { | |
638 | struct net_device_stats *stats = &priv->ndev->stats; | |
639 | struct can_frame *cf; | |
640 | struct sk_buff *skb; | |
641 | u32 data; | |
642 | u8 dlc; | |
643 | ||
644 | skb = alloc_can_skb(priv->ndev, &cf); | |
645 | if (!skb) { | |
646 | stats->rx_dropped++; | |
647 | return; | |
648 | } | |
649 | ||
650 | data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); | |
651 | if (data & RCAR_CAN_IDE) | |
652 | cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
653 | else | |
654 | cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; | |
655 | ||
656 | dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); | |
657 | cf->can_dlc = get_can_dlc(dlc); | |
658 | if (data & RCAR_CAN_RTR) { | |
659 | cf->can_id |= CAN_RTR_FLAG; | |
660 | } else { | |
661 | for (dlc = 0; dlc < cf->can_dlc; dlc++) | |
662 | cf->data[dlc] = | |
663 | readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); | |
664 | } | |
665 | ||
666 | can_led_event(priv->ndev, CAN_LED_EVENT_RX); | |
667 | ||
668 | stats->rx_bytes += cf->can_dlc; | |
669 | stats->rx_packets++; | |
670 | netif_receive_skb(skb); | |
671 | } | |
672 | ||
673 | static int rcar_can_rx_poll(struct napi_struct *napi, int quota) | |
674 | { | |
675 | struct rcar_can_priv *priv = container_of(napi, | |
676 | struct rcar_can_priv, napi); | |
677 | int num_pkts; | |
678 | ||
679 | for (num_pkts = 0; num_pkts < quota; num_pkts++) { | |
680 | u8 rfcr, isr; | |
681 | ||
682 | isr = readb(&priv->regs->isr); | |
683 | /* Clear interrupt bit */ | |
684 | if (isr & RCAR_CAN_ISR_RXFF) | |
685 | writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); | |
686 | rfcr = readb(&priv->regs->rfcr); | |
687 | if (rfcr & RCAR_CAN_RFCR_RFEST) | |
688 | break; | |
689 | rcar_can_rx_pkt(priv); | |
690 | /* Write 0xff to the RFPCR register to increment | |
691 | * the CPU-side pointer for the receive FIFO | |
692 | * to the next mailbox location | |
693 | */ | |
694 | writeb(0xff, &priv->regs->rfpcr); | |
695 | } | |
696 | /* All packets processed */ | |
697 | if (num_pkts < quota) { | |
698 | napi_complete(napi); | |
699 | priv->ier |= RCAR_CAN_IER_RXFIE; | |
700 | writeb(priv->ier, &priv->regs->ier); | |
701 | } | |
702 | return num_pkts; | |
703 | } | |
704 | ||
705 | static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) | |
706 | { | |
707 | switch (mode) { | |
708 | case CAN_MODE_START: | |
709 | rcar_can_start(ndev); | |
710 | netif_wake_queue(ndev); | |
711 | return 0; | |
712 | default: | |
713 | return -EOPNOTSUPP; | |
714 | } | |
715 | } | |
716 | ||
717 | static int rcar_can_get_berr_counter(const struct net_device *dev, | |
718 | struct can_berr_counter *bec) | |
719 | { | |
720 | struct rcar_can_priv *priv = netdev_priv(dev); | |
721 | int err; | |
722 | ||
723 | err = clk_prepare_enable(priv->clk); | |
724 | if (err) | |
725 | return err; | |
726 | bec->txerr = readb(&priv->regs->tecr); | |
727 | bec->rxerr = readb(&priv->regs->recr); | |
728 | clk_disable_unprepare(priv->clk); | |
729 | return 0; | |
730 | } | |
731 | ||
862e2b6a SS |
732 | static const char * const clock_names[] = { |
733 | [CLKR_CLKP1] = "clkp1", | |
734 | [CLKR_CLKP2] = "clkp2", | |
735 | [CLKR_CLKEXT] = "can_clk", | |
736 | }; | |
737 | ||
fd115931 SS |
738 | static int rcar_can_probe(struct platform_device *pdev) |
739 | { | |
740 | struct rcar_can_platform_data *pdata; | |
741 | struct rcar_can_priv *priv; | |
742 | struct net_device *ndev; | |
743 | struct resource *mem; | |
744 | void __iomem *addr; | |
a268de6c | 745 | u32 clock_select = CLKR_CLKP1; |
fd115931 SS |
746 | int err = -ENODEV; |
747 | int irq; | |
748 | ||
a268de6c SS |
749 | if (pdev->dev.of_node) { |
750 | of_property_read_u32(pdev->dev.of_node, | |
751 | "renesas,can-clock-select", &clock_select); | |
752 | } else { | |
753 | pdata = dev_get_platdata(&pdev->dev); | |
754 | if (!pdata) { | |
755 | dev_err(&pdev->dev, "No platform data provided!\n"); | |
756 | goto fail; | |
757 | } | |
758 | clock_select = pdata->clock_select; | |
fd115931 SS |
759 | } |
760 | ||
761 | irq = platform_get_irq(pdev, 0); | |
5e63e6ba | 762 | if (irq < 0) { |
fd115931 | 763 | dev_err(&pdev->dev, "No IRQ resource\n"); |
5e63e6ba | 764 | err = irq; |
fd115931 SS |
765 | goto fail; |
766 | } | |
767 | ||
768 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
769 | addr = devm_ioremap_resource(&pdev->dev, mem); | |
770 | if (IS_ERR(addr)) { | |
771 | err = PTR_ERR(addr); | |
772 | goto fail; | |
773 | } | |
774 | ||
775 | ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); | |
776 | if (!ndev) { | |
777 | dev_err(&pdev->dev, "alloc_candev() failed\n"); | |
778 | err = -ENOMEM; | |
779 | goto fail; | |
780 | } | |
781 | ||
782 | priv = netdev_priv(ndev); | |
783 | ||
862e2b6a | 784 | priv->clk = devm_clk_get(&pdev->dev, "clkp1"); |
fd115931 SS |
785 | if (IS_ERR(priv->clk)) { |
786 | err = PTR_ERR(priv->clk); | |
585bc2ac SS |
787 | dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", |
788 | err); | |
862e2b6a SS |
789 | goto fail_clk; |
790 | } | |
791 | ||
792 | if (clock_select >= ARRAY_SIZE(clock_names)) { | |
793 | err = -EINVAL; | |
794 | dev_err(&pdev->dev, "invalid CAN clock selected\n"); | |
795 | goto fail_clk; | |
796 | } | |
797 | priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); | |
798 | if (IS_ERR(priv->can_clk)) { | |
799 | err = PTR_ERR(priv->can_clk); | |
585bc2ac | 800 | dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); |
fd115931 SS |
801 | goto fail_clk; |
802 | } | |
803 | ||
804 | ndev->netdev_ops = &rcar_can_netdev_ops; | |
805 | ndev->irq = irq; | |
806 | ndev->flags |= IFF_ECHO; | |
807 | priv->ndev = ndev; | |
808 | priv->regs = addr; | |
862e2b6a SS |
809 | priv->clock_select = clock_select; |
810 | priv->can.clock.freq = clk_get_rate(priv->can_clk); | |
fd115931 SS |
811 | priv->can.bittiming_const = &rcar_can_bittiming_const; |
812 | priv->can.do_set_mode = rcar_can_do_set_mode; | |
813 | priv->can.do_get_berr_counter = rcar_can_get_berr_counter; | |
814 | priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; | |
815 | platform_set_drvdata(pdev, ndev); | |
816 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
817 | ||
818 | netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, | |
819 | RCAR_CAN_NAPI_WEIGHT); | |
820 | err = register_candev(ndev); | |
821 | if (err) { | |
822 | dev_err(&pdev->dev, "register_candev() failed, error %d\n", | |
823 | err); | |
824 | goto fail_candev; | |
825 | } | |
826 | ||
827 | devm_can_led_init(ndev); | |
828 | ||
c1a4c87b | 829 | dev_info(&pdev->dev, "device registered (regs @ %p, IRQ%d)\n", |
fd115931 SS |
830 | priv->regs, ndev->irq); |
831 | ||
832 | return 0; | |
833 | fail_candev: | |
834 | netif_napi_del(&priv->napi); | |
835 | fail_clk: | |
836 | free_candev(ndev); | |
837 | fail: | |
838 | return err; | |
839 | } | |
840 | ||
841 | static int rcar_can_remove(struct platform_device *pdev) | |
842 | { | |
843 | struct net_device *ndev = platform_get_drvdata(pdev); | |
844 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
845 | ||
846 | unregister_candev(ndev); | |
847 | netif_napi_del(&priv->napi); | |
848 | free_candev(ndev); | |
849 | return 0; | |
850 | } | |
851 | ||
852 | static int __maybe_unused rcar_can_suspend(struct device *dev) | |
853 | { | |
854 | struct net_device *ndev = dev_get_drvdata(dev); | |
855 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
856 | u16 ctlr; | |
857 | ||
858 | if (netif_running(ndev)) { | |
859 | netif_stop_queue(ndev); | |
860 | netif_device_detach(ndev); | |
861 | } | |
862 | ctlr = readw(&priv->regs->ctlr); | |
863 | ctlr |= RCAR_CAN_CTLR_CANM_HALT; | |
864 | writew(ctlr, &priv->regs->ctlr); | |
865 | ctlr |= RCAR_CAN_CTLR_SLPM; | |
866 | writew(ctlr, &priv->regs->ctlr); | |
867 | priv->can.state = CAN_STATE_SLEEPING; | |
868 | ||
869 | clk_disable(priv->clk); | |
870 | return 0; | |
871 | } | |
872 | ||
873 | static int __maybe_unused rcar_can_resume(struct device *dev) | |
874 | { | |
875 | struct net_device *ndev = dev_get_drvdata(dev); | |
876 | struct rcar_can_priv *priv = netdev_priv(ndev); | |
877 | u16 ctlr; | |
878 | int err; | |
879 | ||
880 | err = clk_enable(priv->clk); | |
881 | if (err) { | |
882 | netdev_err(ndev, "clk_enable() failed, error %d\n", err); | |
883 | return err; | |
884 | } | |
885 | ||
886 | ctlr = readw(&priv->regs->ctlr); | |
887 | ctlr &= ~RCAR_CAN_CTLR_SLPM; | |
888 | writew(ctlr, &priv->regs->ctlr); | |
889 | ctlr &= ~RCAR_CAN_CTLR_CANM; | |
890 | writew(ctlr, &priv->regs->ctlr); | |
891 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
892 | ||
893 | if (netif_running(ndev)) { | |
894 | netif_device_attach(ndev); | |
895 | netif_start_queue(ndev); | |
896 | } | |
897 | return 0; | |
898 | } | |
899 | ||
900 | static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); | |
901 | ||
a268de6c SS |
902 | static const struct of_device_id rcar_can_of_table[] __maybe_unused = { |
903 | { .compatible = "renesas,can-r8a7778" }, | |
904 | { .compatible = "renesas,can-r8a7779" }, | |
905 | { .compatible = "renesas,can-r8a7790" }, | |
906 | { .compatible = "renesas,can-r8a7791" }, | |
907 | { } | |
908 | }; | |
909 | MODULE_DEVICE_TABLE(of, rcar_can_of_table); | |
910 | ||
fd115931 SS |
911 | static struct platform_driver rcar_can_driver = { |
912 | .driver = { | |
913 | .name = RCAR_CAN_DRV_NAME, | |
a268de6c | 914 | .of_match_table = of_match_ptr(rcar_can_of_table), |
fd115931 SS |
915 | .pm = &rcar_can_pm_ops, |
916 | }, | |
917 | .probe = rcar_can_probe, | |
918 | .remove = rcar_can_remove, | |
919 | }; | |
920 | ||
921 | module_platform_driver(rcar_can_driver); | |
922 | ||
923 | MODULE_AUTHOR("Cogent Embedded, Inc."); | |
924 | MODULE_LICENSE("GPL"); | |
925 | MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); | |
926 | MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); |