[mirror_ubuntu-bionic-kernel.git] / drivers / net / can / sja1000 / ems_pci.c

/*
 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the version 2 of the GNU General Public License
 * as published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/can/dev.h>
#include <linux/io.h>

#include "sja1000.h"

#define DRV_NAME  "ems_pci"

MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
MODULE_LICENSE("GPL v2");

#define EMS_PCI_V1_MAX_CHAN 2
#define EMS_PCI_V2_MAX_CHAN 4
#define EMS_PCI_MAX_CHAN    EMS_PCI_V2_MAX_CHAN

struct ems_pci_card {
	int version;
	int channels;

	struct pci_dev *pci_dev;
	struct net_device *net_dev[EMS_PCI_MAX_CHAN];

	void __iomem *conf_addr;
	void __iomem *base_addr;
};

#define EMS_PCI_CAN_CLOCK (16000000 / 2)

/*
 * Register definitions and descriptions are from LinCAN 0.3.3.
 *
 * PSB4610 PITA-2 bridge control registers
 */
#define PITA2_ICR           0x00	/* Interrupt Control Register */
#define PITA2_ICR_INT0      0x00000002	/* [RC] INT0 Active/Clear */
#define PITA2_ICR_INT0_EN   0x00020000	/* [RW] Enable INT0 */

#define PITA2_MISC          0x1c	/* Miscellaneous Register */
#define PITA2_MISC_CONFIG   0x04000000	/* Multiplexed parallel interface */

/*
 * Register definitions for the PLX 9030
 */
#define PLX_ICSR            0x4c   /* Interrupt Control/Status register */
#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
#define PLX_ICSR_ENA_CLR    (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
			     PLX_ICSR_LINTI1_CLR)

/*
 * The board configuration is probably following:
 * RX1 is connected to ground.
 * TX1 is not connected.
 * CLKO is not connected.
 * Setting the OCR register to 0xDA is a good idea.
 * This means normal output mode, push-pull and the correct polarity.
 */
#define EMS_PCI_OCR         (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)

/*
 * In the CDR register, you should set CBP to 1.
 * You will probably also want to set the clock divider value to 7
 * (meaning direct oscillator output) because the second SJA1000 chip
 * is driven by the first one CLKOUT output.
 */
#define EMS_PCI_CDR             (CDR_CBP | CDR_CLKOUT_MASK)

#define EMS_PCI_V1_BASE_BAR     1
#define EMS_PCI_V1_CONF_SIZE    4096 /* size of PITA control area */
#define EMS_PCI_V2_BASE_BAR     2
#define EMS_PCI_V2_CONF_SIZE    128 /* size of PLX control area */
#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
#define EMS_PCI_CAN_CTRL_SIZE   0x200 /* memory size for each controller */

#define EMS_PCI_BASE_SIZE  4096 /* size of controller area */

static DEFINE_PCI_DEVICE_TABLE(ems_pci_tbl) = {
	/* CPC-PCI v1 */
	{PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
	/* CPC-PCI v2 */
	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
	/* CPC-104P v2 */
	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
	{0,}
};
MODULE_DEVICE_TABLE(pci, ems_pci_tbl);

/*
 * Helper to read internal registers from card logic (not CAN)
 */
static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
{
	return readb(card->base_addr + (port * 4));
}

static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
{
	return readb(priv->reg_base + (port * 4));
}

static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
				 int port, u8 val)
{
	writeb(val, priv->reg_base + (port * 4));
}

static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
{
	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;

	/* reset int flag of pita */
	writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
	       card->conf_addr + PITA2_ICR);
}

static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
{
	return readb(priv->reg_base + port);
}

static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
				 int port, u8 val)
{
	writeb(val, priv->reg_base + port);
}

static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
{
	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;

	writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
}

/*
 * Check if a CAN controller is present at the specified location
 * by trying to set 'em into the PeliCAN mode
 */
static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
{
	unsigned char res;

	/* Make sure SJA1000 is in reset mode */
	priv->write_reg(priv, SJA1000_MOD, 1);

	priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);

	/* read reset-values */
	res = priv->read_reg(priv, SJA1000_CDR);

	if (res == CDR_PELICAN)
		return 1;

	return 0;
}

static void ems_pci_del_card(struct pci_dev *pdev)
{
	struct ems_pci_card *card = pci_get_drvdata(pdev);
	struct net_device *dev;
	int i = 0;

	for (i = 0; i < card->channels; i++) {
		dev = card->net_dev[i];

		if (!dev)
			continue;

		dev_info(&pdev->dev, "Removing %s.\n", dev->name);
		unregister_sja1000dev(dev);
		free_sja1000dev(dev);
	}

	if (card->base_addr != NULL)
		pci_iounmap(card->pci_dev, card->base_addr);

	if (card->conf_addr != NULL)
		pci_iounmap(card->pci_dev, card->conf_addr);

	kfree(card);

	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
}

static void ems_pci_card_reset(struct ems_pci_card *card)
{
	/* Request board reset */
	writeb(0, card->base_addr);
}

/*
 * Probe PCI device for EMS CAN signature and register each available
 * CAN channel to SJA1000 Socket-CAN subsystem.
 */
static int ems_pci_add_card(struct pci_dev *pdev,
			    const struct pci_device_id *ent)
{
	struct sja1000_priv *priv;
	struct net_device *dev;
	struct ems_pci_card *card;
	int max_chan, conf_size, base_bar;
	int err, i;

	/* Enabling PCI device */
	if (pci_enable_device(pdev) < 0) {
		dev_err(&pdev->dev, "Enabling PCI device failed\n");
		return -ENODEV;
	}

	/* Allocating card structures to hold addresses, ... */
	card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
	if (card == NULL) {
		pci_disable_device(pdev);
		return -ENOMEM;
	}

	pci_set_drvdata(pdev, card);

	card->pci_dev = pdev;

	card->channels = 0;

	if (pdev->vendor == PCI_VENDOR_ID_PLX) {
		card->version = 2; /* CPC-PCI v2 */
		max_chan = EMS_PCI_V2_MAX_CHAN;
		base_bar = EMS_PCI_V2_BASE_BAR;
		conf_size = EMS_PCI_V2_CONF_SIZE;
	} else {
		card->version = 1; /* CPC-PCI v1 */
		max_chan = EMS_PCI_V1_MAX_CHAN;
		base_bar = EMS_PCI_V1_BASE_BAR;
		conf_size = EMS_PCI_V1_CONF_SIZE;
	}

	/* Remap configuration space and controller memory area */
	card->conf_addr = pci_iomap(pdev, 0, conf_size);
	if (card->conf_addr == NULL) {
		err = -ENOMEM;
		goto failure_cleanup;
	}

	card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
	if (card->base_addr == NULL) {
		err = -ENOMEM;
		goto failure_cleanup;
	}

	if (card->version == 1) {
		/* Configure PITA-2 parallel interface (enable MUX) */
		writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);

		/* Check for unique EMS CAN signature */
		if (ems_pci_v1_readb(card, 0) != 0x55 ||
		    ems_pci_v1_readb(card, 1) != 0xAA ||
		    ems_pci_v1_readb(card, 2) != 0x01 ||
		    ems_pci_v1_readb(card, 3) != 0xCB ||
		    ems_pci_v1_readb(card, 4) != 0x11) {
			dev_err(&pdev->dev,
				"Not EMS Dr. Thomas Wuensche interface\n");
			err = -ENODEV;
			goto failure_cleanup;
		}
	}

	ems_pci_card_reset(card);

	/* Detect available channels */
	for (i = 0; i < max_chan; i++) {
		dev = alloc_sja1000dev(0);
		if (dev == NULL) {
			err = -ENOMEM;
			goto failure_cleanup;
		}

		card->net_dev[i] = dev;
		priv = netdev_priv(dev);
		priv->priv = card;
		priv->irq_flags = IRQF_SHARED;

		dev->irq = pdev->irq;
		priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
					+ (i * EMS_PCI_CAN_CTRL_SIZE);
		if (card->version == 1) {
			priv->read_reg  = ems_pci_v1_read_reg;
			priv->write_reg = ems_pci_v1_write_reg;
			priv->post_irq  = ems_pci_v1_post_irq;
		} else {
			priv->read_reg  = ems_pci_v2_read_reg;
			priv->write_reg = ems_pci_v2_write_reg;
			priv->post_irq  = ems_pci_v2_post_irq;
		}

		/* Check if channel is present */
		if (ems_pci_check_chan(priv)) {
			priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
			priv->ocr = EMS_PCI_OCR;
			priv->cdr = EMS_PCI_CDR;

			SET_NETDEV_DEV(dev, &pdev->dev);

			if (card->version == 1)
				/* reset int flag of pita */
				writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
				       card->conf_addr + PITA2_ICR);
			else
				/* enable IRQ in PLX 9030 */
				writel(PLX_ICSR_ENA_CLR,
				       card->conf_addr + PLX_ICSR);

			/* Register SJA1000 device */
			err = register_sja1000dev(dev);
			if (err) {
				dev_err(&pdev->dev, "Registering device failed "
							"(err=%d)\n", err);
				free_sja1000dev(dev);
				goto failure_cleanup;
			}

			card->channels++;

			dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
					i + 1, priv->reg_base, dev->irq);
		} else {
			free_sja1000dev(dev);
		}
	}

	return 0;

failure_cleanup:
	dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);

	ems_pci_del_card(pdev);

	return err;
}

static struct pci_driver ems_pci_driver = {
	.name = DRV_NAME,
	.id_table = ems_pci_tbl,
	.probe = ems_pci_add_card,
	.remove = ems_pci_del_card,
};

module_pci_driver(ems_pci_driver);
Commit	Line	Data
a61a8423 WG	1	/*
	2	* Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
	3	* Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
	4	* Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the version 2 of the GNU General Public License
	8	* as published by the Free Software Foundation
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software Foundation,
	17	* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/netdevice.h>
	24	#include <linux/delay.h>
5a0e3ad6	25	#include <linux/slab.h>
a61a8423	26	#include <linux/pci.h>
a61a8423 WG	27	#include <linux/can/dev.h>
	28	#include <linux/io.h>
	29
	30	#include "sja1000.h"
	31
	32	#define DRV_NAME "ems_pci"
	33
	34	MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
dd52856b SH	35	MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
dd52856b SH	36	MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
a61a8423 WG	37	MODULE_LICENSE("GPL v2");
a61a8423 WG	38
dd52856b SH	39	#define EMS_PCI_V1_MAX_CHAN 2
	40	#define EMS_PCI_V2_MAX_CHAN 4
	41	#define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
a61a8423 WG	42
a61a8423 WG	43	struct ems_pci_card {
dd52856b	44	int version;
a61a8423 WG	45	int channels;
	46
	47	struct pci_dev *pci_dev;
	48	struct net_device *net_dev[EMS_PCI_MAX_CHAN];
	49
	50	void __iomem *conf_addr;
	51	void __iomem *base_addr;
	52	};
	53
	54	#define EMS_PCI_CAN_CLOCK (16000000 / 2)
	55
	56	/*
	57	* Register definitions and descriptions are from LinCAN 0.3.3.
	58	*
	59	* PSB4610 PITA-2 bridge control registers
	60	*/
	61	#define PITA2_ICR 0x00 /* Interrupt Control Register */
	62	#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
	63	#define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
	64
	65	#define PITA2_MISC 0x1c /* Miscellaneous Register */
	66	#define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
	67
dd52856b SH	68	/*
	69	* Register definitions for the PLX 9030
	70	*/
	71	#define PLX_ICSR 0x4c /* Interrupt Control/Status register */
	72	#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
	73	#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
	74	#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
	75	#define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA \| PLX_ICSR_PCIINT_ENA \| \
	76	PLX_ICSR_LINTI1_CLR)
	77
a61a8423 WG	78	/*
	79	* The board configuration is probably following:
	80	* RX1 is connected to ground.
	81	* TX1 is not connected.
	82	* CLKO is not connected.
	83	* Setting the OCR register to 0xDA is a good idea.
dd52856b	84	* This means normal output mode, push-pull and the correct polarity.
a61a8423 WG	85	*/
	86	#define EMS_PCI_OCR (OCR_TX0_PUSHPULL \| OCR_TX1_PUSHPULL)
	87
	88	/*
	89	* In the CDR register, you should set CBP to 1.
	90	* You will probably also want to set the clock divider value to 7
	91	* (meaning direct oscillator output) because the second SJA1000 chip
	92	* is driven by the first one CLKOUT output.
	93	*/
	94	#define EMS_PCI_CDR (CDR_CBP \| CDR_CLKOUT_MASK)
dd52856b SH	95
dd52856b SH	96	#define EMS_PCI_V1_BASE_BAR 1
edf42a27	97	#define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */
dd52856b	98	#define EMS_PCI_V2_BASE_BAR 2
edf42a27	99	#define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */
a61a8423 WG	100	#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
	101	#define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
	102
edf42a27 SH	103	#define EMS_PCI_BASE_SIZE 4096 /* size of controller area */
edf42a27 SH	104
a3aa1884	105	static DEFINE_PCI_DEVICE_TABLE(ems_pci_tbl) = {
dd52856b SH	106	/* CPC-PCI v1 */
	107	{PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
	108	/* CPC-PCI v2 */
	109	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
	110	/* CPC-104P v2 */
	111	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
a61a8423 WG	112	{0,}
	113	};
	114	MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
	115
	116	/*
	117	* Helper to read internal registers from card logic (not CAN)
	118	*/
dd52856b	119	static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
a61a8423	120	{
dd52856b	121	return readb(card->base_addr + (port * 4));
a61a8423 WG	122	}
a61a8423 WG	123
dd52856b	124	static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
a61a8423	125	{
dd52856b	126	return readb(priv->reg_base + (port * 4));
a61a8423 WG	127	}
a61a8423 WG	128
dd52856b SH	129	static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
dd52856b SH	130	int port, u8 val)
a61a8423	131	{
dd52856b	132	writeb(val, priv->reg_base + (port * 4));
a61a8423 WG	133	}
a61a8423 WG	134
dd52856b	135	static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
a61a8423	136	{
a61a8423 WG	137	struct ems_pci_card card = (struct ems_pci_card )priv->priv;
	138
	139	/* reset int flag of pita */
dd52856b SH	140	writel(PITA2_ICR_INT0_EN \| PITA2_ICR_INT0,
	141	card->conf_addr + PITA2_ICR);
	142	}
	143
	144	static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
	145	{
	146	return readb(priv->reg_base + port);
	147	}
	148
	149	static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
	150	int port, u8 val)
	151	{
	152	writeb(val, priv->reg_base + port);
	153	}
	154
	155	static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
	156	{
	157	struct ems_pci_card card = (struct ems_pci_card )priv->priv;
	158
	159	writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
a61a8423 WG	160	}
	161
	162	/*
	163	* Check if a CAN controller is present at the specified location
	164	* by trying to set 'em into the PeliCAN mode
	165	*/
255a9154	166	static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
a61a8423 WG	167	{
	168	unsigned char res;
	169
	170	/* Make sure SJA1000 is in reset mode */
06e1d1d7	171	priv->write_reg(priv, SJA1000_MOD, 1);
a61a8423	172
06e1d1d7	173	priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
a61a8423 WG	174
a61a8423 WG	175	/* read reset-values */
06e1d1d7	176	res = priv->read_reg(priv, SJA1000_CDR);
a61a8423 WG	177
	178	if (res == CDR_PELICAN)
	179	return 1;
	180
	181	return 0;
	182	}
	183
	184	static void ems_pci_del_card(struct pci_dev *pdev)
	185	{
	186	struct ems_pci_card *card = pci_get_drvdata(pdev);
	187	struct net_device *dev;
	188	int i = 0;
	189
	190	for (i = 0; i < card->channels; i++) {
	191	dev = card->net_dev[i];
	192
	193	if (!dev)
	194	continue;
	195
	196	dev_info(&pdev->dev, "Removing %s.\n", dev->name);
	197	unregister_sja1000dev(dev);
	198	free_sja1000dev(dev);
	199	}
	200
	201	if (card->base_addr != NULL)
	202	pci_iounmap(card->pci_dev, card->base_addr);
	203
	204	if (card->conf_addr != NULL)
	205	pci_iounmap(card->pci_dev, card->conf_addr);
	206
	207	kfree(card);
	208
	209	pci_disable_device(pdev);
	210	pci_set_drvdata(pdev, NULL);
	211	}
	212
	213	static void ems_pci_card_reset(struct ems_pci_card *card)
	214	{
	215	/* Request board reset */
	216	writeb(0, card->base_addr);
	217	}
	218
	219	/*
	220	* Probe PCI device for EMS CAN signature and register each available
	221	* CAN channel to SJA1000 Socket-CAN subsystem.
	222	*/
3c8ac0f2	223	static int ems_pci_add_card(struct pci_dev *pdev,
1dd06ae8	224	const struct pci_device_id *ent)
a61a8423 WG	225	{
	226	struct sja1000_priv *priv;
	227	struct net_device *dev;
	228	struct ems_pci_card *card;
edf42a27	229	int max_chan, conf_size, base_bar;
a61a8423 WG	230	int err, i;
	231
	232	/* Enabling PCI device */
	233	if (pci_enable_device(pdev) < 0) {
	234	dev_err(&pdev->dev, "Enabling PCI device failed\n");
	235	return -ENODEV;
	236	}
	237
	238	/* Allocating card structures to hold addresses, ... */
	239	card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
	240	if (card == NULL) {
a61a8423 WG	241	pci_disable_device(pdev);
	242	return -ENOMEM;
	243	}
	244
	245	pci_set_drvdata(pdev, card);
	246
	247	card->pci_dev = pdev;
	248
	249	card->channels = 0;
	250
dd52856b SH	251	if (pdev->vendor == PCI_VENDOR_ID_PLX) {
	252	card->version = 2; /* CPC-PCI v2 */
	253	max_chan = EMS_PCI_V2_MAX_CHAN;
	254	base_bar = EMS_PCI_V2_BASE_BAR;
edf42a27	255	conf_size = EMS_PCI_V2_CONF_SIZE;
dd52856b SH	256	} else {
	257	card->version = 1; /* CPC-PCI v1 */
	258	max_chan = EMS_PCI_V1_MAX_CHAN;
	259	base_bar = EMS_PCI_V1_BASE_BAR;
edf42a27	260	conf_size = EMS_PCI_V1_CONF_SIZE;
dd52856b SH	261	}
	262
	263	/* Remap configuration space and controller memory area */
edf42a27	264	card->conf_addr = pci_iomap(pdev, 0, conf_size);
a61a8423 WG	265	if (card->conf_addr == NULL) {
a61a8423 WG	266	err = -ENOMEM;
a61a8423 WG	267	goto failure_cleanup;
	268	}
	269
edf42a27	270	card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
a61a8423 WG	271	if (card->base_addr == NULL) {
a61a8423 WG	272	err = -ENOMEM;
a61a8423 WG	273	goto failure_cleanup;
	274	}
	275
dd52856b SH	276	if (card->version == 1) {
	277	/* Configure PITA-2 parallel interface (enable MUX) */
	278	writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
	279
	280	/* Check for unique EMS CAN signature */
	281	if (ems_pci_v1_readb(card, 0) != 0x55 \|\|
	282	ems_pci_v1_readb(card, 1) != 0xAA \|\|
	283	ems_pci_v1_readb(card, 2) != 0x01 \|\|
	284	ems_pci_v1_readb(card, 3) != 0xCB \|\|
	285	ems_pci_v1_readb(card, 4) != 0x11) {
	286	dev_err(&pdev->dev,
	287	"Not EMS Dr. Thomas Wuensche interface\n");
	288	err = -ENODEV;
	289	goto failure_cleanup;
	290	}
a61a8423 WG	291	}
	292
	293	ems_pci_card_reset(card);
	294
	295	/* Detect available channels */
dd52856b	296	for (i = 0; i < max_chan; i++) {
a61a8423 WG	297	dev = alloc_sja1000dev(0);
	298	if (dev == NULL) {
	299	err = -ENOMEM;
	300	goto failure_cleanup;
	301	}
	302
	303	card->net_dev[i] = dev;
	304	priv = netdev_priv(dev);
	305	priv->priv = card;
	306	priv->irq_flags = IRQF_SHARED;
	307
	308	dev->irq = pdev->irq;
255a9154 WG	309	priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
255a9154 WG	310	+ (i * EMS_PCI_CAN_CTRL_SIZE);
dd52856b SH	311	if (card->version == 1) {
	312	priv->read_reg = ems_pci_v1_read_reg;
	313	priv->write_reg = ems_pci_v1_write_reg;
	314	priv->post_irq = ems_pci_v1_post_irq;
	315	} else {
	316	priv->read_reg = ems_pci_v2_read_reg;
	317	priv->write_reg = ems_pci_v2_write_reg;
	318	priv->post_irq = ems_pci_v2_post_irq;
	319	}
a61a8423 WG	320
a61a8423 WG	321	/* Check if channel is present */
255a9154	322	if (ems_pci_check_chan(priv)) {
a61a8423 WG	323	priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
	324	priv->ocr = EMS_PCI_OCR;
	325	priv->cdr = EMS_PCI_CDR;
	326
	327	SET_NETDEV_DEV(dev, &pdev->dev);
	328
dd52856b SH	329	if (card->version == 1)
	330	/* reset int flag of pita */
	331	writel(PITA2_ICR_INT0_EN \| PITA2_ICR_INT0,
	332	card->conf_addr + PITA2_ICR);
	333	else
	334	/* enable IRQ in PLX 9030 */
	335	writel(PLX_ICSR_ENA_CLR,
	336	card->conf_addr + PLX_ICSR);
a61a8423 WG	337
	338	/* Register SJA1000 device */
	339	err = register_sja1000dev(dev);
	340	if (err) {
	341	dev_err(&pdev->dev, "Registering device failed "
	342	"(err=%d)\n", err);
	343	free_sja1000dev(dev);
	344	goto failure_cleanup;
	345	}
	346
	347	card->channels++;
	348
255a9154 WG	349	dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
255a9154 WG	350	i + 1, priv->reg_base, dev->irq);
a61a8423 WG	351	} else {
	352	free_sja1000dev(dev);
	353	}
	354	}
	355
	356	return 0;
	357
	358	failure_cleanup:
	359	dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
	360
	361	ems_pci_del_card(pdev);
	362
	363	return err;
	364	}
	365
	366	static struct pci_driver ems_pci_driver = {
	367	.name = DRV_NAME,
	368	.id_table = ems_pci_tbl,
	369	.probe = ems_pci_add_card,
	370	.remove = ems_pci_del_card,
	371	};
	372
fb7944b3	373	module_pci_driver(ems_pci_driver);