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a61a8423 WG |
1 | /* |
2 | * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> | |
3 | * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> | |
4 | * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the version 2 of the GNU General Public License | |
8 | * as published by the Free Software Foundation | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software Foundation, | |
17 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/netdevice.h> | |
24 | #include <linux/delay.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
a61a8423 WG |
26 | #include <linux/pci.h> |
27 | #include <linux/can.h> | |
28 | #include <linux/can/dev.h> | |
29 | #include <linux/io.h> | |
30 | ||
31 | #include "sja1000.h" | |
32 | ||
33 | #define DRV_NAME "ems_pci" | |
34 | ||
35 | MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>"); | |
dd52856b SH |
36 | MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards"); |
37 | MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card"); | |
a61a8423 WG |
38 | MODULE_LICENSE("GPL v2"); |
39 | ||
dd52856b SH |
40 | #define EMS_PCI_V1_MAX_CHAN 2 |
41 | #define EMS_PCI_V2_MAX_CHAN 4 | |
42 | #define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN | |
a61a8423 WG |
43 | |
44 | struct ems_pci_card { | |
dd52856b | 45 | int version; |
a61a8423 WG |
46 | int channels; |
47 | ||
48 | struct pci_dev *pci_dev; | |
49 | struct net_device *net_dev[EMS_PCI_MAX_CHAN]; | |
50 | ||
51 | void __iomem *conf_addr; | |
52 | void __iomem *base_addr; | |
53 | }; | |
54 | ||
55 | #define EMS_PCI_CAN_CLOCK (16000000 / 2) | |
56 | ||
57 | /* | |
58 | * Register definitions and descriptions are from LinCAN 0.3.3. | |
59 | * | |
60 | * PSB4610 PITA-2 bridge control registers | |
61 | */ | |
62 | #define PITA2_ICR 0x00 /* Interrupt Control Register */ | |
63 | #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */ | |
64 | #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */ | |
65 | ||
66 | #define PITA2_MISC 0x1c /* Miscellaneous Register */ | |
67 | #define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */ | |
68 | ||
dd52856b SH |
69 | /* |
70 | * Register definitions for the PLX 9030 | |
71 | */ | |
72 | #define PLX_ICSR 0x4c /* Interrupt Control/Status register */ | |
73 | #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */ | |
74 | #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */ | |
75 | #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */ | |
76 | #define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \ | |
77 | PLX_ICSR_LINTI1_CLR) | |
78 | ||
a61a8423 WG |
79 | /* |
80 | * The board configuration is probably following: | |
81 | * RX1 is connected to ground. | |
82 | * TX1 is not connected. | |
83 | * CLKO is not connected. | |
84 | * Setting the OCR register to 0xDA is a good idea. | |
dd52856b | 85 | * This means normal output mode, push-pull and the correct polarity. |
a61a8423 WG |
86 | */ |
87 | #define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) | |
88 | ||
89 | /* | |
90 | * In the CDR register, you should set CBP to 1. | |
91 | * You will probably also want to set the clock divider value to 7 | |
92 | * (meaning direct oscillator output) because the second SJA1000 chip | |
93 | * is driven by the first one CLKOUT output. | |
94 | */ | |
95 | #define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) | |
dd52856b SH |
96 | |
97 | #define EMS_PCI_V1_BASE_BAR 1 | |
edf42a27 | 98 | #define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */ |
dd52856b | 99 | #define EMS_PCI_V2_BASE_BAR 2 |
edf42a27 | 100 | #define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */ |
a61a8423 WG |
101 | #define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */ |
102 | #define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */ | |
103 | ||
edf42a27 SH |
104 | #define EMS_PCI_BASE_SIZE 4096 /* size of controller area */ |
105 | ||
a3aa1884 | 106 | static DEFINE_PCI_DEVICE_TABLE(ems_pci_tbl) = { |
dd52856b SH |
107 | /* CPC-PCI v1 */ |
108 | {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,}, | |
109 | /* CPC-PCI v2 */ | |
110 | {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000}, | |
111 | /* CPC-104P v2 */ | |
112 | {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002}, | |
a61a8423 WG |
113 | {0,} |
114 | }; | |
115 | MODULE_DEVICE_TABLE(pci, ems_pci_tbl); | |
116 | ||
117 | /* | |
118 | * Helper to read internal registers from card logic (not CAN) | |
119 | */ | |
dd52856b | 120 | static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port) |
a61a8423 | 121 | { |
dd52856b | 122 | return readb(card->base_addr + (port * 4)); |
a61a8423 WG |
123 | } |
124 | ||
dd52856b | 125 | static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port) |
a61a8423 | 126 | { |
dd52856b | 127 | return readb(priv->reg_base + (port * 4)); |
a61a8423 WG |
128 | } |
129 | ||
dd52856b SH |
130 | static void ems_pci_v1_write_reg(const struct sja1000_priv *priv, |
131 | int port, u8 val) | |
a61a8423 | 132 | { |
dd52856b | 133 | writeb(val, priv->reg_base + (port * 4)); |
a61a8423 WG |
134 | } |
135 | ||
dd52856b | 136 | static void ems_pci_v1_post_irq(const struct sja1000_priv *priv) |
a61a8423 | 137 | { |
a61a8423 WG |
138 | struct ems_pci_card *card = (struct ems_pci_card *)priv->priv; |
139 | ||
140 | /* reset int flag of pita */ | |
dd52856b SH |
141 | writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0, |
142 | card->conf_addr + PITA2_ICR); | |
143 | } | |
144 | ||
145 | static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port) | |
146 | { | |
147 | return readb(priv->reg_base + port); | |
148 | } | |
149 | ||
150 | static void ems_pci_v2_write_reg(const struct sja1000_priv *priv, | |
151 | int port, u8 val) | |
152 | { | |
153 | writeb(val, priv->reg_base + port); | |
154 | } | |
155 | ||
156 | static void ems_pci_v2_post_irq(const struct sja1000_priv *priv) | |
157 | { | |
158 | struct ems_pci_card *card = (struct ems_pci_card *)priv->priv; | |
159 | ||
160 | writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR); | |
a61a8423 WG |
161 | } |
162 | ||
163 | /* | |
164 | * Check if a CAN controller is present at the specified location | |
165 | * by trying to set 'em into the PeliCAN mode | |
166 | */ | |
255a9154 | 167 | static inline int ems_pci_check_chan(const struct sja1000_priv *priv) |
a61a8423 WG |
168 | { |
169 | unsigned char res; | |
170 | ||
171 | /* Make sure SJA1000 is in reset mode */ | |
dd52856b | 172 | priv->write_reg(priv, REG_MOD, 1); |
a61a8423 | 173 | |
dd52856b | 174 | priv->write_reg(priv, REG_CDR, CDR_PELICAN); |
a61a8423 WG |
175 | |
176 | /* read reset-values */ | |
dd52856b | 177 | res = priv->read_reg(priv, REG_CDR); |
a61a8423 WG |
178 | |
179 | if (res == CDR_PELICAN) | |
180 | return 1; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static void ems_pci_del_card(struct pci_dev *pdev) | |
186 | { | |
187 | struct ems_pci_card *card = pci_get_drvdata(pdev); | |
188 | struct net_device *dev; | |
189 | int i = 0; | |
190 | ||
191 | for (i = 0; i < card->channels; i++) { | |
192 | dev = card->net_dev[i]; | |
193 | ||
194 | if (!dev) | |
195 | continue; | |
196 | ||
197 | dev_info(&pdev->dev, "Removing %s.\n", dev->name); | |
198 | unregister_sja1000dev(dev); | |
199 | free_sja1000dev(dev); | |
200 | } | |
201 | ||
202 | if (card->base_addr != NULL) | |
203 | pci_iounmap(card->pci_dev, card->base_addr); | |
204 | ||
205 | if (card->conf_addr != NULL) | |
206 | pci_iounmap(card->pci_dev, card->conf_addr); | |
207 | ||
208 | kfree(card); | |
209 | ||
210 | pci_disable_device(pdev); | |
211 | pci_set_drvdata(pdev, NULL); | |
212 | } | |
213 | ||
214 | static void ems_pci_card_reset(struct ems_pci_card *card) | |
215 | { | |
216 | /* Request board reset */ | |
217 | writeb(0, card->base_addr); | |
218 | } | |
219 | ||
220 | /* | |
221 | * Probe PCI device for EMS CAN signature and register each available | |
222 | * CAN channel to SJA1000 Socket-CAN subsystem. | |
223 | */ | |
224 | static int __devinit ems_pci_add_card(struct pci_dev *pdev, | |
225 | const struct pci_device_id *ent) | |
226 | { | |
227 | struct sja1000_priv *priv; | |
228 | struct net_device *dev; | |
229 | struct ems_pci_card *card; | |
edf42a27 | 230 | int max_chan, conf_size, base_bar; |
a61a8423 WG |
231 | int err, i; |
232 | ||
233 | /* Enabling PCI device */ | |
234 | if (pci_enable_device(pdev) < 0) { | |
235 | dev_err(&pdev->dev, "Enabling PCI device failed\n"); | |
236 | return -ENODEV; | |
237 | } | |
238 | ||
239 | /* Allocating card structures to hold addresses, ... */ | |
240 | card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL); | |
241 | if (card == NULL) { | |
242 | dev_err(&pdev->dev, "Unable to allocate memory\n"); | |
243 | pci_disable_device(pdev); | |
244 | return -ENOMEM; | |
245 | } | |
246 | ||
247 | pci_set_drvdata(pdev, card); | |
248 | ||
249 | card->pci_dev = pdev; | |
250 | ||
251 | card->channels = 0; | |
252 | ||
dd52856b SH |
253 | if (pdev->vendor == PCI_VENDOR_ID_PLX) { |
254 | card->version = 2; /* CPC-PCI v2 */ | |
255 | max_chan = EMS_PCI_V2_MAX_CHAN; | |
256 | base_bar = EMS_PCI_V2_BASE_BAR; | |
edf42a27 | 257 | conf_size = EMS_PCI_V2_CONF_SIZE; |
dd52856b SH |
258 | } else { |
259 | card->version = 1; /* CPC-PCI v1 */ | |
260 | max_chan = EMS_PCI_V1_MAX_CHAN; | |
261 | base_bar = EMS_PCI_V1_BASE_BAR; | |
edf42a27 | 262 | conf_size = EMS_PCI_V1_CONF_SIZE; |
dd52856b SH |
263 | } |
264 | ||
265 | /* Remap configuration space and controller memory area */ | |
edf42a27 | 266 | card->conf_addr = pci_iomap(pdev, 0, conf_size); |
a61a8423 WG |
267 | if (card->conf_addr == NULL) { |
268 | err = -ENOMEM; | |
a61a8423 WG |
269 | goto failure_cleanup; |
270 | } | |
271 | ||
edf42a27 | 272 | card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE); |
a61a8423 WG |
273 | if (card->base_addr == NULL) { |
274 | err = -ENOMEM; | |
a61a8423 WG |
275 | goto failure_cleanup; |
276 | } | |
277 | ||
dd52856b SH |
278 | if (card->version == 1) { |
279 | /* Configure PITA-2 parallel interface (enable MUX) */ | |
280 | writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC); | |
281 | ||
282 | /* Check for unique EMS CAN signature */ | |
283 | if (ems_pci_v1_readb(card, 0) != 0x55 || | |
284 | ems_pci_v1_readb(card, 1) != 0xAA || | |
285 | ems_pci_v1_readb(card, 2) != 0x01 || | |
286 | ems_pci_v1_readb(card, 3) != 0xCB || | |
287 | ems_pci_v1_readb(card, 4) != 0x11) { | |
288 | dev_err(&pdev->dev, | |
289 | "Not EMS Dr. Thomas Wuensche interface\n"); | |
290 | err = -ENODEV; | |
291 | goto failure_cleanup; | |
292 | } | |
a61a8423 WG |
293 | } |
294 | ||
295 | ems_pci_card_reset(card); | |
296 | ||
297 | /* Detect available channels */ | |
dd52856b | 298 | for (i = 0; i < max_chan; i++) { |
a61a8423 WG |
299 | dev = alloc_sja1000dev(0); |
300 | if (dev == NULL) { | |
301 | err = -ENOMEM; | |
302 | goto failure_cleanup; | |
303 | } | |
304 | ||
305 | card->net_dev[i] = dev; | |
306 | priv = netdev_priv(dev); | |
307 | priv->priv = card; | |
308 | priv->irq_flags = IRQF_SHARED; | |
309 | ||
310 | dev->irq = pdev->irq; | |
255a9154 WG |
311 | priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET |
312 | + (i * EMS_PCI_CAN_CTRL_SIZE); | |
dd52856b SH |
313 | if (card->version == 1) { |
314 | priv->read_reg = ems_pci_v1_read_reg; | |
315 | priv->write_reg = ems_pci_v1_write_reg; | |
316 | priv->post_irq = ems_pci_v1_post_irq; | |
317 | } else { | |
318 | priv->read_reg = ems_pci_v2_read_reg; | |
319 | priv->write_reg = ems_pci_v2_write_reg; | |
320 | priv->post_irq = ems_pci_v2_post_irq; | |
321 | } | |
a61a8423 WG |
322 | |
323 | /* Check if channel is present */ | |
255a9154 | 324 | if (ems_pci_check_chan(priv)) { |
a61a8423 WG |
325 | priv->can.clock.freq = EMS_PCI_CAN_CLOCK; |
326 | priv->ocr = EMS_PCI_OCR; | |
327 | priv->cdr = EMS_PCI_CDR; | |
328 | ||
329 | SET_NETDEV_DEV(dev, &pdev->dev); | |
330 | ||
dd52856b SH |
331 | if (card->version == 1) |
332 | /* reset int flag of pita */ | |
333 | writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0, | |
334 | card->conf_addr + PITA2_ICR); | |
335 | else | |
336 | /* enable IRQ in PLX 9030 */ | |
337 | writel(PLX_ICSR_ENA_CLR, | |
338 | card->conf_addr + PLX_ICSR); | |
a61a8423 WG |
339 | |
340 | /* Register SJA1000 device */ | |
341 | err = register_sja1000dev(dev); | |
342 | if (err) { | |
343 | dev_err(&pdev->dev, "Registering device failed " | |
344 | "(err=%d)\n", err); | |
345 | free_sja1000dev(dev); | |
346 | goto failure_cleanup; | |
347 | } | |
348 | ||
349 | card->channels++; | |
350 | ||
255a9154 WG |
351 | dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n", |
352 | i + 1, priv->reg_base, dev->irq); | |
a61a8423 WG |
353 | } else { |
354 | free_sja1000dev(dev); | |
355 | } | |
356 | } | |
357 | ||
358 | return 0; | |
359 | ||
360 | failure_cleanup: | |
361 | dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); | |
362 | ||
363 | ems_pci_del_card(pdev); | |
364 | ||
365 | return err; | |
366 | } | |
367 | ||
368 | static struct pci_driver ems_pci_driver = { | |
369 | .name = DRV_NAME, | |
370 | .id_table = ems_pci_tbl, | |
371 | .probe = ems_pci_add_card, | |
372 | .remove = ems_pci_del_card, | |
373 | }; | |
374 | ||
375 | static int __init ems_pci_init(void) | |
376 | { | |
377 | return pci_register_driver(&ems_pci_driver); | |
378 | } | |
379 | ||
380 | static void __exit ems_pci_exit(void) | |
381 | { | |
382 | pci_unregister_driver(&ems_pci_driver); | |
383 | } | |
384 | ||
385 | module_init(ems_pci_init); | |
386 | module_exit(ems_pci_exit); | |
387 |