]>
Commit | Line | Data |
---|---|---|
38034518 WG |
1 | /* |
2 | * Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> | |
e6d9c80b | 3 | * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com> |
38034518 WG |
4 | * |
5 | * Derived from the PCAN project file driver/src/pcan_pci.c: | |
6 | * | |
7 | * Copyright (C) 2001-2006 PEAK System-Technik GmbH | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the version 2 of the GNU General Public License | |
11 | * as published by the Free Software Foundation | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
38034518 WG |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
38034518 WG |
20 | #include <linux/module.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/io.h> | |
e6d9c80b SG |
26 | #include <linux/i2c.h> |
27 | #include <linux/i2c-algo-bit.h> | |
38034518 WG |
28 | #include <linux/can.h> |
29 | #include <linux/can/dev.h> | |
30 | ||
31 | #include "sja1000.h" | |
32 | ||
fc09e367 | 33 | MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>"); |
e6d9c80b SG |
34 | MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI family cards"); |
35 | MODULE_SUPPORTED_DEVICE("PEAK PCAN PCI/PCIe/PCIeC miniPCI CAN cards"); | |
fc09e367 | 36 | MODULE_SUPPORTED_DEVICE("PEAK PCAN miniPCIe/cPCI PC/104+ PCI/104e CAN Cards"); |
38034518 WG |
37 | MODULE_LICENSE("GPL v2"); |
38 | ||
39 | #define DRV_NAME "peak_pci" | |
40 | ||
e6d9c80b | 41 | struct peak_pciec_card; |
38034518 | 42 | struct peak_pci_chan { |
29830406 SG |
43 | void __iomem *cfg_base; /* Common for all channels */ |
44 | struct net_device *prev_dev; /* Chain of network devices */ | |
45 | u16 icr_mask; /* Interrupt mask for fast ack */ | |
e6d9c80b | 46 | struct peak_pciec_card *pciec_card; /* only for PCIeC LEDs */ |
38034518 WG |
47 | }; |
48 | ||
49 | #define PEAK_PCI_CAN_CLOCK (16000000 / 2) | |
50 | ||
51 | #define PEAK_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) | |
52 | #define PEAK_PCI_OCR OCR_TX0_PUSHPULL | |
53 | ||
54 | /* | |
55 | * Important PITA registers | |
56 | */ | |
57 | #define PITA_ICR 0x00 /* Interrupt control register */ | |
58 | #define PITA_GPIOICR 0x18 /* GPIO interface control register */ | |
59 | #define PITA_MISC 0x1C /* Miscellaneous register */ | |
60 | ||
61 | #define PEAK_PCI_CFG_SIZE 0x1000 /* Size of the config PCI bar */ | |
62 | #define PEAK_PCI_CHAN_SIZE 0x0400 /* Size used by the channel */ | |
63 | ||
64 | #define PEAK_PCI_VENDOR_ID 0x001C /* The PCI device and vendor IDs */ | |
65 | #define PEAK_PCI_DEVICE_ID 0x0001 /* for PCI/PCIe slot cards */ | |
e6d9c80b SG |
66 | #define PEAK_PCIEC_DEVICE_ID 0x0002 /* for ExpressCard slot cards */ |
67 | #define PEAK_PCIE_DEVICE_ID 0x0003 /* for nextgen PCIe slot cards */ | |
fc09e367 SG |
68 | #define PEAK_CPCI_DEVICE_ID 0x0004 /* for nextgen cPCI slot cards */ |
69 | #define PEAK_MPCI_DEVICE_ID 0x0005 /* for nextgen miniPCI slot cards */ | |
70 | #define PEAK_PC_104P_DEVICE_ID 0x0006 /* PCAN-PC/104+ cards */ | |
71 | #define PEAK_PCI_104E_DEVICE_ID 0x0007 /* PCAN-PCI/104 Express cards */ | |
72 | #define PEAK_MPCIE_DEVICE_ID 0x0008 /* The miniPCIe slot cards */ | |
4be0015c OH |
73 | #define PEAK_PCIE_OEM_ID 0x0009 /* PCAN-PCI Express OEM */ |
74 | #define PEAK_PCIEC34_DEVICE_ID 0x000A /* PCAN-PCI Express 34 (one channel) */ | |
e6d9c80b SG |
75 | |
76 | #define PEAK_PCI_CHAN_MAX 4 | |
38034518 | 77 | |
e6d9c80b SG |
78 | static const u16 peak_pci_icr_masks[PEAK_PCI_CHAN_MAX] = { |
79 | 0x02, 0x01, 0x40, 0x80 | |
80 | }; | |
38034518 | 81 | |
9baa3c34 | 82 | static const struct pci_device_id peak_pci_tbl[] = { |
38034518 | 83 | {PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
e6d9c80b SG |
84 | {PEAK_PCI_VENDOR_ID, PEAK_PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
85 | {PEAK_PCI_VENDOR_ID, PEAK_MPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
fc09e367 SG |
86 | {PEAK_PCI_VENDOR_ID, PEAK_MPCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
87 | {PEAK_PCI_VENDOR_ID, PEAK_PC_104P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
88 | {PEAK_PCI_VENDOR_ID, PEAK_PCI_104E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
89 | {PEAK_PCI_VENDOR_ID, PEAK_CPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
7253054e | 90 | {PEAK_PCI_VENDOR_ID, PEAK_PCIE_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
e6d9c80b SG |
91 | #ifdef CONFIG_CAN_PEAK_PCIEC |
92 | {PEAK_PCI_VENDOR_ID, PEAK_PCIEC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
4be0015c | 93 | {PEAK_PCI_VENDOR_ID, PEAK_PCIEC34_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
e6d9c80b | 94 | #endif |
38034518 WG |
95 | {0,} |
96 | }; | |
97 | ||
98 | MODULE_DEVICE_TABLE(pci, peak_pci_tbl); | |
99 | ||
e6d9c80b SG |
100 | #ifdef CONFIG_CAN_PEAK_PCIEC |
101 | /* | |
102 | * PCAN-ExpressCard needs I2C bit-banging configuration option. | |
103 | */ | |
104 | ||
105 | /* GPIOICR byte access offsets */ | |
106 | #define PITA_GPOUT 0x18 /* GPx output value */ | |
107 | #define PITA_GPIN 0x19 /* GPx input value */ | |
108 | #define PITA_GPOEN 0x1A /* configure GPx as ouput pin */ | |
109 | ||
110 | /* I2C GP bits */ | |
111 | #define PITA_GPIN_SCL 0x01 /* Serial Clock Line */ | |
112 | #define PITA_GPIN_SDA 0x04 /* Serial DAta line */ | |
113 | ||
114 | #define PCA9553_1_SLAVEADDR (0xC4 >> 1) | |
115 | ||
116 | /* PCA9553 LS0 fields values */ | |
117 | enum { | |
118 | PCA9553_LOW, | |
119 | PCA9553_HIGHZ, | |
120 | PCA9553_PWM0, | |
121 | PCA9553_PWM1 | |
122 | }; | |
123 | ||
124 | /* LEDs control */ | |
125 | #define PCA9553_ON PCA9553_LOW | |
126 | #define PCA9553_OFF PCA9553_HIGHZ | |
127 | #define PCA9553_SLOW PCA9553_PWM0 | |
128 | #define PCA9553_FAST PCA9553_PWM1 | |
129 | ||
130 | #define PCA9553_LED(c) (1 << (c)) | |
131 | #define PCA9553_LED_STATE(s, c) ((s) << ((c) << 1)) | |
132 | ||
133 | #define PCA9553_LED_ON(c) PCA9553_LED_STATE(PCA9553_ON, c) | |
134 | #define PCA9553_LED_OFF(c) PCA9553_LED_STATE(PCA9553_OFF, c) | |
135 | #define PCA9553_LED_SLOW(c) PCA9553_LED_STATE(PCA9553_SLOW, c) | |
136 | #define PCA9553_LED_FAST(c) PCA9553_LED_STATE(PCA9553_FAST, c) | |
137 | #define PCA9553_LED_MASK(c) PCA9553_LED_STATE(0x03, c) | |
138 | ||
139 | #define PCA9553_LED_OFF_ALL (PCA9553_LED_OFF(0) | PCA9553_LED_OFF(1)) | |
140 | ||
141 | #define PCA9553_LS0_INIT 0x40 /* initial value (!= from 0x00) */ | |
142 | ||
143 | struct peak_pciec_chan { | |
144 | struct net_device *netdev; | |
145 | unsigned long prev_rx_bytes; | |
146 | unsigned long prev_tx_bytes; | |
147 | }; | |
148 | ||
149 | struct peak_pciec_card { | |
150 | void __iomem *cfg_base; /* Common for all channels */ | |
151 | void __iomem *reg_base; /* first channel base address */ | |
152 | u8 led_cache; /* leds state cache */ | |
153 | ||
154 | /* PCIExpressCard i2c data */ | |
155 | struct i2c_algo_bit_data i2c_bit; | |
156 | struct i2c_adapter led_chip; | |
157 | struct delayed_work led_work; /* led delayed work */ | |
158 | int chan_count; | |
159 | struct peak_pciec_chan channel[PEAK_PCI_CHAN_MAX]; | |
160 | }; | |
161 | ||
162 | /* "normal" pci register write callback is overloaded for leds control */ | |
163 | static void peak_pci_write_reg(const struct sja1000_priv *priv, | |
164 | int port, u8 val); | |
165 | ||
166 | static inline void pita_set_scl_highz(struct peak_pciec_card *card) | |
167 | { | |
168 | u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SCL; | |
169 | writeb(gp_outen, card->cfg_base + PITA_GPOEN); | |
170 | } | |
171 | ||
172 | static inline void pita_set_sda_highz(struct peak_pciec_card *card) | |
173 | { | |
174 | u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SDA; | |
175 | writeb(gp_outen, card->cfg_base + PITA_GPOEN); | |
176 | } | |
177 | ||
178 | static void peak_pciec_init_pita_gpio(struct peak_pciec_card *card) | |
179 | { | |
180 | /* raise SCL & SDA GPIOs to high-Z */ | |
181 | pita_set_scl_highz(card); | |
182 | pita_set_sda_highz(card); | |
183 | } | |
184 | ||
185 | static void pita_setsda(void *data, int state) | |
186 | { | |
187 | struct peak_pciec_card *card = (struct peak_pciec_card *)data; | |
188 | u8 gp_out, gp_outen; | |
189 | ||
190 | /* set output sda always to 0 */ | |
191 | gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SDA; | |
192 | writeb(gp_out, card->cfg_base + PITA_GPOUT); | |
193 | ||
194 | /* control output sda with GPOEN */ | |
195 | gp_outen = readb(card->cfg_base + PITA_GPOEN); | |
196 | if (state) | |
197 | gp_outen &= ~PITA_GPIN_SDA; | |
198 | else | |
199 | gp_outen |= PITA_GPIN_SDA; | |
200 | ||
201 | writeb(gp_outen, card->cfg_base + PITA_GPOEN); | |
202 | } | |
203 | ||
204 | static void pita_setscl(void *data, int state) | |
205 | { | |
206 | struct peak_pciec_card *card = (struct peak_pciec_card *)data; | |
207 | u8 gp_out, gp_outen; | |
208 | ||
209 | /* set output scl always to 0 */ | |
210 | gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SCL; | |
211 | writeb(gp_out, card->cfg_base + PITA_GPOUT); | |
212 | ||
213 | /* control output scl with GPOEN */ | |
214 | gp_outen = readb(card->cfg_base + PITA_GPOEN); | |
215 | if (state) | |
216 | gp_outen &= ~PITA_GPIN_SCL; | |
217 | else | |
218 | gp_outen |= PITA_GPIN_SCL; | |
219 | ||
220 | writeb(gp_outen, card->cfg_base + PITA_GPOEN); | |
221 | } | |
222 | ||
223 | static int pita_getsda(void *data) | |
224 | { | |
225 | struct peak_pciec_card *card = (struct peak_pciec_card *)data; | |
226 | ||
227 | /* set tristate */ | |
228 | pita_set_sda_highz(card); | |
229 | ||
230 | return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SDA) ? 1 : 0; | |
231 | } | |
232 | ||
233 | static int pita_getscl(void *data) | |
234 | { | |
235 | struct peak_pciec_card *card = (struct peak_pciec_card *)data; | |
236 | ||
237 | /* set tristate */ | |
238 | pita_set_scl_highz(card); | |
239 | ||
240 | return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SCL) ? 1 : 0; | |
241 | } | |
242 | ||
243 | /* | |
244 | * write commands to the LED chip though the I2C-bus of the PCAN-PCIeC | |
245 | */ | |
246 | static int peak_pciec_write_pca9553(struct peak_pciec_card *card, | |
247 | u8 offset, u8 data) | |
248 | { | |
249 | u8 buffer[2] = { | |
250 | offset, | |
251 | data | |
252 | }; | |
253 | struct i2c_msg msg = { | |
254 | .addr = PCA9553_1_SLAVEADDR, | |
255 | .len = 2, | |
256 | .buf = buffer, | |
257 | }; | |
258 | int ret; | |
259 | ||
260 | /* cache led mask */ | |
261 | if ((offset == 5) && (data == card->led_cache)) | |
262 | return 0; | |
263 | ||
264 | ret = i2c_transfer(&card->led_chip, &msg, 1); | |
265 | if (ret < 0) | |
266 | return ret; | |
267 | ||
268 | if (offset == 5) | |
269 | card->led_cache = data; | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
274 | /* | |
275 | * delayed work callback used to control the LEDs | |
276 | */ | |
277 | static void peak_pciec_led_work(struct work_struct *work) | |
278 | { | |
279 | struct peak_pciec_card *card = | |
280 | container_of(work, struct peak_pciec_card, led_work.work); | |
281 | struct net_device *netdev; | |
282 | u8 new_led = card->led_cache; | |
283 | int i, up_count = 0; | |
284 | ||
285 | /* first check what is to do */ | |
286 | for (i = 0; i < card->chan_count; i++) { | |
287 | /* default is: not configured */ | |
288 | new_led &= ~PCA9553_LED_MASK(i); | |
289 | new_led |= PCA9553_LED_ON(i); | |
290 | ||
291 | netdev = card->channel[i].netdev; | |
292 | if (!netdev || !(netdev->flags & IFF_UP)) | |
293 | continue; | |
294 | ||
295 | up_count++; | |
296 | ||
297 | /* no activity (but configured) */ | |
298 | new_led &= ~PCA9553_LED_MASK(i); | |
299 | new_led |= PCA9553_LED_SLOW(i); | |
300 | ||
301 | /* if bytes counters changed, set fast blinking led */ | |
302 | if (netdev->stats.rx_bytes != card->channel[i].prev_rx_bytes) { | |
303 | card->channel[i].prev_rx_bytes = netdev->stats.rx_bytes; | |
304 | new_led &= ~PCA9553_LED_MASK(i); | |
305 | new_led |= PCA9553_LED_FAST(i); | |
306 | } | |
307 | if (netdev->stats.tx_bytes != card->channel[i].prev_tx_bytes) { | |
308 | card->channel[i].prev_tx_bytes = netdev->stats.tx_bytes; | |
309 | new_led &= ~PCA9553_LED_MASK(i); | |
310 | new_led |= PCA9553_LED_FAST(i); | |
311 | } | |
312 | } | |
313 | ||
314 | /* check if LS0 settings changed, only update i2c if so */ | |
315 | peak_pciec_write_pca9553(card, 5, new_led); | |
316 | ||
317 | /* restart timer (except if no more configured channels) */ | |
318 | if (up_count) | |
319 | schedule_delayed_work(&card->led_work, HZ); | |
320 | } | |
321 | ||
322 | /* | |
323 | * set LEDs blinking state | |
324 | */ | |
325 | static void peak_pciec_set_leds(struct peak_pciec_card *card, u8 led_mask, u8 s) | |
326 | { | |
327 | u8 new_led = card->led_cache; | |
328 | int i; | |
329 | ||
330 | /* first check what is to do */ | |
331 | for (i = 0; i < card->chan_count; i++) | |
332 | if (led_mask & PCA9553_LED(i)) { | |
333 | new_led &= ~PCA9553_LED_MASK(i); | |
334 | new_led |= PCA9553_LED_STATE(s, i); | |
335 | } | |
336 | ||
337 | /* check if LS0 settings changed, only update i2c if so */ | |
338 | peak_pciec_write_pca9553(card, 5, new_led); | |
339 | } | |
340 | ||
341 | /* | |
342 | * start one second delayed work to control LEDs | |
343 | */ | |
344 | static void peak_pciec_start_led_work(struct peak_pciec_card *card) | |
345 | { | |
1cab3f9f | 346 | schedule_delayed_work(&card->led_work, HZ); |
e6d9c80b SG |
347 | } |
348 | ||
349 | /* | |
350 | * stop LEDs delayed work | |
351 | */ | |
352 | static void peak_pciec_stop_led_work(struct peak_pciec_card *card) | |
353 | { | |
354 | cancel_delayed_work_sync(&card->led_work); | |
355 | } | |
356 | ||
357 | /* | |
358 | * initialize the PCA9553 4-bit I2C-bus LED chip | |
359 | */ | |
360 | static int peak_pciec_init_leds(struct peak_pciec_card *card) | |
361 | { | |
362 | int err; | |
363 | ||
364 | /* prescaler for frequency 0: "SLOW" = 1 Hz = "44" */ | |
365 | err = peak_pciec_write_pca9553(card, 1, 44 / 1); | |
366 | if (err) | |
367 | return err; | |
368 | ||
369 | /* duty cycle 0: 50% */ | |
370 | err = peak_pciec_write_pca9553(card, 2, 0x80); | |
371 | if (err) | |
372 | return err; | |
373 | ||
374 | /* prescaler for frequency 1: "FAST" = 5 Hz */ | |
375 | err = peak_pciec_write_pca9553(card, 3, 44 / 5); | |
376 | if (err) | |
377 | return err; | |
378 | ||
379 | /* duty cycle 1: 50% */ | |
380 | err = peak_pciec_write_pca9553(card, 4, 0x80); | |
381 | if (err) | |
382 | return err; | |
383 | ||
384 | /* switch LEDs to initial state */ | |
385 | return peak_pciec_write_pca9553(card, 5, PCA9553_LS0_INIT); | |
386 | } | |
387 | ||
388 | /* | |
389 | * restore LEDs state to off peak_pciec_leds_exit | |
390 | */ | |
391 | static void peak_pciec_leds_exit(struct peak_pciec_card *card) | |
392 | { | |
393 | /* switch LEDs to off */ | |
394 | peak_pciec_write_pca9553(card, 5, PCA9553_LED_OFF_ALL); | |
395 | } | |
396 | ||
397 | /* | |
398 | * normal write sja1000 register method overloaded to catch when controller | |
399 | * is started or stopped, to control leds | |
400 | */ | |
401 | static void peak_pciec_write_reg(const struct sja1000_priv *priv, | |
402 | int port, u8 val) | |
403 | { | |
404 | struct peak_pci_chan *chan = priv->priv; | |
405 | struct peak_pciec_card *card = chan->pciec_card; | |
406 | int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; | |
407 | ||
408 | /* sja1000 register changes control the leds state */ | |
06e1d1d7 | 409 | if (port == SJA1000_MOD) |
e6d9c80b SG |
410 | switch (val) { |
411 | case MOD_RM: | |
412 | /* Reset Mode: set led on */ | |
413 | peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_ON); | |
414 | break; | |
415 | case 0x00: | |
416 | /* Normal Mode: led slow blinking and start led timer */ | |
417 | peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_SLOW); | |
418 | peak_pciec_start_led_work(card); | |
419 | break; | |
420 | default: | |
421 | break; | |
422 | } | |
423 | ||
424 | /* call base function */ | |
425 | peak_pci_write_reg(priv, port, val); | |
426 | } | |
427 | ||
428 | static struct i2c_algo_bit_data peak_pciec_i2c_bit_ops = { | |
429 | .setsda = pita_setsda, | |
430 | .setscl = pita_setscl, | |
431 | .getsda = pita_getsda, | |
432 | .getscl = pita_getscl, | |
433 | .udelay = 10, | |
434 | .timeout = HZ, | |
435 | }; | |
436 | ||
437 | static int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev) | |
438 | { | |
439 | struct sja1000_priv *priv = netdev_priv(dev); | |
440 | struct peak_pci_chan *chan = priv->priv; | |
441 | struct peak_pciec_card *card; | |
442 | int err; | |
443 | ||
444 | /* copy i2c object address from 1st channel */ | |
445 | if (chan->prev_dev) { | |
446 | struct sja1000_priv *prev_priv = netdev_priv(chan->prev_dev); | |
447 | struct peak_pci_chan *prev_chan = prev_priv->priv; | |
448 | ||
449 | card = prev_chan->pciec_card; | |
450 | if (!card) | |
451 | return -ENODEV; | |
452 | ||
453 | /* channel is the first one: do the init part */ | |
454 | } else { | |
455 | /* create the bit banging I2C adapter structure */ | |
456 | card = kzalloc(sizeof(struct peak_pciec_card), GFP_KERNEL); | |
09da6c5f | 457 | if (!card) |
e6d9c80b | 458 | return -ENOMEM; |
e6d9c80b SG |
459 | |
460 | card->cfg_base = chan->cfg_base; | |
461 | card->reg_base = priv->reg_base; | |
462 | ||
463 | card->led_chip.owner = THIS_MODULE; | |
464 | card->led_chip.dev.parent = &pdev->dev; | |
465 | card->led_chip.algo_data = &card->i2c_bit; | |
466 | strncpy(card->led_chip.name, "peak_i2c", | |
467 | sizeof(card->led_chip.name)); | |
468 | ||
469 | card->i2c_bit = peak_pciec_i2c_bit_ops; | |
470 | card->i2c_bit.udelay = 10; | |
471 | card->i2c_bit.timeout = HZ; | |
472 | card->i2c_bit.data = card; | |
473 | ||
474 | peak_pciec_init_pita_gpio(card); | |
475 | ||
476 | err = i2c_bit_add_bus(&card->led_chip); | |
477 | if (err) { | |
478 | dev_err(&pdev->dev, "i2c init failed\n"); | |
479 | goto pciec_init_err_1; | |
480 | } | |
481 | ||
482 | err = peak_pciec_init_leds(card); | |
483 | if (err) { | |
484 | dev_err(&pdev->dev, "leds hardware init failed\n"); | |
485 | goto pciec_init_err_2; | |
486 | } | |
487 | ||
488 | INIT_DELAYED_WORK(&card->led_work, peak_pciec_led_work); | |
489 | /* PCAN-ExpressCard needs its own callback for leds */ | |
490 | priv->write_reg = peak_pciec_write_reg; | |
491 | } | |
492 | ||
493 | chan->pciec_card = card; | |
494 | card->channel[card->chan_count++].netdev = dev; | |
495 | ||
496 | return 0; | |
497 | ||
498 | pciec_init_err_2: | |
499 | i2c_del_adapter(&card->led_chip); | |
500 | ||
501 | pciec_init_err_1: | |
502 | peak_pciec_init_pita_gpio(card); | |
503 | kfree(card); | |
504 | ||
505 | return err; | |
506 | } | |
507 | ||
508 | static void peak_pciec_remove(struct peak_pciec_card *card) | |
509 | { | |
510 | peak_pciec_stop_led_work(card); | |
511 | peak_pciec_leds_exit(card); | |
512 | i2c_del_adapter(&card->led_chip); | |
513 | peak_pciec_init_pita_gpio(card); | |
514 | kfree(card); | |
515 | } | |
516 | ||
517 | #else /* CONFIG_CAN_PEAK_PCIEC */ | |
518 | ||
519 | /* | |
520 | * Placebo functions when PCAN-ExpressCard support is not selected | |
521 | */ | |
522 | static inline int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev) | |
523 | { | |
524 | return -ENODEV; | |
525 | } | |
526 | ||
527 | static inline void peak_pciec_remove(struct peak_pciec_card *card) | |
528 | { | |
529 | } | |
530 | #endif /* CONFIG_CAN_PEAK_PCIEC */ | |
531 | ||
38034518 WG |
532 | static u8 peak_pci_read_reg(const struct sja1000_priv *priv, int port) |
533 | { | |
534 | return readb(priv->reg_base + (port << 2)); | |
535 | } | |
536 | ||
537 | static void peak_pci_write_reg(const struct sja1000_priv *priv, | |
538 | int port, u8 val) | |
539 | { | |
540 | writeb(val, priv->reg_base + (port << 2)); | |
541 | } | |
542 | ||
543 | static void peak_pci_post_irq(const struct sja1000_priv *priv) | |
544 | { | |
545 | struct peak_pci_chan *chan = priv->priv; | |
546 | u16 icr; | |
547 | ||
548 | /* Select and clear in PITA stored interrupt */ | |
549 | icr = readw(chan->cfg_base + PITA_ICR); | |
550 | if (icr & chan->icr_mask) | |
551 | writew(chan->icr_mask, chan->cfg_base + PITA_ICR); | |
552 | } | |
553 | ||
1dd06ae8 | 554 | static int peak_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
38034518 WG |
555 | { |
556 | struct sja1000_priv *priv; | |
557 | struct peak_pci_chan *chan; | |
0b5a958c | 558 | struct net_device *dev, *prev_dev; |
38034518 WG |
559 | void __iomem *cfg_base, *reg_base; |
560 | u16 sub_sys_id, icr; | |
561 | int i, err, channels; | |
562 | ||
563 | err = pci_enable_device(pdev); | |
564 | if (err) | |
565 | return err; | |
566 | ||
567 | err = pci_request_regions(pdev, DRV_NAME); | |
568 | if (err) | |
569 | goto failure_disable_pci; | |
570 | ||
571 | err = pci_read_config_word(pdev, 0x2e, &sub_sys_id); | |
572 | if (err) | |
573 | goto failure_release_regions; | |
574 | ||
575 | dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n", | |
576 | pdev->vendor, pdev->device, sub_sys_id); | |
577 | ||
578 | err = pci_write_config_word(pdev, 0x44, 0); | |
579 | if (err) | |
580 | goto failure_release_regions; | |
581 | ||
582 | if (sub_sys_id >= 12) | |
583 | channels = 4; | |
584 | else if (sub_sys_id >= 10) | |
585 | channels = 3; | |
586 | else if (sub_sys_id >= 4) | |
587 | channels = 2; | |
588 | else | |
589 | channels = 1; | |
590 | ||
591 | cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE); | |
592 | if (!cfg_base) { | |
593 | dev_err(&pdev->dev, "failed to map PCI resource #0\n"); | |
4a4bfdcd | 594 | err = -ENOMEM; |
38034518 WG |
595 | goto failure_release_regions; |
596 | } | |
597 | ||
598 | reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); | |
599 | if (!reg_base) { | |
600 | dev_err(&pdev->dev, "failed to map PCI resource #1\n"); | |
4a4bfdcd | 601 | err = -ENOMEM; |
38034518 WG |
602 | goto failure_unmap_cfg_base; |
603 | } | |
604 | ||
605 | /* Set GPIO control register */ | |
606 | writew(0x0005, cfg_base + PITA_GPIOICR + 2); | |
607 | /* Enable all channels of this card */ | |
608 | writeb(0x00, cfg_base + PITA_GPIOICR); | |
609 | /* Toggle reset */ | |
610 | writeb(0x05, cfg_base + PITA_MISC + 3); | |
611 | mdelay(5); | |
612 | /* Leave parport mux mode */ | |
613 | writeb(0x04, cfg_base + PITA_MISC + 3); | |
614 | ||
615 | icr = readw(cfg_base + PITA_ICR + 2); | |
616 | ||
617 | for (i = 0; i < channels; i++) { | |
618 | dev = alloc_sja1000dev(sizeof(struct peak_pci_chan)); | |
619 | if (!dev) { | |
620 | err = -ENOMEM; | |
621 | goto failure_remove_channels; | |
622 | } | |
623 | ||
624 | priv = netdev_priv(dev); | |
625 | chan = priv->priv; | |
626 | ||
627 | chan->cfg_base = cfg_base; | |
628 | priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE; | |
629 | ||
630 | priv->read_reg = peak_pci_read_reg; | |
631 | priv->write_reg = peak_pci_write_reg; | |
632 | priv->post_irq = peak_pci_post_irq; | |
633 | ||
634 | priv->can.clock.freq = PEAK_PCI_CAN_CLOCK; | |
635 | priv->ocr = PEAK_PCI_OCR; | |
636 | priv->cdr = PEAK_PCI_CDR; | |
637 | /* Neither a slave nor a single device distributes the clock */ | |
638 | if (channels == 1 || i > 0) | |
639 | priv->cdr |= CDR_CLK_OFF; | |
640 | ||
641 | /* Setup interrupt handling */ | |
642 | priv->irq_flags = IRQF_SHARED; | |
643 | dev->irq = pdev->irq; | |
644 | ||
645 | chan->icr_mask = peak_pci_icr_masks[i]; | |
646 | icr |= chan->icr_mask; | |
647 | ||
648 | SET_NETDEV_DEV(dev, &pdev->dev); | |
3e66d013 | 649 | dev->dev_id = i; |
38034518 | 650 | |
e6d9c80b SG |
651 | /* Create chain of SJA1000 devices */ |
652 | chan->prev_dev = pci_get_drvdata(pdev); | |
653 | pci_set_drvdata(pdev, dev); | |
654 | ||
655 | /* | |
656 | * PCAN-ExpressCard needs some additional i2c init. | |
657 | * This must be done *before* register_sja1000dev() but | |
658 | * *after* devices linkage | |
659 | */ | |
4be0015c OH |
660 | if (pdev->device == PEAK_PCIEC_DEVICE_ID || |
661 | pdev->device == PEAK_PCIEC34_DEVICE_ID) { | |
e6d9c80b SG |
662 | err = peak_pciec_probe(pdev, dev); |
663 | if (err) { | |
664 | dev_err(&pdev->dev, | |
665 | "failed to probe device (err %d)\n", | |
666 | err); | |
667 | goto failure_free_dev; | |
668 | } | |
669 | } | |
670 | ||
38034518 WG |
671 | err = register_sja1000dev(dev); |
672 | if (err) { | |
673 | dev_err(&pdev->dev, "failed to register device\n"); | |
e6d9c80b | 674 | goto failure_free_dev; |
38034518 WG |
675 | } |
676 | ||
38034518 WG |
677 | dev_info(&pdev->dev, |
678 | "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n", | |
679 | dev->name, priv->reg_base, chan->cfg_base, dev->irq); | |
680 | } | |
681 | ||
38034518 WG |
682 | /* Enable interrupts */ |
683 | writew(icr, cfg_base + PITA_ICR + 2); | |
684 | ||
685 | return 0; | |
686 | ||
e6d9c80b SG |
687 | failure_free_dev: |
688 | pci_set_drvdata(pdev, chan->prev_dev); | |
689 | free_sja1000dev(dev); | |
690 | ||
38034518 WG |
691 | failure_remove_channels: |
692 | /* Disable interrupts */ | |
693 | writew(0x0, cfg_base + PITA_ICR + 2); | |
694 | ||
e6d9c80b | 695 | chan = NULL; |
0b5a958c | 696 | for (dev = pci_get_drvdata(pdev); dev; dev = prev_dev) { |
38034518 WG |
697 | priv = netdev_priv(dev); |
698 | chan = priv->priv; | |
0b5a958c SG |
699 | prev_dev = chan->prev_dev; |
700 | ||
701 | unregister_sja1000dev(dev); | |
702 | free_sja1000dev(dev); | |
38034518 WG |
703 | } |
704 | ||
e6d9c80b SG |
705 | /* free any PCIeC resources too */ |
706 | if (chan && chan->pciec_card) | |
707 | peak_pciec_remove(chan->pciec_card); | |
708 | ||
38034518 WG |
709 | pci_iounmap(pdev, reg_base); |
710 | ||
711 | failure_unmap_cfg_base: | |
712 | pci_iounmap(pdev, cfg_base); | |
713 | ||
714 | failure_release_regions: | |
715 | pci_release_regions(pdev); | |
716 | ||
717 | failure_disable_pci: | |
718 | pci_disable_device(pdev); | |
719 | ||
720 | return err; | |
721 | } | |
722 | ||
3c8ac0f2 | 723 | static void peak_pci_remove(struct pci_dev *pdev) |
38034518 | 724 | { |
29830406 | 725 | struct net_device *dev = pci_get_drvdata(pdev); /* Last device */ |
38034518 WG |
726 | struct sja1000_priv *priv = netdev_priv(dev); |
727 | struct peak_pci_chan *chan = priv->priv; | |
728 | void __iomem *cfg_base = chan->cfg_base; | |
729 | void __iomem *reg_base = priv->reg_base; | |
730 | ||
731 | /* Disable interrupts */ | |
732 | writew(0x0, cfg_base + PITA_ICR + 2); | |
733 | ||
734 | /* Loop over all registered devices */ | |
735 | while (1) { | |
0b5a958c SG |
736 | struct net_device *prev_dev = chan->prev_dev; |
737 | ||
38034518 WG |
738 | dev_info(&pdev->dev, "removing device %s\n", dev->name); |
739 | unregister_sja1000dev(dev); | |
740 | free_sja1000dev(dev); | |
0b5a958c | 741 | dev = prev_dev; |
e6d9c80b SG |
742 | |
743 | if (!dev) { | |
744 | /* do that only for first channel */ | |
745 | if (chan->pciec_card) | |
746 | peak_pciec_remove(chan->pciec_card); | |
38034518 | 747 | break; |
e6d9c80b | 748 | } |
38034518 WG |
749 | priv = netdev_priv(dev); |
750 | chan = priv->priv; | |
751 | } | |
752 | ||
753 | pci_iounmap(pdev, reg_base); | |
754 | pci_iounmap(pdev, cfg_base); | |
755 | pci_release_regions(pdev); | |
756 | pci_disable_device(pdev); | |
38034518 WG |
757 | } |
758 | ||
759 | static struct pci_driver peak_pci_driver = { | |
760 | .name = DRV_NAME, | |
761 | .id_table = peak_pci_tbl, | |
762 | .probe = peak_pci_probe, | |
3c8ac0f2 | 763 | .remove = peak_pci_remove, |
38034518 WG |
764 | }; |
765 | ||
fb7944b3 | 766 | module_pci_driver(peak_pci_driver); |