[mirror_ubuntu-jammy-kernel.git] / drivers / net / can / sja1000 / plx_pci.c

/*
 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
 *
 * Derived from the ems_pci.c driver:
 *	Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
 *	Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
 *	Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the version 2 of the GNU General Public License
 * as published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/can.h>
#include <linux/can/dev.h>
#include <linux/io.h>

#include "sja1000.h"

#define DRV_NAME  "sja1000_plx_pci"

MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
		   "the SJA1000 chips");
MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
			"Adlink PCI-7841/cPCI-7841 SE, "
			"Marathon CAN-bus-PCI, "
			"TEWS TECHNOLOGIES TPMC810");
MODULE_LICENSE("GPL v2");

#define PLX_PCI_MAX_CHAN 2

struct plx_pci_card {
	int channels;			/* detected channels count */
	struct net_device *net_dev[PLX_PCI_MAX_CHAN];
	void __iomem *conf_addr;
};

#define PLX_PCI_CAN_CLOCK (16000000 / 2)

/* PLX90xx registers */
#define PLX_INTCSR	0x4c		/* Interrupt Control/Status */
#define PLX_CNTRL	0x50		/* User I/O, Direct Slave Response,
					 * Serial EEPROM, and Initialization
					 * Control register
					 */

#define PLX_LINT1_EN	0x1		/* Local interrupt 1 enable */
#define PLX_LINT2_EN	(1 << 3)	/* Local interrupt 2 enable */
#define PLX_PCI_INT_EN	(1 << 6)	/* PCI Interrupt Enable */
#define PLX_PCI_RESET	(1 << 30)	/* PCI Adapter Software Reset */

/*
 * The board configuration is probably following:
 * RX1 is connected to ground.
 * TX1 is not connected.
 * CLKO is not connected.
 * Setting the OCR register to 0xDA is a good idea.
 * This means normal output mode, push-pull and the correct polarity.
 */
#define PLX_PCI_OCR	(OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)

/*
 * In the CDR register, you should set CBP to 1.
 * You will probably also want to set the clock divider value to 7
 * (meaning direct oscillator output) because the second SJA1000 chip
 * is driven by the first one CLKOUT output.
 */
#define PLX_PCI_CDR			(CDR_CBP | CDR_CLKOUT_MASK)

/* SJA1000 Control Register in the BasicCAN Mode */
#define REG_CR				0x00

/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
#define REG_CR_BASICCAN_INITIAL		0x21
#define REG_CR_BASICCAN_INITIAL_MASK	0xa1
#define REG_SR_BASICCAN_INITIAL		0x0c
#define REG_IR_BASICCAN_INITIAL		0xe0

/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
#define REG_MOD_PELICAN_INITIAL		0x01
#define REG_SR_PELICAN_INITIAL		0x3c
#define REG_IR_PELICAN_INITIAL		0x00

#define ADLINK_PCI_VENDOR_ID		0x144A
#define ADLINK_PCI_DEVICE_ID		0x7841

#define MARATHON_PCI_DEVICE_ID		0x2715

#define TEWS_PCI_VENDOR_ID		0x1498
#define TEWS_PCI_DEVICE_ID_TMPC810	0x032A

static void plx_pci_reset_common(struct pci_dev *pdev);
static void plx_pci_reset_marathon(struct pci_dev *pdev);

struct plx_pci_channel_map {
	u32 bar;
	u32 offset;
	u32 size;		/* 0x00 - auto, e.g. length of entire bar */
};

struct plx_pci_card_info {
	const char *name;
	int channel_count;
	u32 can_clock;
	u8 ocr;			/* output control register */
	u8 cdr;			/* clock divider register */

	/* Parameters for mapping local configuration space */
	struct plx_pci_channel_map conf_map;

	/* Parameters for mapping the SJA1000 chips */
	struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];

	/* Pointer to device-dependent reset function */
	void (*reset_func)(struct pci_dev *pdev);
};

static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = {
	"Adlink PCI-7841/cPCI-7841", 2,
	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
	{1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
	&plx_pci_reset_common
	/* based on PLX9052 */
};

static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = {
	"Adlink PCI-7841/cPCI-7841 SE", 2,
	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
	{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
	&plx_pci_reset_common
	/* based on PLX9052 */
};

static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = {
	"Marathon CAN-bus-PCI", 2,
	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
	{0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
	&plx_pci_reset_marathon
	/* based on PLX9052 */
};

static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = {
	"TEWS TECHNOLOGIES TPMC810", 2,
	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
	{0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
	&plx_pci_reset_common
	/* based on PLX9030 */
};

static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = {
	{
		/* Adlink PCI-7841/cPCI-7841 */
		ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_NETWORK_OTHER << 8, ~0,
		(kernel_ulong_t)&plx_pci_card_info_adlink
	},
	{
		/* Adlink PCI-7841/cPCI-7841 SE */
		ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
		(kernel_ulong_t)&plx_pci_card_info_adlink_se
	},
	{
		/* Marathon CAN-bus-PCI card */
		PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		0, 0,
		(kernel_ulong_t)&plx_pci_card_info_marathon
	},
	{
		/* TEWS TECHNOLOGIES TPMC810 card */
		TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
		PCI_ANY_ID, PCI_ANY_ID,
		0, 0,
		(kernel_ulong_t)&plx_pci_card_info_tews
	},
	{ 0,}
};
MODULE_DEVICE_TABLE(pci, plx_pci_tbl);

static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
{
	return ioread8(priv->reg_base + port);
}

static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
{
	iowrite8(val, priv->reg_base + port);
}

/*
 * Check if a CAN controller is present at the specified location
 * by trying to switch 'em from the Basic mode into the PeliCAN mode.
 * Also check states of some registers in reset mode.
 */
static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
{
	int flag = 0;

	/*
	 * Check registers after hardware reset (the Basic mode)
	 * See states on p. 10 of the Datasheet.
	 */
	if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
	    REG_CR_BASICCAN_INITIAL &&
	    (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
	    (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
		flag = 1;

	/* Bring the SJA1000 into the PeliCAN mode*/
	priv->write_reg(priv, REG_CDR, CDR_PELICAN);

	/*
	 * Check registers after reset in the PeliCAN mode.
	 * See states on p. 23 of the Datasheet.
	 */
	if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
	    priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
	    priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
		return flag;

	return 0;
}

/*
 * PLX90xx software reset
 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
 * For most cards it's enough for reset the SJA1000 chips.
 */
static void plx_pci_reset_common(struct pci_dev *pdev)
{
	struct plx_pci_card *card = pci_get_drvdata(pdev);
	u32 cntrl;

	cntrl = ioread32(card->conf_addr + PLX_CNTRL);
	cntrl |= PLX_PCI_RESET;
	iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
	udelay(100);
	cntrl ^= PLX_PCI_RESET;
	iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
};

/* Special reset function for Marathon card */
static void plx_pci_reset_marathon(struct pci_dev *pdev)
{
	void __iomem *reset_addr;
	int i;
	int reset_bar[2] = {3, 5};

	plx_pci_reset_common(pdev);

	for (i = 0; i < 2; i++) {
		reset_addr = pci_iomap(pdev, reset_bar[i], 0);
		if (!reset_addr) {
			dev_err(&pdev->dev, "Failed to remap reset "
				"space %d (BAR%d)\n", i, reset_bar[i]);
		} else {
			/* reset the SJA1000 chip */
			iowrite8(0x1, reset_addr);
			udelay(100);
			pci_iounmap(pdev, reset_addr);
		}
	}
}

static void plx_pci_del_card(struct pci_dev *pdev)
{
	struct plx_pci_card *card = pci_get_drvdata(pdev);
	struct net_device *dev;
	struct sja1000_priv *priv;
	int i = 0;

	for (i = 0; i < card->channels; i++) {
		dev = card->net_dev[i];
		if (!dev)
			continue;

		dev_info(&pdev->dev, "Removing %s\n", dev->name);
		unregister_sja1000dev(dev);
		priv = netdev_priv(dev);
		if (priv->reg_base)
			pci_iounmap(pdev, priv->reg_base);
		free_sja1000dev(dev);
	}

	plx_pci_reset_common(pdev);

	/*
	 * Disable interrupts from PCI-card (PLX90xx) and disable Local_1,
	 * Local_2 interrupts
	 */
	iowrite32(0x0, card->conf_addr + PLX_INTCSR);

	if (card->conf_addr)
		pci_iounmap(pdev, card->conf_addr);

	kfree(card);

	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
}

/*
 * Probe PLX90xx based device for the SJA1000 chips and register each
 * available CAN channel to SJA1000 Socket-CAN subsystem.
 */
static int __devinit plx_pci_add_card(struct pci_dev *pdev,
				      const struct pci_device_id *ent)
{
	struct sja1000_priv *priv;
	struct net_device *dev;
	struct plx_pci_card *card;
	struct plx_pci_card_info *ci;
	int err, i;
	u32 val;
	void __iomem *addr;

	ci = (struct plx_pci_card_info *)ent->driver_data;

	if (pci_enable_device(pdev) < 0) {
		dev_err(&pdev->dev, "Failed to enable PCI device\n");
		return -ENODEV;
	}

	dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
		 ci->name, PCI_SLOT(pdev->devfn));

	/* Allocate card structures to hold addresses, ... */
	card = kzalloc(sizeof(*card), GFP_KERNEL);
	if (!card) {
		dev_err(&pdev->dev, "Unable to allocate memory\n");
		pci_disable_device(pdev);
		return -ENOMEM;
	}

	pci_set_drvdata(pdev, card);

	card->channels = 0;

	/* Remap PLX90xx configuration space */
	addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
	if (!addr) {
		err = -ENOMEM;
		dev_err(&pdev->dev, "Failed to remap configuration space "
			"(BAR%d)\n", ci->conf_map.bar);
		goto failure_cleanup;
	}
	card->conf_addr = addr + ci->conf_map.offset;

	ci->reset_func(pdev);

	/* Detect available channels */
	for (i = 0; i < ci->channel_count; i++) {
		struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];

		dev = alloc_sja1000dev(0);
		if (!dev) {
			err = -ENOMEM;
			goto failure_cleanup;
		}

		card->net_dev[i] = dev;
		priv = netdev_priv(dev);
		priv->priv = card;
		priv->irq_flags = IRQF_SHARED;

		dev->irq = pdev->irq;

		/*
		 * Remap IO space of the SJA1000 chips
		 * This is device-dependent mapping
		 */
		addr = pci_iomap(pdev, cm->bar, cm->size);
		if (!addr) {
			err = -ENOMEM;
			dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
			goto failure_cleanup;
		}

		priv->reg_base = addr + cm->offset;
		priv->read_reg = plx_pci_read_reg;
		priv->write_reg = plx_pci_write_reg;

		/* Check if channel is present */
		if (plx_pci_check_sja1000(priv)) {
			priv->can.clock.freq = ci->can_clock;
			priv->ocr = ci->ocr;
			priv->cdr = ci->cdr;

			SET_NETDEV_DEV(dev, &pdev->dev);

			/* Register SJA1000 device */
			err = register_sja1000dev(dev);
			if (err) {
				dev_err(&pdev->dev, "Registering device failed "
					"(err=%d)\n", err);
				free_sja1000dev(dev);
				goto failure_cleanup;
			}

			card->channels++;

			dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
				 "registered as %s\n", i + 1, priv->reg_base,
				 dev->irq, dev->name);
		} else {
			dev_err(&pdev->dev, "Channel #%d not detected\n",
				i + 1);
			free_sja1000dev(dev);
		}
	}

	if (!card->channels) {
		err = -ENODEV;
		goto failure_cleanup;
	}

	/*
	 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
	 * Local_2 interrupts from the SJA1000 chips
	 */
	val = ioread32(card->conf_addr + PLX_INTCSR);
	val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
	iowrite32(val, card->conf_addr + PLX_INTCSR);

	return 0;

failure_cleanup:
	dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);

	plx_pci_del_card(pdev);

	return err;
}

static struct pci_driver plx_pci_driver = {
	.name = DRV_NAME,
	.id_table = plx_pci_tbl,
	.probe = plx_pci_add_card,
	.remove = plx_pci_del_card,
};

static int __init plx_pci_init(void)
{
	return pci_register_driver(&plx_pci_driver);
}

static void __exit plx_pci_exit(void)
{
	pci_unregister_driver(&plx_pci_driver);
}

module_init(plx_pci_init);
module_exit(plx_pci_exit);
Commit	Line	Data
24c4a3b2 PC	1	/*
	2	* Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
	3	*
	4	* Derived from the ems_pci.c driver:
	5	* Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
	6	* Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
	7	* Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the version 2 of the GNU General Public License
	11	* as published by the Free Software Foundation
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	21	*/
	22
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/netdevice.h>
	27	#include <linux/delay.h>
	28	#include <linux/pci.h>
	29	#include <linux/can.h>
	30	#include <linux/can/dev.h>
	31	#include <linux/io.h>
	32
	33	#include "sja1000.h"
	34
	35	#define DRV_NAME "sja1000_plx_pci"
	36
	37	MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
	38	MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
	39	"the SJA1000 chips");
	40	MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
	41	"Adlink PCI-7841/cPCI-7841 SE, "
	42	"Marathon CAN-bus-PCI, "
	43	"TEWS TECHNOLOGIES TPMC810");
	44	MODULE_LICENSE("GPL v2");
	45
	46	#define PLX_PCI_MAX_CHAN 2
	47
	48	struct plx_pci_card {
	49	int channels; /* detected channels count */
	50	struct net_device *net_dev[PLX_PCI_MAX_CHAN];
	51	void __iomem *conf_addr;
	52	};
	53
	54	#define PLX_PCI_CAN_CLOCK (16000000 / 2)
	55
	56	/* PLX90xx registers */
	57	#define PLX_INTCSR 0x4c /* Interrupt Control/Status */
	58	#define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
	59	* Serial EEPROM, and Initialization
	60	* Control register
	61	*/
	62
	63	#define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
	64	#define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
65	#define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
66	#define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
67
68	/*
69	* The board configuration is probably following:
70	* RX1 is connected to ground.
71	* TX1 is not connected.
72	* CLKO is not connected.
73	* Setting the OCR register to 0xDA is a good idea.
74	* This means normal output mode, push-pull and the correct polarity.
75	*/
76	#define PLX_PCI_OCR (OCR_TX0_PUSHPULL \| OCR_TX1_PUSHPULL)
77
78	/*
79	* In the CDR register, you should set CBP to 1.
80	* You will probably also want to set the clock divider value to 7
81	* (meaning direct oscillator output) because the second SJA1000 chip
82	* is driven by the first one CLKOUT output.
83	*/
84	#define PLX_PCI_CDR (CDR_CBP \| CDR_CLKOUT_MASK)
85
86	/* SJA1000 Control Register in the BasicCAN Mode */
87	#define REG_CR 0x00
88
89	/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
90	#define REG_CR_BASICCAN_INITIAL 0x21
91	#define REG_CR_BASICCAN_INITIAL_MASK 0xa1
92	#define REG_SR_BASICCAN_INITIAL 0x0c
93	#define REG_IR_BASICCAN_INITIAL 0xe0
94
95	/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
96	#define REG_MOD_PELICAN_INITIAL 0x01
97	#define REG_SR_PELICAN_INITIAL 0x3c
98	#define REG_IR_PELICAN_INITIAL 0x00
99
100	#define ADLINK_PCI_VENDOR_ID 0x144A
101	#define ADLINK_PCI_DEVICE_ID 0x7841
102
103	#define MARATHON_PCI_DEVICE_ID 0x2715
104
105	#define TEWS_PCI_VENDOR_ID 0x1498
106	#define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
107
108	static void plx_pci_reset_common(struct pci_dev *pdev);
109	static void plx_pci_reset_marathon(struct pci_dev *pdev);
110
111	struct plx_pci_channel_map {
112	u32 bar;
113	u32 offset;
114	u32 size; /* 0x00 - auto, e.g. length of entire bar */
115	};
116
117	struct plx_pci_card_info {
118	const char *name;
119	int channel_count;
120	u32 can_clock;
121	u8 ocr; /* output control register */
122	u8 cdr; /* clock divider register */
123
124	/* Parameters for mapping local configuration space */
125	struct plx_pci_channel_map conf_map;
126
127	/* Parameters for mapping the SJA1000 chips */
128	struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
129
130	/* Pointer to device-dependent reset function */
131	void (reset_func)(struct pci_dev pdev);
132	};
133
134	static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = {
135	"Adlink PCI-7841/cPCI-7841", 2,
136	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
137	{1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
138	&plx_pci_reset_common
139	/* based on PLX9052 */
140	};
141
142	static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = {
143	"Adlink PCI-7841/cPCI-7841 SE", 2,
144	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
145	{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
146	&plx_pci_reset_common
147	/* based on PLX9052 */
148	};
149
150	static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = {
151	"Marathon CAN-bus-PCI", 2,
152	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
153	{0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
154	&plx_pci_reset_marathon
155	/* based on PLX9052 */
156	};
157
158	static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = {
159	"TEWS TECHNOLOGIES TPMC810", 2,
160	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
161	{0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
162	&plx_pci_reset_common
163	/* based on PLX9030 */
164	};
165
166	static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = {
167	{
168	/* Adlink PCI-7841/cPCI-7841 */
169	ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
170	PCI_ANY_ID, PCI_ANY_ID,
171	PCI_CLASS_NETWORK_OTHER << 8, ~0,
172	(kernel_ulong_t)&plx_pci_card_info_adlink
173	},
174	{
175	/* Adlink PCI-7841/cPCI-7841 SE */
176	ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
177	PCI_ANY_ID, PCI_ANY_ID,
178	PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
179	(kernel_ulong_t)&plx_pci_card_info_adlink_se
180	},
181	{
182	/* Marathon CAN-bus-PCI card */
183	PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
184	PCI_ANY_ID, PCI_ANY_ID,
185	0, 0,
186	(kernel_ulong_t)&plx_pci_card_info_marathon
187	},
188	{
189	/* TEWS TECHNOLOGIES TPMC810 card */
190	TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
191	PCI_ANY_ID, PCI_ANY_ID,
192	0, 0,
193	(kernel_ulong_t)&plx_pci_card_info_tews
194	},
195	{ 0,}
196	};
197	MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
198
199	static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
200	{
201	return ioread8(priv->reg_base + port);
202	}
203
204	static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
205	{
206	iowrite8(val, priv->reg_base + port);
207	}
208
209	/*
210	* Check if a CAN controller is present at the specified location
211	* by trying to switch 'em from the Basic mode into the PeliCAN mode.
212	* Also check states of some registers in reset mode.
213	*/
214	static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
215	{
216	int flag = 0;
217
218	/*
219	* Check registers after hardware reset (the Basic mode)
220	* See states on p. 10 of the Datasheet.
221	*/
222	if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
223	REG_CR_BASICCAN_INITIAL &&
224	(priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
225	(priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
226	flag = 1;
227
228	/* Bring the SJA1000 into the PeliCAN mode*/
229	priv->write_reg(priv, REG_CDR, CDR_PELICAN);
230
231	/*
232	* Check registers after reset in the PeliCAN mode.
233	* See states on p. 23 of the Datasheet.
234	*/
235	if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
236	priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
237	priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
238	return flag;
239
240	return 0;
241	}
242
243	/*
244	* PLX90xx software reset
245	* Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
246	* For most cards it's enough for reset the SJA1000 chips.
247	*/
248	static void plx_pci_reset_common(struct pci_dev *pdev)
249	{
250	struct plx_pci_card *card = pci_get_drvdata(pdev);
251	u32 cntrl;
252
253	cntrl = ioread32(card->conf_addr + PLX_CNTRL);
254	cntrl \|= PLX_PCI_RESET;
255	iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
256	udelay(100);
257	cntrl ^= PLX_PCI_RESET;
258	iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
259	};
260
261	/* Special reset function for Marathon card */
262	static void plx_pci_reset_marathon(struct pci_dev *pdev)
263	{
264	void __iomem *reset_addr;
265	int i;
266	int reset_bar[2] = {3, 5};
267
268	plx_pci_reset_common(pdev);
269
270	for (i = 0; i < 2; i++) {
271	reset_addr = pci_iomap(pdev, reset_bar[i], 0);
272	if (!reset_addr) {
273	dev_err(&pdev->dev, "Failed to remap reset "
274	"space %d (BAR%d)\n", i, reset_bar[i]);
275	} else {
276	/* reset the SJA1000 chip */
277	iowrite8(0x1, reset_addr);
278	udelay(100);
279	pci_iounmap(pdev, reset_addr);
280	}
281	}
282	}
283
284	static void plx_pci_del_card(struct pci_dev *pdev)
285	{
286	struct plx_pci_card *card = pci_get_drvdata(pdev);
287	struct net_device *dev;
288	struct sja1000_priv *priv;
289	int i = 0;
290
291	for (i = 0; i < card->channels; i++) {
292	dev = card->net_dev[i];
293	if (!dev)
294	continue;
295
296	dev_info(&pdev->dev, "Removing %s\n", dev->name);
297	unregister_sja1000dev(dev);
298	priv = netdev_priv(dev);
299	if (priv->reg_base)
300	pci_iounmap(pdev, priv->reg_base);
301	free_sja1000dev(dev);
302	}
303
304	plx_pci_reset_common(pdev);
305
306	/*
307	* Disable interrupts from PCI-card (PLX90xx) and disable Local_1,
308	* Local_2 interrupts
309	*/
310	iowrite32(0x0, card->conf_addr + PLX_INTCSR);
311
312	if (card->conf_addr)
313	pci_iounmap(pdev, card->conf_addr);
314
315	kfree(card);
316
317	pci_disable_device(pdev);
318	pci_set_drvdata(pdev, NULL);
319	}
320
321	/*
322	* Probe PLX90xx based device for the SJA1000 chips and register each
323	* available CAN channel to SJA1000 Socket-CAN subsystem.
324	*/
325	static int __devinit plx_pci_add_card(struct pci_dev *pdev,
326	const struct pci_device_id *ent)
327	{
328	struct sja1000_priv *priv;
329	struct net_device *dev;
330	struct plx_pci_card *card;
331	struct plx_pci_card_info *ci;
332	int err, i;
333	u32 val;
334	void __iomem *addr;
335
336	ci = (struct plx_pci_card_info *)ent->driver_data;
337
338	if (pci_enable_device(pdev) < 0) {
339	dev_err(&pdev->dev, "Failed to enable PCI device\n");
340	return -ENODEV;
341	}
342
343	dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
344	ci->name, PCI_SLOT(pdev->devfn));
345
346	/* Allocate card structures to hold addresses, ... */
347	card = kzalloc(sizeof(*card), GFP_KERNEL);
348	if (!card) {
349	dev_err(&pdev->dev, "Unable to allocate memory\n");
350	pci_disable_device(pdev);
351	return -ENOMEM;
352	}
353
354	pci_set_drvdata(pdev, card);
355
356	card->channels = 0;
357
358	/* Remap PLX90xx configuration space */
359	addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
360	if (!addr) {
361	err = -ENOMEM;
362	dev_err(&pdev->dev, "Failed to remap configuration space "
363	"(BAR%d)\n", ci->conf_map.bar);
364	goto failure_cleanup;
365	}
366	card->conf_addr = addr + ci->conf_map.offset;
367
368	ci->reset_func(pdev);
369
370	/* Detect available channels */
371	for (i = 0; i < ci->channel_count; i++) {
372	struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
373
374	dev = alloc_sja1000dev(0);
375	if (!dev) {
376	err = -ENOMEM;
377	goto failure_cleanup;
378	}
379
380	card->net_dev[i] = dev;
381	priv = netdev_priv(dev);
382	priv->priv = card;
383	priv->irq_flags = IRQF_SHARED;
384
385	dev->irq = pdev->irq;
386
387	/*
388	* Remap IO space of the SJA1000 chips
389	* This is device-dependent mapping
390	*/
391	addr = pci_iomap(pdev, cm->bar, cm->size);
392	if (!addr) {
393	err = -ENOMEM;
394	dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
395	goto failure_cleanup;
396	}
397
398	priv->reg_base = addr + cm->offset;
399	priv->read_reg = plx_pci_read_reg;
400	priv->write_reg = plx_pci_write_reg;
401
402	/* Check if channel is present */
403	if (plx_pci_check_sja1000(priv)) {
404	priv->can.clock.freq = ci->can_clock;
405	priv->ocr = ci->ocr;
406	priv->cdr = ci->cdr;
407
408	SET_NETDEV_DEV(dev, &pdev->dev);
409
410	/* Register SJA1000 device */
411	err = register_sja1000dev(dev);
412	if (err) {
413	dev_err(&pdev->dev, "Registering device failed "
414	"(err=%d)\n", err);
415	free_sja1000dev(dev);
416	goto failure_cleanup;
417	}
418
419	card->channels++;
420
421	dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
422	"registered as %s\n", i + 1, priv->reg_base,
423	dev->irq, dev->name);
424	} else {
425	dev_err(&pdev->dev, "Channel #%d not detected\n",
426	i + 1);
427	free_sja1000dev(dev);
428	}
429	}
430
431	if (!card->channels) {
432	err = -ENODEV;
433	goto failure_cleanup;
434	}
435
436	/*
437	* Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
438	* Local_2 interrupts from the SJA1000 chips
439	*/
440	val = ioread32(card->conf_addr + PLX_INTCSR);
441	val \|= PLX_LINT1_EN \| PLX_LINT2_EN \| PLX_PCI_INT_EN;
442	iowrite32(val, card->conf_addr + PLX_INTCSR);
443
444	return 0;
445
446	failure_cleanup:
447	dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
448
449	plx_pci_del_card(pdev);
450
451	return err;
452	}
453
454	static struct pci_driver plx_pci_driver = {
455	.name = DRV_NAME,
456	.id_table = plx_pci_tbl,
457	.probe = plx_pci_add_card,
458	.remove = plx_pci_del_card,
459	};
460
461	static int __init plx_pci_init(void)
462	{
463	return pci_register_driver(&plx_pci_driver);
464	}
465
466	static void __exit plx_pci_exit(void)
467	{
468	pci_unregister_driver(&plx_pci_driver);
469	}
470
471	module_init(plx_pci_init);
472	module_exit(plx_pci_exit);