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24c4a3b2 PC |
1 | /* |
2 | * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> | |
3 | * | |
4 | * Derived from the ems_pci.c driver: | |
5 | * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> | |
6 | * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> | |
7 | * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the version 2 of the GNU General Public License | |
11 | * as published by the Free Software Foundation | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
05780d98 | 19 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
24c4a3b2 PC |
20 | */ |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/delay.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
24c4a3b2 | 28 | #include <linux/pci.h> |
24c4a3b2 PC |
29 | #include <linux/can/dev.h> |
30 | #include <linux/io.h> | |
31 | ||
32 | #include "sja1000.h" | |
33 | ||
34 | #define DRV_NAME "sja1000_plx_pci" | |
35 | ||
36 | MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); | |
37 | MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " | |
38 | "the SJA1000 chips"); | |
39 | MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " | |
40 | "Adlink PCI-7841/cPCI-7841 SE, " | |
41 | "Marathon CAN-bus-PCI, " | |
82e38177 MF |
42 | "TEWS TECHNOLOGIES TPMC810, " |
43 | "esd CAN-PCI/CPCI/PCI104/200, " | |
44 | "esd CAN-PCI/PMC/266, " | |
e08534b5 | 45 | "esd CAN-PCIe/2000, " |
e4bc6c06 | 46 | "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), " |
2dcb90ef OM |
47 | "IXXAT PC-I 04/PCI, " |
48 | "ELCUS CAN-200-PCI") | |
24c4a3b2 PC |
49 | MODULE_LICENSE("GPL v2"); |
50 | ||
51 | #define PLX_PCI_MAX_CHAN 2 | |
52 | ||
53 | struct plx_pci_card { | |
54 | int channels; /* detected channels count */ | |
55 | struct net_device *net_dev[PLX_PCI_MAX_CHAN]; | |
56 | void __iomem *conf_addr; | |
82e38177 MF |
57 | |
58 | /* Pointer to device-dependent reset function */ | |
59 | void (*reset_func)(struct pci_dev *pdev); | |
24c4a3b2 PC |
60 | }; |
61 | ||
62 | #define PLX_PCI_CAN_CLOCK (16000000 / 2) | |
63 | ||
82e38177 | 64 | /* PLX9030/9050/9052 registers */ |
24c4a3b2 PC |
65 | #define PLX_INTCSR 0x4c /* Interrupt Control/Status */ |
66 | #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, | |
67 | * Serial EEPROM, and Initialization | |
68 | * Control register | |
69 | */ | |
70 | ||
71 | #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ | |
72 | #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ | |
73 | #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ | |
74 | #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ | |
75 | ||
82e38177 MF |
76 | /* PLX9056 registers */ |
77 | #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ | |
78 | #define PLX9056_CNTRL 0x6c /* Control / Software Reset */ | |
79 | ||
80 | #define PLX9056_LINTI (1 << 11) | |
81 | #define PLX9056_PCI_INT_EN (1 << 8) | |
82 | #define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ | |
83 | ||
24c4a3b2 PC |
84 | /* |
85 | * The board configuration is probably following: | |
86 | * RX1 is connected to ground. | |
87 | * TX1 is not connected. | |
88 | * CLKO is not connected. | |
89 | * Setting the OCR register to 0xDA is a good idea. | |
90 | * This means normal output mode, push-pull and the correct polarity. | |
91 | */ | |
92 | #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) | |
93 | ||
94 | /* | |
95 | * In the CDR register, you should set CBP to 1. | |
96 | * You will probably also want to set the clock divider value to 7 | |
97 | * (meaning direct oscillator output) because the second SJA1000 chip | |
98 | * is driven by the first one CLKOUT output. | |
99 | */ | |
100 | #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) | |
101 | ||
102 | /* SJA1000 Control Register in the BasicCAN Mode */ | |
103 | #define REG_CR 0x00 | |
104 | ||
105 | /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ | |
106 | #define REG_CR_BASICCAN_INITIAL 0x21 | |
107 | #define REG_CR_BASICCAN_INITIAL_MASK 0xa1 | |
108 | #define REG_SR_BASICCAN_INITIAL 0x0c | |
109 | #define REG_IR_BASICCAN_INITIAL 0xe0 | |
110 | ||
111 | /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ | |
112 | #define REG_MOD_PELICAN_INITIAL 0x01 | |
113 | #define REG_SR_PELICAN_INITIAL 0x3c | |
114 | #define REG_IR_PELICAN_INITIAL 0x00 | |
115 | ||
116 | #define ADLINK_PCI_VENDOR_ID 0x144A | |
117 | #define ADLINK_PCI_DEVICE_ID 0x7841 | |
118 | ||
82e38177 MF |
119 | #define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 |
120 | #define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 | |
121 | #define ESD_PCI_SUB_SYS_ID_PMC266 0x000e | |
122 | #define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b | |
123 | #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 | |
124 | #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 | |
125 | ||
2dcb90ef OM |
126 | #define CAN200PCI_DEVICE_ID 0x9030 |
127 | #define CAN200PCI_VENDOR_ID 0x10b5 | |
128 | #define CAN200PCI_SUB_DEVICE_ID 0x0301 | |
129 | #define CAN200PCI_SUB_VENDOR_ID 0xe1c5 | |
130 | ||
e08534b5 JK |
131 | #define IXXAT_PCI_VENDOR_ID 0x10b5 |
132 | #define IXXAT_PCI_DEVICE_ID 0x9050 | |
133 | #define IXXAT_PCI_SUB_SYS_ID 0x2540 | |
134 | ||
24c4a3b2 PC |
135 | #define MARATHON_PCI_DEVICE_ID 0x2715 |
136 | ||
137 | #define TEWS_PCI_VENDOR_ID 0x1498 | |
138 | #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A | |
139 | ||
e4bc6c06 MG |
140 | #define CTI_PCI_VENDOR_ID 0x12c4 |
141 | #define CTI_PCI_DEVICE_ID_CRG001 0x0900 | |
142 | ||
24c4a3b2 PC |
143 | static void plx_pci_reset_common(struct pci_dev *pdev); |
144 | static void plx_pci_reset_marathon(struct pci_dev *pdev); | |
82e38177 | 145 | static void plx9056_pci_reset_common(struct pci_dev *pdev); |
24c4a3b2 PC |
146 | |
147 | struct plx_pci_channel_map { | |
148 | u32 bar; | |
149 | u32 offset; | |
150 | u32 size; /* 0x00 - auto, e.g. length of entire bar */ | |
151 | }; | |
152 | ||
153 | struct plx_pci_card_info { | |
154 | const char *name; | |
155 | int channel_count; | |
156 | u32 can_clock; | |
157 | u8 ocr; /* output control register */ | |
158 | u8 cdr; /* clock divider register */ | |
159 | ||
160 | /* Parameters for mapping local configuration space */ | |
161 | struct plx_pci_channel_map conf_map; | |
162 | ||
163 | /* Parameters for mapping the SJA1000 chips */ | |
164 | struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; | |
165 | ||
166 | /* Pointer to device-dependent reset function */ | |
167 | void (*reset_func)(struct pci_dev *pdev); | |
168 | }; | |
169 | ||
3c8ac0f2 | 170 | static struct plx_pci_card_info plx_pci_card_info_adlink = { |
24c4a3b2 PC |
171 | "Adlink PCI-7841/cPCI-7841", 2, |
172 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
173 | {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, | |
174 | &plx_pci_reset_common | |
175 | /* based on PLX9052 */ | |
176 | }; | |
177 | ||
3c8ac0f2 | 178 | static struct plx_pci_card_info plx_pci_card_info_adlink_se = { |
24c4a3b2 PC |
179 | "Adlink PCI-7841/cPCI-7841 SE", 2, |
180 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
181 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, | |
182 | &plx_pci_reset_common | |
183 | /* based on PLX9052 */ | |
184 | }; | |
185 | ||
3c8ac0f2 | 186 | static struct plx_pci_card_info plx_pci_card_info_esd200 = { |
82e38177 MF |
187 | "esd CAN-PCI/CPCI/PCI104/200", 2, |
188 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
189 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, | |
190 | &plx_pci_reset_common | |
191 | /* based on PLX9030/9050 */ | |
192 | }; | |
193 | ||
3c8ac0f2 | 194 | static struct plx_pci_card_info plx_pci_card_info_esd266 = { |
82e38177 MF |
195 | "esd CAN-PCI/PMC/266", 2, |
196 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
197 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, | |
198 | &plx9056_pci_reset_common | |
199 | /* based on PLX9056 */ | |
200 | }; | |
201 | ||
3c8ac0f2 | 202 | static struct plx_pci_card_info plx_pci_card_info_esd2000 = { |
82e38177 MF |
203 | "esd CAN-PCIe/2000", 2, |
204 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
205 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, | |
206 | &plx9056_pci_reset_common | |
207 | /* based on PEX8311 */ | |
208 | }; | |
209 | ||
3c8ac0f2 | 210 | static struct plx_pci_card_info plx_pci_card_info_ixxat = { |
e08534b5 JK |
211 | "IXXAT PC-I 04/PCI", 2, |
212 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
213 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} }, | |
214 | &plx_pci_reset_common | |
215 | /* based on PLX9050 */ | |
216 | }; | |
217 | ||
3c8ac0f2 | 218 | static struct plx_pci_card_info plx_pci_card_info_marathon = { |
24c4a3b2 PC |
219 | "Marathon CAN-bus-PCI", 2, |
220 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
221 | {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, | |
222 | &plx_pci_reset_marathon | |
223 | /* based on PLX9052 */ | |
224 | }; | |
225 | ||
3c8ac0f2 | 226 | static struct plx_pci_card_info plx_pci_card_info_tews = { |
24c4a3b2 PC |
227 | "TEWS TECHNOLOGIES TPMC810", 2, |
228 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
229 | {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, | |
230 | &plx_pci_reset_common | |
231 | /* based on PLX9030 */ | |
232 | }; | |
233 | ||
3c8ac0f2 | 234 | static struct plx_pci_card_info plx_pci_card_info_cti = { |
e4bc6c06 MG |
235 | "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2, |
236 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
237 | {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, | |
238 | &plx_pci_reset_common | |
239 | /* based on PLX9030 */ | |
240 | }; | |
241 | ||
2dcb90ef OM |
242 | static struct plx_pci_card_info plx_pci_card_info_elcus = { |
243 | "Eclus CAN-200-PCI", 2, | |
244 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, | |
245 | {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} }, | |
246 | &plx_pci_reset_common | |
247 | /* based on PLX9030 */ | |
248 | }; | |
249 | ||
9baa3c34 | 250 | static const struct pci_device_id plx_pci_tbl[] = { |
24c4a3b2 PC |
251 | { |
252 | /* Adlink PCI-7841/cPCI-7841 */ | |
253 | ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, | |
254 | PCI_ANY_ID, PCI_ANY_ID, | |
255 | PCI_CLASS_NETWORK_OTHER << 8, ~0, | |
256 | (kernel_ulong_t)&plx_pci_card_info_adlink | |
257 | }, | |
258 | { | |
259 | /* Adlink PCI-7841/cPCI-7841 SE */ | |
260 | ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, | |
261 | PCI_ANY_ID, PCI_ANY_ID, | |
262 | PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, | |
263 | (kernel_ulong_t)&plx_pci_card_info_adlink_se | |
264 | }, | |
82e38177 MF |
265 | { |
266 | /* esd CAN-PCI/200 */ | |
267 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
268 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, | |
269 | 0, 0, | |
270 | (kernel_ulong_t)&plx_pci_card_info_esd200 | |
271 | }, | |
272 | { | |
273 | /* esd CAN-CPCI/200 */ | |
274 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | |
275 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, | |
276 | 0, 0, | |
277 | (kernel_ulong_t)&plx_pci_card_info_esd200 | |
278 | }, | |
279 | { | |
280 | /* esd CAN-PCI104/200 */ | |
281 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | |
282 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, | |
283 | 0, 0, | |
284 | (kernel_ulong_t)&plx_pci_card_info_esd200 | |
285 | }, | |
286 | { | |
287 | /* esd CAN-PCI/266 */ | |
288 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, | |
289 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, | |
290 | 0, 0, | |
291 | (kernel_ulong_t)&plx_pci_card_info_esd266 | |
292 | }, | |
293 | { | |
294 | /* esd CAN-PMC/266 */ | |
295 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, | |
296 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, | |
297 | 0, 0, | |
298 | (kernel_ulong_t)&plx_pci_card_info_esd266 | |
299 | }, | |
300 | { | |
301 | /* esd CAN-PCIE/2000 */ | |
302 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, | |
303 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, | |
304 | 0, 0, | |
305 | (kernel_ulong_t)&plx_pci_card_info_esd2000 | |
306 | }, | |
e08534b5 JK |
307 | { |
308 | /* IXXAT PC-I 04/PCI card */ | |
309 | IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID, | |
310 | PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID, | |
311 | 0, 0, | |
312 | (kernel_ulong_t)&plx_pci_card_info_ixxat | |
313 | }, | |
24c4a3b2 PC |
314 | { |
315 | /* Marathon CAN-bus-PCI card */ | |
316 | PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, | |
317 | PCI_ANY_ID, PCI_ANY_ID, | |
318 | 0, 0, | |
319 | (kernel_ulong_t)&plx_pci_card_info_marathon | |
320 | }, | |
321 | { | |
322 | /* TEWS TECHNOLOGIES TPMC810 card */ | |
323 | TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, | |
324 | PCI_ANY_ID, PCI_ANY_ID, | |
325 | 0, 0, | |
326 | (kernel_ulong_t)&plx_pci_card_info_tews | |
327 | }, | |
e4bc6c06 MG |
328 | { |
329 | /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */ | |
330 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | |
331 | CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001, | |
332 | 0, 0, | |
333 | (kernel_ulong_t)&plx_pci_card_info_cti | |
334 | }, | |
2dcb90ef OM |
335 | { |
336 | /* Elcus CAN-200-PCI */ | |
337 | CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID, | |
338 | CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID, | |
339 | 0, 0, | |
340 | (kernel_ulong_t)&plx_pci_card_info_elcus | |
341 | }, | |
24c4a3b2 PC |
342 | { 0,} |
343 | }; | |
344 | MODULE_DEVICE_TABLE(pci, plx_pci_tbl); | |
345 | ||
346 | static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) | |
347 | { | |
348 | return ioread8(priv->reg_base + port); | |
349 | } | |
350 | ||
351 | static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) | |
352 | { | |
353 | iowrite8(val, priv->reg_base + port); | |
354 | } | |
355 | ||
356 | /* | |
357 | * Check if a CAN controller is present at the specified location | |
358 | * by trying to switch 'em from the Basic mode into the PeliCAN mode. | |
359 | * Also check states of some registers in reset mode. | |
360 | */ | |
361 | static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) | |
362 | { | |
363 | int flag = 0; | |
364 | ||
365 | /* | |
366 | * Check registers after hardware reset (the Basic mode) | |
367 | * See states on p. 10 of the Datasheet. | |
368 | */ | |
369 | if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == | |
370 | REG_CR_BASICCAN_INITIAL && | |
06e1d1d7 OH |
371 | (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && |
372 | (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) | |
24c4a3b2 PC |
373 | flag = 1; |
374 | ||
375 | /* Bring the SJA1000 into the PeliCAN mode*/ | |
06e1d1d7 | 376 | priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); |
24c4a3b2 PC |
377 | |
378 | /* | |
379 | * Check registers after reset in the PeliCAN mode. | |
380 | * See states on p. 23 of the Datasheet. | |
381 | */ | |
06e1d1d7 OH |
382 | if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && |
383 | priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && | |
384 | priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) | |
24c4a3b2 PC |
385 | return flag; |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | /* | |
82e38177 | 391 | * PLX9030/50/52 software reset |
24c4a3b2 PC |
392 | * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). |
393 | * For most cards it's enough for reset the SJA1000 chips. | |
394 | */ | |
395 | static void plx_pci_reset_common(struct pci_dev *pdev) | |
396 | { | |
397 | struct plx_pci_card *card = pci_get_drvdata(pdev); | |
398 | u32 cntrl; | |
399 | ||
400 | cntrl = ioread32(card->conf_addr + PLX_CNTRL); | |
401 | cntrl |= PLX_PCI_RESET; | |
402 | iowrite32(cntrl, card->conf_addr + PLX_CNTRL); | |
403 | udelay(100); | |
404 | cntrl ^= PLX_PCI_RESET; | |
405 | iowrite32(cntrl, card->conf_addr + PLX_CNTRL); | |
406 | }; | |
407 | ||
82e38177 MF |
408 | /* |
409 | * PLX9056 software reset | |
410 | * Assert LRESET# and reset device(s) on the Local Bus (if wired). | |
411 | */ | |
412 | static void plx9056_pci_reset_common(struct pci_dev *pdev) | |
413 | { | |
414 | struct plx_pci_card *card = pci_get_drvdata(pdev); | |
415 | u32 cntrl; | |
416 | ||
417 | /* issue a local bus reset */ | |
418 | cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); | |
419 | cntrl |= PLX_PCI_RESET; | |
420 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); | |
421 | udelay(100); | |
422 | cntrl ^= PLX_PCI_RESET; | |
423 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); | |
424 | ||
425 | /* reload local configuration from EEPROM */ | |
426 | cntrl |= PLX9056_PCI_RCR; | |
427 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); | |
428 | ||
429 | /* | |
430 | * There is no safe way to poll for the end | |
431 | * of reconfiguration process. Waiting for 10ms | |
432 | * is safe. | |
433 | */ | |
434 | mdelay(10); | |
435 | ||
436 | cntrl ^= PLX9056_PCI_RCR; | |
437 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); | |
438 | }; | |
439 | ||
24c4a3b2 PC |
440 | /* Special reset function for Marathon card */ |
441 | static void plx_pci_reset_marathon(struct pci_dev *pdev) | |
442 | { | |
443 | void __iomem *reset_addr; | |
444 | int i; | |
215faf9c | 445 | static const int reset_bar[2] = {3, 5}; |
24c4a3b2 PC |
446 | |
447 | plx_pci_reset_common(pdev); | |
448 | ||
449 | for (i = 0; i < 2; i++) { | |
450 | reset_addr = pci_iomap(pdev, reset_bar[i], 0); | |
451 | if (!reset_addr) { | |
452 | dev_err(&pdev->dev, "Failed to remap reset " | |
453 | "space %d (BAR%d)\n", i, reset_bar[i]); | |
454 | } else { | |
455 | /* reset the SJA1000 chip */ | |
456 | iowrite8(0x1, reset_addr); | |
457 | udelay(100); | |
458 | pci_iounmap(pdev, reset_addr); | |
459 | } | |
460 | } | |
461 | } | |
462 | ||
463 | static void plx_pci_del_card(struct pci_dev *pdev) | |
464 | { | |
465 | struct plx_pci_card *card = pci_get_drvdata(pdev); | |
466 | struct net_device *dev; | |
467 | struct sja1000_priv *priv; | |
468 | int i = 0; | |
469 | ||
951f2f96 | 470 | for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { |
24c4a3b2 PC |
471 | dev = card->net_dev[i]; |
472 | if (!dev) | |
473 | continue; | |
474 | ||
475 | dev_info(&pdev->dev, "Removing %s\n", dev->name); | |
476 | unregister_sja1000dev(dev); | |
477 | priv = netdev_priv(dev); | |
478 | if (priv->reg_base) | |
479 | pci_iounmap(pdev, priv->reg_base); | |
480 | free_sja1000dev(dev); | |
481 | } | |
482 | ||
82e38177 | 483 | card->reset_func(pdev); |
24c4a3b2 PC |
484 | |
485 | /* | |
82e38177 MF |
486 | * Disable interrupts from PCI-card and disable local |
487 | * interrupts | |
24c4a3b2 | 488 | */ |
82e38177 MF |
489 | if (pdev->device != PCI_DEVICE_ID_PLX_9056) |
490 | iowrite32(0x0, card->conf_addr + PLX_INTCSR); | |
491 | else | |
492 | iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); | |
24c4a3b2 PC |
493 | |
494 | if (card->conf_addr) | |
495 | pci_iounmap(pdev, card->conf_addr); | |
496 | ||
497 | kfree(card); | |
498 | ||
499 | pci_disable_device(pdev); | |
24c4a3b2 PC |
500 | } |
501 | ||
502 | /* | |
503 | * Probe PLX90xx based device for the SJA1000 chips and register each | |
504 | * available CAN channel to SJA1000 Socket-CAN subsystem. | |
505 | */ | |
3c8ac0f2 | 506 | static int plx_pci_add_card(struct pci_dev *pdev, |
1dd06ae8 | 507 | const struct pci_device_id *ent) |
24c4a3b2 PC |
508 | { |
509 | struct sja1000_priv *priv; | |
510 | struct net_device *dev; | |
511 | struct plx_pci_card *card; | |
512 | struct plx_pci_card_info *ci; | |
513 | int err, i; | |
514 | u32 val; | |
515 | void __iomem *addr; | |
516 | ||
517 | ci = (struct plx_pci_card_info *)ent->driver_data; | |
518 | ||
519 | if (pci_enable_device(pdev) < 0) { | |
520 | dev_err(&pdev->dev, "Failed to enable PCI device\n"); | |
521 | return -ENODEV; | |
522 | } | |
523 | ||
524 | dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", | |
525 | ci->name, PCI_SLOT(pdev->devfn)); | |
526 | ||
527 | /* Allocate card structures to hold addresses, ... */ | |
528 | card = kzalloc(sizeof(*card), GFP_KERNEL); | |
529 | if (!card) { | |
24c4a3b2 PC |
530 | pci_disable_device(pdev); |
531 | return -ENOMEM; | |
532 | } | |
533 | ||
534 | pci_set_drvdata(pdev, card); | |
535 | ||
536 | card->channels = 0; | |
537 | ||
538 | /* Remap PLX90xx configuration space */ | |
539 | addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); | |
540 | if (!addr) { | |
541 | err = -ENOMEM; | |
542 | dev_err(&pdev->dev, "Failed to remap configuration space " | |
543 | "(BAR%d)\n", ci->conf_map.bar); | |
544 | goto failure_cleanup; | |
545 | } | |
546 | card->conf_addr = addr + ci->conf_map.offset; | |
547 | ||
548 | ci->reset_func(pdev); | |
82e38177 | 549 | card->reset_func = ci->reset_func; |
24c4a3b2 PC |
550 | |
551 | /* Detect available channels */ | |
552 | for (i = 0; i < ci->channel_count; i++) { | |
553 | struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; | |
554 | ||
555 | dev = alloc_sja1000dev(0); | |
556 | if (!dev) { | |
557 | err = -ENOMEM; | |
558 | goto failure_cleanup; | |
559 | } | |
560 | ||
561 | card->net_dev[i] = dev; | |
562 | priv = netdev_priv(dev); | |
563 | priv->priv = card; | |
564 | priv->irq_flags = IRQF_SHARED; | |
565 | ||
566 | dev->irq = pdev->irq; | |
567 | ||
568 | /* | |
569 | * Remap IO space of the SJA1000 chips | |
570 | * This is device-dependent mapping | |
571 | */ | |
572 | addr = pci_iomap(pdev, cm->bar, cm->size); | |
573 | if (!addr) { | |
574 | err = -ENOMEM; | |
575 | dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); | |
576 | goto failure_cleanup; | |
577 | } | |
578 | ||
579 | priv->reg_base = addr + cm->offset; | |
580 | priv->read_reg = plx_pci_read_reg; | |
581 | priv->write_reg = plx_pci_write_reg; | |
582 | ||
583 | /* Check if channel is present */ | |
584 | if (plx_pci_check_sja1000(priv)) { | |
585 | priv->can.clock.freq = ci->can_clock; | |
586 | priv->ocr = ci->ocr; | |
587 | priv->cdr = ci->cdr; | |
588 | ||
589 | SET_NETDEV_DEV(dev, &pdev->dev); | |
3e66d013 | 590 | dev->dev_id = i; |
24c4a3b2 PC |
591 | |
592 | /* Register SJA1000 device */ | |
593 | err = register_sja1000dev(dev); | |
594 | if (err) { | |
595 | dev_err(&pdev->dev, "Registering device failed " | |
596 | "(err=%d)\n", err); | |
24c4a3b2 PC |
597 | goto failure_cleanup; |
598 | } | |
599 | ||
600 | card->channels++; | |
601 | ||
602 | dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " | |
603 | "registered as %s\n", i + 1, priv->reg_base, | |
604 | dev->irq, dev->name); | |
605 | } else { | |
606 | dev_err(&pdev->dev, "Channel #%d not detected\n", | |
607 | i + 1); | |
608 | free_sja1000dev(dev); | |
951f2f96 | 609 | card->net_dev[i] = NULL; |
24c4a3b2 PC |
610 | } |
611 | } | |
612 | ||
613 | if (!card->channels) { | |
614 | err = -ENODEV; | |
615 | goto failure_cleanup; | |
616 | } | |
617 | ||
618 | /* | |
619 | * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, | |
620 | * Local_2 interrupts from the SJA1000 chips | |
621 | */ | |
82e38177 MF |
622 | if (pdev->device != PCI_DEVICE_ID_PLX_9056) { |
623 | val = ioread32(card->conf_addr + PLX_INTCSR); | |
624 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) | |
625 | val |= PLX_LINT1_EN | PLX_PCI_INT_EN; | |
626 | else | |
627 | val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; | |
628 | iowrite32(val, card->conf_addr + PLX_INTCSR); | |
629 | } else { | |
630 | iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, | |
631 | card->conf_addr + PLX9056_INTCSR); | |
632 | } | |
24c4a3b2 PC |
633 | return 0; |
634 | ||
635 | failure_cleanup: | |
636 | dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); | |
637 | ||
638 | plx_pci_del_card(pdev); | |
639 | ||
640 | return err; | |
641 | } | |
642 | ||
643 | static struct pci_driver plx_pci_driver = { | |
644 | .name = DRV_NAME, | |
645 | .id_table = plx_pci_tbl, | |
646 | .probe = plx_pci_add_card, | |
647 | .remove = plx_pci_del_card, | |
648 | }; | |
649 | ||
fb7944b3 | 650 | module_pci_driver(plx_pci_driver); |