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b1201e44 KA |
1 | /* Xilinx CAN device driver |
2 | * | |
3 | * Copyright (C) 2012 - 2014 Xilinx, Inc. | |
4 | * Copyright (C) 2009 PetaLogix. All rights reserved. | |
95efd400 | 5 | * Copyright (C) 2017 Sandvik Mining and Construction Oy |
b1201e44 KA |
6 | * |
7 | * Description: | |
8 | * This driver is developed for Axi CAN IP and for Zynq CANPS Controller. | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | */ | |
19 | ||
20 | #include <linux/clk.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/netdevice.h> | |
28 | #include <linux/of.h> | |
0e2078f5 | 29 | #include <linux/of_device.h> |
b1201e44 KA |
30 | #include <linux/platform_device.h> |
31 | #include <linux/skbuff.h> | |
0e2078f5 | 32 | #include <linux/spinlock.h> |
b1201e44 KA |
33 | #include <linux/string.h> |
34 | #include <linux/types.h> | |
35 | #include <linux/can/dev.h> | |
36 | #include <linux/can/error.h> | |
37 | #include <linux/can/led.h> | |
4716620d | 38 | #include <linux/pm_runtime.h> |
b1201e44 KA |
39 | |
40 | #define DRIVER_NAME "xilinx_can" | |
41 | ||
42 | /* CAN registers set */ | |
43 | enum xcan_reg { | |
44 | XCAN_SRR_OFFSET = 0x00, /* Software reset */ | |
45 | XCAN_MSR_OFFSET = 0x04, /* Mode select */ | |
46 | XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */ | |
47 | XCAN_BTR_OFFSET = 0x0C, /* Bit timing */ | |
48 | XCAN_ECR_OFFSET = 0x10, /* Error counter */ | |
49 | XCAN_ESR_OFFSET = 0x14, /* Error status */ | |
50 | XCAN_SR_OFFSET = 0x18, /* Status */ | |
51 | XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */ | |
52 | XCAN_IER_OFFSET = 0x20, /* Interrupt enable */ | |
53 | XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */ | |
54 | XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */ | |
55 | XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */ | |
56 | XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */ | |
57 | XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */ | |
58 | XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */ | |
59 | XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */ | |
60 | XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */ | |
61 | XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */ | |
62 | }; | |
63 | ||
64 | /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */ | |
65 | #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */ | |
66 | #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */ | |
67 | #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */ | |
68 | #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */ | |
69 | #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */ | |
70 | #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */ | |
71 | #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */ | |
72 | #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */ | |
73 | #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */ | |
74 | #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */ | |
75 | #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */ | |
76 | #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */ | |
77 | #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */ | |
78 | #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */ | |
79 | #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */ | |
80 | #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */ | |
81 | #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */ | |
82 | #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */ | |
83 | #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */ | |
84 | #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */ | |
85 | #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */ | |
86 | #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */ | |
87 | #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */ | |
88 | #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */ | |
89 | #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */ | |
90 | #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */ | |
91 | #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */ | |
92 | #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */ | |
93 | #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */ | |
94 | #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ | |
95 | #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ | |
96 | #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ | |
97 | #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ | |
98 | #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ | |
99 | #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ | |
100 | #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */ | |
101 | #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */ | |
102 | #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */ | |
103 | ||
104 | #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\ | |
105 | XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \ | |
106 | XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \ | |
59a9765e | 107 | XCAN_IXR_ARBLST_MASK) |
b1201e44 KA |
108 | |
109 | /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */ | |
110 | #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */ | |
111 | #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */ | |
112 | #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */ | |
113 | #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ | |
114 | #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */ | |
115 | #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */ | |
116 | ||
117 | /* CAN frame length constants */ | |
118 | #define XCAN_FRAME_MAX_DATA_LEN 8 | |
119 | #define XCAN_TIMEOUT (1 * HZ) | |
120 | ||
121 | /** | |
122 | * struct xcan_priv - This definition define CAN driver instance | |
123 | * @can: CAN private data structure. | |
0e2078f5 | 124 | * @tx_lock: Lock for synchronizing TX interrupt handling |
b1201e44 KA |
125 | * @tx_head: Tx CAN packets ready to send on the queue |
126 | * @tx_tail: Tx CAN packets successfully sended on the queue | |
127 | * @tx_max: Maximum number packets the driver can send | |
128 | * @napi: NAPI structure | |
129 | * @read_reg: For reading data from CAN registers | |
130 | * @write_reg: For writing data to CAN registers | |
131 | * @dev: Network device data structure | |
132 | * @reg_base: Ioremapped address to registers | |
133 | * @irq_flags: For request_irq() | |
134 | * @bus_clk: Pointer to struct clk | |
135 | * @can_clk: Pointer to struct clk | |
136 | */ | |
137 | struct xcan_priv { | |
138 | struct can_priv can; | |
0e2078f5 | 139 | spinlock_t tx_lock; |
b1201e44 KA |
140 | unsigned int tx_head; |
141 | unsigned int tx_tail; | |
142 | unsigned int tx_max; | |
143 | struct napi_struct napi; | |
144 | u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); | |
145 | void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, | |
146 | u32 val); | |
4716620d | 147 | struct device *dev; |
b1201e44 KA |
148 | void __iomem *reg_base; |
149 | unsigned long irq_flags; | |
150 | struct clk *bus_clk; | |
151 | struct clk *can_clk; | |
152 | }; | |
153 | ||
154 | /* CAN Bittiming constants as per Xilinx CAN specs */ | |
155 | static const struct can_bittiming_const xcan_bittiming_const = { | |
156 | .name = DRIVER_NAME, | |
157 | .tseg1_min = 1, | |
158 | .tseg1_max = 16, | |
159 | .tseg2_min = 1, | |
160 | .tseg2_max = 8, | |
161 | .sjw_max = 4, | |
162 | .brp_min = 1, | |
163 | .brp_max = 256, | |
164 | .brp_inc = 1, | |
165 | }; | |
166 | ||
0e2078f5 AH |
167 | #define XCAN_CAP_WATERMARK 0x0001 |
168 | struct xcan_devtype_data { | |
169 | unsigned int caps; | |
170 | }; | |
171 | ||
b1201e44 KA |
172 | /** |
173 | * xcan_write_reg_le - Write a value to the device register little endian | |
174 | * @priv: Driver private data structure | |
175 | * @reg: Register offset | |
176 | * @val: Value to write at the Register offset | |
177 | * | |
178 | * Write data to the paricular CAN register | |
179 | */ | |
180 | static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg, | |
181 | u32 val) | |
182 | { | |
183 | iowrite32(val, priv->reg_base + reg); | |
184 | } | |
185 | ||
186 | /** | |
187 | * xcan_read_reg_le - Read a value from the device register little endian | |
188 | * @priv: Driver private data structure | |
189 | * @reg: Register offset | |
190 | * | |
191 | * Read data from the particular CAN register | |
192 | * Return: value read from the CAN register | |
193 | */ | |
194 | static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg) | |
195 | { | |
196 | return ioread32(priv->reg_base + reg); | |
197 | } | |
198 | ||
199 | /** | |
200 | * xcan_write_reg_be - Write a value to the device register big endian | |
201 | * @priv: Driver private data structure | |
202 | * @reg: Register offset | |
203 | * @val: Value to write at the Register offset | |
204 | * | |
205 | * Write data to the paricular CAN register | |
206 | */ | |
207 | static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg, | |
208 | u32 val) | |
209 | { | |
210 | iowrite32be(val, priv->reg_base + reg); | |
211 | } | |
212 | ||
213 | /** | |
214 | * xcan_read_reg_be - Read a value from the device register big endian | |
215 | * @priv: Driver private data structure | |
216 | * @reg: Register offset | |
217 | * | |
218 | * Read data from the particular CAN register | |
219 | * Return: value read from the CAN register | |
220 | */ | |
221 | static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg) | |
222 | { | |
223 | return ioread32be(priv->reg_base + reg); | |
224 | } | |
225 | ||
226 | /** | |
227 | * set_reset_mode - Resets the CAN device mode | |
228 | * @ndev: Pointer to net_device structure | |
229 | * | |
230 | * This is the driver reset mode routine.The driver | |
231 | * enters into configuration mode. | |
232 | * | |
233 | * Return: 0 on success and failure value on error | |
234 | */ | |
235 | static int set_reset_mode(struct net_device *ndev) | |
236 | { | |
237 | struct xcan_priv *priv = netdev_priv(ndev); | |
238 | unsigned long timeout; | |
239 | ||
240 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); | |
241 | ||
242 | timeout = jiffies + XCAN_TIMEOUT; | |
243 | while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { | |
244 | if (time_after(jiffies, timeout)) { | |
245 | netdev_warn(ndev, "timed out for config mode\n"); | |
246 | return -ETIMEDOUT; | |
247 | } | |
248 | usleep_range(500, 10000); | |
249 | } | |
250 | ||
0e2078f5 AH |
251 | /* reset clears FIFOs */ |
252 | priv->tx_head = 0; | |
253 | priv->tx_tail = 0; | |
254 | ||
b1201e44 KA |
255 | return 0; |
256 | } | |
257 | ||
258 | /** | |
259 | * xcan_set_bittiming - CAN set bit timing routine | |
260 | * @ndev: Pointer to net_device structure | |
261 | * | |
262 | * This is the driver set bittiming routine. | |
263 | * Return: 0 on success and failure value on error | |
264 | */ | |
265 | static int xcan_set_bittiming(struct net_device *ndev) | |
266 | { | |
267 | struct xcan_priv *priv = netdev_priv(ndev); | |
268 | struct can_bittiming *bt = &priv->can.bittiming; | |
269 | u32 btr0, btr1; | |
270 | u32 is_config_mode; | |
271 | ||
272 | /* Check whether Xilinx CAN is in configuration mode. | |
273 | * It cannot set bit timing if Xilinx CAN is not in configuration mode. | |
274 | */ | |
275 | is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & | |
276 | XCAN_SR_CONFIG_MASK; | |
277 | if (!is_config_mode) { | |
278 | netdev_alert(ndev, | |
279 | "BUG! Cannot set bittiming - CAN is not in config mode\n"); | |
280 | return -EPERM; | |
281 | } | |
282 | ||
283 | /* Setting Baud Rate prescalar value in BRPR Register */ | |
284 | btr0 = (bt->brp - 1); | |
285 | ||
286 | /* Setting Time Segment 1 in BTR Register */ | |
287 | btr1 = (bt->prop_seg + bt->phase_seg1 - 1); | |
288 | ||
289 | /* Setting Time Segment 2 in BTR Register */ | |
290 | btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT; | |
291 | ||
292 | /* Setting Synchronous jump width in BTR Register */ | |
293 | btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT; | |
294 | ||
295 | priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); | |
296 | priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); | |
297 | ||
298 | netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n", | |
299 | priv->read_reg(priv, XCAN_BRPR_OFFSET), | |
300 | priv->read_reg(priv, XCAN_BTR_OFFSET)); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | /** | |
306 | * xcan_chip_start - This the drivers start routine | |
307 | * @ndev: Pointer to net_device structure | |
308 | * | |
309 | * This is the drivers start routine. | |
310 | * Based on the State of the CAN device it puts | |
311 | * the CAN device into a proper mode. | |
312 | * | |
313 | * Return: 0 on success and failure value on error | |
314 | */ | |
315 | static int xcan_chip_start(struct net_device *ndev) | |
316 | { | |
317 | struct xcan_priv *priv = netdev_priv(ndev); | |
fb3ec7ba SM |
318 | u32 reg_msr, reg_sr_mask; |
319 | int err; | |
b1201e44 KA |
320 | unsigned long timeout; |
321 | ||
322 | /* Check if it is in reset mode */ | |
323 | err = set_reset_mode(ndev); | |
324 | if (err < 0) | |
325 | return err; | |
326 | ||
327 | err = xcan_set_bittiming(ndev); | |
328 | if (err < 0) | |
329 | return err; | |
330 | ||
331 | /* Enable interrupts */ | |
332 | priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL); | |
333 | ||
334 | /* Check whether it is loopback mode or normal mode */ | |
335 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
336 | reg_msr = XCAN_MSR_LBACK_MASK; | |
337 | reg_sr_mask = XCAN_SR_LBACK_MASK; | |
338 | } else { | |
339 | reg_msr = 0x0; | |
340 | reg_sr_mask = XCAN_SR_NORMAL_MASK; | |
341 | } | |
342 | ||
343 | priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); | |
344 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); | |
345 | ||
346 | timeout = jiffies + XCAN_TIMEOUT; | |
347 | while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) { | |
348 | if (time_after(jiffies, timeout)) { | |
349 | netdev_warn(ndev, | |
350 | "timed out for correct mode\n"); | |
351 | return -ETIMEDOUT; | |
352 | } | |
353 | } | |
354 | netdev_dbg(ndev, "status:#x%08x\n", | |
355 | priv->read_reg(priv, XCAN_SR_OFFSET)); | |
356 | ||
357 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
358 | return 0; | |
359 | } | |
360 | ||
361 | /** | |
362 | * xcan_do_set_mode - This sets the mode of the driver | |
363 | * @ndev: Pointer to net_device structure | |
364 | * @mode: Tells the mode of the driver | |
365 | * | |
366 | * This check the drivers state and calls the | |
367 | * the corresponding modes to set. | |
368 | * | |
369 | * Return: 0 on success and failure value on error | |
370 | */ | |
371 | static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode) | |
372 | { | |
373 | int ret; | |
374 | ||
375 | switch (mode) { | |
376 | case CAN_MODE_START: | |
377 | ret = xcan_chip_start(ndev); | |
378 | if (ret < 0) { | |
379 | netdev_err(ndev, "xcan_chip_start failed!\n"); | |
380 | return ret; | |
381 | } | |
382 | netif_wake_queue(ndev); | |
383 | break; | |
384 | default: | |
385 | ret = -EOPNOTSUPP; | |
386 | break; | |
387 | } | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
392 | /** | |
393 | * xcan_start_xmit - Starts the transmission | |
394 | * @skb: sk_buff pointer that contains data to be Txed | |
395 | * @ndev: Pointer to net_device structure | |
396 | * | |
397 | * This function is invoked from upper layers to initiate transmission. This | |
398 | * function uses the next available free txbuff and populates their fields to | |
399 | * start the transmission. | |
400 | * | |
401 | * Return: 0 on success and failure value on error | |
402 | */ | |
403 | static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
404 | { | |
405 | struct xcan_priv *priv = netdev_priv(ndev); | |
406 | struct net_device_stats *stats = &ndev->stats; | |
407 | struct can_frame *cf = (struct can_frame *)skb->data; | |
408 | u32 id, dlc, data[2] = {0, 0}; | |
0e2078f5 | 409 | unsigned long flags; |
b1201e44 KA |
410 | |
411 | if (can_dropped_invalid_skb(ndev, skb)) | |
412 | return NETDEV_TX_OK; | |
413 | ||
414 | /* Check if the TX buffer is full */ | |
415 | if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & | |
416 | XCAN_SR_TXFLL_MASK)) { | |
417 | netif_stop_queue(ndev); | |
418 | netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n"); | |
419 | return NETDEV_TX_BUSY; | |
420 | } | |
421 | ||
422 | /* Watch carefully on the bit sequence */ | |
423 | if (cf->can_id & CAN_EFF_FLAG) { | |
424 | /* Extended CAN ID format */ | |
425 | id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & | |
426 | XCAN_IDR_ID2_MASK; | |
427 | id |= (((cf->can_id & CAN_EFF_MASK) >> | |
428 | (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) << | |
429 | XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK; | |
430 | ||
431 | /* The substibute remote TX request bit should be "1" | |
432 | * for extended frames as in the Xilinx CAN datasheet | |
433 | */ | |
434 | id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK; | |
435 | ||
436 | if (cf->can_id & CAN_RTR_FLAG) | |
437 | /* Extended frames remote TX request */ | |
438 | id |= XCAN_IDR_RTR_MASK; | |
439 | } else { | |
440 | /* Standard CAN ID format */ | |
441 | id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & | |
442 | XCAN_IDR_ID1_MASK; | |
443 | ||
444 | if (cf->can_id & CAN_RTR_FLAG) | |
445 | /* Standard frames remote TX request */ | |
446 | id |= XCAN_IDR_SRR_MASK; | |
447 | } | |
448 | ||
449 | dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT; | |
450 | ||
451 | if (cf->can_dlc > 0) | |
452 | data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); | |
453 | if (cf->can_dlc > 4) | |
454 | data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); | |
455 | ||
456 | can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max); | |
0e2078f5 AH |
457 | |
458 | spin_lock_irqsave(&priv->tx_lock, flags); | |
459 | ||
b1201e44 KA |
460 | priv->tx_head++; |
461 | ||
462 | /* Write the Frame to Xilinx CAN TX FIFO */ | |
463 | priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id); | |
464 | /* If the CAN frame is RTR frame this write triggers tranmission */ | |
465 | priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc); | |
466 | if (!(cf->can_id & CAN_RTR_FLAG)) { | |
467 | priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]); | |
468 | /* If the CAN frame is Standard/Extended frame this | |
469 | * write triggers tranmission | |
470 | */ | |
471 | priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]); | |
472 | stats->tx_bytes += cf->can_dlc; | |
473 | } | |
474 | ||
0e2078f5 AH |
475 | /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ |
476 | if (priv->tx_max > 1) | |
477 | priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); | |
478 | ||
b1201e44 KA |
479 | /* Check if the TX buffer is full */ |
480 | if ((priv->tx_head - priv->tx_tail) == priv->tx_max) | |
481 | netif_stop_queue(ndev); | |
482 | ||
0e2078f5 AH |
483 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
484 | ||
b1201e44 KA |
485 | return NETDEV_TX_OK; |
486 | } | |
487 | ||
488 | /** | |
489 | * xcan_rx - Is called from CAN isr to complete the received | |
490 | * frame processing | |
491 | * @ndev: Pointer to net_device structure | |
492 | * | |
493 | * This function is invoked from the CAN isr(poll) to process the Rx frames. It | |
494 | * does minimal processing and invokes "netif_receive_skb" to complete further | |
495 | * processing. | |
496 | * Return: 1 on success and 0 on failure. | |
497 | */ | |
498 | static int xcan_rx(struct net_device *ndev) | |
499 | { | |
500 | struct xcan_priv *priv = netdev_priv(ndev); | |
501 | struct net_device_stats *stats = &ndev->stats; | |
502 | struct can_frame *cf; | |
503 | struct sk_buff *skb; | |
504 | u32 id_xcan, dlc, data[2] = {0, 0}; | |
505 | ||
506 | skb = alloc_can_skb(ndev, &cf); | |
507 | if (unlikely(!skb)) { | |
508 | stats->rx_dropped++; | |
509 | return 0; | |
510 | } | |
511 | ||
512 | /* Read a frame from Xilinx zynq CANPS */ | |
513 | id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET); | |
514 | dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >> | |
515 | XCAN_DLCR_DLC_SHIFT; | |
516 | ||
517 | /* Change Xilinx CAN data length format to socketCAN data format */ | |
518 | cf->can_dlc = get_can_dlc(dlc); | |
519 | ||
520 | /* Change Xilinx CAN ID format to socketCAN ID format */ | |
521 | if (id_xcan & XCAN_IDR_IDE_MASK) { | |
522 | /* The received frame is an Extended format frame */ | |
523 | cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; | |
524 | cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> | |
525 | XCAN_IDR_ID2_SHIFT; | |
526 | cf->can_id |= CAN_EFF_FLAG; | |
527 | if (id_xcan & XCAN_IDR_RTR_MASK) | |
528 | cf->can_id |= CAN_RTR_FLAG; | |
529 | } else { | |
530 | /* The received frame is a standard format frame */ | |
531 | cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> | |
532 | XCAN_IDR_ID1_SHIFT; | |
533 | if (id_xcan & XCAN_IDR_SRR_MASK) | |
534 | cf->can_id |= CAN_RTR_FLAG; | |
535 | } | |
536 | ||
5793affe JLP |
537 | /* DW1/DW2 must always be read to remove message from RXFIFO */ |
538 | data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET); | |
539 | data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET); | |
b1201e44 | 540 | |
5793affe | 541 | if (!(cf->can_id & CAN_RTR_FLAG)) { |
b1201e44 KA |
542 | /* Change Xilinx CAN data format to socketCAN data format */ |
543 | if (cf->can_dlc > 0) | |
544 | *(__be32 *)(cf->data) = cpu_to_be32(data[0]); | |
545 | if (cf->can_dlc > 4) | |
546 | *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); | |
547 | } | |
548 | ||
549 | stats->rx_bytes += cf->can_dlc; | |
550 | stats->rx_packets++; | |
551 | netif_receive_skb(skb); | |
552 | ||
553 | return 1; | |
554 | } | |
555 | ||
95efd400 AH |
556 | /** |
557 | * xcan_current_error_state - Get current error state from HW | |
558 | * @ndev: Pointer to net_device structure | |
559 | * | |
560 | * Checks the current CAN error state from the HW. Note that this | |
561 | * only checks for ERROR_PASSIVE and ERROR_WARNING. | |
562 | * | |
563 | * Return: | |
564 | * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE | |
565 | * otherwise. | |
566 | */ | |
567 | static enum can_state xcan_current_error_state(struct net_device *ndev) | |
568 | { | |
569 | struct xcan_priv *priv = netdev_priv(ndev); | |
570 | u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); | |
571 | ||
572 | if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) | |
573 | return CAN_STATE_ERROR_PASSIVE; | |
574 | else if (status & XCAN_SR_ERRWRN_MASK) | |
575 | return CAN_STATE_ERROR_WARNING; | |
576 | else | |
577 | return CAN_STATE_ERROR_ACTIVE; | |
578 | } | |
579 | ||
580 | /** | |
581 | * xcan_set_error_state - Set new CAN error state | |
582 | * @ndev: Pointer to net_device structure | |
583 | * @new_state: The new CAN state to be set | |
584 | * @cf: Error frame to be populated or NULL | |
585 | * | |
586 | * Set new CAN error state for the device, updating statistics and | |
587 | * populating the error frame if given. | |
588 | */ | |
589 | static void xcan_set_error_state(struct net_device *ndev, | |
590 | enum can_state new_state, | |
591 | struct can_frame *cf) | |
592 | { | |
593 | struct xcan_priv *priv = netdev_priv(ndev); | |
594 | u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); | |
595 | u32 txerr = ecr & XCAN_ECR_TEC_MASK; | |
596 | u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT; | |
597 | ||
598 | priv->can.state = new_state; | |
599 | ||
600 | if (cf) { | |
601 | cf->can_id |= CAN_ERR_CRTL; | |
602 | cf->data[6] = txerr; | |
603 | cf->data[7] = rxerr; | |
604 | } | |
605 | ||
606 | switch (new_state) { | |
607 | case CAN_STATE_ERROR_PASSIVE: | |
608 | priv->can.can_stats.error_passive++; | |
609 | if (cf) | |
610 | cf->data[1] = (rxerr > 127) ? | |
611 | CAN_ERR_CRTL_RX_PASSIVE : | |
612 | CAN_ERR_CRTL_TX_PASSIVE; | |
613 | break; | |
614 | case CAN_STATE_ERROR_WARNING: | |
615 | priv->can.can_stats.error_warning++; | |
616 | if (cf) | |
617 | cf->data[1] |= (txerr > rxerr) ? | |
618 | CAN_ERR_CRTL_TX_WARNING : | |
619 | CAN_ERR_CRTL_RX_WARNING; | |
620 | break; | |
621 | case CAN_STATE_ERROR_ACTIVE: | |
622 | if (cf) | |
623 | cf->data[1] |= CAN_ERR_CRTL_ACTIVE; | |
624 | break; | |
625 | default: | |
626 | /* non-ERROR states are handled elsewhere */ | |
627 | WARN_ON(1); | |
628 | break; | |
629 | } | |
630 | } | |
631 | ||
632 | /** | |
633 | * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX | |
634 | * @ndev: Pointer to net_device structure | |
635 | * | |
636 | * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if | |
637 | * the performed RX/TX has caused it to drop to a lesser state and set | |
638 | * the interface state accordingly. | |
639 | */ | |
640 | static void xcan_update_error_state_after_rxtx(struct net_device *ndev) | |
641 | { | |
642 | struct xcan_priv *priv = netdev_priv(ndev); | |
643 | enum can_state old_state = priv->can.state; | |
644 | enum can_state new_state; | |
645 | ||
646 | /* changing error state due to successful frame RX/TX can only | |
647 | * occur from these states | |
648 | */ | |
649 | if (old_state != CAN_STATE_ERROR_WARNING && | |
650 | old_state != CAN_STATE_ERROR_PASSIVE) | |
651 | return; | |
652 | ||
653 | new_state = xcan_current_error_state(ndev); | |
654 | ||
655 | if (new_state != old_state) { | |
656 | struct sk_buff *skb; | |
657 | struct can_frame *cf; | |
658 | ||
659 | skb = alloc_can_err_skb(ndev, &cf); | |
660 | ||
661 | xcan_set_error_state(ndev, new_state, skb ? cf : NULL); | |
662 | ||
663 | if (skb) { | |
664 | struct net_device_stats *stats = &ndev->stats; | |
665 | ||
666 | stats->rx_packets++; | |
667 | stats->rx_bytes += cf->can_dlc; | |
668 | netif_rx(skb); | |
669 | } | |
670 | } | |
671 | } | |
672 | ||
b1201e44 KA |
673 | /** |
674 | * xcan_err_interrupt - error frame Isr | |
675 | * @ndev: net_device pointer | |
676 | * @isr: interrupt status register value | |
677 | * | |
678 | * This is the CAN error interrupt and it will | |
679 | * check the the type of error and forward the error | |
680 | * frame to upper layers. | |
681 | */ | |
682 | static void xcan_err_interrupt(struct net_device *ndev, u32 isr) | |
683 | { | |
684 | struct xcan_priv *priv = netdev_priv(ndev); | |
685 | struct net_device_stats *stats = &ndev->stats; | |
686 | struct can_frame *cf; | |
687 | struct sk_buff *skb; | |
95efd400 | 688 | u32 err_status; |
b1201e44 KA |
689 | |
690 | skb = alloc_can_err_skb(ndev, &cf); | |
691 | ||
692 | err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); | |
693 | priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); | |
b1201e44 KA |
694 | |
695 | if (isr & XCAN_IXR_BSOFF_MASK) { | |
696 | priv->can.state = CAN_STATE_BUS_OFF; | |
697 | priv->can.can_stats.bus_off++; | |
698 | /* Leave device in Config Mode in bus-off state */ | |
699 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); | |
700 | can_bus_off(ndev); | |
701 | if (skb) | |
702 | cf->can_id |= CAN_ERR_BUSOFF; | |
95efd400 AH |
703 | } else { |
704 | enum can_state new_state = xcan_current_error_state(ndev); | |
705 | ||
706 | xcan_set_error_state(ndev, new_state, skb ? cf : NULL); | |
b1201e44 KA |
707 | } |
708 | ||
709 | /* Check for Arbitration lost interrupt */ | |
710 | if (isr & XCAN_IXR_ARBLST_MASK) { | |
711 | priv->can.can_stats.arbitration_lost++; | |
712 | if (skb) { | |
713 | cf->can_id |= CAN_ERR_LOSTARB; | |
714 | cf->data[0] = CAN_ERR_LOSTARB_UNSPEC; | |
715 | } | |
716 | } | |
717 | ||
718 | /* Check for RX FIFO Overflow interrupt */ | |
719 | if (isr & XCAN_IXR_RXOFLW_MASK) { | |
720 | stats->rx_over_errors++; | |
721 | stats->rx_errors++; | |
b1201e44 KA |
722 | if (skb) { |
723 | cf->can_id |= CAN_ERR_CRTL; | |
724 | cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; | |
725 | } | |
726 | } | |
727 | ||
728 | /* Check for error interrupt */ | |
729 | if (isr & XCAN_IXR_ERROR_MASK) { | |
a2ec19f8 | 730 | if (skb) |
b1201e44 | 731 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; |
b1201e44 KA |
732 | |
733 | /* Check for Ack error interrupt */ | |
734 | if (err_status & XCAN_ESR_ACKER_MASK) { | |
735 | stats->tx_errors++; | |
736 | if (skb) { | |
737 | cf->can_id |= CAN_ERR_ACK; | |
ffd461f8 | 738 | cf->data[3] = CAN_ERR_PROT_LOC_ACK; |
b1201e44 KA |
739 | } |
740 | } | |
741 | ||
742 | /* Check for Bit error interrupt */ | |
743 | if (err_status & XCAN_ESR_BERR_MASK) { | |
744 | stats->tx_errors++; | |
745 | if (skb) { | |
746 | cf->can_id |= CAN_ERR_PROT; | |
747 | cf->data[2] = CAN_ERR_PROT_BIT; | |
748 | } | |
749 | } | |
750 | ||
751 | /* Check for Stuff error interrupt */ | |
752 | if (err_status & XCAN_ESR_STER_MASK) { | |
753 | stats->rx_errors++; | |
754 | if (skb) { | |
755 | cf->can_id |= CAN_ERR_PROT; | |
756 | cf->data[2] = CAN_ERR_PROT_STUFF; | |
757 | } | |
758 | } | |
759 | ||
760 | /* Check for Form error interrupt */ | |
761 | if (err_status & XCAN_ESR_FMER_MASK) { | |
762 | stats->rx_errors++; | |
763 | if (skb) { | |
764 | cf->can_id |= CAN_ERR_PROT; | |
765 | cf->data[2] = CAN_ERR_PROT_FORM; | |
766 | } | |
767 | } | |
768 | ||
769 | /* Check for CRC error interrupt */ | |
770 | if (err_status & XCAN_ESR_CRCER_MASK) { | |
771 | stats->rx_errors++; | |
772 | if (skb) { | |
773 | cf->can_id |= CAN_ERR_PROT; | |
ffd461f8 | 774 | cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; |
b1201e44 KA |
775 | } |
776 | } | |
777 | priv->can.can_stats.bus_error++; | |
778 | } | |
779 | ||
780 | if (skb) { | |
781 | stats->rx_packets++; | |
782 | stats->rx_bytes += cf->can_dlc; | |
783 | netif_rx(skb); | |
784 | } | |
785 | ||
786 | netdev_dbg(ndev, "%s: error status register:0x%x\n", | |
787 | __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); | |
788 | } | |
789 | ||
790 | /** | |
791 | * xcan_state_interrupt - It will check the state of the CAN device | |
792 | * @ndev: net_device pointer | |
793 | * @isr: interrupt status register value | |
794 | * | |
795 | * This will checks the state of the CAN device | |
796 | * and puts the device into appropriate state. | |
797 | */ | |
798 | static void xcan_state_interrupt(struct net_device *ndev, u32 isr) | |
799 | { | |
800 | struct xcan_priv *priv = netdev_priv(ndev); | |
801 | ||
802 | /* Check for Sleep interrupt if set put CAN device in sleep state */ | |
803 | if (isr & XCAN_IXR_SLP_MASK) | |
804 | priv->can.state = CAN_STATE_SLEEPING; | |
805 | ||
806 | /* Check for Wake up interrupt if set put CAN device in Active state */ | |
807 | if (isr & XCAN_IXR_WKUP_MASK) | |
808 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
809 | } | |
810 | ||
811 | /** | |
812 | * xcan_rx_poll - Poll routine for rx packets (NAPI) | |
813 | * @napi: napi structure pointer | |
814 | * @quota: Max number of rx packets to be processed. | |
815 | * | |
816 | * This is the poll routine for rx part. | |
817 | * It will process the packets maximux quota value. | |
818 | * | |
819 | * Return: number of packets received | |
820 | */ | |
821 | static int xcan_rx_poll(struct napi_struct *napi, int quota) | |
822 | { | |
823 | struct net_device *ndev = napi->dev; | |
824 | struct xcan_priv *priv = netdev_priv(ndev); | |
825 | u32 isr, ier; | |
826 | int work_done = 0; | |
827 | ||
828 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); | |
829 | while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) { | |
59a9765e | 830 | work_done += xcan_rx(ndev); |
b1201e44 KA |
831 | priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK); |
832 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); | |
833 | } | |
834 | ||
95efd400 | 835 | if (work_done) { |
b1201e44 | 836 | can_led_event(ndev, CAN_LED_EVENT_RX); |
95efd400 AH |
837 | xcan_update_error_state_after_rxtx(ndev); |
838 | } | |
b1201e44 KA |
839 | |
840 | if (work_done < quota) { | |
6ad20165 | 841 | napi_complete_done(napi, work_done); |
b1201e44 | 842 | ier = priv->read_reg(priv, XCAN_IER_OFFSET); |
59a9765e | 843 | ier |= XCAN_IXR_RXNEMP_MASK; |
b1201e44 KA |
844 | priv->write_reg(priv, XCAN_IER_OFFSET, ier); |
845 | } | |
846 | return work_done; | |
847 | } | |
848 | ||
849 | /** | |
850 | * xcan_tx_interrupt - Tx Done Isr | |
851 | * @ndev: net_device pointer | |
852 | * @isr: Interrupt status register value | |
853 | */ | |
854 | static void xcan_tx_interrupt(struct net_device *ndev, u32 isr) | |
855 | { | |
856 | struct xcan_priv *priv = netdev_priv(ndev); | |
857 | struct net_device_stats *stats = &ndev->stats; | |
0e2078f5 AH |
858 | unsigned int frames_in_fifo; |
859 | int frames_sent = 1; /* TXOK => at least 1 frame was sent */ | |
860 | unsigned long flags; | |
861 | int retries = 0; | |
862 | ||
863 | /* Synchronize with xmit as we need to know the exact number | |
864 | * of frames in the FIFO to stay in sync due to the TXFEMP | |
865 | * handling. | |
866 | * This also prevents a race between netif_wake_queue() and | |
867 | * netif_stop_queue(). | |
868 | */ | |
869 | spin_lock_irqsave(&priv->tx_lock, flags); | |
870 | ||
871 | frames_in_fifo = priv->tx_head - priv->tx_tail; | |
b1201e44 | 872 | |
0e2078f5 AH |
873 | if (WARN_ON_ONCE(frames_in_fifo == 0)) { |
874 | /* clear TXOK anyway to avoid getting back here */ | |
b1201e44 | 875 | priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); |
0e2078f5 AH |
876 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
877 | return; | |
878 | } | |
879 | ||
880 | /* Check if 2 frames were sent (TXOK only means that at least 1 | |
881 | * frame was sent). | |
882 | */ | |
883 | if (frames_in_fifo > 1) { | |
884 | WARN_ON(frames_in_fifo > priv->tx_max); | |
885 | ||
886 | /* Synchronize TXOK and isr so that after the loop: | |
887 | * (1) isr variable is up-to-date at least up to TXOK clear | |
888 | * time. This avoids us clearing a TXOK of a second frame | |
889 | * but not noticing that the FIFO is now empty and thus | |
890 | * marking only a single frame as sent. | |
891 | * (2) No TXOK is left. Having one could mean leaving a | |
892 | * stray TXOK as we might process the associated frame | |
893 | * via TXFEMP handling as we read TXFEMP *after* TXOK | |
894 | * clear to satisfy (1). | |
895 | */ | |
896 | while ((isr & XCAN_IXR_TXOK_MASK) && !WARN_ON(++retries == 100)) { | |
897 | priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); | |
898 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); | |
899 | } | |
900 | ||
901 | if (isr & XCAN_IXR_TXFEMP_MASK) { | |
902 | /* nothing in FIFO anymore */ | |
903 | frames_sent = frames_in_fifo; | |
904 | } | |
905 | } else { | |
906 | /* single frame in fifo, just clear TXOK */ | |
907 | priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); | |
908 | } | |
909 | ||
910 | while (frames_sent--) { | |
b1201e44 KA |
911 | can_get_echo_skb(ndev, priv->tx_tail % |
912 | priv->tx_max); | |
913 | priv->tx_tail++; | |
914 | stats->tx_packets++; | |
b1201e44 | 915 | } |
0e2078f5 AH |
916 | |
917 | netif_wake_queue(ndev); | |
918 | ||
919 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
920 | ||
b1201e44 | 921 | can_led_event(ndev, CAN_LED_EVENT_TX); |
95efd400 | 922 | xcan_update_error_state_after_rxtx(ndev); |
b1201e44 KA |
923 | } |
924 | ||
925 | /** | |
926 | * xcan_interrupt - CAN Isr | |
927 | * @irq: irq number | |
928 | * @dev_id: device id poniter | |
929 | * | |
930 | * This is the xilinx CAN Isr. It checks for the type of interrupt | |
931 | * and invokes the corresponding ISR. | |
932 | * | |
933 | * Return: | |
934 | * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise | |
935 | */ | |
936 | static irqreturn_t xcan_interrupt(int irq, void *dev_id) | |
937 | { | |
938 | struct net_device *ndev = (struct net_device *)dev_id; | |
939 | struct xcan_priv *priv = netdev_priv(ndev); | |
940 | u32 isr, ier; | |
f8e54cf3 | 941 | u32 isr_errors; |
b1201e44 KA |
942 | |
943 | /* Get the interrupt status from Xilinx CAN */ | |
944 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); | |
945 | if (!isr) | |
946 | return IRQ_NONE; | |
947 | ||
948 | /* Check for the type of interrupt and Processing it */ | |
949 | if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) { | |
950 | priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | | |
951 | XCAN_IXR_WKUP_MASK)); | |
952 | xcan_state_interrupt(ndev, isr); | |
953 | } | |
954 | ||
955 | /* Check for Tx interrupt and Processing it */ | |
956 | if (isr & XCAN_IXR_TXOK_MASK) | |
957 | xcan_tx_interrupt(ndev, isr); | |
958 | ||
959 | /* Check for the type of error interrupt and Processing it */ | |
f8e54cf3 AH |
960 | isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | |
961 | XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK); | |
962 | if (isr_errors) { | |
963 | priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); | |
b1201e44 KA |
964 | xcan_err_interrupt(ndev, isr); |
965 | } | |
966 | ||
967 | /* Check for the type of receive interrupt and Processing it */ | |
59a9765e | 968 | if (isr & XCAN_IXR_RXNEMP_MASK) { |
b1201e44 | 969 | ier = priv->read_reg(priv, XCAN_IER_OFFSET); |
59a9765e | 970 | ier &= ~XCAN_IXR_RXNEMP_MASK; |
b1201e44 KA |
971 | priv->write_reg(priv, XCAN_IER_OFFSET, ier); |
972 | napi_schedule(&priv->napi); | |
973 | } | |
974 | return IRQ_HANDLED; | |
975 | } | |
976 | ||
977 | /** | |
978 | * xcan_chip_stop - Driver stop routine | |
979 | * @ndev: Pointer to net_device structure | |
980 | * | |
981 | * This is the drivers stop routine. It will disable the | |
982 | * interrupts and put the device into configuration mode. | |
983 | */ | |
984 | static void xcan_chip_stop(struct net_device *ndev) | |
985 | { | |
986 | struct xcan_priv *priv = netdev_priv(ndev); | |
b1201e44 KA |
987 | |
988 | /* Disable interrupts and leave the can in configuration mode */ | |
d7aaf591 | 989 | set_reset_mode(ndev); |
b1201e44 KA |
990 | priv->can.state = CAN_STATE_STOPPED; |
991 | } | |
992 | ||
993 | /** | |
994 | * xcan_open - Driver open routine | |
995 | * @ndev: Pointer to net_device structure | |
996 | * | |
997 | * This is the driver open routine. | |
998 | * Return: 0 on success and failure value on error | |
999 | */ | |
1000 | static int xcan_open(struct net_device *ndev) | |
1001 | { | |
1002 | struct xcan_priv *priv = netdev_priv(ndev); | |
1003 | int ret; | |
1004 | ||
4716620d KA |
1005 | ret = pm_runtime_get_sync(priv->dev); |
1006 | if (ret < 0) { | |
1007 | netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", | |
1008 | __func__, ret); | |
1009 | return ret; | |
1010 | } | |
1011 | ||
b1201e44 KA |
1012 | ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, |
1013 | ndev->name, ndev); | |
1014 | if (ret < 0) { | |
1015 | netdev_err(ndev, "irq allocation for CAN failed\n"); | |
1016 | goto err; | |
1017 | } | |
1018 | ||
b1201e44 KA |
1019 | /* Set chip into reset mode */ |
1020 | ret = set_reset_mode(ndev); | |
1021 | if (ret < 0) { | |
1022 | netdev_err(ndev, "mode resetting failed!\n"); | |
4716620d | 1023 | goto err_irq; |
b1201e44 KA |
1024 | } |
1025 | ||
1026 | /* Common open */ | |
1027 | ret = open_candev(ndev); | |
1028 | if (ret) | |
4716620d | 1029 | goto err_irq; |
b1201e44 KA |
1030 | |
1031 | ret = xcan_chip_start(ndev); | |
1032 | if (ret < 0) { | |
1033 | netdev_err(ndev, "xcan_chip_start failed!\n"); | |
1034 | goto err_candev; | |
1035 | } | |
1036 | ||
1037 | can_led_event(ndev, CAN_LED_EVENT_OPEN); | |
1038 | napi_enable(&priv->napi); | |
1039 | netif_start_queue(ndev); | |
1040 | ||
1041 | return 0; | |
1042 | ||
1043 | err_candev: | |
1044 | close_candev(ndev); | |
b1201e44 KA |
1045 | err_irq: |
1046 | free_irq(ndev->irq, ndev); | |
1047 | err: | |
4716620d KA |
1048 | pm_runtime_put(priv->dev); |
1049 | ||
b1201e44 KA |
1050 | return ret; |
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * xcan_close - Driver close routine | |
1055 | * @ndev: Pointer to net_device structure | |
1056 | * | |
1057 | * Return: 0 always | |
1058 | */ | |
1059 | static int xcan_close(struct net_device *ndev) | |
1060 | { | |
1061 | struct xcan_priv *priv = netdev_priv(ndev); | |
1062 | ||
1063 | netif_stop_queue(ndev); | |
1064 | napi_disable(&priv->napi); | |
1065 | xcan_chip_stop(ndev); | |
b1201e44 KA |
1066 | free_irq(ndev->irq, ndev); |
1067 | close_candev(ndev); | |
1068 | ||
1069 | can_led_event(ndev, CAN_LED_EVENT_STOP); | |
4716620d | 1070 | pm_runtime_put(priv->dev); |
b1201e44 KA |
1071 | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | /** | |
1076 | * xcan_get_berr_counter - error counter routine | |
1077 | * @ndev: Pointer to net_device structure | |
1078 | * @bec: Pointer to can_berr_counter structure | |
1079 | * | |
1080 | * This is the driver error counter routine. | |
1081 | * Return: 0 on success and failure value on error | |
1082 | */ | |
1083 | static int xcan_get_berr_counter(const struct net_device *ndev, | |
1084 | struct can_berr_counter *bec) | |
1085 | { | |
1086 | struct xcan_priv *priv = netdev_priv(ndev); | |
1087 | int ret; | |
1088 | ||
4716620d KA |
1089 | ret = pm_runtime_get_sync(priv->dev); |
1090 | if (ret < 0) { | |
1091 | netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", | |
1092 | __func__, ret); | |
1093 | return ret; | |
1094 | } | |
b1201e44 KA |
1095 | |
1096 | bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; | |
1097 | bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & | |
1098 | XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); | |
1099 | ||
4716620d | 1100 | pm_runtime_put(priv->dev); |
b1201e44 KA |
1101 | |
1102 | return 0; | |
b1201e44 KA |
1103 | } |
1104 | ||
1105 | ||
1106 | static const struct net_device_ops xcan_netdev_ops = { | |
1107 | .ndo_open = xcan_open, | |
1108 | .ndo_stop = xcan_close, | |
1109 | .ndo_start_xmit = xcan_start_xmit, | |
92593a03 | 1110 | .ndo_change_mtu = can_change_mtu, |
b1201e44 KA |
1111 | }; |
1112 | ||
1113 | /** | |
1114 | * xcan_suspend - Suspend method for the driver | |
4716620d | 1115 | * @dev: Address of the device structure |
b1201e44 KA |
1116 | * |
1117 | * Put the driver into low power mode. | |
4716620d | 1118 | * Return: 0 on success and failure value on error |
b1201e44 KA |
1119 | */ |
1120 | static int __maybe_unused xcan_suspend(struct device *dev) | |
1121 | { | |
d7aaf591 | 1122 | struct net_device *ndev = dev_get_drvdata(dev); |
4716620d | 1123 | |
d7aaf591 AH |
1124 | if (netif_running(ndev)) { |
1125 | netif_stop_queue(ndev); | |
1126 | netif_device_detach(ndev); | |
1127 | xcan_chip_stop(ndev); | |
1128 | } | |
1129 | ||
1130 | return pm_runtime_force_suspend(dev); | |
4716620d KA |
1131 | } |
1132 | ||
1133 | /** | |
1134 | * xcan_resume - Resume from suspend | |
1135 | * @dev: Address of the device structure | |
1136 | * | |
1137 | * Resume operation after suspend. | |
1138 | * Return: 0 on success and failure value on error | |
1139 | */ | |
1140 | static int __maybe_unused xcan_resume(struct device *dev) | |
1141 | { | |
d7aaf591 AH |
1142 | struct net_device *ndev = dev_get_drvdata(dev); |
1143 | int ret; | |
4716620d | 1144 | |
d7aaf591 AH |
1145 | ret = pm_runtime_force_resume(dev); |
1146 | if (ret) { | |
1147 | dev_err(dev, "pm_runtime_force_resume failed on resume\n"); | |
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | if (netif_running(ndev)) { | |
1152 | ret = xcan_chip_start(ndev); | |
1153 | if (ret) { | |
1154 | dev_err(dev, "xcan_chip_start failed on resume\n"); | |
1155 | return ret; | |
1156 | } | |
1157 | ||
1158 | netif_device_attach(ndev); | |
1159 | netif_start_queue(ndev); | |
1160 | } | |
4716620d | 1161 | |
d7aaf591 | 1162 | return 0; |
4716620d KA |
1163 | } |
1164 | ||
1165 | /** | |
1166 | * xcan_runtime_suspend - Runtime suspend method for the driver | |
1167 | * @dev: Address of the device structure | |
1168 | * | |
1169 | * Put the driver into low power mode. | |
1170 | * Return: 0 always | |
1171 | */ | |
1172 | static int __maybe_unused xcan_runtime_suspend(struct device *dev) | |
1173 | { | |
1174 | struct net_device *ndev = dev_get_drvdata(dev); | |
b1201e44 KA |
1175 | struct xcan_priv *priv = netdev_priv(ndev); |
1176 | ||
4716620d KA |
1177 | clk_disable_unprepare(priv->bus_clk); |
1178 | clk_disable_unprepare(priv->can_clk); | |
b1201e44 KA |
1179 | |
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | /** | |
4716620d KA |
1184 | * xcan_runtime_resume - Runtime resume from suspend |
1185 | * @dev: Address of the device structure | |
b1201e44 KA |
1186 | * |
1187 | * Resume operation after suspend. | |
1188 | * Return: 0 on success and failure value on error | |
1189 | */ | |
4716620d | 1190 | static int __maybe_unused xcan_runtime_resume(struct device *dev) |
b1201e44 | 1191 | { |
4716620d | 1192 | struct net_device *ndev = dev_get_drvdata(dev); |
b1201e44 KA |
1193 | struct xcan_priv *priv = netdev_priv(ndev); |
1194 | int ret; | |
1195 | ||
4716620d | 1196 | ret = clk_prepare_enable(priv->bus_clk); |
b1201e44 KA |
1197 | if (ret) { |
1198 | dev_err(dev, "Cannot enable clock.\n"); | |
1199 | return ret; | |
1200 | } | |
4716620d | 1201 | ret = clk_prepare_enable(priv->can_clk); |
b1201e44 KA |
1202 | if (ret) { |
1203 | dev_err(dev, "Cannot enable clock.\n"); | |
1204 | clk_disable_unprepare(priv->bus_clk); | |
1205 | return ret; | |
1206 | } | |
1207 | ||
b1201e44 KA |
1208 | return 0; |
1209 | } | |
1210 | ||
4716620d KA |
1211 | static const struct dev_pm_ops xcan_dev_pm_ops = { |
1212 | SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume) | |
1213 | SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL) | |
1214 | }; | |
b1201e44 | 1215 | |
0e2078f5 AH |
1216 | static const struct xcan_devtype_data xcan_zynq_data = { |
1217 | .caps = XCAN_CAP_WATERMARK, | |
1218 | }; | |
1219 | ||
1220 | /* Match table for OF platform binding */ | |
1221 | static const struct of_device_id xcan_of_match[] = { | |
1222 | { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data }, | |
1223 | { .compatible = "xlnx,axi-can-1.00.a", }, | |
1224 | { /* end of list */ }, | |
1225 | }; | |
1226 | MODULE_DEVICE_TABLE(of, xcan_of_match); | |
1227 | ||
b1201e44 KA |
1228 | /** |
1229 | * xcan_probe - Platform registration call | |
1230 | * @pdev: Handle to the platform device structure | |
1231 | * | |
1232 | * This function does all the memory allocation and registration for the CAN | |
1233 | * device. | |
1234 | * | |
1235 | * Return: 0 on success and failure value on error | |
1236 | */ | |
1237 | static int xcan_probe(struct platform_device *pdev) | |
1238 | { | |
1239 | struct resource *res; /* IO mem resources */ | |
1240 | struct net_device *ndev; | |
1241 | struct xcan_priv *priv; | |
0e2078f5 AH |
1242 | const struct of_device_id *of_id; |
1243 | int caps = 0; | |
b1201e44 | 1244 | void __iomem *addr; |
0e2078f5 | 1245 | int ret, rx_max, tx_max, tx_fifo_depth; |
b1201e44 KA |
1246 | |
1247 | /* Get the virtual base address for the device */ | |
1248 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1249 | addr = devm_ioremap_resource(&pdev->dev, res); | |
1250 | if (IS_ERR(addr)) { | |
1251 | ret = PTR_ERR(addr); | |
1252 | goto err; | |
1253 | } | |
1254 | ||
0e2078f5 AH |
1255 | ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", |
1256 | &tx_fifo_depth); | |
b1201e44 KA |
1257 | if (ret < 0) |
1258 | goto err; | |
1259 | ||
1260 | ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max); | |
1261 | if (ret < 0) | |
1262 | goto err; | |
1263 | ||
0e2078f5 AH |
1264 | of_id = of_match_device(xcan_of_match, &pdev->dev); |
1265 | if (of_id) { | |
1266 | const struct xcan_devtype_data *devtype_data = of_id->data; | |
1267 | ||
1268 | if (devtype_data) | |
1269 | caps = devtype_data->caps; | |
1270 | } | |
1271 | ||
1272 | /* There is no way to directly figure out how many frames have been | |
1273 | * sent when the TXOK interrupt is processed. If watermark programming | |
1274 | * is supported, we can have 2 frames in the FIFO and use TXFEMP | |
1275 | * to determine if 1 or 2 frames have been sent. | |
1276 | * Theoretically we should be able to use TXFWMEMP to determine up | |
1277 | * to 3 frames, but it seems that after putting a second frame in the | |
1278 | * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less | |
1279 | * than 2 frames in FIFO) is set anyway with no TXOK (a frame was | |
1280 | * sent), which is not a sensible state - possibly TXFWMEMP is not | |
1281 | * completely synchronized with the rest of the bits? | |
1282 | */ | |
1283 | if (caps & XCAN_CAP_WATERMARK) | |
1284 | tx_max = min(tx_fifo_depth, 2); | |
1285 | else | |
1286 | tx_max = 1; | |
1287 | ||
b1201e44 KA |
1288 | /* Create a CAN device instance */ |
1289 | ndev = alloc_candev(sizeof(struct xcan_priv), tx_max); | |
1290 | if (!ndev) | |
1291 | return -ENOMEM; | |
1292 | ||
1293 | priv = netdev_priv(ndev); | |
4716620d | 1294 | priv->dev = &pdev->dev; |
b1201e44 KA |
1295 | priv->can.bittiming_const = &xcan_bittiming_const; |
1296 | priv->can.do_set_mode = xcan_do_set_mode; | |
1297 | priv->can.do_get_berr_counter = xcan_get_berr_counter; | |
1298 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | | |
1299 | CAN_CTRLMODE_BERR_REPORTING; | |
1300 | priv->reg_base = addr; | |
1301 | priv->tx_max = tx_max; | |
0e2078f5 | 1302 | spin_lock_init(&priv->tx_lock); |
b1201e44 KA |
1303 | |
1304 | /* Get IRQ for the device */ | |
1305 | ndev->irq = platform_get_irq(pdev, 0); | |
1306 | ndev->flags |= IFF_ECHO; /* We support local echo */ | |
1307 | ||
1308 | platform_set_drvdata(pdev, ndev); | |
1309 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1310 | ndev->netdev_ops = &xcan_netdev_ops; | |
1311 | ||
1312 | /* Getting the CAN can_clk info */ | |
1313 | priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); | |
1314 | if (IS_ERR(priv->can_clk)) { | |
1315 | dev_err(&pdev->dev, "Device clock not found.\n"); | |
1316 | ret = PTR_ERR(priv->can_clk); | |
1317 | goto err_free; | |
1318 | } | |
1319 | /* Check for type of CAN device */ | |
1320 | if (of_device_is_compatible(pdev->dev.of_node, | |
1321 | "xlnx,zynq-can-1.0")) { | |
1322 | priv->bus_clk = devm_clk_get(&pdev->dev, "pclk"); | |
1323 | if (IS_ERR(priv->bus_clk)) { | |
1324 | dev_err(&pdev->dev, "bus clock not found\n"); | |
1325 | ret = PTR_ERR(priv->bus_clk); | |
1326 | goto err_free; | |
1327 | } | |
1328 | } else { | |
1329 | priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); | |
1330 | if (IS_ERR(priv->bus_clk)) { | |
1331 | dev_err(&pdev->dev, "bus clock not found\n"); | |
1332 | ret = PTR_ERR(priv->bus_clk); | |
1333 | goto err_free; | |
1334 | } | |
1335 | } | |
1336 | ||
b1201e44 KA |
1337 | priv->write_reg = xcan_write_reg_le; |
1338 | priv->read_reg = xcan_read_reg_le; | |
1339 | ||
4716620d KA |
1340 | pm_runtime_enable(&pdev->dev); |
1341 | ret = pm_runtime_get_sync(&pdev->dev); | |
1342 | if (ret < 0) { | |
1343 | netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", | |
1344 | __func__, ret); | |
1345 | goto err_pmdisable; | |
1346 | } | |
1347 | ||
b1201e44 KA |
1348 | if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { |
1349 | priv->write_reg = xcan_write_reg_be; | |
1350 | priv->read_reg = xcan_read_reg_be; | |
1351 | } | |
1352 | ||
1353 | priv->can.clock.freq = clk_get_rate(priv->can_clk); | |
1354 | ||
1355 | netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max); | |
1356 | ||
1357 | ret = register_candev(ndev); | |
1358 | if (ret) { | |
1359 | dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); | |
4716620d | 1360 | goto err_disableclks; |
b1201e44 KA |
1361 | } |
1362 | ||
1363 | devm_can_led_init(ndev); | |
4716620d KA |
1364 | |
1365 | pm_runtime_put(&pdev->dev); | |
1366 | ||
0e2078f5 | 1367 | netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth: actual %d, using %d\n", |
b1201e44 | 1368 | priv->reg_base, ndev->irq, priv->can.clock.freq, |
0e2078f5 | 1369 | tx_fifo_depth, priv->tx_max); |
b1201e44 KA |
1370 | |
1371 | return 0; | |
1372 | ||
4716620d KA |
1373 | err_disableclks: |
1374 | pm_runtime_put(priv->dev); | |
1375 | err_pmdisable: | |
1376 | pm_runtime_disable(&pdev->dev); | |
b1201e44 KA |
1377 | err_free: |
1378 | free_candev(ndev); | |
1379 | err: | |
1380 | return ret; | |
1381 | } | |
1382 | ||
1383 | /** | |
1384 | * xcan_remove - Unregister the device after releasing the resources | |
1385 | * @pdev: Handle to the platform device structure | |
1386 | * | |
1387 | * This function frees all the resources allocated to the device. | |
1388 | * Return: 0 always | |
1389 | */ | |
1390 | static int xcan_remove(struct platform_device *pdev) | |
1391 | { | |
1392 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1393 | struct xcan_priv *priv = netdev_priv(ndev); | |
1394 | ||
b1201e44 | 1395 | unregister_candev(ndev); |
4716620d | 1396 | pm_runtime_disable(&pdev->dev); |
b1201e44 KA |
1397 | netif_napi_del(&priv->napi); |
1398 | free_candev(ndev); | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
b1201e44 KA |
1403 | static struct platform_driver xcan_driver = { |
1404 | .probe = xcan_probe, | |
1405 | .remove = xcan_remove, | |
1406 | .driver = { | |
b1201e44 KA |
1407 | .name = DRIVER_NAME, |
1408 | .pm = &xcan_dev_pm_ops, | |
1409 | .of_match_table = xcan_of_match, | |
1410 | }, | |
1411 | }; | |
1412 | ||
1413 | module_platform_driver(xcan_driver); | |
1414 | ||
1415 | MODULE_LICENSE("GPL"); | |
1416 | MODULE_AUTHOR("Xilinx Inc"); | |
1417 | MODULE_DESCRIPTION("Xilinx CAN interface"); |