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igbvf: Allow VF driver to correctly recognize failure to set mac
[mirror_ubuntu-bionic-kernel.git] / drivers / net / chelsio / cxgb2.c
CommitLineData
8199d3a7
CL		 1/*****************************************************************************
2 * *
3 * File: cxgb2.c *
559fb51b
SB		 4 * $Revision: 1.25 $ *
5 * $Date: 2005/06/22 00:43:25 $ *
8199d3a7
CL		 6 * Description: *
7 * Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#include "common.h"
8199d3a7
CL		 40#include <linux/module.h>
41#include <linux/init.h>
42#include <linux/pci.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/if_vlan.h>
46#include <linux/mii.h>
47#include <linux/sockios.h>
559fb51b 48#include <linux/dma-mapping.h>
8199d3a7
CL		 49#include <asm/uaccess.h>
50
8199d3a7
CL		 51#include "cpl5_cmd.h"
52#include "regs.h"
53#include "gmac.h"
54#include "cphy.h"
55#include "sge.h"
f1d3d38a 56#include "tp.h"
8199d3a7 57#include "espi.h"
f1d3d38a 58#include "elmer0.h"
8199d3a7 59
559fb51b 60#include <linux/workqueue.h>
8199d3a7 61
559fb51b
SB		 62static inline void schedule_mac_stats_update(struct adapter *ap, int secs)
63{
64 schedule_delayed_work(&ap->stats_update_task, secs * HZ);
65}
8199d3a7 66
559fb51b
SB		 67static inline void cancel_mac_stats_update(struct adapter *ap)
68{
69 cancel_delayed_work(&ap->stats_update_task);
70}
8199d3a7 71
356bd146
FR		 72#define MAX_CMDQ_ENTRIES 16384
73#define MAX_CMDQ1_ENTRIES 1024
74#define MAX_RX_BUFFERS 16384
75#define MAX_RX_JUMBO_BUFFERS 16384
8199d3a7
CL		 76#define MAX_TX_BUFFERS_HIGH 16384U
77#define MAX_TX_BUFFERS_LOW 1536U
f1d3d38a 78#define MAX_TX_BUFFERS 1460U
356bd146 79#define MIN_FL_ENTRIES 32
8199d3a7 80
8199d3a7
CL		 81#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
82 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
83 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
84
85/*
86 * The EEPROM is actually bigger but only the first few bytes are used so we
87 * only report those.
88 */
89#define EEPROM_SIZE 32
90
559fb51b 91MODULE_DESCRIPTION(DRV_DESCRIPTION);
8199d3a7
CL		 92MODULE_AUTHOR("Chelsio Communications");
93MODULE_LICENSE("GPL");
8199d3a7
CL		 94
95static int dflt_msg_enable = DFLT_MSG_ENABLE;
96
8d3b33f6 97module_param(dflt_msg_enable, int, 0);
f1d3d38a
SH		 98MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T1 default message enable bitmap");
99
100#define HCLOCK 0x0
101#define LCLOCK 0x1
102
103/* T1 cards powersave mode */
104static int t1_clock(struct adapter *adapter, int mode);
105static int t1powersave = 1; /* HW default is powersave mode. */
8199d3a7 106
f1d3d38a
SH		 107module_param(t1powersave, int, 0);
108MODULE_PARM_DESC(t1powersave, "Enable/Disable T1 powersaving mode");
8199d3a7 109
325dde48
SH		 110static int disable_msi = 0;
111module_param(disable_msi, int, 0);
112MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
8199d3a7
CL		 113
114static const char pci_speed[][4] = {
115 "33", "66", "100", "133"
116};
117
118/*
119 * Setup MAC to receive the types of packets we want.
120 */
121static void t1_set_rxmode(struct net_device *dev)
122{
c3ccc123 123 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 124 struct cmac *mac = adapter->port[dev->if_port].mac;
125 struct t1_rx_mode rm;
126
127 rm.dev = dev;
128 rm.idx = 0;
129 rm.list = dev->mc_list;
130 mac->ops->set_rx_mode(mac, &rm);
131}
132
133static void link_report(struct port_info *p)
134{
135 if (!netif_carrier_ok(p->dev))
20578151 136 printk(KERN_INFO "%s: link down\n", p->dev->name);
8199d3a7 137 else {
559fb51b 138 const char *s = "10Mbps";
8199d3a7
CL		 139
140 switch (p->link_config.speed) {
559fb51b
SB		 141 case SPEED_10000: s = "10Gbps"; break;
142 case SPEED_1000: s = "1000Mbps"; break;
143 case SPEED_100: s = "100Mbps"; break;
8199d3a7
CL		 144 }
145
356bd146 146 printk(KERN_INFO "%s: link up, %s, %s-duplex\n",
8199d3a7
CL		 147 p->dev->name, s,
148 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
149 }
150}
151
f1d3d38a 152void t1_link_negotiated(struct adapter *adapter, int port_id, int link_stat,
8199d3a7
CL		 153 int speed, int duplex, int pause)
154{
155 struct port_info *p = &adapter->port[port_id];
156
157 if (link_stat != netif_carrier_ok(p->dev)) {
158 if (link_stat)
159 netif_carrier_on(p->dev);
160 else
161 netif_carrier_off(p->dev);
162 link_report(p);
163
f1d3d38a
SH		 164 /* multi-ports: inform toe */
165 if ((speed > 0) && (adapter->params.nports > 1)) {
166 unsigned int sched_speed = 10;
167 switch (speed) {
168 case SPEED_1000:
169 sched_speed = 1000;
170 break;
171 case SPEED_100:
172 sched_speed = 100;
173 break;
174 case SPEED_10:
175 sched_speed = 10;
176 break;
177 }
178 t1_sched_update_parms(adapter->sge, port_id, 0, sched_speed);
179 }
8199d3a7
CL		 180 }
181}
182
183static void link_start(struct port_info *p)
184{
185 struct cmac *mac = p->mac;
186
187 mac->ops->reset(mac);
188 if (mac->ops->macaddress_set)
189 mac->ops->macaddress_set(mac, p->dev->dev_addr);
190 t1_set_rxmode(p->dev);
191 t1_link_start(p->phy, mac, &p->link_config);
192 mac->ops->enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
193}
194
195static void enable_hw_csum(struct adapter *adapter)
196{
197 if (adapter->flags & TSO_CAPABLE)
f1d3d38a
SH		 198 t1_tp_set_ip_checksum_offload(adapter->tp, 1); /* for TSO only */
199 if (adapter->flags & UDP_CSUM_CAPABLE)
200 t1_tp_set_udp_checksum_offload(adapter->tp, 1);
201 t1_tp_set_tcp_checksum_offload(adapter->tp, 1);
8199d3a7
CL		 202}
203
204/*
205 * Things to do upon first use of a card.
206 * This must run with the rtnl lock held.
207 */
208static int cxgb_up(struct adapter *adapter)
209{
210 int err = 0;
211
212 if (!(adapter->flags & FULL_INIT_DONE)) {
213 err = t1_init_hw_modules(adapter);
214 if (err)
215 goto out_err;
216
217 enable_hw_csum(adapter);
218 adapter->flags |= FULL_INIT_DONE;
219 }
220
221 t1_interrupts_clear(adapter);
325dde48 222
7fe26a60
SH		 223 adapter->params.has_msi = !disable_msi && !pci_enable_msi(adapter->pdev);
224 err = request_irq(adapter->pdev->irq, t1_interrupt,
325dde48
SH		 225 adapter->params.has_msi ? 0 : IRQF_SHARED,
226 adapter->name, adapter);
227 if (err) {
228 if (adapter->params.has_msi)
229 pci_disable_msi(adapter->pdev);
230
8199d3a7 231 goto out_err;
559fb51b 232 }
325dde48 233
8199d3a7
CL		 234 t1_sge_start(adapter->sge);
235 t1_interrupts_enable(adapter);
356bd146 236out_err:
8199d3a7
CL		 237 return err;
238}
239
240/*
241 * Release resources when all the ports have been stopped.
242 */
243static void cxgb_down(struct adapter *adapter)
244{
245 t1_sge_stop(adapter->sge);
246 t1_interrupts_disable(adapter);
247 free_irq(adapter->pdev->irq, adapter);
325dde48
SH		 248 if (adapter->params.has_msi)
249 pci_disable_msi(adapter->pdev);
8199d3a7
CL		 250}
251
252static int cxgb_open(struct net_device *dev)
253{
254 int err;
c3ccc123 255 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 256 int other_ports = adapter->open_device_map & PORT_MASK;
257
bea3348e
SH		 258 napi_enable(&adapter->napi);
259 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0) {
260 napi_disable(&adapter->napi);
8199d3a7 261 return err;
bea3348e 262 }
8199d3a7
CL		 263
264 __set_bit(dev->if_port, &adapter->open_device_map);
265 link_start(&adapter->port[dev->if_port]);
266 netif_start_queue(dev);
267 if (!other_ports && adapter->params.stats_update_period)
268 schedule_mac_stats_update(adapter,
269 adapter->params.stats_update_period);
270 return 0;
271}
272
273static int cxgb_close(struct net_device *dev)
274{
c3ccc123 275 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 276 struct port_info *p = &adapter->port[dev->if_port];
277 struct cmac *mac = p->mac;
278
279 netif_stop_queue(dev);
bea3348e 280 napi_disable(&adapter->napi);
8199d3a7
CL		 281 mac->ops->disable(mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
282 netif_carrier_off(dev);
283
284 clear_bit(dev->if_port, &adapter->open_device_map);
285 if (adapter->params.stats_update_period &&
286 !(adapter->open_device_map & PORT_MASK)) {
287 /* Stop statistics accumulation. */
288 smp_mb__after_clear_bit();
289 spin_lock(&adapter->work_lock); /* sync with update task */
290 spin_unlock(&adapter->work_lock);
291 cancel_mac_stats_update(adapter);
292 }
293
294 if (!adapter->open_device_map)
295 cxgb_down(adapter);
296 return 0;
297}
298
299static struct net_device_stats *t1_get_stats(struct net_device *dev)
300{
c3ccc123 301 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 302 struct port_info *p = &adapter->port[dev->if_port];
303 struct net_device_stats *ns = &p->netstats;
304 const struct cmac_statistics *pstats;
305
306 /* Do a full update of the MAC stats */
307 pstats = p->mac->ops->statistics_update(p->mac,
20578151 308 MAC_STATS_UPDATE_FULL);
8199d3a7
CL		 309
310 ns->tx_packets = pstats->TxUnicastFramesOK +
311 pstats->TxMulticastFramesOK + pstats->TxBroadcastFramesOK;
312
313 ns->rx_packets = pstats->RxUnicastFramesOK +
314 pstats->RxMulticastFramesOK + pstats->RxBroadcastFramesOK;
315
316 ns->tx_bytes = pstats->TxOctetsOK;
317 ns->rx_bytes = pstats->RxOctetsOK;
318
319 ns->tx_errors = pstats->TxLateCollisions + pstats->TxLengthErrors +
320 pstats->TxUnderrun + pstats->TxFramesAbortedDueToXSCollisions;
321 ns->rx_errors = pstats->RxDataErrors + pstats->RxJabberErrors +
322 pstats->RxFCSErrors + pstats->RxAlignErrors +
323 pstats->RxSequenceErrors + pstats->RxFrameTooLongErrors +
324 pstats->RxSymbolErrors + pstats->RxRuntErrors;
325
326 ns->multicast = pstats->RxMulticastFramesOK;
327 ns->collisions = pstats->TxTotalCollisions;
328
329 /* detailed rx_errors */
330 ns->rx_length_errors = pstats->RxFrameTooLongErrors +
331 pstats->RxJabberErrors;
332 ns->rx_over_errors = 0;
333 ns->rx_crc_errors = pstats->RxFCSErrors;
334 ns->rx_frame_errors = pstats->RxAlignErrors;
335 ns->rx_fifo_errors = 0;
336 ns->rx_missed_errors = 0;
337
338 /* detailed tx_errors */
339 ns->tx_aborted_errors = pstats->TxFramesAbortedDueToXSCollisions;
340 ns->tx_carrier_errors = 0;
341 ns->tx_fifo_errors = pstats->TxUnderrun;
342 ns->tx_heartbeat_errors = 0;
343 ns->tx_window_errors = pstats->TxLateCollisions;
344 return ns;
345}
346
347static u32 get_msglevel(struct net_device *dev)
348{
c3ccc123 349 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 350
351 return adapter->msg_enable;
352}
353
354static void set_msglevel(struct net_device *dev, u32 val)
355{
c3ccc123 356 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 357
358 adapter->msg_enable = val;
359}
360
361static char stats_strings[][ETH_GSTRING_LEN] = {
20578151
SH		 362 "TxOctetsOK",
363 "TxOctetsBad",
364 "TxUnicastFramesOK",
365 "TxMulticastFramesOK",
366 "TxBroadcastFramesOK",
367 "TxPauseFrames",
368 "TxFramesWithDeferredXmissions",
369 "TxLateCollisions",
370 "TxTotalCollisions",
371 "TxFramesAbortedDueToXSCollisions",
372 "TxUnderrun",
373 "TxLengthErrors",
374 "TxInternalMACXmitError",
375 "TxFramesWithExcessiveDeferral",
376 "TxFCSErrors",
e0348b9a
DLR		 377 "TxJumboFramesOk",
378 "TxJumboOctetsOk",
379
20578151
SH		 380 "RxOctetsOK",
381 "RxOctetsBad",
382 "RxUnicastFramesOK",
383 "RxMulticastFramesOK",
384 "RxBroadcastFramesOK",
385 "RxPauseFrames",
386 "RxFCSErrors",
387 "RxAlignErrors",
388 "RxSymbolErrors",
389 "RxDataErrors",
390 "RxSequenceErrors",
391 "RxRuntErrors",
392 "RxJabberErrors",
393 "RxInternalMACRcvError",
394 "RxInRangeLengthErrors",
395 "RxOutOfRangeLengthField",
396 "RxFrameTooLongErrors",
e0348b9a
DLR		 397 "RxJumboFramesOk",
398 "RxJumboOctetsOk",
559fb51b 399
56f643c2 400 /* Port stats */
559fb51b
SB		 401 "RxCsumGood",
402 "TxCsumOffload",
56f643c2
SH		 403 "TxTso",
404 "RxVlan",
405 "TxVlan",
7832ee03
DLR		 406 "TxNeedHeadroom",
407
56f643c2
SH		 408 /* Interrupt stats */
409 "rx drops",
410 "pure_rsps",
411 "unhandled irqs",
559fb51b
SB		 412 "respQ_empty",
413 "respQ_overflow",
414 "freelistQ_empty",
415 "pkt_too_big",
416 "pkt_mismatch",
417 "cmdQ_full0",
418 "cmdQ_full1",
20578151 419
559fb51b
SB		 420 "espi_DIP2ParityErr",
421 "espi_DIP4Err",
422 "espi_RxDrops",
423 "espi_TxDrops",
424 "espi_RxOvfl",
425 "espi_ParityErr"
8199d3a7 426};
20578151 427
559fb51b
SB		 428#define T2_REGMAP_SIZE (3 * 1024)
429
430static int get_regs_len(struct net_device *dev)
431{
432 return T2_REGMAP_SIZE;
433}
8199d3a7
CL		 434
435static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
436{
c3ccc123 437 struct adapter *adapter = dev->ml_priv;
8199d3a7 438
559fb51b
SB		 439 strcpy(info->driver, DRV_NAME);
440 strcpy(info->version, DRV_VERSION);
8199d3a7
CL		 441 strcpy(info->fw_version, "N/A");
442 strcpy(info->bus_info, pci_name(adapter->pdev));
443}
444
b9f2c044 445static int get_sset_count(struct net_device *dev, int sset)
8199d3a7 446{
b9f2c044
JG		 447 switch (sset) {
448 case ETH_SS_STATS:
449 return ARRAY_SIZE(stats_strings);
450 default:
451 return -EOPNOTSUPP;
452 }
8199d3a7
CL		 453}
454
455static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
456{
457 if (stringset == ETH_SS_STATS)
458 memcpy(data, stats_strings, sizeof(stats_strings));
459}
460
461static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
462 u64 *data)
463{
c3ccc123 464 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 465 struct cmac *mac = adapter->port[dev->if_port].mac;
466 const struct cmac_statistics *s;
559fb51b 467 const struct sge_intr_counts *t;
56f643c2 468 struct sge_port_stats ss;
8199d3a7
CL		 469
470 s = mac->ops->statistics_update(mac, MAC_STATS_UPDATE_FULL);
e0348b9a 471 t = t1_sge_get_intr_counts(adapter->sge);
56f643c2 472 t1_sge_get_port_stats(adapter->sge, dev->if_port, &ss);
56f643c2 473
e0348b9a
DLR		 474 *data++ = s->TxOctetsOK;
475 *data++ = s->TxOctetsBad;
476 *data++ = s->TxUnicastFramesOK;
477 *data++ = s->TxMulticastFramesOK;
478 *data++ = s->TxBroadcastFramesOK;
479 *data++ = s->TxPauseFrames;
480 *data++ = s->TxFramesWithDeferredXmissions;
481 *data++ = s->TxLateCollisions;
482 *data++ = s->TxTotalCollisions;
483 *data++ = s->TxFramesAbortedDueToXSCollisions;
484 *data++ = s->TxUnderrun;
485 *data++ = s->TxLengthErrors;
486 *data++ = s->TxInternalMACXmitError;
487 *data++ = s->TxFramesWithExcessiveDeferral;
488 *data++ = s->TxFCSErrors;
489 *data++ = s->TxJumboFramesOK;
490 *data++ = s->TxJumboOctetsOK;
491
492 *data++ = s->RxOctetsOK;
493 *data++ = s->RxOctetsBad;
494 *data++ = s->RxUnicastFramesOK;
495 *data++ = s->RxMulticastFramesOK;
496 *data++ = s->RxBroadcastFramesOK;
497 *data++ = s->RxPauseFrames;
498 *data++ = s->RxFCSErrors;
499 *data++ = s->RxAlignErrors;
500 *data++ = s->RxSymbolErrors;
501 *data++ = s->RxDataErrors;
502 *data++ = s->RxSequenceErrors;
503 *data++ = s->RxRuntErrors;
504 *data++ = s->RxJabberErrors;
505 *data++ = s->RxInternalMACRcvError;
506 *data++ = s->RxInRangeLengthErrors;
507 *data++ = s->RxOutOfRangeLengthField;
508 *data++ = s->RxFrameTooLongErrors;
509 *data++ = s->RxJumboFramesOK;
510 *data++ = s->RxJumboOctetsOK;
511
512 *data++ = ss.rx_cso_good;
513 *data++ = ss.tx_cso;
514 *data++ = ss.tx_tso;
515 *data++ = ss.vlan_xtract;
516 *data++ = ss.vlan_insert;
517 *data++ = ss.tx_need_hdrroom;
518
56f643c2
SH		 519 *data++ = t->rx_drops;
520 *data++ = t->pure_rsps;
521 *data++ = t->unhandled_irqs;
522 *data++ = t->respQ_empty;
523 *data++ = t->respQ_overflow;
524 *data++ = t->freelistQ_empty;
525 *data++ = t->pkt_too_big;
526 *data++ = t->pkt_mismatch;
527 *data++ = t->cmdQ_full[0];
528 *data++ = t->cmdQ_full[1];
f1d3d38a
SH		 529
530 if (adapter->espi) {
531 const struct espi_intr_counts *e;
532
533 e = t1_espi_get_intr_counts(adapter->espi);
56f643c2
SH		 534 *data++ = e->DIP2_parity_err;
535 *data++ = e->DIP4_err;
536 *data++ = e->rx_drops;
537 *data++ = e->tx_drops;
538 *data++ = e->rx_ovflw;
539 *data++ = e->parity_err;
f1d3d38a 540 }
559fb51b
SB		 541}
542
543static inline void reg_block_dump(struct adapter *ap, void *buf,
544 unsigned int start, unsigned int end)
545{
546 u32 *p = buf + start;
547
548 for ( ; start <= end; start += sizeof(u32))
549 *p++ = readl(ap->regs + start);
550}
8199d3a7 551
559fb51b
SB		 552static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
553 void *buf)
554{
c3ccc123 555 struct adapter *ap = dev->ml_priv;
559fb51b
SB		 556
557 /*
558 * Version scheme: bits 0..9: chip version, bits 10..15: chip revision
559 */
560 regs->version = 2;
561
562 memset(buf, 0, T2_REGMAP_SIZE);
563 reg_block_dump(ap, buf, 0, A_SG_RESPACCUTIMER);
f1d3d38a
SH		 564 reg_block_dump(ap, buf, A_MC3_CFG, A_MC4_INT_CAUSE);
565 reg_block_dump(ap, buf, A_TPI_ADDR, A_TPI_PAR);
566 reg_block_dump(ap, buf, A_TP_IN_CONFIG, A_TP_TX_DROP_COUNT);
567 reg_block_dump(ap, buf, A_RAT_ROUTE_CONTROL, A_RAT_INTR_CAUSE);
568 reg_block_dump(ap, buf, A_CSPI_RX_AE_WM, A_CSPI_INTR_ENABLE);
569 reg_block_dump(ap, buf, A_ESPI_SCH_TOKEN0, A_ESPI_GOSTAT);
570 reg_block_dump(ap, buf, A_ULP_ULIMIT, A_ULP_PIO_CTRL);
571 reg_block_dump(ap, buf, A_PL_ENABLE, A_PL_CAUSE);
572 reg_block_dump(ap, buf, A_MC5_CONFIG, A_MC5_MASK_WRITE_CMD);
8199d3a7
CL		 573}
574
575static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
576{
c3ccc123 577 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 578 struct port_info *p = &adapter->port[dev->if_port];
579
580 cmd->supported = p->link_config.supported;
581 cmd->advertising = p->link_config.advertising;
582
583 if (netif_carrier_ok(dev)) {
584 cmd->speed = p->link_config.speed;
585 cmd->duplex = p->link_config.duplex;
586 } else {
587 cmd->speed = -1;
588 cmd->duplex = -1;
589 }
590
20578151 591 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
23c3320c 592 cmd->phy_address = p->phy->mdio.prtad;
20578151
SH		 593 cmd->transceiver = XCVR_EXTERNAL;
594 cmd->autoneg = p->link_config.autoneg;
595 cmd->maxtxpkt = 0;
596 cmd->maxrxpkt = 0;
8199d3a7
CL		 597 return 0;
598}
599
600static int speed_duplex_to_caps(int speed, int duplex)
601{
602 int cap = 0;
603
604 switch (speed) {
605 case SPEED_10:
606 if (duplex == DUPLEX_FULL)
607 cap = SUPPORTED_10baseT_Full;
608 else
609 cap = SUPPORTED_10baseT_Half;
610 break;
611 case SPEED_100:
612 if (duplex == DUPLEX_FULL)
613 cap = SUPPORTED_100baseT_Full;
614 else
615 cap = SUPPORTED_100baseT_Half;
616 break;
617 case SPEED_1000:
618 if (duplex == DUPLEX_FULL)
619 cap = SUPPORTED_1000baseT_Full;
620 else
621 cap = SUPPORTED_1000baseT_Half;
622 break;
623 case SPEED_10000:
624 if (duplex == DUPLEX_FULL)
625 cap = SUPPORTED_10000baseT_Full;
626 }
627 return cap;
628}
629
630#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
631 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
632 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
633 ADVERTISED_10000baseT_Full)
634
635static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
636{
c3ccc123 637 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 638 struct port_info *p = &adapter->port[dev->if_port];
639 struct link_config *lc = &p->link_config;
640
641 if (!(lc->supported & SUPPORTED_Autoneg))
559fb51b 642 return -EOPNOTSUPP; /* can't change speed/duplex */
8199d3a7
CL		 643
644 if (cmd->autoneg == AUTONEG_DISABLE) {
645 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
646
647 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
648 return -EINVAL;
649 lc->requested_speed = cmd->speed;
650 lc->requested_duplex = cmd->duplex;
651 lc->advertising = 0;
652 } else {
653 cmd->advertising &= ADVERTISED_MASK;
654 if (cmd->advertising & (cmd->advertising - 1))
655 cmd->advertising = lc->supported;
656 cmd->advertising &= lc->supported;
657 if (!cmd->advertising)
658 return -EINVAL;
659 lc->requested_speed = SPEED_INVALID;
660 lc->requested_duplex = DUPLEX_INVALID;
661 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
662 }
663 lc->autoneg = cmd->autoneg;
664 if (netif_running(dev))
665 t1_link_start(p->phy, p->mac, lc);
666 return 0;
667}
668
669static void get_pauseparam(struct net_device *dev,
670 struct ethtool_pauseparam *epause)
671{
c3ccc123 672 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 673 struct port_info *p = &adapter->port[dev->if_port];
674
675 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
676 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
677 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
678}
679
680static int set_pauseparam(struct net_device *dev,
681 struct ethtool_pauseparam *epause)
682{
c3ccc123 683 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 684 struct port_info *p = &adapter->port[dev->if_port];
685 struct link_config *lc = &p->link_config;
686
687 if (epause->autoneg == AUTONEG_DISABLE)
688 lc->requested_fc = 0;
689 else if (lc->supported & SUPPORTED_Autoneg)
690 lc->requested_fc = PAUSE_AUTONEG;
691 else
692 return -EINVAL;
693
694 if (epause->rx_pause)
695 lc->requested_fc |= PAUSE_RX;
696 if (epause->tx_pause)
697 lc->requested_fc |= PAUSE_TX;
698 if (lc->autoneg == AUTONEG_ENABLE) {
699 if (netif_running(dev))
700 t1_link_start(p->phy, p->mac, lc);
701 } else {
702 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
703 if (netif_running(dev))
704 p->mac->ops->set_speed_duplex_fc(p->mac, -1, -1,
705 lc->fc);
706 }
707 return 0;
708}
709
710static u32 get_rx_csum(struct net_device *dev)
711{
c3ccc123 712 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 713
714 return (adapter->flags & RX_CSUM_ENABLED) != 0;
715}
716
717static int set_rx_csum(struct net_device *dev, u32 data)
718{
c3ccc123 719 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 720
721 if (data)
722 adapter->flags |= RX_CSUM_ENABLED;
723 else
724 adapter->flags &= ~RX_CSUM_ENABLED;
725 return 0;
726}
727
728static int set_tso(struct net_device *dev, u32 value)
729{
c3ccc123 730 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 731
732 if (!(adapter->flags & TSO_CAPABLE))
733 return value ? -EOPNOTSUPP : 0;
734 return ethtool_op_set_tso(dev, value);
735}
736
737static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
738{
c3ccc123 739 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 740 int jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
741
742 e->rx_max_pending = MAX_RX_BUFFERS;
743 e->rx_mini_max_pending = 0;
744 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
745 e->tx_max_pending = MAX_CMDQ_ENTRIES;
746
747 e->rx_pending = adapter->params.sge.freelQ_size[!jumbo_fl];
748 e->rx_mini_pending = 0;
749 e->rx_jumbo_pending = adapter->params.sge.freelQ_size[jumbo_fl];
750 e->tx_pending = adapter->params.sge.cmdQ_size[0];
751}
752
753static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
754{
c3ccc123 755 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 756 int jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
757
758 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_mini_pending ||
759 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
760 e->tx_pending > MAX_CMDQ_ENTRIES ||
761 e->rx_pending < MIN_FL_ENTRIES ||
762 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
763 e->tx_pending < (adapter->params.nports + 1) * (MAX_SKB_FRAGS + 1))
764 return -EINVAL;
765
766 if (adapter->flags & FULL_INIT_DONE)
356bd146 767 return -EBUSY;
8199d3a7
CL		 768
769 adapter->params.sge.freelQ_size[!jumbo_fl] = e->rx_pending;
770 adapter->params.sge.freelQ_size[jumbo_fl] = e->rx_jumbo_pending;
771 adapter->params.sge.cmdQ_size[0] = e->tx_pending;
772 adapter->params.sge.cmdQ_size[1] = e->tx_pending > MAX_CMDQ1_ENTRIES ?
773 MAX_CMDQ1_ENTRIES : e->tx_pending;
774 return 0;
775}
776
777static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
778{
c3ccc123 779 struct adapter *adapter = dev->ml_priv;
8199d3a7 780
7fe26a60 781 adapter->params.sge.rx_coalesce_usecs = c->rx_coalesce_usecs;
356bd146 782 adapter->params.sge.coalesce_enable = c->use_adaptive_rx_coalesce;
8199d3a7 783 adapter->params.sge.sample_interval_usecs = c->rate_sample_interval;
8199d3a7
CL		 784 t1_sge_set_coalesce_params(adapter->sge, &adapter->params.sge);
785 return 0;
786}
787
788static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
789{
c3ccc123 790 struct adapter *adapter = dev->ml_priv;
8199d3a7 791
559fb51b 792 c->rx_coalesce_usecs = adapter->params.sge.rx_coalesce_usecs;
8199d3a7
CL		 793 c->rate_sample_interval = adapter->params.sge.sample_interval_usecs;
794 c->use_adaptive_rx_coalesce = adapter->params.sge.coalesce_enable;
795 return 0;
796}
797
798static int get_eeprom_len(struct net_device *dev)
799{
c3ccc123 800 struct adapter *adapter = dev->ml_priv;
f1d3d38a 801
356bd146 802 return t1_is_asic(adapter) ? EEPROM_SIZE : 0;
8199d3a7
CL		 803}
804
805#define EEPROM_MAGIC(ap) \
806 (PCI_VENDOR_ID_CHELSIO | ((ap)->params.chip_version << 16))
807
808static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
809 u8 *data)
810{
811 int i;
812 u8 buf[EEPROM_SIZE] __attribute__((aligned(4)));
c3ccc123 813 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 814
815 e->magic = EEPROM_MAGIC(adapter);
816 for (i = e->offset & ~3; i < e->offset + e->len; i += sizeof(u32))
ac390c60 817 t1_seeprom_read(adapter, i, (__le32 *)&buf[i]);
8199d3a7
CL		 818 memcpy(data, buf + e->offset, e->len);
819 return 0;
820}
821
7282d491 822static const struct ethtool_ops t1_ethtool_ops = {
8199d3a7
CL		 823 .get_settings = get_settings,
824 .set_settings = set_settings,
825 .get_drvinfo = get_drvinfo,
826 .get_msglevel = get_msglevel,
827 .set_msglevel = set_msglevel,
828 .get_ringparam = get_sge_param,
829 .set_ringparam = set_sge_param,
830 .get_coalesce = get_coalesce,
831 .set_coalesce = set_coalesce,
832 .get_eeprom_len = get_eeprom_len,
833 .get_eeprom = get_eeprom,
834 .get_pauseparam = get_pauseparam,
835 .set_pauseparam = set_pauseparam,
836 .get_rx_csum = get_rx_csum,
837 .set_rx_csum = set_rx_csum,
8199d3a7 838 .set_tx_csum = ethtool_op_set_tx_csum,
8199d3a7
CL		 839 .set_sg = ethtool_op_set_sg,
840 .get_link = ethtool_op_get_link,
841 .get_strings = get_strings,
b9f2c044 842 .get_sset_count = get_sset_count,
8199d3a7 843 .get_ethtool_stats = get_stats,
559fb51b
SB		 844 .get_regs_len = get_regs_len,
845 .get_regs = get_regs,
8199d3a7
CL		 846 .set_tso = set_tso,
847};
848
8199d3a7
CL		 849static int t1_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
850{
c3ccc123 851 struct adapter *adapter = dev->ml_priv;
23c3320c 852 struct mdio_if_info *mdio = &adapter->port[dev->if_port].phy->mdio;
8199d3a7 853
23c3320c 854 return mdio_mii_ioctl(mdio, if_mii(req), cmd);
8199d3a7
CL		 855}
856
857static int t1_change_mtu(struct net_device *dev, int new_mtu)
858{
859 int ret;
c3ccc123 860 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 861 struct cmac *mac = adapter->port[dev->if_port].mac;
862
863 if (!mac->ops->set_mtu)
356bd146 864 return -EOPNOTSUPP;
8199d3a7 865 if (new_mtu < 68)
356bd146 866 return -EINVAL;
8199d3a7
CL		 867 if ((ret = mac->ops->set_mtu(mac, new_mtu)))
868 return ret;
869 dev->mtu = new_mtu;
870 return 0;
871}
872
873static int t1_set_mac_addr(struct net_device *dev, void *p)
874{
c3ccc123 875 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 876 struct cmac *mac = adapter->port[dev->if_port].mac;
877 struct sockaddr *addr = p;
878
879 if (!mac->ops->macaddress_set)
880 return -EOPNOTSUPP;
881
882 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
883 mac->ops->macaddress_set(mac, dev->dev_addr);
884 return 0;
885}
886
887#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
00829823 888static void t1_vlan_rx_register(struct net_device *dev,
8199d3a7
CL		 889 struct vlan_group *grp)
890{
c3ccc123 891 struct adapter *adapter = dev->ml_priv;
8199d3a7
CL		 892
893 spin_lock_irq(&adapter->async_lock);
894 adapter->vlan_grp = grp;
895 t1_set_vlan_accel(adapter, grp != NULL);
896 spin_unlock_irq(&adapter->async_lock);
897}
8199d3a7
CL		 898#endif
899
900#ifdef CONFIG_NET_POLL_CONTROLLER
901static void t1_netpoll(struct net_device *dev)
902{
559fb51b 903 unsigned long flags;
c3ccc123 904 struct adapter *adapter = dev->ml_priv;
8199d3a7 905
559fb51b 906 local_irq_save(flags);
7fe26a60 907 t1_interrupt(adapter->pdev->irq, adapter);
559fb51b 908 local_irq_restore(flags);
8199d3a7
CL		 909}
910#endif
911
912/*
913 * Periodic accumulation of MAC statistics. This is used only if the MAC
914 * does not have any other way to prevent stats counter overflow.
915 */
c4028958 916static void mac_stats_task(struct work_struct *work)
8199d3a7
CL		 917{
918 int i;
c4028958
DH		 919 struct adapter *adapter =
920 container_of(work, struct adapter, stats_update_task.work);
8199d3a7
CL		 921
922 for_each_port(adapter, i) {
923 struct port_info *p = &adapter->port[i];
924
925 if (netif_running(p->dev))
926 p->mac->ops->statistics_update(p->mac,
927 MAC_STATS_UPDATE_FAST);
928 }
929
930 /* Schedule the next statistics update if any port is active. */
931 spin_lock(&adapter->work_lock);
932 if (adapter->open_device_map & PORT_MASK)
933 schedule_mac_stats_update(adapter,
934 adapter->params.stats_update_period);
935 spin_unlock(&adapter->work_lock);
936}
937
938/*
939 * Processes elmer0 external interrupts in process context.
940 */
c4028958 941static void ext_intr_task(struct work_struct *work)
8199d3a7 942{
c4028958
DH		 943 struct adapter *adapter =
944 container_of(work, struct adapter, ext_intr_handler_task);
8199d3a7 945
f1d3d38a 946 t1_elmer0_ext_intr_handler(adapter);
8199d3a7
CL		 947
948 /* Now reenable external interrupts */
559fb51b 949 spin_lock_irq(&adapter->async_lock);
8199d3a7 950 adapter->slow_intr_mask |= F_PL_INTR_EXT;
559fb51b
SB		 951 writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE);
952 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
20578151 953 adapter->regs + A_PL_ENABLE);
559fb51b 954 spin_unlock_irq(&adapter->async_lock);
8199d3a7
CL		 955}
956
957/*
958 * Interrupt-context handler for elmer0 external interrupts.
959 */
960void t1_elmer0_ext_intr(struct adapter *adapter)
961{
8199d3a7
CL		 962 /*
963 * Schedule a task to handle external interrupts as we require
964 * a process context. We disable EXT interrupts in the interim
965 * and let the task reenable them when it's done.
966 */
967 adapter->slow_intr_mask &= ~F_PL_INTR_EXT;
559fb51b 968 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
20578151 969 adapter->regs + A_PL_ENABLE);
8199d3a7
CL		 970 schedule_work(&adapter->ext_intr_handler_task);
971}
972
973void t1_fatal_err(struct adapter *adapter)
974{
975 if (adapter->flags & FULL_INIT_DONE) {
976 t1_sge_stop(adapter->sge);
977 t1_interrupts_disable(adapter);
978 }
979 CH_ALERT("%s: encountered fatal error, operation suspended\n",
980 adapter->name);
981}
982
80ff32b7
SH		 983static const struct net_device_ops cxgb_netdev_ops = {
984 .ndo_open = cxgb_open,
985 .ndo_stop = cxgb_close,
00829823 986 .ndo_start_xmit = t1_start_xmit,
80ff32b7
SH		 987 .ndo_get_stats = t1_get_stats,
988 .ndo_validate_addr = eth_validate_addr,
989 .ndo_set_multicast_list = t1_set_rxmode,
990 .ndo_do_ioctl = t1_ioctl,
991 .ndo_change_mtu = t1_change_mtu,
992 .ndo_set_mac_address = t1_set_mac_addr,
993#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
00829823 994 .ndo_vlan_rx_register = t1_vlan_rx_register,
80ff32b7
SH		 995#endif
996#ifdef CONFIG_NET_POLL_CONTROLLER
997 .ndo_poll_controller = t1_netpoll,
998#endif
999};
1000
8199d3a7
CL		 1001static int __devinit init_one(struct pci_dev *pdev,
1002 const struct pci_device_id *ent)
1003{
1004 static int version_printed;
1005
1006 int i, err, pci_using_dac = 0;
1007 unsigned long mmio_start, mmio_len;
1008 const struct board_info *bi;
1009 struct adapter *adapter = NULL;
1010 struct port_info *pi;
1011
1012 if (!version_printed) {
559fb51b
SB		 1013 printk(KERN_INFO "%s - version %s\n", DRV_DESCRIPTION,
1014 DRV_VERSION);
8199d3a7
CL		 1015 ++version_printed;
1016 }
1017
1018 err = pci_enable_device(pdev);
1019 if (err)
20578151 1020 return err;
8199d3a7
CL		 1021
1022 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1023 CH_ERR("%s: cannot find PCI device memory base address\n",
1024 pci_name(pdev));
1025 err = -ENODEV;
1026 goto out_disable_pdev;
1027 }
1028
6a35528a 1029 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
8199d3a7 1030 pci_using_dac = 1;
559fb51b 1031
6a35528a 1032 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
31067527 1033 CH_ERR("%s: unable to obtain 64-bit DMA for "
8199d3a7
CL		 1034 "consistent allocations\n", pci_name(pdev));
1035 err = -ENODEV;
1036 goto out_disable_pdev;
1037 }
559fb51b 1038
284901a9 1039 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
8199d3a7
CL		 1040 CH_ERR("%s: no usable DMA configuration\n", pci_name(pdev));
1041 goto out_disable_pdev;
1042 }
1043
559fb51b 1044 err = pci_request_regions(pdev, DRV_NAME);
8199d3a7
CL		 1045 if (err) {
1046 CH_ERR("%s: cannot obtain PCI resources\n", pci_name(pdev));
1047 goto out_disable_pdev;
1048 }
1049
1050 pci_set_master(pdev);
1051
20578151 1052 mmio_start = pci_resource_start(pdev, 0);
8199d3a7
CL		 1053 mmio_len = pci_resource_len(pdev, 0);
1054 bi = t1_get_board_info(ent->driver_data);
1055
1056 for (i = 0; i < bi->port_number; ++i) {
1057 struct net_device *netdev;
1058
1059 netdev = alloc_etherdev(adapter ? 0 : sizeof(*adapter));
1060 if (!netdev) {
1061 err = -ENOMEM;
1062 goto out_free_dev;
1063 }
1064
8199d3a7
CL		 1065 SET_NETDEV_DEV(netdev, &pdev->dev);
1066
1067 if (!adapter) {
c3ccc123 1068 adapter = netdev_priv(netdev);
8199d3a7
CL		 1069 adapter->pdev = pdev;
1070 adapter->port[0].dev = netdev; /* so we don't leak it */
1071
1072 adapter->regs = ioremap(mmio_start, mmio_len);
1073 if (!adapter->regs) {
1074 CH_ERR("%s: cannot map device registers\n",
1075 pci_name(pdev));
1076 err = -ENOMEM;
1077 goto out_free_dev;
1078 }
1079
1080 if (t1_get_board_rev(adapter, bi, &adapter->params)) {
1081 err = -ENODEV; /* Can't handle this chip rev */
1082 goto out_free_dev;
1083 }
1084
1085 adapter->name = pci_name(pdev);
1086 adapter->msg_enable = dflt_msg_enable;
1087 adapter->mmio_len = mmio_len;
1088
8199d3a7
CL		 1089 spin_lock_init(&adapter->tpi_lock);
1090 spin_lock_init(&adapter->work_lock);
1091 spin_lock_init(&adapter->async_lock);
352c417d 1092 spin_lock_init(&adapter->mac_lock);
8199d3a7
CL		 1093
1094 INIT_WORK(&adapter->ext_intr_handler_task,
c4028958
DH		 1095 ext_intr_task);
1096 INIT_DELAYED_WORK(&adapter->stats_update_task,
1097 mac_stats_task);
8199d3a7
CL		 1098
1099 pci_set_drvdata(pdev, netdev);
8199d3a7
CL		 1100 }
1101
1102 pi = &adapter->port[i];
1103 pi->dev = netdev;
1104 netif_carrier_off(netdev);
1105 netdev->irq = pdev->irq;
1106 netdev->if_port = i;
1107 netdev->mem_start = mmio_start;
1108 netdev->mem_end = mmio_start + mmio_len - 1;
c3ccc123 1109 netdev->ml_priv = adapter;
8199d3a7 1110 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
559fb51b
SB		 1111 netdev->features |= NETIF_F_LLTX;
1112
8199d3a7
CL		 1113 adapter->flags |= RX_CSUM_ENABLED | TCP_CSUM_CAPABLE;
1114 if (pci_using_dac)
1115 netdev->features |= NETIF_F_HIGHDMA;
1116 if (vlan_tso_capable(adapter)) {
8199d3a7
CL		 1117#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1118 adapter->flags |= VLAN_ACCEL_CAPABLE;
1119 netdev->features |=
1120 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8199d3a7 1121#endif
f1d3d38a
SH		 1122
1123 /* T204: disable TSO */
1124 if (!(is_T2(adapter)) || bi->port_number != 4) {
1125 adapter->flags |= TSO_CAPABLE;
1126 netdev->features |= NETIF_F_TSO;
1127 }
8199d3a7
CL		 1128 }
1129
80ff32b7 1130 netdev->netdev_ops = &cxgb_netdev_ops;
8199d3a7 1131 netdev->hard_header_len += (adapter->flags & TSO_CAPABLE) ?
f1d3d38a 1132 sizeof(struct cpl_tx_pkt_lso) : sizeof(struct cpl_tx_pkt);
80ff32b7 1133
bea3348e 1134 netif_napi_add(netdev, &adapter->napi, t1_poll, 64);
8199d3a7 1135
20578151 1136 SET_ETHTOOL_OPS(netdev, &t1_ethtool_ops);
8199d3a7
CL		 1137 }
1138
1139 if (t1_init_sw_modules(adapter, bi) < 0) {
1140 err = -ENODEV;
1141 goto out_free_dev;
1142 }
1143
1144 /*
1145 * The card is now ready to go. If any errors occur during device
1146 * registration we do not fail the whole card but rather proceed only
1147 * with the ports we manage to register successfully. However we must
1148 * register at least one net device.
1149 */
1150 for (i = 0; i < bi->port_number; ++i) {
1151 err = register_netdev(adapter->port[i].dev);
1152 if (err)
1153 CH_WARN("%s: cannot register net device %s, skipping\n",
1154 pci_name(pdev), adapter->port[i].dev->name);
1155 else {
1156 /*
1157 * Change the name we use for messages to the name of
1158 * the first successfully registered interface.
1159 */
1160 if (!adapter->registered_device_map)
1161 adapter->name = adapter->port[i].dev->name;
1162
20578151 1163 __set_bit(i, &adapter->registered_device_map);
8199d3a7
CL		 1164 }
1165 }
1166 if (!adapter->registered_device_map) {
1167 CH_ERR("%s: could not register any net devices\n",
1168 pci_name(pdev));
1169 goto out_release_adapter_res;
1170 }
1171
1172 printk(KERN_INFO "%s: %s (rev %d), %s %dMHz/%d-bit\n", adapter->name,
1173 bi->desc, adapter->params.chip_revision,
1174 adapter->params.pci.is_pcix ? "PCIX" : "PCI",
1175 adapter->params.pci.speed, adapter->params.pci.width);
f1d3d38a
SH		 1176
1177 /*
1178 * Set the T1B ASIC and memory clocks.
1179 */
1180 if (t1powersave)
1181 adapter->t1powersave = LCLOCK; /* HW default is powersave mode. */
1182 else
1183 adapter->t1powersave = HCLOCK;
1184 if (t1_is_T1B(adapter))
1185 t1_clock(adapter, t1powersave);
1186
8199d3a7
CL		 1187 return 0;
1188
356bd146 1189out_release_adapter_res:
8199d3a7 1190 t1_free_sw_modules(adapter);
356bd146 1191out_free_dev:
8199d3a7 1192 if (adapter) {
e487647a
SH		 1193 if (adapter->regs)
1194 iounmap(adapter->regs);
8199d3a7 1195 for (i = bi->port_number - 1; i >= 0; --i)
e487647a
SH		 1196 if (adapter->port[i].dev)
1197 free_netdev(adapter->port[i].dev);
8199d3a7
CL		 1198 }
1199 pci_release_regions(pdev);
356bd146 1200out_disable_pdev:
8199d3a7
CL		 1201 pci_disable_device(pdev);
1202 pci_set_drvdata(pdev, NULL);
1203 return err;
1204}
1205
f1d3d38a
SH		 1206static void bit_bang(struct adapter *adapter, int bitdata, int nbits)
1207{
1208 int data;
1209 int i;
1210 u32 val;
1211
1212 enum {
1213 S_CLOCK = 1 << 3,
1214 S_DATA = 1 << 4
1215 };
1216
1217 for (i = (nbits - 1); i > -1; i--) {
1218
1219 udelay(50);
1220
1221 data = ((bitdata >> i) & 0x1);
1222 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1223
1224 if (data)
1225 val |= S_DATA;
1226 else
1227 val &= ~S_DATA;
1228
1229 udelay(50);
1230
1231 /* Set SCLOCK low */
1232 val &= ~S_CLOCK;
1233 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1234
1235 udelay(50);
1236
1237 /* Write SCLOCK high */
1238 val |= S_CLOCK;
1239 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1240
1241 }
1242}
1243
1244static int t1_clock(struct adapter *adapter, int mode)
1245{
1246 u32 val;
1247 int M_CORE_VAL;
1248 int M_MEM_VAL;
1249
1250 enum {
356bd146
FR		 1251 M_CORE_BITS = 9,
1252 T_CORE_VAL = 0,
1253 T_CORE_BITS = 2,
1254 N_CORE_VAL = 0,
1255 N_CORE_BITS = 2,
1256 M_MEM_BITS = 9,
1257 T_MEM_VAL = 0,
1258 T_MEM_BITS = 2,
1259 N_MEM_VAL = 0,
1260 N_MEM_BITS = 2,
1261 NP_LOAD = 1 << 17,
1262 S_LOAD_MEM = 1 << 5,
1263 S_LOAD_CORE = 1 << 6,
1264 S_CLOCK = 1 << 3
f1d3d38a
SH		 1265 };
1266
1267 if (!t1_is_T1B(adapter))
1268 return -ENODEV; /* Can't re-clock this chip. */
1269
d7487421 1270 if (mode & 2)
f1d3d38a 1271 return 0; /* show current mode. */
f1d3d38a
SH		 1272
1273 if ((adapter->t1powersave & 1) == (mode & 1))
1274 return -EALREADY; /* ASIC already running in mode. */
1275
1276 if ((mode & 1) == HCLOCK) {
1277 M_CORE_VAL = 0x14;
1278 M_MEM_VAL = 0x18;
1279 adapter->t1powersave = HCLOCK; /* overclock */
1280 } else {
1281 M_CORE_VAL = 0xe;
1282 M_MEM_VAL = 0x10;
1283 adapter->t1powersave = LCLOCK; /* underclock */
1284 }
1285
1286 /* Don't interrupt this serial stream! */
1287 spin_lock(&adapter->tpi_lock);
1288
1289 /* Initialize for ASIC core */
1290 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1291 val |= NP_LOAD;
1292 udelay(50);
1293 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1294 udelay(50);
1295 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1296 val &= ~S_LOAD_CORE;
1297 val &= ~S_CLOCK;
1298 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1299 udelay(50);
1300
1301 /* Serial program the ASIC clock synthesizer */
1302 bit_bang(adapter, T_CORE_VAL, T_CORE_BITS);
1303 bit_bang(adapter, N_CORE_VAL, N_CORE_BITS);
1304 bit_bang(adapter, M_CORE_VAL, M_CORE_BITS);
1305 udelay(50);
1306
1307 /* Finish ASIC core */
1308 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1309 val |= S_LOAD_CORE;
1310 udelay(50);
1311 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1312 udelay(50);
1313 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1314 val &= ~S_LOAD_CORE;
1315 udelay(50);
1316 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1317 udelay(50);
1318
1319 /* Initialize for memory */
1320 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1321 val |= NP_LOAD;
1322 udelay(50);
1323 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1324 udelay(50);
1325 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1326 val &= ~S_LOAD_MEM;
1327 val &= ~S_CLOCK;
1328 udelay(50);
1329 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1330 udelay(50);
1331
1332 /* Serial program the memory clock synthesizer */
1333 bit_bang(adapter, T_MEM_VAL, T_MEM_BITS);
1334 bit_bang(adapter, N_MEM_VAL, N_MEM_BITS);
1335 bit_bang(adapter, M_MEM_VAL, M_MEM_BITS);
1336 udelay(50);
1337
1338 /* Finish memory */
1339 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1340 val |= S_LOAD_MEM;
1341 udelay(50);
1342 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1343 udelay(50);
1344 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1345 val &= ~S_LOAD_MEM;
1346 udelay(50);
1347 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1348
1349 spin_unlock(&adapter->tpi_lock);
1350
1351 return 0;
1352}
1353
8199d3a7
CL		 1354static inline void t1_sw_reset(struct pci_dev *pdev)
1355{
1356 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 3);
1357 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 0);
1358}
1359
1360static void __devexit remove_one(struct pci_dev *pdev)
1361{
1362 struct net_device *dev = pci_get_drvdata(pdev);
c3ccc123 1363 struct adapter *adapter = dev->ml_priv;
47cbe6f4 1364 int i;
8199d3a7 1365
47cbe6f4
FR		 1366 for_each_port(adapter, i) {
1367 if (test_bit(i, &adapter->registered_device_map))
1368 unregister_netdev(adapter->port[i].dev);
1369 }
8199d3a7 1370
47cbe6f4
FR		 1371 t1_free_sw_modules(adapter);
1372 iounmap(adapter->regs);
e487647a 1373
47cbe6f4
FR		 1374 while (--i >= 0) {
1375 if (adapter->port[i].dev)
1376 free_netdev(adapter->port[i].dev);
8199d3a7 1377 }
47cbe6f4
FR		 1378
1379 pci_release_regions(pdev);
1380 pci_disable_device(pdev);
1381 pci_set_drvdata(pdev, NULL);
1382 t1_sw_reset(pdev);
8199d3a7
CL		 1383}
1384
1385static struct pci_driver driver = {
559fb51b 1386 .name = DRV_NAME,
8199d3a7
CL		 1387 .id_table = t1_pci_tbl,
1388 .probe = init_one,
1389 .remove = __devexit_p(remove_one),
1390};
1391
1392static int __init t1_init_module(void)
1393{
29917620 1394 return pci_register_driver(&driver);
8199d3a7
CL		 1395}
1396
1397static void __exit t1_cleanup_module(void)
1398{
1399 pci_unregister_driver(&driver);
1400}
1401
1402module_init(t1_init_module);
1403module_exit(t1_cleanup_module);
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