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8199d3a7 CL |
1 | /***************************************************************************** |
2 | * * | |
3 | * File: sge.c * | |
559fb51b SB |
4 | * $Revision: 1.26 $ * |
5 | * $Date: 2005/06/21 18:29:48 $ * | |
8199d3a7 CL |
6 | * Description: * |
7 | * DMA engine. * | |
8 | * part of the Chelsio 10Gb Ethernet Driver. * | |
9 | * * | |
10 | * This program is free software; you can redistribute it and/or modify * | |
11 | * it under the terms of the GNU General Public License, version 2, as * | |
12 | * published by the Free Software Foundation. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License along * | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., * | |
16 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
17 | * * | |
18 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * | |
19 | * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * | |
20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * | |
21 | * * | |
22 | * http://www.chelsio.com * | |
23 | * * | |
24 | * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * | |
25 | * All rights reserved. * | |
26 | * * | |
27 | * Maintainers: maintainers@chelsio.com * | |
28 | * * | |
29 | * Authors: Dimitrios Michailidis <dm@chelsio.com> * | |
30 | * Tina Yang <tainay@chelsio.com> * | |
31 | * Felix Marti <felix@chelsio.com> * | |
32 | * Scott Bardone <sbardone@chelsio.com> * | |
33 | * Kurt Ottaway <kottaway@chelsio.com> * | |
34 | * Frank DiMambro <frank@chelsio.com> * | |
35 | * * | |
36 | * History: * | |
37 | * * | |
38 | ****************************************************************************/ | |
39 | ||
40 | #include "common.h" | |
41 | ||
8199d3a7 CL |
42 | #include <linux/types.h> |
43 | #include <linux/errno.h> | |
44 | #include <linux/pci.h> | |
f1d3d38a | 45 | #include <linux/ktime.h> |
8199d3a7 CL |
46 | #include <linux/netdevice.h> |
47 | #include <linux/etherdevice.h> | |
48 | #include <linux/if_vlan.h> | |
49 | #include <linux/skbuff.h> | |
50 | #include <linux/init.h> | |
51 | #include <linux/mm.h> | |
f1d3d38a | 52 | #include <linux/tcp.h> |
8199d3a7 CL |
53 | #include <linux/ip.h> |
54 | #include <linux/in.h> | |
55 | #include <linux/if_arp.h> | |
56 | ||
57 | #include "cpl5_cmd.h" | |
58 | #include "sge.h" | |
59 | #include "regs.h" | |
60 | #include "espi.h" | |
61 | ||
f1d3d38a SH |
62 | /* This belongs in if_ether.h */ |
63 | #define ETH_P_CPL5 0xf | |
8199d3a7 CL |
64 | |
65 | #define SGE_CMDQ_N 2 | |
66 | #define SGE_FREELQ_N 2 | |
559fb51b | 67 | #define SGE_CMDQ0_E_N 1024 |
8199d3a7 CL |
68 | #define SGE_CMDQ1_E_N 128 |
69 | #define SGE_FREEL_SIZE 4096 | |
70 | #define SGE_JUMBO_FREEL_SIZE 512 | |
71 | #define SGE_FREEL_REFILL_THRESH 16 | |
72 | #define SGE_RESPQ_E_N 1024 | |
559fb51b SB |
73 | #define SGE_INTRTIMER_NRES 1000 |
74 | #define SGE_RX_COPY_THRES 256 | |
8199d3a7 | 75 | #define SGE_RX_SM_BUF_SIZE 1536 |
f1d3d38a | 76 | #define SGE_TX_DESC_MAX_PLEN 16384 |
8199d3a7 | 77 | |
559fb51b SB |
78 | # define SGE_RX_DROP_THRES 2 |
79 | ||
80 | #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4) | |
81 | ||
82 | /* | |
83 | * Period of the TX buffer reclaim timer. This timer does not need to run | |
84 | * frequently as TX buffers are usually reclaimed by new TX packets. | |
85 | */ | |
86 | #define TX_RECLAIM_PERIOD (HZ / 4) | |
8199d3a7 | 87 | |
8199d3a7 | 88 | #ifndef NET_IP_ALIGN |
559fb51b | 89 | # define NET_IP_ALIGN 2 |
8199d3a7 CL |
90 | #endif |
91 | ||
559fb51b SB |
92 | #define M_CMD_LEN 0x7fffffff |
93 | #define V_CMD_LEN(v) (v) | |
94 | #define G_CMD_LEN(v) ((v) & M_CMD_LEN) | |
95 | #define V_CMD_GEN1(v) ((v) << 31) | |
96 | #define V_CMD_GEN2(v) (v) | |
97 | #define F_CMD_DATAVALID (1 << 1) | |
98 | #define F_CMD_SOP (1 << 2) | |
99 | #define V_CMD_EOP(v) ((v) << 3) | |
100 | ||
8199d3a7 | 101 | /* |
559fb51b | 102 | * Command queue, receive buffer list, and response queue descriptors. |
8199d3a7 CL |
103 | */ |
104 | #if defined(__BIG_ENDIAN_BITFIELD) | |
105 | struct cmdQ_e { | |
559fb51b SB |
106 | u32 addr_lo; |
107 | u32 len_gen; | |
108 | u32 flags; | |
109 | u32 addr_hi; | |
8199d3a7 CL |
110 | }; |
111 | ||
112 | struct freelQ_e { | |
559fb51b SB |
113 | u32 addr_lo; |
114 | u32 len_gen; | |
115 | u32 gen2; | |
116 | u32 addr_hi; | |
8199d3a7 CL |
117 | }; |
118 | ||
119 | struct respQ_e { | |
120 | u32 Qsleeping : 4; | |
121 | u32 Cmdq1CreditReturn : 5; | |
122 | u32 Cmdq1DmaComplete : 5; | |
123 | u32 Cmdq0CreditReturn : 5; | |
124 | u32 Cmdq0DmaComplete : 5; | |
125 | u32 FreelistQid : 2; | |
126 | u32 CreditValid : 1; | |
127 | u32 DataValid : 1; | |
128 | u32 Offload : 1; | |
129 | u32 Eop : 1; | |
130 | u32 Sop : 1; | |
131 | u32 GenerationBit : 1; | |
132 | u32 BufferLength; | |
133 | }; | |
8199d3a7 CL |
134 | #elif defined(__LITTLE_ENDIAN_BITFIELD) |
135 | struct cmdQ_e { | |
559fb51b SB |
136 | u32 len_gen; |
137 | u32 addr_lo; | |
138 | u32 addr_hi; | |
139 | u32 flags; | |
8199d3a7 CL |
140 | }; |
141 | ||
142 | struct freelQ_e { | |
559fb51b SB |
143 | u32 len_gen; |
144 | u32 addr_lo; | |
145 | u32 addr_hi; | |
146 | u32 gen2; | |
8199d3a7 CL |
147 | }; |
148 | ||
149 | struct respQ_e { | |
150 | u32 BufferLength; | |
151 | u32 GenerationBit : 1; | |
152 | u32 Sop : 1; | |
153 | u32 Eop : 1; | |
154 | u32 Offload : 1; | |
155 | u32 DataValid : 1; | |
156 | u32 CreditValid : 1; | |
157 | u32 FreelistQid : 2; | |
158 | u32 Cmdq0DmaComplete : 5; | |
159 | u32 Cmdq0CreditReturn : 5; | |
160 | u32 Cmdq1DmaComplete : 5; | |
161 | u32 Cmdq1CreditReturn : 5; | |
162 | u32 Qsleeping : 4; | |
163 | } ; | |
164 | #endif | |
165 | ||
166 | /* | |
167 | * SW Context Command and Freelist Queue Descriptors | |
168 | */ | |
169 | struct cmdQ_ce { | |
170 | struct sk_buff *skb; | |
171 | DECLARE_PCI_UNMAP_ADDR(dma_addr); | |
172 | DECLARE_PCI_UNMAP_LEN(dma_len); | |
8199d3a7 CL |
173 | }; |
174 | ||
175 | struct freelQ_ce { | |
176 | struct sk_buff *skb; | |
177 | DECLARE_PCI_UNMAP_ADDR(dma_addr); | |
178 | DECLARE_PCI_UNMAP_LEN(dma_len); | |
179 | }; | |
180 | ||
181 | /* | |
559fb51b | 182 | * SW command, freelist and response rings |
8199d3a7 CL |
183 | */ |
184 | struct cmdQ { | |
559fb51b SB |
185 | unsigned long status; /* HW DMA fetch status */ |
186 | unsigned int in_use; /* # of in-use command descriptors */ | |
187 | unsigned int size; /* # of descriptors */ | |
f1d3d38a SH |
188 | unsigned int processed; /* total # of descs HW has processed */ |
189 | unsigned int cleaned; /* total # of descs SW has reclaimed */ | |
190 | unsigned int stop_thres; /* SW TX queue suspend threshold */ | |
559fb51b SB |
191 | u16 pidx; /* producer index (SW) */ |
192 | u16 cidx; /* consumer index (HW) */ | |
193 | u8 genbit; /* current generation (=valid) bit */ | |
f1d3d38a | 194 | u8 sop; /* is next entry start of packet? */ |
559fb51b SB |
195 | struct cmdQ_e *entries; /* HW command descriptor Q */ |
196 | struct cmdQ_ce *centries; /* SW command context descriptor Q */ | |
559fb51b | 197 | dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ |
356bd146 | 198 | spinlock_t lock; /* Lock to protect cmdQ enqueuing */ |
8199d3a7 CL |
199 | }; |
200 | ||
201 | struct freelQ { | |
559fb51b SB |
202 | unsigned int credits; /* # of available RX buffers */ |
203 | unsigned int size; /* free list capacity */ | |
204 | u16 pidx; /* producer index (SW) */ | |
205 | u16 cidx; /* consumer index (HW) */ | |
8199d3a7 | 206 | u16 rx_buffer_size; /* Buffer size on this free list */ |
f1d3d38a SH |
207 | u16 dma_offset; /* DMA offset to align IP headers */ |
208 | u16 recycleq_idx; /* skb recycle q to use */ | |
559fb51b SB |
209 | u8 genbit; /* current generation (=valid) bit */ |
210 | struct freelQ_e *entries; /* HW freelist descriptor Q */ | |
211 | struct freelQ_ce *centries; /* SW freelist context descriptor Q */ | |
212 | dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */ | |
8199d3a7 CL |
213 | }; |
214 | ||
215 | struct respQ { | |
559fb51b SB |
216 | unsigned int credits; /* credits to be returned to SGE */ |
217 | unsigned int size; /* # of response Q descriptors */ | |
218 | u16 cidx; /* consumer index (SW) */ | |
219 | u8 genbit; /* current generation(=valid) bit */ | |
8199d3a7 | 220 | struct respQ_e *entries; /* HW response descriptor Q */ |
559fb51b SB |
221 | dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */ |
222 | }; | |
223 | ||
224 | /* Bit flags for cmdQ.status */ | |
225 | enum { | |
226 | CMDQ_STAT_RUNNING = 1, /* fetch engine is running */ | |
227 | CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ | |
8199d3a7 CL |
228 | }; |
229 | ||
f1d3d38a SH |
230 | /* T204 TX SW scheduler */ |
231 | ||
232 | /* Per T204 TX port */ | |
233 | struct sched_port { | |
234 | unsigned int avail; /* available bits - quota */ | |
235 | unsigned int drain_bits_per_1024ns; /* drain rate */ | |
236 | unsigned int speed; /* drain rate, mbps */ | |
237 | unsigned int mtu; /* mtu size */ | |
238 | struct sk_buff_head skbq; /* pending skbs */ | |
239 | }; | |
240 | ||
241 | /* Per T204 device */ | |
242 | struct sched { | |
243 | ktime_t last_updated; /* last time quotas were computed */ | |
356bd146 FR |
244 | unsigned int max_avail; /* max bits to be sent to any port */ |
245 | unsigned int port; /* port index (round robin ports) */ | |
246 | unsigned int num; /* num skbs in per port queues */ | |
f1d3d38a SH |
247 | struct sched_port p[MAX_NPORTS]; |
248 | struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */ | |
249 | }; | |
250 | static void restart_sched(unsigned long); | |
251 | ||
252 | ||
8199d3a7 CL |
253 | /* |
254 | * Main SGE data structure | |
255 | * | |
256 | * Interrupts are handled by a single CPU and it is likely that on a MP system | |
257 | * the application is migrated to another CPU. In that scenario, we try to | |
258 | * seperate the RX(in irq context) and TX state in order to decrease memory | |
259 | * contention. | |
260 | */ | |
261 | struct sge { | |
356bd146 | 262 | struct adapter *adapter; /* adapter backpointer */ |
559fb51b | 263 | struct net_device *netdev; /* netdevice backpointer */ |
356bd146 FR |
264 | struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */ |
265 | struct respQ respQ; /* response Q */ | |
559fb51b | 266 | unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */ |
8199d3a7 CL |
267 | unsigned int rx_pkt_pad; /* RX padding for L2 packets */ |
268 | unsigned int jumbo_fl; /* jumbo freelist Q index */ | |
559fb51b | 269 | unsigned int intrtimer_nres; /* no-resource interrupt timer */ |
f1d3d38a | 270 | unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ |
559fb51b SB |
271 | struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ |
272 | struct timer_list espibug_timer; | |
f1d3d38a SH |
273 | unsigned long espibug_timeout; |
274 | struct sk_buff *espibug_skb[MAX_NPORTS]; | |
559fb51b SB |
275 | u32 sge_control; /* shadow value of sge control reg */ |
276 | struct sge_intr_counts stats; | |
56f643c2 | 277 | struct sge_port_stats *port_stats[MAX_NPORTS]; |
f1d3d38a | 278 | struct sched *tx_sched; |
559fb51b | 279 | struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; |
8199d3a7 CL |
280 | }; |
281 | ||
f1d3d38a SH |
282 | /* |
283 | * stop tasklet and free all pending skb's | |
284 | */ | |
285 | static void tx_sched_stop(struct sge *sge) | |
286 | { | |
287 | struct sched *s = sge->tx_sched; | |
288 | int i; | |
289 | ||
290 | tasklet_kill(&s->sched_tsk); | |
291 | ||
292 | for (i = 0; i < MAX_NPORTS; i++) | |
293 | __skb_queue_purge(&s->p[s->port].skbq); | |
294 | } | |
295 | ||
296 | /* | |
297 | * t1_sched_update_parms() is called when the MTU or link speed changes. It | |
298 | * re-computes scheduler parameters to scope with the change. | |
299 | */ | |
300 | unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port, | |
301 | unsigned int mtu, unsigned int speed) | |
302 | { | |
303 | struct sched *s = sge->tx_sched; | |
304 | struct sched_port *p = &s->p[port]; | |
305 | unsigned int max_avail_segs; | |
306 | ||
307 | pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed); | |
308 | if (speed) | |
309 | p->speed = speed; | |
310 | if (mtu) | |
311 | p->mtu = mtu; | |
312 | ||
313 | if (speed || mtu) { | |
314 | unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40); | |
315 | do_div(drain, (p->mtu + 50) * 1000); | |
316 | p->drain_bits_per_1024ns = (unsigned int) drain; | |
317 | ||
318 | if (p->speed < 1000) | |
319 | p->drain_bits_per_1024ns = | |
320 | 90 * p->drain_bits_per_1024ns / 100; | |
321 | } | |
322 | ||
323 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) { | |
324 | p->drain_bits_per_1024ns -= 16; | |
325 | s->max_avail = max(4096U, p->mtu + 16 + 14 + 4); | |
326 | max_avail_segs = max(1U, 4096 / (p->mtu - 40)); | |
327 | } else { | |
328 | s->max_avail = 16384; | |
329 | max_avail_segs = max(1U, 9000 / (p->mtu - 40)); | |
330 | } | |
331 | ||
332 | pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u " | |
333 | "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu, | |
334 | p->speed, s->max_avail, max_avail_segs, | |
335 | p->drain_bits_per_1024ns); | |
336 | ||
337 | return max_avail_segs * (p->mtu - 40); | |
338 | } | |
339 | ||
340 | /* | |
341 | * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of | |
342 | * data that can be pushed per port. | |
343 | */ | |
344 | void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val) | |
345 | { | |
346 | struct sched *s = sge->tx_sched; | |
347 | unsigned int i; | |
348 | ||
349 | s->max_avail = val; | |
350 | for (i = 0; i < MAX_NPORTS; i++) | |
351 | t1_sched_update_parms(sge, i, 0, 0); | |
352 | } | |
353 | ||
354 | /* | |
355 | * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port | |
356 | * is draining. | |
357 | */ | |
358 | void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port, | |
359 | unsigned int val) | |
360 | { | |
361 | struct sched *s = sge->tx_sched; | |
362 | struct sched_port *p = &s->p[port]; | |
363 | p->drain_bits_per_1024ns = val * 1024 / 1000; | |
364 | t1_sched_update_parms(sge, port, 0, 0); | |
365 | } | |
366 | ||
367 | ||
368 | /* | |
369 | * get_clock() implements a ns clock (see ktime_get) | |
370 | */ | |
371 | static inline ktime_t get_clock(void) | |
372 | { | |
373 | struct timespec ts; | |
374 | ||
375 | ktime_get_ts(&ts); | |
376 | return timespec_to_ktime(ts); | |
377 | } | |
378 | ||
379 | /* | |
380 | * tx_sched_init() allocates resources and does basic initialization. | |
381 | */ | |
382 | static int tx_sched_init(struct sge *sge) | |
383 | { | |
384 | struct sched *s; | |
385 | int i; | |
386 | ||
387 | s = kzalloc(sizeof (struct sched), GFP_KERNEL); | |
388 | if (!s) | |
389 | return -ENOMEM; | |
390 | ||
391 | pr_debug("tx_sched_init\n"); | |
392 | tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge); | |
393 | sge->tx_sched = s; | |
394 | ||
395 | for (i = 0; i < MAX_NPORTS; i++) { | |
396 | skb_queue_head_init(&s->p[i].skbq); | |
397 | t1_sched_update_parms(sge, i, 1500, 1000); | |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | /* | |
404 | * sched_update_avail() computes the delta since the last time it was called | |
405 | * and updates the per port quota (number of bits that can be sent to the any | |
406 | * port). | |
407 | */ | |
408 | static inline int sched_update_avail(struct sge *sge) | |
409 | { | |
410 | struct sched *s = sge->tx_sched; | |
411 | ktime_t now = get_clock(); | |
412 | unsigned int i; | |
413 | long long delta_time_ns; | |
414 | ||
415 | delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated)); | |
416 | ||
417 | pr_debug("sched_update_avail delta=%lld\n", delta_time_ns); | |
418 | if (delta_time_ns < 15000) | |
419 | return 0; | |
420 | ||
421 | for (i = 0; i < MAX_NPORTS; i++) { | |
422 | struct sched_port *p = &s->p[i]; | |
423 | unsigned int delta_avail; | |
424 | ||
425 | delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13; | |
426 | p->avail = min(p->avail + delta_avail, s->max_avail); | |
427 | } | |
428 | ||
429 | s->last_updated = now; | |
430 | ||
431 | return 1; | |
432 | } | |
433 | ||
434 | /* | |
435 | * sched_skb() is called from two different places. In the tx path, any | |
436 | * packet generating load on an output port will call sched_skb() | |
437 | * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq | |
438 | * context (skb == NULL). | |
439 | * The scheduler only returns a skb (which will then be sent) if the | |
440 | * length of the skb is <= the current quota of the output port. | |
441 | */ | |
442 | static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb, | |
443 | unsigned int credits) | |
444 | { | |
445 | struct sched *s = sge->tx_sched; | |
446 | struct sk_buff_head *skbq; | |
447 | unsigned int i, len, update = 1; | |
448 | ||
449 | pr_debug("sched_skb %p\n", skb); | |
450 | if (!skb) { | |
451 | if (!s->num) | |
452 | return NULL; | |
453 | } else { | |
454 | skbq = &s->p[skb->dev->if_port].skbq; | |
455 | __skb_queue_tail(skbq, skb); | |
456 | s->num++; | |
457 | skb = NULL; | |
458 | } | |
459 | ||
460 | if (credits < MAX_SKB_FRAGS + 1) | |
461 | goto out; | |
462 | ||
356bd146 | 463 | again: |
f1d3d38a SH |
464 | for (i = 0; i < MAX_NPORTS; i++) { |
465 | s->port = ++s->port & (MAX_NPORTS - 1); | |
466 | skbq = &s->p[s->port].skbq; | |
467 | ||
468 | skb = skb_peek(skbq); | |
469 | ||
470 | if (!skb) | |
471 | continue; | |
472 | ||
473 | len = skb->len; | |
474 | if (len <= s->p[s->port].avail) { | |
475 | s->p[s->port].avail -= len; | |
476 | s->num--; | |
477 | __skb_unlink(skb, skbq); | |
478 | goto out; | |
479 | } | |
480 | skb = NULL; | |
481 | } | |
482 | ||
483 | if (update-- && sched_update_avail(sge)) | |
484 | goto again; | |
485 | ||
356bd146 FR |
486 | out: |
487 | /* If there are more pending skbs, we use the hardware to schedule us | |
f1d3d38a SH |
488 | * again. |
489 | */ | |
490 | if (s->num && !skb) { | |
491 | struct cmdQ *q = &sge->cmdQ[0]; | |
492 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
493 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
494 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
495 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
496 | } | |
497 | } | |
498 | pr_debug("sched_skb ret %p\n", skb); | |
499 | ||
500 | return skb; | |
501 | } | |
502 | ||
8199d3a7 CL |
503 | /* |
504 | * PIO to indicate that memory mapped Q contains valid descriptor(s). | |
505 | */ | |
559fb51b | 506 | static inline void doorbell_pio(struct adapter *adapter, u32 val) |
8199d3a7 CL |
507 | { |
508 | wmb(); | |
559fb51b | 509 | writel(val, adapter->regs + A_SG_DOORBELL); |
8199d3a7 CL |
510 | } |
511 | ||
512 | /* | |
513 | * Frees all RX buffers on the freelist Q. The caller must make sure that | |
514 | * the SGE is turned off before calling this function. | |
515 | */ | |
559fb51b | 516 | static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q) |
8199d3a7 | 517 | { |
559fb51b | 518 | unsigned int cidx = q->cidx; |
8199d3a7 | 519 | |
559fb51b SB |
520 | while (q->credits--) { |
521 | struct freelQ_ce *ce = &q->centries[cidx]; | |
8199d3a7 CL |
522 | |
523 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), | |
524 | pci_unmap_len(ce, dma_len), | |
525 | PCI_DMA_FROMDEVICE); | |
526 | dev_kfree_skb(ce->skb); | |
527 | ce->skb = NULL; | |
559fb51b | 528 | if (++cidx == q->size) |
8199d3a7 CL |
529 | cidx = 0; |
530 | } | |
531 | } | |
532 | ||
533 | /* | |
534 | * Free RX free list and response queue resources. | |
535 | */ | |
536 | static void free_rx_resources(struct sge *sge) | |
537 | { | |
538 | struct pci_dev *pdev = sge->adapter->pdev; | |
539 | unsigned int size, i; | |
540 | ||
541 | if (sge->respQ.entries) { | |
559fb51b | 542 | size = sizeof(struct respQ_e) * sge->respQ.size; |
8199d3a7 CL |
543 | pci_free_consistent(pdev, size, sge->respQ.entries, |
544 | sge->respQ.dma_addr); | |
545 | } | |
546 | ||
547 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b | 548 | struct freelQ *q = &sge->freelQ[i]; |
8199d3a7 | 549 | |
559fb51b SB |
550 | if (q->centries) { |
551 | free_freelQ_buffers(pdev, q); | |
552 | kfree(q->centries); | |
8199d3a7 | 553 | } |
559fb51b SB |
554 | if (q->entries) { |
555 | size = sizeof(struct freelQ_e) * q->size; | |
556 | pci_free_consistent(pdev, size, q->entries, | |
557 | q->dma_addr); | |
8199d3a7 CL |
558 | } |
559 | } | |
560 | } | |
561 | ||
562 | /* | |
563 | * Allocates basic RX resources, consisting of memory mapped freelist Qs and a | |
559fb51b | 564 | * response queue. |
8199d3a7 CL |
565 | */ |
566 | static int alloc_rx_resources(struct sge *sge, struct sge_params *p) | |
567 | { | |
568 | struct pci_dev *pdev = sge->adapter->pdev; | |
569 | unsigned int size, i; | |
570 | ||
571 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b SB |
572 | struct freelQ *q = &sge->freelQ[i]; |
573 | ||
574 | q->genbit = 1; | |
575 | q->size = p->freelQ_size[i]; | |
576 | q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN; | |
577 | size = sizeof(struct freelQ_e) * q->size; | |
578 | q->entries = (struct freelQ_e *) | |
579 | pci_alloc_consistent(pdev, size, &q->dma_addr); | |
580 | if (!q->entries) | |
8199d3a7 | 581 | goto err_no_mem; |
559fb51b SB |
582 | memset(q->entries, 0, size); |
583 | size = sizeof(struct freelQ_ce) * q->size; | |
cbee9f91 | 584 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 585 | if (!q->centries) |
8199d3a7 CL |
586 | goto err_no_mem; |
587 | } | |
588 | ||
589 | /* | |
590 | * Calculate the buffer sizes for the two free lists. FL0 accommodates | |
591 | * regular sized Ethernet frames, FL1 is sized not to exceed 16K, | |
592 | * including all the sk_buff overhead. | |
593 | * | |
594 | * Note: For T2 FL0 and FL1 are reversed. | |
595 | */ | |
596 | sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + | |
597 | sizeof(struct cpl_rx_data) + | |
598 | sge->freelQ[!sge->jumbo_fl].dma_offset; | |
f1d3d38a SH |
599 | |
600 | size = (16 * 1024) - | |
601 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
602 | ||
603 | sge->freelQ[sge->jumbo_fl].rx_buffer_size = size; | |
8199d3a7 | 604 | |
559fb51b SB |
605 | /* |
606 | * Setup which skb recycle Q should be used when recycling buffers from | |
607 | * each free list. | |
608 | */ | |
609 | sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0; | |
610 | sge->freelQ[sge->jumbo_fl].recycleq_idx = 1; | |
611 | ||
8199d3a7 | 612 | sge->respQ.genbit = 1; |
559fb51b SB |
613 | sge->respQ.size = SGE_RESPQ_E_N; |
614 | sge->respQ.credits = 0; | |
615 | size = sizeof(struct respQ_e) * sge->respQ.size; | |
8199d3a7 CL |
616 | sge->respQ.entries = (struct respQ_e *) |
617 | pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr); | |
618 | if (!sge->respQ.entries) | |
619 | goto err_no_mem; | |
620 | memset(sge->respQ.entries, 0, size); | |
621 | return 0; | |
622 | ||
623 | err_no_mem: | |
624 | free_rx_resources(sge); | |
625 | return -ENOMEM; | |
626 | } | |
627 | ||
628 | /* | |
559fb51b | 629 | * Reclaims n TX descriptors and frees the buffers associated with them. |
8199d3a7 | 630 | */ |
559fb51b | 631 | static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n) |
8199d3a7 | 632 | { |
559fb51b | 633 | struct cmdQ_ce *ce; |
8199d3a7 | 634 | struct pci_dev *pdev = sge->adapter->pdev; |
559fb51b | 635 | unsigned int cidx = q->cidx; |
8199d3a7 | 636 | |
559fb51b SB |
637 | q->in_use -= n; |
638 | ce = &q->centries[cidx]; | |
639 | while (n--) { | |
f1d3d38a SH |
640 | if (q->sop) { |
641 | if (likely(pci_unmap_len(ce, dma_len))) { | |
642 | pci_unmap_single(pdev, | |
643 | pci_unmap_addr(ce, dma_addr), | |
356bd146 | 644 | pci_unmap_len(ce, dma_len), |
f1d3d38a SH |
645 | PCI_DMA_TODEVICE); |
646 | q->sop = 0; | |
647 | } | |
648 | } else { | |
649 | if (likely(pci_unmap_len(ce, dma_len))) { | |
650 | pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr), | |
356bd146 | 651 | pci_unmap_len(ce, dma_len), |
f1d3d38a SH |
652 | PCI_DMA_TODEVICE); |
653 | } | |
654 | } | |
559fb51b | 655 | if (ce->skb) { |
f1d3d38a | 656 | dev_kfree_skb_any(ce->skb); |
559fb51b SB |
657 | q->sop = 1; |
658 | } | |
8199d3a7 | 659 | ce++; |
559fb51b | 660 | if (++cidx == q->size) { |
8199d3a7 | 661 | cidx = 0; |
559fb51b | 662 | ce = q->centries; |
8199d3a7 CL |
663 | } |
664 | } | |
559fb51b | 665 | q->cidx = cidx; |
8199d3a7 CL |
666 | } |
667 | ||
668 | /* | |
669 | * Free TX resources. | |
670 | * | |
671 | * Assumes that SGE is stopped and all interrupts are disabled. | |
672 | */ | |
673 | static void free_tx_resources(struct sge *sge) | |
674 | { | |
675 | struct pci_dev *pdev = sge->adapter->pdev; | |
676 | unsigned int size, i; | |
677 | ||
678 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b | 679 | struct cmdQ *q = &sge->cmdQ[i]; |
8199d3a7 | 680 | |
559fb51b SB |
681 | if (q->centries) { |
682 | if (q->in_use) | |
683 | free_cmdQ_buffers(sge, q, q->in_use); | |
684 | kfree(q->centries); | |
8199d3a7 | 685 | } |
559fb51b SB |
686 | if (q->entries) { |
687 | size = sizeof(struct cmdQ_e) * q->size; | |
688 | pci_free_consistent(pdev, size, q->entries, | |
689 | q->dma_addr); | |
8199d3a7 CL |
690 | } |
691 | } | |
692 | } | |
693 | ||
694 | /* | |
695 | * Allocates basic TX resources, consisting of memory mapped command Qs. | |
696 | */ | |
697 | static int alloc_tx_resources(struct sge *sge, struct sge_params *p) | |
698 | { | |
699 | struct pci_dev *pdev = sge->adapter->pdev; | |
700 | unsigned int size, i; | |
701 | ||
702 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b SB |
703 | struct cmdQ *q = &sge->cmdQ[i]; |
704 | ||
705 | q->genbit = 1; | |
706 | q->sop = 1; | |
707 | q->size = p->cmdQ_size[i]; | |
708 | q->in_use = 0; | |
709 | q->status = 0; | |
710 | q->processed = q->cleaned = 0; | |
711 | q->stop_thres = 0; | |
712 | spin_lock_init(&q->lock); | |
713 | size = sizeof(struct cmdQ_e) * q->size; | |
714 | q->entries = (struct cmdQ_e *) | |
715 | pci_alloc_consistent(pdev, size, &q->dma_addr); | |
716 | if (!q->entries) | |
8199d3a7 | 717 | goto err_no_mem; |
559fb51b SB |
718 | memset(q->entries, 0, size); |
719 | size = sizeof(struct cmdQ_ce) * q->size; | |
cbee9f91 | 720 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 721 | if (!q->centries) |
8199d3a7 CL |
722 | goto err_no_mem; |
723 | } | |
724 | ||
559fb51b SB |
725 | /* |
726 | * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE | |
727 | * only. For queue 0 set the stop threshold so we can handle one more | |
728 | * packet from each port, plus reserve an additional 24 entries for | |
729 | * Ethernet packets only. Queue 1 never suspends nor do we reserve | |
730 | * space for Ethernet packets. | |
731 | */ | |
732 | sge->cmdQ[0].stop_thres = sge->adapter->params.nports * | |
733 | (MAX_SKB_FRAGS + 1); | |
8199d3a7 CL |
734 | return 0; |
735 | ||
736 | err_no_mem: | |
737 | free_tx_resources(sge); | |
738 | return -ENOMEM; | |
739 | } | |
740 | ||
741 | static inline void setup_ring_params(struct adapter *adapter, u64 addr, | |
742 | u32 size, int base_reg_lo, | |
743 | int base_reg_hi, int size_reg) | |
744 | { | |
559fb51b SB |
745 | writel((u32)addr, adapter->regs + base_reg_lo); |
746 | writel(addr >> 32, adapter->regs + base_reg_hi); | |
747 | writel(size, adapter->regs + size_reg); | |
8199d3a7 CL |
748 | } |
749 | ||
750 | /* | |
751 | * Enable/disable VLAN acceleration. | |
752 | */ | |
753 | void t1_set_vlan_accel(struct adapter *adapter, int on_off) | |
754 | { | |
755 | struct sge *sge = adapter->sge; | |
756 | ||
757 | sge->sge_control &= ~F_VLAN_XTRACT; | |
758 | if (on_off) | |
759 | sge->sge_control |= F_VLAN_XTRACT; | |
760 | if (adapter->open_device_map) { | |
559fb51b | 761 | writel(sge->sge_control, adapter->regs + A_SG_CONTROL); |
f1d3d38a | 762 | readl(adapter->regs + A_SG_CONTROL); /* flush */ |
8199d3a7 CL |
763 | } |
764 | } | |
765 | ||
8199d3a7 CL |
766 | /* |
767 | * Programs the various SGE registers. However, the engine is not yet enabled, | |
768 | * but sge->sge_control is setup and ready to go. | |
769 | */ | |
770 | static void configure_sge(struct sge *sge, struct sge_params *p) | |
771 | { | |
772 | struct adapter *ap = sge->adapter; | |
356bd146 | 773 | |
559fb51b SB |
774 | writel(0, ap->regs + A_SG_CONTROL); |
775 | setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, | |
8199d3a7 | 776 | A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE); |
559fb51b | 777 | setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size, |
8199d3a7 CL |
778 | A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE); |
779 | setup_ring_params(ap, sge->freelQ[0].dma_addr, | |
559fb51b | 780 | sge->freelQ[0].size, A_SG_FL0BASELWR, |
8199d3a7 CL |
781 | A_SG_FL0BASEUPR, A_SG_FL0SIZE); |
782 | setup_ring_params(ap, sge->freelQ[1].dma_addr, | |
559fb51b | 783 | sge->freelQ[1].size, A_SG_FL1BASELWR, |
8199d3a7 CL |
784 | A_SG_FL1BASEUPR, A_SG_FL1SIZE); |
785 | ||
786 | /* The threshold comparison uses <. */ | |
559fb51b | 787 | writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD); |
8199d3a7 | 788 | |
559fb51b SB |
789 | setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size, |
790 | A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE); | |
791 | writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT); | |
8199d3a7 CL |
792 | |
793 | sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | | |
794 | F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | | |
795 | V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | | |
796 | V_RX_PKT_OFFSET(sge->rx_pkt_pad); | |
797 | ||
798 | #if defined(__BIG_ENDIAN_BITFIELD) | |
799 | sge->sge_control |= F_ENABLE_BIG_ENDIAN; | |
800 | #endif | |
801 | ||
559fb51b SB |
802 | /* Initialize no-resource timer */ |
803 | sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap); | |
804 | ||
805 | t1_sge_set_coalesce_params(sge, p); | |
8199d3a7 CL |
806 | } |
807 | ||
808 | /* | |
809 | * Return the payload capacity of the jumbo free-list buffers. | |
810 | */ | |
811 | static inline unsigned int jumbo_payload_capacity(const struct sge *sge) | |
812 | { | |
813 | return sge->freelQ[sge->jumbo_fl].rx_buffer_size - | |
559fb51b SB |
814 | sge->freelQ[sge->jumbo_fl].dma_offset - |
815 | sizeof(struct cpl_rx_data); | |
8199d3a7 CL |
816 | } |
817 | ||
818 | /* | |
819 | * Frees all SGE related resources and the sge structure itself | |
820 | */ | |
821 | void t1_sge_destroy(struct sge *sge) | |
822 | { | |
56f643c2 SH |
823 | int i; |
824 | ||
825 | for_each_port(sge->adapter, i) | |
826 | free_percpu(sge->port_stats[i]); | |
827 | ||
f1d3d38a | 828 | kfree(sge->tx_sched); |
8199d3a7 CL |
829 | free_tx_resources(sge); |
830 | free_rx_resources(sge); | |
831 | kfree(sge); | |
832 | } | |
833 | ||
834 | /* | |
835 | * Allocates new RX buffers on the freelist Q (and tracks them on the freelist | |
836 | * context Q) until the Q is full or alloc_skb fails. | |
837 | * | |
838 | * It is possible that the generation bits already match, indicating that the | |
839 | * buffer is already valid and nothing needs to be done. This happens when we | |
840 | * copied a received buffer into a new sk_buff during the interrupt processing. | |
841 | * | |
842 | * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad), | |
843 | * we specify a RX_OFFSET in order to make sure that the IP header is 4B | |
844 | * aligned. | |
845 | */ | |
559fb51b | 846 | static void refill_free_list(struct sge *sge, struct freelQ *q) |
8199d3a7 CL |
847 | { |
848 | struct pci_dev *pdev = sge->adapter->pdev; | |
559fb51b SB |
849 | struct freelQ_ce *ce = &q->centries[q->pidx]; |
850 | struct freelQ_e *e = &q->entries[q->pidx]; | |
851 | unsigned int dma_len = q->rx_buffer_size - q->dma_offset; | |
8199d3a7 | 852 | |
559fb51b SB |
853 | while (q->credits < q->size) { |
854 | struct sk_buff *skb; | |
855 | dma_addr_t mapping; | |
8199d3a7 | 856 | |
559fb51b SB |
857 | skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC); |
858 | if (!skb) | |
859 | break; | |
860 | ||
861 | skb_reserve(skb, q->dma_offset); | |
862 | mapping = pci_map_single(pdev, skb->data, dma_len, | |
863 | PCI_DMA_FROMDEVICE); | |
864 | ce->skb = skb; | |
865 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
866 | pci_unmap_len_set(ce, dma_len, dma_len); | |
867 | e->addr_lo = (u32)mapping; | |
868 | e->addr_hi = (u64)mapping >> 32; | |
869 | e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit); | |
870 | wmb(); | |
871 | e->gen2 = V_CMD_GEN2(q->genbit); | |
8199d3a7 CL |
872 | |
873 | e++; | |
874 | ce++; | |
559fb51b SB |
875 | if (++q->pidx == q->size) { |
876 | q->pidx = 0; | |
877 | q->genbit ^= 1; | |
878 | ce = q->centries; | |
879 | e = q->entries; | |
8199d3a7 | 880 | } |
559fb51b | 881 | q->credits++; |
8199d3a7 | 882 | } |
8199d3a7 CL |
883 | } |
884 | ||
885 | /* | |
559fb51b SB |
886 | * Calls refill_free_list for both free lists. If we cannot fill at least 1/4 |
887 | * of both rings, we go into 'few interrupt mode' in order to give the system | |
888 | * time to free up resources. | |
8199d3a7 CL |
889 | */ |
890 | static void freelQs_empty(struct sge *sge) | |
891 | { | |
559fb51b SB |
892 | struct adapter *adapter = sge->adapter; |
893 | u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
894 | u32 irqholdoff_reg; |
895 | ||
896 | refill_free_list(sge, &sge->freelQ[0]); | |
897 | refill_free_list(sge, &sge->freelQ[1]); | |
898 | ||
559fb51b SB |
899 | if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) && |
900 | sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) { | |
8199d3a7 | 901 | irq_reg |= F_FL_EXHAUSTED; |
559fb51b | 902 | irqholdoff_reg = sge->fixed_intrtimer; |
8199d3a7 CL |
903 | } else { |
904 | /* Clear the F_FL_EXHAUSTED interrupts for now */ | |
905 | irq_reg &= ~F_FL_EXHAUSTED; | |
906 | irqholdoff_reg = sge->intrtimer_nres; | |
907 | } | |
559fb51b SB |
908 | writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER); |
909 | writel(irq_reg, adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
910 | |
911 | /* We reenable the Qs to force a freelist GTS interrupt later */ | |
559fb51b | 912 | doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE); |
8199d3a7 CL |
913 | } |
914 | ||
915 | #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA) | |
916 | #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
917 | #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \ | |
918 | F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
919 | ||
920 | /* | |
921 | * Disable SGE Interrupts | |
922 | */ | |
923 | void t1_sge_intr_disable(struct sge *sge) | |
924 | { | |
559fb51b | 925 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 | 926 | |
559fb51b SB |
927 | writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); |
928 | writel(0, sge->adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
929 | } |
930 | ||
931 | /* | |
932 | * Enable SGE interrupts. | |
933 | */ | |
934 | void t1_sge_intr_enable(struct sge *sge) | |
935 | { | |
936 | u32 en = SGE_INT_ENABLE; | |
559fb51b | 937 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 CL |
938 | |
939 | if (sge->adapter->flags & TSO_CAPABLE) | |
940 | en &= ~F_PACKET_TOO_BIG; | |
559fb51b SB |
941 | writel(en, sge->adapter->regs + A_SG_INT_ENABLE); |
942 | writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); | |
8199d3a7 CL |
943 | } |
944 | ||
945 | /* | |
946 | * Clear SGE interrupts. | |
947 | */ | |
948 | void t1_sge_intr_clear(struct sge *sge) | |
949 | { | |
559fb51b SB |
950 | writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); |
951 | writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE); | |
8199d3a7 CL |
952 | } |
953 | ||
954 | /* | |
955 | * SGE 'Error' interrupt handler | |
956 | */ | |
957 | int t1_sge_intr_error_handler(struct sge *sge) | |
958 | { | |
959 | struct adapter *adapter = sge->adapter; | |
559fb51b | 960 | u32 cause = readl(adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 CL |
961 | |
962 | if (adapter->flags & TSO_CAPABLE) | |
963 | cause &= ~F_PACKET_TOO_BIG; | |
964 | if (cause & F_RESPQ_EXHAUSTED) | |
559fb51b | 965 | sge->stats.respQ_empty++; |
8199d3a7 | 966 | if (cause & F_RESPQ_OVERFLOW) { |
559fb51b | 967 | sge->stats.respQ_overflow++; |
8199d3a7 CL |
968 | CH_ALERT("%s: SGE response queue overflow\n", |
969 | adapter->name); | |
970 | } | |
971 | if (cause & F_FL_EXHAUSTED) { | |
559fb51b | 972 | sge->stats.freelistQ_empty++; |
8199d3a7 CL |
973 | freelQs_empty(sge); |
974 | } | |
975 | if (cause & F_PACKET_TOO_BIG) { | |
559fb51b | 976 | sge->stats.pkt_too_big++; |
8199d3a7 CL |
977 | CH_ALERT("%s: SGE max packet size exceeded\n", |
978 | adapter->name); | |
979 | } | |
980 | if (cause & F_PACKET_MISMATCH) { | |
559fb51b | 981 | sge->stats.pkt_mismatch++; |
8199d3a7 CL |
982 | CH_ALERT("%s: SGE packet mismatch\n", adapter->name); |
983 | } | |
984 | if (cause & SGE_INT_FATAL) | |
985 | t1_fatal_err(adapter); | |
986 | ||
559fb51b | 987 | writel(cause, adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 CL |
988 | return 0; |
989 | } | |
990 | ||
56f643c2 | 991 | const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge) |
559fb51b SB |
992 | { |
993 | return &sge->stats; | |
994 | } | |
995 | ||
56f643c2 SH |
996 | void t1_sge_get_port_stats(const struct sge *sge, int port, |
997 | struct sge_port_stats *ss) | |
559fb51b | 998 | { |
56f643c2 SH |
999 | int cpu; |
1000 | ||
1001 | memset(ss, 0, sizeof(*ss)); | |
1002 | for_each_possible_cpu(cpu) { | |
1003 | struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu); | |
1004 | ||
1005 | ss->rx_packets += st->rx_packets; | |
1006 | ss->rx_cso_good += st->rx_cso_good; | |
1007 | ss->tx_packets += st->tx_packets; | |
1008 | ss->tx_cso += st->tx_cso; | |
1009 | ss->tx_tso += st->tx_tso; | |
1010 | ss->vlan_xtract += st->vlan_xtract; | |
1011 | ss->vlan_insert += st->vlan_insert; | |
1012 | } | |
559fb51b SB |
1013 | } |
1014 | ||
1015 | /** | |
1016 | * recycle_fl_buf - recycle a free list buffer | |
1017 | * @fl: the free list | |
1018 | * @idx: index of buffer to recycle | |
8199d3a7 | 1019 | * |
559fb51b SB |
1020 | * Recycles the specified buffer on the given free list by adding it at |
1021 | * the next available slot on the list. | |
8199d3a7 | 1022 | */ |
559fb51b | 1023 | static void recycle_fl_buf(struct freelQ *fl, int idx) |
8199d3a7 | 1024 | { |
559fb51b SB |
1025 | struct freelQ_e *from = &fl->entries[idx]; |
1026 | struct freelQ_e *to = &fl->entries[fl->pidx]; | |
8199d3a7 | 1027 | |
559fb51b SB |
1028 | fl->centries[fl->pidx] = fl->centries[idx]; |
1029 | to->addr_lo = from->addr_lo; | |
1030 | to->addr_hi = from->addr_hi; | |
1031 | to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit); | |
1032 | wmb(); | |
1033 | to->gen2 = V_CMD_GEN2(fl->genbit); | |
1034 | fl->credits++; | |
8199d3a7 | 1035 | |
559fb51b SB |
1036 | if (++fl->pidx == fl->size) { |
1037 | fl->pidx = 0; | |
1038 | fl->genbit ^= 1; | |
8199d3a7 | 1039 | } |
559fb51b | 1040 | } |
8199d3a7 | 1041 | |
559fb51b SB |
1042 | /** |
1043 | * get_packet - return the next ingress packet buffer | |
1044 | * @pdev: the PCI device that received the packet | |
1045 | * @fl: the SGE free list holding the packet | |
1046 | * @len: the actual packet length, excluding any SGE padding | |
1047 | * @dma_pad: padding at beginning of buffer left by SGE DMA | |
1048 | * @skb_pad: padding to be used if the packet is copied | |
1049 | * @copy_thres: length threshold under which a packet should be copied | |
1050 | * @drop_thres: # of remaining buffers before we start dropping packets | |
1051 | * | |
1052 | * Get the next packet from a free list and complete setup of the | |
1053 | * sk_buff. If the packet is small we make a copy and recycle the | |
1054 | * original buffer, otherwise we use the original buffer itself. If a | |
1055 | * positive drop threshold is supplied packets are dropped and their | |
1056 | * buffers recycled if (a) the number of remaining buffers is under the | |
1057 | * threshold and the packet is too big to copy, or (b) the packet should | |
1058 | * be copied but there is no memory for the copy. | |
1059 | */ | |
1060 | static inline struct sk_buff *get_packet(struct pci_dev *pdev, | |
1061 | struct freelQ *fl, unsigned int len, | |
1062 | int dma_pad, int skb_pad, | |
1063 | unsigned int copy_thres, | |
1064 | unsigned int drop_thres) | |
1065 | { | |
1066 | struct sk_buff *skb; | |
1067 | struct freelQ_ce *ce = &fl->centries[fl->cidx]; | |
1068 | ||
1069 | if (len < copy_thres) { | |
1070 | skb = alloc_skb(len + skb_pad, GFP_ATOMIC); | |
1071 | if (likely(skb != NULL)) { | |
1072 | skb_reserve(skb, skb_pad); | |
1073 | skb_put(skb, len); | |
1074 | pci_dma_sync_single_for_cpu(pdev, | |
1075 | pci_unmap_addr(ce, dma_addr), | |
356bd146 | 1076 | pci_unmap_len(ce, dma_len), |
559fb51b SB |
1077 | PCI_DMA_FROMDEVICE); |
1078 | memcpy(skb->data, ce->skb->data + dma_pad, len); | |
1079 | pci_dma_sync_single_for_device(pdev, | |
1080 | pci_unmap_addr(ce, dma_addr), | |
356bd146 | 1081 | pci_unmap_len(ce, dma_len), |
559fb51b SB |
1082 | PCI_DMA_FROMDEVICE); |
1083 | } else if (!drop_thres) | |
1084 | goto use_orig_buf; | |
8199d3a7 | 1085 | |
559fb51b SB |
1086 | recycle_fl_buf(fl, fl->cidx); |
1087 | return skb; | |
8199d3a7 CL |
1088 | } |
1089 | ||
559fb51b SB |
1090 | if (fl->credits < drop_thres) { |
1091 | recycle_fl_buf(fl, fl->cidx); | |
1092 | return NULL; | |
1093 | } | |
8199d3a7 | 1094 | |
559fb51b SB |
1095 | use_orig_buf: |
1096 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), | |
1097 | pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
1098 | skb = ce->skb; | |
1099 | skb_reserve(skb, dma_pad); | |
1100 | skb_put(skb, len); | |
1101 | return skb; | |
1102 | } | |
8199d3a7 | 1103 | |
559fb51b SB |
1104 | /** |
1105 | * unexpected_offload - handle an unexpected offload packet | |
1106 | * @adapter: the adapter | |
1107 | * @fl: the free list that received the packet | |
1108 | * | |
1109 | * Called when we receive an unexpected offload packet (e.g., the TOE | |
1110 | * function is disabled or the card is a NIC). Prints a message and | |
1111 | * recycles the buffer. | |
1112 | */ | |
1113 | static void unexpected_offload(struct adapter *adapter, struct freelQ *fl) | |
1114 | { | |
1115 | struct freelQ_ce *ce = &fl->centries[fl->cidx]; | |
1116 | struct sk_buff *skb = ce->skb; | |
1117 | ||
1118 | pci_dma_sync_single_for_cpu(adapter->pdev, pci_unmap_addr(ce, dma_addr), | |
1119 | pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
1120 | CH_ERR("%s: unexpected offload packet, cmd %u\n", | |
1121 | adapter->name, *skb->data); | |
1122 | recycle_fl_buf(fl, fl->cidx); | |
8199d3a7 CL |
1123 | } |
1124 | ||
f1d3d38a SH |
1125 | /* |
1126 | * T1/T2 SGE limits the maximum DMA size per TX descriptor to | |
1127 | * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the | |
1128 | * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner. | |
1129 | * Note that the *_large_page_tx_descs stuff will be optimized out when | |
1130 | * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN. | |
1131 | * | |
1132 | * compute_large_page_descs() computes how many additional descriptors are | |
1133 | * required to break down the stack's request. | |
1134 | */ | |
1135 | static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb) | |
1136 | { | |
1137 | unsigned int count = 0; | |
356bd146 | 1138 | |
f1d3d38a SH |
1139 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { |
1140 | unsigned int nfrags = skb_shinfo(skb)->nr_frags; | |
1141 | unsigned int i, len = skb->len - skb->data_len; | |
1142 | while (len > SGE_TX_DESC_MAX_PLEN) { | |
1143 | count++; | |
1144 | len -= SGE_TX_DESC_MAX_PLEN; | |
1145 | } | |
1146 | for (i = 0; nfrags--; i++) { | |
1147 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1148 | len = frag->size; | |
1149 | while (len > SGE_TX_DESC_MAX_PLEN) { | |
1150 | count++; | |
1151 | len -= SGE_TX_DESC_MAX_PLEN; | |
1152 | } | |
1153 | } | |
1154 | } | |
1155 | return count; | |
1156 | } | |
1157 | ||
1158 | /* | |
1159 | * Write a cmdQ entry. | |
1160 | * | |
1161 | * Since this function writes the 'flags' field, it must not be used to | |
1162 | * write the first cmdQ entry. | |
1163 | */ | |
1164 | static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping, | |
1165 | unsigned int len, unsigned int gen, | |
1166 | unsigned int eop) | |
1167 | { | |
1168 | if (unlikely(len > SGE_TX_DESC_MAX_PLEN)) | |
1169 | BUG(); | |
1170 | e->addr_lo = (u32)mapping; | |
1171 | e->addr_hi = (u64)mapping >> 32; | |
1172 | e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen); | |
1173 | e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen); | |
1174 | } | |
1175 | ||
1176 | /* | |
1177 | * See comment for previous function. | |
1178 | * | |
1179 | * write_tx_descs_large_page() writes additional SGE tx descriptors if | |
1180 | * *desc_len exceeds HW's capability. | |
1181 | */ | |
1182 | static inline unsigned int write_large_page_tx_descs(unsigned int pidx, | |
1183 | struct cmdQ_e **e, | |
1184 | struct cmdQ_ce **ce, | |
1185 | unsigned int *gen, | |
1186 | dma_addr_t *desc_mapping, | |
1187 | unsigned int *desc_len, | |
1188 | unsigned int nfrags, | |
1189 | struct cmdQ *q) | |
1190 | { | |
1191 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { | |
1192 | struct cmdQ_e *e1 = *e; | |
1193 | struct cmdQ_ce *ce1 = *ce; | |
1194 | ||
1195 | while (*desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1196 | *desc_len -= SGE_TX_DESC_MAX_PLEN; | |
1197 | write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN, | |
1198 | *gen, nfrags == 0 && *desc_len == 0); | |
1199 | ce1->skb = NULL; | |
1200 | pci_unmap_len_set(ce1, dma_len, 0); | |
1201 | *desc_mapping += SGE_TX_DESC_MAX_PLEN; | |
1202 | if (*desc_len) { | |
1203 | ce1++; | |
1204 | e1++; | |
1205 | if (++pidx == q->size) { | |
1206 | pidx = 0; | |
1207 | *gen ^= 1; | |
1208 | ce1 = q->centries; | |
1209 | e1 = q->entries; | |
1210 | } | |
1211 | } | |
1212 | } | |
1213 | *e = e1; | |
1214 | *ce = ce1; | |
1215 | } | |
1216 | return pidx; | |
1217 | } | |
1218 | ||
8199d3a7 | 1219 | /* |
559fb51b SB |
1220 | * Write the command descriptors to transmit the given skb starting at |
1221 | * descriptor pidx with the given generation. | |
8199d3a7 | 1222 | */ |
559fb51b SB |
1223 | static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb, |
1224 | unsigned int pidx, unsigned int gen, | |
1225 | struct cmdQ *q) | |
8199d3a7 | 1226 | { |
f1d3d38a | 1227 | dma_addr_t mapping, desc_mapping; |
559fb51b SB |
1228 | struct cmdQ_e *e, *e1; |
1229 | struct cmdQ_ce *ce; | |
f1d3d38a SH |
1230 | unsigned int i, flags, first_desc_len, desc_len, |
1231 | nfrags = skb_shinfo(skb)->nr_frags; | |
559fb51b | 1232 | |
f1d3d38a | 1233 | e = e1 = &q->entries[pidx]; |
559fb51b | 1234 | ce = &q->centries[pidx]; |
f1d3d38a SH |
1235 | |
1236 | mapping = pci_map_single(adapter->pdev, skb->data, | |
1237 | skb->len - skb->data_len, PCI_DMA_TODEVICE); | |
1238 | ||
1239 | desc_mapping = mapping; | |
1240 | desc_len = skb->len - skb->data_len; | |
1241 | ||
1242 | flags = F_CMD_DATAVALID | F_CMD_SOP | | |
1243 | V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) | | |
1244 | V_CMD_GEN2(gen); | |
1245 | first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ? | |
1246 | desc_len : SGE_TX_DESC_MAX_PLEN; | |
1247 | e->addr_lo = (u32)desc_mapping; | |
1248 | e->addr_hi = (u64)desc_mapping >> 32; | |
1249 | e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen); | |
1250 | ce->skb = NULL; | |
1251 | pci_unmap_len_set(ce, dma_len, 0); | |
1252 | ||
1253 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN && | |
1254 | desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1255 | desc_mapping += first_desc_len; | |
1256 | desc_len -= first_desc_len; | |
1257 | e1++; | |
1258 | ce++; | |
1259 | if (++pidx == q->size) { | |
1260 | pidx = 0; | |
1261 | gen ^= 1; | |
1262 | e1 = q->entries; | |
1263 | ce = q->centries; | |
1264 | } | |
1265 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1266 | &desc_mapping, &desc_len, | |
1267 | nfrags, q); | |
1268 | ||
1269 | if (likely(desc_len)) | |
1270 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1271 | nfrags == 0); | |
1272 | } | |
1273 | ||
559fb51b SB |
1274 | ce->skb = NULL; |
1275 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
1276 | pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len); | |
8199d3a7 | 1277 | |
f1d3d38a | 1278 | for (i = 0; nfrags--; i++) { |
559fb51b | 1279 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
559fb51b | 1280 | e1++; |
f1d3d38a | 1281 | ce++; |
559fb51b SB |
1282 | if (++pidx == q->size) { |
1283 | pidx = 0; | |
1284 | gen ^= 1; | |
559fb51b | 1285 | e1 = q->entries; |
f1d3d38a | 1286 | ce = q->centries; |
8199d3a7 | 1287 | } |
8199d3a7 | 1288 | |
559fb51b SB |
1289 | mapping = pci_map_page(adapter->pdev, frag->page, |
1290 | frag->page_offset, frag->size, | |
1291 | PCI_DMA_TODEVICE); | |
f1d3d38a SH |
1292 | desc_mapping = mapping; |
1293 | desc_len = frag->size; | |
1294 | ||
1295 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1296 | &desc_mapping, &desc_len, | |
1297 | nfrags, q); | |
1298 | if (likely(desc_len)) | |
1299 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1300 | nfrags == 0); | |
559fb51b SB |
1301 | ce->skb = NULL; |
1302 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
1303 | pci_unmap_len_set(ce, dma_len, frag->size); | |
8199d3a7 | 1304 | } |
559fb51b SB |
1305 | ce->skb = skb; |
1306 | wmb(); | |
1307 | e->flags = flags; | |
1308 | } | |
8199d3a7 | 1309 | |
559fb51b SB |
1310 | /* |
1311 | * Clean up completed Tx buffers. | |
1312 | */ | |
1313 | static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q) | |
1314 | { | |
1315 | unsigned int reclaim = q->processed - q->cleaned; | |
8199d3a7 | 1316 | |
559fb51b | 1317 | if (reclaim) { |
f1d3d38a SH |
1318 | pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n", |
1319 | q->processed, q->cleaned); | |
559fb51b SB |
1320 | free_cmdQ_buffers(sge, q, reclaim); |
1321 | q->cleaned += reclaim; | |
8199d3a7 | 1322 | } |
559fb51b | 1323 | } |
8199d3a7 | 1324 | |
f1d3d38a SH |
1325 | /* |
1326 | * Called from tasklet. Checks the scheduler for any | |
1327 | * pending skbs that can be sent. | |
1328 | */ | |
1329 | static void restart_sched(unsigned long arg) | |
1330 | { | |
1331 | struct sge *sge = (struct sge *) arg; | |
1332 | struct adapter *adapter = sge->adapter; | |
1333 | struct cmdQ *q = &sge->cmdQ[0]; | |
1334 | struct sk_buff *skb; | |
1335 | unsigned int credits, queued_skb = 0; | |
1336 | ||
1337 | spin_lock(&q->lock); | |
1338 | reclaim_completed_tx(sge, q); | |
1339 | ||
1340 | credits = q->size - q->in_use; | |
1341 | pr_debug("restart_sched credits=%d\n", credits); | |
1342 | while ((skb = sched_skb(sge, NULL, credits)) != NULL) { | |
1343 | unsigned int genbit, pidx, count; | |
1344 | count = 1 + skb_shinfo(skb)->nr_frags; | |
356bd146 | 1345 | count += compute_large_page_tx_descs(skb); |
f1d3d38a SH |
1346 | q->in_use += count; |
1347 | genbit = q->genbit; | |
1348 | pidx = q->pidx; | |
1349 | q->pidx += count; | |
1350 | if (q->pidx >= q->size) { | |
1351 | q->pidx -= q->size; | |
1352 | q->genbit ^= 1; | |
1353 | } | |
1354 | write_tx_descs(adapter, skb, pidx, genbit, q); | |
1355 | credits = q->size - q->in_use; | |
1356 | queued_skb = 1; | |
1357 | } | |
1358 | ||
1359 | if (queued_skb) { | |
1360 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1361 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1362 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1363 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1364 | } | |
1365 | } | |
1366 | spin_unlock(&q->lock); | |
1367 | } | |
8199d3a7 | 1368 | |
559fb51b SB |
1369 | /** |
1370 | * sge_rx - process an ingress ethernet packet | |
1371 | * @sge: the sge structure | |
1372 | * @fl: the free list that contains the packet buffer | |
1373 | * @len: the packet length | |
8199d3a7 | 1374 | * |
559fb51b | 1375 | * Process an ingress ethernet pakcet and deliver it to the stack. |
8199d3a7 | 1376 | */ |
559fb51b | 1377 | static int sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len) |
8199d3a7 | 1378 | { |
559fb51b SB |
1379 | struct sk_buff *skb; |
1380 | struct cpl_rx_pkt *p; | |
1381 | struct adapter *adapter = sge->adapter; | |
56f643c2 | 1382 | struct sge_port_stats *st; |
8199d3a7 | 1383 | |
559fb51b SB |
1384 | skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad, |
1385 | sge->rx_pkt_pad, 2, SGE_RX_COPY_THRES, | |
1386 | SGE_RX_DROP_THRES); | |
56f643c2 SH |
1387 | if (unlikely(!skb)) { |
1388 | sge->stats.rx_drops++; | |
559fb51b | 1389 | return 0; |
8199d3a7 | 1390 | } |
559fb51b SB |
1391 | |
1392 | p = (struct cpl_rx_pkt *)skb->data; | |
1393 | skb_pull(skb, sizeof(*p)); | |
f1d3d38a SH |
1394 | if (p->iff >= adapter->params.nports) { |
1395 | kfree_skb(skb); | |
1396 | return 0; | |
1397 | } | |
1398 | ||
56f643c2 | 1399 | skb->dev = adapter->port[p->iff].dev; |
559fb51b | 1400 | skb->dev->last_rx = jiffies; |
56f643c2 SH |
1401 | st = per_cpu_ptr(sge->port_stats[p->iff], smp_processor_id()); |
1402 | st->rx_packets++; | |
1403 | ||
559fb51b SB |
1404 | skb->protocol = eth_type_trans(skb, skb->dev); |
1405 | if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff && | |
1406 | skb->protocol == htons(ETH_P_IP) && | |
1407 | (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { | |
56f643c2 | 1408 | ++st->rx_cso_good; |
559fb51b SB |
1409 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1410 | } else | |
1411 | skb->ip_summed = CHECKSUM_NONE; | |
1412 | ||
1413 | if (unlikely(adapter->vlan_grp && p->vlan_valid)) { | |
56f643c2 | 1414 | st->vlan_xtract++; |
7fe26a60 | 1415 | #ifdef CONFIG_CHELSIO_T1_NAPI |
559fb51b SB |
1416 | vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, |
1417 | ntohs(p->vlan)); | |
7fe26a60 | 1418 | #else |
559fb51b SB |
1419 | vlan_hwaccel_rx(skb, adapter->vlan_grp, |
1420 | ntohs(p->vlan)); | |
7fe26a60 SH |
1421 | #endif |
1422 | } else { | |
1423 | #ifdef CONFIG_CHELSIO_T1_NAPI | |
559fb51b | 1424 | netif_receive_skb(skb); |
7fe26a60 | 1425 | #else |
559fb51b | 1426 | netif_rx(skb); |
7fe26a60 SH |
1427 | #endif |
1428 | } | |
559fb51b | 1429 | return 0; |
8199d3a7 CL |
1430 | } |
1431 | ||
1432 | /* | |
559fb51b | 1433 | * Returns true if a command queue has enough available descriptors that |
8199d3a7 CL |
1434 | * we can resume Tx operation after temporarily disabling its packet queue. |
1435 | */ | |
559fb51b | 1436 | static inline int enough_free_Tx_descs(const struct cmdQ *q) |
8199d3a7 | 1437 | { |
559fb51b SB |
1438 | unsigned int r = q->processed - q->cleaned; |
1439 | ||
1440 | return q->in_use - r < (q->size >> 1); | |
8199d3a7 CL |
1441 | } |
1442 | ||
1443 | /* | |
559fb51b SB |
1444 | * Called when sufficient space has become available in the SGE command queues |
1445 | * after the Tx packet schedulers have been suspended to restart the Tx path. | |
8199d3a7 | 1446 | */ |
559fb51b | 1447 | static void restart_tx_queues(struct sge *sge) |
8199d3a7 | 1448 | { |
559fb51b | 1449 | struct adapter *adap = sge->adapter; |
8199d3a7 | 1450 | |
559fb51b SB |
1451 | if (enough_free_Tx_descs(&sge->cmdQ[0])) { |
1452 | int i; | |
1453 | ||
1454 | for_each_port(adap, i) { | |
1455 | struct net_device *nd = adap->port[i].dev; | |
1456 | ||
1457 | if (test_and_clear_bit(nd->if_port, | |
1458 | &sge->stopped_tx_queues) && | |
1459 | netif_running(nd)) { | |
232a347a | 1460 | sge->stats.cmdQ_restarted[2]++; |
559fb51b SB |
1461 | netif_wake_queue(nd); |
1462 | } | |
1463 | } | |
1464 | } | |
1465 | } | |
1466 | ||
1467 | /* | |
356bd146 | 1468 | * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0 |
559fb51b SB |
1469 | * information. |
1470 | */ | |
356bd146 FR |
1471 | static unsigned int update_tx_info(struct adapter *adapter, |
1472 | unsigned int flags, | |
559fb51b SB |
1473 | unsigned int pr0) |
1474 | { | |
1475 | struct sge *sge = adapter->sge; | |
1476 | struct cmdQ *cmdq = &sge->cmdQ[0]; | |
8199d3a7 | 1477 | |
559fb51b | 1478 | cmdq->processed += pr0; |
f1d3d38a SH |
1479 | if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) { |
1480 | freelQs_empty(sge); | |
1481 | flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE); | |
1482 | } | |
559fb51b SB |
1483 | if (flags & F_CMDQ0_ENABLE) { |
1484 | clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
f1d3d38a | 1485 | |
559fb51b SB |
1486 | if (cmdq->cleaned + cmdq->in_use != cmdq->processed && |
1487 | !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { | |
1488 | set_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
1489 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1490 | } | |
f1d3d38a SH |
1491 | if (sge->tx_sched) |
1492 | tasklet_hi_schedule(&sge->tx_sched->sched_tsk); | |
1493 | ||
1494 | flags &= ~F_CMDQ0_ENABLE; | |
559fb51b | 1495 | } |
f1d3d38a | 1496 | |
559fb51b SB |
1497 | if (unlikely(sge->stopped_tx_queues != 0)) |
1498 | restart_tx_queues(sge); | |
8199d3a7 | 1499 | |
559fb51b SB |
1500 | return flags; |
1501 | } | |
8199d3a7 | 1502 | |
559fb51b SB |
1503 | /* |
1504 | * Process SGE responses, up to the supplied budget. Returns the number of | |
1505 | * responses processed. A negative budget is effectively unlimited. | |
1506 | */ | |
1507 | static int process_responses(struct adapter *adapter, int budget) | |
1508 | { | |
1509 | struct sge *sge = adapter->sge; | |
1510 | struct respQ *q = &sge->respQ; | |
1511 | struct respQ_e *e = &q->entries[q->cidx]; | |
1512 | int budget_left = budget; | |
1513 | unsigned int flags = 0; | |
1514 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
356bd146 | 1515 | |
559fb51b SB |
1516 | |
1517 | while (likely(budget_left && e->GenerationBit == q->genbit)) { | |
1518 | flags |= e->Qsleeping; | |
356bd146 | 1519 | |
559fb51b SB |
1520 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1521 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1522 | |
559fb51b SB |
1523 | /* We batch updates to the TX side to avoid cacheline |
1524 | * ping-pong of TX state information on MP where the sender | |
1525 | * might run on a different CPU than this function... | |
1526 | */ | |
1527 | if (unlikely(flags & F_CMDQ0_ENABLE || cmdq_processed[0] > 64)) { | |
1528 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); | |
1529 | cmdq_processed[0] = 0; | |
1530 | } | |
1531 | if (unlikely(cmdq_processed[1] > 16)) { | |
1532 | sge->cmdQ[1].processed += cmdq_processed[1]; | |
1533 | cmdq_processed[1] = 0; | |
8199d3a7 CL |
1534 | } |
1535 | if (likely(e->DataValid)) { | |
559fb51b SB |
1536 | struct freelQ *fl = &sge->freelQ[e->FreelistQid]; |
1537 | ||
5d9428de | 1538 | BUG_ON(!e->Sop || !e->Eop); |
559fb51b SB |
1539 | if (unlikely(e->Offload)) |
1540 | unexpected_offload(adapter, fl); | |
1541 | else | |
1542 | sge_rx(sge, fl, e->BufferLength); | |
1543 | ||
1544 | /* | |
1545 | * Note: this depends on each packet consuming a | |
1546 | * single free-list buffer; cf. the BUG above. | |
1547 | */ | |
1548 | if (++fl->cidx == fl->size) | |
1549 | fl->cidx = 0; | |
1550 | if (unlikely(--fl->credits < | |
1551 | fl->size - SGE_FREEL_REFILL_THRESH)) | |
1552 | refill_free_list(sge, fl); | |
1553 | } else | |
1554 | sge->stats.pure_rsps++; | |
8199d3a7 | 1555 | |
8199d3a7 | 1556 | e++; |
559fb51b SB |
1557 | if (unlikely(++q->cidx == q->size)) { |
1558 | q->cidx = 0; | |
1559 | q->genbit ^= 1; | |
1560 | e = q->entries; | |
1561 | } | |
1562 | prefetch(e); | |
1563 | ||
1564 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { | |
1565 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1566 | q->credits = 0; | |
8199d3a7 | 1567 | } |
559fb51b | 1568 | --budget_left; |
8199d3a7 CL |
1569 | } |
1570 | ||
356bd146 | 1571 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1572 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1573 | |
559fb51b SB |
1574 | budget -= budget_left; |
1575 | return budget; | |
1576 | } | |
8199d3a7 | 1577 | |
7fe26a60 | 1578 | #ifdef CONFIG_CHELSIO_T1_NAPI |
559fb51b SB |
1579 | /* |
1580 | * A simpler version of process_responses() that handles only pure (i.e., | |
1581 | * non data-carrying) responses. Such respones are too light-weight to justify | |
1582 | * calling a softirq when using NAPI, so we handle them specially in hard | |
1583 | * interrupt context. The function is called with a pointer to a response, | |
1584 | * which the caller must ensure is a valid pure response. Returns 1 if it | |
1585 | * encounters a valid data-carrying response, 0 otherwise. | |
1586 | */ | |
1587 | static int process_pure_responses(struct adapter *adapter, struct respQ_e *e) | |
1588 | { | |
1589 | struct sge *sge = adapter->sge; | |
1590 | struct respQ *q = &sge->respQ; | |
1591 | unsigned int flags = 0; | |
1592 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
8199d3a7 | 1593 | |
559fb51b SB |
1594 | do { |
1595 | flags |= e->Qsleeping; | |
8199d3a7 | 1596 | |
559fb51b SB |
1597 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1598 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1599 | |
559fb51b SB |
1600 | e++; |
1601 | if (unlikely(++q->cidx == q->size)) { | |
1602 | q->cidx = 0; | |
1603 | q->genbit ^= 1; | |
1604 | e = q->entries; | |
8199d3a7 | 1605 | } |
559fb51b | 1606 | prefetch(e); |
8199d3a7 | 1607 | |
559fb51b SB |
1608 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { |
1609 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1610 | q->credits = 0; | |
8199d3a7 | 1611 | } |
559fb51b SB |
1612 | sge->stats.pure_rsps++; |
1613 | } while (e->GenerationBit == q->genbit && !e->DataValid); | |
8199d3a7 | 1614 | |
356bd146 | 1615 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1616 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1617 | |
559fb51b | 1618 | return e->GenerationBit == q->genbit; |
8199d3a7 CL |
1619 | } |
1620 | ||
1621 | /* | |
559fb51b SB |
1622 | * Handler for new data events when using NAPI. This does not need any locking |
1623 | * or protection from interrupts as data interrupts are off at this point and | |
1624 | * other adapter interrupts do not interfere. | |
8199d3a7 | 1625 | */ |
7fe26a60 | 1626 | int t1_poll(struct net_device *dev, int *budget) |
8199d3a7 | 1627 | { |
559fb51b SB |
1628 | struct adapter *adapter = dev->priv; |
1629 | int effective_budget = min(*budget, dev->quota); | |
559fb51b | 1630 | int work_done = process_responses(adapter, effective_budget); |
7fe26a60 | 1631 | |
559fb51b SB |
1632 | *budget -= work_done; |
1633 | dev->quota -= work_done; | |
8199d3a7 | 1634 | |
559fb51b SB |
1635 | if (work_done >= effective_budget) |
1636 | return 1; | |
1637 | ||
356bd146 | 1638 | spin_lock_irq(&adapter->async_lock); |
559fb51b | 1639 | __netif_rx_complete(dev); |
559fb51b | 1640 | writel(adapter->sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); |
7fe26a60 SH |
1641 | writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, |
1642 | adapter->regs + A_PL_ENABLE); | |
356bd146 | 1643 | spin_unlock_irq(&adapter->async_lock); |
8199d3a7 | 1644 | |
7fe26a60 | 1645 | return 0; |
559fb51b | 1646 | } |
8199d3a7 | 1647 | |
559fb51b SB |
1648 | /* |
1649 | * NAPI version of the main interrupt handler. | |
1650 | */ | |
7fe26a60 | 1651 | irqreturn_t t1_interrupt(int irq, void *data) |
559fb51b | 1652 | { |
559fb51b | 1653 | struct adapter *adapter = data; |
356bd146 | 1654 | struct net_device *dev = adapter->sge->netdev; |
559fb51b | 1655 | struct sge *sge = adapter->sge; |
356bd146 | 1656 | u32 cause; |
7fe26a60 | 1657 | int handled = 0; |
8199d3a7 | 1658 | |
7fe26a60 SH |
1659 | cause = readl(adapter->regs + A_PL_CAUSE); |
1660 | if (cause == 0 || cause == ~0) | |
1661 | return IRQ_NONE; | |
559fb51b SB |
1662 | |
1663 | spin_lock(&adapter->async_lock); | |
356bd146 | 1664 | if (cause & F_PL_INTR_SGE_DATA) { |
7fe26a60 | 1665 | struct respQ *q = &adapter->sge->respQ; |
559fb51b SB |
1666 | struct respQ_e *e = &q->entries[q->cidx]; |
1667 | ||
356bd146 FR |
1668 | handled = 1; |
1669 | writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); | |
7fe26a60 SH |
1670 | |
1671 | if (e->GenerationBit == q->genbit && | |
1672 | __netif_rx_schedule_prep(dev)) { | |
1673 | if (e->DataValid || process_pure_responses(adapter, e)) { | |
1674 | /* mask off data IRQ */ | |
1675 | writel(adapter->slow_intr_mask, | |
1676 | adapter->regs + A_PL_ENABLE); | |
1677 | __netif_rx_schedule(sge->netdev); | |
1678 | goto unlock; | |
1679 | } | |
1680 | /* no data, no NAPI needed */ | |
1681 | netif_poll_enable(dev); | |
1682 | ||
1683 | } | |
1684 | writel(q->cidx, adapter->regs + A_SG_SLEEPING); | |
1685 | } else | |
1686 | handled = t1_slow_intr_handler(adapter); | |
1687 | ||
559fb51b SB |
1688 | if (!handled) |
1689 | sge->stats.unhandled_irqs++; | |
7fe26a60 | 1690 | unlock: |
559fb51b SB |
1691 | spin_unlock(&adapter->async_lock); |
1692 | return IRQ_RETVAL(handled != 0); | |
1693 | } | |
8199d3a7 | 1694 | |
7fe26a60 | 1695 | #else |
559fb51b SB |
1696 | /* |
1697 | * Main interrupt handler, optimized assuming that we took a 'DATA' | |
1698 | * interrupt. | |
1699 | * | |
1700 | * 1. Clear the interrupt | |
1701 | * 2. Loop while we find valid descriptors and process them; accumulate | |
1702 | * information that can be processed after the loop | |
1703 | * 3. Tell the SGE at which index we stopped processing descriptors | |
1704 | * 4. Bookkeeping; free TX buffers, ring doorbell if there are any | |
1705 | * outstanding TX buffers waiting, replenish RX buffers, potentially | |
1706 | * reenable upper layers if they were turned off due to lack of TX | |
1707 | * resources which are available again. | |
1708 | * 5. If we took an interrupt, but no valid respQ descriptors was found we | |
1709 | * let the slow_intr_handler run and do error handling. | |
1710 | */ | |
7fe26a60 | 1711 | irqreturn_t t1_interrupt(int irq, void *cookie) |
559fb51b SB |
1712 | { |
1713 | int work_done; | |
1714 | struct respQ_e *e; | |
1715 | struct adapter *adapter = cookie; | |
1716 | struct respQ *Q = &adapter->sge->respQ; | |
8199d3a7 | 1717 | |
559fb51b SB |
1718 | spin_lock(&adapter->async_lock); |
1719 | e = &Q->entries[Q->cidx]; | |
1720 | prefetch(e); | |
8199d3a7 | 1721 | |
559fb51b | 1722 | writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); |
8199d3a7 | 1723 | |
559fb51b SB |
1724 | if (likely(e->GenerationBit == Q->genbit)) |
1725 | work_done = process_responses(adapter, -1); | |
1726 | else | |
1727 | work_done = t1_slow_intr_handler(adapter); | |
8199d3a7 | 1728 | |
559fb51b SB |
1729 | /* |
1730 | * The unconditional clearing of the PL_CAUSE above may have raced | |
1731 | * with DMA completion and the corresponding generation of a response | |
1732 | * to cause us to miss the resulting data interrupt. The next write | |
1733 | * is also unconditional to recover the missed interrupt and render | |
1734 | * this race harmless. | |
1735 | */ | |
1736 | writel(Q->cidx, adapter->regs + A_SG_SLEEPING); | |
1737 | ||
1738 | if (!work_done) | |
1739 | adapter->sge->stats.unhandled_irqs++; | |
1740 | spin_unlock(&adapter->async_lock); | |
1741 | return IRQ_RETVAL(work_done != 0); | |
1742 | } | |
7fe26a60 | 1743 | #endif |
559fb51b SB |
1744 | |
1745 | /* | |
1746 | * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. | |
1747 | * | |
1748 | * The code figures out how many entries the sk_buff will require in the | |
1749 | * cmdQ and updates the cmdQ data structure with the state once the enqueue | |
1750 | * has complete. Then, it doesn't access the global structure anymore, but | |
1751 | * uses the corresponding fields on the stack. In conjuction with a spinlock | |
1752 | * around that code, we can make the function reentrant without holding the | |
1753 | * lock when we actually enqueue (which might be expensive, especially on | |
1754 | * architectures with IO MMUs). | |
1755 | * | |
1756 | * This runs with softirqs disabled. | |
1757 | */ | |
aa84505f SH |
1758 | static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter, |
1759 | unsigned int qid, struct net_device *dev) | |
559fb51b SB |
1760 | { |
1761 | struct sge *sge = adapter->sge; | |
1762 | struct cmdQ *q = &sge->cmdQ[qid]; | |
f1d3d38a | 1763 | unsigned int credits, pidx, genbit, count, use_sched_skb = 0; |
559fb51b | 1764 | |
cabdfb37 SH |
1765 | if (!spin_trylock(&q->lock)) |
1766 | return NETDEV_TX_LOCKED; | |
1767 | ||
559fb51b SB |
1768 | reclaim_completed_tx(sge, q); |
1769 | ||
1770 | pidx = q->pidx; | |
1771 | credits = q->size - q->in_use; | |
1772 | count = 1 + skb_shinfo(skb)->nr_frags; | |
f1d3d38a | 1773 | count += compute_large_page_tx_descs(skb); |
559fb51b | 1774 | |
f1d3d38a SH |
1775 | /* Ethernet packet */ |
1776 | if (unlikely(credits < count)) { | |
1777 | if (!netif_queue_stopped(dev)) { | |
559fb51b SB |
1778 | netif_stop_queue(dev); |
1779 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
232a347a | 1780 | sge->stats.cmdQ_full[2]++; |
f1d3d38a SH |
1781 | CH_ERR("%s: Tx ring full while queue awake!\n", |
1782 | adapter->name); | |
8199d3a7 | 1783 | } |
f1d3d38a SH |
1784 | spin_unlock(&q->lock); |
1785 | return NETDEV_TX_BUSY; | |
1786 | } | |
1787 | ||
1788 | if (unlikely(credits - count < q->stop_thres)) { | |
1789 | netif_stop_queue(dev); | |
1790 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
1791 | sge->stats.cmdQ_full[2]++; | |
1792 | } | |
1793 | ||
1794 | /* T204 cmdQ0 skbs that are destined for a certain port have to go | |
1795 | * through the scheduler. | |
1796 | */ | |
1797 | if (sge->tx_sched && !qid && skb->dev) { | |
356bd146 | 1798 | use_sched: |
f1d3d38a SH |
1799 | use_sched_skb = 1; |
1800 | /* Note that the scheduler might return a different skb than | |
1801 | * the one passed in. | |
1802 | */ | |
1803 | skb = sched_skb(sge, skb, credits); | |
1804 | if (!skb) { | |
1805 | spin_unlock(&q->lock); | |
1806 | return NETDEV_TX_OK; | |
559fb51b | 1807 | } |
f1d3d38a SH |
1808 | pidx = q->pidx; |
1809 | count = 1 + skb_shinfo(skb)->nr_frags; | |
1810 | count += compute_large_page_tx_descs(skb); | |
559fb51b | 1811 | } |
f1d3d38a | 1812 | |
559fb51b SB |
1813 | q->in_use += count; |
1814 | genbit = q->genbit; | |
f1d3d38a | 1815 | pidx = q->pidx; |
559fb51b SB |
1816 | q->pidx += count; |
1817 | if (q->pidx >= q->size) { | |
1818 | q->pidx -= q->size; | |
1819 | q->genbit ^= 1; | |
8199d3a7 | 1820 | } |
559fb51b | 1821 | spin_unlock(&q->lock); |
8199d3a7 | 1822 | |
559fb51b | 1823 | write_tx_descs(adapter, skb, pidx, genbit, q); |
8199d3a7 CL |
1824 | |
1825 | /* | |
1826 | * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring | |
1827 | * the doorbell if the Q is asleep. There is a natural race, where | |
1828 | * the hardware is going to sleep just after we checked, however, | |
1829 | * then the interrupt handler will detect the outstanding TX packet | |
1830 | * and ring the doorbell for us. | |
1831 | */ | |
559fb51b SB |
1832 | if (qid) |
1833 | doorbell_pio(adapter, F_CMDQ1_ENABLE); | |
1834 | else { | |
1835 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1836 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1837 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1838 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1839 | } | |
8199d3a7 | 1840 | } |
f1d3d38a SH |
1841 | |
1842 | if (use_sched_skb) { | |
1843 | if (spin_trylock(&q->lock)) { | |
1844 | credits = q->size - q->in_use; | |
1845 | skb = NULL; | |
1846 | goto use_sched; | |
1847 | } | |
1848 | } | |
aa84505f | 1849 | return NETDEV_TX_OK; |
8199d3a7 CL |
1850 | } |
1851 | ||
1852 | #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14)) | |
1853 | ||
559fb51b SB |
1854 | /* |
1855 | * eth_hdr_len - return the length of an Ethernet header | |
1856 | * @data: pointer to the start of the Ethernet header | |
1857 | * | |
1858 | * Returns the length of an Ethernet header, including optional VLAN tag. | |
1859 | */ | |
1860 | static inline int eth_hdr_len(const void *data) | |
1861 | { | |
1862 | const struct ethhdr *e = data; | |
1863 | ||
1864 | return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN; | |
1865 | } | |
1866 | ||
8199d3a7 CL |
1867 | /* |
1868 | * Adds the CPL header to the sk_buff and passes it to t1_sge_tx. | |
1869 | */ | |
1870 | int t1_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1871 | { | |
1872 | struct adapter *adapter = dev->priv; | |
559fb51b | 1873 | struct sge *sge = adapter->sge; |
56f643c2 | 1874 | struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port], smp_processor_id()); |
8199d3a7 | 1875 | struct cpl_tx_pkt *cpl; |
cabdfb37 SH |
1876 | struct sk_buff *orig_skb = skb; |
1877 | int ret; | |
8199d3a7 | 1878 | |
f1d3d38a SH |
1879 | if (skb->protocol == htons(ETH_P_CPL5)) |
1880 | goto send; | |
1881 | ||
1882 | if (skb_shinfo(skb)->gso_size) { | |
8199d3a7 CL |
1883 | int eth_type; |
1884 | struct cpl_tx_pkt_lso *hdr; | |
1885 | ||
56f643c2 | 1886 | ++st->tx_tso; |
559fb51b | 1887 | |
8199d3a7 CL |
1888 | eth_type = skb->nh.raw - skb->data == ETH_HLEN ? |
1889 | CPL_ETH_II : CPL_ETH_II_VLAN; | |
1890 | ||
1891 | hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr)); | |
1892 | hdr->opcode = CPL_TX_PKT_LSO; | |
1893 | hdr->ip_csum_dis = hdr->l4_csum_dis = 0; | |
1894 | hdr->ip_hdr_words = skb->nh.iph->ihl; | |
1895 | hdr->tcp_hdr_words = skb->h.th->doff; | |
1896 | hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, | |
f1d3d38a | 1897 | skb_shinfo(skb)->gso_size)); |
8199d3a7 CL |
1898 | hdr->len = htonl(skb->len - sizeof(*hdr)); |
1899 | cpl = (struct cpl_tx_pkt *)hdr; | |
f1d3d38a | 1900 | } else { |
8199d3a7 | 1901 | /* |
356bd146 | 1902 | * Packets shorter than ETH_HLEN can break the MAC, drop them |
559fb51b SB |
1903 | * early. Also, we may get oversized packets because some |
1904 | * parts of the kernel don't handle our unusual hard_header_len | |
1905 | * right, drop those too. | |
8199d3a7 | 1906 | */ |
559fb51b SB |
1907 | if (unlikely(skb->len < ETH_HLEN || |
1908 | skb->len > dev->mtu + eth_hdr_len(skb->data))) { | |
f1d3d38a SH |
1909 | pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name, |
1910 | skb->len, eth_hdr_len(skb->data), dev->mtu); | |
559fb51b | 1911 | dev_kfree_skb_any(skb); |
aa84505f | 1912 | return NETDEV_TX_OK; |
559fb51b SB |
1913 | } |
1914 | ||
1915 | /* | |
1916 | * We are using a non-standard hard_header_len and some kernel | |
1917 | * components, such as pktgen, do not handle it right. | |
1918 | * Complain when this happens but try to fix things up. | |
1919 | */ | |
f1d3d38a | 1920 | if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) { |
f1d3d38a SH |
1921 | pr_debug("%s: headroom %d header_len %d\n", dev->name, |
1922 | skb_headroom(skb), dev->hard_header_len); | |
1923 | ||
559fb51b SB |
1924 | if (net_ratelimit()) |
1925 | printk(KERN_ERR "%s: inadequate headroom in " | |
1926 | "Tx packet\n", dev->name); | |
1927 | skb = skb_realloc_headroom(skb, sizeof(*cpl)); | |
1928 | dev_kfree_skb_any(orig_skb); | |
1929 | if (!skb) | |
aa84505f | 1930 | return NETDEV_TX_OK; |
559fb51b | 1931 | } |
8199d3a7 CL |
1932 | |
1933 | if (!(adapter->flags & UDP_CSUM_CAPABLE) && | |
84fa7933 | 1934 | skb->ip_summed == CHECKSUM_PARTIAL && |
f1d3d38a | 1935 | skb->nh.iph->protocol == IPPROTO_UDP) { |
84fa7933 | 1936 | if (unlikely(skb_checksum_help(skb))) { |
f1d3d38a | 1937 | pr_debug("%s: unable to do udp checksum\n", dev->name); |
559fb51b | 1938 | dev_kfree_skb_any(skb); |
aa84505f | 1939 | return NETDEV_TX_OK; |
559fb51b | 1940 | } |
f1d3d38a | 1941 | } |
8199d3a7 | 1942 | |
559fb51b SB |
1943 | /* Hmmm, assuming to catch the gratious arp... and we'll use |
1944 | * it to flush out stuck espi packets... | |
f1d3d38a SH |
1945 | */ |
1946 | if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) { | |
8199d3a7 | 1947 | if (skb->protocol == htons(ETH_P_ARP) && |
559fb51b | 1948 | skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) { |
f1d3d38a | 1949 | adapter->sge->espibug_skb[dev->if_port] = skb; |
559fb51b SB |
1950 | /* We want to re-use this skb later. We |
1951 | * simply bump the reference count and it | |
1952 | * will not be freed... | |
1953 | */ | |
1954 | skb = skb_get(skb); | |
1955 | } | |
8199d3a7 | 1956 | } |
559fb51b SB |
1957 | |
1958 | cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl)); | |
8199d3a7 CL |
1959 | cpl->opcode = CPL_TX_PKT; |
1960 | cpl->ip_csum_dis = 1; /* SW calculates IP csum */ | |
84fa7933 | 1961 | cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1; |
8199d3a7 | 1962 | /* the length field isn't used so don't bother setting it */ |
559fb51b | 1963 | |
84fa7933 | 1964 | st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); |
8199d3a7 CL |
1965 | } |
1966 | cpl->iff = dev->if_port; | |
1967 | ||
1968 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
1969 | if (adapter->vlan_grp && vlan_tx_tag_present(skb)) { | |
1970 | cpl->vlan_valid = 1; | |
1971 | cpl->vlan = htons(vlan_tx_tag_get(skb)); | |
559fb51b | 1972 | st->vlan_insert++; |
8199d3a7 CL |
1973 | } else |
1974 | #endif | |
1975 | cpl->vlan_valid = 0; | |
1976 | ||
f1d3d38a | 1977 | send: |
56f643c2 | 1978 | st->tx_packets++; |
8199d3a7 | 1979 | dev->trans_start = jiffies; |
cabdfb37 SH |
1980 | ret = t1_sge_tx(skb, adapter, 0, dev); |
1981 | ||
1982 | /* If transmit busy, and we reallocated skb's due to headroom limit, | |
1983 | * then silently discard to avoid leak. | |
1984 | */ | |
1985 | if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) { | |
356bd146 | 1986 | dev_kfree_skb_any(skb); |
cabdfb37 | 1987 | ret = NETDEV_TX_OK; |
356bd146 | 1988 | } |
cabdfb37 | 1989 | return ret; |
559fb51b | 1990 | } |
8199d3a7 | 1991 | |
559fb51b SB |
1992 | /* |
1993 | * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled. | |
1994 | */ | |
1995 | static void sge_tx_reclaim_cb(unsigned long data) | |
1996 | { | |
1997 | int i; | |
1998 | struct sge *sge = (struct sge *)data; | |
1999 | ||
2000 | for (i = 0; i < SGE_CMDQ_N; ++i) { | |
2001 | struct cmdQ *q = &sge->cmdQ[i]; | |
2002 | ||
2003 | if (!spin_trylock(&q->lock)) | |
2004 | continue; | |
8199d3a7 | 2005 | |
559fb51b | 2006 | reclaim_completed_tx(sge, q); |
f1d3d38a SH |
2007 | if (i == 0 && q->in_use) { /* flush pending credits */ |
2008 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
2009 | } | |
559fb51b SB |
2010 | spin_unlock(&q->lock); |
2011 | } | |
2012 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
2013 | } | |
2014 | ||
2015 | /* | |
2016 | * Propagate changes of the SGE coalescing parameters to the HW. | |
2017 | */ | |
2018 | int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p) | |
2019 | { | |
559fb51b SB |
2020 | sge->fixed_intrtimer = p->rx_coalesce_usecs * |
2021 | core_ticks_per_usec(sge->adapter); | |
2022 | writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER); | |
8199d3a7 CL |
2023 | return 0; |
2024 | } | |
2025 | ||
559fb51b SB |
2026 | /* |
2027 | * Allocates both RX and TX resources and configures the SGE. However, | |
2028 | * the hardware is not enabled yet. | |
2029 | */ | |
2030 | int t1_sge_configure(struct sge *sge, struct sge_params *p) | |
8199d3a7 | 2031 | { |
559fb51b SB |
2032 | if (alloc_rx_resources(sge, p)) |
2033 | return -ENOMEM; | |
2034 | if (alloc_tx_resources(sge, p)) { | |
2035 | free_rx_resources(sge); | |
2036 | return -ENOMEM; | |
2037 | } | |
2038 | configure_sge(sge, p); | |
2039 | ||
2040 | /* | |
2041 | * Now that we have sized the free lists calculate the payload | |
2042 | * capacity of the large buffers. Other parts of the driver use | |
2043 | * this to set the max offload coalescing size so that RX packets | |
2044 | * do not overflow our large buffers. | |
2045 | */ | |
2046 | p->large_buf_capacity = jumbo_payload_capacity(sge); | |
2047 | return 0; | |
2048 | } | |
8199d3a7 | 2049 | |
559fb51b SB |
2050 | /* |
2051 | * Disables the DMA engine. | |
2052 | */ | |
2053 | void t1_sge_stop(struct sge *sge) | |
2054 | { | |
f1d3d38a | 2055 | int i; |
559fb51b | 2056 | writel(0, sge->adapter->regs + A_SG_CONTROL); |
f1d3d38a SH |
2057 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
2058 | ||
559fb51b SB |
2059 | if (is_T2(sge->adapter)) |
2060 | del_timer_sync(&sge->espibug_timer); | |
f1d3d38a | 2061 | |
559fb51b | 2062 | del_timer_sync(&sge->tx_reclaim_timer); |
f1d3d38a SH |
2063 | if (sge->tx_sched) |
2064 | tx_sched_stop(sge); | |
2065 | ||
2066 | for (i = 0; i < MAX_NPORTS; i++) | |
2067 | if (sge->espibug_skb[i]) | |
2068 | kfree_skb(sge->espibug_skb[i]); | |
8199d3a7 CL |
2069 | } |
2070 | ||
559fb51b SB |
2071 | /* |
2072 | * Enables the DMA engine. | |
2073 | */ | |
2074 | void t1_sge_start(struct sge *sge) | |
8199d3a7 | 2075 | { |
559fb51b SB |
2076 | refill_free_list(sge, &sge->freelQ[0]); |
2077 | refill_free_list(sge, &sge->freelQ[1]); | |
2078 | ||
2079 | writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); | |
2080 | doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); | |
f1d3d38a | 2081 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
559fb51b SB |
2082 | |
2083 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
2084 | ||
f1d3d38a | 2085 | if (is_T2(sge->adapter)) |
559fb51b SB |
2086 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); |
2087 | } | |
2088 | ||
2089 | /* | |
2090 | * Callback for the T2 ESPI 'stuck packet feature' workaorund | |
2091 | */ | |
f1d3d38a | 2092 | static void espibug_workaround_t204(unsigned long data) |
559fb51b SB |
2093 | { |
2094 | struct adapter *adapter = (struct adapter *)data; | |
8199d3a7 | 2095 | struct sge *sge = adapter->sge; |
f1d3d38a SH |
2096 | unsigned int nports = adapter->params.nports; |
2097 | u32 seop[MAX_NPORTS]; | |
8199d3a7 | 2098 | |
f1d3d38a SH |
2099 | if (adapter->open_device_map & PORT_MASK) { |
2100 | int i; | |
356bd146 FR |
2101 | |
2102 | if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) | |
f1d3d38a | 2103 | return; |
356bd146 | 2104 | |
f1d3d38a | 2105 | for (i = 0; i < nports; i++) { |
356bd146 FR |
2106 | struct sk_buff *skb = sge->espibug_skb[i]; |
2107 | ||
2108 | if (!netif_running(adapter->port[i].dev) || | |
2109 | netif_queue_stopped(adapter->port[i].dev) || | |
2110 | !seop[i] || ((seop[i] & 0xfff) != 0) || !skb) | |
2111 | continue; | |
2112 | ||
2113 | if (!skb->cb[0]) { | |
2114 | u8 ch_mac_addr[ETH_ALEN] = { | |
2115 | 0x0, 0x7, 0x43, 0x0, 0x0, 0x0 | |
2116 | }; | |
2117 | ||
2118 | memcpy(skb->data + sizeof(struct cpl_tx_pkt), | |
2119 | ch_mac_addr, ETH_ALEN); | |
2120 | memcpy(skb->data + skb->len - 10, | |
2121 | ch_mac_addr, ETH_ALEN); | |
2122 | skb->cb[0] = 0xff; | |
559fb51b | 2123 | } |
356bd146 FR |
2124 | |
2125 | /* bump the reference count to avoid freeing of | |
2126 | * the skb once the DMA has completed. | |
2127 | */ | |
2128 | skb = skb_get(skb); | |
2129 | t1_sge_tx(skb, adapter, 0, adapter->port[i].dev); | |
559fb51b SB |
2130 | } |
2131 | } | |
2132 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
8199d3a7 CL |
2133 | } |
2134 | ||
f1d3d38a SH |
2135 | static void espibug_workaround(unsigned long data) |
2136 | { | |
2137 | struct adapter *adapter = (struct adapter *)data; | |
2138 | struct sge *sge = adapter->sge; | |
2139 | ||
2140 | if (netif_running(adapter->port[0].dev)) { | |
2141 | struct sk_buff *skb = sge->espibug_skb[0]; | |
2142 | u32 seop = t1_espi_get_mon(adapter, 0x930, 0); | |
2143 | ||
2144 | if ((seop & 0xfff0fff) == 0xfff && skb) { | |
2145 | if (!skb->cb[0]) { | |
2146 | u8 ch_mac_addr[ETH_ALEN] = | |
2147 | {0x0, 0x7, 0x43, 0x0, 0x0, 0x0}; | |
2148 | memcpy(skb->data + sizeof(struct cpl_tx_pkt), | |
2149 | ch_mac_addr, ETH_ALEN); | |
2150 | memcpy(skb->data + skb->len - 10, ch_mac_addr, | |
2151 | ETH_ALEN); | |
2152 | skb->cb[0] = 0xff; | |
2153 | } | |
2154 | ||
2155 | /* bump the reference count to avoid freeing of the | |
2156 | * skb once the DMA has completed. | |
2157 | */ | |
2158 | skb = skb_get(skb); | |
2159 | t1_sge_tx(skb, adapter, 0, adapter->port[0].dev); | |
2160 | } | |
2161 | } | |
2162 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
2163 | } | |
2164 | ||
559fb51b SB |
2165 | /* |
2166 | * Creates a t1_sge structure and returns suggested resource parameters. | |
2167 | */ | |
2168 | struct sge * __devinit t1_sge_create(struct adapter *adapter, | |
2169 | struct sge_params *p) | |
2170 | { | |
cbee9f91 | 2171 | struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL); |
56f643c2 | 2172 | int i; |
559fb51b SB |
2173 | |
2174 | if (!sge) | |
2175 | return NULL; | |
559fb51b SB |
2176 | |
2177 | sge->adapter = adapter; | |
2178 | sge->netdev = adapter->port[0].dev; | |
2179 | sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; | |
2180 | sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; | |
2181 | ||
56f643c2 SH |
2182 | for_each_port(adapter, i) { |
2183 | sge->port_stats[i] = alloc_percpu(struct sge_port_stats); | |
2184 | if (!sge->port_stats[i]) | |
2185 | goto nomem_port; | |
2186 | } | |
2187 | ||
559fb51b SB |
2188 | init_timer(&sge->tx_reclaim_timer); |
2189 | sge->tx_reclaim_timer.data = (unsigned long)sge; | |
2190 | sge->tx_reclaim_timer.function = sge_tx_reclaim_cb; | |
2191 | ||
2192 | if (is_T2(sge->adapter)) { | |
2193 | init_timer(&sge->espibug_timer); | |
f1d3d38a SH |
2194 | |
2195 | if (adapter->params.nports > 1) { | |
2196 | tx_sched_init(sge); | |
2197 | sge->espibug_timer.function = espibug_workaround_t204; | |
2198 | } else { | |
2199 | sge->espibug_timer.function = espibug_workaround; | |
2200 | } | |
559fb51b | 2201 | sge->espibug_timer.data = (unsigned long)sge->adapter; |
f1d3d38a | 2202 | |
559fb51b | 2203 | sge->espibug_timeout = 1; |
f1d3d38a SH |
2204 | /* for T204, every 10ms */ |
2205 | if (adapter->params.nports > 1) | |
2206 | sge->espibug_timeout = HZ/100; | |
559fb51b | 2207 | } |
356bd146 | 2208 | |
559fb51b SB |
2209 | |
2210 | p->cmdQ_size[0] = SGE_CMDQ0_E_N; | |
2211 | p->cmdQ_size[1] = SGE_CMDQ1_E_N; | |
2212 | p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; | |
2213 | p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; | |
f1d3d38a SH |
2214 | if (sge->tx_sched) { |
2215 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) | |
2216 | p->rx_coalesce_usecs = 15; | |
2217 | else | |
2218 | p->rx_coalesce_usecs = 50; | |
2219 | } else | |
2220 | p->rx_coalesce_usecs = 50; | |
2221 | ||
559fb51b SB |
2222 | p->coalesce_enable = 0; |
2223 | p->sample_interval_usecs = 0; | |
559fb51b SB |
2224 | |
2225 | return sge; | |
56f643c2 SH |
2226 | nomem_port: |
2227 | while (i >= 0) { | |
2228 | free_percpu(sge->port_stats[i]); | |
2229 | --i; | |
2230 | } | |
2231 | kfree(sge); | |
2232 | return NULL; | |
2233 | ||
559fb51b | 2234 | } |