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Commit | Line | Data |
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a4636960 MC |
1 | /* cnic.c: Broadcom CNIC core network driver. |
2 | * | |
1d9cfc4e | 3 | * Copyright (c) 2006-2010 Broadcom Corporation |
a4636960 MC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com) | |
10 | * Modified and maintained by: Michael Chan <mchan@broadcom.com> | |
11 | */ | |
12 | ||
ddf79b20 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
a4636960 MC |
15 | #include <linux/module.h> |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/netdevice.h> | |
24 | #include <linux/uio_driver.h> | |
25 | #include <linux/in.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ethtool.h> | |
29 | #include <linux/if_vlan.h> | |
30 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
31 | #define BCM_VLAN 1 | |
32 | #endif | |
33 | #include <net/ip.h> | |
34 | #include <net/tcp.h> | |
35 | #include <net/route.h> | |
36 | #include <net/ipv6.h> | |
37 | #include <net/ip6_route.h> | |
c05e85a0 | 38 | #include <net/ip6_checksum.h> |
a4636960 MC |
39 | #include <scsi/iscsi_if.h> |
40 | ||
41 | #include "cnic_if.h" | |
42 | #include "bnx2.h" | |
5d1e859c DK |
43 | #include "bnx2x/bnx2x_reg.h" |
44 | #include "bnx2x/bnx2x_fw_defs.h" | |
45 | #include "bnx2x/bnx2x_hsi.h" | |
e2513065 MC |
46 | #include "../scsi/bnx2i/57xx_iscsi_constants.h" |
47 | #include "../scsi/bnx2i/57xx_iscsi_hsi.h" | |
a4636960 MC |
48 | #include "cnic.h" |
49 | #include "cnic_defs.h" | |
50 | ||
51 | #define DRV_MODULE_NAME "cnic" | |
a4636960 MC |
52 | |
53 | static char version[] __devinitdata = | |
54 | "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n"; | |
55 | ||
56 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) " | |
57 | "Chen (zongxi@broadcom.com"); | |
58 | MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver"); | |
59 | MODULE_LICENSE("GPL"); | |
60 | MODULE_VERSION(CNIC_MODULE_VERSION); | |
61 | ||
8adc9240 | 62 | /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */ |
a4636960 | 63 | static LIST_HEAD(cnic_dev_list); |
a3ceeeb8 | 64 | static LIST_HEAD(cnic_udev_list); |
a4636960 MC |
65 | static DEFINE_RWLOCK(cnic_dev_lock); |
66 | static DEFINE_MUTEX(cnic_lock); | |
67 | ||
68 | static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE]; | |
69 | ||
70 | static int cnic_service_bnx2(void *, void *); | |
71034ba8 | 71 | static int cnic_service_bnx2x(void *, void *); |
a4636960 MC |
72 | static int cnic_ctl(void *, struct cnic_ctl_info *); |
73 | ||
74 | static struct cnic_ops cnic_bnx2_ops = { | |
75 | .cnic_owner = THIS_MODULE, | |
76 | .cnic_handler = cnic_service_bnx2, | |
77 | .cnic_ctl = cnic_ctl, | |
78 | }; | |
79 | ||
71034ba8 MC |
80 | static struct cnic_ops cnic_bnx2x_ops = { |
81 | .cnic_owner = THIS_MODULE, | |
82 | .cnic_handler = cnic_service_bnx2x, | |
83 | .cnic_ctl = cnic_ctl, | |
84 | }; | |
85 | ||
fdf24086 MC |
86 | static struct workqueue_struct *cnic_wq; |
87 | ||
86b53606 MC |
88 | static void cnic_shutdown_rings(struct cnic_dev *); |
89 | static void cnic_init_rings(struct cnic_dev *); | |
a4636960 MC |
90 | static int cnic_cm_set_pg(struct cnic_sock *); |
91 | ||
92 | static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode) | |
93 | { | |
cd801536 MC |
94 | struct cnic_uio_dev *udev = uinfo->priv; |
95 | struct cnic_dev *dev; | |
a4636960 MC |
96 | |
97 | if (!capable(CAP_NET_ADMIN)) | |
98 | return -EPERM; | |
99 | ||
cd801536 | 100 | if (udev->uio_dev != -1) |
a4636960 MC |
101 | return -EBUSY; |
102 | ||
86b53606 | 103 | rtnl_lock(); |
cd801536 MC |
104 | dev = udev->dev; |
105 | ||
a3ceeeb8 | 106 | if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) { |
86b53606 MC |
107 | rtnl_unlock(); |
108 | return -ENODEV; | |
109 | } | |
110 | ||
cd801536 | 111 | udev->uio_dev = iminor(inode); |
a4636960 | 112 | |
a3ceeeb8 | 113 | cnic_shutdown_rings(dev); |
86b53606 MC |
114 | cnic_init_rings(dev); |
115 | rtnl_unlock(); | |
a4636960 MC |
116 | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode) | |
121 | { | |
cd801536 | 122 | struct cnic_uio_dev *udev = uinfo->priv; |
6ef57a0e | 123 | |
cd801536 | 124 | udev->uio_dev = -1; |
a4636960 MC |
125 | return 0; |
126 | } | |
127 | ||
128 | static inline void cnic_hold(struct cnic_dev *dev) | |
129 | { | |
130 | atomic_inc(&dev->ref_count); | |
131 | } | |
132 | ||
133 | static inline void cnic_put(struct cnic_dev *dev) | |
134 | { | |
135 | atomic_dec(&dev->ref_count); | |
136 | } | |
137 | ||
138 | static inline void csk_hold(struct cnic_sock *csk) | |
139 | { | |
140 | atomic_inc(&csk->ref_count); | |
141 | } | |
142 | ||
143 | static inline void csk_put(struct cnic_sock *csk) | |
144 | { | |
145 | atomic_dec(&csk->ref_count); | |
146 | } | |
147 | ||
148 | static struct cnic_dev *cnic_from_netdev(struct net_device *netdev) | |
149 | { | |
150 | struct cnic_dev *cdev; | |
151 | ||
152 | read_lock(&cnic_dev_lock); | |
153 | list_for_each_entry(cdev, &cnic_dev_list, list) { | |
154 | if (netdev == cdev->netdev) { | |
155 | cnic_hold(cdev); | |
156 | read_unlock(&cnic_dev_lock); | |
157 | return cdev; | |
158 | } | |
159 | } | |
160 | read_unlock(&cnic_dev_lock); | |
161 | return NULL; | |
162 | } | |
163 | ||
7fc1ece4 MC |
164 | static inline void ulp_get(struct cnic_ulp_ops *ulp_ops) |
165 | { | |
166 | atomic_inc(&ulp_ops->ref_count); | |
167 | } | |
168 | ||
169 | static inline void ulp_put(struct cnic_ulp_ops *ulp_ops) | |
170 | { | |
171 | atomic_dec(&ulp_ops->ref_count); | |
172 | } | |
173 | ||
a4636960 MC |
174 | static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val) |
175 | { | |
176 | struct cnic_local *cp = dev->cnic_priv; | |
177 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
178 | struct drv_ctl_info info; | |
179 | struct drv_ctl_io *io = &info.data.io; | |
180 | ||
181 | info.cmd = DRV_CTL_CTX_WR_CMD; | |
182 | io->cid_addr = cid_addr; | |
183 | io->offset = off; | |
184 | io->data = val; | |
185 | ethdev->drv_ctl(dev->netdev, &info); | |
186 | } | |
187 | ||
71034ba8 MC |
188 | static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr) |
189 | { | |
190 | struct cnic_local *cp = dev->cnic_priv; | |
191 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
192 | struct drv_ctl_info info; | |
193 | struct drv_ctl_io *io = &info.data.io; | |
194 | ||
195 | info.cmd = DRV_CTL_CTXTBL_WR_CMD; | |
196 | io->offset = off; | |
197 | io->dma_addr = addr; | |
198 | ethdev->drv_ctl(dev->netdev, &info); | |
199 | } | |
200 | ||
201 | static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start) | |
202 | { | |
203 | struct cnic_local *cp = dev->cnic_priv; | |
204 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
205 | struct drv_ctl_info info; | |
206 | struct drv_ctl_l2_ring *ring = &info.data.ring; | |
207 | ||
208 | if (start) | |
209 | info.cmd = DRV_CTL_START_L2_CMD; | |
210 | else | |
211 | info.cmd = DRV_CTL_STOP_L2_CMD; | |
212 | ||
213 | ring->cid = cid; | |
214 | ring->client_id = cl_id; | |
215 | ethdev->drv_ctl(dev->netdev, &info); | |
216 | } | |
217 | ||
a4636960 MC |
218 | static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val) |
219 | { | |
220 | struct cnic_local *cp = dev->cnic_priv; | |
221 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
222 | struct drv_ctl_info info; | |
223 | struct drv_ctl_io *io = &info.data.io; | |
224 | ||
225 | info.cmd = DRV_CTL_IO_WR_CMD; | |
226 | io->offset = off; | |
227 | io->data = val; | |
228 | ethdev->drv_ctl(dev->netdev, &info); | |
229 | } | |
230 | ||
231 | static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off) | |
232 | { | |
233 | struct cnic_local *cp = dev->cnic_priv; | |
234 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
235 | struct drv_ctl_info info; | |
236 | struct drv_ctl_io *io = &info.data.io; | |
237 | ||
238 | info.cmd = DRV_CTL_IO_RD_CMD; | |
239 | io->offset = off; | |
240 | ethdev->drv_ctl(dev->netdev, &info); | |
241 | return io->data; | |
242 | } | |
243 | ||
244 | static int cnic_in_use(struct cnic_sock *csk) | |
245 | { | |
246 | return test_bit(SK_F_INUSE, &csk->flags); | |
247 | } | |
248 | ||
c2bff63f | 249 | static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count) |
a4636960 MC |
250 | { |
251 | struct cnic_local *cp = dev->cnic_priv; | |
252 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
253 | struct drv_ctl_info info; | |
254 | ||
c2bff63f DK |
255 | info.cmd = cmd; |
256 | info.data.credit.credit_count = count; | |
a4636960 MC |
257 | ethdev->drv_ctl(dev->netdev, &info); |
258 | } | |
259 | ||
71034ba8 MC |
260 | static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid) |
261 | { | |
262 | u32 i; | |
263 | ||
520efdf4 | 264 | for (i = 0; i < cp->max_cid_space; i++) { |
71034ba8 MC |
265 | if (cp->ctx_tbl[i].cid == cid) { |
266 | *l5_cid = i; | |
267 | return 0; | |
268 | } | |
269 | } | |
270 | return -EINVAL; | |
271 | } | |
272 | ||
a4636960 MC |
273 | static int cnic_send_nlmsg(struct cnic_local *cp, u32 type, |
274 | struct cnic_sock *csk) | |
275 | { | |
276 | struct iscsi_path path_req; | |
277 | char *buf = NULL; | |
278 | u16 len = 0; | |
279 | u32 msg_type = ISCSI_KEVENT_IF_DOWN; | |
280 | struct cnic_ulp_ops *ulp_ops; | |
cd801536 | 281 | struct cnic_uio_dev *udev = cp->udev; |
939b82e5 | 282 | int rc = 0, retry = 0; |
a4636960 | 283 | |
cd801536 | 284 | if (!udev || udev->uio_dev == -1) |
a4636960 MC |
285 | return -ENODEV; |
286 | ||
287 | if (csk) { | |
288 | len = sizeof(path_req); | |
289 | buf = (char *) &path_req; | |
290 | memset(&path_req, 0, len); | |
291 | ||
292 | msg_type = ISCSI_KEVENT_PATH_REQ; | |
293 | path_req.handle = (u64) csk->l5_cid; | |
294 | if (test_bit(SK_F_IPV6, &csk->flags)) { | |
295 | memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0], | |
296 | sizeof(struct in6_addr)); | |
297 | path_req.ip_addr_len = 16; | |
298 | } else { | |
299 | memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0], | |
300 | sizeof(struct in_addr)); | |
301 | path_req.ip_addr_len = 4; | |
302 | } | |
303 | path_req.vlan_id = csk->vlan_id; | |
304 | path_req.pmtu = csk->mtu; | |
305 | } | |
306 | ||
939b82e5 MC |
307 | while (retry < 3) { |
308 | rc = 0; | |
309 | rcu_read_lock(); | |
310 | ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]); | |
311 | if (ulp_ops) | |
312 | rc = ulp_ops->iscsi_nl_send_msg( | |
313 | cp->ulp_handle[CNIC_ULP_ISCSI], | |
314 | msg_type, buf, len); | |
315 | rcu_read_unlock(); | |
316 | if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ) | |
317 | break; | |
318 | ||
319 | msleep(100); | |
320 | retry++; | |
321 | } | |
a4636960 MC |
322 | return 0; |
323 | } | |
324 | ||
42ecbb84 EW |
325 | static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8); |
326 | ||
a4636960 MC |
327 | static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type, |
328 | char *buf, u16 len) | |
329 | { | |
330 | int rc = -EINVAL; | |
331 | ||
332 | switch (msg_type) { | |
333 | case ISCSI_UEVENT_PATH_UPDATE: { | |
334 | struct cnic_local *cp; | |
335 | u32 l5_cid; | |
336 | struct cnic_sock *csk; | |
337 | struct iscsi_path *path_resp; | |
338 | ||
339 | if (len < sizeof(*path_resp)) | |
340 | break; | |
341 | ||
342 | path_resp = (struct iscsi_path *) buf; | |
343 | cp = dev->cnic_priv; | |
344 | l5_cid = (u32) path_resp->handle; | |
345 | if (l5_cid >= MAX_CM_SK_TBL_SZ) | |
346 | break; | |
347 | ||
d02a5e6c MC |
348 | rcu_read_lock(); |
349 | if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) { | |
350 | rc = -ENODEV; | |
351 | rcu_read_unlock(); | |
352 | break; | |
353 | } | |
a4636960 MC |
354 | csk = &cp->csk_tbl[l5_cid]; |
355 | csk_hold(csk); | |
42ecbb84 EW |
356 | if (cnic_in_use(csk) && |
357 | test_bit(SK_F_CONNECT_START, &csk->flags)) { | |
358 | ||
a4636960 MC |
359 | memcpy(csk->ha, path_resp->mac_addr, 6); |
360 | if (test_bit(SK_F_IPV6, &csk->flags)) | |
361 | memcpy(&csk->src_ip[0], &path_resp->src.v6_addr, | |
362 | sizeof(struct in6_addr)); | |
363 | else | |
364 | memcpy(&csk->src_ip[0], &path_resp->src.v4_addr, | |
365 | sizeof(struct in_addr)); | |
42ecbb84 EW |
366 | |
367 | if (is_valid_ether_addr(csk->ha)) { | |
a4636960 | 368 | cnic_cm_set_pg(csk); |
42ecbb84 EW |
369 | } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) && |
370 | !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) { | |
371 | ||
372 | cnic_cm_upcall(cp, csk, | |
373 | L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE); | |
374 | clear_bit(SK_F_CONNECT_START, &csk->flags); | |
375 | } | |
a4636960 MC |
376 | } |
377 | csk_put(csk); | |
d02a5e6c | 378 | rcu_read_unlock(); |
a4636960 MC |
379 | rc = 0; |
380 | } | |
381 | } | |
382 | ||
383 | return rc; | |
384 | } | |
385 | ||
386 | static int cnic_offld_prep(struct cnic_sock *csk) | |
387 | { | |
388 | if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags)) | |
389 | return 0; | |
390 | ||
391 | if (!test_bit(SK_F_CONNECT_START, &csk->flags)) { | |
392 | clear_bit(SK_F_OFFLD_SCHED, &csk->flags); | |
393 | return 0; | |
394 | } | |
395 | ||
396 | return 1; | |
397 | } | |
398 | ||
399 | static int cnic_close_prep(struct cnic_sock *csk) | |
400 | { | |
401 | clear_bit(SK_F_CONNECT_START, &csk->flags); | |
402 | smp_mb__after_clear_bit(); | |
403 | ||
404 | if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) { | |
405 | while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags)) | |
406 | msleep(1); | |
407 | ||
408 | return 1; | |
409 | } | |
410 | return 0; | |
411 | } | |
412 | ||
413 | static int cnic_abort_prep(struct cnic_sock *csk) | |
414 | { | |
415 | clear_bit(SK_F_CONNECT_START, &csk->flags); | |
416 | smp_mb__after_clear_bit(); | |
417 | ||
418 | while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags)) | |
419 | msleep(1); | |
420 | ||
421 | if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) { | |
422 | csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP; | |
423 | return 1; | |
424 | } | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops) | |
430 | { | |
431 | struct cnic_dev *dev; | |
432 | ||
0d37f36f | 433 | if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) { |
ddf79b20 | 434 | pr_err("%s: Bad type %d\n", __func__, ulp_type); |
a4636960 MC |
435 | return -EINVAL; |
436 | } | |
437 | mutex_lock(&cnic_lock); | |
438 | if (cnic_ulp_tbl[ulp_type]) { | |
ddf79b20 JP |
439 | pr_err("%s: Type %d has already been registered\n", |
440 | __func__, ulp_type); | |
a4636960 MC |
441 | mutex_unlock(&cnic_lock); |
442 | return -EBUSY; | |
443 | } | |
444 | ||
445 | read_lock(&cnic_dev_lock); | |
446 | list_for_each_entry(dev, &cnic_dev_list, list) { | |
447 | struct cnic_local *cp = dev->cnic_priv; | |
448 | ||
449 | clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]); | |
450 | } | |
451 | read_unlock(&cnic_dev_lock); | |
452 | ||
7fc1ece4 | 453 | atomic_set(&ulp_ops->ref_count, 0); |
a4636960 MC |
454 | rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops); |
455 | mutex_unlock(&cnic_lock); | |
456 | ||
457 | /* Prevent race conditions with netdev_event */ | |
458 | rtnl_lock(); | |
a4636960 MC |
459 | list_for_each_entry(dev, &cnic_dev_list, list) { |
460 | struct cnic_local *cp = dev->cnic_priv; | |
461 | ||
462 | if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type])) | |
463 | ulp_ops->cnic_init(dev); | |
464 | } | |
a4636960 MC |
465 | rtnl_unlock(); |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | int cnic_unregister_driver(int ulp_type) | |
471 | { | |
472 | struct cnic_dev *dev; | |
7fc1ece4 MC |
473 | struct cnic_ulp_ops *ulp_ops; |
474 | int i = 0; | |
a4636960 | 475 | |
0d37f36f | 476 | if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) { |
ddf79b20 | 477 | pr_err("%s: Bad type %d\n", __func__, ulp_type); |
a4636960 MC |
478 | return -EINVAL; |
479 | } | |
480 | mutex_lock(&cnic_lock); | |
7fc1ece4 MC |
481 | ulp_ops = cnic_ulp_tbl[ulp_type]; |
482 | if (!ulp_ops) { | |
ddf79b20 JP |
483 | pr_err("%s: Type %d has not been registered\n", |
484 | __func__, ulp_type); | |
a4636960 MC |
485 | goto out_unlock; |
486 | } | |
487 | read_lock(&cnic_dev_lock); | |
488 | list_for_each_entry(dev, &cnic_dev_list, list) { | |
489 | struct cnic_local *cp = dev->cnic_priv; | |
490 | ||
491 | if (rcu_dereference(cp->ulp_ops[ulp_type])) { | |
ddf79b20 JP |
492 | pr_err("%s: Type %d still has devices registered\n", |
493 | __func__, ulp_type); | |
a4636960 MC |
494 | read_unlock(&cnic_dev_lock); |
495 | goto out_unlock; | |
496 | } | |
497 | } | |
498 | read_unlock(&cnic_dev_lock); | |
499 | ||
500 | rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL); | |
501 | ||
502 | mutex_unlock(&cnic_lock); | |
503 | synchronize_rcu(); | |
7fc1ece4 MC |
504 | while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) { |
505 | msleep(100); | |
506 | i++; | |
507 | } | |
508 | ||
509 | if (atomic_read(&ulp_ops->ref_count) != 0) | |
ddf79b20 | 510 | netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n"); |
a4636960 MC |
511 | return 0; |
512 | ||
513 | out_unlock: | |
514 | mutex_unlock(&cnic_lock); | |
515 | return -EINVAL; | |
516 | } | |
517 | ||
518 | static int cnic_start_hw(struct cnic_dev *); | |
519 | static void cnic_stop_hw(struct cnic_dev *); | |
520 | ||
521 | static int cnic_register_device(struct cnic_dev *dev, int ulp_type, | |
522 | void *ulp_ctx) | |
523 | { | |
524 | struct cnic_local *cp = dev->cnic_priv; | |
525 | struct cnic_ulp_ops *ulp_ops; | |
526 | ||
0d37f36f | 527 | if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) { |
ddf79b20 | 528 | pr_err("%s: Bad type %d\n", __func__, ulp_type); |
a4636960 MC |
529 | return -EINVAL; |
530 | } | |
531 | mutex_lock(&cnic_lock); | |
532 | if (cnic_ulp_tbl[ulp_type] == NULL) { | |
ddf79b20 JP |
533 | pr_err("%s: Driver with type %d has not been registered\n", |
534 | __func__, ulp_type); | |
a4636960 MC |
535 | mutex_unlock(&cnic_lock); |
536 | return -EAGAIN; | |
537 | } | |
538 | if (rcu_dereference(cp->ulp_ops[ulp_type])) { | |
ddf79b20 JP |
539 | pr_err("%s: Type %d has already been registered to this device\n", |
540 | __func__, ulp_type); | |
a4636960 MC |
541 | mutex_unlock(&cnic_lock); |
542 | return -EBUSY; | |
543 | } | |
544 | ||
545 | clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]); | |
546 | cp->ulp_handle[ulp_type] = ulp_ctx; | |
547 | ulp_ops = cnic_ulp_tbl[ulp_type]; | |
548 | rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops); | |
549 | cnic_hold(dev); | |
550 | ||
551 | if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) | |
552 | if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type])) | |
553 | ulp_ops->cnic_start(cp->ulp_handle[ulp_type]); | |
554 | ||
555 | mutex_unlock(&cnic_lock); | |
556 | ||
557 | return 0; | |
558 | ||
559 | } | |
560 | EXPORT_SYMBOL(cnic_register_driver); | |
561 | ||
562 | static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type) | |
563 | { | |
564 | struct cnic_local *cp = dev->cnic_priv; | |
681dbd71 | 565 | int i = 0; |
a4636960 | 566 | |
0d37f36f | 567 | if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) { |
ddf79b20 | 568 | pr_err("%s: Bad type %d\n", __func__, ulp_type); |
a4636960 MC |
569 | return -EINVAL; |
570 | } | |
571 | mutex_lock(&cnic_lock); | |
572 | if (rcu_dereference(cp->ulp_ops[ulp_type])) { | |
573 | rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL); | |
574 | cnic_put(dev); | |
575 | } else { | |
ddf79b20 JP |
576 | pr_err("%s: device not registered to this ulp type %d\n", |
577 | __func__, ulp_type); | |
a4636960 MC |
578 | mutex_unlock(&cnic_lock); |
579 | return -EINVAL; | |
580 | } | |
581 | mutex_unlock(&cnic_lock); | |
582 | ||
42bb8d56 MC |
583 | if (ulp_type == CNIC_ULP_ISCSI) |
584 | cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL); | |
585 | ||
a4636960 MC |
586 | synchronize_rcu(); |
587 | ||
681dbd71 MC |
588 | while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) && |
589 | i < 20) { | |
590 | msleep(100); | |
591 | i++; | |
592 | } | |
593 | if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type])) | |
ddf79b20 | 594 | netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n"); |
681dbd71 | 595 | |
a4636960 MC |
596 | return 0; |
597 | } | |
598 | EXPORT_SYMBOL(cnic_unregister_driver); | |
599 | ||
600 | static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id) | |
601 | { | |
602 | id_tbl->start = start_id; | |
603 | id_tbl->max = size; | |
604 | id_tbl->next = 0; | |
605 | spin_lock_init(&id_tbl->lock); | |
606 | id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL); | |
607 | if (!id_tbl->table) | |
608 | return -ENOMEM; | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl) | |
614 | { | |
615 | kfree(id_tbl->table); | |
616 | id_tbl->table = NULL; | |
617 | } | |
618 | ||
619 | static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id) | |
620 | { | |
621 | int ret = -1; | |
622 | ||
623 | id -= id_tbl->start; | |
624 | if (id >= id_tbl->max) | |
625 | return ret; | |
626 | ||
627 | spin_lock(&id_tbl->lock); | |
628 | if (!test_bit(id, id_tbl->table)) { | |
629 | set_bit(id, id_tbl->table); | |
630 | ret = 0; | |
631 | } | |
632 | spin_unlock(&id_tbl->lock); | |
633 | return ret; | |
634 | } | |
635 | ||
636 | /* Returns -1 if not successful */ | |
637 | static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl) | |
638 | { | |
639 | u32 id; | |
640 | ||
641 | spin_lock(&id_tbl->lock); | |
642 | id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next); | |
643 | if (id >= id_tbl->max) { | |
644 | id = -1; | |
645 | if (id_tbl->next != 0) { | |
646 | id = find_first_zero_bit(id_tbl->table, id_tbl->next); | |
647 | if (id >= id_tbl->next) | |
648 | id = -1; | |
649 | } | |
650 | } | |
651 | ||
652 | if (id < id_tbl->max) { | |
653 | set_bit(id, id_tbl->table); | |
654 | id_tbl->next = (id + 1) & (id_tbl->max - 1); | |
655 | id += id_tbl->start; | |
656 | } | |
657 | ||
658 | spin_unlock(&id_tbl->lock); | |
659 | ||
660 | return id; | |
661 | } | |
662 | ||
663 | static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id) | |
664 | { | |
665 | if (id == -1) | |
666 | return; | |
667 | ||
668 | id -= id_tbl->start; | |
669 | if (id >= id_tbl->max) | |
670 | return; | |
671 | ||
672 | clear_bit(id, id_tbl->table); | |
673 | } | |
674 | ||
675 | static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma) | |
676 | { | |
677 | int i; | |
678 | ||
679 | if (!dma->pg_arr) | |
680 | return; | |
681 | ||
682 | for (i = 0; i < dma->num_pages; i++) { | |
683 | if (dma->pg_arr[i]) { | |
3248e168 MC |
684 | dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE, |
685 | dma->pg_arr[i], dma->pg_map_arr[i]); | |
a4636960 MC |
686 | dma->pg_arr[i] = NULL; |
687 | } | |
688 | } | |
689 | if (dma->pgtbl) { | |
3248e168 MC |
690 | dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size, |
691 | dma->pgtbl, dma->pgtbl_map); | |
a4636960 MC |
692 | dma->pgtbl = NULL; |
693 | } | |
694 | kfree(dma->pg_arr); | |
695 | dma->pg_arr = NULL; | |
696 | dma->num_pages = 0; | |
697 | } | |
698 | ||
699 | static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma) | |
700 | { | |
701 | int i; | |
5138826b | 702 | __le32 *page_table = (__le32 *) dma->pgtbl; |
a4636960 MC |
703 | |
704 | for (i = 0; i < dma->num_pages; i++) { | |
705 | /* Each entry needs to be in big endian format. */ | |
5138826b | 706 | *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32); |
a4636960 | 707 | page_table++; |
5138826b | 708 | *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff); |
a4636960 MC |
709 | page_table++; |
710 | } | |
711 | } | |
712 | ||
71034ba8 MC |
713 | static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma) |
714 | { | |
715 | int i; | |
5138826b | 716 | __le32 *page_table = (__le32 *) dma->pgtbl; |
71034ba8 MC |
717 | |
718 | for (i = 0; i < dma->num_pages; i++) { | |
719 | /* Each entry needs to be in little endian format. */ | |
5138826b | 720 | *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff); |
71034ba8 | 721 | page_table++; |
5138826b | 722 | *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32); |
71034ba8 MC |
723 | page_table++; |
724 | } | |
725 | } | |
726 | ||
a4636960 MC |
727 | static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma, |
728 | int pages, int use_pg_tbl) | |
729 | { | |
730 | int i, size; | |
731 | struct cnic_local *cp = dev->cnic_priv; | |
732 | ||
733 | size = pages * (sizeof(void *) + sizeof(dma_addr_t)); | |
734 | dma->pg_arr = kzalloc(size, GFP_ATOMIC); | |
735 | if (dma->pg_arr == NULL) | |
736 | return -ENOMEM; | |
737 | ||
738 | dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages); | |
739 | dma->num_pages = pages; | |
740 | ||
741 | for (i = 0; i < pages; i++) { | |
3248e168 MC |
742 | dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev, |
743 | BCM_PAGE_SIZE, | |
744 | &dma->pg_map_arr[i], | |
745 | GFP_ATOMIC); | |
a4636960 MC |
746 | if (dma->pg_arr[i] == NULL) |
747 | goto error; | |
748 | } | |
749 | if (!use_pg_tbl) | |
750 | return 0; | |
751 | ||
752 | dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) & | |
753 | ~(BCM_PAGE_SIZE - 1); | |
3248e168 MC |
754 | dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size, |
755 | &dma->pgtbl_map, GFP_ATOMIC); | |
a4636960 MC |
756 | if (dma->pgtbl == NULL) |
757 | goto error; | |
758 | ||
759 | cp->setup_pgtbl(dev, dma); | |
760 | ||
761 | return 0; | |
762 | ||
763 | error: | |
764 | cnic_free_dma(dev, dma); | |
765 | return -ENOMEM; | |
766 | } | |
767 | ||
86b53606 MC |
768 | static void cnic_free_context(struct cnic_dev *dev) |
769 | { | |
770 | struct cnic_local *cp = dev->cnic_priv; | |
771 | int i; | |
772 | ||
773 | for (i = 0; i < cp->ctx_blks; i++) { | |
774 | if (cp->ctx_arr[i].ctx) { | |
3248e168 MC |
775 | dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size, |
776 | cp->ctx_arr[i].ctx, | |
777 | cp->ctx_arr[i].mapping); | |
86b53606 MC |
778 | cp->ctx_arr[i].ctx = NULL; |
779 | } | |
780 | } | |
781 | } | |
782 | ||
cd801536 | 783 | static void __cnic_free_uio(struct cnic_uio_dev *udev) |
a4636960 | 784 | { |
cd801536 | 785 | uio_unregister_device(&udev->cnic_uinfo); |
c06c0462 | 786 | |
cd801536 MC |
787 | if (udev->l2_buf) { |
788 | dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size, | |
789 | udev->l2_buf, udev->l2_buf_map); | |
790 | udev->l2_buf = NULL; | |
a4636960 MC |
791 | } |
792 | ||
cd801536 MC |
793 | if (udev->l2_ring) { |
794 | dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size, | |
795 | udev->l2_ring, udev->l2_ring_map); | |
796 | udev->l2_ring = NULL; | |
a4636960 | 797 | } |
a3ceeeb8 MC |
798 | |
799 | pci_dev_put(udev->pdev); | |
800 | kfree(udev); | |
c06c0462 MC |
801 | } |
802 | ||
cd801536 | 803 | static void cnic_free_uio(struct cnic_uio_dev *udev) |
c06c0462 | 804 | { |
cd801536 | 805 | if (!udev) |
c06c0462 MC |
806 | return; |
807 | ||
a3ceeeb8 MC |
808 | write_lock(&cnic_dev_lock); |
809 | list_del_init(&udev->list); | |
810 | write_unlock(&cnic_dev_lock); | |
cd801536 | 811 | __cnic_free_uio(udev); |
c06c0462 MC |
812 | } |
813 | ||
814 | static void cnic_free_resc(struct cnic_dev *dev) | |
815 | { | |
816 | struct cnic_local *cp = dev->cnic_priv; | |
cd801536 | 817 | struct cnic_uio_dev *udev = cp->udev; |
c06c0462 | 818 | |
cd801536 | 819 | if (udev) { |
a3ceeeb8 | 820 | udev->dev = NULL; |
cd801536 | 821 | cp->udev = NULL; |
c06c0462 | 822 | } |
a4636960 | 823 | |
86b53606 | 824 | cnic_free_context(dev); |
a4636960 MC |
825 | kfree(cp->ctx_arr); |
826 | cp->ctx_arr = NULL; | |
827 | cp->ctx_blks = 0; | |
828 | ||
829 | cnic_free_dma(dev, &cp->gbl_buf_info); | |
830 | cnic_free_dma(dev, &cp->conn_buf_info); | |
831 | cnic_free_dma(dev, &cp->kwq_info); | |
71034ba8 | 832 | cnic_free_dma(dev, &cp->kwq_16_data_info); |
e21ba414 | 833 | cnic_free_dma(dev, &cp->kcq2.dma); |
e6c28894 | 834 | cnic_free_dma(dev, &cp->kcq1.dma); |
a4636960 MC |
835 | kfree(cp->iscsi_tbl); |
836 | cp->iscsi_tbl = NULL; | |
837 | kfree(cp->ctx_tbl); | |
838 | cp->ctx_tbl = NULL; | |
839 | ||
e1928c86 | 840 | cnic_free_id_tbl(&cp->fcoe_cid_tbl); |
a4636960 MC |
841 | cnic_free_id_tbl(&cp->cid_tbl); |
842 | } | |
843 | ||
844 | static int cnic_alloc_context(struct cnic_dev *dev) | |
845 | { | |
846 | struct cnic_local *cp = dev->cnic_priv; | |
847 | ||
848 | if (CHIP_NUM(cp) == CHIP_NUM_5709) { | |
849 | int i, k, arr_size; | |
850 | ||
851 | cp->ctx_blk_size = BCM_PAGE_SIZE; | |
852 | cp->cids_per_blk = BCM_PAGE_SIZE / 128; | |
853 | arr_size = BNX2_MAX_CID / cp->cids_per_blk * | |
854 | sizeof(struct cnic_ctx); | |
855 | cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL); | |
856 | if (cp->ctx_arr == NULL) | |
857 | return -ENOMEM; | |
858 | ||
859 | k = 0; | |
860 | for (i = 0; i < 2; i++) { | |
861 | u32 j, reg, off, lo, hi; | |
862 | ||
863 | if (i == 0) | |
864 | off = BNX2_PG_CTX_MAP; | |
865 | else | |
866 | off = BNX2_ISCSI_CTX_MAP; | |
867 | ||
868 | reg = cnic_reg_rd_ind(dev, off); | |
869 | lo = reg >> 16; | |
870 | hi = reg & 0xffff; | |
871 | for (j = lo; j < hi; j += cp->cids_per_blk, k++) | |
872 | cp->ctx_arr[k].cid = j; | |
873 | } | |
874 | ||
875 | cp->ctx_blks = k; | |
876 | if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) { | |
877 | cp->ctx_blks = 0; | |
878 | return -ENOMEM; | |
879 | } | |
880 | ||
881 | for (i = 0; i < cp->ctx_blks; i++) { | |
882 | cp->ctx_arr[i].ctx = | |
3248e168 MC |
883 | dma_alloc_coherent(&dev->pcidev->dev, |
884 | BCM_PAGE_SIZE, | |
885 | &cp->ctx_arr[i].mapping, | |
886 | GFP_KERNEL); | |
a4636960 MC |
887 | if (cp->ctx_arr[i].ctx == NULL) |
888 | return -ENOMEM; | |
889 | } | |
890 | } | |
891 | return 0; | |
892 | } | |
893 | ||
e6c28894 MC |
894 | static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info) |
895 | { | |
896 | int err, i, is_bnx2 = 0; | |
897 | struct kcqe **kcq; | |
898 | ||
899 | if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) | |
900 | is_bnx2 = 1; | |
901 | ||
902 | err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2); | |
903 | if (err) | |
904 | return err; | |
905 | ||
906 | kcq = (struct kcqe **) info->dma.pg_arr; | |
907 | info->kcq = kcq; | |
908 | ||
909 | if (is_bnx2) | |
910 | return 0; | |
911 | ||
912 | for (i = 0; i < KCQ_PAGE_CNT; i++) { | |
913 | struct bnx2x_bd_chain_next *next = | |
914 | (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT]; | |
915 | int j = i + 1; | |
916 | ||
917 | if (j >= KCQ_PAGE_CNT) | |
918 | j = 0; | |
919 | next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32; | |
920 | next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff; | |
921 | } | |
922 | return 0; | |
923 | } | |
924 | ||
cd801536 | 925 | static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages) |
ec0248ea MC |
926 | { |
927 | struct cnic_local *cp = dev->cnic_priv; | |
cd801536 MC |
928 | struct cnic_uio_dev *udev; |
929 | ||
a3ceeeb8 MC |
930 | read_lock(&cnic_dev_lock); |
931 | list_for_each_entry(udev, &cnic_udev_list, list) { | |
932 | if (udev->pdev == dev->pcidev) { | |
933 | udev->dev = dev; | |
934 | cp->udev = udev; | |
935 | read_unlock(&cnic_dev_lock); | |
936 | return 0; | |
937 | } | |
938 | } | |
939 | read_unlock(&cnic_dev_lock); | |
940 | ||
cd801536 MC |
941 | udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC); |
942 | if (!udev) | |
943 | return -ENOMEM; | |
944 | ||
945 | udev->uio_dev = -1; | |
ec0248ea | 946 | |
cd801536 MC |
947 | udev->dev = dev; |
948 | udev->pdev = dev->pcidev; | |
949 | udev->l2_ring_size = pages * BCM_PAGE_SIZE; | |
950 | udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size, | |
951 | &udev->l2_ring_map, | |
952 | GFP_KERNEL | __GFP_COMP); | |
953 | if (!udev->l2_ring) | |
f7e4c977 | 954 | goto err_udev; |
ec0248ea | 955 | |
cd801536 MC |
956 | udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size; |
957 | udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size); | |
958 | udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size, | |
959 | &udev->l2_buf_map, | |
960 | GFP_KERNEL | __GFP_COMP); | |
961 | if (!udev->l2_buf) | |
f7e4c977 | 962 | goto err_dma; |
ec0248ea | 963 | |
a3ceeeb8 MC |
964 | write_lock(&cnic_dev_lock); |
965 | list_add(&udev->list, &cnic_udev_list); | |
966 | write_unlock(&cnic_dev_lock); | |
967 | ||
968 | pci_dev_get(udev->pdev); | |
969 | ||
cd801536 MC |
970 | cp->udev = udev; |
971 | ||
ec0248ea | 972 | return 0; |
f7e4c977 JJ |
973 | err_dma: |
974 | dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size, | |
975 | udev->l2_ring, udev->l2_ring_map); | |
976 | err_udev: | |
977 | kfree(udev); | |
978 | return -ENOMEM; | |
ec0248ea MC |
979 | } |
980 | ||
cd801536 MC |
981 | static int cnic_init_uio(struct cnic_dev *dev) |
982 | { | |
a4636960 | 983 | struct cnic_local *cp = dev->cnic_priv; |
cd801536 | 984 | struct cnic_uio_dev *udev = cp->udev; |
a4636960 | 985 | struct uio_info *uinfo; |
cd801536 | 986 | int ret = 0; |
a4636960 | 987 | |
cd801536 | 988 | if (!udev) |
5e9b2dbf | 989 | return -ENOMEM; |
a4636960 | 990 | |
cd801536 MC |
991 | uinfo = &udev->cnic_uinfo; |
992 | ||
a4636960 MC |
993 | uinfo->mem[0].addr = dev->netdev->base_addr; |
994 | uinfo->mem[0].internal_addr = dev->regview; | |
995 | uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start; | |
996 | uinfo->mem[0].memtype = UIO_MEM_PHYS; | |
997 | ||
5e9b2dbf | 998 | if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) { |
a4dde3ab | 999 | uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen & |
cd801536 | 1000 | PAGE_MASK; |
5e9b2dbf MC |
1001 | if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) |
1002 | uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9; | |
1003 | else | |
1004 | uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE; | |
1005 | ||
1006 | uinfo->name = "bnx2_cnic"; | |
71034ba8 MC |
1007 | } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) { |
1008 | uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk & | |
1009 | PAGE_MASK; | |
523224a3 | 1010 | uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk); |
71034ba8 MC |
1011 | |
1012 | uinfo->name = "bnx2x_cnic"; | |
5e9b2dbf MC |
1013 | } |
1014 | ||
a4636960 MC |
1015 | uinfo->mem[1].memtype = UIO_MEM_LOGICAL; |
1016 | ||
cd801536 MC |
1017 | uinfo->mem[2].addr = (unsigned long) udev->l2_ring; |
1018 | uinfo->mem[2].size = udev->l2_ring_size; | |
a4636960 MC |
1019 | uinfo->mem[2].memtype = UIO_MEM_LOGICAL; |
1020 | ||
cd801536 MC |
1021 | uinfo->mem[3].addr = (unsigned long) udev->l2_buf; |
1022 | uinfo->mem[3].size = udev->l2_buf_size; | |
a4636960 MC |
1023 | uinfo->mem[3].memtype = UIO_MEM_LOGICAL; |
1024 | ||
a4636960 MC |
1025 | uinfo->version = CNIC_MODULE_VERSION; |
1026 | uinfo->irq = UIO_IRQ_CUSTOM; | |
1027 | ||
1028 | uinfo->open = cnic_uio_open; | |
1029 | uinfo->release = cnic_uio_close; | |
1030 | ||
a3ceeeb8 MC |
1031 | if (udev->uio_dev == -1) { |
1032 | if (!uinfo->priv) { | |
1033 | uinfo->priv = udev; | |
a4636960 | 1034 | |
a3ceeeb8 MC |
1035 | ret = uio_register_device(&udev->pdev->dev, uinfo); |
1036 | } | |
1037 | } else { | |
1038 | cnic_init_rings(dev); | |
1039 | } | |
a4636960 | 1040 | |
cd801536 | 1041 | return ret; |
5e9b2dbf MC |
1042 | } |
1043 | ||
1044 | static int cnic_alloc_bnx2_resc(struct cnic_dev *dev) | |
1045 | { | |
1046 | struct cnic_local *cp = dev->cnic_priv; | |
1047 | int ret; | |
1048 | ||
1049 | ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1); | |
1050 | if (ret) | |
1051 | goto error; | |
1052 | cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr; | |
1053 | ||
e6c28894 | 1054 | ret = cnic_alloc_kcq(dev, &cp->kcq1); |
5e9b2dbf MC |
1055 | if (ret) |
1056 | goto error; | |
5e9b2dbf MC |
1057 | |
1058 | ret = cnic_alloc_context(dev); | |
1059 | if (ret) | |
1060 | goto error; | |
1061 | ||
cd801536 | 1062 | ret = cnic_alloc_uio_rings(dev, 2); |
5e9b2dbf MC |
1063 | if (ret) |
1064 | goto error; | |
1065 | ||
cd801536 | 1066 | ret = cnic_init_uio(dev); |
5e9b2dbf MC |
1067 | if (ret) |
1068 | goto error; | |
a4636960 MC |
1069 | |
1070 | return 0; | |
1071 | ||
1072 | error: | |
1073 | cnic_free_resc(dev); | |
1074 | return ret; | |
1075 | } | |
1076 | ||
71034ba8 MC |
1077 | static int cnic_alloc_bnx2x_context(struct cnic_dev *dev) |
1078 | { | |
1079 | struct cnic_local *cp = dev->cnic_priv; | |
71034ba8 | 1080 | int ctx_blk_size = cp->ethdev->ctx_blk_size; |
520efdf4 | 1081 | int total_mem, blks, i; |
71034ba8 | 1082 | |
520efdf4 | 1083 | total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space; |
71034ba8 MC |
1084 | blks = total_mem / ctx_blk_size; |
1085 | if (total_mem % ctx_blk_size) | |
1086 | blks++; | |
1087 | ||
1088 | if (blks > cp->ethdev->ctx_tbl_len) | |
1089 | return -ENOMEM; | |
1090 | ||
baeb2ffa | 1091 | cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL); |
71034ba8 MC |
1092 | if (cp->ctx_arr == NULL) |
1093 | return -ENOMEM; | |
1094 | ||
1095 | cp->ctx_blks = blks; | |
1096 | cp->ctx_blk_size = ctx_blk_size; | |
ee87a82a | 1097 | if (!BNX2X_CHIP_IS_57710(cp->chip_id)) |
71034ba8 MC |
1098 | cp->ctx_align = 0; |
1099 | else | |
1100 | cp->ctx_align = ctx_blk_size; | |
1101 | ||
1102 | cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE; | |
1103 | ||
1104 | for (i = 0; i < blks; i++) { | |
1105 | cp->ctx_arr[i].ctx = | |
3248e168 MC |
1106 | dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size, |
1107 | &cp->ctx_arr[i].mapping, | |
1108 | GFP_KERNEL); | |
71034ba8 MC |
1109 | if (cp->ctx_arr[i].ctx == NULL) |
1110 | return -ENOMEM; | |
1111 | ||
1112 | if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) { | |
1113 | if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) { | |
1114 | cnic_free_context(dev); | |
1115 | cp->ctx_blk_size += cp->ctx_align; | |
1116 | i = -1; | |
1117 | continue; | |
1118 | } | |
1119 | } | |
1120 | } | |
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev) | |
1125 | { | |
1126 | struct cnic_local *cp = dev->cnic_priv; | |
520efdf4 MC |
1127 | struct cnic_eth_dev *ethdev = cp->ethdev; |
1128 | u32 start_cid = ethdev->starting_cid; | |
71034ba8 MC |
1129 | int i, j, n, ret, pages; |
1130 | struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info; | |
1131 | ||
523224a3 DK |
1132 | cp->iro_arr = ethdev->iro_arr; |
1133 | ||
e1928c86 | 1134 | cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS; |
520efdf4 | 1135 | cp->iscsi_start_cid = start_cid; |
e1928c86 MC |
1136 | cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ; |
1137 | ||
1138 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { | |
1139 | cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS; | |
1140 | cp->fcoe_init_cid = ethdev->fcoe_init_cid; | |
1141 | if (!cp->fcoe_init_cid) | |
1142 | cp->fcoe_init_cid = 0x10; | |
1143 | } | |
1144 | ||
520efdf4 MC |
1145 | if (start_cid < BNX2X_ISCSI_START_CID) { |
1146 | u32 delta = BNX2X_ISCSI_START_CID - start_cid; | |
1147 | ||
1148 | cp->iscsi_start_cid = BNX2X_ISCSI_START_CID; | |
e1928c86 | 1149 | cp->fcoe_start_cid += delta; |
520efdf4 MC |
1150 | cp->max_cid_space += delta; |
1151 | } | |
1152 | ||
71034ba8 MC |
1153 | cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ, |
1154 | GFP_KERNEL); | |
1155 | if (!cp->iscsi_tbl) | |
1156 | goto error; | |
1157 | ||
1158 | cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) * | |
520efdf4 | 1159 | cp->max_cid_space, GFP_KERNEL); |
71034ba8 MC |
1160 | if (!cp->ctx_tbl) |
1161 | goto error; | |
1162 | ||
1163 | for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) { | |
1164 | cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i]; | |
1165 | cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI; | |
1166 | } | |
1167 | ||
e1928c86 MC |
1168 | for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++) |
1169 | cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE; | |
1170 | ||
520efdf4 | 1171 | pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) / |
71034ba8 MC |
1172 | PAGE_SIZE; |
1173 | ||
1174 | ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0); | |
1175 | if (ret) | |
1176 | return -ENOMEM; | |
1177 | ||
1178 | n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE; | |
520efdf4 | 1179 | for (i = 0, j = 0; i < cp->max_cid_space; i++) { |
71034ba8 MC |
1180 | long off = CNIC_KWQ16_DATA_SIZE * (i % n); |
1181 | ||
1182 | cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off; | |
1183 | cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] + | |
1184 | off; | |
1185 | ||
1186 | if ((i % n) == (n - 1)) | |
1187 | j++; | |
1188 | } | |
1189 | ||
e6c28894 | 1190 | ret = cnic_alloc_kcq(dev, &cp->kcq1); |
71034ba8 MC |
1191 | if (ret) |
1192 | goto error; | |
71034ba8 | 1193 | |
e21ba414 MC |
1194 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { |
1195 | ret = cnic_alloc_kcq(dev, &cp->kcq2); | |
1196 | if (ret) | |
1197 | goto error; | |
1198 | } | |
1199 | ||
71034ba8 MC |
1200 | pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS * |
1201 | BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE; | |
1202 | ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1); | |
1203 | if (ret) | |
1204 | goto error; | |
1205 | ||
1206 | pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE; | |
1207 | ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0); | |
1208 | if (ret) | |
1209 | goto error; | |
1210 | ||
1211 | ret = cnic_alloc_bnx2x_context(dev); | |
1212 | if (ret) | |
1213 | goto error; | |
1214 | ||
71034ba8 MC |
1215 | cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk; |
1216 | ||
1217 | cp->l2_rx_ring_size = 15; | |
1218 | ||
cd801536 | 1219 | ret = cnic_alloc_uio_rings(dev, 4); |
71034ba8 MC |
1220 | if (ret) |
1221 | goto error; | |
1222 | ||
cd801536 | 1223 | ret = cnic_init_uio(dev); |
71034ba8 MC |
1224 | if (ret) |
1225 | goto error; | |
1226 | ||
1227 | return 0; | |
1228 | ||
1229 | error: | |
1230 | cnic_free_resc(dev); | |
1231 | return -ENOMEM; | |
1232 | } | |
1233 | ||
a4636960 MC |
1234 | static inline u32 cnic_kwq_avail(struct cnic_local *cp) |
1235 | { | |
1236 | return cp->max_kwq_idx - | |
1237 | ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx); | |
1238 | } | |
1239 | ||
1240 | static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[], | |
1241 | u32 num_wqes) | |
1242 | { | |
1243 | struct cnic_local *cp = dev->cnic_priv; | |
1244 | struct kwqe *prod_qe; | |
1245 | u16 prod, sw_prod, i; | |
1246 | ||
1247 | if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) | |
1248 | return -EAGAIN; /* bnx2 is down */ | |
1249 | ||
1250 | spin_lock_bh(&cp->cnic_ulp_lock); | |
1251 | if (num_wqes > cnic_kwq_avail(cp) && | |
1f1332a3 | 1252 | !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) { |
a4636960 MC |
1253 | spin_unlock_bh(&cp->cnic_ulp_lock); |
1254 | return -EAGAIN; | |
1255 | } | |
1256 | ||
1f1332a3 | 1257 | clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags); |
a4636960 MC |
1258 | |
1259 | prod = cp->kwq_prod_idx; | |
1260 | sw_prod = prod & MAX_KWQ_IDX; | |
1261 | for (i = 0; i < num_wqes; i++) { | |
1262 | prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)]; | |
1263 | memcpy(prod_qe, wqes[i], sizeof(struct kwqe)); | |
1264 | prod++; | |
1265 | sw_prod = prod & MAX_KWQ_IDX; | |
1266 | } | |
1267 | cp->kwq_prod_idx = prod; | |
1268 | ||
1269 | CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx); | |
1270 | ||
1271 | spin_unlock_bh(&cp->cnic_ulp_lock); | |
1272 | return 0; | |
1273 | } | |
1274 | ||
71034ba8 MC |
1275 | static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid, |
1276 | union l5cm_specific_data *l5_data) | |
1277 | { | |
1278 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
1279 | dma_addr_t map; | |
1280 | ||
1281 | map = ctx->kwqe_data_mapping; | |
1282 | l5_data->phy_address.lo = (u64) map & 0xffffffff; | |
1283 | l5_data->phy_address.hi = (u64) map >> 32; | |
1284 | return ctx->kwqe_data; | |
1285 | } | |
1286 | ||
1287 | static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid, | |
1288 | u32 type, union l5cm_specific_data *l5_data) | |
1289 | { | |
1290 | struct cnic_local *cp = dev->cnic_priv; | |
1291 | struct l5cm_spe kwqe; | |
1292 | struct kwqe_16 *kwq[1]; | |
68d7c1aa | 1293 | u16 type_16; |
71034ba8 MC |
1294 | int ret; |
1295 | ||
1296 | kwqe.hdr.conn_and_cmd_data = | |
1297 | cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) | | |
ceb7e1c7 | 1298 | BNX2X_HW_CID(cp, cid))); |
68d7c1aa MC |
1299 | |
1300 | type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; | |
1301 | type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) & | |
1302 | SPE_HDR_FUNCTION_ID; | |
1303 | ||
1304 | kwqe.hdr.type = cpu_to_le16(type_16); | |
523224a3 | 1305 | kwqe.hdr.reserved1 = 0; |
71034ba8 MC |
1306 | kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo); |
1307 | kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi); | |
1308 | ||
1309 | kwq[0] = (struct kwqe_16 *) &kwqe; | |
1310 | ||
1311 | spin_lock_bh(&cp->cnic_ulp_lock); | |
1312 | ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1); | |
1313 | spin_unlock_bh(&cp->cnic_ulp_lock); | |
1314 | ||
1315 | if (ret == 1) | |
1316 | return 0; | |
1317 | ||
1318 | return -EBUSY; | |
1319 | } | |
1320 | ||
1321 | static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type, | |
1322 | struct kcqe *cqes[], u32 num_cqes) | |
1323 | { | |
1324 | struct cnic_local *cp = dev->cnic_priv; | |
1325 | struct cnic_ulp_ops *ulp_ops; | |
1326 | ||
1327 | rcu_read_lock(); | |
1328 | ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]); | |
1329 | if (likely(ulp_ops)) { | |
1330 | ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type], | |
1331 | cqes, num_cqes); | |
1332 | } | |
1333 | rcu_read_unlock(); | |
1334 | } | |
1335 | ||
1336 | static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe) | |
1337 | { | |
1338 | struct cnic_local *cp = dev->cnic_priv; | |
1339 | struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe; | |
1420398d MC |
1340 | int hq_bds, pages; |
1341 | u32 pfid = cp->pfid; | |
71034ba8 MC |
1342 | |
1343 | cp->num_iscsi_tasks = req1->num_tasks_per_conn; | |
1344 | cp->num_ccells = req1->num_ccells_per_conn; | |
1345 | cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE * | |
1346 | cp->num_iscsi_tasks; | |
1347 | cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS * | |
1348 | BNX2X_ISCSI_R2TQE_SIZE; | |
1349 | cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE; | |
1350 | pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE; | |
1351 | hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE); | |
1352 | cp->num_cqs = req1->num_cqs; | |
1353 | ||
1354 | if (!dev->max_iscsi_conn) | |
1355 | return 0; | |
1356 | ||
1357 | /* init Tstorm RAM */ | |
1420398d | 1358 | CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid), |
71034ba8 | 1359 | req1->rq_num_wqes); |
1420398d | 1360 | CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid), |
71034ba8 MC |
1361 | PAGE_SIZE); |
1362 | CNIC_WR8(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 1363 | TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT); |
71034ba8 | 1364 | CNIC_WR16(dev, BAR_TSTRORM_INTMEM + |
1420398d | 1365 | TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid), |
71034ba8 MC |
1366 | req1->num_tasks_per_conn); |
1367 | ||
1368 | /* init Ustorm RAM */ | |
1369 | CNIC_WR16(dev, BAR_USTRORM_INTMEM + | |
1420398d | 1370 | USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid), |
71034ba8 | 1371 | req1->rq_buffer_size); |
1420398d | 1372 | CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid), |
71034ba8 MC |
1373 | PAGE_SIZE); |
1374 | CNIC_WR8(dev, BAR_USTRORM_INTMEM + | |
1420398d | 1375 | USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT); |
71034ba8 | 1376 | CNIC_WR16(dev, BAR_USTRORM_INTMEM + |
1420398d | 1377 | USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid), |
71034ba8 | 1378 | req1->num_tasks_per_conn); |
1420398d | 1379 | CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid), |
71034ba8 | 1380 | req1->rq_num_wqes); |
1420398d | 1381 | CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid), |
71034ba8 | 1382 | req1->cq_num_wqes); |
1420398d | 1383 | CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid), |
71034ba8 MC |
1384 | cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS); |
1385 | ||
1386 | /* init Xstorm RAM */ | |
1420398d | 1387 | CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid), |
71034ba8 MC |
1388 | PAGE_SIZE); |
1389 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + | |
1420398d | 1390 | XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT); |
71034ba8 | 1391 | CNIC_WR16(dev, BAR_XSTRORM_INTMEM + |
1420398d | 1392 | XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid), |
71034ba8 | 1393 | req1->num_tasks_per_conn); |
1420398d | 1394 | CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid), |
71034ba8 | 1395 | hq_bds); |
1420398d | 1396 | CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid), |
71034ba8 | 1397 | req1->num_tasks_per_conn); |
1420398d | 1398 | CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid), |
71034ba8 MC |
1399 | cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS); |
1400 | ||
1401 | /* init Cstorm RAM */ | |
1420398d | 1402 | CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid), |
71034ba8 MC |
1403 | PAGE_SIZE); |
1404 | CNIC_WR8(dev, BAR_CSTRORM_INTMEM + | |
1420398d | 1405 | CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT); |
71034ba8 | 1406 | CNIC_WR16(dev, BAR_CSTRORM_INTMEM + |
1420398d | 1407 | CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid), |
71034ba8 | 1408 | req1->num_tasks_per_conn); |
1420398d | 1409 | CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid), |
71034ba8 | 1410 | req1->cq_num_wqes); |
1420398d | 1411 | CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid), |
71034ba8 MC |
1412 | hq_bds); |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe) | |
1418 | { | |
1419 | struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe; | |
1420 | struct cnic_local *cp = dev->cnic_priv; | |
1420398d | 1421 | u32 pfid = cp->pfid; |
71034ba8 MC |
1422 | struct iscsi_kcqe kcqe; |
1423 | struct kcqe *cqes[1]; | |
1424 | ||
1425 | memset(&kcqe, 0, sizeof(kcqe)); | |
1426 | if (!dev->max_iscsi_conn) { | |
1427 | kcqe.completion_status = | |
1428 | ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED; | |
1429 | goto done; | |
1430 | } | |
1431 | ||
1432 | CNIC_WR(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 1433 | TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]); |
71034ba8 | 1434 | CNIC_WR(dev, BAR_TSTRORM_INTMEM + |
1420398d | 1435 | TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4, |
71034ba8 MC |
1436 | req2->error_bit_map[1]); |
1437 | ||
1438 | CNIC_WR16(dev, BAR_USTRORM_INTMEM + | |
1420398d | 1439 | USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn); |
71034ba8 | 1440 | CNIC_WR(dev, BAR_USTRORM_INTMEM + |
1420398d | 1441 | USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]); |
71034ba8 | 1442 | CNIC_WR(dev, BAR_USTRORM_INTMEM + |
1420398d | 1443 | USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4, |
71034ba8 MC |
1444 | req2->error_bit_map[1]); |
1445 | ||
1446 | CNIC_WR16(dev, BAR_CSTRORM_INTMEM + | |
1420398d | 1447 | CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn); |
71034ba8 MC |
1448 | |
1449 | kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS; | |
1450 | ||
1451 | done: | |
1452 | kcqe.op_code = ISCSI_KCQE_OPCODE_INIT; | |
1453 | cqes[0] = (struct kcqe *) &kcqe; | |
1454 | cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1); | |
1455 | ||
1456 | return 0; | |
1457 | } | |
1458 | ||
1459 | static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid) | |
1460 | { | |
1461 | struct cnic_local *cp = dev->cnic_priv; | |
1462 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
1463 | ||
1464 | if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) { | |
1465 | struct cnic_iscsi *iscsi = ctx->proto.iscsi; | |
1466 | ||
1467 | cnic_free_dma(dev, &iscsi->hq_info); | |
1468 | cnic_free_dma(dev, &iscsi->r2tq_info); | |
1469 | cnic_free_dma(dev, &iscsi->task_array_info); | |
e1928c86 MC |
1470 | cnic_free_id(&cp->cid_tbl, ctx->cid); |
1471 | } else { | |
1472 | cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid); | |
71034ba8 | 1473 | } |
e1928c86 | 1474 | |
71034ba8 MC |
1475 | ctx->cid = 0; |
1476 | } | |
1477 | ||
1478 | static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid) | |
1479 | { | |
1480 | u32 cid; | |
1481 | int ret, pages; | |
1482 | struct cnic_local *cp = dev->cnic_priv; | |
1483 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
1484 | struct cnic_iscsi *iscsi = ctx->proto.iscsi; | |
1485 | ||
e1928c86 MC |
1486 | if (ctx->ulp_proto_id == CNIC_ULP_FCOE) { |
1487 | cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl); | |
1488 | if (cid == -1) { | |
1489 | ret = -ENOMEM; | |
1490 | goto error; | |
1491 | } | |
1492 | ctx->cid = cid; | |
1493 | return 0; | |
1494 | } | |
1495 | ||
71034ba8 MC |
1496 | cid = cnic_alloc_new_id(&cp->cid_tbl); |
1497 | if (cid == -1) { | |
1498 | ret = -ENOMEM; | |
1499 | goto error; | |
1500 | } | |
1501 | ||
1502 | ctx->cid = cid; | |
1503 | pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE; | |
1504 | ||
1505 | ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1); | |
1506 | if (ret) | |
1507 | goto error; | |
1508 | ||
1509 | pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE; | |
1510 | ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1); | |
1511 | if (ret) | |
1512 | goto error; | |
1513 | ||
1514 | pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE; | |
1515 | ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1); | |
1516 | if (ret) | |
1517 | goto error; | |
1518 | ||
1519 | return 0; | |
1520 | ||
1521 | error: | |
1522 | cnic_free_bnx2x_conn_resc(dev, l5_cid); | |
1523 | return ret; | |
1524 | } | |
1525 | ||
1526 | static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init, | |
1527 | struct regpair *ctx_addr) | |
1528 | { | |
1529 | struct cnic_local *cp = dev->cnic_priv; | |
1530 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
1531 | int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk; | |
1532 | int off = (cid - ethdev->starting_cid) % cp->cids_per_blk; | |
1533 | unsigned long align_off = 0; | |
1534 | dma_addr_t ctx_map; | |
1535 | void *ctx; | |
1536 | ||
1537 | if (cp->ctx_align) { | |
1538 | unsigned long mask = cp->ctx_align - 1; | |
1539 | ||
1540 | if (cp->ctx_arr[blk].mapping & mask) | |
1541 | align_off = cp->ctx_align - | |
1542 | (cp->ctx_arr[blk].mapping & mask); | |
1543 | } | |
1544 | ctx_map = cp->ctx_arr[blk].mapping + align_off + | |
1545 | (off * BNX2X_CONTEXT_MEM_SIZE); | |
1546 | ctx = cp->ctx_arr[blk].ctx + align_off + | |
1547 | (off * BNX2X_CONTEXT_MEM_SIZE); | |
1548 | if (init) | |
1549 | memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE); | |
1550 | ||
1551 | ctx_addr->lo = ctx_map & 0xffffffff; | |
1552 | ctx_addr->hi = (u64) ctx_map >> 32; | |
1553 | return ctx; | |
1554 | } | |
1555 | ||
1556 | static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[], | |
1557 | u32 num) | |
1558 | { | |
1559 | struct cnic_local *cp = dev->cnic_priv; | |
1560 | struct iscsi_kwqe_conn_offload1 *req1 = | |
1561 | (struct iscsi_kwqe_conn_offload1 *) wqes[0]; | |
1562 | struct iscsi_kwqe_conn_offload2 *req2 = | |
1563 | (struct iscsi_kwqe_conn_offload2 *) wqes[1]; | |
1564 | struct iscsi_kwqe_conn_offload3 *req3; | |
1565 | struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id]; | |
1566 | struct cnic_iscsi *iscsi = ctx->proto.iscsi; | |
1567 | u32 cid = ctx->cid; | |
ceb7e1c7 | 1568 | u32 hw_cid = BNX2X_HW_CID(cp, cid); |
71034ba8 MC |
1569 | struct iscsi_context *ictx; |
1570 | struct regpair context_addr; | |
1571 | int i, j, n = 2, n_max; | |
1572 | ||
1573 | ctx->ctx_flags = 0; | |
1574 | if (!req2->num_additional_wqes) | |
1575 | return -EINVAL; | |
1576 | ||
1577 | n_max = req2->num_additional_wqes + 2; | |
1578 | ||
1579 | ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr); | |
1580 | if (ictx == NULL) | |
1581 | return -ENOMEM; | |
1582 | ||
1583 | req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++]; | |
1584 | ||
1585 | ictx->xstorm_ag_context.hq_prod = 1; | |
1586 | ||
1587 | ictx->xstorm_st_context.iscsi.first_burst_length = | |
1588 | ISCSI_DEF_FIRST_BURST_LEN; | |
1589 | ictx->xstorm_st_context.iscsi.max_send_pdu_length = | |
1590 | ISCSI_DEF_MAX_RECV_SEG_LEN; | |
1591 | ictx->xstorm_st_context.iscsi.sq_pbl_base.lo = | |
1592 | req1->sq_page_table_addr_lo; | |
1593 | ictx->xstorm_st_context.iscsi.sq_pbl_base.hi = | |
1594 | req1->sq_page_table_addr_hi; | |
1595 | ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi; | |
1596 | ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo; | |
1597 | ictx->xstorm_st_context.iscsi.hq_pbl_base.lo = | |
1598 | iscsi->hq_info.pgtbl_map & 0xffffffff; | |
1599 | ictx->xstorm_st_context.iscsi.hq_pbl_base.hi = | |
1600 | (u64) iscsi->hq_info.pgtbl_map >> 32; | |
1601 | ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo = | |
1602 | iscsi->hq_info.pgtbl[0]; | |
1603 | ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi = | |
1604 | iscsi->hq_info.pgtbl[1]; | |
1605 | ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo = | |
1606 | iscsi->r2tq_info.pgtbl_map & 0xffffffff; | |
1607 | ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi = | |
1608 | (u64) iscsi->r2tq_info.pgtbl_map >> 32; | |
1609 | ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo = | |
1610 | iscsi->r2tq_info.pgtbl[0]; | |
1611 | ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi = | |
1612 | iscsi->r2tq_info.pgtbl[1]; | |
1613 | ictx->xstorm_st_context.iscsi.task_pbl_base.lo = | |
1614 | iscsi->task_array_info.pgtbl_map & 0xffffffff; | |
1615 | ictx->xstorm_st_context.iscsi.task_pbl_base.hi = | |
1616 | (u64) iscsi->task_array_info.pgtbl_map >> 32; | |
1617 | ictx->xstorm_st_context.iscsi.task_pbl_cache_idx = | |
1618 | BNX2X_ISCSI_PBL_NOT_CACHED; | |
1619 | ictx->xstorm_st_context.iscsi.flags.flags |= | |
1620 | XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA; | |
1621 | ictx->xstorm_st_context.iscsi.flags.flags |= | |
1622 | XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T; | |
1623 | ||
1624 | ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE; | |
1625 | /* TSTORM requires the base address of RQ DB & not PTE */ | |
1626 | ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo = | |
1627 | req2->rq_page_table_addr_lo & PAGE_MASK; | |
1628 | ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi = | |
1629 | req2->rq_page_table_addr_hi; | |
1630 | ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id; | |
1631 | ictx->tstorm_st_context.tcp.cwnd = 0x5A8; | |
1632 | ictx->tstorm_st_context.tcp.flags2 |= | |
1633 | TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN; | |
523224a3 DK |
1634 | ictx->tstorm_st_context.tcp.ooo_support_mode = |
1635 | TCP_TSTORM_OOO_DROP_AND_PROC_ACK; | |
71034ba8 | 1636 | |
523224a3 | 1637 | ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG; |
71034ba8 MC |
1638 | |
1639 | ictx->ustorm_st_context.ring.rq.pbl_base.lo = | |
15971c3c | 1640 | req2->rq_page_table_addr_lo; |
71034ba8 | 1641 | ictx->ustorm_st_context.ring.rq.pbl_base.hi = |
15971c3c | 1642 | req2->rq_page_table_addr_hi; |
71034ba8 MC |
1643 | ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi; |
1644 | ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo; | |
1645 | ictx->ustorm_st_context.ring.r2tq.pbl_base.lo = | |
1646 | iscsi->r2tq_info.pgtbl_map & 0xffffffff; | |
1647 | ictx->ustorm_st_context.ring.r2tq.pbl_base.hi = | |
1648 | (u64) iscsi->r2tq_info.pgtbl_map >> 32; | |
1649 | ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo = | |
1650 | iscsi->r2tq_info.pgtbl[0]; | |
1651 | ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi = | |
1652 | iscsi->r2tq_info.pgtbl[1]; | |
1653 | ictx->ustorm_st_context.ring.cq_pbl_base.lo = | |
1654 | req1->cq_page_table_addr_lo; | |
1655 | ictx->ustorm_st_context.ring.cq_pbl_base.hi = | |
1656 | req1->cq_page_table_addr_hi; | |
1657 | ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN; | |
1658 | ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi; | |
1659 | ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo; | |
1660 | ictx->ustorm_st_context.task_pbe_cache_index = | |
1661 | BNX2X_ISCSI_PBL_NOT_CACHED; | |
1662 | ictx->ustorm_st_context.task_pdu_cache_index = | |
1663 | BNX2X_ISCSI_PDU_HEADER_NOT_CACHED; | |
1664 | ||
1665 | for (i = 1, j = 1; i < cp->num_cqs; i++, j++) { | |
1666 | if (j == 3) { | |
1667 | if (n >= n_max) | |
1668 | break; | |
1669 | req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++]; | |
1670 | j = 0; | |
1671 | } | |
1672 | ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN; | |
1673 | ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo = | |
1674 | req3->qp_first_pte[j].hi; | |
1675 | ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi = | |
1676 | req3->qp_first_pte[j].lo; | |
1677 | } | |
1678 | ||
1679 | ictx->ustorm_st_context.task_pbl_base.lo = | |
1680 | iscsi->task_array_info.pgtbl_map & 0xffffffff; | |
1681 | ictx->ustorm_st_context.task_pbl_base.hi = | |
1682 | (u64) iscsi->task_array_info.pgtbl_map >> 32; | |
1683 | ictx->ustorm_st_context.tce_phy_addr.lo = | |
1684 | iscsi->task_array_info.pgtbl[0]; | |
1685 | ictx->ustorm_st_context.tce_phy_addr.hi = | |
1686 | iscsi->task_array_info.pgtbl[1]; | |
1687 | ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id; | |
1688 | ictx->ustorm_st_context.num_cqs = cp->num_cqs; | |
1689 | ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN; | |
1690 | ictx->ustorm_st_context.negotiated_rx_and_flags |= | |
1691 | ISCSI_DEF_MAX_BURST_LEN; | |
1692 | ictx->ustorm_st_context.negotiated_rx |= | |
1693 | ISCSI_DEFAULT_MAX_OUTSTANDING_R2T << | |
1694 | USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT; | |
1695 | ||
1696 | ictx->cstorm_st_context.hq_pbl_base.lo = | |
1697 | iscsi->hq_info.pgtbl_map & 0xffffffff; | |
1698 | ictx->cstorm_st_context.hq_pbl_base.hi = | |
1699 | (u64) iscsi->hq_info.pgtbl_map >> 32; | |
1700 | ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0]; | |
1701 | ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1]; | |
1702 | ictx->cstorm_st_context.task_pbl_base.lo = | |
1703 | iscsi->task_array_info.pgtbl_map & 0xffffffff; | |
1704 | ictx->cstorm_st_context.task_pbl_base.hi = | |
1705 | (u64) iscsi->task_array_info.pgtbl_map >> 32; | |
1706 | /* CSTORM and USTORM initialization is different, CSTORM requires | |
1707 | * CQ DB base & not PTE addr */ | |
1708 | ictx->cstorm_st_context.cq_db_base.lo = | |
1709 | req1->cq_page_table_addr_lo & PAGE_MASK; | |
1710 | ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi; | |
1711 | ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id; | |
1712 | ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1; | |
1713 | for (i = 0; i < cp->num_cqs; i++) { | |
1714 | ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] = | |
1715 | ISCSI_INITIAL_SN; | |
1716 | ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] = | |
1717 | ISCSI_INITIAL_SN; | |
1718 | } | |
1719 | ||
1720 | ictx->xstorm_ag_context.cdu_reserved = | |
1721 | CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG, | |
1722 | ISCSI_CONNECTION_TYPE); | |
1723 | ictx->ustorm_ag_context.cdu_usage = | |
1724 | CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG, | |
1725 | ISCSI_CONNECTION_TYPE); | |
1726 | return 0; | |
1727 | ||
1728 | } | |
1729 | ||
1730 | static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[], | |
1731 | u32 num, int *work) | |
1732 | { | |
1733 | struct iscsi_kwqe_conn_offload1 *req1; | |
1734 | struct iscsi_kwqe_conn_offload2 *req2; | |
1735 | struct cnic_local *cp = dev->cnic_priv; | |
fdf24086 | 1736 | struct cnic_context *ctx; |
71034ba8 MC |
1737 | struct iscsi_kcqe kcqe; |
1738 | struct kcqe *cqes[1]; | |
1739 | u32 l5_cid; | |
fdf24086 | 1740 | int ret = 0; |
71034ba8 MC |
1741 | |
1742 | if (num < 2) { | |
1743 | *work = num; | |
1744 | return -EINVAL; | |
1745 | } | |
1746 | ||
1747 | req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0]; | |
1748 | req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1]; | |
1749 | if ((num - 2) < req2->num_additional_wqes) { | |
1750 | *work = num; | |
1751 | return -EINVAL; | |
1752 | } | |
779bb41d | 1753 | *work = 2 + req2->num_additional_wqes; |
71034ba8 MC |
1754 | |
1755 | l5_cid = req1->iscsi_conn_id; | |
1756 | if (l5_cid >= MAX_ISCSI_TBL_SZ) | |
1757 | return -EINVAL; | |
1758 | ||
1759 | memset(&kcqe, 0, sizeof(kcqe)); | |
1760 | kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN; | |
1761 | kcqe.iscsi_conn_id = l5_cid; | |
1762 | kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE; | |
1763 | ||
fdf24086 MC |
1764 | ctx = &cp->ctx_tbl[l5_cid]; |
1765 | if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) { | |
1766 | kcqe.completion_status = | |
1767 | ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY; | |
1768 | goto done; | |
1769 | } | |
1770 | ||
71034ba8 MC |
1771 | if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) { |
1772 | atomic_dec(&cp->iscsi_conn); | |
71034ba8 MC |
1773 | goto done; |
1774 | } | |
1775 | ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid); | |
1776 | if (ret) { | |
1777 | atomic_dec(&cp->iscsi_conn); | |
1778 | ret = 0; | |
1779 | goto done; | |
1780 | } | |
1781 | ret = cnic_setup_bnx2x_ctx(dev, wqes, num); | |
1782 | if (ret < 0) { | |
1783 | cnic_free_bnx2x_conn_resc(dev, l5_cid); | |
1784 | atomic_dec(&cp->iscsi_conn); | |
1785 | goto done; | |
1786 | } | |
1787 | ||
1788 | kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS; | |
ceb7e1c7 | 1789 | kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid); |
71034ba8 MC |
1790 | |
1791 | done: | |
1792 | cqes[0] = (struct kcqe *) &kcqe; | |
1793 | cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1); | |
1794 | return ret; | |
1795 | } | |
1796 | ||
1797 | ||
1798 | static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe) | |
1799 | { | |
1800 | struct cnic_local *cp = dev->cnic_priv; | |
1801 | struct iscsi_kwqe_conn_update *req = | |
1802 | (struct iscsi_kwqe_conn_update *) kwqe; | |
1803 | void *data; | |
1804 | union l5cm_specific_data l5_data; | |
1805 | u32 l5_cid, cid = BNX2X_SW_CID(req->context_id); | |
1806 | int ret; | |
1807 | ||
1808 | if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0) | |
1809 | return -EINVAL; | |
1810 | ||
1811 | data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data); | |
1812 | if (!data) | |
1813 | return -ENOMEM; | |
1814 | ||
1815 | memcpy(data, kwqe, sizeof(struct kwqe)); | |
1816 | ||
1817 | ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN, | |
1818 | req->context_id, ISCSI_CONNECTION_TYPE, &l5_data); | |
1819 | return ret; | |
1820 | } | |
1821 | ||
a2c9e769 | 1822 | static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid) |
71034ba8 MC |
1823 | { |
1824 | struct cnic_local *cp = dev->cnic_priv; | |
71034ba8 | 1825 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; |
a2c9e769 MC |
1826 | union l5cm_specific_data l5_data; |
1827 | int ret; | |
68d7c1aa | 1828 | u32 hw_cid; |
71034ba8 | 1829 | |
71034ba8 MC |
1830 | init_waitqueue_head(&ctx->waitq); |
1831 | ctx->wait_cond = 0; | |
1832 | memset(&l5_data, 0, sizeof(l5_data)); | |
523224a3 | 1833 | hw_cid = BNX2X_HW_CID(cp, ctx->cid); |
523224a3 DK |
1834 | |
1835 | ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL, | |
68d7c1aa | 1836 | hw_cid, NONE_CONNECTION_TYPE, &l5_data); |
523224a3 | 1837 | |
71034ba8 MC |
1838 | if (ret == 0) |
1839 | wait_event(ctx->waitq, ctx->wait_cond); | |
1840 | ||
a2c9e769 MC |
1841 | return ret; |
1842 | } | |
1843 | ||
1844 | static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe) | |
1845 | { | |
1846 | struct cnic_local *cp = dev->cnic_priv; | |
1847 | struct iscsi_kwqe_conn_destroy *req = | |
1848 | (struct iscsi_kwqe_conn_destroy *) kwqe; | |
1849 | u32 l5_cid = req->reserved0; | |
1850 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
1851 | int ret = 0; | |
1852 | struct iscsi_kcqe kcqe; | |
1853 | struct kcqe *cqes[1]; | |
1854 | ||
1855 | if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) | |
1856 | goto skip_cfc_delete; | |
1857 | ||
fdf24086 MC |
1858 | if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) { |
1859 | unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies; | |
1860 | ||
1861 | if (delta > (2 * HZ)) | |
1862 | delta = 0; | |
1863 | ||
1864 | set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags); | |
1865 | queue_delayed_work(cnic_wq, &cp->delete_task, delta); | |
1866 | goto destroy_reply; | |
1867 | } | |
a2c9e769 MC |
1868 | |
1869 | ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid); | |
1870 | ||
71034ba8 MC |
1871 | skip_cfc_delete: |
1872 | cnic_free_bnx2x_conn_resc(dev, l5_cid); | |
1873 | ||
1874 | atomic_dec(&cp->iscsi_conn); | |
fdf24086 | 1875 | clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags); |
71034ba8 | 1876 | |
fdf24086 | 1877 | destroy_reply: |
71034ba8 MC |
1878 | memset(&kcqe, 0, sizeof(kcqe)); |
1879 | kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN; | |
1880 | kcqe.iscsi_conn_id = l5_cid; | |
1881 | kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS; | |
1882 | kcqe.iscsi_conn_context_id = req->context_id; | |
1883 | ||
1884 | cqes[0] = (struct kcqe *) &kcqe; | |
1885 | cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1); | |
1886 | ||
1887 | return ret; | |
1888 | } | |
1889 | ||
1890 | static void cnic_init_storm_conn_bufs(struct cnic_dev *dev, | |
1891 | struct l4_kwq_connect_req1 *kwqe1, | |
1892 | struct l4_kwq_connect_req3 *kwqe3, | |
1893 | struct l5cm_active_conn_buffer *conn_buf) | |
1894 | { | |
1895 | struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf; | |
1896 | struct l5cm_xstorm_conn_buffer *xstorm_buf = | |
1897 | &conn_buf->xstorm_conn_buffer; | |
1898 | struct l5cm_tstorm_conn_buffer *tstorm_buf = | |
1899 | &conn_buf->tstorm_conn_buffer; | |
1900 | struct regpair context_addr; | |
1901 | u32 cid = BNX2X_SW_CID(kwqe1->cid); | |
1902 | struct in6_addr src_ip, dst_ip; | |
1903 | int i; | |
1904 | u32 *addrp; | |
1905 | ||
1906 | addrp = (u32 *) &conn_addr->local_ip_addr; | |
1907 | for (i = 0; i < 4; i++, addrp++) | |
1908 | src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp); | |
1909 | ||
1910 | addrp = (u32 *) &conn_addr->remote_ip_addr; | |
1911 | for (i = 0; i < 4; i++, addrp++) | |
1912 | dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp); | |
1913 | ||
1914 | cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr); | |
1915 | ||
1916 | xstorm_buf->context_addr.hi = context_addr.hi; | |
1917 | xstorm_buf->context_addr.lo = context_addr.lo; | |
1918 | xstorm_buf->mss = 0xffff; | |
1919 | xstorm_buf->rcv_buf = kwqe3->rcv_buf; | |
1920 | if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE) | |
1921 | xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE; | |
1922 | xstorm_buf->pseudo_header_checksum = | |
1923 | swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0)); | |
1924 | ||
1925 | if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK)) | |
1926 | tstorm_buf->params |= | |
1927 | L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE; | |
1928 | if (kwqe3->ka_timeout) { | |
1929 | tstorm_buf->ka_enable = 1; | |
1930 | tstorm_buf->ka_timeout = kwqe3->ka_timeout; | |
1931 | tstorm_buf->ka_interval = kwqe3->ka_interval; | |
1932 | tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count; | |
1933 | } | |
1934 | tstorm_buf->rcv_buf = kwqe3->rcv_buf; | |
1935 | tstorm_buf->snd_buf = kwqe3->snd_buf; | |
1936 | tstorm_buf->max_rt_time = 0xffffffff; | |
1937 | } | |
1938 | ||
1939 | static void cnic_init_bnx2x_mac(struct cnic_dev *dev) | |
1940 | { | |
1941 | struct cnic_local *cp = dev->cnic_priv; | |
1420398d | 1942 | u32 pfid = cp->pfid; |
71034ba8 MC |
1943 | u8 *mac = dev->mac_addr; |
1944 | ||
1945 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + | |
1420398d | 1946 | XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]); |
71034ba8 | 1947 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + |
1420398d | 1948 | XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]); |
71034ba8 | 1949 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + |
1420398d | 1950 | XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]); |
71034ba8 | 1951 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + |
1420398d | 1952 | XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]); |
71034ba8 | 1953 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + |
1420398d | 1954 | XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]); |
71034ba8 | 1955 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + |
1420398d | 1956 | XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]); |
71034ba8 MC |
1957 | |
1958 | CNIC_WR8(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 1959 | TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]); |
71034ba8 | 1960 | CNIC_WR8(dev, BAR_TSTRORM_INTMEM + |
1420398d | 1961 | TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1, |
71034ba8 MC |
1962 | mac[4]); |
1963 | CNIC_WR8(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 1964 | TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]); |
71034ba8 | 1965 | CNIC_WR8(dev, BAR_TSTRORM_INTMEM + |
1420398d | 1966 | TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1, |
71034ba8 MC |
1967 | mac[2]); |
1968 | CNIC_WR8(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 1969 | TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2, |
71034ba8 MC |
1970 | mac[1]); |
1971 | CNIC_WR8(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 1972 | TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3, |
71034ba8 MC |
1973 | mac[0]); |
1974 | } | |
1975 | ||
1976 | static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts) | |
1977 | { | |
1978 | struct cnic_local *cp = dev->cnic_priv; | |
1979 | u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN; | |
1980 | u16 tstorm_flags = 0; | |
1981 | ||
1982 | if (tcp_ts) { | |
1983 | xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED; | |
1984 | tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED; | |
1985 | } | |
1986 | ||
1987 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + | |
1420398d | 1988 | XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags); |
71034ba8 MC |
1989 | |
1990 | CNIC_WR16(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 1991 | TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags); |
71034ba8 MC |
1992 | } |
1993 | ||
1994 | static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[], | |
1995 | u32 num, int *work) | |
1996 | { | |
1997 | struct cnic_local *cp = dev->cnic_priv; | |
1998 | struct l4_kwq_connect_req1 *kwqe1 = | |
1999 | (struct l4_kwq_connect_req1 *) wqes[0]; | |
2000 | struct l4_kwq_connect_req3 *kwqe3; | |
2001 | struct l5cm_active_conn_buffer *conn_buf; | |
2002 | struct l5cm_conn_addr_params *conn_addr; | |
2003 | union l5cm_specific_data l5_data; | |
2004 | u32 l5_cid = kwqe1->pg_cid; | |
2005 | struct cnic_sock *csk = &cp->csk_tbl[l5_cid]; | |
2006 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
2007 | int ret; | |
2008 | ||
2009 | if (num < 2) { | |
2010 | *work = num; | |
2011 | return -EINVAL; | |
2012 | } | |
2013 | ||
2014 | if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) | |
2015 | *work = 3; | |
2016 | else | |
2017 | *work = 2; | |
2018 | ||
2019 | if (num < *work) { | |
2020 | *work = num; | |
2021 | return -EINVAL; | |
2022 | } | |
2023 | ||
2024 | if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) { | |
ddf79b20 | 2025 | netdev_err(dev->netdev, "conn_buf size too big\n"); |
71034ba8 MC |
2026 | return -ENOMEM; |
2027 | } | |
2028 | conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data); | |
2029 | if (!conn_buf) | |
2030 | return -ENOMEM; | |
2031 | ||
2032 | memset(conn_buf, 0, sizeof(*conn_buf)); | |
2033 | ||
2034 | conn_addr = &conn_buf->conn_addr_buf; | |
2035 | conn_addr->remote_addr_0 = csk->ha[0]; | |
2036 | conn_addr->remote_addr_1 = csk->ha[1]; | |
2037 | conn_addr->remote_addr_2 = csk->ha[2]; | |
2038 | conn_addr->remote_addr_3 = csk->ha[3]; | |
2039 | conn_addr->remote_addr_4 = csk->ha[4]; | |
2040 | conn_addr->remote_addr_5 = csk->ha[5]; | |
2041 | ||
2042 | if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) { | |
2043 | struct l4_kwq_connect_req2 *kwqe2 = | |
2044 | (struct l4_kwq_connect_req2 *) wqes[1]; | |
2045 | ||
2046 | conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4; | |
2047 | conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3; | |
2048 | conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2; | |
2049 | ||
2050 | conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4; | |
2051 | conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3; | |
2052 | conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2; | |
2053 | conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION; | |
2054 | } | |
2055 | kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1]; | |
2056 | ||
2057 | conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip; | |
2058 | conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip; | |
2059 | conn_addr->local_tcp_port = kwqe1->src_port; | |
2060 | conn_addr->remote_tcp_port = kwqe1->dst_port; | |
2061 | ||
2062 | conn_addr->pmtu = kwqe3->pmtu; | |
2063 | cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf); | |
2064 | ||
2065 | CNIC_WR16(dev, BAR_XSTRORM_INTMEM + | |
1420398d | 2066 | XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id); |
71034ba8 MC |
2067 | |
2068 | cnic_bnx2x_set_tcp_timestamp(dev, | |
2069 | kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP); | |
2070 | ||
2071 | ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT, | |
2072 | kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data); | |
2073 | if (!ret) | |
6e0dda0c | 2074 | set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags); |
71034ba8 MC |
2075 | |
2076 | return ret; | |
2077 | } | |
2078 | ||
2079 | static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe) | |
2080 | { | |
2081 | struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe; | |
2082 | union l5cm_specific_data l5_data; | |
2083 | int ret; | |
2084 | ||
2085 | memset(&l5_data, 0, sizeof(l5_data)); | |
2086 | ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE, | |
2087 | req->cid, ISCSI_CONNECTION_TYPE, &l5_data); | |
2088 | return ret; | |
2089 | } | |
2090 | ||
2091 | static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe) | |
2092 | { | |
2093 | struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe; | |
2094 | union l5cm_specific_data l5_data; | |
2095 | int ret; | |
2096 | ||
2097 | memset(&l5_data, 0, sizeof(l5_data)); | |
2098 | ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT, | |
2099 | req->cid, ISCSI_CONNECTION_TYPE, &l5_data); | |
2100 | return ret; | |
2101 | } | |
2102 | static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe) | |
2103 | { | |
2104 | struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe; | |
2105 | struct l4_kcq kcqe; | |
2106 | struct kcqe *cqes[1]; | |
2107 | ||
2108 | memset(&kcqe, 0, sizeof(kcqe)); | |
2109 | kcqe.pg_host_opaque = req->host_opaque; | |
2110 | kcqe.pg_cid = req->host_opaque; | |
2111 | kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG; | |
2112 | cqes[0] = (struct kcqe *) &kcqe; | |
2113 | cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1); | |
2114 | return 0; | |
2115 | } | |
2116 | ||
2117 | static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe) | |
2118 | { | |
2119 | struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe; | |
2120 | struct l4_kcq kcqe; | |
2121 | struct kcqe *cqes[1]; | |
2122 | ||
2123 | memset(&kcqe, 0, sizeof(kcqe)); | |
2124 | kcqe.pg_host_opaque = req->pg_host_opaque; | |
2125 | kcqe.pg_cid = req->pg_cid; | |
2126 | kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG; | |
2127 | cqes[0] = (struct kcqe *) &kcqe; | |
2128 | cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1); | |
2129 | return 0; | |
2130 | } | |
2131 | ||
e1928c86 MC |
2132 | static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe) |
2133 | { | |
2134 | struct fcoe_kwqe_stat *req; | |
2135 | struct fcoe_stat_ramrod_params *fcoe_stat; | |
2136 | union l5cm_specific_data l5_data; | |
2137 | struct cnic_local *cp = dev->cnic_priv; | |
2138 | int ret; | |
2139 | u32 cid; | |
2140 | ||
2141 | req = (struct fcoe_kwqe_stat *) kwqe; | |
2142 | cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid); | |
2143 | ||
2144 | fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data); | |
2145 | if (!fcoe_stat) | |
2146 | return -ENOMEM; | |
2147 | ||
2148 | memset(fcoe_stat, 0, sizeof(*fcoe_stat)); | |
2149 | memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req)); | |
2150 | ||
2151 | ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid, | |
2152 | FCOE_CONNECTION_TYPE, &l5_data); | |
2153 | return ret; | |
2154 | } | |
2155 | ||
2156 | static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[], | |
2157 | u32 num, int *work) | |
2158 | { | |
2159 | int ret; | |
2160 | struct cnic_local *cp = dev->cnic_priv; | |
2161 | u32 cid; | |
2162 | struct fcoe_init_ramrod_params *fcoe_init; | |
2163 | struct fcoe_kwqe_init1 *req1; | |
2164 | struct fcoe_kwqe_init2 *req2; | |
2165 | struct fcoe_kwqe_init3 *req3; | |
2166 | union l5cm_specific_data l5_data; | |
2167 | ||
2168 | if (num < 3) { | |
2169 | *work = num; | |
2170 | return -EINVAL; | |
2171 | } | |
2172 | req1 = (struct fcoe_kwqe_init1 *) wqes[0]; | |
2173 | req2 = (struct fcoe_kwqe_init2 *) wqes[1]; | |
2174 | req3 = (struct fcoe_kwqe_init3 *) wqes[2]; | |
2175 | if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) { | |
2176 | *work = 1; | |
2177 | return -EINVAL; | |
2178 | } | |
2179 | if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) { | |
2180 | *work = 2; | |
2181 | return -EINVAL; | |
2182 | } | |
2183 | ||
2184 | if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) { | |
2185 | netdev_err(dev->netdev, "fcoe_init size too big\n"); | |
2186 | return -ENOMEM; | |
2187 | } | |
2188 | fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data); | |
2189 | if (!fcoe_init) | |
2190 | return -ENOMEM; | |
2191 | ||
2192 | memset(fcoe_init, 0, sizeof(*fcoe_init)); | |
2193 | memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1)); | |
2194 | memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2)); | |
2195 | memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3)); | |
2196 | fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff; | |
2197 | fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32; | |
2198 | fcoe_init->eq_next_page_addr.lo = | |
2199 | cp->kcq2.dma.pg_map_arr[1] & 0xffffffff; | |
2200 | fcoe_init->eq_next_page_addr.hi = | |
2201 | (u64) cp->kcq2.dma.pg_map_arr[1] >> 32; | |
2202 | ||
2203 | fcoe_init->sb_num = cp->status_blk_num; | |
2204 | fcoe_init->eq_prod = MAX_KCQ_IDX; | |
2205 | fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS; | |
2206 | cp->kcq2.sw_prod_idx = 0; | |
2207 | ||
2208 | cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid); | |
e1928c86 MC |
2209 | ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid, |
2210 | FCOE_CONNECTION_TYPE, &l5_data); | |
2211 | *work = 3; | |
2212 | return ret; | |
2213 | } | |
2214 | ||
2215 | static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[], | |
2216 | u32 num, int *work) | |
2217 | { | |
2218 | int ret = 0; | |
2219 | u32 cid = -1, l5_cid; | |
2220 | struct cnic_local *cp = dev->cnic_priv; | |
2221 | struct fcoe_kwqe_conn_offload1 *req1; | |
2222 | struct fcoe_kwqe_conn_offload2 *req2; | |
2223 | struct fcoe_kwqe_conn_offload3 *req3; | |
2224 | struct fcoe_kwqe_conn_offload4 *req4; | |
2225 | struct fcoe_conn_offload_ramrod_params *fcoe_offload; | |
2226 | struct cnic_context *ctx; | |
2227 | struct fcoe_context *fctx; | |
2228 | struct regpair ctx_addr; | |
2229 | union l5cm_specific_data l5_data; | |
2230 | struct fcoe_kcqe kcqe; | |
2231 | struct kcqe *cqes[1]; | |
2232 | ||
2233 | if (num < 4) { | |
2234 | *work = num; | |
2235 | return -EINVAL; | |
2236 | } | |
2237 | req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0]; | |
2238 | req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1]; | |
2239 | req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2]; | |
2240 | req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3]; | |
2241 | ||
2242 | *work = 4; | |
2243 | ||
2244 | l5_cid = req1->fcoe_conn_id; | |
2245 | if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS) | |
2246 | goto err_reply; | |
2247 | ||
2248 | l5_cid += BNX2X_FCOE_L5_CID_BASE; | |
2249 | ||
2250 | ctx = &cp->ctx_tbl[l5_cid]; | |
2251 | if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) | |
2252 | goto err_reply; | |
2253 | ||
2254 | ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid); | |
2255 | if (ret) { | |
2256 | ret = 0; | |
2257 | goto err_reply; | |
2258 | } | |
2259 | cid = ctx->cid; | |
2260 | ||
2261 | fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr); | |
2262 | if (fctx) { | |
2263 | u32 hw_cid = BNX2X_HW_CID(cp, cid); | |
2264 | u32 val; | |
2265 | ||
2266 | val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG, | |
2267 | FCOE_CONNECTION_TYPE); | |
2268 | fctx->xstorm_ag_context.cdu_reserved = val; | |
2269 | val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG, | |
2270 | FCOE_CONNECTION_TYPE); | |
2271 | fctx->ustorm_ag_context.cdu_usage = val; | |
2272 | } | |
2273 | if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) { | |
2274 | netdev_err(dev->netdev, "fcoe_offload size too big\n"); | |
2275 | goto err_reply; | |
2276 | } | |
2277 | fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data); | |
2278 | if (!fcoe_offload) | |
2279 | goto err_reply; | |
2280 | ||
2281 | memset(fcoe_offload, 0, sizeof(*fcoe_offload)); | |
2282 | memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1)); | |
2283 | memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2)); | |
2284 | memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3)); | |
2285 | memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4)); | |
2286 | ||
2287 | cid = BNX2X_HW_CID(cp, cid); | |
2288 | ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid, | |
2289 | FCOE_CONNECTION_TYPE, &l5_data); | |
2290 | if (!ret) | |
2291 | set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags); | |
2292 | ||
2293 | return ret; | |
2294 | ||
2295 | err_reply: | |
2296 | if (cid != -1) | |
2297 | cnic_free_bnx2x_conn_resc(dev, l5_cid); | |
2298 | ||
2299 | memset(&kcqe, 0, sizeof(kcqe)); | |
2300 | kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN; | |
2301 | kcqe.fcoe_conn_id = req1->fcoe_conn_id; | |
2302 | kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE; | |
2303 | ||
2304 | cqes[0] = (struct kcqe *) &kcqe; | |
2305 | cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1); | |
2306 | return ret; | |
2307 | } | |
2308 | ||
2309 | static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe) | |
2310 | { | |
2311 | struct fcoe_kwqe_conn_enable_disable *req; | |
2312 | struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable; | |
2313 | union l5cm_specific_data l5_data; | |
2314 | int ret; | |
2315 | u32 cid, l5_cid; | |
2316 | struct cnic_local *cp = dev->cnic_priv; | |
2317 | ||
2318 | req = (struct fcoe_kwqe_conn_enable_disable *) kwqe; | |
2319 | cid = req->context_id; | |
2320 | l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE; | |
2321 | ||
2322 | if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) { | |
2323 | netdev_err(dev->netdev, "fcoe_enable size too big\n"); | |
2324 | return -ENOMEM; | |
2325 | } | |
2326 | fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data); | |
2327 | if (!fcoe_enable) | |
2328 | return -ENOMEM; | |
2329 | ||
2330 | memset(fcoe_enable, 0, sizeof(*fcoe_enable)); | |
2331 | memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req)); | |
2332 | ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid, | |
2333 | FCOE_CONNECTION_TYPE, &l5_data); | |
2334 | return ret; | |
2335 | } | |
2336 | ||
2337 | static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe) | |
2338 | { | |
2339 | struct fcoe_kwqe_conn_enable_disable *req; | |
2340 | struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable; | |
2341 | union l5cm_specific_data l5_data; | |
2342 | int ret; | |
2343 | u32 cid, l5_cid; | |
2344 | struct cnic_local *cp = dev->cnic_priv; | |
2345 | ||
2346 | req = (struct fcoe_kwqe_conn_enable_disable *) kwqe; | |
2347 | cid = req->context_id; | |
2348 | l5_cid = req->conn_id; | |
2349 | if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS) | |
2350 | return -EINVAL; | |
2351 | ||
2352 | l5_cid += BNX2X_FCOE_L5_CID_BASE; | |
2353 | ||
2354 | if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) { | |
2355 | netdev_err(dev->netdev, "fcoe_disable size too big\n"); | |
2356 | return -ENOMEM; | |
2357 | } | |
2358 | fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data); | |
2359 | if (!fcoe_disable) | |
2360 | return -ENOMEM; | |
2361 | ||
2362 | memset(fcoe_disable, 0, sizeof(*fcoe_disable)); | |
2363 | memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req)); | |
2364 | ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid, | |
2365 | FCOE_CONNECTION_TYPE, &l5_data); | |
2366 | return ret; | |
2367 | } | |
2368 | ||
2369 | static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe) | |
2370 | { | |
2371 | struct fcoe_kwqe_conn_destroy *req; | |
2372 | union l5cm_specific_data l5_data; | |
2373 | int ret; | |
2374 | u32 cid, l5_cid; | |
2375 | struct cnic_local *cp = dev->cnic_priv; | |
2376 | struct cnic_context *ctx; | |
2377 | struct fcoe_kcqe kcqe; | |
2378 | struct kcqe *cqes[1]; | |
2379 | ||
2380 | req = (struct fcoe_kwqe_conn_destroy *) kwqe; | |
2381 | cid = req->context_id; | |
2382 | l5_cid = req->conn_id; | |
2383 | if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS) | |
2384 | return -EINVAL; | |
2385 | ||
2386 | l5_cid += BNX2X_FCOE_L5_CID_BASE; | |
2387 | ||
2388 | ctx = &cp->ctx_tbl[l5_cid]; | |
2389 | ||
2390 | init_waitqueue_head(&ctx->waitq); | |
2391 | ctx->wait_cond = 0; | |
2392 | ||
2393 | memset(&l5_data, 0, sizeof(l5_data)); | |
2394 | ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid, | |
2395 | FCOE_CONNECTION_TYPE, &l5_data); | |
2396 | if (ret == 0) { | |
2397 | wait_event(ctx->waitq, ctx->wait_cond); | |
2398 | set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags); | |
2399 | queue_delayed_work(cnic_wq, &cp->delete_task, | |
2400 | msecs_to_jiffies(2000)); | |
2401 | } | |
2402 | ||
2403 | memset(&kcqe, 0, sizeof(kcqe)); | |
2404 | kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN; | |
2405 | kcqe.fcoe_conn_id = req->conn_id; | |
2406 | kcqe.fcoe_conn_context_id = cid; | |
2407 | ||
2408 | cqes[0] = (struct kcqe *) &kcqe; | |
2409 | cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1); | |
2410 | return ret; | |
2411 | } | |
2412 | ||
2413 | static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe) | |
2414 | { | |
2415 | struct fcoe_kwqe_destroy *req; | |
2416 | union l5cm_specific_data l5_data; | |
2417 | struct cnic_local *cp = dev->cnic_priv; | |
2418 | int ret; | |
2419 | u32 cid; | |
2420 | ||
2421 | req = (struct fcoe_kwqe_destroy *) kwqe; | |
2422 | cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid); | |
2423 | ||
2424 | memset(&l5_data, 0, sizeof(l5_data)); | |
2425 | ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid, | |
2426 | FCOE_CONNECTION_TYPE, &l5_data); | |
2427 | return ret; | |
2428 | } | |
2429 | ||
2430 | static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev, | |
2431 | struct kwqe *wqes[], u32 num_wqes) | |
71034ba8 MC |
2432 | { |
2433 | int i, work, ret; | |
2434 | u32 opcode; | |
2435 | struct kwqe *kwqe; | |
2436 | ||
2437 | if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) | |
2438 | return -EAGAIN; /* bnx2 is down */ | |
2439 | ||
2440 | for (i = 0; i < num_wqes; ) { | |
2441 | kwqe = wqes[i]; | |
2442 | opcode = KWQE_OPCODE(kwqe->kwqe_op_flag); | |
2443 | work = 1; | |
2444 | ||
2445 | switch (opcode) { | |
2446 | case ISCSI_KWQE_OPCODE_INIT1: | |
2447 | ret = cnic_bnx2x_iscsi_init1(dev, kwqe); | |
2448 | break; | |
2449 | case ISCSI_KWQE_OPCODE_INIT2: | |
2450 | ret = cnic_bnx2x_iscsi_init2(dev, kwqe); | |
2451 | break; | |
2452 | case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1: | |
2453 | ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i], | |
2454 | num_wqes - i, &work); | |
2455 | break; | |
2456 | case ISCSI_KWQE_OPCODE_UPDATE_CONN: | |
2457 | ret = cnic_bnx2x_iscsi_update(dev, kwqe); | |
2458 | break; | |
2459 | case ISCSI_KWQE_OPCODE_DESTROY_CONN: | |
2460 | ret = cnic_bnx2x_iscsi_destroy(dev, kwqe); | |
2461 | break; | |
2462 | case L4_KWQE_OPCODE_VALUE_CONNECT1: | |
2463 | ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i, | |
2464 | &work); | |
2465 | break; | |
2466 | case L4_KWQE_OPCODE_VALUE_CLOSE: | |
2467 | ret = cnic_bnx2x_close(dev, kwqe); | |
2468 | break; | |
2469 | case L4_KWQE_OPCODE_VALUE_RESET: | |
2470 | ret = cnic_bnx2x_reset(dev, kwqe); | |
2471 | break; | |
2472 | case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG: | |
2473 | ret = cnic_bnx2x_offload_pg(dev, kwqe); | |
2474 | break; | |
2475 | case L4_KWQE_OPCODE_VALUE_UPDATE_PG: | |
2476 | ret = cnic_bnx2x_update_pg(dev, kwqe); | |
2477 | break; | |
2478 | case L4_KWQE_OPCODE_VALUE_UPLOAD_PG: | |
2479 | ret = 0; | |
2480 | break; | |
2481 | default: | |
2482 | ret = 0; | |
ddf79b20 JP |
2483 | netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n", |
2484 | opcode); | |
71034ba8 MC |
2485 | break; |
2486 | } | |
2487 | if (ret < 0) | |
ddf79b20 JP |
2488 | netdev_err(dev->netdev, "KWQE(0x%x) failed\n", |
2489 | opcode); | |
71034ba8 MC |
2490 | i += work; |
2491 | } | |
2492 | return 0; | |
2493 | } | |
2494 | ||
e1928c86 MC |
2495 | static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev, |
2496 | struct kwqe *wqes[], u32 num_wqes) | |
2497 | { | |
2498 | struct cnic_local *cp = dev->cnic_priv; | |
2499 | int i, work, ret; | |
2500 | u32 opcode; | |
2501 | struct kwqe *kwqe; | |
2502 | ||
2503 | if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) | |
2504 | return -EAGAIN; /* bnx2 is down */ | |
2505 | ||
2506 | if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710) | |
2507 | return -EINVAL; | |
2508 | ||
2509 | for (i = 0; i < num_wqes; ) { | |
2510 | kwqe = wqes[i]; | |
2511 | opcode = KWQE_OPCODE(kwqe->kwqe_op_flag); | |
2512 | work = 1; | |
2513 | ||
2514 | switch (opcode) { | |
2515 | case FCOE_KWQE_OPCODE_INIT1: | |
2516 | ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i], | |
2517 | num_wqes - i, &work); | |
2518 | break; | |
2519 | case FCOE_KWQE_OPCODE_OFFLOAD_CONN1: | |
2520 | ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i], | |
2521 | num_wqes - i, &work); | |
2522 | break; | |
2523 | case FCOE_KWQE_OPCODE_ENABLE_CONN: | |
2524 | ret = cnic_bnx2x_fcoe_enable(dev, kwqe); | |
2525 | break; | |
2526 | case FCOE_KWQE_OPCODE_DISABLE_CONN: | |
2527 | ret = cnic_bnx2x_fcoe_disable(dev, kwqe); | |
2528 | break; | |
2529 | case FCOE_KWQE_OPCODE_DESTROY_CONN: | |
2530 | ret = cnic_bnx2x_fcoe_destroy(dev, kwqe); | |
2531 | break; | |
2532 | case FCOE_KWQE_OPCODE_DESTROY: | |
2533 | ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe); | |
2534 | break; | |
2535 | case FCOE_KWQE_OPCODE_STAT: | |
2536 | ret = cnic_bnx2x_fcoe_stat(dev, kwqe); | |
2537 | break; | |
2538 | default: | |
2539 | ret = 0; | |
2540 | netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n", | |
2541 | opcode); | |
2542 | break; | |
2543 | } | |
2544 | if (ret < 0) | |
2545 | netdev_err(dev->netdev, "KWQE(0x%x) failed\n", | |
2546 | opcode); | |
2547 | i += work; | |
2548 | } | |
2549 | return 0; | |
2550 | } | |
2551 | ||
2552 | static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[], | |
2553 | u32 num_wqes) | |
2554 | { | |
2555 | int ret = -EINVAL; | |
2556 | u32 layer_code; | |
2557 | ||
2558 | if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) | |
2559 | return -EAGAIN; /* bnx2x is down */ | |
2560 | ||
2561 | if (!num_wqes) | |
2562 | return 0; | |
2563 | ||
2564 | layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK; | |
2565 | switch (layer_code) { | |
2566 | case KWQE_FLAGS_LAYER_MASK_L5_ISCSI: | |
2567 | case KWQE_FLAGS_LAYER_MASK_L4: | |
2568 | case KWQE_FLAGS_LAYER_MASK_L2: | |
2569 | ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes); | |
2570 | break; | |
2571 | ||
2572 | case KWQE_FLAGS_LAYER_MASK_L5_FCOE: | |
2573 | ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes); | |
2574 | break; | |
2575 | } | |
2576 | return ret; | |
2577 | } | |
2578 | ||
2579 | static inline u32 cnic_get_kcqe_layer_mask(u32 opflag) | |
2580 | { | |
2581 | if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN)) | |
2582 | return KCQE_FLAGS_LAYER_MASK_L4; | |
2583 | ||
2584 | return opflag & KCQE_FLAGS_LAYER_MASK; | |
2585 | } | |
2586 | ||
a4636960 MC |
2587 | static void service_kcqes(struct cnic_dev *dev, int num_cqes) |
2588 | { | |
2589 | struct cnic_local *cp = dev->cnic_priv; | |
c2bff63f | 2590 | int i, j, comp = 0; |
a4636960 MC |
2591 | |
2592 | i = 0; | |
2593 | j = 1; | |
2594 | while (num_cqes) { | |
2595 | struct cnic_ulp_ops *ulp_ops; | |
2596 | int ulp_type; | |
2597 | u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag; | |
e1928c86 | 2598 | u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag); |
a4636960 MC |
2599 | |
2600 | if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION)) | |
c2bff63f | 2601 | comp++; |
a4636960 MC |
2602 | |
2603 | while (j < num_cqes) { | |
2604 | u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag; | |
2605 | ||
e1928c86 | 2606 | if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer) |
a4636960 MC |
2607 | break; |
2608 | ||
2609 | if (unlikely(next_op & KCQE_RAMROD_COMPLETION)) | |
c2bff63f | 2610 | comp++; |
a4636960 MC |
2611 | j++; |
2612 | } | |
2613 | ||
2614 | if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA) | |
2615 | ulp_type = CNIC_ULP_RDMA; | |
2616 | else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI) | |
2617 | ulp_type = CNIC_ULP_ISCSI; | |
e1928c86 MC |
2618 | else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE) |
2619 | ulp_type = CNIC_ULP_FCOE; | |
a4636960 MC |
2620 | else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4) |
2621 | ulp_type = CNIC_ULP_L4; | |
2622 | else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2) | |
2623 | goto end; | |
2624 | else { | |
ddf79b20 JP |
2625 | netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n", |
2626 | kcqe_op_flag); | |
a4636960 MC |
2627 | goto end; |
2628 | } | |
2629 | ||
2630 | rcu_read_lock(); | |
2631 | ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]); | |
2632 | if (likely(ulp_ops)) { | |
2633 | ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type], | |
2634 | cp->completed_kcq + i, j); | |
2635 | } | |
2636 | rcu_read_unlock(); | |
2637 | end: | |
2638 | num_cqes -= j; | |
2639 | i += j; | |
2640 | j = 1; | |
2641 | } | |
c2bff63f DK |
2642 | if (unlikely(comp)) |
2643 | cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp); | |
a4636960 MC |
2644 | } |
2645 | ||
71034ba8 MC |
2646 | static u16 cnic_bnx2_next_idx(u16 idx) |
2647 | { | |
2648 | return idx + 1; | |
2649 | } | |
2650 | ||
2651 | static u16 cnic_bnx2_hw_idx(u16 idx) | |
2652 | { | |
2653 | return idx; | |
2654 | } | |
2655 | ||
2656 | static u16 cnic_bnx2x_next_idx(u16 idx) | |
a4636960 | 2657 | { |
71034ba8 MC |
2658 | idx++; |
2659 | if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT) | |
2660 | idx++; | |
2661 | ||
2662 | return idx; | |
a4636960 MC |
2663 | } |
2664 | ||
71034ba8 | 2665 | static u16 cnic_bnx2x_hw_idx(u16 idx) |
a4636960 | 2666 | { |
71034ba8 MC |
2667 | if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT) |
2668 | idx++; | |
a4636960 MC |
2669 | return idx; |
2670 | } | |
2671 | ||
644b9d4f | 2672 | static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info) |
a4636960 MC |
2673 | { |
2674 | struct cnic_local *cp = dev->cnic_priv; | |
644b9d4f | 2675 | u16 i, ri, hw_prod, last; |
a4636960 MC |
2676 | struct kcqe *kcqe; |
2677 | int kcqe_cnt = 0, last_cnt = 0; | |
2678 | ||
644b9d4f | 2679 | i = ri = last = info->sw_prod_idx; |
a4636960 | 2680 | ri &= MAX_KCQ_IDX; |
644b9d4f MC |
2681 | hw_prod = *info->hw_prod_idx_ptr; |
2682 | hw_prod = cp->hw_idx(hw_prod); | |
a4636960 MC |
2683 | |
2684 | while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) { | |
644b9d4f | 2685 | kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)]; |
a4636960 MC |
2686 | cp->completed_kcq[kcqe_cnt++] = kcqe; |
2687 | i = cp->next_idx(i); | |
2688 | ri = i & MAX_KCQ_IDX; | |
2689 | if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) { | |
2690 | last_cnt = kcqe_cnt; | |
2691 | last = i; | |
2692 | } | |
2693 | } | |
2694 | ||
644b9d4f | 2695 | info->sw_prod_idx = last; |
a4636960 MC |
2696 | return last_cnt; |
2697 | } | |
2698 | ||
48f753d2 MC |
2699 | static int cnic_l2_completion(struct cnic_local *cp) |
2700 | { | |
2701 | u16 hw_cons, sw_cons; | |
cd801536 | 2702 | struct cnic_uio_dev *udev = cp->udev; |
48f753d2 | 2703 | union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *) |
cd801536 | 2704 | (udev->l2_ring + (2 * BCM_PAGE_SIZE)); |
48f753d2 MC |
2705 | u32 cmd; |
2706 | int comp = 0; | |
2707 | ||
2708 | if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags)) | |
2709 | return 0; | |
2710 | ||
2711 | hw_cons = *cp->rx_cons_ptr; | |
2712 | if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT) | |
2713 | hw_cons++; | |
2714 | ||
2715 | sw_cons = cp->rx_cons; | |
2716 | while (sw_cons != hw_cons) { | |
2717 | u8 cqe_fp_flags; | |
2718 | ||
2719 | cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT]; | |
2720 | cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; | |
2721 | if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) { | |
2722 | cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data); | |
2723 | cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT; | |
2724 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP || | |
2725 | cmd == RAMROD_CMD_ID_ETH_HALT) | |
2726 | comp++; | |
2727 | } | |
2728 | sw_cons = BNX2X_NEXT_RCQE(sw_cons); | |
2729 | } | |
2730 | return comp; | |
2731 | } | |
2732 | ||
86b53606 | 2733 | static void cnic_chk_pkt_rings(struct cnic_local *cp) |
a4636960 | 2734 | { |
541a7810 | 2735 | u16 rx_cons, tx_cons; |
48f753d2 | 2736 | int comp = 0; |
a4636960 | 2737 | |
541a7810 | 2738 | if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags)) |
66fee9ed MC |
2739 | return; |
2740 | ||
541a7810 MC |
2741 | rx_cons = *cp->rx_cons_ptr; |
2742 | tx_cons = *cp->tx_cons_ptr; | |
a4636960 | 2743 | if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) { |
48f753d2 MC |
2744 | if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags)) |
2745 | comp = cnic_l2_completion(cp); | |
2746 | ||
a4636960 MC |
2747 | cp->tx_cons = tx_cons; |
2748 | cp->rx_cons = rx_cons; | |
71034ba8 | 2749 | |
cd801536 MC |
2750 | if (cp->udev) |
2751 | uio_event_notify(&cp->udev->cnic_uinfo); | |
a4636960 | 2752 | } |
48f753d2 MC |
2753 | if (comp) |
2754 | clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags); | |
a4636960 MC |
2755 | } |
2756 | ||
b177a5d5 | 2757 | static u32 cnic_service_bnx2_queues(struct cnic_dev *dev) |
a4636960 | 2758 | { |
a4636960 | 2759 | struct cnic_local *cp = dev->cnic_priv; |
b177a5d5 | 2760 | u32 status_idx = (u16) *cp->kcq1.status_idx_ptr; |
a4636960 MC |
2761 | int kcqe_cnt; |
2762 | ||
a4636960 MC |
2763 | cp->kwq_con_idx = *cp->kwq_con_idx_ptr; |
2764 | ||
644b9d4f | 2765 | while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) { |
a4636960 MC |
2766 | |
2767 | service_kcqes(dev, kcqe_cnt); | |
2768 | ||
2769 | /* Tell compiler that status_blk fields can change. */ | |
2770 | barrier(); | |
644b9d4f | 2771 | if (status_idx != *cp->kcq1.status_idx_ptr) { |
b177a5d5 | 2772 | status_idx = (u16) *cp->kcq1.status_idx_ptr; |
a4636960 | 2773 | cp->kwq_con_idx = *cp->kwq_con_idx_ptr; |
a4636960 MC |
2774 | } else |
2775 | break; | |
2776 | } | |
2777 | ||
644b9d4f | 2778 | CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx); |
a4636960 | 2779 | |
86b53606 | 2780 | cnic_chk_pkt_rings(cp); |
b177a5d5 | 2781 | |
a4636960 MC |
2782 | return status_idx; |
2783 | } | |
2784 | ||
b177a5d5 | 2785 | static int cnic_service_bnx2(void *data, void *status_blk) |
a4636960 | 2786 | { |
b177a5d5 | 2787 | struct cnic_dev *dev = data; |
a4636960 | 2788 | |
eaaa6e9c MC |
2789 | if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) { |
2790 | struct status_block *sblk = status_blk; | |
2791 | ||
2792 | return sblk->status_idx; | |
2793 | } | |
a4636960 | 2794 | |
b177a5d5 MC |
2795 | return cnic_service_bnx2_queues(dev); |
2796 | } | |
a4636960 | 2797 | |
b177a5d5 MC |
2798 | static void cnic_service_bnx2_msix(unsigned long data) |
2799 | { | |
2800 | struct cnic_dev *dev = (struct cnic_dev *) data; | |
2801 | struct cnic_local *cp = dev->cnic_priv; | |
a4636960 | 2802 | |
b177a5d5 | 2803 | cp->last_status_idx = cnic_service_bnx2_queues(dev); |
a4636960 | 2804 | |
a4636960 MC |
2805 | CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num | |
2806 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx); | |
2807 | } | |
2808 | ||
66fee9ed MC |
2809 | static void cnic_doirq(struct cnic_dev *dev) |
2810 | { | |
2811 | struct cnic_local *cp = dev->cnic_priv; | |
66fee9ed MC |
2812 | |
2813 | if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) { | |
eaaa6e9c MC |
2814 | u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX; |
2815 | ||
66fee9ed | 2816 | prefetch(cp->status_blk.gen); |
e6c28894 | 2817 | prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]); |
66fee9ed MC |
2818 | |
2819 | tasklet_schedule(&cp->cnic_irq_task); | |
2820 | } | |
2821 | } | |
2822 | ||
a4636960 MC |
2823 | static irqreturn_t cnic_irq(int irq, void *dev_instance) |
2824 | { | |
2825 | struct cnic_dev *dev = dev_instance; | |
2826 | struct cnic_local *cp = dev->cnic_priv; | |
a4636960 MC |
2827 | |
2828 | if (cp->ack_int) | |
2829 | cp->ack_int(dev); | |
2830 | ||
66fee9ed | 2831 | cnic_doirq(dev); |
a4636960 MC |
2832 | |
2833 | return IRQ_HANDLED; | |
2834 | } | |
2835 | ||
71034ba8 MC |
2836 | static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm, |
2837 | u16 index, u8 op, u8 update) | |
2838 | { | |
2839 | struct cnic_local *cp = dev->cnic_priv; | |
2840 | u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 + | |
2841 | COMMAND_REG_INT_ACK); | |
2842 | struct igu_ack_register igu_ack; | |
2843 | ||
2844 | igu_ack.status_block_index = index; | |
2845 | igu_ack.sb_id_and_flags = | |
2846 | ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
2847 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
2848 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
2849 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
2850 | ||
2851 | CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack)); | |
2852 | } | |
2853 | ||
ee87a82a MC |
2854 | static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment, |
2855 | u16 index, u8 op, u8 update) | |
2856 | { | |
2857 | struct igu_regular cmd_data; | |
2858 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8; | |
2859 | ||
2860 | cmd_data.sb_id_and_flags = | |
2861 | (index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
2862 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
2863 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
2864 | (op << IGU_REGULAR_ENABLE_INT_SHIFT); | |
2865 | ||
2866 | ||
2867 | CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags); | |
2868 | } | |
2869 | ||
71034ba8 MC |
2870 | static void cnic_ack_bnx2x_msix(struct cnic_dev *dev) |
2871 | { | |
2872 | struct cnic_local *cp = dev->cnic_priv; | |
2873 | ||
523224a3 | 2874 | cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0, |
71034ba8 MC |
2875 | IGU_INT_DISABLE, 0); |
2876 | } | |
2877 | ||
ee87a82a MC |
2878 | static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev) |
2879 | { | |
2880 | struct cnic_local *cp = dev->cnic_priv; | |
2881 | ||
2882 | cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0, | |
2883 | IGU_INT_DISABLE, 0); | |
2884 | } | |
2885 | ||
b177a5d5 | 2886 | static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info) |
71034ba8 | 2887 | { |
b177a5d5 | 2888 | u32 last_status = *info->status_idx_ptr; |
71034ba8 MC |
2889 | int kcqe_cnt; |
2890 | ||
b177a5d5 | 2891 | while ((kcqe_cnt = cnic_get_kcqes(dev, info))) { |
71034ba8 MC |
2892 | |
2893 | service_kcqes(dev, kcqe_cnt); | |
2894 | ||
2895 | /* Tell compiler that sblk fields can change. */ | |
2896 | barrier(); | |
b177a5d5 | 2897 | if (last_status == *info->status_idx_ptr) |
71034ba8 MC |
2898 | break; |
2899 | ||
b177a5d5 | 2900 | last_status = *info->status_idx_ptr; |
71034ba8 | 2901 | } |
b177a5d5 MC |
2902 | return last_status; |
2903 | } | |
2904 | ||
2905 | static void cnic_service_bnx2x_bh(unsigned long data) | |
2906 | { | |
2907 | struct cnic_dev *dev = (struct cnic_dev *) data; | |
2908 | struct cnic_local *cp = dev->cnic_priv; | |
2909 | u32 status_idx; | |
2910 | ||
2911 | if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) | |
2912 | return; | |
2913 | ||
2914 | status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1); | |
71034ba8 | 2915 | |
644b9d4f | 2916 | CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX); |
e21ba414 MC |
2917 | |
2918 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { | |
2919 | status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2); | |
2920 | ||
2921 | CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx + | |
2922 | MAX_KCQ_IDX); | |
2923 | ||
ee87a82a MC |
2924 | cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, |
2925 | status_idx, IGU_INT_ENABLE, 1); | |
e21ba414 | 2926 | } else { |
ee87a82a MC |
2927 | cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID, |
2928 | status_idx, IGU_INT_ENABLE, 1); | |
e21ba414 | 2929 | } |
71034ba8 MC |
2930 | } |
2931 | ||
2932 | static int cnic_service_bnx2x(void *data, void *status_blk) | |
2933 | { | |
2934 | struct cnic_dev *dev = data; | |
2935 | struct cnic_local *cp = dev->cnic_priv; | |
71034ba8 | 2936 | |
66fee9ed MC |
2937 | if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)) |
2938 | cnic_doirq(dev); | |
71034ba8 | 2939 | |
66fee9ed | 2940 | cnic_chk_pkt_rings(cp); |
71034ba8 MC |
2941 | |
2942 | return 0; | |
2943 | } | |
2944 | ||
a4636960 MC |
2945 | static void cnic_ulp_stop(struct cnic_dev *dev) |
2946 | { | |
2947 | struct cnic_local *cp = dev->cnic_priv; | |
2948 | int if_type; | |
2949 | ||
cd801536 | 2950 | cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL); |
6d7760a8 | 2951 | |
a4636960 MC |
2952 | for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) { |
2953 | struct cnic_ulp_ops *ulp_ops; | |
2954 | ||
681dbd71 MC |
2955 | mutex_lock(&cnic_lock); |
2956 | ulp_ops = cp->ulp_ops[if_type]; | |
2957 | if (!ulp_ops) { | |
2958 | mutex_unlock(&cnic_lock); | |
a4636960 | 2959 | continue; |
681dbd71 MC |
2960 | } |
2961 | set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]); | |
2962 | mutex_unlock(&cnic_lock); | |
a4636960 MC |
2963 | |
2964 | if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type])) | |
2965 | ulp_ops->cnic_stop(cp->ulp_handle[if_type]); | |
681dbd71 MC |
2966 | |
2967 | clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]); | |
a4636960 | 2968 | } |
a4636960 MC |
2969 | } |
2970 | ||
2971 | static void cnic_ulp_start(struct cnic_dev *dev) | |
2972 | { | |
2973 | struct cnic_local *cp = dev->cnic_priv; | |
2974 | int if_type; | |
2975 | ||
a4636960 MC |
2976 | for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) { |
2977 | struct cnic_ulp_ops *ulp_ops; | |
2978 | ||
681dbd71 MC |
2979 | mutex_lock(&cnic_lock); |
2980 | ulp_ops = cp->ulp_ops[if_type]; | |
2981 | if (!ulp_ops || !ulp_ops->cnic_start) { | |
2982 | mutex_unlock(&cnic_lock); | |
a4636960 | 2983 | continue; |
681dbd71 MC |
2984 | } |
2985 | set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]); | |
2986 | mutex_unlock(&cnic_lock); | |
a4636960 MC |
2987 | |
2988 | if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type])) | |
2989 | ulp_ops->cnic_start(cp->ulp_handle[if_type]); | |
681dbd71 MC |
2990 | |
2991 | clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]); | |
a4636960 | 2992 | } |
a4636960 MC |
2993 | } |
2994 | ||
2995 | static int cnic_ctl(void *data, struct cnic_ctl_info *info) | |
2996 | { | |
2997 | struct cnic_dev *dev = data; | |
2998 | ||
2999 | switch (info->cmd) { | |
3000 | case CNIC_CTL_STOP_CMD: | |
3001 | cnic_hold(dev); | |
a4636960 MC |
3002 | |
3003 | cnic_ulp_stop(dev); | |
3004 | cnic_stop_hw(dev); | |
3005 | ||
a4636960 MC |
3006 | cnic_put(dev); |
3007 | break; | |
3008 | case CNIC_CTL_START_CMD: | |
3009 | cnic_hold(dev); | |
a4636960 MC |
3010 | |
3011 | if (!cnic_start_hw(dev)) | |
3012 | cnic_ulp_start(dev); | |
3013 | ||
a4636960 MC |
3014 | cnic_put(dev); |
3015 | break; | |
71034ba8 MC |
3016 | case CNIC_CTL_COMPLETION_CMD: { |
3017 | u32 cid = BNX2X_SW_CID(info->data.comp.cid); | |
3018 | u32 l5_cid; | |
3019 | struct cnic_local *cp = dev->cnic_priv; | |
3020 | ||
3021 | if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) { | |
3022 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
3023 | ||
3024 | ctx->wait_cond = 1; | |
3025 | wake_up(&ctx->waitq); | |
3026 | } | |
3027 | break; | |
3028 | } | |
a4636960 MC |
3029 | default: |
3030 | return -EINVAL; | |
3031 | } | |
3032 | return 0; | |
3033 | } | |
3034 | ||
3035 | static void cnic_ulp_init(struct cnic_dev *dev) | |
3036 | { | |
3037 | int i; | |
3038 | struct cnic_local *cp = dev->cnic_priv; | |
3039 | ||
a4636960 MC |
3040 | for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) { |
3041 | struct cnic_ulp_ops *ulp_ops; | |
3042 | ||
7fc1ece4 MC |
3043 | mutex_lock(&cnic_lock); |
3044 | ulp_ops = cnic_ulp_tbl[i]; | |
3045 | if (!ulp_ops || !ulp_ops->cnic_init) { | |
3046 | mutex_unlock(&cnic_lock); | |
a4636960 | 3047 | continue; |
7fc1ece4 MC |
3048 | } |
3049 | ulp_get(ulp_ops); | |
3050 | mutex_unlock(&cnic_lock); | |
a4636960 MC |
3051 | |
3052 | if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i])) | |
3053 | ulp_ops->cnic_init(dev); | |
3054 | ||
7fc1ece4 | 3055 | ulp_put(ulp_ops); |
a4636960 | 3056 | } |
a4636960 MC |
3057 | } |
3058 | ||
3059 | static void cnic_ulp_exit(struct cnic_dev *dev) | |
3060 | { | |
3061 | int i; | |
3062 | struct cnic_local *cp = dev->cnic_priv; | |
3063 | ||
a4636960 MC |
3064 | for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) { |
3065 | struct cnic_ulp_ops *ulp_ops; | |
3066 | ||
7fc1ece4 MC |
3067 | mutex_lock(&cnic_lock); |
3068 | ulp_ops = cnic_ulp_tbl[i]; | |
3069 | if (!ulp_ops || !ulp_ops->cnic_exit) { | |
3070 | mutex_unlock(&cnic_lock); | |
a4636960 | 3071 | continue; |
7fc1ece4 MC |
3072 | } |
3073 | ulp_get(ulp_ops); | |
3074 | mutex_unlock(&cnic_lock); | |
a4636960 MC |
3075 | |
3076 | if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i])) | |
3077 | ulp_ops->cnic_exit(dev); | |
3078 | ||
7fc1ece4 | 3079 | ulp_put(ulp_ops); |
a4636960 | 3080 | } |
a4636960 MC |
3081 | } |
3082 | ||
3083 | static int cnic_cm_offload_pg(struct cnic_sock *csk) | |
3084 | { | |
3085 | struct cnic_dev *dev = csk->dev; | |
3086 | struct l4_kwq_offload_pg *l4kwqe; | |
3087 | struct kwqe *wqes[1]; | |
3088 | ||
3089 | l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1; | |
3090 | memset(l4kwqe, 0, sizeof(*l4kwqe)); | |
3091 | wqes[0] = (struct kwqe *) l4kwqe; | |
3092 | ||
3093 | l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG; | |
3094 | l4kwqe->flags = | |
3095 | L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT; | |
3096 | l4kwqe->l2hdr_nbytes = ETH_HLEN; | |
3097 | ||
3098 | l4kwqe->da0 = csk->ha[0]; | |
3099 | l4kwqe->da1 = csk->ha[1]; | |
3100 | l4kwqe->da2 = csk->ha[2]; | |
3101 | l4kwqe->da3 = csk->ha[3]; | |
3102 | l4kwqe->da4 = csk->ha[4]; | |
3103 | l4kwqe->da5 = csk->ha[5]; | |
3104 | ||
3105 | l4kwqe->sa0 = dev->mac_addr[0]; | |
3106 | l4kwqe->sa1 = dev->mac_addr[1]; | |
3107 | l4kwqe->sa2 = dev->mac_addr[2]; | |
3108 | l4kwqe->sa3 = dev->mac_addr[3]; | |
3109 | l4kwqe->sa4 = dev->mac_addr[4]; | |
3110 | l4kwqe->sa5 = dev->mac_addr[5]; | |
3111 | ||
3112 | l4kwqe->etype = ETH_P_IP; | |
a9736c08 | 3113 | l4kwqe->ipid_start = DEF_IPID_START; |
a4636960 MC |
3114 | l4kwqe->host_opaque = csk->l5_cid; |
3115 | ||
3116 | if (csk->vlan_id) { | |
3117 | l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING; | |
3118 | l4kwqe->vlan_tag = csk->vlan_id; | |
3119 | l4kwqe->l2hdr_nbytes += 4; | |
3120 | } | |
3121 | ||
3122 | return dev->submit_kwqes(dev, wqes, 1); | |
3123 | } | |
3124 | ||
3125 | static int cnic_cm_update_pg(struct cnic_sock *csk) | |
3126 | { | |
3127 | struct cnic_dev *dev = csk->dev; | |
3128 | struct l4_kwq_update_pg *l4kwqe; | |
3129 | struct kwqe *wqes[1]; | |
3130 | ||
3131 | l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1; | |
3132 | memset(l4kwqe, 0, sizeof(*l4kwqe)); | |
3133 | wqes[0] = (struct kwqe *) l4kwqe; | |
3134 | ||
3135 | l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG; | |
3136 | l4kwqe->flags = | |
3137 | L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT; | |
3138 | l4kwqe->pg_cid = csk->pg_cid; | |
3139 | ||
3140 | l4kwqe->da0 = csk->ha[0]; | |
3141 | l4kwqe->da1 = csk->ha[1]; | |
3142 | l4kwqe->da2 = csk->ha[2]; | |
3143 | l4kwqe->da3 = csk->ha[3]; | |
3144 | l4kwqe->da4 = csk->ha[4]; | |
3145 | l4kwqe->da5 = csk->ha[5]; | |
3146 | ||
3147 | l4kwqe->pg_host_opaque = csk->l5_cid; | |
3148 | l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA; | |
3149 | ||
3150 | return dev->submit_kwqes(dev, wqes, 1); | |
3151 | } | |
3152 | ||
3153 | static int cnic_cm_upload_pg(struct cnic_sock *csk) | |
3154 | { | |
3155 | struct cnic_dev *dev = csk->dev; | |
3156 | struct l4_kwq_upload *l4kwqe; | |
3157 | struct kwqe *wqes[1]; | |
3158 | ||
3159 | l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1; | |
3160 | memset(l4kwqe, 0, sizeof(*l4kwqe)); | |
3161 | wqes[0] = (struct kwqe *) l4kwqe; | |
3162 | ||
3163 | l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG; | |
3164 | l4kwqe->flags = | |
3165 | L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT; | |
3166 | l4kwqe->cid = csk->pg_cid; | |
3167 | ||
3168 | return dev->submit_kwqes(dev, wqes, 1); | |
3169 | } | |
3170 | ||
3171 | static int cnic_cm_conn_req(struct cnic_sock *csk) | |
3172 | { | |
3173 | struct cnic_dev *dev = csk->dev; | |
3174 | struct l4_kwq_connect_req1 *l4kwqe1; | |
3175 | struct l4_kwq_connect_req2 *l4kwqe2; | |
3176 | struct l4_kwq_connect_req3 *l4kwqe3; | |
3177 | struct kwqe *wqes[3]; | |
3178 | u8 tcp_flags = 0; | |
3179 | int num_wqes = 2; | |
3180 | ||
3181 | l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1; | |
3182 | l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2; | |
3183 | l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3; | |
3184 | memset(l4kwqe1, 0, sizeof(*l4kwqe1)); | |
3185 | memset(l4kwqe2, 0, sizeof(*l4kwqe2)); | |
3186 | memset(l4kwqe3, 0, sizeof(*l4kwqe3)); | |
3187 | ||
3188 | l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3; | |
3189 | l4kwqe3->flags = | |
3190 | L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT; | |
3191 | l4kwqe3->ka_timeout = csk->ka_timeout; | |
3192 | l4kwqe3->ka_interval = csk->ka_interval; | |
3193 | l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count; | |
3194 | l4kwqe3->tos = csk->tos; | |
3195 | l4kwqe3->ttl = csk->ttl; | |
3196 | l4kwqe3->snd_seq_scale = csk->snd_seq_scale; | |
3197 | l4kwqe3->pmtu = csk->mtu; | |
3198 | l4kwqe3->rcv_buf = csk->rcv_buf; | |
3199 | l4kwqe3->snd_buf = csk->snd_buf; | |
3200 | l4kwqe3->seed = csk->seed; | |
3201 | ||
3202 | wqes[0] = (struct kwqe *) l4kwqe1; | |
3203 | if (test_bit(SK_F_IPV6, &csk->flags)) { | |
3204 | wqes[1] = (struct kwqe *) l4kwqe2; | |
3205 | wqes[2] = (struct kwqe *) l4kwqe3; | |
3206 | num_wqes = 3; | |
3207 | ||
3208 | l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6; | |
3209 | l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2; | |
3210 | l4kwqe2->flags = | |
3211 | L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT | | |
3212 | L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT; | |
3213 | l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]); | |
3214 | l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]); | |
3215 | l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]); | |
3216 | l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]); | |
3217 | l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]); | |
3218 | l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]); | |
3219 | l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) - | |
3220 | sizeof(struct tcphdr); | |
3221 | } else { | |
3222 | wqes[1] = (struct kwqe *) l4kwqe3; | |
3223 | l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) - | |
3224 | sizeof(struct tcphdr); | |
3225 | } | |
3226 | ||
3227 | l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1; | |
3228 | l4kwqe1->flags = | |
3229 | (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) | | |
3230 | L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT; | |
3231 | l4kwqe1->cid = csk->cid; | |
3232 | l4kwqe1->pg_cid = csk->pg_cid; | |
3233 | l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]); | |
3234 | l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]); | |
3235 | l4kwqe1->src_port = be16_to_cpu(csk->src_port); | |
3236 | l4kwqe1->dst_port = be16_to_cpu(csk->dst_port); | |
3237 | if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK) | |
3238 | tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK; | |
3239 | if (csk->tcp_flags & SK_TCP_KEEP_ALIVE) | |
3240 | tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE; | |
3241 | if (csk->tcp_flags & SK_TCP_NAGLE) | |
3242 | tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE; | |
3243 | if (csk->tcp_flags & SK_TCP_TIMESTAMP) | |
3244 | tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP; | |
3245 | if (csk->tcp_flags & SK_TCP_SACK) | |
3246 | tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK; | |
3247 | if (csk->tcp_flags & SK_TCP_SEG_SCALING) | |
3248 | tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING; | |
3249 | ||
3250 | l4kwqe1->tcp_flags = tcp_flags; | |
3251 | ||
3252 | return dev->submit_kwqes(dev, wqes, num_wqes); | |
3253 | } | |
3254 | ||
3255 | static int cnic_cm_close_req(struct cnic_sock *csk) | |
3256 | { | |
3257 | struct cnic_dev *dev = csk->dev; | |
3258 | struct l4_kwq_close_req *l4kwqe; | |
3259 | struct kwqe *wqes[1]; | |
3260 | ||
3261 | l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2; | |
3262 | memset(l4kwqe, 0, sizeof(*l4kwqe)); | |
3263 | wqes[0] = (struct kwqe *) l4kwqe; | |
3264 | ||
3265 | l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE; | |
3266 | l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT; | |
3267 | l4kwqe->cid = csk->cid; | |
3268 | ||
3269 | return dev->submit_kwqes(dev, wqes, 1); | |
3270 | } | |
3271 | ||
3272 | static int cnic_cm_abort_req(struct cnic_sock *csk) | |
3273 | { | |
3274 | struct cnic_dev *dev = csk->dev; | |
3275 | struct l4_kwq_reset_req *l4kwqe; | |
3276 | struct kwqe *wqes[1]; | |
3277 | ||
3278 | l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2; | |
3279 | memset(l4kwqe, 0, sizeof(*l4kwqe)); | |
3280 | wqes[0] = (struct kwqe *) l4kwqe; | |
3281 | ||
3282 | l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET; | |
3283 | l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT; | |
3284 | l4kwqe->cid = csk->cid; | |
3285 | ||
3286 | return dev->submit_kwqes(dev, wqes, 1); | |
3287 | } | |
3288 | ||
3289 | static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid, | |
3290 | u32 l5_cid, struct cnic_sock **csk, void *context) | |
3291 | { | |
3292 | struct cnic_local *cp = dev->cnic_priv; | |
3293 | struct cnic_sock *csk1; | |
3294 | ||
3295 | if (l5_cid >= MAX_CM_SK_TBL_SZ) | |
3296 | return -EINVAL; | |
3297 | ||
fdf24086 MC |
3298 | if (cp->ctx_tbl) { |
3299 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
3300 | ||
3301 | if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) | |
3302 | return -EAGAIN; | |
3303 | } | |
3304 | ||
a4636960 MC |
3305 | csk1 = &cp->csk_tbl[l5_cid]; |
3306 | if (atomic_read(&csk1->ref_count)) | |
3307 | return -EAGAIN; | |
3308 | ||
3309 | if (test_and_set_bit(SK_F_INUSE, &csk1->flags)) | |
3310 | return -EBUSY; | |
3311 | ||
3312 | csk1->dev = dev; | |
3313 | csk1->cid = cid; | |
3314 | csk1->l5_cid = l5_cid; | |
3315 | csk1->ulp_type = ulp_type; | |
3316 | csk1->context = context; | |
3317 | ||
3318 | csk1->ka_timeout = DEF_KA_TIMEOUT; | |
3319 | csk1->ka_interval = DEF_KA_INTERVAL; | |
3320 | csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT; | |
3321 | csk1->tos = DEF_TOS; | |
3322 | csk1->ttl = DEF_TTL; | |
3323 | csk1->snd_seq_scale = DEF_SND_SEQ_SCALE; | |
3324 | csk1->rcv_buf = DEF_RCV_BUF; | |
3325 | csk1->snd_buf = DEF_SND_BUF; | |
3326 | csk1->seed = DEF_SEED; | |
3327 | ||
3328 | *csk = csk1; | |
3329 | return 0; | |
3330 | } | |
3331 | ||
3332 | static void cnic_cm_cleanup(struct cnic_sock *csk) | |
3333 | { | |
3334 | if (csk->src_port) { | |
3335 | struct cnic_dev *dev = csk->dev; | |
3336 | struct cnic_local *cp = dev->cnic_priv; | |
3337 | ||
9b093360 | 3338 | cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port)); |
a4636960 MC |
3339 | csk->src_port = 0; |
3340 | } | |
3341 | } | |
3342 | ||
3343 | static void cnic_close_conn(struct cnic_sock *csk) | |
3344 | { | |
3345 | if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) { | |
3346 | cnic_cm_upload_pg(csk); | |
3347 | clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags); | |
3348 | } | |
3349 | cnic_cm_cleanup(csk); | |
3350 | } | |
3351 | ||
3352 | static int cnic_cm_destroy(struct cnic_sock *csk) | |
3353 | { | |
3354 | if (!cnic_in_use(csk)) | |
3355 | return -EINVAL; | |
3356 | ||
3357 | csk_hold(csk); | |
3358 | clear_bit(SK_F_INUSE, &csk->flags); | |
3359 | smp_mb__after_clear_bit(); | |
3360 | while (atomic_read(&csk->ref_count) != 1) | |
3361 | msleep(1); | |
3362 | cnic_cm_cleanup(csk); | |
3363 | ||
3364 | csk->flags = 0; | |
3365 | csk_put(csk); | |
3366 | return 0; | |
3367 | } | |
3368 | ||
3369 | static inline u16 cnic_get_vlan(struct net_device *dev, | |
3370 | struct net_device **vlan_dev) | |
3371 | { | |
3372 | if (dev->priv_flags & IFF_802_1Q_VLAN) { | |
3373 | *vlan_dev = vlan_dev_real_dev(dev); | |
3374 | return vlan_dev_vlan_id(dev); | |
3375 | } | |
3376 | *vlan_dev = dev; | |
3377 | return 0; | |
3378 | } | |
3379 | ||
3380 | static int cnic_get_v4_route(struct sockaddr_in *dst_addr, | |
3381 | struct dst_entry **dst) | |
3382 | { | |
faea56c9 | 3383 | #if defined(CONFIG_INET) |
a4636960 MC |
3384 | struct flowi fl; |
3385 | int err; | |
3386 | struct rtable *rt; | |
3387 | ||
3388 | memset(&fl, 0, sizeof(fl)); | |
3389 | fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr; | |
3390 | ||
3391 | err = ip_route_output_key(&init_net, &rt, &fl); | |
3392 | if (!err) | |
d8d1f30b | 3393 | *dst = &rt->dst; |
a4636960 | 3394 | return err; |
faea56c9 RD |
3395 | #else |
3396 | return -ENETUNREACH; | |
3397 | #endif | |
a4636960 MC |
3398 | } |
3399 | ||
3400 | static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr, | |
3401 | struct dst_entry **dst) | |
3402 | { | |
faea56c9 | 3403 | #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE)) |
a4636960 MC |
3404 | struct flowi fl; |
3405 | ||
3406 | memset(&fl, 0, sizeof(fl)); | |
3407 | ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr); | |
3408 | if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL) | |
3409 | fl.oif = dst_addr->sin6_scope_id; | |
3410 | ||
3411 | *dst = ip6_route_output(&init_net, NULL, &fl); | |
3412 | if (*dst) | |
3413 | return 0; | |
3414 | #endif | |
3415 | ||
3416 | return -ENETUNREACH; | |
3417 | } | |
3418 | ||
3419 | static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr, | |
3420 | int ulp_type) | |
3421 | { | |
3422 | struct cnic_dev *dev = NULL; | |
3423 | struct dst_entry *dst; | |
3424 | struct net_device *netdev = NULL; | |
3425 | int err = -ENETUNREACH; | |
3426 | ||
3427 | if (dst_addr->sin_family == AF_INET) | |
3428 | err = cnic_get_v4_route(dst_addr, &dst); | |
3429 | else if (dst_addr->sin_family == AF_INET6) { | |
3430 | struct sockaddr_in6 *dst_addr6 = | |
3431 | (struct sockaddr_in6 *) dst_addr; | |
3432 | ||
3433 | err = cnic_get_v6_route(dst_addr6, &dst); | |
3434 | } else | |
3435 | return NULL; | |
3436 | ||
3437 | if (err) | |
3438 | return NULL; | |
3439 | ||
3440 | if (!dst->dev) | |
3441 | goto done; | |
3442 | ||
3443 | cnic_get_vlan(dst->dev, &netdev); | |
3444 | ||
3445 | dev = cnic_from_netdev(netdev); | |
3446 | ||
3447 | done: | |
3448 | dst_release(dst); | |
3449 | if (dev) | |
3450 | cnic_put(dev); | |
3451 | return dev; | |
3452 | } | |
3453 | ||
3454 | static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr) | |
3455 | { | |
3456 | struct cnic_dev *dev = csk->dev; | |
3457 | struct cnic_local *cp = dev->cnic_priv; | |
3458 | ||
3459 | return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk); | |
3460 | } | |
3461 | ||
3462 | static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr) | |
3463 | { | |
3464 | struct cnic_dev *dev = csk->dev; | |
3465 | struct cnic_local *cp = dev->cnic_priv; | |
c76284af MC |
3466 | int is_v6, rc = 0; |
3467 | struct dst_entry *dst = NULL; | |
a4636960 | 3468 | struct net_device *realdev; |
9b093360 MC |
3469 | __be16 local_port; |
3470 | u32 port_id; | |
a4636960 MC |
3471 | |
3472 | if (saddr->local.v6.sin6_family == AF_INET6 && | |
3473 | saddr->remote.v6.sin6_family == AF_INET6) | |
3474 | is_v6 = 1; | |
3475 | else if (saddr->local.v4.sin_family == AF_INET && | |
3476 | saddr->remote.v4.sin_family == AF_INET) | |
3477 | is_v6 = 0; | |
3478 | else | |
3479 | return -EINVAL; | |
3480 | ||
3481 | clear_bit(SK_F_IPV6, &csk->flags); | |
3482 | ||
3483 | if (is_v6) { | |
a4636960 | 3484 | set_bit(SK_F_IPV6, &csk->flags); |
c76284af | 3485 | cnic_get_v6_route(&saddr->remote.v6, &dst); |
a4636960 MC |
3486 | |
3487 | memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr, | |
3488 | sizeof(struct in6_addr)); | |
3489 | csk->dst_port = saddr->remote.v6.sin6_port; | |
3490 | local_port = saddr->local.v6.sin6_port; | |
a4636960 MC |
3491 | |
3492 | } else { | |
c76284af | 3493 | cnic_get_v4_route(&saddr->remote.v4, &dst); |
a4636960 MC |
3494 | |
3495 | csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr; | |
3496 | csk->dst_port = saddr->remote.v4.sin_port; | |
3497 | local_port = saddr->local.v4.sin_port; | |
3498 | } | |
3499 | ||
c76284af MC |
3500 | csk->vlan_id = 0; |
3501 | csk->mtu = dev->netdev->mtu; | |
3502 | if (dst && dst->dev) { | |
3503 | u16 vlan = cnic_get_vlan(dst->dev, &realdev); | |
3504 | if (realdev == dev->netdev) { | |
3505 | csk->vlan_id = vlan; | |
3506 | csk->mtu = dst_mtu(dst); | |
3507 | } | |
3508 | } | |
a4636960 | 3509 | |
9b093360 MC |
3510 | port_id = be16_to_cpu(local_port); |
3511 | if (port_id >= CNIC_LOCAL_PORT_MIN && | |
3512 | port_id < CNIC_LOCAL_PORT_MAX) { | |
3513 | if (cnic_alloc_id(&cp->csk_port_tbl, port_id)) | |
3514 | port_id = 0; | |
a4636960 | 3515 | } else |
9b093360 | 3516 | port_id = 0; |
a4636960 | 3517 | |
9b093360 MC |
3518 | if (!port_id) { |
3519 | port_id = cnic_alloc_new_id(&cp->csk_port_tbl); | |
3520 | if (port_id == -1) { | |
a4636960 MC |
3521 | rc = -ENOMEM; |
3522 | goto err_out; | |
3523 | } | |
9b093360 | 3524 | local_port = cpu_to_be16(port_id); |
a4636960 MC |
3525 | } |
3526 | csk->src_port = local_port; | |
3527 | ||
a4636960 MC |
3528 | err_out: |
3529 | dst_release(dst); | |
3530 | return rc; | |
3531 | } | |
3532 | ||
3533 | static void cnic_init_csk_state(struct cnic_sock *csk) | |
3534 | { | |
3535 | csk->state = 0; | |
3536 | clear_bit(SK_F_OFFLD_SCHED, &csk->flags); | |
3537 | clear_bit(SK_F_CLOSING, &csk->flags); | |
3538 | } | |
3539 | ||
3540 | static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr) | |
3541 | { | |
3542 | int err = 0; | |
3543 | ||
3544 | if (!cnic_in_use(csk)) | |
3545 | return -EINVAL; | |
3546 | ||
3547 | if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags)) | |
3548 | return -EINVAL; | |
3549 | ||
3550 | cnic_init_csk_state(csk); | |
3551 | ||
3552 | err = cnic_get_route(csk, saddr); | |
3553 | if (err) | |
3554 | goto err_out; | |
3555 | ||
3556 | err = cnic_resolve_addr(csk, saddr); | |
3557 | if (!err) | |
3558 | return 0; | |
3559 | ||
3560 | err_out: | |
3561 | clear_bit(SK_F_CONNECT_START, &csk->flags); | |
3562 | return err; | |
3563 | } | |
3564 | ||
3565 | static int cnic_cm_abort(struct cnic_sock *csk) | |
3566 | { | |
3567 | struct cnic_local *cp = csk->dev->cnic_priv; | |
7b34a464 | 3568 | u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP; |
a4636960 MC |
3569 | |
3570 | if (!cnic_in_use(csk)) | |
3571 | return -EINVAL; | |
3572 | ||
3573 | if (cnic_abort_prep(csk)) | |
3574 | return cnic_cm_abort_req(csk); | |
3575 | ||
3576 | /* Getting here means that we haven't started connect, or | |
3577 | * connect was not successful. | |
3578 | */ | |
3579 | ||
a4636960 | 3580 | cp->close_conn(csk, opcode); |
7b34a464 MC |
3581 | if (csk->state != opcode) |
3582 | return -EALREADY; | |
a4636960 MC |
3583 | |
3584 | return 0; | |
3585 | } | |
3586 | ||
3587 | static int cnic_cm_close(struct cnic_sock *csk) | |
3588 | { | |
3589 | if (!cnic_in_use(csk)) | |
3590 | return -EINVAL; | |
3591 | ||
3592 | if (cnic_close_prep(csk)) { | |
3593 | csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP; | |
3594 | return cnic_cm_close_req(csk); | |
ed99daa5 MC |
3595 | } else { |
3596 | return -EALREADY; | |
a4636960 MC |
3597 | } |
3598 | return 0; | |
3599 | } | |
3600 | ||
3601 | static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk, | |
3602 | u8 opcode) | |
3603 | { | |
3604 | struct cnic_ulp_ops *ulp_ops; | |
3605 | int ulp_type = csk->ulp_type; | |
3606 | ||
3607 | rcu_read_lock(); | |
3608 | ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]); | |
3609 | if (ulp_ops) { | |
3610 | if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE) | |
3611 | ulp_ops->cm_connect_complete(csk); | |
3612 | else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) | |
3613 | ulp_ops->cm_close_complete(csk); | |
3614 | else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) | |
3615 | ulp_ops->cm_remote_abort(csk); | |
3616 | else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP) | |
3617 | ulp_ops->cm_abort_complete(csk); | |
3618 | else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED) | |
3619 | ulp_ops->cm_remote_close(csk); | |
3620 | } | |
3621 | rcu_read_unlock(); | |
3622 | } | |
3623 | ||
3624 | static int cnic_cm_set_pg(struct cnic_sock *csk) | |
3625 | { | |
3626 | if (cnic_offld_prep(csk)) { | |
3627 | if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) | |
3628 | cnic_cm_update_pg(csk); | |
3629 | else | |
3630 | cnic_cm_offload_pg(csk); | |
3631 | } | |
3632 | return 0; | |
3633 | } | |
3634 | ||
3635 | static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe) | |
3636 | { | |
3637 | struct cnic_local *cp = dev->cnic_priv; | |
3638 | u32 l5_cid = kcqe->pg_host_opaque; | |
3639 | u8 opcode = kcqe->op_code; | |
3640 | struct cnic_sock *csk = &cp->csk_tbl[l5_cid]; | |
3641 | ||
3642 | csk_hold(csk); | |
3643 | if (!cnic_in_use(csk)) | |
3644 | goto done; | |
3645 | ||
3646 | if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) { | |
3647 | clear_bit(SK_F_OFFLD_SCHED, &csk->flags); | |
3648 | goto done; | |
3649 | } | |
a9736c08 EW |
3650 | /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */ |
3651 | if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) { | |
3652 | clear_bit(SK_F_OFFLD_SCHED, &csk->flags); | |
3653 | cnic_cm_upcall(cp, csk, | |
3654 | L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE); | |
3655 | goto done; | |
3656 | } | |
3657 | ||
a4636960 MC |
3658 | csk->pg_cid = kcqe->pg_cid; |
3659 | set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags); | |
3660 | cnic_cm_conn_req(csk); | |
3661 | ||
3662 | done: | |
3663 | csk_put(csk); | |
3664 | } | |
3665 | ||
e1928c86 MC |
3666 | static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe) |
3667 | { | |
3668 | struct cnic_local *cp = dev->cnic_priv; | |
3669 | struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe; | |
3670 | u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE; | |
3671 | struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; | |
3672 | ||
3673 | ctx->timestamp = jiffies; | |
3674 | ctx->wait_cond = 1; | |
3675 | wake_up(&ctx->waitq); | |
3676 | } | |
3677 | ||
a4636960 MC |
3678 | static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe) |
3679 | { | |
3680 | struct cnic_local *cp = dev->cnic_priv; | |
3681 | struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe; | |
3682 | u8 opcode = l4kcqe->op_code; | |
3683 | u32 l5_cid; | |
3684 | struct cnic_sock *csk; | |
3685 | ||
e1928c86 MC |
3686 | if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) { |
3687 | cnic_process_fcoe_term_conn(dev, kcqe); | |
3688 | return; | |
3689 | } | |
a4636960 MC |
3690 | if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG || |
3691 | opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) { | |
3692 | cnic_cm_process_offld_pg(dev, l4kcqe); | |
3693 | return; | |
3694 | } | |
3695 | ||
3696 | l5_cid = l4kcqe->conn_id; | |
3697 | if (opcode & 0x80) | |
3698 | l5_cid = l4kcqe->cid; | |
3699 | if (l5_cid >= MAX_CM_SK_TBL_SZ) | |
3700 | return; | |
3701 | ||
3702 | csk = &cp->csk_tbl[l5_cid]; | |
3703 | csk_hold(csk); | |
3704 | ||
3705 | if (!cnic_in_use(csk)) { | |
3706 | csk_put(csk); | |
3707 | return; | |
3708 | } | |
3709 | ||
3710 | switch (opcode) { | |
a9736c08 EW |
3711 | case L5CM_RAMROD_CMD_ID_TCP_CONNECT: |
3712 | if (l4kcqe->status != 0) { | |
3713 | clear_bit(SK_F_OFFLD_SCHED, &csk->flags); | |
3714 | cnic_cm_upcall(cp, csk, | |
3715 | L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE); | |
3716 | } | |
3717 | break; | |
a4636960 MC |
3718 | case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE: |
3719 | if (l4kcqe->status == 0) | |
3720 | set_bit(SK_F_OFFLD_COMPLETE, &csk->flags); | |
3721 | ||
3722 | smp_mb__before_clear_bit(); | |
3723 | clear_bit(SK_F_OFFLD_SCHED, &csk->flags); | |
3724 | cnic_cm_upcall(cp, csk, opcode); | |
3725 | break; | |
3726 | ||
3727 | case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED: | |
a4636960 MC |
3728 | case L4_KCQE_OPCODE_VALUE_CLOSE_COMP: |
3729 | case L4_KCQE_OPCODE_VALUE_RESET_COMP: | |
71034ba8 MC |
3730 | case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE: |
3731 | case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD: | |
a4636960 MC |
3732 | cp->close_conn(csk, opcode); |
3733 | break; | |
3734 | ||
3735 | case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED: | |
3736 | cnic_cm_upcall(cp, csk, opcode); | |
3737 | break; | |
3738 | } | |
3739 | csk_put(csk); | |
3740 | } | |
3741 | ||
3742 | static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num) | |
3743 | { | |
3744 | struct cnic_dev *dev = data; | |
3745 | int i; | |
3746 | ||
3747 | for (i = 0; i < num; i++) | |
3748 | cnic_cm_process_kcqe(dev, kcqe[i]); | |
3749 | } | |
3750 | ||
3751 | static struct cnic_ulp_ops cm_ulp_ops = { | |
3752 | .indicate_kcqes = cnic_cm_indicate_kcqe, | |
3753 | }; | |
3754 | ||
3755 | static void cnic_cm_free_mem(struct cnic_dev *dev) | |
3756 | { | |
3757 | struct cnic_local *cp = dev->cnic_priv; | |
3758 | ||
3759 | kfree(cp->csk_tbl); | |
3760 | cp->csk_tbl = NULL; | |
3761 | cnic_free_id_tbl(&cp->csk_port_tbl); | |
3762 | } | |
3763 | ||
3764 | static int cnic_cm_alloc_mem(struct cnic_dev *dev) | |
3765 | { | |
3766 | struct cnic_local *cp = dev->cnic_priv; | |
3767 | ||
3768 | cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ, | |
3769 | GFP_KERNEL); | |
3770 | if (!cp->csk_tbl) | |
3771 | return -ENOMEM; | |
3772 | ||
3773 | if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE, | |
3774 | CNIC_LOCAL_PORT_MIN)) { | |
3775 | cnic_cm_free_mem(dev); | |
3776 | return -ENOMEM; | |
3777 | } | |
3778 | return 0; | |
3779 | } | |
3780 | ||
3781 | static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode) | |
3782 | { | |
943189f1 MC |
3783 | if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) { |
3784 | /* Unsolicited RESET_COMP or RESET_RECEIVED */ | |
3785 | opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED; | |
3786 | csk->state = opcode; | |
a4636960 | 3787 | } |
943189f1 MC |
3788 | |
3789 | /* 1. If event opcode matches the expected event in csk->state | |
3790 | * 2. If the expected event is CLOSE_COMP, we accept any event | |
7b34a464 MC |
3791 | * 3. If the expected event is 0, meaning the connection was never |
3792 | * never established, we accept the opcode from cm_abort. | |
66883e90 | 3793 | */ |
7b34a464 MC |
3794 | if (opcode == csk->state || csk->state == 0 || |
3795 | csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) { | |
3796 | if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) { | |
3797 | if (csk->state == 0) | |
3798 | csk->state = opcode; | |
66883e90 | 3799 | return 1; |
7b34a464 | 3800 | } |
66883e90 | 3801 | } |
a4636960 MC |
3802 | return 0; |
3803 | } | |
3804 | ||
3805 | static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode) | |
3806 | { | |
3807 | struct cnic_dev *dev = csk->dev; | |
3808 | struct cnic_local *cp = dev->cnic_priv; | |
3809 | ||
a1e621bf MC |
3810 | if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) { |
3811 | cnic_cm_upcall(cp, csk, opcode); | |
3812 | return; | |
3813 | } | |
3814 | ||
a4636960 | 3815 | clear_bit(SK_F_CONNECT_START, &csk->flags); |
66883e90 | 3816 | cnic_close_conn(csk); |
7b34a464 | 3817 | csk->state = opcode; |
66883e90 | 3818 | cnic_cm_upcall(cp, csk, opcode); |
a4636960 MC |
3819 | } |
3820 | ||
3821 | static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev) | |
3822 | { | |
3823 | } | |
3824 | ||
3825 | static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev) | |
3826 | { | |
3827 | u32 seed; | |
3828 | ||
3829 | get_random_bytes(&seed, 4); | |
3830 | cnic_ctx_wr(dev, 45, 0, seed); | |
3831 | return 0; | |
3832 | } | |
3833 | ||
71034ba8 MC |
3834 | static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode) |
3835 | { | |
3836 | struct cnic_dev *dev = csk->dev; | |
3837 | struct cnic_local *cp = dev->cnic_priv; | |
3838 | struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid]; | |
3839 | union l5cm_specific_data l5_data; | |
3840 | u32 cmd = 0; | |
3841 | int close_complete = 0; | |
3842 | ||
3843 | switch (opcode) { | |
3844 | case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED: | |
3845 | case L4_KCQE_OPCODE_VALUE_CLOSE_COMP: | |
3846 | case L4_KCQE_OPCODE_VALUE_RESET_COMP: | |
7b34a464 MC |
3847 | if (cnic_ready_to_close(csk, opcode)) { |
3848 | if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) | |
3849 | cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE; | |
3850 | else | |
3851 | close_complete = 1; | |
3852 | } | |
71034ba8 MC |
3853 | break; |
3854 | case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE: | |
3855 | cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD; | |
3856 | break; | |
3857 | case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD: | |
3858 | close_complete = 1; | |
3859 | break; | |
3860 | } | |
3861 | if (cmd) { | |
3862 | memset(&l5_data, 0, sizeof(l5_data)); | |
3863 | ||
3864 | cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE, | |
3865 | &l5_data); | |
3866 | } else if (close_complete) { | |
3867 | ctx->timestamp = jiffies; | |
3868 | cnic_close_conn(csk); | |
3869 | cnic_cm_upcall(cp, csk, csk->state); | |
3870 | } | |
3871 | } | |
3872 | ||
3873 | static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev) | |
3874 | { | |
fdf24086 MC |
3875 | struct cnic_local *cp = dev->cnic_priv; |
3876 | int i; | |
3877 | ||
3878 | if (!cp->ctx_tbl) | |
3879 | return; | |
3880 | ||
3881 | if (!netif_running(dev->netdev)) | |
3882 | return; | |
3883 | ||
3884 | for (i = 0; i < cp->max_cid_space; i++) { | |
3885 | struct cnic_context *ctx = &cp->ctx_tbl[i]; | |
3886 | ||
3887 | while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags)) | |
3888 | msleep(10); | |
3889 | ||
3890 | if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) | |
3891 | netdev_warn(dev->netdev, "CID %x not deleted\n", | |
3892 | ctx->cid); | |
3893 | } | |
3894 | ||
3895 | cancel_delayed_work(&cp->delete_task); | |
3896 | flush_workqueue(cnic_wq); | |
3897 | ||
3898 | if (atomic_read(&cp->iscsi_conn) != 0) | |
3899 | netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n", | |
3900 | atomic_read(&cp->iscsi_conn)); | |
71034ba8 MC |
3901 | } |
3902 | ||
3903 | static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev) | |
3904 | { | |
3905 | struct cnic_local *cp = dev->cnic_priv; | |
1420398d | 3906 | u32 pfid = cp->pfid; |
523224a3 | 3907 | u32 port = CNIC_PORT(cp); |
71034ba8 MC |
3908 | |
3909 | cnic_init_bnx2x_mac(dev); | |
3910 | cnic_bnx2x_set_tcp_timestamp(dev, 1); | |
3911 | ||
3912 | CNIC_WR16(dev, BAR_XSTRORM_INTMEM + | |
1420398d | 3913 | XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0); |
71034ba8 MC |
3914 | |
3915 | CNIC_WR(dev, BAR_XSTRORM_INTMEM + | |
523224a3 | 3916 | XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1); |
71034ba8 | 3917 | CNIC_WR(dev, BAR_XSTRORM_INTMEM + |
523224a3 | 3918 | XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port), |
71034ba8 MC |
3919 | DEF_MAX_DA_COUNT); |
3920 | ||
3921 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + | |
1420398d | 3922 | XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL); |
71034ba8 | 3923 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + |
1420398d | 3924 | XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS); |
71034ba8 | 3925 | CNIC_WR8(dev, BAR_XSTRORM_INTMEM + |
1420398d | 3926 | XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2); |
71034ba8 | 3927 | CNIC_WR(dev, BAR_XSTRORM_INTMEM + |
1420398d | 3928 | XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER); |
71034ba8 | 3929 | |
1420398d | 3930 | CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid), |
71034ba8 MC |
3931 | DEF_MAX_CWND); |
3932 | return 0; | |
3933 | } | |
3934 | ||
fdf24086 MC |
3935 | static void cnic_delete_task(struct work_struct *work) |
3936 | { | |
3937 | struct cnic_local *cp; | |
3938 | struct cnic_dev *dev; | |
3939 | u32 i; | |
3940 | int need_resched = 0; | |
3941 | ||
3942 | cp = container_of(work, struct cnic_local, delete_task.work); | |
3943 | dev = cp->dev; | |
3944 | ||
3945 | for (i = 0; i < cp->max_cid_space; i++) { | |
3946 | struct cnic_context *ctx = &cp->ctx_tbl[i]; | |
3947 | ||
3948 | if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) || | |
3949 | !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags)) | |
3950 | continue; | |
3951 | ||
3952 | if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) { | |
3953 | need_resched = 1; | |
3954 | continue; | |
3955 | } | |
3956 | ||
3957 | if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags)) | |
3958 | continue; | |
3959 | ||
3960 | cnic_bnx2x_destroy_ramrod(dev, i); | |
3961 | ||
3962 | cnic_free_bnx2x_conn_resc(dev, i); | |
3963 | if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) | |
3964 | atomic_dec(&cp->iscsi_conn); | |
3965 | ||
3966 | clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags); | |
3967 | } | |
3968 | ||
3969 | if (need_resched) | |
3970 | queue_delayed_work(cnic_wq, &cp->delete_task, | |
3971 | msecs_to_jiffies(10)); | |
3972 | ||
3973 | } | |
3974 | ||
a4636960 MC |
3975 | static int cnic_cm_open(struct cnic_dev *dev) |
3976 | { | |
3977 | struct cnic_local *cp = dev->cnic_priv; | |
3978 | int err; | |
3979 | ||
3980 | err = cnic_cm_alloc_mem(dev); | |
3981 | if (err) | |
3982 | return err; | |
3983 | ||
3984 | err = cp->start_cm(dev); | |
3985 | ||
3986 | if (err) | |
3987 | goto err_out; | |
3988 | ||
fdf24086 MC |
3989 | INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task); |
3990 | ||
a4636960 MC |
3991 | dev->cm_create = cnic_cm_create; |
3992 | dev->cm_destroy = cnic_cm_destroy; | |
3993 | dev->cm_connect = cnic_cm_connect; | |
3994 | dev->cm_abort = cnic_cm_abort; | |
3995 | dev->cm_close = cnic_cm_close; | |
3996 | dev->cm_select_dev = cnic_cm_select_dev; | |
3997 | ||
3998 | cp->ulp_handle[CNIC_ULP_L4] = dev; | |
3999 | rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops); | |
4000 | return 0; | |
4001 | ||
4002 | err_out: | |
4003 | cnic_cm_free_mem(dev); | |
4004 | return err; | |
4005 | } | |
4006 | ||
4007 | static int cnic_cm_shutdown(struct cnic_dev *dev) | |
4008 | { | |
4009 | struct cnic_local *cp = dev->cnic_priv; | |
4010 | int i; | |
4011 | ||
4012 | cp->stop_cm(dev); | |
4013 | ||
4014 | if (!cp->csk_tbl) | |
4015 | return 0; | |
4016 | ||
4017 | for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) { | |
4018 | struct cnic_sock *csk = &cp->csk_tbl[i]; | |
4019 | ||
4020 | clear_bit(SK_F_INUSE, &csk->flags); | |
4021 | cnic_cm_cleanup(csk); | |
4022 | } | |
4023 | cnic_cm_free_mem(dev); | |
4024 | ||
4025 | return 0; | |
4026 | } | |
4027 | ||
4028 | static void cnic_init_context(struct cnic_dev *dev, u32 cid) | |
4029 | { | |
a4636960 MC |
4030 | u32 cid_addr; |
4031 | int i; | |
4032 | ||
a4636960 MC |
4033 | cid_addr = GET_CID_ADDR(cid); |
4034 | ||
4035 | for (i = 0; i < CTX_SIZE; i += 4) | |
4036 | cnic_ctx_wr(dev, cid_addr, i, 0); | |
4037 | } | |
4038 | ||
4039 | static int cnic_setup_5709_context(struct cnic_dev *dev, int valid) | |
4040 | { | |
4041 | struct cnic_local *cp = dev->cnic_priv; | |
4042 | int ret = 0, i; | |
4043 | u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0; | |
4044 | ||
4045 | if (CHIP_NUM(cp) != CHIP_NUM_5709) | |
4046 | return 0; | |
4047 | ||
4048 | for (i = 0; i < cp->ctx_blks; i++) { | |
4049 | int j; | |
4050 | u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk; | |
4051 | u32 val; | |
4052 | ||
4053 | memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE); | |
4054 | ||
4055 | CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0, | |
4056 | (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit); | |
4057 | CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1, | |
4058 | (u64) cp->ctx_arr[i].mapping >> 32); | |
4059 | CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx | | |
4060 | BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); | |
4061 | for (j = 0; j < 10; j++) { | |
4062 | ||
4063 | val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL); | |
4064 | if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) | |
4065 | break; | |
4066 | udelay(5); | |
4067 | } | |
4068 | if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { | |
4069 | ret = -EBUSY; | |
4070 | break; | |
4071 | } | |
4072 | } | |
4073 | return ret; | |
4074 | } | |
4075 | ||
4076 | static void cnic_free_irq(struct cnic_dev *dev) | |
4077 | { | |
4078 | struct cnic_local *cp = dev->cnic_priv; | |
4079 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
4080 | ||
4081 | if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { | |
4082 | cp->disable_int_sync(dev); | |
6e0dc643 | 4083 | tasklet_kill(&cp->cnic_irq_task); |
a4636960 MC |
4084 | free_irq(ethdev->irq_arr[0].vector, dev); |
4085 | } | |
4086 | } | |
4087 | ||
6e0dc643 MC |
4088 | static int cnic_request_irq(struct cnic_dev *dev) |
4089 | { | |
4090 | struct cnic_local *cp = dev->cnic_priv; | |
4091 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
4092 | int err; | |
4093 | ||
4094 | err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev); | |
4095 | if (err) | |
4096 | tasklet_disable(&cp->cnic_irq_task); | |
4097 | ||
4098 | return err; | |
4099 | } | |
4100 | ||
a4636960 MC |
4101 | static int cnic_init_bnx2_irq(struct cnic_dev *dev) |
4102 | { | |
4103 | struct cnic_local *cp = dev->cnic_priv; | |
4104 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
4105 | ||
4106 | if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { | |
4107 | int err, i = 0; | |
4108 | int sblk_num = cp->status_blk_num; | |
4109 | u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) + | |
4110 | BNX2_HC_SB_CONFIG_1; | |
4111 | ||
4112 | CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT); | |
4113 | ||
4114 | CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8); | |
4115 | CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220); | |
4116 | CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220); | |
4117 | ||
a4dde3ab | 4118 | cp->last_status_idx = cp->status_blk.bnx2->status_idx; |
164165da | 4119 | tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix, |
a4636960 | 4120 | (unsigned long) dev); |
6e0dc643 MC |
4121 | err = cnic_request_irq(dev); |
4122 | if (err) | |
a4636960 | 4123 | return err; |
6e0dc643 | 4124 | |
a4dde3ab | 4125 | while (cp->status_blk.bnx2->status_completion_producer_index && |
a4636960 MC |
4126 | i < 10) { |
4127 | CNIC_WR(dev, BNX2_HC_COALESCE_NOW, | |
4128 | 1 << (11 + sblk_num)); | |
4129 | udelay(10); | |
4130 | i++; | |
4131 | barrier(); | |
4132 | } | |
a4dde3ab | 4133 | if (cp->status_blk.bnx2->status_completion_producer_index) { |
a4636960 MC |
4134 | cnic_free_irq(dev); |
4135 | goto failed; | |
4136 | } | |
4137 | ||
4138 | } else { | |
a4dde3ab | 4139 | struct status_block *sblk = cp->status_blk.gen; |
a4636960 MC |
4140 | u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND); |
4141 | int i = 0; | |
4142 | ||
4143 | while (sblk->status_completion_producer_index && i < 10) { | |
4144 | CNIC_WR(dev, BNX2_HC_COMMAND, | |
4145 | hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
4146 | udelay(10); | |
4147 | i++; | |
4148 | barrier(); | |
4149 | } | |
4150 | if (sblk->status_completion_producer_index) | |
4151 | goto failed; | |
4152 | ||
4153 | } | |
4154 | return 0; | |
4155 | ||
4156 | failed: | |
ddf79b20 | 4157 | netdev_err(dev->netdev, "KCQ index not resetting to 0\n"); |
a4636960 MC |
4158 | return -EBUSY; |
4159 | } | |
4160 | ||
4161 | static void cnic_enable_bnx2_int(struct cnic_dev *dev) | |
4162 | { | |
4163 | struct cnic_local *cp = dev->cnic_priv; | |
4164 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
4165 | ||
4166 | if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)) | |
4167 | return; | |
4168 | ||
4169 | CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num | | |
4170 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx); | |
4171 | } | |
4172 | ||
4173 | static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev) | |
4174 | { | |
4175 | struct cnic_local *cp = dev->cnic_priv; | |
4176 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
4177 | ||
4178 | if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)) | |
4179 | return; | |
4180 | ||
4181 | CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num | | |
4182 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
4183 | CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD); | |
4184 | synchronize_irq(ethdev->irq_arr[0].vector); | |
4185 | } | |
4186 | ||
4187 | static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev) | |
4188 | { | |
4189 | struct cnic_local *cp = dev->cnic_priv; | |
4190 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
cd801536 | 4191 | struct cnic_uio_dev *udev = cp->udev; |
a4636960 MC |
4192 | u32 cid_addr, tx_cid, sb_id; |
4193 | u32 val, offset0, offset1, offset2, offset3; | |
4194 | int i; | |
4195 | struct tx_bd *txbd; | |
cd801536 | 4196 | dma_addr_t buf_map, ring_map = udev->l2_ring_map; |
a4dde3ab | 4197 | struct status_block *s_blk = cp->status_blk.gen; |
a4636960 MC |
4198 | |
4199 | sb_id = cp->status_blk_num; | |
4200 | tx_cid = 20; | |
a4636960 MC |
4201 | cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2; |
4202 | if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { | |
a4dde3ab | 4203 | struct status_block_msix *sblk = cp->status_blk.bnx2; |
a4636960 MC |
4204 | |
4205 | tx_cid = TX_TSS_CID + sb_id - 1; | |
a4636960 MC |
4206 | CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) | |
4207 | (TX_TSS_CID << 7)); | |
4208 | cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index; | |
4209 | } | |
4210 | cp->tx_cons = *cp->tx_cons_ptr; | |
4211 | ||
4212 | cid_addr = GET_CID_ADDR(tx_cid); | |
4213 | if (CHIP_NUM(cp) == CHIP_NUM_5709) { | |
4214 | u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40; | |
4215 | ||
4216 | for (i = 0; i < PHY_CTX_SIZE; i += 4) | |
4217 | cnic_ctx_wr(dev, cid_addr2, i, 0); | |
4218 | ||
4219 | offset0 = BNX2_L2CTX_TYPE_XI; | |
4220 | offset1 = BNX2_L2CTX_CMD_TYPE_XI; | |
4221 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; | |
4222 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; | |
4223 | } else { | |
b58ffb41 MC |
4224 | cnic_init_context(dev, tx_cid); |
4225 | cnic_init_context(dev, tx_cid + 1); | |
4226 | ||
a4636960 MC |
4227 | offset0 = BNX2_L2CTX_TYPE; |
4228 | offset1 = BNX2_L2CTX_CMD_TYPE; | |
4229 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; | |
4230 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; | |
4231 | } | |
4232 | val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; | |
4233 | cnic_ctx_wr(dev, cid_addr, offset0, val); | |
4234 | ||
4235 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); | |
4236 | cnic_ctx_wr(dev, cid_addr, offset1, val); | |
4237 | ||
cd801536 | 4238 | txbd = (struct tx_bd *) udev->l2_ring; |
a4636960 | 4239 | |
cd801536 | 4240 | buf_map = udev->l2_buf_map; |
a4636960 MC |
4241 | for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) { |
4242 | txbd->tx_bd_haddr_hi = (u64) buf_map >> 32; | |
4243 | txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff; | |
4244 | } | |
cd801536 | 4245 | val = (u64) ring_map >> 32; |
a4636960 MC |
4246 | cnic_ctx_wr(dev, cid_addr, offset2, val); |
4247 | txbd->tx_bd_haddr_hi = val; | |
4248 | ||
cd801536 | 4249 | val = (u64) ring_map & 0xffffffff; |
a4636960 MC |
4250 | cnic_ctx_wr(dev, cid_addr, offset3, val); |
4251 | txbd->tx_bd_haddr_lo = val; | |
4252 | } | |
4253 | ||
4254 | static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev) | |
4255 | { | |
4256 | struct cnic_local *cp = dev->cnic_priv; | |
4257 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
cd801536 | 4258 | struct cnic_uio_dev *udev = cp->udev; |
a4636960 MC |
4259 | u32 cid_addr, sb_id, val, coal_reg, coal_val; |
4260 | int i; | |
4261 | struct rx_bd *rxbd; | |
a4dde3ab | 4262 | struct status_block *s_blk = cp->status_blk.gen; |
cd801536 | 4263 | dma_addr_t ring_map = udev->l2_ring_map; |
a4636960 MC |
4264 | |
4265 | sb_id = cp->status_blk_num; | |
4266 | cnic_init_context(dev, 2); | |
4267 | cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2; | |
4268 | coal_reg = BNX2_HC_COMMAND; | |
4269 | coal_val = CNIC_RD(dev, coal_reg); | |
4270 | if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { | |
a4dde3ab | 4271 | struct status_block_msix *sblk = cp->status_blk.bnx2; |
a4636960 MC |
4272 | |
4273 | cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index; | |
4274 | coal_reg = BNX2_HC_COALESCE_NOW; | |
4275 | coal_val = 1 << (11 + sb_id); | |
4276 | } | |
4277 | i = 0; | |
4278 | while (!(*cp->rx_cons_ptr != 0) && i < 10) { | |
4279 | CNIC_WR(dev, coal_reg, coal_val); | |
4280 | udelay(10); | |
4281 | i++; | |
4282 | barrier(); | |
4283 | } | |
4284 | cp->rx_cons = *cp->rx_cons_ptr; | |
4285 | ||
4286 | cid_addr = GET_CID_ADDR(2); | |
4287 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | | |
4288 | BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); | |
4289 | cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val); | |
4290 | ||
4291 | if (sb_id == 0) | |
d0549382 | 4292 | val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT; |
a4636960 | 4293 | else |
d0549382 | 4294 | val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id); |
a4636960 MC |
4295 | cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val); |
4296 | ||
cd801536 | 4297 | rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE); |
a4636960 MC |
4298 | for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) { |
4299 | dma_addr_t buf_map; | |
4300 | int n = (i % cp->l2_rx_ring_size) + 1; | |
4301 | ||
cd801536 | 4302 | buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size); |
a4636960 MC |
4303 | rxbd->rx_bd_len = cp->l2_single_buf_size; |
4304 | rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; | |
4305 | rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32; | |
4306 | rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff; | |
4307 | } | |
cd801536 | 4308 | val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32; |
a4636960 MC |
4309 | cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); |
4310 | rxbd->rx_bd_haddr_hi = val; | |
4311 | ||
cd801536 | 4312 | val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff; |
a4636960 MC |
4313 | cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); |
4314 | rxbd->rx_bd_haddr_lo = val; | |
4315 | ||
4316 | val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD); | |
4317 | cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2)); | |
4318 | } | |
4319 | ||
4320 | static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev) | |
4321 | { | |
4322 | struct kwqe *wqes[1], l2kwqe; | |
4323 | ||
4324 | memset(&l2kwqe, 0, sizeof(l2kwqe)); | |
4325 | wqes[0] = &l2kwqe; | |
e1928c86 | 4326 | l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) | |
a4636960 MC |
4327 | (L2_KWQE_OPCODE_VALUE_FLUSH << |
4328 | KWQE_OPCODE_SHIFT) | 2; | |
4329 | dev->submit_kwqes(dev, wqes, 1); | |
4330 | } | |
4331 | ||
4332 | static void cnic_set_bnx2_mac(struct cnic_dev *dev) | |
4333 | { | |
4334 | struct cnic_local *cp = dev->cnic_priv; | |
4335 | u32 val; | |
4336 | ||
4337 | val = cp->func << 2; | |
4338 | ||
4339 | cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val); | |
4340 | ||
4341 | val = cnic_reg_rd_ind(dev, cp->shmem_base + | |
4342 | BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER); | |
4343 | dev->mac_addr[0] = (u8) (val >> 8); | |
4344 | dev->mac_addr[1] = (u8) val; | |
4345 | ||
4346 | CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val); | |
4347 | ||
4348 | val = cnic_reg_rd_ind(dev, cp->shmem_base + | |
4349 | BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER); | |
4350 | dev->mac_addr[2] = (u8) (val >> 24); | |
4351 | dev->mac_addr[3] = (u8) (val >> 16); | |
4352 | dev->mac_addr[4] = (u8) (val >> 8); | |
4353 | dev->mac_addr[5] = (u8) val; | |
4354 | ||
4355 | CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val); | |
4356 | ||
4357 | val = 4 | BNX2_RPM_SORT_USER2_BC_EN; | |
4358 | if (CHIP_NUM(cp) != CHIP_NUM_5709) | |
4359 | val |= BNX2_RPM_SORT_USER2_PROM_VLAN; | |
4360 | ||
4361 | CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0); | |
4362 | CNIC_WR(dev, BNX2_RPM_SORT_USER2, val); | |
4363 | CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA); | |
4364 | } | |
4365 | ||
4366 | static int cnic_start_bnx2_hw(struct cnic_dev *dev) | |
4367 | { | |
4368 | struct cnic_local *cp = dev->cnic_priv; | |
4369 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
a4dde3ab | 4370 | struct status_block *sblk = cp->status_blk.gen; |
e6c28894 | 4371 | u32 val, kcq_cid_addr, kwq_cid_addr; |
a4636960 MC |
4372 | int err; |
4373 | ||
4374 | cnic_set_bnx2_mac(dev); | |
4375 | ||
4376 | val = CNIC_RD(dev, BNX2_MQ_CONFIG); | |
4377 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; | |
4378 | if (BCM_PAGE_BITS > 12) | |
4379 | val |= (12 - 8) << 4; | |
4380 | else | |
4381 | val |= (BCM_PAGE_BITS - 8) << 4; | |
4382 | ||
4383 | CNIC_WR(dev, BNX2_MQ_CONFIG, val); | |
4384 | ||
4385 | CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8); | |
4386 | CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220); | |
4387 | CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220); | |
4388 | ||
4389 | err = cnic_setup_5709_context(dev, 1); | |
4390 | if (err) | |
4391 | return err; | |
4392 | ||
4393 | cnic_init_context(dev, KWQ_CID); | |
4394 | cnic_init_context(dev, KCQ_CID); | |
4395 | ||
e6c28894 | 4396 | kwq_cid_addr = GET_CID_ADDR(KWQ_CID); |
a4636960 MC |
4397 | cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX; |
4398 | ||
4399 | cp->max_kwq_idx = MAX_KWQ_IDX; | |
4400 | cp->kwq_prod_idx = 0; | |
4401 | cp->kwq_con_idx = 0; | |
1f1332a3 | 4402 | set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags); |
a4636960 MC |
4403 | |
4404 | if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708) | |
4405 | cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15; | |
4406 | else | |
4407 | cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index; | |
4408 | ||
4409 | /* Initialize the kernel work queue context. */ | |
4410 | val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | | |
4411 | (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; | |
e6c28894 | 4412 | cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val); |
a4636960 MC |
4413 | |
4414 | val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16; | |
e6c28894 | 4415 | cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); |
a4636960 MC |
4416 | |
4417 | val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT; | |
e6c28894 | 4418 | cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); |
a4636960 MC |
4419 | |
4420 | val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32); | |
e6c28894 | 4421 | cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val); |
a4636960 MC |
4422 | |
4423 | val = (u32) cp->kwq_info.pgtbl_map; | |
e6c28894 MC |
4424 | cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val); |
4425 | ||
4426 | kcq_cid_addr = GET_CID_ADDR(KCQ_CID); | |
4427 | cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX; | |
a4636960 | 4428 | |
e6c28894 MC |
4429 | cp->kcq1.sw_prod_idx = 0; |
4430 | cp->kcq1.hw_prod_idx_ptr = | |
4431 | (u16 *) &sblk->status_completion_producer_index; | |
a4636960 | 4432 | |
e6c28894 | 4433 | cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx; |
a4636960 MC |
4434 | |
4435 | /* Initialize the kernel complete queue context. */ | |
4436 | val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | | |
4437 | (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; | |
e6c28894 | 4438 | cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val); |
a4636960 MC |
4439 | |
4440 | val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16; | |
e6c28894 | 4441 | cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); |
a4636960 MC |
4442 | |
4443 | val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT; | |
e6c28894 | 4444 | cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); |
a4636960 | 4445 | |
e6c28894 MC |
4446 | val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32); |
4447 | cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val); | |
a4636960 | 4448 | |
e6c28894 MC |
4449 | val = (u32) cp->kcq1.dma.pgtbl_map; |
4450 | cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val); | |
a4636960 MC |
4451 | |
4452 | cp->int_num = 0; | |
4453 | if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) { | |
e6c28894 | 4454 | struct status_block_msix *msblk = cp->status_blk.bnx2; |
a4636960 | 4455 | u32 sb_id = cp->status_blk_num; |
d0549382 | 4456 | u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id); |
a4636960 | 4457 | |
e6c28894 MC |
4458 | cp->kcq1.hw_prod_idx_ptr = |
4459 | (u16 *) &msblk->status_completion_producer_index; | |
4460 | cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx; | |
b177a5d5 | 4461 | cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index; |
a4636960 | 4462 | cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT; |
e6c28894 MC |
4463 | cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb); |
4464 | cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb); | |
a4636960 MC |
4465 | } |
4466 | ||
4467 | /* Enable Commnad Scheduler notification when we write to the | |
4468 | * host producer index of the kernel contexts. */ | |
4469 | CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2); | |
4470 | ||
4471 | /* Enable Command Scheduler notification when we write to either | |
4472 | * the Send Queue or Receive Queue producer indexes of the kernel | |
4473 | * bypass contexts. */ | |
4474 | CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7); | |
4475 | CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7); | |
4476 | ||
4477 | /* Notify COM when the driver post an application buffer. */ | |
4478 | CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000); | |
4479 | ||
4480 | /* Set the CP and COM doorbells. These two processors polls the | |
4481 | * doorbell for a non zero value before running. This must be done | |
4482 | * after setting up the kernel queue contexts. */ | |
4483 | cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1); | |
4484 | cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1); | |
4485 | ||
4486 | cnic_init_bnx2_tx_ring(dev); | |
4487 | cnic_init_bnx2_rx_ring(dev); | |
4488 | ||
4489 | err = cnic_init_bnx2_irq(dev); | |
4490 | if (err) { | |
ddf79b20 | 4491 | netdev_err(dev->netdev, "cnic_init_irq failed\n"); |
a4636960 MC |
4492 | cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0); |
4493 | cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0); | |
4494 | return err; | |
4495 | } | |
4496 | ||
4497 | return 0; | |
4498 | } | |
4499 | ||
71034ba8 MC |
4500 | static void cnic_setup_bnx2x_context(struct cnic_dev *dev) |
4501 | { | |
4502 | struct cnic_local *cp = dev->cnic_priv; | |
4503 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
4504 | u32 start_offset = ethdev->ctx_tbl_offset; | |
4505 | int i; | |
4506 | ||
4507 | for (i = 0; i < cp->ctx_blks; i++) { | |
4508 | struct cnic_ctx *ctx = &cp->ctx_arr[i]; | |
4509 | dma_addr_t map = ctx->mapping; | |
4510 | ||
4511 | if (cp->ctx_align) { | |
4512 | unsigned long mask = cp->ctx_align - 1; | |
4513 | ||
4514 | map = (map + mask) & ~mask; | |
4515 | } | |
4516 | ||
4517 | cnic_ctx_tbl_wr(dev, start_offset + i, map); | |
4518 | } | |
4519 | } | |
4520 | ||
4521 | static int cnic_init_bnx2x_irq(struct cnic_dev *dev) | |
4522 | { | |
4523 | struct cnic_local *cp = dev->cnic_priv; | |
4524 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
4525 | int err = 0; | |
4526 | ||
164165da | 4527 | tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh, |
71034ba8 | 4528 | (unsigned long) dev); |
6e0dc643 MC |
4529 | if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) |
4530 | err = cnic_request_irq(dev); | |
4531 | ||
71034ba8 MC |
4532 | return err; |
4533 | } | |
4534 | ||
523224a3 DK |
4535 | static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev, |
4536 | u16 sb_id, u8 sb_index, | |
4537 | u8 disable) | |
4538 | { | |
4539 | ||
4540 | u32 addr = BAR_CSTRORM_INTMEM + | |
4541 | CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) + | |
4542 | offsetof(struct hc_status_block_data_e1x, index_data) + | |
4543 | sizeof(struct hc_index_data)*sb_index + | |
4544 | offsetof(struct hc_index_data, flags); | |
4545 | u16 flags = CNIC_RD16(dev, addr); | |
4546 | /* clear and set */ | |
4547 | flags &= ~HC_INDEX_DATA_HC_ENABLED; | |
4548 | flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) & | |
4549 | HC_INDEX_DATA_HC_ENABLED); | |
4550 | CNIC_WR16(dev, addr, flags); | |
4551 | } | |
4552 | ||
71034ba8 MC |
4553 | static void cnic_enable_bnx2x_int(struct cnic_dev *dev) |
4554 | { | |
4555 | struct cnic_local *cp = dev->cnic_priv; | |
4556 | u8 sb_id = cp->status_blk_num; | |
71034ba8 MC |
4557 | |
4558 | CNIC_WR8(dev, BAR_CSTRORM_INTMEM + | |
523224a3 DK |
4559 | CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) + |
4560 | offsetof(struct hc_status_block_data_e1x, index_data) + | |
4561 | sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS + | |
4562 | offsetof(struct hc_index_data, timeout), 64 / 12); | |
4563 | cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0); | |
71034ba8 MC |
4564 | } |
4565 | ||
4566 | static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev) | |
4567 | { | |
4568 | } | |
4569 | ||
523224a3 DK |
4570 | static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev, |
4571 | struct client_init_ramrod_data *data) | |
71034ba8 MC |
4572 | { |
4573 | struct cnic_local *cp = dev->cnic_priv; | |
cd801536 MC |
4574 | struct cnic_uio_dev *udev = cp->udev; |
4575 | union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring; | |
4576 | dma_addr_t buf_map, ring_map = udev->l2_ring_map; | |
523224a3 | 4577 | struct host_sp_status_block *sb = cp->bnx2x_def_status_blk; |
71034ba8 MC |
4578 | int port = CNIC_PORT(cp); |
4579 | int i; | |
5159fdc1 | 4580 | u32 cli = cp->ethdev->iscsi_l2_client_id; |
71034ba8 MC |
4581 | u32 val; |
4582 | ||
4583 | memset(txbd, 0, BCM_PAGE_SIZE); | |
4584 | ||
cd801536 | 4585 | buf_map = udev->l2_buf_map; |
71034ba8 MC |
4586 | for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) { |
4587 | struct eth_tx_start_bd *start_bd = &txbd->start_bd; | |
4588 | struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd); | |
4589 | ||
4590 | start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32); | |
4591 | start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff); | |
4592 | reg_bd->addr_hi = start_bd->addr_hi; | |
4593 | reg_bd->addr_lo = start_bd->addr_lo + 0x10; | |
4594 | start_bd->nbytes = cpu_to_le16(0x10); | |
4595 | start_bd->nbd = cpu_to_le16(3); | |
4596 | start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; | |
4597 | start_bd->general_data = (UNICAST_ADDRESS << | |
4598 | ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT); | |
4599 | start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT); | |
4600 | ||
4601 | } | |
71034ba8 | 4602 | |
523224a3 | 4603 | val = (u64) ring_map >> 32; |
71034ba8 MC |
4604 | txbd->next_bd.addr_hi = cpu_to_le32(val); |
4605 | ||
523224a3 | 4606 | data->tx.tx_bd_page_base.hi = cpu_to_le32(val); |
71034ba8 | 4607 | |
523224a3 | 4608 | val = (u64) ring_map & 0xffffffff; |
71034ba8 MC |
4609 | txbd->next_bd.addr_lo = cpu_to_le32(val); |
4610 | ||
523224a3 | 4611 | data->tx.tx_bd_page_base.lo = cpu_to_le32(val); |
71034ba8 | 4612 | |
523224a3 DK |
4613 | /* Other ramrod params */ |
4614 | data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS; | |
4615 | data->tx.tx_status_block_id = BNX2X_DEF_SB_ID; | |
71034ba8 MC |
4616 | |
4617 | /* reset xstorm per client statistics */ | |
523224a3 | 4618 | if (cli < MAX_STAT_COUNTER_ID) { |
6b2a541d DK |
4619 | val = BAR_XSTRORM_INTMEM + |
4620 | XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli); | |
4621 | for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) | |
4622 | CNIC_WR(dev, val + i * 4, 0); | |
4623 | } | |
71034ba8 MC |
4624 | |
4625 | cp->tx_cons_ptr = | |
523224a3 | 4626 | &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS]; |
71034ba8 MC |
4627 | } |
4628 | ||
523224a3 DK |
4629 | static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev, |
4630 | struct client_init_ramrod_data *data) | |
71034ba8 MC |
4631 | { |
4632 | struct cnic_local *cp = dev->cnic_priv; | |
cd801536 MC |
4633 | struct cnic_uio_dev *udev = cp->udev; |
4634 | struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring + | |
71034ba8 MC |
4635 | BCM_PAGE_SIZE); |
4636 | struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *) | |
cd801536 | 4637 | (udev->l2_ring + (2 * BCM_PAGE_SIZE)); |
523224a3 | 4638 | struct host_sp_status_block *sb = cp->bnx2x_def_status_blk; |
71034ba8 MC |
4639 | int i; |
4640 | int port = CNIC_PORT(cp); | |
5159fdc1 | 4641 | u32 cli = cp->ethdev->iscsi_l2_client_id; |
523224a3 | 4642 | int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli); |
71034ba8 | 4643 | u32 val; |
cd801536 | 4644 | dma_addr_t ring_map = udev->l2_ring_map; |
523224a3 DK |
4645 | |
4646 | /* General data */ | |
4647 | data->general.client_id = cli; | |
4648 | data->general.statistics_en_flg = 1; | |
4649 | data->general.statistics_counter_id = cli; | |
4650 | data->general.activate_flg = 1; | |
4651 | data->general.sp_client_id = cli; | |
71034ba8 MC |
4652 | |
4653 | for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) { | |
4654 | dma_addr_t buf_map; | |
4655 | int n = (i % cp->l2_rx_ring_size) + 1; | |
4656 | ||
cd801536 | 4657 | buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size); |
71034ba8 MC |
4658 | rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32); |
4659 | rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff); | |
4660 | } | |
71034ba8 | 4661 | |
523224a3 | 4662 | val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32; |
71034ba8 | 4663 | rxbd->addr_hi = cpu_to_le32(val); |
523224a3 | 4664 | data->rx.bd_page_base.hi = cpu_to_le32(val); |
71034ba8 | 4665 | |
523224a3 | 4666 | val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff; |
71034ba8 | 4667 | rxbd->addr_lo = cpu_to_le32(val); |
523224a3 | 4668 | data->rx.bd_page_base.lo = cpu_to_le32(val); |
71034ba8 MC |
4669 | |
4670 | rxcqe += BNX2X_MAX_RCQ_DESC_CNT; | |
523224a3 | 4671 | val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32; |
71034ba8 | 4672 | rxcqe->addr_hi = cpu_to_le32(val); |
523224a3 | 4673 | data->rx.cqe_page_base.hi = cpu_to_le32(val); |
71034ba8 | 4674 | |
523224a3 | 4675 | val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff; |
71034ba8 | 4676 | rxcqe->addr_lo = cpu_to_le32(val); |
523224a3 | 4677 | data->rx.cqe_page_base.lo = cpu_to_le32(val); |
71034ba8 | 4678 | |
523224a3 DK |
4679 | /* Other ramrod params */ |
4680 | data->rx.client_qzone_id = cl_qzone_id; | |
4681 | data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS; | |
4682 | data->rx.status_block_id = BNX2X_DEF_SB_ID; | |
71034ba8 | 4683 | |
523224a3 DK |
4684 | data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT; |
4685 | data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size); | |
71034ba8 | 4686 | |
523224a3 DK |
4687 | data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14); |
4688 | data->rx.outer_vlan_removal_enable_flg = 1; | |
6b2a541d | 4689 | |
523224a3 DK |
4690 | /* reset tstorm and ustorm per client statistics */ |
4691 | if (cli < MAX_STAT_COUNTER_ID) { | |
6b2a541d DK |
4692 | val = BAR_TSTRORM_INTMEM + |
4693 | TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli); | |
4694 | for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) | |
4695 | CNIC_WR(dev, val + i * 4, 0); | |
71034ba8 | 4696 | |
6b2a541d DK |
4697 | val = BAR_USTRORM_INTMEM + |
4698 | USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli); | |
4699 | for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++) | |
4700 | CNIC_WR(dev, val + i * 4, 0); | |
4701 | } | |
71034ba8 MC |
4702 | |
4703 | cp->rx_cons_ptr = | |
523224a3 | 4704 | &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS]; |
5159fdc1 | 4705 | cp->rx_cons = *cp->rx_cons_ptr; |
71034ba8 MC |
4706 | } |
4707 | ||
4aacb7af MC |
4708 | static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr, |
4709 | u32 lower_addr) | |
4710 | { | |
4711 | u32 val; | |
4712 | u8 mac[6]; | |
4713 | ||
4714 | val = CNIC_RD(dev, upper_addr); | |
4715 | ||
4716 | mac[0] = (u8) (val >> 8); | |
4717 | mac[1] = (u8) val; | |
4718 | ||
4719 | val = CNIC_RD(dev, lower_addr); | |
4720 | ||
4721 | mac[2] = (u8) (val >> 24); | |
4722 | mac[3] = (u8) (val >> 16); | |
4723 | mac[4] = (u8) (val >> 8); | |
4724 | mac[5] = (u8) val; | |
4725 | ||
4726 | if (is_valid_ether_addr(mac)) { | |
4727 | memcpy(dev->mac_addr, mac, 6); | |
4728 | return 0; | |
4729 | } else { | |
4730 | return -EINVAL; | |
4731 | } | |
4732 | } | |
4733 | ||
71034ba8 MC |
4734 | static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev) |
4735 | { | |
4736 | struct cnic_local *cp = dev->cnic_priv; | |
4aacb7af | 4737 | u32 base, base2, addr, addr1, val; |
71034ba8 MC |
4738 | int port = CNIC_PORT(cp); |
4739 | ||
4740 | dev->max_iscsi_conn = 0; | |
4741 | base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR); | |
523224a3 | 4742 | if (base == 0) |
71034ba8 MC |
4743 | return; |
4744 | ||
ee87a82a MC |
4745 | base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 : |
4746 | MISC_REG_GENERIC_CR_0)); | |
dd2e4dbc | 4747 | addr = BNX2X_SHMEM_ADDR(base, |
71034ba8 MC |
4748 | dev_info.port_hw_config[port].iscsi_mac_upper); |
4749 | ||
4aacb7af | 4750 | addr1 = BNX2X_SHMEM_ADDR(base, |
71034ba8 MC |
4751 | dev_info.port_hw_config[port].iscsi_mac_lower); |
4752 | ||
4aacb7af | 4753 | cnic_read_bnx2x_iscsi_mac(dev, addr, addr1); |
71034ba8 MC |
4754 | |
4755 | addr = BNX2X_SHMEM_ADDR(base, validity_map[port]); | |
4756 | val = CNIC_RD(dev, addr); | |
4757 | ||
4758 | if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) { | |
4759 | u16 val16; | |
4760 | ||
4761 | addr = BNX2X_SHMEM_ADDR(base, | |
4762 | drv_lic_key[port].max_iscsi_init_conn); | |
4763 | val16 = CNIC_RD16(dev, addr); | |
4764 | ||
4765 | if (val16) | |
4766 | val16 ^= 0x1e1e; | |
4767 | dev->max_iscsi_conn = val16; | |
4768 | } | |
e1928c86 MC |
4769 | |
4770 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) | |
4771 | dev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS; | |
4772 | ||
ee87a82a | 4773 | if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) { |
71034ba8 | 4774 | int func = CNIC_FUNC(cp); |
523224a3 DK |
4775 | u32 mf_cfg_addr; |
4776 | ||
ee87a82a MC |
4777 | if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr)) |
4778 | mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2, | |
4779 | mf_cfg_addr)); | |
4780 | else | |
4781 | mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET; | |
523224a3 | 4782 | |
4aacb7af MC |
4783 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { |
4784 | /* Must determine if the MF is SD vs SI mode */ | |
4785 | addr = BNX2X_SHMEM_ADDR(base, | |
4786 | dev_info.shared_feature_config.config); | |
4787 | val = CNIC_RD(dev, addr); | |
4788 | if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) == | |
4789 | SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) { | |
4790 | int rc; | |
4791 | ||
4792 | /* MULTI_FUNCTION_SI mode */ | |
4793 | addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr, | |
4794 | func_ext_config[func].func_cfg); | |
4795 | val = CNIC_RD(dev, addr); | |
4796 | if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)) | |
4797 | dev->max_iscsi_conn = 0; | |
4798 | ||
e1928c86 MC |
4799 | if (!(val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) |
4800 | dev->max_fcoe_conn = 0; | |
4801 | ||
4aacb7af MC |
4802 | addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr, |
4803 | func_ext_config[func]. | |
4804 | iscsi_mac_addr_upper); | |
4805 | addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr, | |
4806 | func_ext_config[func]. | |
4807 | iscsi_mac_addr_lower); | |
4808 | rc = cnic_read_bnx2x_iscsi_mac(dev, addr, | |
4809 | addr1); | |
4810 | if (rc && func > 1) | |
4811 | dev->max_iscsi_conn = 0; | |
4812 | ||
4813 | return; | |
4814 | } | |
4815 | } | |
4816 | ||
4817 | addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr, | |
4818 | func_mf_config[func].e1hov_tag); | |
71034ba8 | 4819 | |
71034ba8 MC |
4820 | val = CNIC_RD(dev, addr); |
4821 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
4822 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
57045c99 MC |
4823 | dev->max_fcoe_conn = 0; |
4824 | dev->max_iscsi_conn = 0; | |
71034ba8 MC |
4825 | } |
4826 | } | |
4aacb7af MC |
4827 | if (!is_valid_ether_addr(dev->mac_addr)) |
4828 | dev->max_iscsi_conn = 0; | |
71034ba8 MC |
4829 | } |
4830 | ||
e21ba414 MC |
4831 | static void cnic_init_bnx2x_kcq(struct cnic_dev *dev) |
4832 | { | |
4833 | struct cnic_local *cp = dev->cnic_priv; | |
4834 | u32 pfid = cp->pfid; | |
4835 | ||
4836 | cp->kcq1.io_addr = BAR_CSTRORM_INTMEM + | |
4837 | CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0); | |
4838 | cp->kcq1.sw_prod_idx = 0; | |
4839 | ||
4840 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { | |
4841 | struct host_hc_status_block_e2 *sb = cp->status_blk.gen; | |
4842 | ||
4843 | cp->kcq1.hw_prod_idx_ptr = | |
4844 | &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS]; | |
4845 | cp->kcq1.status_idx_ptr = | |
4846 | &sb->sb.running_index[SM_RX_ID]; | |
4847 | } else { | |
4848 | struct host_hc_status_block_e1x *sb = cp->status_blk.gen; | |
4849 | ||
4850 | cp->kcq1.hw_prod_idx_ptr = | |
4851 | &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS]; | |
4852 | cp->kcq1.status_idx_ptr = | |
4853 | &sb->sb.running_index[SM_RX_ID]; | |
4854 | } | |
4855 | ||
4856 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { | |
4857 | struct host_hc_status_block_e2 *sb = cp->status_blk.gen; | |
4858 | ||
4859 | cp->kcq2.io_addr = BAR_USTRORM_INTMEM + | |
4860 | USTORM_FCOE_EQ_PROD_OFFSET(pfid); | |
4861 | cp->kcq2.sw_prod_idx = 0; | |
4862 | cp->kcq2.hw_prod_idx_ptr = | |
4863 | &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS]; | |
4864 | cp->kcq2.status_idx_ptr = | |
4865 | &sb->sb.running_index[SM_RX_ID]; | |
4866 | } | |
4867 | } | |
4868 | ||
71034ba8 MC |
4869 | static int cnic_start_bnx2x_hw(struct cnic_dev *dev) |
4870 | { | |
4871 | struct cnic_local *cp = dev->cnic_priv; | |
523224a3 | 4872 | struct cnic_eth_dev *ethdev = cp->ethdev; |
71034ba8 | 4873 | int func = CNIC_FUNC(cp), ret, i; |
1420398d | 4874 | u32 pfid; |
71034ba8 | 4875 | |
ee87a82a MC |
4876 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { |
4877 | u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR); | |
4878 | ||
4879 | if (!(val & 1)) | |
4880 | val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN); | |
4881 | else | |
4882 | val = (val >> 1) & 1; | |
4883 | ||
4884 | if (val) | |
4885 | cp->pfid = func >> 1; | |
4886 | else | |
4887 | cp->pfid = func & 0x6; | |
4888 | } else { | |
4889 | cp->pfid = func; | |
4890 | } | |
1420398d MC |
4891 | pfid = cp->pfid; |
4892 | ||
71034ba8 | 4893 | ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ, |
520efdf4 | 4894 | cp->iscsi_start_cid); |
71034ba8 MC |
4895 | |
4896 | if (ret) | |
4897 | return -ENOMEM; | |
4898 | ||
e1928c86 MC |
4899 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) { |
4900 | ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, | |
4901 | BNX2X_FCOE_NUM_CONNECTIONS, | |
4902 | cp->fcoe_start_cid); | |
4903 | ||
4904 | if (ret) | |
4905 | return -ENOMEM; | |
4906 | } | |
4907 | ||
523224a3 DK |
4908 | cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2; |
4909 | ||
e21ba414 | 4910 | cnic_init_bnx2x_kcq(dev); |
71034ba8 MC |
4911 | |
4912 | cnic_get_bnx2x_iscsi_info(dev); | |
4913 | ||
4914 | /* Only 1 EQ */ | |
e6c28894 | 4915 | CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX); |
71034ba8 | 4916 | CNIC_WR(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4917 | CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0); |
71034ba8 | 4918 | CNIC_WR(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4919 | CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0), |
e6c28894 | 4920 | cp->kcq1.dma.pg_map_arr[1] & 0xffffffff); |
71034ba8 | 4921 | CNIC_WR(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4922 | CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4, |
e6c28894 | 4923 | (u64) cp->kcq1.dma.pg_map_arr[1] >> 32); |
71034ba8 | 4924 | CNIC_WR(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4925 | CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0), |
e6c28894 | 4926 | cp->kcq1.dma.pg_map_arr[0] & 0xffffffff); |
71034ba8 | 4927 | CNIC_WR(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4928 | CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4, |
e6c28894 | 4929 | (u64) cp->kcq1.dma.pg_map_arr[0] >> 32); |
71034ba8 | 4930 | CNIC_WR8(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4931 | CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1); |
71034ba8 | 4932 | CNIC_WR16(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4933 | CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num); |
71034ba8 | 4934 | CNIC_WR8(dev, BAR_CSTRORM_INTMEM + |
1420398d | 4935 | CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0), |
523224a3 | 4936 | HC_INDEX_ISCSI_EQ_CONS); |
71034ba8 MC |
4937 | |
4938 | for (i = 0; i < cp->conn_buf_info.num_pages; i++) { | |
4939 | CNIC_WR(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 4940 | TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i), |
71034ba8 MC |
4941 | cp->conn_buf_info.pgtbl[2 * i]); |
4942 | CNIC_WR(dev, BAR_TSTRORM_INTMEM + | |
1420398d | 4943 | TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4, |
71034ba8 MC |
4944 | cp->conn_buf_info.pgtbl[(2 * i) + 1]); |
4945 | } | |
4946 | ||
4947 | CNIC_WR(dev, BAR_USTRORM_INTMEM + | |
1420398d | 4948 | USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid), |
71034ba8 MC |
4949 | cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff); |
4950 | CNIC_WR(dev, BAR_USTRORM_INTMEM + | |
1420398d | 4951 | USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4, |
71034ba8 MC |
4952 | (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32); |
4953 | ||
523224a3 DK |
4954 | CNIC_WR(dev, BAR_TSTRORM_INTMEM + |
4955 | TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF); | |
4956 | ||
71034ba8 MC |
4957 | cnic_setup_bnx2x_context(dev); |
4958 | ||
71034ba8 MC |
4959 | ret = cnic_init_bnx2x_irq(dev); |
4960 | if (ret) | |
4961 | return ret; | |
4962 | ||
71034ba8 MC |
4963 | return 0; |
4964 | } | |
4965 | ||
86b53606 MC |
4966 | static void cnic_init_rings(struct cnic_dev *dev) |
4967 | { | |
541a7810 | 4968 | struct cnic_local *cp = dev->cnic_priv; |
cd801536 | 4969 | struct cnic_uio_dev *udev = cp->udev; |
541a7810 MC |
4970 | |
4971 | if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags)) | |
4972 | return; | |
4973 | ||
86b53606 MC |
4974 | if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) { |
4975 | cnic_init_bnx2_tx_ring(dev); | |
4976 | cnic_init_bnx2_rx_ring(dev); | |
541a7810 | 4977 | set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags); |
71034ba8 | 4978 | } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) { |
5159fdc1 MC |
4979 | u32 cli = cp->ethdev->iscsi_l2_client_id; |
4980 | u32 cid = cp->ethdev->iscsi_l2_cid; | |
68d7c1aa | 4981 | u32 cl_qzone_id; |
523224a3 | 4982 | struct client_init_ramrod_data *data; |
71034ba8 MC |
4983 | union l5cm_specific_data l5_data; |
4984 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
c7596b79 | 4985 | u32 off, i; |
71034ba8 MC |
4986 | |
4987 | rx_prods.bd_prod = 0; | |
4988 | rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT; | |
4989 | barrier(); | |
4990 | ||
523224a3 DK |
4991 | cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli); |
4992 | ||
c7596b79 | 4993 | off = BAR_USTRORM_INTMEM + |
ee87a82a MC |
4994 | (BNX2X_CHIP_IS_E2(cp->chip_id) ? |
4995 | USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) : | |
4996 | USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli)); | |
71034ba8 MC |
4997 | |
4998 | for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++) | |
c7596b79 | 4999 | CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]); |
71034ba8 | 5000 | |
48f753d2 MC |
5001 | set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags); |
5002 | ||
cd801536 | 5003 | data = udev->l2_buf; |
523224a3 DK |
5004 | |
5005 | memset(data, 0, sizeof(*data)); | |
5006 | ||
5007 | cnic_init_bnx2x_tx_ring(dev, data); | |
5008 | cnic_init_bnx2x_rx_ring(dev, data); | |
5009 | ||
cd801536 MC |
5010 | l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff; |
5011 | l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32; | |
523224a3 | 5012 | |
541a7810 MC |
5013 | set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags); |
5014 | ||
71034ba8 | 5015 | cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP, |
68d7c1aa | 5016 | cid, ETH_CONNECTION_TYPE, &l5_data); |
523224a3 | 5017 | |
48f753d2 MC |
5018 | i = 0; |
5019 | while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) && | |
5020 | ++i < 10) | |
5021 | msleep(1); | |
5022 | ||
5023 | if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags)) | |
5024 | netdev_err(dev->netdev, | |
5025 | "iSCSI CLIENT_SETUP did not complete\n"); | |
c2bff63f | 5026 | cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1); |
5159fdc1 | 5027 | cnic_ring_ctl(dev, cid, cli, 1); |
86b53606 MC |
5028 | } |
5029 | } | |
5030 | ||
5031 | static void cnic_shutdown_rings(struct cnic_dev *dev) | |
5032 | { | |
541a7810 MC |
5033 | struct cnic_local *cp = dev->cnic_priv; |
5034 | ||
5035 | if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags)) | |
5036 | return; | |
5037 | ||
86b53606 MC |
5038 | if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) { |
5039 | cnic_shutdown_bnx2_rx_ring(dev); | |
71034ba8 MC |
5040 | } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) { |
5041 | struct cnic_local *cp = dev->cnic_priv; | |
5159fdc1 MC |
5042 | u32 cli = cp->ethdev->iscsi_l2_client_id; |
5043 | u32 cid = cp->ethdev->iscsi_l2_cid; | |
8b065b67 | 5044 | union l5cm_specific_data l5_data; |
48f753d2 | 5045 | int i; |
71034ba8 | 5046 | |
5159fdc1 | 5047 | cnic_ring_ctl(dev, cid, cli, 0); |
8b065b67 | 5048 | |
48f753d2 MC |
5049 | set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags); |
5050 | ||
8b065b67 MC |
5051 | l5_data.phy_address.lo = cli; |
5052 | l5_data.phy_address.hi = 0; | |
5053 | cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT, | |
5159fdc1 | 5054 | cid, ETH_CONNECTION_TYPE, &l5_data); |
48f753d2 MC |
5055 | i = 0; |
5056 | while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) && | |
5057 | ++i < 10) | |
5058 | msleep(1); | |
5059 | ||
5060 | if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags)) | |
5061 | netdev_err(dev->netdev, | |
5062 | "iSCSI CLIENT_HALT did not complete\n"); | |
c2bff63f | 5063 | cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1); |
1bcdc32c MC |
5064 | |
5065 | memset(&l5_data, 0, sizeof(l5_data)); | |
523224a3 | 5066 | cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL, |
68d7c1aa | 5067 | cid, NONE_CONNECTION_TYPE, &l5_data); |
1bcdc32c | 5068 | msleep(10); |
86b53606 | 5069 | } |
541a7810 | 5070 | clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags); |
86b53606 MC |
5071 | } |
5072 | ||
a3059b12 | 5073 | static int cnic_register_netdev(struct cnic_dev *dev) |
a4636960 MC |
5074 | { |
5075 | struct cnic_local *cp = dev->cnic_priv; | |
5076 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
5077 | int err; | |
5078 | ||
a3059b12 MC |
5079 | if (!ethdev) |
5080 | return -ENODEV; | |
5081 | ||
5082 | if (ethdev->drv_state & CNIC_DRV_STATE_REGD) | |
5083 | return 0; | |
a4636960 MC |
5084 | |
5085 | err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev); | |
a3059b12 | 5086 | if (err) |
ddf79b20 | 5087 | netdev_err(dev->netdev, "register_cnic failed\n"); |
a3059b12 MC |
5088 | |
5089 | return err; | |
5090 | } | |
5091 | ||
5092 | static void cnic_unregister_netdev(struct cnic_dev *dev) | |
5093 | { | |
5094 | struct cnic_local *cp = dev->cnic_priv; | |
5095 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
5096 | ||
5097 | if (!ethdev) | |
5098 | return; | |
5099 | ||
5100 | ethdev->drv_unregister_cnic(dev->netdev); | |
5101 | } | |
5102 | ||
5103 | static int cnic_start_hw(struct cnic_dev *dev) | |
5104 | { | |
5105 | struct cnic_local *cp = dev->cnic_priv; | |
5106 | struct cnic_eth_dev *ethdev = cp->ethdev; | |
5107 | int err; | |
5108 | ||
5109 | if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) | |
5110 | return -EALREADY; | |
a4636960 MC |
5111 | |
5112 | dev->regview = ethdev->io_base; | |
a4636960 MC |
5113 | pci_dev_get(dev->pcidev); |
5114 | cp->func = PCI_FUNC(dev->pcidev->devfn); | |
a4dde3ab | 5115 | cp->status_blk.gen = ethdev->irq_arr[0].status_blk; |
a4636960 MC |
5116 | cp->status_blk_num = ethdev->irq_arr[0].status_blk_num; |
5117 | ||
5118 | err = cp->alloc_resc(dev); | |
5119 | if (err) { | |
ddf79b20 | 5120 | netdev_err(dev->netdev, "allocate resource failure\n"); |
a4636960 MC |
5121 | goto err1; |
5122 | } | |
5123 | ||
5124 | err = cp->start_hw(dev); | |
5125 | if (err) | |
5126 | goto err1; | |
5127 | ||
5128 | err = cnic_cm_open(dev); | |
5129 | if (err) | |
5130 | goto err1; | |
5131 | ||
5132 | set_bit(CNIC_F_CNIC_UP, &dev->flags); | |
5133 | ||
5134 | cp->enable_int(dev); | |
5135 | ||
5136 | return 0; | |
5137 | ||
5138 | err1: | |
a4636960 MC |
5139 | cp->free_resc(dev); |
5140 | pci_dev_put(dev->pcidev); | |
a4636960 MC |
5141 | return err; |
5142 | } | |
5143 | ||
5144 | static void cnic_stop_bnx2_hw(struct cnic_dev *dev) | |
5145 | { | |
a4636960 MC |
5146 | cnic_disable_bnx2_int_sync(dev); |
5147 | ||
5148 | cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0); | |
5149 | cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0); | |
5150 | ||
5151 | cnic_init_context(dev, KWQ_CID); | |
5152 | cnic_init_context(dev, KCQ_CID); | |
5153 | ||
5154 | cnic_setup_5709_context(dev, 0); | |
5155 | cnic_free_irq(dev); | |
5156 | ||
a4636960 MC |
5157 | cnic_free_resc(dev); |
5158 | } | |
5159 | ||
71034ba8 MC |
5160 | |
5161 | static void cnic_stop_bnx2x_hw(struct cnic_dev *dev) | |
5162 | { | |
5163 | struct cnic_local *cp = dev->cnic_priv; | |
71034ba8 MC |
5164 | |
5165 | cnic_free_irq(dev); | |
523224a3 | 5166 | *cp->kcq1.hw_prod_idx_ptr = 0; |
4e9c4fd3 | 5167 | CNIC_WR(dev, BAR_CSTRORM_INTMEM + |
1420398d | 5168 | CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0); |
e6c28894 | 5169 | CNIC_WR16(dev, cp->kcq1.io_addr, 0); |
71034ba8 MC |
5170 | cnic_free_resc(dev); |
5171 | } | |
5172 | ||
a4636960 MC |
5173 | static void cnic_stop_hw(struct cnic_dev *dev) |
5174 | { | |
5175 | if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) { | |
5176 | struct cnic_local *cp = dev->cnic_priv; | |
48f753d2 | 5177 | int i = 0; |
a4636960 | 5178 | |
48f753d2 MC |
5179 | /* Need to wait for the ring shutdown event to complete |
5180 | * before clearing the CNIC_UP flag. | |
5181 | */ | |
cd801536 | 5182 | while (cp->udev->uio_dev != -1 && i < 15) { |
48f753d2 MC |
5183 | msleep(100); |
5184 | i++; | |
5185 | } | |
a3ceeeb8 | 5186 | cnic_shutdown_rings(dev); |
a4636960 MC |
5187 | clear_bit(CNIC_F_CNIC_UP, &dev->flags); |
5188 | rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL); | |
5189 | synchronize_rcu(); | |
5190 | cnic_cm_shutdown(dev); | |
5191 | cp->stop_hw(dev); | |
5192 | pci_dev_put(dev->pcidev); | |
5193 | } | |
5194 | } | |
5195 | ||
5196 | static void cnic_free_dev(struct cnic_dev *dev) | |
5197 | { | |
5198 | int i = 0; | |
5199 | ||
5200 | while ((atomic_read(&dev->ref_count) != 0) && i < 10) { | |
5201 | msleep(100); | |
5202 | i++; | |
5203 | } | |
5204 | if (atomic_read(&dev->ref_count) != 0) | |
ddf79b20 | 5205 | netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n"); |
a4636960 | 5206 | |
ddf79b20 | 5207 | netdev_info(dev->netdev, "Removed CNIC device\n"); |
a4636960 MC |
5208 | dev_put(dev->netdev); |
5209 | kfree(dev); | |
5210 | } | |
5211 | ||
5212 | static struct cnic_dev *cnic_alloc_dev(struct net_device *dev, | |
5213 | struct pci_dev *pdev) | |
5214 | { | |
5215 | struct cnic_dev *cdev; | |
5216 | struct cnic_local *cp; | |
5217 | int alloc_size; | |
5218 | ||
5219 | alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local); | |
5220 | ||
5221 | cdev = kzalloc(alloc_size , GFP_KERNEL); | |
5222 | if (cdev == NULL) { | |
ddf79b20 | 5223 | netdev_err(dev, "allocate dev struct failure\n"); |
a4636960 MC |
5224 | return NULL; |
5225 | } | |
5226 | ||
5227 | cdev->netdev = dev; | |
5228 | cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev); | |
5229 | cdev->register_device = cnic_register_device; | |
5230 | cdev->unregister_device = cnic_unregister_device; | |
5231 | cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv; | |
5232 | ||
5233 | cp = cdev->cnic_priv; | |
5234 | cp->dev = cdev; | |
a4636960 MC |
5235 | cp->l2_single_buf_size = 0x400; |
5236 | cp->l2_rx_ring_size = 3; | |
5237 | ||
5238 | spin_lock_init(&cp->cnic_ulp_lock); | |
5239 | ||
ddf79b20 | 5240 | netdev_info(dev, "Added CNIC device\n"); |
a4636960 MC |
5241 | |
5242 | return cdev; | |
5243 | } | |
5244 | ||
5245 | static struct cnic_dev *init_bnx2_cnic(struct net_device *dev) | |
5246 | { | |
5247 | struct pci_dev *pdev; | |
5248 | struct cnic_dev *cdev; | |
5249 | struct cnic_local *cp; | |
5250 | struct cnic_eth_dev *ethdev = NULL; | |
e2ee3616 | 5251 | struct cnic_eth_dev *(*probe)(struct net_device *) = NULL; |
a4636960 | 5252 | |
e2ee3616 | 5253 | probe = symbol_get(bnx2_cnic_probe); |
a4636960 MC |
5254 | if (probe) { |
5255 | ethdev = (*probe)(dev); | |
64c64608 | 5256 | symbol_put(bnx2_cnic_probe); |
a4636960 MC |
5257 | } |
5258 | if (!ethdev) | |
5259 | return NULL; | |
5260 | ||
5261 | pdev = ethdev->pdev; | |
5262 | if (!pdev) | |
5263 | return NULL; | |
5264 | ||
5265 | dev_hold(dev); | |
5266 | pci_dev_get(pdev); | |
5267 | if (pdev->device == PCI_DEVICE_ID_NX2_5709 || | |
5268 | pdev->device == PCI_DEVICE_ID_NX2_5709S) { | |
5269 | u8 rev; | |
5270 | ||
5271 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
5272 | if (rev < 0x10) { | |
5273 | pci_dev_put(pdev); | |
5274 | goto cnic_err; | |
5275 | } | |
5276 | } | |
5277 | pci_dev_put(pdev); | |
5278 | ||
5279 | cdev = cnic_alloc_dev(dev, pdev); | |
5280 | if (cdev == NULL) | |
5281 | goto cnic_err; | |
5282 | ||
5283 | set_bit(CNIC_F_BNX2_CLASS, &cdev->flags); | |
5284 | cdev->submit_kwqes = cnic_submit_bnx2_kwqes; | |
5285 | ||
5286 | cp = cdev->cnic_priv; | |
5287 | cp->ethdev = ethdev; | |
5288 | cdev->pcidev = pdev; | |
ee87a82a | 5289 | cp->chip_id = ethdev->chip_id; |
a4636960 MC |
5290 | |
5291 | cp->cnic_ops = &cnic_bnx2_ops; | |
5292 | cp->start_hw = cnic_start_bnx2_hw; | |
5293 | cp->stop_hw = cnic_stop_bnx2_hw; | |
5294 | cp->setup_pgtbl = cnic_setup_page_tbl; | |
5295 | cp->alloc_resc = cnic_alloc_bnx2_resc; | |
5296 | cp->free_resc = cnic_free_resc; | |
5297 | cp->start_cm = cnic_cm_init_bnx2_hw; | |
5298 | cp->stop_cm = cnic_cm_stop_bnx2_hw; | |
5299 | cp->enable_int = cnic_enable_bnx2_int; | |
5300 | cp->disable_int_sync = cnic_disable_bnx2_int_sync; | |
5301 | cp->close_conn = cnic_close_bnx2_conn; | |
5302 | cp->next_idx = cnic_bnx2_next_idx; | |
5303 | cp->hw_idx = cnic_bnx2_hw_idx; | |
5304 | return cdev; | |
5305 | ||
5306 | cnic_err: | |
5307 | dev_put(dev); | |
5308 | return NULL; | |
5309 | } | |
5310 | ||
71034ba8 MC |
5311 | static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev) |
5312 | { | |
5313 | struct pci_dev *pdev; | |
5314 | struct cnic_dev *cdev; | |
5315 | struct cnic_local *cp; | |
5316 | struct cnic_eth_dev *ethdev = NULL; | |
5317 | struct cnic_eth_dev *(*probe)(struct net_device *) = NULL; | |
5318 | ||
5319 | probe = symbol_get(bnx2x_cnic_probe); | |
5320 | if (probe) { | |
5321 | ethdev = (*probe)(dev); | |
5322 | symbol_put(bnx2x_cnic_probe); | |
5323 | } | |
5324 | if (!ethdev) | |
5325 | return NULL; | |
5326 | ||
5327 | pdev = ethdev->pdev; | |
5328 | if (!pdev) | |
5329 | return NULL; | |
5330 | ||
5331 | dev_hold(dev); | |
5332 | cdev = cnic_alloc_dev(dev, pdev); | |
5333 | if (cdev == NULL) { | |
5334 | dev_put(dev); | |
5335 | return NULL; | |
5336 | } | |
5337 | ||
5338 | set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags); | |
5339 | cdev->submit_kwqes = cnic_submit_bnx2x_kwqes; | |
5340 | ||
5341 | cp = cdev->cnic_priv; | |
5342 | cp->ethdev = ethdev; | |
5343 | cdev->pcidev = pdev; | |
ee87a82a | 5344 | cp->chip_id = ethdev->chip_id; |
71034ba8 MC |
5345 | |
5346 | cp->cnic_ops = &cnic_bnx2x_ops; | |
5347 | cp->start_hw = cnic_start_bnx2x_hw; | |
5348 | cp->stop_hw = cnic_stop_bnx2x_hw; | |
5349 | cp->setup_pgtbl = cnic_setup_page_tbl_le; | |
5350 | cp->alloc_resc = cnic_alloc_bnx2x_resc; | |
5351 | cp->free_resc = cnic_free_resc; | |
5352 | cp->start_cm = cnic_cm_init_bnx2x_hw; | |
5353 | cp->stop_cm = cnic_cm_stop_bnx2x_hw; | |
5354 | cp->enable_int = cnic_enable_bnx2x_int; | |
5355 | cp->disable_int_sync = cnic_disable_bnx2x_int_sync; | |
ee87a82a MC |
5356 | if (BNX2X_CHIP_IS_E2(cp->chip_id)) |
5357 | cp->ack_int = cnic_ack_bnx2x_e2_msix; | |
5358 | else | |
5359 | cp->ack_int = cnic_ack_bnx2x_msix; | |
71034ba8 MC |
5360 | cp->close_conn = cnic_close_bnx2x_conn; |
5361 | cp->next_idx = cnic_bnx2x_next_idx; | |
5362 | cp->hw_idx = cnic_bnx2x_hw_idx; | |
5363 | return cdev; | |
5364 | } | |
5365 | ||
a4636960 MC |
5366 | static struct cnic_dev *is_cnic_dev(struct net_device *dev) |
5367 | { | |
5368 | struct ethtool_drvinfo drvinfo; | |
5369 | struct cnic_dev *cdev = NULL; | |
5370 | ||
5371 | if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) { | |
5372 | memset(&drvinfo, 0, sizeof(drvinfo)); | |
5373 | dev->ethtool_ops->get_drvinfo(dev, &drvinfo); | |
5374 | ||
5375 | if (!strcmp(drvinfo.driver, "bnx2")) | |
5376 | cdev = init_bnx2_cnic(dev); | |
71034ba8 MC |
5377 | if (!strcmp(drvinfo.driver, "bnx2x")) |
5378 | cdev = init_bnx2x_cnic(dev); | |
a4636960 MC |
5379 | if (cdev) { |
5380 | write_lock(&cnic_dev_lock); | |
5381 | list_add(&cdev->list, &cnic_dev_list); | |
5382 | write_unlock(&cnic_dev_lock); | |
5383 | } | |
5384 | } | |
5385 | return cdev; | |
5386 | } | |
5387 | ||
5388 | /** | |
5389 | * netdev event handler | |
5390 | */ | |
5391 | static int cnic_netdev_event(struct notifier_block *this, unsigned long event, | |
5392 | void *ptr) | |
5393 | { | |
5394 | struct net_device *netdev = ptr; | |
5395 | struct cnic_dev *dev; | |
5396 | int if_type; | |
5397 | int new_dev = 0; | |
5398 | ||
5399 | dev = cnic_from_netdev(netdev); | |
5400 | ||
5401 | if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) { | |
5402 | /* Check for the hot-plug device */ | |
5403 | dev = is_cnic_dev(netdev); | |
5404 | if (dev) { | |
5405 | new_dev = 1; | |
5406 | cnic_hold(dev); | |
5407 | } | |
5408 | } | |
5409 | if (dev) { | |
5410 | struct cnic_local *cp = dev->cnic_priv; | |
5411 | ||
5412 | if (new_dev) | |
5413 | cnic_ulp_init(dev); | |
5414 | else if (event == NETDEV_UNREGISTER) | |
5415 | cnic_ulp_exit(dev); | |
6053bbf7 MC |
5416 | |
5417 | if (event == NETDEV_UP) { | |
a3059b12 MC |
5418 | if (cnic_register_netdev(dev) != 0) { |
5419 | cnic_put(dev); | |
5420 | goto done; | |
5421 | } | |
a4636960 MC |
5422 | if (!cnic_start_hw(dev)) |
5423 | cnic_ulp_start(dev); | |
a4636960 MC |
5424 | } |
5425 | ||
5426 | rcu_read_lock(); | |
5427 | for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) { | |
5428 | struct cnic_ulp_ops *ulp_ops; | |
5429 | void *ctx; | |
5430 | ||
5431 | ulp_ops = rcu_dereference(cp->ulp_ops[if_type]); | |
5432 | if (!ulp_ops || !ulp_ops->indicate_netevent) | |
5433 | continue; | |
5434 | ||
5435 | ctx = cp->ulp_handle[if_type]; | |
5436 | ||
5437 | ulp_ops->indicate_netevent(ctx, event); | |
5438 | } | |
5439 | rcu_read_unlock(); | |
5440 | ||
5441 | if (event == NETDEV_GOING_DOWN) { | |
a4636960 MC |
5442 | cnic_ulp_stop(dev); |
5443 | cnic_stop_hw(dev); | |
a3059b12 | 5444 | cnic_unregister_netdev(dev); |
a4636960 MC |
5445 | } else if (event == NETDEV_UNREGISTER) { |
5446 | write_lock(&cnic_dev_lock); | |
5447 | list_del_init(&dev->list); | |
5448 | write_unlock(&cnic_dev_lock); | |
5449 | ||
5450 | cnic_put(dev); | |
5451 | cnic_free_dev(dev); | |
5452 | goto done; | |
5453 | } | |
5454 | cnic_put(dev); | |
5455 | } | |
5456 | done: | |
5457 | return NOTIFY_DONE; | |
5458 | } | |
5459 | ||
5460 | static struct notifier_block cnic_netdev_notifier = { | |
5461 | .notifier_call = cnic_netdev_event | |
5462 | }; | |
5463 | ||
5464 | static void cnic_release(void) | |
5465 | { | |
5466 | struct cnic_dev *dev; | |
a3ceeeb8 | 5467 | struct cnic_uio_dev *udev; |
a4636960 MC |
5468 | |
5469 | while (!list_empty(&cnic_dev_list)) { | |
5470 | dev = list_entry(cnic_dev_list.next, struct cnic_dev, list); | |
5471 | if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) { | |
5472 | cnic_ulp_stop(dev); | |
5473 | cnic_stop_hw(dev); | |
5474 | } | |
5475 | ||
5476 | cnic_ulp_exit(dev); | |
a3059b12 | 5477 | cnic_unregister_netdev(dev); |
a4636960 MC |
5478 | list_del_init(&dev->list); |
5479 | cnic_free_dev(dev); | |
5480 | } | |
a3ceeeb8 MC |
5481 | while (!list_empty(&cnic_udev_list)) { |
5482 | udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev, | |
5483 | list); | |
5484 | cnic_free_uio(udev); | |
5485 | } | |
a4636960 MC |
5486 | } |
5487 | ||
5488 | static int __init cnic_init(void) | |
5489 | { | |
5490 | int rc = 0; | |
5491 | ||
ddf79b20 | 5492 | pr_info("%s", version); |
a4636960 MC |
5493 | |
5494 | rc = register_netdevice_notifier(&cnic_netdev_notifier); | |
5495 | if (rc) { | |
5496 | cnic_release(); | |
5497 | return rc; | |
5498 | } | |
5499 | ||
fdf24086 MC |
5500 | cnic_wq = create_singlethread_workqueue("cnic_wq"); |
5501 | if (!cnic_wq) { | |
5502 | cnic_release(); | |
5503 | unregister_netdevice_notifier(&cnic_netdev_notifier); | |
5504 | return -ENOMEM; | |
5505 | } | |
5506 | ||
a4636960 MC |
5507 | return 0; |
5508 | } | |
5509 | ||
5510 | static void __exit cnic_exit(void) | |
5511 | { | |
5512 | unregister_netdevice_notifier(&cnic_netdev_notifier); | |
5513 | cnic_release(); | |
fdf24086 | 5514 | destroy_workqueue(cnic_wq); |
a4636960 MC |
5515 | } |
5516 | ||
5517 | module_init(cnic_init); | |
5518 | module_exit(cnic_exit); |