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cxgb3: start qset timers when setup succeeded
[mirror_ubuntu-zesty-kernel.git] / drivers / net / cxgb3 / t3_hw.c
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4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include "common.h"
33#include "regs.h"
34#include "sge_defs.h"
35#include "firmware_exports.h"
36
f2c6879e
DLR		 37/**
38 * t3_wait_op_done_val - wait until an operation is completed
39 * @adapter: the adapter performing the operation
40 * @reg: the register to check for completion
41 * @mask: a single-bit field within @reg that indicates completion
42 * @polarity: the value of the field when the operation is completed
43 * @attempts: number of check iterations
44 * @delay: delay in usecs between iterations
45 * @valp: where to store the value of the register at completion time
46 *
47 * Wait until an operation is completed by checking a bit in a register
48 * up to @attempts times. If @valp is not NULL the value of the register
49 * at the time it indicated completion is stored there. Returns 0 if the
50 * operation completes and -EAGAIN otherwise.
51 */
4d22de3e
DLR		 52
53int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
54 int polarity, int attempts, int delay, u32 *valp)
55{
56 while (1) {
57 u32 val = t3_read_reg(adapter, reg);
58
59 if (!!(val & mask) == polarity) {
60 if (valp)
61 *valp = val;
62 return 0;
63 }
64 if (--attempts == 0)
b881955b 65 return -EAGAIN;
4d22de3e
DLR		 66 if (delay)
67 udelay(delay);
68 }
69}
70
71/**
72 * t3_write_regs - write a bunch of registers
73 * @adapter: the adapter to program
74 * @p: an array of register address/register value pairs
75 * @n: the number of address/value pairs
76 * @offset: register address offset
77 *
78 * Takes an array of register address/register value pairs and writes each
79 * value to the corresponding register. Register addresses are adjusted
80 * by the supplied offset.
81 */
82void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
83 int n, unsigned int offset)
84{
85 while (n--) {
86 t3_write_reg(adapter, p->reg_addr + offset, p->val);
87 p++;
88 }
89}
90
91/**
92 * t3_set_reg_field - set a register field to a value
93 * @adapter: the adapter to program
94 * @addr: the register address
95 * @mask: specifies the portion of the register to modify
96 * @val: the new value for the register field
97 *
98 * Sets a register field specified by the supplied mask to the
99 * given value.
100 */
101void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
102 u32 val)
103{
104 u32 v = t3_read_reg(adapter, addr) & ~mask;
105
106 t3_write_reg(adapter, addr, v | val);
107 t3_read_reg(adapter, addr); /* flush */
108}
109
110/**
111 * t3_read_indirect - read indirectly addressed registers
112 * @adap: the adapter
113 * @addr_reg: register holding the indirect address
114 * @data_reg: register holding the value of the indirect register
115 * @vals: where the read register values are stored
116 * @start_idx: index of first indirect register to read
117 * @nregs: how many indirect registers to read
118 *
119 * Reads registers that are accessed indirectly through an address/data
120 * register pair.
121 */
9265fabf
SH		 122static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg,
123 unsigned int data_reg, u32 *vals,
124 unsigned int nregs, unsigned int start_idx)
4d22de3e
DLR		 125{
126 while (nregs--) {
127 t3_write_reg(adap, addr_reg, start_idx);
128 *vals++ = t3_read_reg(adap, data_reg);
129 start_idx++;
130 }
131}
132
133/**
134 * t3_mc7_bd_read - read from MC7 through backdoor accesses
135 * @mc7: identifies MC7 to read from
136 * @start: index of first 64-bit word to read
137 * @n: number of 64-bit words to read
138 * @buf: where to store the read result
139 *
140 * Read n 64-bit words from MC7 starting at word start, using backdoor
141 * accesses.
142 */
143int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
144 u64 *buf)
145{
146 static const int shift[] = { 0, 0, 16, 24 };
147 static const int step[] = { 0, 32, 16, 8 };
148
149 unsigned int size64 = mc7->size / 8; /* # of 64-bit words */
150 struct adapter *adap = mc7->adapter;
151
152 if (start >= size64 || start + n > size64)
153 return -EINVAL;
154
155 start *= (8 << mc7->width);
156 while (n--) {
157 int i;
158 u64 val64 = 0;
159
160 for (i = (1 << mc7->width) - 1; i >= 0; --i) {
161 int attempts = 10;
162 u32 val;
163
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
165 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
166 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
167 while ((val & F_BUSY) && attempts--)
168 val = t3_read_reg(adap,
169 mc7->offset + A_MC7_BD_OP);
170 if (val & F_BUSY)
171 return -EIO;
172
173 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
174 if (mc7->width == 0) {
175 val64 = t3_read_reg(adap,
176 mc7->offset +
177 A_MC7_BD_DATA0);
178 val64 |= (u64) val << 32;
179 } else {
180 if (mc7->width > 1)
181 val >>= shift[mc7->width];
182 val64 |= (u64) val << (step[mc7->width] * i);
183 }
184 start += 8;
185 }
186 *buf++ = val64;
187 }
188 return 0;
189}
190
191/*
192 * Initialize MI1.
193 */
194static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
195{
196 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
04497982 197 u32 val = F_PREEN | V_CLKDIV(clkdiv);
4d22de3e 198
4d22de3e
DLR		 199 t3_write_reg(adap, A_MI1_CFG, val);
200}
201
04497982 202#define MDIO_ATTEMPTS 20
4d22de3e
DLR		 203
204/*
04497982 205 * MI1 read/write operations for clause 22 PHYs.
4d22de3e 206 */
04497982
DLR		 207static int t3_mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr,
208 int reg_addr, unsigned int *valp)
4d22de3e
DLR		 209{
210 int ret;
211 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
212
213 if (mmd_addr)
214 return -EINVAL;
215
216 mutex_lock(&adapter->mdio_lock);
04497982 217 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
4d22de3e
DLR		 218 t3_write_reg(adapter, A_MI1_ADDR, addr);
219 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
04497982 220 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
4d22de3e
DLR		 221 if (!ret)
222 *valp = t3_read_reg(adapter, A_MI1_DATA);
223 mutex_unlock(&adapter->mdio_lock);
224 return ret;
225}
226
04497982 227static int t3_mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr,
4d22de3e
DLR		 228 int reg_addr, unsigned int val)
229{
230 int ret;
231 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
232
233 if (mmd_addr)
234 return -EINVAL;
235
236 mutex_lock(&adapter->mdio_lock);
04497982 237 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
4d22de3e
DLR		 238 t3_write_reg(adapter, A_MI1_ADDR, addr);
239 t3_write_reg(adapter, A_MI1_DATA, val);
240 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
04497982 241 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
4d22de3e
DLR		 242 mutex_unlock(&adapter->mdio_lock);
243 return ret;
244}
245
246static const struct mdio_ops mi1_mdio_ops = {
04497982
DLR		 247 t3_mi1_read,
248 t3_mi1_write
4d22de3e
DLR		 249};
250
04497982
DLR		 251/*
252 * Performs the address cycle for clause 45 PHYs.
253 * Must be called with the MDIO_LOCK held.
254 */
255static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr,
256 int reg_addr)
257{
258 u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
259
260 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
261 t3_write_reg(adapter, A_MI1_ADDR, addr);
262 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
263 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
264 return t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
265 MDIO_ATTEMPTS, 10);
266}
267
4d22de3e
DLR		 268/*
269 * MI1 read/write operations for indirect-addressed PHYs.
270 */
271static int mi1_ext_read(struct adapter *adapter, int phy_addr, int mmd_addr,
272 int reg_addr, unsigned int *valp)
273{
274 int ret;
4d22de3e
DLR		 275
276 mutex_lock(&adapter->mdio_lock);
04497982 277 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
4d22de3e
DLR		 278 if (!ret) {
279 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
280 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
04497982 281 MDIO_ATTEMPTS, 10);
4d22de3e
DLR		 282 if (!ret)
283 *valp = t3_read_reg(adapter, A_MI1_DATA);
284 }
285 mutex_unlock(&adapter->mdio_lock);
286 return ret;
287}
288
289static int mi1_ext_write(struct adapter *adapter, int phy_addr, int mmd_addr,
290 int reg_addr, unsigned int val)
291{
292 int ret;
4d22de3e
DLR		 293
294 mutex_lock(&adapter->mdio_lock);
04497982 295 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
4d22de3e
DLR		 296 if (!ret) {
297 t3_write_reg(adapter, A_MI1_DATA, val);
298 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
299 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
04497982 300 MDIO_ATTEMPTS, 10);
4d22de3e
DLR		 301 }
302 mutex_unlock(&adapter->mdio_lock);
303 return ret;
304}
305
306static const struct mdio_ops mi1_mdio_ext_ops = {
307 mi1_ext_read,
308 mi1_ext_write
309};
310
311/**
312 * t3_mdio_change_bits - modify the value of a PHY register
313 * @phy: the PHY to operate on
314 * @mmd: the device address
315 * @reg: the register address
316 * @clear: what part of the register value to mask off
317 * @set: what part of the register value to set
318 *
319 * Changes the value of a PHY register by applying a mask to its current
320 * value and ORing the result with a new value.
321 */
322int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
323 unsigned int set)
324{
325 int ret;
326 unsigned int val;
327
328 ret = mdio_read(phy, mmd, reg, &val);
329 if (!ret) {
330 val &= ~clear;
331 ret = mdio_write(phy, mmd, reg, val | set);
332 }
333 return ret;
334}
335
336/**
337 * t3_phy_reset - reset a PHY block
338 * @phy: the PHY to operate on
339 * @mmd: the device address of the PHY block to reset
340 * @wait: how long to wait for the reset to complete in 1ms increments
341 *
342 * Resets a PHY block and optionally waits for the reset to complete.
343 * @mmd should be 0 for 10/100/1000 PHYs and the device address to reset
344 * for 10G PHYs.
345 */
346int t3_phy_reset(struct cphy *phy, int mmd, int wait)
347{
348 int err;
349 unsigned int ctl;
350
351 err = t3_mdio_change_bits(phy, mmd, MII_BMCR, BMCR_PDOWN, BMCR_RESET);
352 if (err || !wait)
353 return err;
354
355 do {
356 err = mdio_read(phy, mmd, MII_BMCR, &ctl);
357 if (err)
358 return err;
359 ctl &= BMCR_RESET;
360 if (ctl)
361 msleep(1);
362 } while (ctl && --wait);
363
364 return ctl ? -1 : 0;
365}
366
367/**
368 * t3_phy_advertise - set the PHY advertisement registers for autoneg
369 * @phy: the PHY to operate on
370 * @advert: bitmap of capabilities the PHY should advertise
371 *
372 * Sets a 10/100/1000 PHY's advertisement registers to advertise the
373 * requested capabilities.
374 */
375int t3_phy_advertise(struct cphy *phy, unsigned int advert)
376{
377 int err;
378 unsigned int val = 0;
379
380 err = mdio_read(phy, 0, MII_CTRL1000, &val);
381 if (err)
382 return err;
383
384 val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
385 if (advert & ADVERTISED_1000baseT_Half)
386 val |= ADVERTISE_1000HALF;
387 if (advert & ADVERTISED_1000baseT_Full)
388 val |= ADVERTISE_1000FULL;
389
390 err = mdio_write(phy, 0, MII_CTRL1000, val);
391 if (err)
392 return err;
393
394 val = 1;
395 if (advert & ADVERTISED_10baseT_Half)
396 val |= ADVERTISE_10HALF;
397 if (advert & ADVERTISED_10baseT_Full)
398 val |= ADVERTISE_10FULL;
399 if (advert & ADVERTISED_100baseT_Half)
400 val |= ADVERTISE_100HALF;
401 if (advert & ADVERTISED_100baseT_Full)
402 val |= ADVERTISE_100FULL;
403 if (advert & ADVERTISED_Pause)
404 val |= ADVERTISE_PAUSE_CAP;
405 if (advert & ADVERTISED_Asym_Pause)
406 val |= ADVERTISE_PAUSE_ASYM;
407 return mdio_write(phy, 0, MII_ADVERTISE, val);
408}
409
0ce2f03b
DLR		 410/**
411 * t3_phy_advertise_fiber - set fiber PHY advertisement register
412 * @phy: the PHY to operate on
413 * @advert: bitmap of capabilities the PHY should advertise
414 *
415 * Sets a fiber PHY's advertisement register to advertise the
416 * requested capabilities.
417 */
418int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert)
419{
420 unsigned int val = 0;
421
422 if (advert & ADVERTISED_1000baseT_Half)
423 val |= ADVERTISE_1000XHALF;
424 if (advert & ADVERTISED_1000baseT_Full)
425 val |= ADVERTISE_1000XFULL;
426 if (advert & ADVERTISED_Pause)
427 val |= ADVERTISE_1000XPAUSE;
428 if (advert & ADVERTISED_Asym_Pause)
429 val |= ADVERTISE_1000XPSE_ASYM;
430 return mdio_write(phy, 0, MII_ADVERTISE, val);
431}
432
4d22de3e
DLR		 433/**
434 * t3_set_phy_speed_duplex - force PHY speed and duplex
435 * @phy: the PHY to operate on
436 * @speed: requested PHY speed
437 * @duplex: requested PHY duplex
438 *
439 * Force a 10/100/1000 PHY's speed and duplex. This also disables
440 * auto-negotiation except for GigE, where auto-negotiation is mandatory.
441 */
442int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
443{
444 int err;
445 unsigned int ctl;
446
447 err = mdio_read(phy, 0, MII_BMCR, &ctl);
448 if (err)
449 return err;
450
451 if (speed >= 0) {
452 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
453 if (speed == SPEED_100)
454 ctl |= BMCR_SPEED100;
455 else if (speed == SPEED_1000)
456 ctl |= BMCR_SPEED1000;
457 }
458 if (duplex >= 0) {
459 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
460 if (duplex == DUPLEX_FULL)
461 ctl |= BMCR_FULLDPLX;
462 }
463 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
464 ctl |= BMCR_ANENABLE;
465 return mdio_write(phy, 0, MII_BMCR, ctl);
466}
467
9b1e3656
DLR		 468int t3_phy_lasi_intr_enable(struct cphy *phy)
469{
470 return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1);
471}
472
473int t3_phy_lasi_intr_disable(struct cphy *phy)
474{
475 return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0);
476}
477
478int t3_phy_lasi_intr_clear(struct cphy *phy)
479{
480 u32 val;
481
482 return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val);
483}
484
485int t3_phy_lasi_intr_handler(struct cphy *phy)
486{
487 unsigned int status;
488 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status);
489
490 if (err)
491 return err;
492 return (status & 1) ? cphy_cause_link_change : 0;
493}
494
4d22de3e 495static const struct adapter_info t3_adap_info[] = {
04497982 496 {2, 0,
4d22de3e 497 F_GPIO2_OEN | F_GPIO4_OEN |
f231e0a5 498 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
4d22de3e 499 &mi1_mdio_ops, "Chelsio PE9000"},
04497982 500 {2, 0,
4d22de3e 501 F_GPIO2_OEN | F_GPIO4_OEN |
f231e0a5 502 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
4d22de3e 503 &mi1_mdio_ops, "Chelsio T302"},
04497982 504 {1, 0,
4d22de3e 505 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
75758e8a 506 F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
f231e0a5 507 { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
4d22de3e 508 &mi1_mdio_ext_ops, "Chelsio T310"},
04497982 509 {2, 0,
4d22de3e
DLR		 510 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
511 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
f231e0a5
DLR		 512 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
513 { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
4d22de3e 514 &mi1_mdio_ext_ops, "Chelsio T320"},
ce03aadd
DLR		 515 {},
516 {},
517 {1, 0,
518 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO6_OEN | F_GPIO7_OEN |
519 F_GPIO10_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
520 { S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
521 &mi1_mdio_ext_ops, "Chelsio T310" },
4d22de3e
DLR		 522};
523
524/*
525 * Return the adapter_info structure with a given index. Out-of-range indices
526 * return NULL.
527 */
528const struct adapter_info *t3_get_adapter_info(unsigned int id)
529{
530 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
531}
532
04497982
DLR		 533struct port_type_info {
534 int (*phy_prep)(struct cphy *phy, struct adapter *adapter,
535 int phy_addr, const struct mdio_ops *ops);
536};
4d22de3e
DLR		 537
538static const struct port_type_info port_types[] = {
04497982
DLR		 539 { NULL },
540 { t3_ael1002_phy_prep },
541 { t3_vsc8211_phy_prep },
542 { NULL},
543 { t3_xaui_direct_phy_prep },
1e882025 544 { t3_ael2005_phy_prep },
04497982
DLR		 545 { t3_qt2045_phy_prep },
546 { t3_ael1006_phy_prep },
547 { NULL },
4d22de3e
DLR		 548};
549
4d22de3e
DLR		 550#define VPD_ENTRY(name, len) \
551 u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
552
553/*
554 * Partial EEPROM Vital Product Data structure. Includes only the ID and
555 * VPD-R sections.
556 */
557struct t3_vpd {
558 u8 id_tag;
559 u8 id_len[2];
560 u8 id_data[16];
561 u8 vpdr_tag;
562 u8 vpdr_len[2];
563 VPD_ENTRY(pn, 16); /* part number */
564 VPD_ENTRY(ec, 16); /* EC level */
167cdf5f 565 VPD_ENTRY(sn, SERNUM_LEN); /* serial number */
4d22de3e
DLR		 566 VPD_ENTRY(na, 12); /* MAC address base */
567 VPD_ENTRY(cclk, 6); /* core clock */
568 VPD_ENTRY(mclk, 6); /* mem clock */
569 VPD_ENTRY(uclk, 6); /* uP clk */
570 VPD_ENTRY(mdc, 6); /* MDIO clk */
571 VPD_ENTRY(mt, 2); /* mem timing */
572 VPD_ENTRY(xaui0cfg, 6); /* XAUI0 config */
573 VPD_ENTRY(xaui1cfg, 6); /* XAUI1 config */
574 VPD_ENTRY(port0, 2); /* PHY0 complex */
575 VPD_ENTRY(port1, 2); /* PHY1 complex */
576 VPD_ENTRY(port2, 2); /* PHY2 complex */
577 VPD_ENTRY(port3, 2); /* PHY3 complex */
578 VPD_ENTRY(rv, 1); /* csum */
579 u32 pad; /* for multiple-of-4 sizing and alignment */
580};
581
9f64306b 582#define EEPROM_MAX_POLL 40
4d22de3e
DLR		 583#define EEPROM_STAT_ADDR 0x4000
584#define VPD_BASE 0xc00
585
586/**
587 * t3_seeprom_read - read a VPD EEPROM location
588 * @adapter: adapter to read
589 * @addr: EEPROM address
590 * @data: where to store the read data
591 *
592 * Read a 32-bit word from a location in VPD EEPROM using the card's PCI
593 * VPD ROM capability. A zero is written to the flag bit when the
594 * addres is written to the control register. The hardware device will
595 * set the flag to 1 when 4 bytes have been read into the data register.
596 */
05e5c116 597int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data)
4d22de3e
DLR		 598{
599 u16 val;
600 int attempts = EEPROM_MAX_POLL;
05e5c116 601 u32 v;
4d22de3e
DLR		 602 unsigned int base = adapter->params.pci.vpd_cap_addr;
603
604 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
605 return -EINVAL;
606
607 pci_write_config_word(adapter->pdev, base + PCI_VPD_ADDR, addr);
608 do {
609 udelay(10);
610 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
611 } while (!(val & PCI_VPD_ADDR_F) && --attempts);
612
613 if (!(val & PCI_VPD_ADDR_F)) {
614 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr);
615 return -EIO;
616 }
05e5c116
AV		 617 pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, &v);
618 *data = cpu_to_le32(v);
4d22de3e
DLR		 619 return 0;
620}
621
622/**
623 * t3_seeprom_write - write a VPD EEPROM location
624 * @adapter: adapter to write
625 * @addr: EEPROM address
626 * @data: value to write
627 *
628 * Write a 32-bit word to a location in VPD EEPROM using the card's PCI
629 * VPD ROM capability.
630 */
05e5c116 631int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data)
4d22de3e
DLR		 632{
633 u16 val;
634 int attempts = EEPROM_MAX_POLL;
635 unsigned int base = adapter->params.pci.vpd_cap_addr;
636
637 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
638 return -EINVAL;
639
640 pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA,
05e5c116 641 le32_to_cpu(data));
4d22de3e
DLR		 642 pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR,
643 addr | PCI_VPD_ADDR_F);
644 do {
645 msleep(1);
646 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
647 } while ((val & PCI_VPD_ADDR_F) && --attempts);
648
649 if (val & PCI_VPD_ADDR_F) {
650 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
651 return -EIO;
652 }
653 return 0;
654}
655
656/**
657 * t3_seeprom_wp - enable/disable EEPROM write protection
658 * @adapter: the adapter
659 * @enable: 1 to enable write protection, 0 to disable it
660 *
661 * Enables or disables write protection on the serial EEPROM.
662 */
663int t3_seeprom_wp(struct adapter *adapter, int enable)
664{
665 return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
666}
667
668/*
669 * Convert a character holding a hex digit to a number.
670 */
671static unsigned int hex2int(unsigned char c)
672{
673 return isdigit(c) ? c - '0' : toupper(c) - 'A' + 10;
674}
675
676/**
677 * get_vpd_params - read VPD parameters from VPD EEPROM
678 * @adapter: adapter to read
679 * @p: where to store the parameters
680 *
681 * Reads card parameters stored in VPD EEPROM.
682 */
683static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
684{
685 int i, addr, ret;
686 struct t3_vpd vpd;
687
688 /*
689 * Card information is normally at VPD_BASE but some early cards had
690 * it at 0.
691 */
05e5c116 692 ret = t3_seeprom_read(adapter, VPD_BASE, (__le32 *)&vpd);
4d22de3e
DLR		 693 if (ret)
694 return ret;
695 addr = vpd.id_tag == 0x82 ? VPD_BASE : 0;
696
697 for (i = 0; i < sizeof(vpd); i += 4) {
698 ret = t3_seeprom_read(adapter, addr + i,
05e5c116 699 (__le32 *)((u8 *)&vpd + i));
4d22de3e
DLR		 700 if (ret)
701 return ret;
702 }
703
704 p->cclk = simple_strtoul(vpd.cclk_data, NULL, 10);
705 p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10);
706 p->uclk = simple_strtoul(vpd.uclk_data, NULL, 10);
707 p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10);
708 p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10);
167cdf5f 709 memcpy(p->sn, vpd.sn_data, SERNUM_LEN);
4d22de3e
DLR		 710
711 /* Old eeproms didn't have port information */
712 if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
713 p->port_type[0] = uses_xaui(adapter) ? 1 : 2;
714 p->port_type[1] = uses_xaui(adapter) ? 6 : 2;
715 } else {
716 p->port_type[0] = hex2int(vpd.port0_data[0]);
717 p->port_type[1] = hex2int(vpd.port1_data[0]);
718 p->xauicfg[0] = simple_strtoul(vpd.xaui0cfg_data, NULL, 16);
719 p->xauicfg[1] = simple_strtoul(vpd.xaui1cfg_data, NULL, 16);
720 }
721
722 for (i = 0; i < 6; i++)
723 p->eth_base[i] = hex2int(vpd.na_data[2 * i]) * 16 +
724 hex2int(vpd.na_data[2 * i + 1]);
725 return 0;
726}
727
728/* serial flash and firmware constants */
729enum {
730 SF_ATTEMPTS = 5, /* max retries for SF1 operations */
731 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
732 SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */
733
734 /* flash command opcodes */
735 SF_PROG_PAGE = 2, /* program page */
736 SF_WR_DISABLE = 4, /* disable writes */
737 SF_RD_STATUS = 5, /* read status register */
738 SF_WR_ENABLE = 6, /* enable writes */
739 SF_RD_DATA_FAST = 0xb, /* read flash */
740 SF_ERASE_SECTOR = 0xd8, /* erase sector */
741
742 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
80513675 743 FW_VERS_ADDR = 0x7fffc, /* flash address holding FW version */
2e283962 744 FW_MIN_SIZE = 8 /* at least version and csum */
4d22de3e
DLR		 745};
746
747/**
748 * sf1_read - read data from the serial flash
749 * @adapter: the adapter
750 * @byte_cnt: number of bytes to read
751 * @cont: whether another operation will be chained
752 * @valp: where to store the read data
753 *
754 * Reads up to 4 bytes of data from the serial flash. The location of
755 * the read needs to be specified prior to calling this by issuing the
756 * appropriate commands to the serial flash.
757 */
758static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
759 u32 *valp)
760{
761 int ret;
762
763 if (!byte_cnt || byte_cnt > 4)
764 return -EINVAL;
765 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
766 return -EBUSY;
767 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
768 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
769 if (!ret)
770 *valp = t3_read_reg(adapter, A_SF_DATA);
771 return ret;
772}
773
774/**
775 * sf1_write - write data to the serial flash
776 * @adapter: the adapter
777 * @byte_cnt: number of bytes to write
778 * @cont: whether another operation will be chained
779 * @val: value to write
780 *
781 * Writes up to 4 bytes of data to the serial flash. The location of
782 * the write needs to be specified prior to calling this by issuing the
783 * appropriate commands to the serial flash.
784 */
785static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
786 u32 val)
787{
788 if (!byte_cnt || byte_cnt > 4)
789 return -EINVAL;
790 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
791 return -EBUSY;
792 t3_write_reg(adapter, A_SF_DATA, val);
793 t3_write_reg(adapter, A_SF_OP,
794 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
795 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
796}
797
798/**
799 * flash_wait_op - wait for a flash operation to complete
800 * @adapter: the adapter
801 * @attempts: max number of polls of the status register
802 * @delay: delay between polls in ms
803 *
804 * Wait for a flash operation to complete by polling the status register.
805 */
806static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
807{
808 int ret;
809 u32 status;
810
811 while (1) {
812 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
813 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
814 return ret;
815 if (!(status & 1))
816 return 0;
817 if (--attempts == 0)
818 return -EAGAIN;
819 if (delay)
820 msleep(delay);
821 }
822}
823
824/**
825 * t3_read_flash - read words from serial flash
826 * @adapter: the adapter
827 * @addr: the start address for the read
828 * @nwords: how many 32-bit words to read
829 * @data: where to store the read data
830 * @byte_oriented: whether to store data as bytes or as words
831 *
832 * Read the specified number of 32-bit words from the serial flash.
833 * If @byte_oriented is set the read data is stored as a byte array
834 * (i.e., big-endian), otherwise as 32-bit words in the platform's
835 * natural endianess.
836 */
837int t3_read_flash(struct adapter *adapter, unsigned int addr,
838 unsigned int nwords, u32 *data, int byte_oriented)
839{
840 int ret;
841
842 if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3))
843 return -EINVAL;
844
845 addr = swab32(addr) | SF_RD_DATA_FAST;
846
847 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 ||
848 (ret = sf1_read(adapter, 1, 1, data)) != 0)
849 return ret;
850
851 for (; nwords; nwords--, data++) {
852 ret = sf1_read(adapter, 4, nwords > 1, data);
853 if (ret)
854 return ret;
855 if (byte_oriented)
856 *data = htonl(*data);
857 }
858 return 0;
859}
860
861/**
862 * t3_write_flash - write up to a page of data to the serial flash
863 * @adapter: the adapter
864 * @addr: the start address to write
865 * @n: length of data to write
866 * @data: the data to write
867 *
868 * Writes up to a page of data (256 bytes) to the serial flash starting
869 * at the given address.
870 */
871static int t3_write_flash(struct adapter *adapter, unsigned int addr,
872 unsigned int n, const u8 *data)
873{
874 int ret;
875 u32 buf[64];
876 unsigned int i, c, left, val, offset = addr & 0xff;
877
878 if (addr + n > SF_SIZE || offset + n > 256)
879 return -EINVAL;
880
881 val = swab32(addr) | SF_PROG_PAGE;
882
883 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
884 (ret = sf1_write(adapter, 4, 1, val)) != 0)
885 return ret;
886
887 for (left = n; left; left -= c) {
888 c = min(left, 4U);
889 for (val = 0, i = 0; i < c; ++i)
890 val = (val << 8) + *data++;
891
892 ret = sf1_write(adapter, c, c != left, val);
893 if (ret)
894 return ret;
895 }
896 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
897 return ret;
898
899 /* Read the page to verify the write succeeded */
900 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
901 if (ret)
902 return ret;
903
904 if (memcmp(data - n, (u8 *) buf + offset, n))
905 return -EIO;
906 return 0;
907}
908
480fe1a3 909/**
47330077 910 * t3_get_tp_version - read the tp sram version
480fe1a3 911 * @adapter: the adapter
47330077 912 * @vers: where to place the version
480fe1a3 913 *
47330077 914 * Reads the protocol sram version from sram.
480fe1a3 915 */
47330077 916int t3_get_tp_version(struct adapter *adapter, u32 *vers)
480fe1a3
DLR		 917{
918 int ret;
480fe1a3
DLR		 919
920 /* Get version loaded in SRAM */
921 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
922 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
923 1, 1, 5, 1);
924 if (ret)
925 return ret;
2eab17ab 926
47330077
DLR		 927 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
928
929 return 0;
930}
931
932/**
933 * t3_check_tpsram_version - read the tp sram version
934 * @adapter: the adapter
47330077
DLR		 935 *
936 * Reads the protocol sram version from flash.
937 */
8207befa 938int t3_check_tpsram_version(struct adapter *adapter)
47330077
DLR		 939{
940 int ret;
941 u32 vers;
942 unsigned int major, minor;
943
944 if (adapter->params.rev == T3_REV_A)
945 return 0;
946
47330077
DLR		 947
948 ret = t3_get_tp_version(adapter, &vers);
949 if (ret)
950 return ret;
480fe1a3
DLR		 951
952 major = G_TP_VERSION_MAJOR(vers);
953 minor = G_TP_VERSION_MINOR(vers);
954
2eab17ab 955 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
480fe1a3 956 return 0;
47330077 957 else {
47330077
DLR		 958 CH_ERR(adapter, "found wrong TP version (%u.%u), "
959 "driver compiled for version %d.%d\n", major, minor,
960 TP_VERSION_MAJOR, TP_VERSION_MINOR);
961 }
480fe1a3
DLR		 962 return -EINVAL;
963}
964
965/**
2eab17ab 966 * t3_check_tpsram - check if provided protocol SRAM
480fe1a3
DLR		 967 * is compatible with this driver
968 * @adapter: the adapter
969 * @tp_sram: the firmware image to write
970 * @size: image size
971 *
972 * Checks if an adapter's tp sram is compatible with the driver.
973 * Returns 0 if the versions are compatible, a negative error otherwise.
974 */
2c733a16
DW		 975int t3_check_tpsram(struct adapter *adapter, const u8 *tp_sram,
976 unsigned int size)
480fe1a3
DLR		 977{
978 u32 csum;
979 unsigned int i;
05e5c116 980 const __be32 *p = (const __be32 *)tp_sram;
480fe1a3
DLR		 981
982 /* Verify checksum */
983 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
984 csum += ntohl(p[i]);
985 if (csum != 0xffffffff) {
986 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n",
987 csum);
988 return -EINVAL;
989 }
990
991 return 0;
992}
993
4aac3899
DLR		 994enum fw_version_type {
995 FW_VERSION_N3,
996 FW_VERSION_T3
997};
998
4d22de3e
DLR		 999/**
1000 * t3_get_fw_version - read the firmware version
1001 * @adapter: the adapter
1002 * @vers: where to place the version
1003 *
1004 * Reads the FW version from flash.
1005 */
1006int t3_get_fw_version(struct adapter *adapter, u32 *vers)
1007{
1008 return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
1009}
1010
1011/**
1012 * t3_check_fw_version - check if the FW is compatible with this driver
1013 * @adapter: the adapter
8207befa 1014 *
4d22de3e
DLR		 1015 * Checks if an adapter's FW is compatible with the driver. Returns 0
1016 * if the versions are compatible, a negative error otherwise.
1017 */
8207befa 1018int t3_check_fw_version(struct adapter *adapter)
4d22de3e
DLR		 1019{
1020 int ret;
1021 u32 vers;
4aac3899 1022 unsigned int type, major, minor;
4d22de3e
DLR		 1023
1024 ret = t3_get_fw_version(adapter, &vers);
1025 if (ret)
1026 return ret;
1027
4aac3899
DLR		 1028 type = G_FW_VERSION_TYPE(vers);
1029 major = G_FW_VERSION_MAJOR(vers);
1030 minor = G_FW_VERSION_MINOR(vers);
4d22de3e 1031
75d8626f
DLR		 1032 if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR &&
1033 minor == FW_VERSION_MINOR)
4d22de3e 1034 return 0;
8207befa 1035 else if (major != FW_VERSION_MAJOR || minor < FW_VERSION_MINOR)
273fa904
DLR		 1036 CH_WARN(adapter, "found old FW minor version(%u.%u), "
1037 "driver compiled for version %u.%u\n", major, minor,
1038 FW_VERSION_MAJOR, FW_VERSION_MINOR);
8207befa 1039 else {
273fa904 1040 CH_WARN(adapter, "found newer FW version(%u.%u), "
a5a3b460
DLR		 1041 "driver compiled for version %u.%u\n", major, minor,
1042 FW_VERSION_MAJOR, FW_VERSION_MINOR);
273fa904 1043 return 0;
a5a3b460 1044 }
4d22de3e
DLR		 1045 return -EINVAL;
1046}
1047
1048/**
1049 * t3_flash_erase_sectors - erase a range of flash sectors
1050 * @adapter: the adapter
1051 * @start: the first sector to erase
1052 * @end: the last sector to erase
1053 *
1054 * Erases the sectors in the given range.
1055 */
1056static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end)
1057{
1058 while (start <= end) {
1059 int ret;
1060
1061 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
1062 (ret = sf1_write(adapter, 4, 0,
1063 SF_ERASE_SECTOR | (start << 8))) != 0 ||
1064 (ret = flash_wait_op(adapter, 5, 500)) != 0)
1065 return ret;
1066 start++;
1067 }
1068 return 0;
1069}
1070
1071/*
1072 * t3_load_fw - download firmware
1073 * @adapter: the adapter
8a9fab22 1074 * @fw_data: the firmware image to write
4d22de3e
DLR		 1075 * @size: image size
1076 *
1077 * Write the supplied firmware image to the card's serial flash.
1078 * The FW image has the following sections: @size - 8 bytes of code and
1079 * data, followed by 4 bytes of FW version, followed by the 32-bit
1080 * 1's complement checksum of the whole image.
1081 */
1082int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size)
1083{
1084 u32 csum;
1085 unsigned int i;
05e5c116 1086 const __be32 *p = (const __be32 *)fw_data;
4d22de3e
DLR		 1087 int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
1088
2e283962 1089 if ((size & 3) || size < FW_MIN_SIZE)
4d22de3e
DLR		 1090 return -EINVAL;
1091 if (size > FW_VERS_ADDR + 8 - FW_FLASH_BOOT_ADDR)
1092 return -EFBIG;
1093
1094 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1095 csum += ntohl(p[i]);
1096 if (csum != 0xffffffff) {
1097 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1098 csum);
1099 return -EINVAL;
1100 }
1101
1102 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
1103 if (ret)
1104 goto out;
1105
1106 size -= 8; /* trim off version and checksum */
1107 for (addr = FW_FLASH_BOOT_ADDR; size;) {
1108 unsigned int chunk_size = min(size, 256U);
1109
1110 ret = t3_write_flash(adapter, addr, chunk_size, fw_data);
1111 if (ret)
1112 goto out;
1113
1114 addr += chunk_size;
1115 fw_data += chunk_size;
1116 size -= chunk_size;
1117 }
1118
1119 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data);
1120out:
1121 if (ret)
1122 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
1123 return ret;
1124}
1125
1126#define CIM_CTL_BASE 0x2000
1127
1128/**
1129 * t3_cim_ctl_blk_read - read a block from CIM control region
1130 *
1131 * @adap: the adapter
1132 * @addr: the start address within the CIM control region
1133 * @n: number of words to read
1134 * @valp: where to store the result
1135 *
1136 * Reads a block of 4-byte words from the CIM control region.
1137 */
1138int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
1139 unsigned int n, unsigned int *valp)
1140{
1141 int ret = 0;
1142
1143 if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1144 return -EBUSY;
1145
1146 for ( ; !ret && n--; addr += 4) {
1147 t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
1148 ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
1149 0, 5, 2);
1150 if (!ret)
1151 *valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
1152 }
1153 return ret;
1154}
1155
bf792094
DLR		 1156static void t3_gate_rx_traffic(struct cmac *mac, u32 *rx_cfg,
1157 u32 *rx_hash_high, u32 *rx_hash_low)
1158{
1159 /* stop Rx unicast traffic */
1160 t3_mac_disable_exact_filters(mac);
1161
1162 /* stop broadcast, multicast, promiscuous mode traffic */
1163 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG);
1164 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
1165 F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES,
1166 F_DISBCAST);
1167
1168 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH);
1169 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0);
1170
1171 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW);
1172 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0);
1173
1174 /* Leave time to drain max RX fifo */
1175 msleep(1);
1176}
1177
1178static void t3_open_rx_traffic(struct cmac *mac, u32 rx_cfg,
1179 u32 rx_hash_high, u32 rx_hash_low)
1180{
1181 t3_mac_enable_exact_filters(mac);
1182 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
1183 F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES,
1184 rx_cfg);
1185 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high);
1186 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low);
1187}
4d22de3e
DLR		 1188
1189/**
1190 * t3_link_changed - handle interface link changes
1191 * @adapter: the adapter
1192 * @port_id: the port index that changed link state
1193 *
1194 * Called when a port's link settings change to propagate the new values
1195 * to the associated PHY and MAC. After performing the common tasks it
1196 * invokes an OS-specific handler.
1197 */
1198void t3_link_changed(struct adapter *adapter, int port_id)
1199{
1200 int link_ok, speed, duplex, fc;
1201 struct port_info *pi = adap2pinfo(adapter, port_id);
1202 struct cphy *phy = &pi->phy;
1203 struct cmac *mac = &pi->mac;
1204 struct link_config *lc = &pi->link_config;
bf792094 1205 int force_link_down = 0;
4d22de3e
DLR		 1206
1207 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
1208
bf792094
DLR		 1209 if (!lc->link_ok && link_ok) {
1210 u32 rx_cfg, rx_hash_high, rx_hash_low;
1211 u32 status;
1212
1213 t3_xgm_intr_enable(adapter, port_id);
1214 t3_gate_rx_traffic(mac, &rx_cfg, &rx_hash_high, &rx_hash_low);
1215 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1216 t3_mac_enable(mac, MAC_DIRECTION_RX);
1217
1218 status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
1219 if (status & F_LINKFAULTCHANGE) {
1220 mac->stats.link_faults++;
1221 force_link_down = 1;
1222 }
1223 t3_open_rx_traffic(mac, rx_cfg, rx_hash_high, rx_hash_low);
1224
1225 if (force_link_down) {
1226 t3_os_link_fault_handler(adapter, port_id);
1227 return;
1228 }
1229 }
1230
9b1e3656
DLR		 1231 if (lc->requested_fc & PAUSE_AUTONEG)
1232 fc &= lc->requested_fc;
1233 else
1234 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1235
1236 if (link_ok == lc->link_ok && speed == lc->speed &&
1237 duplex == lc->duplex && fc == lc->fc)
1238 return; /* nothing changed */
1239
4d22de3e
DLR		 1240 if (link_ok != lc->link_ok && adapter->params.rev > 0 &&
1241 uses_xaui(adapter)) {
1242 if (link_ok)
1243 t3b_pcs_reset(mac);
1244 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1245 link_ok ? F_TXACTENABLE | F_RXEN : 0);
1246 }
1247 lc->link_ok = link_ok;
1248 lc->speed = speed < 0 ? SPEED_INVALID : speed;
1249 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
4d22de3e
DLR		 1250
1251 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
1252 /* Set MAC speed, duplex, and flow control to match PHY. */
1253 t3_mac_set_speed_duplex_fc(mac, speed, duplex, fc);
1254 lc->fc = fc;
1255 }
1256
1257 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
1258}
1259
bf792094
DLR		 1260void t3_link_fault(struct adapter *adapter, int port_id)
1261{
1262 struct port_info *pi = adap2pinfo(adapter, port_id);
1263 struct cmac *mac = &pi->mac;
1264 struct cphy *phy = &pi->phy;
1265 struct link_config *lc = &pi->link_config;
1266 int link_ok, speed, duplex, fc, link_fault;
1267 u32 rx_cfg, rx_hash_high, rx_hash_low;
1268
1269 t3_gate_rx_traffic(mac, &rx_cfg, &rx_hash_high, &rx_hash_low);
1270
1271 if (adapter->params.rev > 0 && uses_xaui(adapter))
1272 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0);
1273
1274 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1275 t3_mac_enable(mac, MAC_DIRECTION_RX);
1276
1277 t3_open_rx_traffic(mac, rx_cfg, rx_hash_high, rx_hash_low);
1278
1279 link_fault = t3_read_reg(adapter,
1280 A_XGM_INT_STATUS + mac->offset);
1281 link_fault &= F_LINKFAULTCHANGE;
1282
1283 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
1284
1285 if (link_fault) {
1286 lc->link_ok = 0;
1287 lc->speed = SPEED_INVALID;
1288 lc->duplex = DUPLEX_INVALID;
1289
1290 t3_os_link_fault(adapter, port_id, 0);
1291
1292 /* Account link faults only when the phy reports a link up */
1293 if (link_ok)
1294 mac->stats.link_faults++;
1295
1296 msleep(1000);
1297 t3_os_link_fault_handler(adapter, port_id);
1298 } else {
1299 if (link_ok)
1300 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1301 F_TXACTENABLE | F_RXEN);
1302
1303 pi->link_fault = 0;
1304 lc->link_ok = (unsigned char)link_ok;
1305 lc->speed = speed < 0 ? SPEED_INVALID : speed;
1306 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
1307 t3_os_link_fault(adapter, port_id, link_ok);
1308 }
1309}
1310
4d22de3e
DLR		 1311/**
1312 * t3_link_start - apply link configuration to MAC/PHY
1313 * @phy: the PHY to setup
1314 * @mac: the MAC to setup
1315 * @lc: the requested link configuration
1316 *
1317 * Set up a port's MAC and PHY according to a desired link configuration.
1318 * - If the PHY can auto-negotiate first decide what to advertise, then
1319 * enable/disable auto-negotiation as desired, and reset.
1320 * - If the PHY does not auto-negotiate just reset it.
1321 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1322 * otherwise do it later based on the outcome of auto-negotiation.
1323 */
1324int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
1325{
1326 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1327
1328 lc->link_ok = 0;
1329 if (lc->supported & SUPPORTED_Autoneg) {
1330 lc->advertising &= ~(ADVERTISED_Asym_Pause | ADVERTISED_Pause);
1331 if (fc) {
1332 lc->advertising |= ADVERTISED_Asym_Pause;
1333 if (fc & PAUSE_RX)
1334 lc->advertising |= ADVERTISED_Pause;
1335 }
1336 phy->ops->advertise(phy, lc->advertising);
1337
1338 if (lc->autoneg == AUTONEG_DISABLE) {
1339 lc->speed = lc->requested_speed;
1340 lc->duplex = lc->requested_duplex;
1341 lc->fc = (unsigned char)fc;
1342 t3_mac_set_speed_duplex_fc(mac, lc->speed, lc->duplex,
1343 fc);
1344 /* Also disables autoneg */
1345 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
4d22de3e
DLR		 1346 } else
1347 phy->ops->autoneg_enable(phy);
1348 } else {
1349 t3_mac_set_speed_duplex_fc(mac, -1, -1, fc);
1350 lc->fc = (unsigned char)fc;
1351 phy->ops->reset(phy, 0);
1352 }
1353 return 0;
1354}
1355
1356/**
1357 * t3_set_vlan_accel - control HW VLAN extraction
1358 * @adapter: the adapter
1359 * @ports: bitmap of adapter ports to operate on
1360 * @on: enable (1) or disable (0) HW VLAN extraction
1361 *
1362 * Enables or disables HW extraction of VLAN tags for the given port.
1363 */
1364void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on)
1365{
1366 t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
1367 ports << S_VLANEXTRACTIONENABLE,
1368 on ? (ports << S_VLANEXTRACTIONENABLE) : 0);
1369}
1370
1371struct intr_info {
1372 unsigned int mask; /* bits to check in interrupt status */
1373 const char *msg; /* message to print or NULL */
1374 short stat_idx; /* stat counter to increment or -1 */
20d3fc11 1375 unsigned short fatal; /* whether the condition reported is fatal */
4d22de3e
DLR		 1376};
1377
1378/**
1379 * t3_handle_intr_status - table driven interrupt handler
1380 * @adapter: the adapter that generated the interrupt
1381 * @reg: the interrupt status register to process
1382 * @mask: a mask to apply to the interrupt status
1383 * @acts: table of interrupt actions
1384 * @stats: statistics counters tracking interrupt occurences
1385 *
1386 * A table driven interrupt handler that applies a set of masks to an
1387 * interrupt status word and performs the corresponding actions if the
1388 * interrupts described by the mask have occured. The actions include
1389 * optionally printing a warning or alert message, and optionally
1390 * incrementing a stat counter. The table is terminated by an entry
1391 * specifying mask 0. Returns the number of fatal interrupt conditions.
1392 */
1393static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg,
1394 unsigned int mask,
1395 const struct intr_info *acts,
1396 unsigned long *stats)
1397{
1398 int fatal = 0;
1399 unsigned int status = t3_read_reg(adapter, reg) & mask;
1400
1401 for (; acts->mask; ++acts) {
1402 if (!(status & acts->mask))
1403 continue;
1404 if (acts->fatal) {
1405 fatal++;
1406 CH_ALERT(adapter, "%s (0x%x)\n",
1407 acts->msg, status & acts->mask);
1408 } else if (acts->msg)
1409 CH_WARN(adapter, "%s (0x%x)\n",
1410 acts->msg, status & acts->mask);
1411 if (acts->stat_idx >= 0)
1412 stats[acts->stat_idx]++;
1413 }
1414 if (status) /* clear processed interrupts */
1415 t3_write_reg(adapter, reg, status);
1416 return fatal;
1417}
1418
b881955b
DLR		 1419#define SGE_INTR_MASK (F_RSPQDISABLED | \
1420 F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR | \
1421 F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
1422 F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
1423 V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
1424 F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
1425 F_HIRCQPARITYERROR)
4d22de3e
DLR		 1426#define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \
1427 F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \
1428 F_NFASRCHFAIL)
1429#define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE))
1430#define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1431 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \
fc882196 1432 F_TXFIFO_UNDERRUN)
4d22de3e
DLR		 1433#define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \
1434 F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \
1435 F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \
1436 F_DETCORECCERR | F_DETUNCECCERR | F_PIOPARERR | \
1437 V_WFPARERR(M_WFPARERR) | V_RFPARERR(M_RFPARERR) | \
1438 V_CFPARERR(M_CFPARERR) /* | V_MSIXPARERR(M_MSIXPARERR) */)
1439#define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\
1440 F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \
1441 /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \
b881955b
DLR		 1442 F_RETRYBUFPARERR | F_RETRYLUTPARERR | F_RXPARERR | \
1443 F_TXPARERR | V_BISTERR(M_BISTERR))
1444#define ULPRX_INTR_MASK (F_PARERRDATA | F_PARERRPCMD | F_ARBPF1PERR | \
1445 F_ARBPF0PERR | F_ARBFPERR | F_PCMDMUXPERR | \
1446 F_DATASELFRAMEERR1 | F_DATASELFRAMEERR0)
1447#define ULPTX_INTR_MASK 0xfc
1448#define CPLSW_INTR_MASK (F_CIM_OP_MAP_PERR | F_TP_FRAMING_ERROR | \
4d22de3e
DLR		 1449 F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \
1450 F_ZERO_SWITCH_ERROR)
1451#define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \
1452 F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \
1453 F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \
b881955b
DLR		 1454 F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT | \
1455 F_DRAMPARERR | F_ICACHEPARERR | F_DCACHEPARERR | \
1456 F_OBQSGEPARERR | F_OBQULPHIPARERR | F_OBQULPLOPARERR | \
1457 F_IBQSGELOPARERR | F_IBQSGEHIPARERR | F_IBQULPPARERR | \
1458 F_IBQTPPARERR | F_ITAGPARERR | F_DTAGPARERR)
4d22de3e
DLR		 1459#define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \
1460 V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \
1461 V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR))
1462#define PMRX_INTR_MASK (F_ZERO_E_CMD_ERROR | IESPI_FRM_ERR | OCSPI_FRM_ERR | \
1463 V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR) | \
1464 V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR))
1465#define MPS_INTR_MASK (V_TX0TPPARERRENB(M_TX0TPPARERRENB) | \
1466 V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \
1467 V_RXTPPARERRENB(M_RXTPPARERRENB) | \
1468 V_MCAPARERRENB(M_MCAPARERRENB))
bf792094 1469#define XGM_EXTRA_INTR_MASK (F_LINKFAULTCHANGE)
4d22de3e
DLR		 1470#define PL_INTR_MASK (F_T3DBG | F_XGMAC0_0 | F_XGMAC0_1 | F_MC5A | F_PM1_TX | \
1471 F_PM1_RX | F_ULP2_TX | F_ULP2_RX | F_TP1 | F_CIM | \
1472 F_MC7_CM | F_MC7_PMTX | F_MC7_PMRX | F_SGE3 | F_PCIM0 | \
1473 F_MPS0 | F_CPL_SWITCH)
4d22de3e
DLR		 1474/*
1475 * Interrupt handler for the PCIX1 module.
1476 */
1477static void pci_intr_handler(struct adapter *adapter)
1478{
1479 static const struct intr_info pcix1_intr_info[] = {
4d22de3e
DLR		 1480 {F_MSTDETPARERR, "PCI master detected parity error", -1, 1},
1481 {F_SIGTARABT, "PCI signaled target abort", -1, 1},
1482 {F_RCVTARABT, "PCI received target abort", -1, 1},
1483 {F_RCVMSTABT, "PCI received master abort", -1, 1},
1484 {F_SIGSYSERR, "PCI signaled system error", -1, 1},
1485 {F_DETPARERR, "PCI detected parity error", -1, 1},
1486 {F_SPLCMPDIS, "PCI split completion discarded", -1, 1},
1487 {F_UNXSPLCMP, "PCI unexpected split completion error", -1, 1},
1488 {F_RCVSPLCMPERR, "PCI received split completion error", -1,
1489 1},
1490 {F_DETCORECCERR, "PCI correctable ECC error",
1491 STAT_PCI_CORR_ECC, 0},
1492 {F_DETUNCECCERR, "PCI uncorrectable ECC error", -1, 1},
1493 {F_PIOPARERR, "PCI PIO FIFO parity error", -1, 1},
1494 {V_WFPARERR(M_WFPARERR), "PCI write FIFO parity error", -1,
1495 1},
1496 {V_RFPARERR(M_RFPARERR), "PCI read FIFO parity error", -1,
1497 1},
1498 {V_CFPARERR(M_CFPARERR), "PCI command FIFO parity error", -1,
1499 1},
1500 {V_MSIXPARERR(M_MSIXPARERR), "PCI MSI-X table/PBA parity "
1501 "error", -1, 1},
1502 {0}
1503 };
1504
1505 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK,
1506 pcix1_intr_info, adapter->irq_stats))
1507 t3_fatal_err(adapter);
1508}
1509
1510/*
1511 * Interrupt handler for the PCIE module.
1512 */
1513static void pcie_intr_handler(struct adapter *adapter)
1514{
1515 static const struct intr_info pcie_intr_info[] = {
b5a44bcb 1516 {F_PEXERR, "PCI PEX error", -1, 1},
4d22de3e
DLR		 1517 {F_UNXSPLCPLERRR,
1518 "PCI unexpected split completion DMA read error", -1, 1},
1519 {F_UNXSPLCPLERRC,
1520 "PCI unexpected split completion DMA command error", -1, 1},
1521 {F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1},
1522 {F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1},
1523 {F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1},
1524 {F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1},
1525 {V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR),
1526 "PCI MSI-X table/PBA parity error", -1, 1},
b881955b
DLR		 1527 {F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1},
1528 {F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1},
1529 {F_RXPARERR, "PCI Rx parity error", -1, 1},
1530 {F_TXPARERR, "PCI Tx parity error", -1, 1},
4d22de3e
DLR		 1531 {V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1},
1532 {0}
1533 };
1534
3eea3337
DLR		 1535 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1536 CH_ALERT(adapter, "PEX error code 0x%x\n",
1537 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1538
4d22de3e
DLR		 1539 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK,
1540 pcie_intr_info, adapter->irq_stats))
1541 t3_fatal_err(adapter);
1542}
1543
1544/*
1545 * TP interrupt handler.
1546 */
1547static void tp_intr_handler(struct adapter *adapter)
1548{
1549 static const struct intr_info tp_intr_info[] = {
1550 {0xffffff, "TP parity error", -1, 1},
1551 {0x1000000, "TP out of Rx pages", -1, 1},
1552 {0x2000000, "TP out of Tx pages", -1, 1},
1553 {0}
1554 };
1555
a2604be5 1556 static struct intr_info tp_intr_info_t3c[] = {
b881955b
DLR		 1557 {0x1fffffff, "TP parity error", -1, 1},
1558 {F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1},
1559 {F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1},
1560 {0}
a2604be5
DLR		 1561 };
1562
4d22de3e 1563 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
a2604be5 1564 adapter->params.rev < T3_REV_C ?
b881955b 1565 tp_intr_info : tp_intr_info_t3c, NULL))
4d22de3e
DLR		 1566 t3_fatal_err(adapter);
1567}
1568
1569/*
1570 * CIM interrupt handler.
1571 */
1572static void cim_intr_handler(struct adapter *adapter)
1573{
1574 static const struct intr_info cim_intr_info[] = {
1575 {F_RSVDSPACEINT, "CIM reserved space write", -1, 1},
1576 {F_SDRAMRANGEINT, "CIM SDRAM address out of range", -1, 1},
1577 {F_FLASHRANGEINT, "CIM flash address out of range", -1, 1},
1578 {F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1},
1579 {F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1},
1580 {F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1},
1581 {F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1},
1582 {F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1},
1583 {F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1},
1584 {F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1},
1585 {F_BLKRDPLINT, "CIM block read from PL space", -1, 1},
1586 {F_BLKWRPLINT, "CIM block write to PL space", -1, 1},
b881955b
DLR		 1587 {F_DRAMPARERR, "CIM DRAM parity error", -1, 1},
1588 {F_ICACHEPARERR, "CIM icache parity error", -1, 1},
1589 {F_DCACHEPARERR, "CIM dcache parity error", -1, 1},
1590 {F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1},
1591 {F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1},
1592 {F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1},
1593 {F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1},
1594 {F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1},
1595 {F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1},
1596 {F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1},
1597 {F_ITAGPARERR, "CIM itag parity error", -1, 1},
1598 {F_DTAGPARERR, "CIM dtag parity error", -1, 1},
4d22de3e
DLR		 1599 {0}
1600 };
1601
1602 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff,
1603 cim_intr_info, NULL))
1604 t3_fatal_err(adapter);
1605}
1606
1607/*
1608 * ULP RX interrupt handler.
1609 */
1610static void ulprx_intr_handler(struct adapter *adapter)
1611{
1612 static const struct intr_info ulprx_intr_info[] = {
b881955b
DLR		 1613 {F_PARERRDATA, "ULP RX data parity error", -1, 1},
1614 {F_PARERRPCMD, "ULP RX command parity error", -1, 1},
1615 {F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1},
1616 {F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1},
1617 {F_ARBFPERR, "ULP RX ArbF parity error", -1, 1},
1618 {F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1},
1619 {F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1},
1620 {F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1},
4d22de3e
DLR		 1621 {0}
1622 };
1623
1624 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1625 ulprx_intr_info, NULL))
1626 t3_fatal_err(adapter);
1627}
1628
1629/*
1630 * ULP TX interrupt handler.
1631 */
1632static void ulptx_intr_handler(struct adapter *adapter)
1633{
1634 static const struct intr_info ulptx_intr_info[] = {
1635 {F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds",
1636 STAT_ULP_CH0_PBL_OOB, 0},
1637 {F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds",
1638 STAT_ULP_CH1_PBL_OOB, 0},
b881955b 1639 {0xfc, "ULP TX parity error", -1, 1},
4d22de3e
DLR		 1640 {0}
1641 };
1642
1643 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1644 ulptx_intr_info, adapter->irq_stats))
1645 t3_fatal_err(adapter);
1646}
1647
1648#define ICSPI_FRM_ERR (F_ICSPI0_FIFO2X_RX_FRAMING_ERROR | \
1649 F_ICSPI1_FIFO2X_RX_FRAMING_ERROR | F_ICSPI0_RX_FRAMING_ERROR | \
1650 F_ICSPI1_RX_FRAMING_ERROR | F_ICSPI0_TX_FRAMING_ERROR | \
1651 F_ICSPI1_TX_FRAMING_ERROR)
1652#define OESPI_FRM_ERR (F_OESPI0_RX_FRAMING_ERROR | \
1653 F_OESPI1_RX_FRAMING_ERROR | F_OESPI0_TX_FRAMING_ERROR | \
1654 F_OESPI1_TX_FRAMING_ERROR | F_OESPI0_OFIFO2X_TX_FRAMING_ERROR | \
1655 F_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1656
1657/*
1658 * PM TX interrupt handler.
1659 */
1660static void pmtx_intr_handler(struct adapter *adapter)
1661{
1662 static const struct intr_info pmtx_intr_info[] = {
1663 {F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1},
1664 {ICSPI_FRM_ERR, "PMTX ispi framing error", -1, 1},
1665 {OESPI_FRM_ERR, "PMTX ospi framing error", -1, 1},
1666 {V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR),
1667 "PMTX ispi parity error", -1, 1},
1668 {V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR),
1669 "PMTX ospi parity error", -1, 1},
1670 {0}
1671 };
1672
1673 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff,
1674 pmtx_intr_info, NULL))
1675 t3_fatal_err(adapter);
1676}
1677
1678#define IESPI_FRM_ERR (F_IESPI0_FIFO2X_RX_FRAMING_ERROR | \
1679 F_IESPI1_FIFO2X_RX_FRAMING_ERROR | F_IESPI0_RX_FRAMING_ERROR | \
1680 F_IESPI1_RX_FRAMING_ERROR | F_IESPI0_TX_FRAMING_ERROR | \
1681 F_IESPI1_TX_FRAMING_ERROR)
1682#define OCSPI_FRM_ERR (F_OCSPI0_RX_FRAMING_ERROR | \
1683 F_OCSPI1_RX_FRAMING_ERROR | F_OCSPI0_TX_FRAMING_ERROR | \
1684 F_OCSPI1_TX_FRAMING_ERROR | F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR | \
1685 F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1686
1687/*
1688 * PM RX interrupt handler.
1689 */
1690static void pmrx_intr_handler(struct adapter *adapter)
1691{
1692 static const struct intr_info pmrx_intr_info[] = {
1693 {F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1},
1694 {IESPI_FRM_ERR, "PMRX ispi framing error", -1, 1},
1695 {OCSPI_FRM_ERR, "PMRX ospi framing error", -1, 1},
1696 {V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR),
1697 "PMRX ispi parity error", -1, 1},
1698 {V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR),
1699 "PMRX ospi parity error", -1, 1},
1700 {0}
1701 };
1702
1703 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff,
1704 pmrx_intr_info, NULL))
1705 t3_fatal_err(adapter);
1706}
1707
1708/*
1709 * CPL switch interrupt handler.
1710 */
1711static void cplsw_intr_handler(struct adapter *adapter)
1712{
1713 static const struct intr_info cplsw_intr_info[] = {
b881955b
DLR		 1714 {F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1},
1715 {F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1},
4d22de3e
DLR		 1716 {F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1},
1717 {F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1},
1718 {F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1},
1719 {F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1},
1720 {0}
1721 };
1722
1723 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
1724 cplsw_intr_info, NULL))
1725 t3_fatal_err(adapter);
1726}
1727
1728/*
1729 * MPS interrupt handler.
1730 */
1731static void mps_intr_handler(struct adapter *adapter)
1732{
1733 static const struct intr_info mps_intr_info[] = {
1734 {0x1ff, "MPS parity error", -1, 1},
1735 {0}
1736 };
1737
1738 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff,
1739 mps_intr_info, NULL))
1740 t3_fatal_err(adapter);
1741}
1742
1743#define MC7_INTR_FATAL (F_UE | V_PE(M_PE) | F_AE)
1744
1745/*
1746 * MC7 interrupt handler.
1747 */
1748static void mc7_intr_handler(struct mc7 *mc7)
1749{
1750 struct adapter *adapter = mc7->adapter;
1751 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1752
1753 if (cause & F_CE) {
1754 mc7->stats.corr_err++;
1755 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, "
1756 "data 0x%x 0x%x 0x%x\n", mc7->name,
1757 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1758 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1759 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1760 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1761 }
1762
1763 if (cause & F_UE) {
1764 mc7->stats.uncorr_err++;
1765 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, "
1766 "data 0x%x 0x%x 0x%x\n", mc7->name,
1767 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1768 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1769 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1770 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1771 }
1772
1773 if (G_PE(cause)) {
1774 mc7->stats.parity_err++;
1775 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n",
1776 mc7->name, G_PE(cause));
1777 }
1778
1779 if (cause & F_AE) {
1780 u32 addr = 0;
1781
1782 if (adapter->params.rev > 0)
1783 addr = t3_read_reg(adapter,
1784 mc7->offset + A_MC7_ERR_ADDR);
1785 mc7->stats.addr_err++;
1786 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n",
1787 mc7->name, addr);
1788 }
1789
1790 if (cause & MC7_INTR_FATAL)
1791 t3_fatal_err(adapter);
1792
1793 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1794}
1795
1796#define XGM_INTR_FATAL (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1797 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR))
1798/*
1799 * XGMAC interrupt handler.
1800 */
1801static int mac_intr_handler(struct adapter *adap, unsigned int idx)
1802{
1803 struct cmac *mac = &adap2pinfo(adap, idx)->mac;
fc882196
DLR		 1804 /*
1805 * We mask out interrupt causes for which we're not taking interrupts.
1806 * This allows us to use polling logic to monitor some of the other
1807 * conditions when taking interrupts would impose too much load on the
1808 * system.
1809 */
1810 u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) &
1811 ~F_RXFIFO_OVERFLOW;
4d22de3e
DLR		 1812
1813 if (cause & V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR)) {
1814 mac->stats.tx_fifo_parity_err++;
1815 CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx);
1816 }
1817 if (cause & V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR)) {
1818 mac->stats.rx_fifo_parity_err++;
1819 CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx);
1820 }
1821 if (cause & F_TXFIFO_UNDERRUN)
1822 mac->stats.tx_fifo_urun++;
1823 if (cause & F_RXFIFO_OVERFLOW)
1824 mac->stats.rx_fifo_ovfl++;
1825 if (cause & V_SERDES_LOS(M_SERDES_LOS))
1826 mac->stats.serdes_signal_loss++;
1827 if (cause & F_XAUIPCSCTCERR)
1828 mac->stats.xaui_pcs_ctc_err++;
1829 if (cause & F_XAUIPCSALIGNCHANGE)
1830 mac->stats.xaui_pcs_align_change++;
bf792094
DLR		 1831 if (cause & F_XGM_INT) {
1832 t3_set_reg_field(adap,
1833 A_XGM_INT_ENABLE + mac->offset,
1834 F_XGM_INT, 0);
1835 mac->stats.link_faults++;
1836
1837 t3_os_link_fault_handler(adap, idx);
1838 }
4d22de3e
DLR		 1839
1840 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
bf792094 1841
4d22de3e
DLR		 1842 if (cause & XGM_INTR_FATAL)
1843 t3_fatal_err(adap);
bf792094 1844
4d22de3e
DLR		 1845 return cause != 0;
1846}
1847
1848/*
1849 * Interrupt handler for PHY events.
1850 */
1851int t3_phy_intr_handler(struct adapter *adapter)
1852{
4d22de3e
DLR		 1853 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1854
1855 for_each_port(adapter, i) {
1ca03cbc
DLR		 1856 struct port_info *p = adap2pinfo(adapter, i);
1857
04497982 1858 if (!(p->phy.caps & SUPPORTED_IRQ))
1ca03cbc
DLR		 1859 continue;
1860
f231e0a5 1861 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) {
1ca03cbc 1862 int phy_cause = p->phy.ops->intr_handler(&p->phy);
4d22de3e
DLR		 1863
1864 if (phy_cause & cphy_cause_link_change)
1865 t3_link_changed(adapter, i);
1866 if (phy_cause & cphy_cause_fifo_error)
1ca03cbc 1867 p->phy.fifo_errors++;
1e882025
DLR		 1868 if (phy_cause & cphy_cause_module_change)
1869 t3_os_phymod_changed(adapter, i);
4d22de3e
DLR		 1870 }
1871 }
1872
1873 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1874 return 0;
1875}
1876
1877/*
1878 * T3 slow path (non-data) interrupt handler.
1879 */
1880int t3_slow_intr_handler(struct adapter *adapter)
1881{
1882 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1883
1884 cause &= adapter->slow_intr_mask;
1885 if (!cause)
1886 return 0;
1887 if (cause & F_PCIM0) {
1888 if (is_pcie(adapter))
1889 pcie_intr_handler(adapter);
1890 else
1891 pci_intr_handler(adapter);
1892 }
1893 if (cause & F_SGE3)
1894 t3_sge_err_intr_handler(adapter);
1895 if (cause & F_MC7_PMRX)
1896 mc7_intr_handler(&adapter->pmrx);
1897 if (cause & F_MC7_PMTX)
1898 mc7_intr_handler(&adapter->pmtx);
1899 if (cause & F_MC7_CM)
1900 mc7_intr_handler(&adapter->cm);
1901 if (cause & F_CIM)
1902 cim_intr_handler(adapter);
1903 if (cause & F_TP1)
1904 tp_intr_handler(adapter);
1905 if (cause & F_ULP2_RX)
1906 ulprx_intr_handler(adapter);
1907 if (cause & F_ULP2_TX)
1908 ulptx_intr_handler(adapter);
1909 if (cause & F_PM1_RX)
1910 pmrx_intr_handler(adapter);
1911 if (cause & F_PM1_TX)
1912 pmtx_intr_handler(adapter);
1913 if (cause & F_CPL_SWITCH)
1914 cplsw_intr_handler(adapter);
1915 if (cause & F_MPS0)
1916 mps_intr_handler(adapter);
1917 if (cause & F_MC5A)
1918 t3_mc5_intr_handler(&adapter->mc5);
1919 if (cause & F_XGMAC0_0)
1920 mac_intr_handler(adapter, 0);
1921 if (cause & F_XGMAC0_1)
1922 mac_intr_handler(adapter, 1);
1923 if (cause & F_T3DBG)
1924 t3_os_ext_intr_handler(adapter);
1925
1926 /* Clear the interrupts just processed. */
1927 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1928 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1929 return 1;
1930}
1931
f231e0a5
DLR		 1932static unsigned int calc_gpio_intr(struct adapter *adap)
1933{
1934 unsigned int i, gpi_intr = 0;
1935
1936 for_each_port(adap, i)
1937 if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&
1938 adapter_info(adap)->gpio_intr[i])
1939 gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i];
1940 return gpi_intr;
1941}
1942
4d22de3e
DLR		 1943/**
1944 * t3_intr_enable - enable interrupts
1945 * @adapter: the adapter whose interrupts should be enabled
1946 *
1947 * Enable interrupts by setting the interrupt enable registers of the
1948 * various HW modules and then enabling the top-level interrupt
1949 * concentrator.
1950 */
1951void t3_intr_enable(struct adapter *adapter)
1952{
1953 static const struct addr_val_pair intr_en_avp[] = {
1954 {A_SG_INT_ENABLE, SGE_INTR_MASK},
1955 {A_MC7_INT_ENABLE, MC7_INTR_MASK},
1956 {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
1957 MC7_INTR_MASK},
1958 {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
1959 MC7_INTR_MASK},
1960 {A_MC5_DB_INT_ENABLE, MC5_INTR_MASK},
1961 {A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK},
4d22de3e
DLR		 1962 {A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK},
1963 {A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK},
1964 {A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK},
1965 {A_MPS_INT_ENABLE, MPS_INTR_MASK},
1966 };
1967
1968 adapter->slow_intr_mask = PL_INTR_MASK;
1969
1970 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
a2604be5
DLR		 1971 t3_write_reg(adapter, A_TP_INT_ENABLE,
1972 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff);
4d22de3e
DLR		 1973
1974 if (adapter->params.rev > 0) {
1975 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1976 CPLSW_INTR_MASK | F_CIM_OVFL_ERROR);
1977 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1978 ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
1979 F_PBL_BOUND_ERR_CH1);
1980 } else {
1981 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1982 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1983 }
1984
f231e0a5
DLR		 1985 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
1986
4d22de3e
DLR		 1987 if (is_pcie(adapter))
1988 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1989 else
1990 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1991 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1992 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1993}
1994
1995/**
1996 * t3_intr_disable - disable a card's interrupts
1997 * @adapter: the adapter whose interrupts should be disabled
1998 *
1999 * Disable interrupts. We only disable the top-level interrupt
2000 * concentrator and the SGE data interrupts.
2001 */
2002void t3_intr_disable(struct adapter *adapter)
2003{
2004 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
2005 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
2006 adapter->slow_intr_mask = 0;
2007}
2008
2009/**
2010 * t3_intr_clear - clear all interrupts
2011 * @adapter: the adapter whose interrupts should be cleared
2012 *
2013 * Clears all interrupts.
2014 */
2015void t3_intr_clear(struct adapter *adapter)
2016{
2017 static const unsigned int cause_reg_addr[] = {
2018 A_SG_INT_CAUSE,
2019 A_SG_RSPQ_FL_STATUS,
2020 A_PCIX_INT_CAUSE,
2021 A_MC7_INT_CAUSE,
2022 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
2023 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
2024 A_CIM_HOST_INT_CAUSE,
2025 A_TP_INT_CAUSE,
2026 A_MC5_DB_INT_CAUSE,
2027 A_ULPRX_INT_CAUSE,
2028 A_ULPTX_INT_CAUSE,
2029 A_CPL_INTR_CAUSE,
2030 A_PM1_TX_INT_CAUSE,
2031 A_PM1_RX_INT_CAUSE,
2032 A_MPS_INT_CAUSE,
2033 A_T3DBG_INT_CAUSE,
2034 };
2035 unsigned int i;
2036
2037 /* Clear PHY and MAC interrupts for each port. */
2038 for_each_port(adapter, i)
2039 t3_port_intr_clear(adapter, i);
2040
2041 for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i)
2042 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
2043
3eea3337
DLR		 2044 if (is_pcie(adapter))
2045 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff);
4d22de3e
DLR		 2046 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
2047 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
2048}
2049
bf792094
DLR		 2050void t3_xgm_intr_enable(struct adapter *adapter, int idx)
2051{
2052 struct port_info *pi = adap2pinfo(adapter, idx);
2053
2054 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset,
2055 XGM_EXTRA_INTR_MASK);
2056}
2057
2058void t3_xgm_intr_disable(struct adapter *adapter, int idx)
2059{
2060 struct port_info *pi = adap2pinfo(adapter, idx);
2061
2062 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset,
2063 0x7ff);
2064}
2065
4d22de3e
DLR		 2066/**
2067 * t3_port_intr_enable - enable port-specific interrupts
2068 * @adapter: associated adapter
2069 * @idx: index of port whose interrupts should be enabled
2070 *
2071 * Enable port-specific (i.e., MAC and PHY) interrupts for the given
2072 * adapter port.
2073 */
2074void t3_port_intr_enable(struct adapter *adapter, int idx)
2075{
2076 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
2077
2078 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK);
2079 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
2080 phy->ops->intr_enable(phy);
2081}
2082
2083/**
2084 * t3_port_intr_disable - disable port-specific interrupts
2085 * @adapter: associated adapter
2086 * @idx: index of port whose interrupts should be disabled
2087 *
2088 * Disable port-specific (i.e., MAC and PHY) interrupts for the given
2089 * adapter port.
2090 */
2091void t3_port_intr_disable(struct adapter *adapter, int idx)
2092{
2093 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
2094
2095 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0);
2096 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
2097 phy->ops->intr_disable(phy);
2098}
2099
2100/**
2101 * t3_port_intr_clear - clear port-specific interrupts
2102 * @adapter: associated adapter
2103 * @idx: index of port whose interrupts to clear
2104 *
2105 * Clear port-specific (i.e., MAC and PHY) interrupts for the given
2106 * adapter port.
2107 */
2108void t3_port_intr_clear(struct adapter *adapter, int idx)
2109{
2110 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
2111
2112 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff);
2113 t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */
2114 phy->ops->intr_clear(phy);
2115}
2116
bb9366af
DLR		 2117#define SG_CONTEXT_CMD_ATTEMPTS 100
2118
4d22de3e
DLR		 2119/**
2120 * t3_sge_write_context - write an SGE context
2121 * @adapter: the adapter
2122 * @id: the context id
2123 * @type: the context type
2124 *
2125 * Program an SGE context with the values already loaded in the
2126 * CONTEXT_DATA? registers.
2127 */
2128static int t3_sge_write_context(struct adapter *adapter, unsigned int id,
2129 unsigned int type)
2130{
2131 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
2132 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
2133 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
2134 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2135 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2136 V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
2137 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
bb9366af 2138 0, SG_CONTEXT_CMD_ATTEMPTS, 1);
4d22de3e
DLR		 2139}
2140
b881955b
DLR		 2141static int clear_sge_ctxt(struct adapter *adap, unsigned int id,
2142 unsigned int type)
2143{
2144 t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
2145 t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
2146 t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
2147 t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
2148 return t3_sge_write_context(adap, id, type);
2149}
2150
4d22de3e
DLR		 2151/**
2152 * t3_sge_init_ecntxt - initialize an SGE egress context
2153 * @adapter: the adapter to configure
2154 * @id: the context id
2155 * @gts_enable: whether to enable GTS for the context
2156 * @type: the egress context type
2157 * @respq: associated response queue
2158 * @base_addr: base address of queue
2159 * @size: number of queue entries
2160 * @token: uP token
2161 * @gen: initial generation value for the context
2162 * @cidx: consumer pointer
2163 *
2164 * Initialize an SGE egress context and make it ready for use. If the
2165 * platform allows concurrent context operations, the caller is
2166 * responsible for appropriate locking.
2167 */
2168int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
2169 enum sge_context_type type, int respq, u64 base_addr,
2170 unsigned int size, unsigned int token, int gen,
2171 unsigned int cidx)
2172{
2173 unsigned int credits = type == SGE_CNTXT_OFLD ? 0 : FW_WR_NUM;
2174
2175 if (base_addr & 0xfff) /* must be 4K aligned */
2176 return -EINVAL;
2177 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2178 return -EBUSY;
2179
2180 base_addr >>= 12;
2181 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
2182 V_EC_CREDITS(credits) | V_EC_GTS(gts_enable));
2183 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
2184 V_EC_BASE_LO(base_addr & 0xffff));
2185 base_addr >>= 16;
2186 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr);
2187 base_addr >>= 32;
2188 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2189 V_EC_BASE_HI(base_addr & 0xf) | V_EC_RESPQ(respq) |
2190 V_EC_TYPE(type) | V_EC_GEN(gen) | V_EC_UP_TOKEN(token) |
2191 F_EC_VALID);
2192 return t3_sge_write_context(adapter, id, F_EGRESS);
2193}
2194
2195/**
2196 * t3_sge_init_flcntxt - initialize an SGE free-buffer list context
2197 * @adapter: the adapter to configure
2198 * @id: the context id
2199 * @gts_enable: whether to enable GTS for the context
2200 * @base_addr: base address of queue
2201 * @size: number of queue entries
2202 * @bsize: size of each buffer for this queue
2203 * @cong_thres: threshold to signal congestion to upstream producers
2204 * @gen: initial generation value for the context
2205 * @cidx: consumer pointer
2206 *
2207 * Initialize an SGE free list context and make it ready for use. The
2208 * caller is responsible for ensuring only one context operation occurs
2209 * at a time.
2210 */
2211int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
2212 int gts_enable, u64 base_addr, unsigned int size,
2213 unsigned int bsize, unsigned int cong_thres, int gen,
2214 unsigned int cidx)
2215{
2216 if (base_addr & 0xfff) /* must be 4K aligned */
2217 return -EINVAL;
2218 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2219 return -EBUSY;
2220
2221 base_addr >>= 12;
2222 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr);
2223 base_addr >>= 32;
2224 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
2225 V_FL_BASE_HI((u32) base_addr) |
2226 V_FL_INDEX_LO(cidx & M_FL_INDEX_LO));
2227 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
2228 V_FL_GEN(gen) | V_FL_INDEX_HI(cidx >> 12) |
2229 V_FL_ENTRY_SIZE_LO(bsize & M_FL_ENTRY_SIZE_LO));
2230 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2231 V_FL_ENTRY_SIZE_HI(bsize >> (32 - S_FL_ENTRY_SIZE_LO)) |
2232 V_FL_CONG_THRES(cong_thres) | V_FL_GTS(gts_enable));
2233 return t3_sge_write_context(adapter, id, F_FREELIST);
2234}
2235
2236/**
2237 * t3_sge_init_rspcntxt - initialize an SGE response queue context
2238 * @adapter: the adapter to configure
2239 * @id: the context id
2240 * @irq_vec_idx: MSI-X interrupt vector index, 0 if no MSI-X, -1 if no IRQ
2241 * @base_addr: base address of queue
2242 * @size: number of queue entries
2243 * @fl_thres: threshold for selecting the normal or jumbo free list
2244 * @gen: initial generation value for the context
2245 * @cidx: consumer pointer
2246 *
2247 * Initialize an SGE response queue context and make it ready for use.
2248 * The caller is responsible for ensuring only one context operation
2249 * occurs at a time.
2250 */
2251int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
2252 int irq_vec_idx, u64 base_addr, unsigned int size,
2253 unsigned int fl_thres, int gen, unsigned int cidx)
2254{
2255 unsigned int intr = 0;
2256
2257 if (base_addr & 0xfff) /* must be 4K aligned */
2258 return -EINVAL;
2259 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2260 return -EBUSY;
2261
2262 base_addr >>= 12;
2263 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
2264 V_CQ_INDEX(cidx));
2265 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
2266 base_addr >>= 32;
2267 if (irq_vec_idx >= 0)
2268 intr = V_RQ_MSI_VEC(irq_vec_idx) | F_RQ_INTR_EN;
2269 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2270 V_CQ_BASE_HI((u32) base_addr) | intr | V_RQ_GEN(gen));
2271 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
2272 return t3_sge_write_context(adapter, id, F_RESPONSEQ);
2273}
2274
2275/**
2276 * t3_sge_init_cqcntxt - initialize an SGE completion queue context
2277 * @adapter: the adapter to configure
2278 * @id: the context id
2279 * @base_addr: base address of queue
2280 * @size: number of queue entries
2281 * @rspq: response queue for async notifications
2282 * @ovfl_mode: CQ overflow mode
2283 * @credits: completion queue credits
2284 * @credit_thres: the credit threshold
2285 *
2286 * Initialize an SGE completion queue context and make it ready for use.
2287 * The caller is responsible for ensuring only one context operation
2288 * occurs at a time.
2289 */
2290int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
2291 unsigned int size, int rspq, int ovfl_mode,
2292 unsigned int credits, unsigned int credit_thres)
2293{
2294 if (base_addr & 0xfff) /* must be 4K aligned */
2295 return -EINVAL;
2296 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2297 return -EBUSY;
2298
2299 base_addr >>= 12;
2300 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
2301 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
2302 base_addr >>= 32;
2303 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2304 V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) |
1c17ae8a
DLR		 2305 V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode) |
2306 V_CQ_ERR(ovfl_mode));
4d22de3e
DLR		 2307 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2308 V_CQ_CREDIT_THRES(credit_thres));
2309 return t3_sge_write_context(adapter, id, F_CQ);
2310}
2311
2312/**
2313 * t3_sge_enable_ecntxt - enable/disable an SGE egress context
2314 * @adapter: the adapter
2315 * @id: the egress context id
2316 * @enable: enable (1) or disable (0) the context
2317 *
2318 * Enable or disable an SGE egress context. The caller is responsible for
2319 * ensuring only one context operation occurs at a time.
2320 */
2321int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable)
2322{
2323 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2324 return -EBUSY;
2325
2326 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2327 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2328 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2329 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
2330 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
2331 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2332 V_CONTEXT_CMD_OPCODE(1) | F_EGRESS | V_CONTEXT(id));
2333 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
bb9366af 2334 0, SG_CONTEXT_CMD_ATTEMPTS, 1);
4d22de3e
DLR		 2335}
2336
2337/**
2338 * t3_sge_disable_fl - disable an SGE free-buffer list
2339 * @adapter: the adapter
2340 * @id: the free list context id
2341 *
2342 * Disable an SGE free-buffer list. The caller is responsible for
2343 * ensuring only one context operation occurs at a time.
2344 */
2345int t3_sge_disable_fl(struct adapter *adapter, unsigned int id)
2346{
2347 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2348 return -EBUSY;
2349
2350 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2351 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2352 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
2353 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2354 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
2355 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2356 V_CONTEXT_CMD_OPCODE(1) | F_FREELIST | V_CONTEXT(id));
2357 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
bb9366af 2358 0, SG_CONTEXT_CMD_ATTEMPTS, 1);
4d22de3e
DLR		 2359}
2360
2361/**
2362 * t3_sge_disable_rspcntxt - disable an SGE response queue
2363 * @adapter: the adapter
2364 * @id: the response queue context id
2365 *
2366 * Disable an SGE response queue. The caller is responsible for
2367 * ensuring only one context operation occurs at a time.
2368 */
2369int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id)
2370{
2371 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2372 return -EBUSY;
2373
2374 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2375 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2376 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2377 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2378 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2379 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2380 V_CONTEXT_CMD_OPCODE(1) | F_RESPONSEQ | V_CONTEXT(id));
2381 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
bb9366af 2382 0, SG_CONTEXT_CMD_ATTEMPTS, 1);
4d22de3e
DLR		 2383}
2384
2385/**
2386 * t3_sge_disable_cqcntxt - disable an SGE completion queue
2387 * @adapter: the adapter
2388 * @id: the completion queue context id
2389 *
2390 * Disable an SGE completion queue. The caller is responsible for
2391 * ensuring only one context operation occurs at a time.
2392 */
2393int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id)
2394{
2395 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2396 return -EBUSY;
2397
2398 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2399 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2400 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2401 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2402 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2403 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2404 V_CONTEXT_CMD_OPCODE(1) | F_CQ | V_CONTEXT(id));
2405 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
bb9366af 2406 0, SG_CONTEXT_CMD_ATTEMPTS, 1);
4d22de3e
DLR		 2407}
2408
2409/**
2410 * t3_sge_cqcntxt_op - perform an operation on a completion queue context
2411 * @adapter: the adapter
2412 * @id: the context id
2413 * @op: the operation to perform
2414 *
2415 * Perform the selected operation on an SGE completion queue context.
2416 * The caller is responsible for ensuring only one context operation
2417 * occurs at a time.
2418 */
2419int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
2420 unsigned int credits)
2421{
2422 u32 val;
2423
2424 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2425 return -EBUSY;
2426
2427 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2428 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2429 V_CONTEXT(id) | F_CQ);
2430 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
bb9366af 2431 0, SG_CONTEXT_CMD_ATTEMPTS, 1, &val))
4d22de3e
DLR		 2432 return -EIO;
2433
2434 if (op >= 2 && op < 7) {
2435 if (adapter->params.rev > 0)
2436 return G_CQ_INDEX(val);
2437
2438 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2439 V_CONTEXT_CMD_OPCODE(0) | F_CQ | V_CONTEXT(id));
2440 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD,
bb9366af
DLR		 2441 F_CONTEXT_CMD_BUSY, 0,
2442 SG_CONTEXT_CMD_ATTEMPTS, 1))
4d22de3e
DLR		 2443 return -EIO;
2444 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2445 }
2446 return 0;
2447}
2448
2449/**
2450 * t3_sge_read_context - read an SGE context
2451 * @type: the context type
2452 * @adapter: the adapter
2453 * @id: the context id
2454 * @data: holds the retrieved context
2455 *
2456 * Read an SGE egress context. The caller is responsible for ensuring
2457 * only one context operation occurs at a time.
2458 */
2459static int t3_sge_read_context(unsigned int type, struct adapter *adapter,
2460 unsigned int id, u32 data[4])
2461{
2462 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2463 return -EBUSY;
2464
2465 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2466 V_CONTEXT_CMD_OPCODE(0) | type | V_CONTEXT(id));
2467 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0,
bb9366af 2468 SG_CONTEXT_CMD_ATTEMPTS, 1))
4d22de3e
DLR		 2469 return -EIO;
2470 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
2471 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
2472 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2);
2473 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3);
2474 return 0;
2475}
2476
2477/**
2478 * t3_sge_read_ecntxt - read an SGE egress context
2479 * @adapter: the adapter
2480 * @id: the context id
2481 * @data: holds the retrieved context
2482 *
2483 * Read an SGE egress context. The caller is responsible for ensuring
2484 * only one context operation occurs at a time.
2485 */
2486int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4])
2487{
2488 if (id >= 65536)
2489 return -EINVAL;
2490 return t3_sge_read_context(F_EGRESS, adapter, id, data);
2491}
2492
2493/**
2494 * t3_sge_read_cq - read an SGE CQ context
2495 * @adapter: the adapter
2496 * @id: the context id
2497 * @data: holds the retrieved context
2498 *
2499 * Read an SGE CQ context. The caller is responsible for ensuring
2500 * only one context operation occurs at a time.
2501 */
2502int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4])
2503{
2504 if (id >= 65536)
2505 return -EINVAL;
2506 return t3_sge_read_context(F_CQ, adapter, id, data);
2507}
2508
2509/**
2510 * t3_sge_read_fl - read an SGE free-list context
2511 * @adapter: the adapter
2512 * @id: the context id
2513 * @data: holds the retrieved context
2514 *
2515 * Read an SGE free-list context. The caller is responsible for ensuring
2516 * only one context operation occurs at a time.
2517 */
2518int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4])
2519{
2520 if (id >= SGE_QSETS * 2)
2521 return -EINVAL;
2522 return t3_sge_read_context(F_FREELIST, adapter, id, data);
2523}
2524
2525/**
2526 * t3_sge_read_rspq - read an SGE response queue context
2527 * @adapter: the adapter
2528 * @id: the context id
2529 * @data: holds the retrieved context
2530 *
2531 * Read an SGE response queue context. The caller is responsible for
2532 * ensuring only one context operation occurs at a time.
2533 */
2534int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4])
2535{
2536 if (id >= SGE_QSETS)
2537 return -EINVAL;
2538 return t3_sge_read_context(F_RESPONSEQ, adapter, id, data);
2539}
2540
2541/**
2542 * t3_config_rss - configure Rx packet steering
2543 * @adapter: the adapter
2544 * @rss_config: RSS settings (written to TP_RSS_CONFIG)
2545 * @cpus: values for the CPU lookup table (0xff terminated)
2546 * @rspq: values for the response queue lookup table (0xffff terminated)
2547 *
2548 * Programs the receive packet steering logic. @cpus and @rspq provide
2549 * the values for the CPU and response queue lookup tables. If they
2550 * provide fewer values than the size of the tables the supplied values
2551 * are used repeatedly until the tables are fully populated.
2552 */
2553void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
2554 const u8 * cpus, const u16 *rspq)
2555{
2556 int i, j, cpu_idx = 0, q_idx = 0;
2557
2558 if (cpus)
2559 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2560 u32 val = i << 16;
2561
2562 for (j = 0; j < 2; ++j) {
2563 val |= (cpus[cpu_idx++] & 0x3f) << (8 * j);
2564 if (cpus[cpu_idx] == 0xff)
2565 cpu_idx = 0;
2566 }
2567 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2568 }
2569
2570 if (rspq)
2571 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2572 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2573 (i << 16) | rspq[q_idx++]);
2574 if (rspq[q_idx] == 0xffff)
2575 q_idx = 0;
2576 }
2577
2578 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2579}
2580
2581/**
2582 * t3_read_rss - read the contents of the RSS tables
2583 * @adapter: the adapter
2584 * @lkup: holds the contents of the RSS lookup table
2585 * @map: holds the contents of the RSS map table
2586 *
2587 * Reads the contents of the receive packet steering tables.
2588 */
2589int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map)
2590{
2591 int i;
2592 u32 val;
2593
2594 if (lkup)
2595 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2596 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE,
2597 0xffff0000 | i);
2598 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE);
2599 if (!(val & 0x80000000))
2600 return -EAGAIN;
2601 *lkup++ = val;
2602 *lkup++ = (val >> 8);
2603 }
2604
2605 if (map)
2606 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2607 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2608 0xffff0000 | i);
2609 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE);
2610 if (!(val & 0x80000000))
2611 return -EAGAIN;
2612 *map++ = val;
2613 }
2614 return 0;
2615}
2616
2617/**
2618 * t3_tp_set_offload_mode - put TP in NIC/offload mode
2619 * @adap: the adapter
2620 * @enable: 1 to select offload mode, 0 for regular NIC
2621 *
2622 * Switches TP to NIC/offload mode.
2623 */
2624void t3_tp_set_offload_mode(struct adapter *adap, int enable)
2625{
2626 if (is_offload(adap) || !enable)
2627 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2628 V_NICMODE(!enable));
2629}
2630
2631/**
2632 * pm_num_pages - calculate the number of pages of the payload memory
2633 * @mem_size: the size of the payload memory
2634 * @pg_size: the size of each payload memory page
2635 *
2636 * Calculate the number of pages, each of the given size, that fit in a
2637 * memory of the specified size, respecting the HW requirement that the
2638 * number of pages must be a multiple of 24.
2639 */
2640static inline unsigned int pm_num_pages(unsigned int mem_size,
2641 unsigned int pg_size)
2642{
2643 unsigned int n = mem_size / pg_size;
2644
2645 return n - n % 24;
2646}
2647
2648#define mem_region(adap, start, size, reg) \
2649 t3_write_reg((adap), A_ ## reg, (start)); \
2650 start += size
2651
b881955b 2652/**
4d22de3e
DLR		 2653 * partition_mem - partition memory and configure TP memory settings
2654 * @adap: the adapter
2655 * @p: the TP parameters
2656 *
2657 * Partitions context and payload memory and configures TP's memory
2658 * registers.
2659 */
2660static void partition_mem(struct adapter *adap, const struct tp_params *p)
2661{
2662 unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5);
2663 unsigned int timers = 0, timers_shift = 22;
2664
2665 if (adap->params.rev > 0) {
2666 if (tids <= 16 * 1024) {
2667 timers = 1;
2668 timers_shift = 16;
2669 } else if (tids <= 64 * 1024) {
2670 timers = 2;
2671 timers_shift = 18;
2672 } else if (tids <= 256 * 1024) {
2673 timers = 3;
2674 timers_shift = 20;
2675 }
2676 }
2677
2678 t3_write_reg(adap, A_TP_PMM_SIZE,
2679 p->chan_rx_size | (p->chan_tx_size >> 16));
2680
2681 t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
2682 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
2683 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
2684 t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
2685 V_TXDATAACKIDX(fls(p->tx_pg_size) - 12));
2686
2687 t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
2688 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
2689 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
2690
2691 pstructs = p->rx_num_pgs + p->tx_num_pgs;
2692 /* Add a bit of headroom and make multiple of 24 */
2693 pstructs += 48;
2694 pstructs -= pstructs % 24;
2695 t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
2696
2697 m = tids * TCB_SIZE;
2698 mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR);
2699 mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR);
2700 t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
2701 m += ((p->ntimer_qs - 1) << timers_shift) + (1 << 22);
2702 mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE);
2703 mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE);
2704 mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE);
2705 mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE);
2706
2707 m = (m + 4095) & ~0xfff;
2708 t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
2709 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
2710
2711 tids = (p->cm_size - m - (3 << 20)) / 3072 - 32;
2712 m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
2713 adap->params.mc5.nfilters - adap->params.mc5.nroutes;
2714 if (tids < m)
2715 adap->params.mc5.nservers += m - tids;
2716}
2717
2718static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr,
2719 u32 val)
2720{
2721 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2722 t3_write_reg(adap, A_TP_PIO_DATA, val);
2723}
2724
2725static void tp_config(struct adapter *adap, const struct tp_params *p)
2726{
4d22de3e
DLR		 2727 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2728 F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD |
2729 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2730 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2731 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
8a9fab22 2732 V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
4d22de3e
DLR		 2733 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2734 V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
2735 V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
2736 F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
b881955b 2737 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
4d22de3e
DLR		 2738 F_IPV6ENABLE | F_NICMODE);
2739 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2740 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
8a9fab22
DLR		 2741 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2742 adap->params.rev > 0 ? F_ENABLEESND :
2743 F_T3A_ENABLEESND);
4d22de3e 2744
3b1d307b 2745 t3_set_reg_field(adap, A_TP_PC_CONFIG,
8a9fab22
DLR		 2746 F_ENABLEEPCMDAFULL,
2747 F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
2748 F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
b881955b
DLR		 2749 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
2750 F_ENABLEIPV6RSS | F_ENABLENONOFDTNLSYN |
2751 F_ENABLEARPMISS | F_DISBLEDAPARBIT0);
8a9fab22
DLR		 2752 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2753 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2eab17ab 2754
4d22de3e
DLR		 2755 if (adap->params.rev > 0) {
2756 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2757 t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,
2758 F_TXPACEAUTO);
2759 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2760 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT);
2761 } else
2762 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2763
a2604be5
DLR		 2764 if (adap->params.rev == T3_REV_C)
2765 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2766 V_TABLELATENCYDELTA(M_TABLELATENCYDELTA),
2767 V_TABLELATENCYDELTA(4));
2768
8a9fab22
DLR		 2769 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2770 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2771 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2772 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
4d22de3e
DLR		 2773}
2774
2775/* Desired TP timer resolution in usec */
2776#define TP_TMR_RES 50
2777
2778/* TCP timer values in ms */
2779#define TP_DACK_TIMER 50
2780#define TP_RTO_MIN 250
2781
2782/**
2783 * tp_set_timers - set TP timing parameters
2784 * @adap: the adapter to set
2785 * @core_clk: the core clock frequency in Hz
2786 *
2787 * Set TP's timing parameters, such as the various timer resolutions and
2788 * the TCP timer values.
2789 */
2790static void tp_set_timers(struct adapter *adap, unsigned int core_clk)
2791{
2792 unsigned int tre = fls(core_clk / (1000000 / TP_TMR_RES)) - 1;
2793 unsigned int dack_re = fls(core_clk / 5000) - 1; /* 200us */
2794 unsigned int tstamp_re = fls(core_clk / 1000); /* 1ms, at least */
2795 unsigned int tps = core_clk >> tre;
2796
2797 t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
2798 V_DELAYEDACKRESOLUTION(dack_re) |
2799 V_TIMESTAMPRESOLUTION(tstamp_re));
2800 t3_write_reg(adap, A_TP_DACK_TIMER,
2801 (core_clk >> dack_re) / (1000 / TP_DACK_TIMER));
2802 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
2803 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
2804 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
2805 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
2806 t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
2807 V_RXTSHIFTMAXR1(4) | V_RXTSHIFTMAXR2(15) |
2808 V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) |
2809 V_KEEPALIVEMAX(9));
2810
2811#define SECONDS * tps
2812
2813 t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS);
2814 t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
2815 t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
2816 t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
2817 t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
2818 t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
2819 t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
2820 t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
2821 t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
2822
2823#undef SECONDS
2824}
2825
2826/**
2827 * t3_tp_set_coalescing_size - set receive coalescing size
2828 * @adap: the adapter
2829 * @size: the receive coalescing size
2830 * @psh: whether a set PSH bit should deliver coalesced data
2831 *
2832 * Set the receive coalescing size and PSH bit handling.
2833 */
2834int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh)
2835{
2836 u32 val;
2837
2838 if (size > MAX_RX_COALESCING_LEN)
2839 return -EINVAL;
2840
2841 val = t3_read_reg(adap, A_TP_PARA_REG3);
2842 val &= ~(F_RXCOALESCEENABLE | F_RXCOALESCEPSHEN);
2843
2844 if (size) {
2845 val |= F_RXCOALESCEENABLE;
2846 if (psh)
2847 val |= F_RXCOALESCEPSHEN;
8a9fab22 2848 size = min(MAX_RX_COALESCING_LEN, size);
4d22de3e
DLR		 2849 t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
2850 V_MAXRXDATA(MAX_RX_COALESCING_LEN));
2851 }
2852 t3_write_reg(adap, A_TP_PARA_REG3, val);
2853 return 0;
2854}
2855
2856/**
2857 * t3_tp_set_max_rxsize - set the max receive size
2858 * @adap: the adapter
2859 * @size: the max receive size
2860 *
2861 * Set TP's max receive size. This is the limit that applies when
2862 * receive coalescing is disabled.
2863 */
2864void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size)
2865{
2866 t3_write_reg(adap, A_TP_PARA_REG7,
2867 V_PMMAXXFERLEN0(size) | V_PMMAXXFERLEN1(size));
2868}
2869
7b9b0943 2870static void init_mtus(unsigned short mtus[])
4d22de3e
DLR		 2871{
2872 /*
2873 * See draft-mathis-plpmtud-00.txt for the values. The min is 88 so
2874 * it can accomodate max size TCP/IP headers when SACK and timestamps
2875 * are enabled and still have at least 8 bytes of payload.
2876 */
75758e8a 2877 mtus[0] = 88;
8a9fab22
DLR		 2878 mtus[1] = 88;
2879 mtus[2] = 256;
2880 mtus[3] = 512;
2881 mtus[4] = 576;
4d22de3e
DLR		 2882 mtus[5] = 1024;
2883 mtus[6] = 1280;
2884 mtus[7] = 1492;
2885 mtus[8] = 1500;
2886 mtus[9] = 2002;
2887 mtus[10] = 2048;
2888 mtus[11] = 4096;
2889 mtus[12] = 4352;
2890 mtus[13] = 8192;
2891 mtus[14] = 9000;
2892 mtus[15] = 9600;
2893}
2894
2895/*
2896 * Initial congestion control parameters.
2897 */
7b9b0943 2898static void init_cong_ctrl(unsigned short *a, unsigned short *b)
4d22de3e
DLR		 2899{
2900 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2901 a[9] = 2;
2902 a[10] = 3;
2903 a[11] = 4;
2904 a[12] = 5;
2905 a[13] = 6;
2906 a[14] = 7;
2907 a[15] = 8;
2908 a[16] = 9;
2909 a[17] = 10;
2910 a[18] = 14;
2911 a[19] = 17;
2912 a[20] = 21;
2913 a[21] = 25;
2914 a[22] = 30;
2915 a[23] = 35;
2916 a[24] = 45;
2917 a[25] = 60;
2918 a[26] = 80;
2919 a[27] = 100;
2920 a[28] = 200;
2921 a[29] = 300;
2922 a[30] = 400;
2923 a[31] = 500;
2924
2925 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2926 b[9] = b[10] = 1;
2927 b[11] = b[12] = 2;
2928 b[13] = b[14] = b[15] = b[16] = 3;
2929 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2930 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2931 b[28] = b[29] = 6;
2932 b[30] = b[31] = 7;
2933}
2934
2935/* The minimum additive increment value for the congestion control table */
2936#define CC_MIN_INCR 2U
2937
2938/**
2939 * t3_load_mtus - write the MTU and congestion control HW tables
2940 * @adap: the adapter
2941 * @mtus: the unrestricted values for the MTU table
2942 * @alphs: the values for the congestion control alpha parameter
2943 * @beta: the values for the congestion control beta parameter
2944 * @mtu_cap: the maximum permitted effective MTU
2945 *
2946 * Write the MTU table with the supplied MTUs capping each at &mtu_cap.
2947 * Update the high-speed congestion control table with the supplied alpha,
2948 * beta, and MTUs.
2949 */
2950void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
2951 unsigned short alpha[NCCTRL_WIN],
2952 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap)
2953{
2954 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2955 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2956 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2957 28672, 40960, 57344, 81920, 114688, 163840, 229376
2958 };
2959
2960 unsigned int i, w;
2961
2962 for (i = 0; i < NMTUS; ++i) {
2963 unsigned int mtu = min(mtus[i], mtu_cap);
2964 unsigned int log2 = fls(mtu);
2965
2966 if (!(mtu & ((1 << log2) >> 2))) /* round */
2967 log2--;
2968 t3_write_reg(adap, A_TP_MTU_TABLE,
2969 (i << 24) | (log2 << 16) | mtu);
2970
2971 for (w = 0; w < NCCTRL_WIN; ++w) {
2972 unsigned int inc;
2973
2974 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2975 CC_MIN_INCR);
2976
2977 t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
2978 (w << 16) | (beta[w] << 13) | inc);
2979 }
2980 }
2981}
2982
2983/**
2984 * t3_read_hw_mtus - returns the values in the HW MTU table
2985 * @adap: the adapter
2986 * @mtus: where to store the HW MTU values
2987 *
2988 * Reads the HW MTU table.
2989 */
2990void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS])
2991{
2992 int i;
2993
2994 for (i = 0; i < NMTUS; ++i) {
2995 unsigned int val;
2996
2997 t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i);
2998 val = t3_read_reg(adap, A_TP_MTU_TABLE);
2999 mtus[i] = val & 0x3fff;
3000 }
3001}
3002
3003/**
3004 * t3_get_cong_cntl_tab - reads the congestion control table
3005 * @adap: the adapter
3006 * @incr: where to store the alpha values
3007 *
3008 * Reads the additive increments programmed into the HW congestion
3009 * control table.
3010 */
3011void t3_get_cong_cntl_tab(struct adapter *adap,
3012 unsigned short incr[NMTUS][NCCTRL_WIN])
3013{
3014 unsigned int mtu, w;
3015
3016 for (mtu = 0; mtu < NMTUS; ++mtu)
3017 for (w = 0; w < NCCTRL_WIN; ++w) {
3018 t3_write_reg(adap, A_TP_CCTRL_TABLE,
3019 0xffff0000 | (mtu << 5) | w);
3020 incr[mtu][w] = t3_read_reg(adap, A_TP_CCTRL_TABLE) &
3021 0x1fff;
3022 }
3023}
3024
3025/**
3026 * t3_tp_get_mib_stats - read TP's MIB counters
3027 * @adap: the adapter
3028 * @tps: holds the returned counter values
3029 *
3030 * Returns the values of TP's MIB counters.
3031 */
3032void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps)
3033{
3034 t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *) tps,
3035 sizeof(*tps) / sizeof(u32), 0);
3036}
3037
3038#define ulp_region(adap, name, start, len) \
3039 t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
3040 t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
3041 (start) + (len) - 1); \
3042 start += len
3043
3044#define ulptx_region(adap, name, start, len) \
3045 t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
3046 t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
3047 (start) + (len) - 1)
3048
3049static void ulp_config(struct adapter *adap, const struct tp_params *p)
3050{
3051 unsigned int m = p->chan_rx_size;
3052
3053 ulp_region(adap, ISCSI, m, p->chan_rx_size / 8);
3054 ulp_region(adap, TDDP, m, p->chan_rx_size / 8);
3055 ulptx_region(adap, TPT, m, p->chan_rx_size / 4);
3056 ulp_region(adap, STAG, m, p->chan_rx_size / 4);
3057 ulp_region(adap, RQ, m, p->chan_rx_size / 4);
3058 ulptx_region(adap, PBL, m, p->chan_rx_size / 4);
3059 ulp_region(adap, PBL, m, p->chan_rx_size / 4);
3060 t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
3061}
3062
480fe1a3
DLR		 3063/**
3064 * t3_set_proto_sram - set the contents of the protocol sram
3065 * @adapter: the adapter
3066 * @data: the protocol image
3067 *
3068 * Write the contents of the protocol SRAM.
3069 */
2c733a16 3070int t3_set_proto_sram(struct adapter *adap, const u8 *data)
480fe1a3
DLR		 3071{
3072 int i;
2c733a16 3073 const __be32 *buf = (const __be32 *)data;
480fe1a3
DLR		 3074
3075 for (i = 0; i < PROTO_SRAM_LINES; i++) {
05e5c116
AV		 3076 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, be32_to_cpu(*buf++));
3077 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, be32_to_cpu(*buf++));
3078 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, be32_to_cpu(*buf++));
3079 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, be32_to_cpu(*buf++));
3080 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, be32_to_cpu(*buf++));
2eab17ab 3081
480fe1a3
DLR		 3082 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
3083 if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
3084 return -EIO;
3085 }
3086 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, 0);
3087
3088 return 0;
3089}
3090
4d22de3e
DLR		 3091void t3_config_trace_filter(struct adapter *adapter,
3092 const struct trace_params *tp, int filter_index,
3093 int invert, int enable)
3094{
3095 u32 addr, key[4], mask[4];
3096
3097 key[0] = tp->sport | (tp->sip << 16);
3098 key[1] = (tp->sip >> 16) | (tp->dport << 16);
3099 key[2] = tp->dip;
3100 key[3] = tp->proto | (tp->vlan << 8) | (tp->intf << 20);
3101
3102 mask[0] = tp->sport_mask | (tp->sip_mask << 16);
3103 mask[1] = (tp->sip_mask >> 16) | (tp->dport_mask << 16);
3104 mask[2] = tp->dip_mask;
3105 mask[3] = tp->proto_mask | (tp->vlan_mask << 8) | (tp->intf_mask << 20);
3106
3107 if (invert)
3108 key[3] |= (1 << 29);
3109 if (enable)
3110 key[3] |= (1 << 28);
3111
3112 addr = filter_index ? A_TP_RX_TRC_KEY0 : A_TP_TX_TRC_KEY0;
3113 tp_wr_indirect(adapter, addr++, key[0]);
3114 tp_wr_indirect(adapter, addr++, mask[0]);
3115 tp_wr_indirect(adapter, addr++, key[1]);
3116 tp_wr_indirect(adapter, addr++, mask[1]);
3117 tp_wr_indirect(adapter, addr++, key[2]);
3118 tp_wr_indirect(adapter, addr++, mask[2]);
3119 tp_wr_indirect(adapter, addr++, key[3]);
3120 tp_wr_indirect(adapter, addr, mask[3]);
3121 t3_read_reg(adapter, A_TP_PIO_DATA);
3122}
3123
3124/**
3125 * t3_config_sched - configure a HW traffic scheduler
3126 * @adap: the adapter
3127 * @kbps: target rate in Kbps
3128 * @sched: the scheduler index
3129 *
3130 * Configure a HW scheduler for the target rate
3131 */
3132int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched)
3133{
3134 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
3135 unsigned int clk = adap->params.vpd.cclk * 1000;
3136 unsigned int selected_cpt = 0, selected_bpt = 0;
3137
3138 if (kbps > 0) {
3139 kbps *= 125; /* -> bytes */
3140 for (cpt = 1; cpt <= 255; cpt++) {
3141 tps = clk / cpt;
3142 bpt = (kbps + tps / 2) / tps;
3143 if (bpt > 0 && bpt <= 255) {
3144 v = bpt * tps;
3145 delta = v >= kbps ? v - kbps : kbps - v;
3146 if (delta <= mindelta) {
3147 mindelta = delta;
3148 selected_cpt = cpt;
3149 selected_bpt = bpt;
3150 }
3151 } else if (selected_cpt)
3152 break;
3153 }
3154 if (!selected_cpt)
3155 return -EINVAL;
3156 }
3157 t3_write_reg(adap, A_TP_TM_PIO_ADDR,
3158 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
3159 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3160 if (sched & 1)
3161 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
3162 else
3163 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
3164 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3165 return 0;
3166}
3167
3168static int tp_init(struct adapter *adap, const struct tp_params *p)
3169{
3170 int busy = 0;
3171
3172 tp_config(adap, p);
3173 t3_set_vlan_accel(adap, 3, 0);
3174
3175 if (is_offload(adap)) {
3176 tp_set_timers(adap, adap->params.vpd.cclk * 1000);
3177 t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
3178 busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE,
3179 0, 1000, 5);
3180 if (busy)
3181 CH_ERR(adap, "TP initialization timed out\n");
3182 }
3183
3184 if (!busy)
3185 t3_write_reg(adap, A_TP_RESET, F_TPRESET);
3186 return busy;
3187}
3188
3189int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask)
3190{
3191 if (port_mask & ~((1 << adap->params.nports) - 1))
3192 return -EINVAL;
3193 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
3194 port_mask << S_PORT0ACTIVE);
3195 return 0;
3196}
3197
3198/*
3199 * Perform the bits of HW initialization that are dependent on the number
3200 * of available ports.
3201 */
3202static void init_hw_for_avail_ports(struct adapter *adap, int nports)
3203{
3204 int i;
3205
3206 if (nports == 1) {
3207 t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
3208 t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
3209 t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN |
3210 F_PORT0ACTIVE | F_ENFORCEPKT);
8a9fab22 3211 t3_write_reg(adap, A_PM1_TX_CFG, 0xffffffff);
4d22de3e
DLR		 3212 } else {
3213 t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
3214 t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
3215 t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
3216 V_D1_WEIGHT(16) | V_D0_WEIGHT(16));
3217 t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
3218 F_TPRXPORTEN | F_PORT0ACTIVE | F_PORT1ACTIVE |
3219 F_ENFORCEPKT);
3220 t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
3221 t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
3222 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3223 V_TX_MOD_QUEUE_REQ_MAP(0xaa));
3224 for (i = 0; i < 16; i++)
3225 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
3226 (i << 16) | 0x1010);
3227 }
3228}
3229
3230static int calibrate_xgm(struct adapter *adapter)
3231{
3232 if (uses_xaui(adapter)) {
3233 unsigned int v, i;
3234
3235 for (i = 0; i < 5; ++i) {
3236 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3237 t3_read_reg(adapter, A_XGM_XAUI_IMP);
3238 msleep(1);
3239 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3240 if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) {
3241 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3242 V_XAUIIMP(G_CALIMP(v) >> 2));
3243 return 0;
3244 }
3245 }
3246 CH_ERR(adapter, "MAC calibration failed\n");
3247 return -1;
3248 } else {
3249 t3_write_reg(adapter, A_XGM_RGMII_IMP,
3250 V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3));
3251 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3252 F_XGM_IMPSETUPDATE);
3253 }
3254 return 0;
3255}
3256
3257static void calibrate_xgm_t3b(struct adapter *adapter)
3258{
3259 if (!uses_xaui(adapter)) {
3260 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
3261 F_CALUPDATE | V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3));
3262 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
3263 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
3264 F_XGM_IMPSETUPDATE);
3265 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3266 0);
3267 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
3268 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
3269 }
3270}
3271
3272struct mc7_timing_params {
3273 unsigned char ActToPreDly;
3274 unsigned char ActToRdWrDly;
3275 unsigned char PreCyc;
3276 unsigned char RefCyc[5];
3277 unsigned char BkCyc;
3278 unsigned char WrToRdDly;
3279 unsigned char RdToWrDly;
3280};
3281
3282/*
3283 * Write a value to a register and check that the write completed. These
3284 * writes normally complete in a cycle or two, so one read should suffice.
3285 * The very first read exists to flush the posted write to the device.
3286 */
3287static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val)
3288{
3289 t3_write_reg(adapter, addr, val);
3290 t3_read_reg(adapter, addr); /* flush */
3291 if (!(t3_read_reg(adapter, addr) & F_BUSY))
3292 return 0;
3293 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr);
3294 return -EIO;
3295}
3296
3297static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)
3298{
3299 static const unsigned int mc7_mode[] = {
3300 0x632, 0x642, 0x652, 0x432, 0x442
3301 };
3302 static const struct mc7_timing_params mc7_timings[] = {
3303 {12, 3, 4, {20, 28, 34, 52, 0}, 15, 6, 4},
3304 {12, 4, 5, {20, 28, 34, 52, 0}, 16, 7, 4},
3305 {12, 5, 6, {20, 28, 34, 52, 0}, 17, 8, 4},
3306 {9, 3, 4, {15, 21, 26, 39, 0}, 12, 6, 4},
3307 {9, 4, 5, {15, 21, 26, 39, 0}, 13, 7, 4}
3308 };
3309
3310 u32 val;
3311 unsigned int width, density, slow, attempts;
3312 struct adapter *adapter = mc7->adapter;
3313 const struct mc7_timing_params *p = &mc7_timings[mem_type];
3314
8ac3ba68
DLR		 3315 if (!mc7->size)
3316 return 0;
3317
4d22de3e
DLR		 3318 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3319 slow = val & F_SLOW;
3320 width = G_WIDTH(val);
3321 density = G_DEN(val);
3322
3323 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3324 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3325 msleep(1);
3326
3327 if (!slow) {
3328 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3329 t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3330 msleep(1);
3331 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3332 (F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) {
3333 CH_ERR(adapter, "%s MC7 calibration timed out\n",
3334 mc7->name);
3335 goto out_fail;
3336 }
3337 }
3338
3339 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3340 V_ACTTOPREDLY(p->ActToPreDly) |
3341 V_ACTTORDWRDLY(p->ActToRdWrDly) | V_PRECYC(p->PreCyc) |
3342 V_REFCYC(p->RefCyc[density]) | V_BKCYC(p->BkCyc) |
3343 V_WRTORDDLY(p->WrToRdDly) | V_RDTOWRDLY(p->RdToWrDly));
3344
3345 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3346 val | F_CLKEN | F_TERM150);
3347 t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3348
3349 if (!slow)
3350 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
3351 F_DLLENB);
3352 udelay(1);
3353
3354 val = slow ? 3 : 6;
3355 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3356 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
3357 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
3358 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3359 goto out_fail;
3360
3361 if (!slow) {
3362 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
3363 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);
3364 udelay(5);
3365 }
3366
3367 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3368 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3369 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3370 wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
3371 mc7_mode[mem_type]) ||
3372 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
3373 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3374 goto out_fail;
3375
3376 /* clock value is in KHz */
3377 mc7_clock = mc7_clock * 7812 + mc7_clock / 2; /* ns */
3378 mc7_clock /= 1000000; /* KHz->MHz, ns->us */
3379
3380 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
3381 F_PERREFEN | V_PREREFDIV(mc7_clock));
3382 t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
3383
3384 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);
3385 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
3386 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3387 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3388 (mc7->size << width) - 1);
3389 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3390 t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3391
3392 attempts = 50;
3393 do {
3394 msleep(250);
3395 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3396 } while ((val & F_BUSY) && --attempts);
3397 if (val & F_BUSY) {
3398 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
3399 goto out_fail;
3400 }
3401
3402 /* Enable normal memory accesses. */
3403 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
3404 return 0;
3405
3406out_fail:
3407 return -1;
3408}
3409
3410static void config_pcie(struct adapter *adap)
3411{
3412 static const u16 ack_lat[4][6] = {
3413 {237, 416, 559, 1071, 2095, 4143},
3414 {128, 217, 289, 545, 1057, 2081},
3415 {73, 118, 154, 282, 538, 1050},
3416 {67, 107, 86, 150, 278, 534}
3417 };
3418 static const u16 rpl_tmr[4][6] = {
3419 {711, 1248, 1677, 3213, 6285, 12429},
3420 {384, 651, 867, 1635, 3171, 6243},
3421 {219, 354, 462, 846, 1614, 3150},
3422 {201, 321, 258, 450, 834, 1602}
3423 };
3424
3425 u16 val;
3426 unsigned int log2_width, pldsize;
3427 unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
3428
3429 pci_read_config_word(adap->pdev,
3430 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
3431 &val);
3432 pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
3433 pci_read_config_word(adap->pdev,
3434 adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
3435 &val);
3436
3437 fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
3438 fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
3439 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3440 log2_width = fls(adap->params.pci.width) - 1;
3441 acklat = ack_lat[log2_width][pldsize];
3442 if (val & 1) /* check LOsEnable */
3443 acklat += fst_trn_tx * 4;
3444 rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;
3445
3446 if (adap->params.rev == 0)
3447 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
3448 V_T3A_ACKLAT(M_T3A_ACKLAT),
3449 V_T3A_ACKLAT(acklat));
3450 else
3451 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3452 V_ACKLAT(acklat));
3453
3454 t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3455 V_REPLAYLMT(rpllmt));
3456
3457 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
b881955b 3458 t3_set_reg_field(adap, A_PCIE_CFG, 0,
204e2f98 3459 F_ENABLELINKDWNDRST | F_ENABLELINKDOWNRST |
b881955b 3460 F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN);
4d22de3e
DLR		 3461}
3462
3463/*
3464 * Initialize and configure T3 HW modules. This performs the
3465 * initialization steps that need to be done once after a card is reset.
3466 * MAC and PHY initialization is handled separarely whenever a port is enabled.
3467 *
3468 * fw_params are passed to FW and their value is platform dependent. Only the
3469 * top 8 bits are available for use, the rest must be 0.
3470 */
3471int t3_init_hw(struct adapter *adapter, u32 fw_params)
3472{
b881955b 3473 int err = -EIO, attempts, i;
4d22de3e
DLR		 3474 const struct vpd_params *vpd = &adapter->params.vpd;
3475
3476 if (adapter->params.rev > 0)
3477 calibrate_xgm_t3b(adapter);
3478 else if (calibrate_xgm(adapter))
3479 goto out_err;
3480
3481 if (vpd->mclk) {
3482 partition_mem(adapter, &adapter->params.tp);
3483
3484 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3485 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3486 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3487 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
3488 adapter->params.mc5.nfilters,
3489 adapter->params.mc5.nroutes))
3490 goto out_err;
b881955b
DLR		 3491
3492 for (i = 0; i < 32; i++)
3493 if (clear_sge_ctxt(adapter, i, F_CQ))
3494 goto out_err;
4d22de3e
DLR		 3495 }
3496
3497 if (tp_init(adapter, &adapter->params.tp))
3498 goto out_err;
3499
3500 t3_tp_set_coalescing_size(adapter,
3501 min(adapter->params.sge.max_pkt_size,
3502 MAX_RX_COALESCING_LEN), 1);
3503 t3_tp_set_max_rxsize(adapter,
3504 min(adapter->params.sge.max_pkt_size, 16384U));
3505 ulp_config(adapter, &adapter->params.tp);
3506
3507 if (is_pcie(adapter))
3508 config_pcie(adapter);
3509 else
b881955b
DLR		 3510 t3_set_reg_field(adapter, A_PCIX_CFG, 0,
3511 F_DMASTOPEN | F_CLIDECEN);
4d22de3e 3512
a2604be5
DLR		 3513 if (adapter->params.rev == T3_REV_C)
3514 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
3515 F_CFG_CQE_SOP_MASK);
3516
8a9fab22 3517 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3f61e427
DLR		 3518 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3519 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
4d22de3e
DLR		 3520 init_hw_for_avail_ports(adapter, adapter->params.nports);
3521 t3_sge_init(adapter, &adapter->params.sge);
3522
f231e0a5
DLR		 3523 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter));
3524
4d22de3e
DLR		 3525 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3526 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3527 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3528 t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3529
b881955b 3530 attempts = 100;
4d22de3e
DLR		 3531 do { /* wait for uP to initialize */
3532 msleep(20);
3533 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
8ac3ba68
DLR		 3534 if (!attempts) {
3535 CH_ERR(adapter, "uP initialization timed out\n");
4d22de3e 3536 goto out_err;
8ac3ba68 3537 }
4d22de3e
DLR		 3538
3539 err = 0;
3540out_err:
3541 return err;
3542}
3543
3544/**
3545 * get_pci_mode - determine a card's PCI mode
3546 * @adapter: the adapter
3547 * @p: where to store the PCI settings
3548 *
3549 * Determines a card's PCI mode and associated parameters, such as speed
3550 * and width.
3551 */
7b9b0943 3552static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
4d22de3e
DLR		 3553{
3554 static unsigned short speed_map[] = { 33, 66, 100, 133 };
3555 u32 pci_mode, pcie_cap;
3556
3557 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
3558 if (pcie_cap) {
3559 u16 val;
3560
3561 p->variant = PCI_VARIANT_PCIE;
3562 p->pcie_cap_addr = pcie_cap;
3563 pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
3564 &val);
3565 p->width = (val >> 4) & 0x3f;
3566 return;
3567 }
3568
3569 pci_mode = t3_read_reg(adapter, A_PCIX_MODE);
3570 p->speed = speed_map[G_PCLKRANGE(pci_mode)];
3571 p->width = (pci_mode & F_64BIT) ? 64 : 32;
3572 pci_mode = G_PCIXINITPAT(pci_mode);
3573 if (pci_mode == 0)
3574 p->variant = PCI_VARIANT_PCI;
3575 else if (pci_mode < 4)
3576 p->variant = PCI_VARIANT_PCIX_MODE1_PARITY;
3577 else if (pci_mode < 8)
3578 p->variant = PCI_VARIANT_PCIX_MODE1_ECC;
3579 else
3580 p->variant = PCI_VARIANT_PCIX_266_MODE2;
3581}
3582
3583/**
3584 * init_link_config - initialize a link's SW state
3585 * @lc: structure holding the link state
3586 * @ai: information about the current card
3587 *
3588 * Initializes the SW state maintained for each link, including the link's
3589 * capabilities and default speed/duplex/flow-control/autonegotiation
3590 * settings.
3591 */
7b9b0943 3592static void init_link_config(struct link_config *lc, unsigned int caps)
4d22de3e
DLR		 3593{
3594 lc->supported = caps;
3595 lc->requested_speed = lc->speed = SPEED_INVALID;
3596 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
3597 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3598 if (lc->supported & SUPPORTED_Autoneg) {
3599 lc->advertising = lc->supported;
3600 lc->autoneg = AUTONEG_ENABLE;
3601 lc->requested_fc |= PAUSE_AUTONEG;
3602 } else {
3603 lc->advertising = 0;
3604 lc->autoneg = AUTONEG_DISABLE;
3605 }
3606}
3607
3608/**
3609 * mc7_calc_size - calculate MC7 memory size
3610 * @cfg: the MC7 configuration
3611 *
3612 * Calculates the size of an MC7 memory in bytes from the value of its
3613 * configuration register.
3614 */
7b9b0943 3615static unsigned int mc7_calc_size(u32 cfg)
4d22de3e
DLR		 3616{
3617 unsigned int width = G_WIDTH(cfg);
3618 unsigned int banks = !!(cfg & F_BKS) + 1;
3619 unsigned int org = !!(cfg & F_ORG) + 1;
3620 unsigned int density = G_DEN(cfg);
3621 unsigned int MBs = ((256 << density) * banks) / (org << width);
3622
3623 return MBs << 20;
3624}
3625
7b9b0943
RD		 3626static void mc7_prep(struct adapter *adapter, struct mc7 *mc7,
3627 unsigned int base_addr, const char *name)
4d22de3e
DLR		 3628{
3629 u32 cfg;
3630
3631 mc7->adapter = adapter;
3632 mc7->name = name;
3633 mc7->offset = base_addr - MC7_PMRX_BASE_ADDR;
3634 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
8ac3ba68 3635 mc7->size = mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg);
4d22de3e
DLR		 3636 mc7->width = G_WIDTH(cfg);
3637}
3638
3639void mac_prep(struct cmac *mac, struct adapter *adapter, int index)
3640{
3641 mac->adapter = adapter;
3642 mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index;
3643 mac->nucast = 1;
3644
3645 if (adapter->params.rev == 0 && uses_xaui(adapter)) {
3646 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
3647 is_10G(adapter) ? 0x2901c04 : 0x2301c04);
3648 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
3649 F_ENRGMII, 0);
3650 }
3651}
3652
3653void early_hw_init(struct adapter *adapter, const struct adapter_info *ai)
3654{
3655 u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2);
3656
3657 mi1_init(adapter, ai);
3658 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3659 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
3660 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3661 ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
8ac3ba68 3662 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
b881955b 3663 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
4d22de3e
DLR		 3664
3665 if (adapter->params.rev == 0 || !uses_xaui(adapter))
3666 val |= F_ENRGMII;
3667
3668 /* Enable MAC clocks so we can access the registers */
3669 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3670 t3_read_reg(adapter, A_XGM_PORT_CFG);
3671
3672 val |= F_CLKDIVRESET_;
3673 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3674 t3_read_reg(adapter, A_XGM_PORT_CFG);
3675 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
3676 t3_read_reg(adapter, A_XGM_PORT_CFG);
3677}
3678
3679/*
2eab17ab 3680 * Reset the adapter.
e4d08359 3681 * Older PCIe cards lose their config space during reset, PCI-X
4d22de3e
DLR		 3682 * ones don't.
3683 */
20d3fc11 3684int t3_reset_adapter(struct adapter *adapter)
4d22de3e 3685{
2eab17ab 3686 int i, save_and_restore_pcie =
e4d08359 3687 adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
4d22de3e
DLR		 3688 uint16_t devid = 0;
3689
e4d08359 3690 if (save_and_restore_pcie)
4d22de3e
DLR		 3691 pci_save_state(adapter->pdev);
3692 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3693
3694 /*
3695 * Delay. Give Some time to device to reset fully.
3696 * XXX The delay time should be modified.
3697 */
3698 for (i = 0; i < 10; i++) {
3699 msleep(50);
3700 pci_read_config_word(adapter->pdev, 0x00, &devid);
3701 if (devid == 0x1425)
3702 break;
3703 }
3704
3705 if (devid != 0x1425)
3706 return -1;
3707
e4d08359 3708 if (save_and_restore_pcie)
4d22de3e
DLR		 3709 pci_restore_state(adapter->pdev);
3710 return 0;
3711}
3712
7b9b0943 3713static int init_parity(struct adapter *adap)
b881955b
DLR		 3714{
3715 int i, err, addr;
3716
3717 if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
3718 return -EBUSY;
3719
3720 for (err = i = 0; !err && i < 16; i++)
3721 err = clear_sge_ctxt(adap, i, F_EGRESS);
3722 for (i = 0xfff0; !err && i <= 0xffff; i++)
3723 err = clear_sge_ctxt(adap, i, F_EGRESS);
3724 for (i = 0; !err && i < SGE_QSETS; i++)
3725 err = clear_sge_ctxt(adap, i, F_RESPONSEQ);
3726 if (err)
3727 return err;
3728
3729 t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);
3730 for (i = 0; i < 4; i++)
3731 for (addr = 0; addr <= M_IBQDBGADDR; addr++) {
3732 t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |
3733 F_IBQDBGWR | V_IBQDBGQID(i) |
3734 V_IBQDBGADDR(addr));
3735 err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG,
3736 F_IBQDBGBUSY, 0, 2, 1);
3737 if (err)
3738 return err;
3739 }
3740 return 0;
3741}
3742
4d22de3e
DLR		 3743/*
3744 * Initialize adapter SW state for the various HW modules, set initial values
3745 * for some adapter tunables, take PHYs out of reset, and initialize the MDIO
3746 * interface.
3747 */
7b9b0943
RD		 3748int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
3749 int reset)
4d22de3e
DLR		 3750{
3751 int ret;
04497982 3752 unsigned int i, j = -1;
4d22de3e
DLR		 3753
3754 get_pci_mode(adapter, &adapter->params.pci);
3755
3756 adapter->params.info = ai;
3757 adapter->params.nports = ai->nports;
3758 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
fc882196
DLR		 3759 /*
3760 * We used to only run the "adapter check task" once a second if
3761 * we had PHYs which didn't support interrupts (we would check
3762 * their link status once a second). Now we check other conditions
3763 * in that routine which could potentially impose a very high
3764 * interrupt load on the system. As such, we now always scan the
3765 * adapter state once a second ...
3766 */
3767 adapter->params.linkpoll_period = 10;
4d22de3e
DLR		 3768 adapter->params.stats_update_period = is_10G(adapter) ?
3769 MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10);
3770 adapter->params.pci.vpd_cap_addr =
3771 pci_find_capability(adapter->pdev, PCI_CAP_ID_VPD);
3772 ret = get_vpd_params(adapter, &adapter->params.vpd);
3773 if (ret < 0)
3774 return ret;
3775
3776 if (reset && t3_reset_adapter(adapter))
3777 return -1;
3778
3779 t3_sge_prep(adapter, &adapter->params.sge);
3780
3781 if (adapter->params.vpd.mclk) {
3782 struct tp_params *p = &adapter->params.tp;
3783
3784 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX");
3785 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX");
3786 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM");
3787
3788 p->nchan = ai->nports;
3789 p->pmrx_size = t3_mc7_size(&adapter->pmrx);
3790 p->pmtx_size = t3_mc7_size(&adapter->pmtx);
3791 p->cm_size = t3_mc7_size(&adapter->cm);
3792 p->chan_rx_size = p->pmrx_size / 2; /* only 1 Rx channel */
3793 p->chan_tx_size = p->pmtx_size / p->nchan;
3794 p->rx_pg_size = 64 * 1024;
3795 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024;
3796 p->rx_num_pgs = pm_num_pages(p->chan_rx_size, p->rx_pg_size);
3797 p->tx_num_pgs = pm_num_pages(p->chan_tx_size, p->tx_pg_size);
3798 p->ntimer_qs = p->cm_size >= (128 << 20) ||
3799 adapter->params.rev > 0 ? 12 : 6;
8ac3ba68
DLR		 3800 }
3801
3802 adapter->params.offload = t3_mc7_size(&adapter->pmrx) &&
3803 t3_mc7_size(&adapter->pmtx) &&
3804 t3_mc7_size(&adapter->cm);
4d22de3e 3805
8ac3ba68 3806 if (is_offload(adapter)) {
4d22de3e
DLR		 3807 adapter->params.mc5.nservers = DEFAULT_NSERVERS;
3808 adapter->params.mc5.nfilters = adapter->params.rev > 0 ?
3809 DEFAULT_NFILTERS : 0;
3810 adapter->params.mc5.nroutes = 0;
3811 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT);
3812
3813 init_mtus(adapter->params.mtus);
3814 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3815 }
3816
3817 early_hw_init(adapter, ai);
b881955b
DLR		 3818 ret = init_parity(adapter);
3819 if (ret)
3820 return ret;
4d22de3e
DLR		 3821
3822 for_each_port(adapter, i) {
3823 u8 hw_addr[6];
04497982 3824 const struct port_type_info *pti;
4d22de3e
DLR		 3825 struct port_info *p = adap2pinfo(adapter, i);
3826
04497982
DLR		 3827 while (!adapter->params.vpd.port_type[++j])
3828 ;
4d22de3e 3829
04497982 3830 pti = &port_types[adapter->params.vpd.port_type[j]];
9f64306b
DLR		 3831 if (!pti->phy_prep) {
3832 CH_ALERT(adapter, "Invalid port type index %d\n",
3833 adapter->params.vpd.port_type[j]);
3834 return -EINVAL;
3835 }
3836
04497982
DLR		 3837 ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3838 ai->mdio_ops);
78e4689e
DLR		 3839 if (ret)
3840 return ret;
4d22de3e 3841 mac_prep(&p->mac, adapter, j);
4d22de3e
DLR		 3842
3843 /*
3844 * The VPD EEPROM stores the base Ethernet address for the
3845 * card. A port's address is derived from the base by adding
3846 * the port's index to the base's low octet.
3847 */
3848 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
3849 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
3850
3851 memcpy(adapter->port[i]->dev_addr, hw_addr,
3852 ETH_ALEN);
3853 memcpy(adapter->port[i]->perm_addr, hw_addr,
3854 ETH_ALEN);
04497982 3855 init_link_config(&p->link_config, p->phy.caps);
4d22de3e 3856 p->phy.ops->power_down(&p->phy, 1);
fc882196
DLR		 3857
3858 /*
3859 * If the PHY doesn't support interrupts for link status
3860 * changes, schedule a scan of the adapter links at least
3861 * once a second.
3862 */
3863 if (!(p->phy.caps & SUPPORTED_IRQ) &&
3864 adapter->params.linkpoll_period > 10)
4d22de3e
DLR		 3865 adapter->params.linkpoll_period = 10;
3866 }
3867
3868 return 0;
3869}
3870
3871void t3_led_ready(struct adapter *adapter)
3872{
3873 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
3874 F_GPIO0_OUT_VAL);
3875}
204e2f98
DLR		 3876
3877int t3_replay_prep_adapter(struct adapter *adapter)
3878{
3879 const struct adapter_info *ai = adapter->params.info;
04497982 3880 unsigned int i, j = -1;
204e2f98
DLR		 3881 int ret;
3882
3883 early_hw_init(adapter, ai);
3884 ret = init_parity(adapter);
3885 if (ret)
3886 return ret;
3887
3888 for_each_port(adapter, i) {
04497982 3889 const struct port_type_info *pti;
204e2f98 3890 struct port_info *p = adap2pinfo(adapter, i);
204e2f98 3891
04497982
DLR		 3892 while (!adapter->params.vpd.port_type[++j])
3893 ;
3894
3895 pti = &port_types[adapter->params.vpd.port_type[j]];
3896 ret = pti->phy_prep(&p->phy, adapter, p->phy.addr, NULL);
78e4689e
DLR		 3897 if (ret)
3898 return ret;
204e2f98 3899 p->phy.ops->power_down(&p->phy, 1);
204e2f98
DLR		 3900 }
3901
3902return 0;
3903}
3904
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