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cxgb3 - Safeguard TCAM size usage
[mirror_ubuntu-kernels.git] / drivers / net / cxgb3 / t3_hw.c
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4d22de3e 1/*
1d68e93d 2 * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include "common.h"
33#include "regs.h"
34#include "sge_defs.h"
35#include "firmware_exports.h"
36
f2c6879e
DLR		 37/**
38 * t3_wait_op_done_val - wait until an operation is completed
39 * @adapter: the adapter performing the operation
40 * @reg: the register to check for completion
41 * @mask: a single-bit field within @reg that indicates completion
42 * @polarity: the value of the field when the operation is completed
43 * @attempts: number of check iterations
44 * @delay: delay in usecs between iterations
45 * @valp: where to store the value of the register at completion time
46 *
47 * Wait until an operation is completed by checking a bit in a register
48 * up to @attempts times. If @valp is not NULL the value of the register
49 * at the time it indicated completion is stored there. Returns 0 if the
50 * operation completes and -EAGAIN otherwise.
51 */
4d22de3e
DLR		 52
53int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
54 int polarity, int attempts, int delay, u32 *valp)
55{
56 while (1) {
57 u32 val = t3_read_reg(adapter, reg);
58
59 if (!!(val & mask) == polarity) {
60 if (valp)
61 *valp = val;
62 return 0;
63 }
64 if (--attempts == 0)
65 return -EAGAIN;
66 if (delay)
67 udelay(delay);
68 }
69}
70
71/**
72 * t3_write_regs - write a bunch of registers
73 * @adapter: the adapter to program
74 * @p: an array of register address/register value pairs
75 * @n: the number of address/value pairs
76 * @offset: register address offset
77 *
78 * Takes an array of register address/register value pairs and writes each
79 * value to the corresponding register. Register addresses are adjusted
80 * by the supplied offset.
81 */
82void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
83 int n, unsigned int offset)
84{
85 while (n--) {
86 t3_write_reg(adapter, p->reg_addr + offset, p->val);
87 p++;
88 }
89}
90
91/**
92 * t3_set_reg_field - set a register field to a value
93 * @adapter: the adapter to program
94 * @addr: the register address
95 * @mask: specifies the portion of the register to modify
96 * @val: the new value for the register field
97 *
98 * Sets a register field specified by the supplied mask to the
99 * given value.
100 */
101void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
102 u32 val)
103{
104 u32 v = t3_read_reg(adapter, addr) & ~mask;
105
106 t3_write_reg(adapter, addr, v | val);
107 t3_read_reg(adapter, addr); /* flush */
108}
109
110/**
111 * t3_read_indirect - read indirectly addressed registers
112 * @adap: the adapter
113 * @addr_reg: register holding the indirect address
114 * @data_reg: register holding the value of the indirect register
115 * @vals: where the read register values are stored
116 * @start_idx: index of first indirect register to read
117 * @nregs: how many indirect registers to read
118 *
119 * Reads registers that are accessed indirectly through an address/data
120 * register pair.
121 */
122void t3_read_indirect(struct adapter *adap, unsigned int addr_reg,
123 unsigned int data_reg, u32 *vals, unsigned int nregs,
124 unsigned int start_idx)
125{
126 while (nregs--) {
127 t3_write_reg(adap, addr_reg, start_idx);
128 *vals++ = t3_read_reg(adap, data_reg);
129 start_idx++;
130 }
131}
132
133/**
134 * t3_mc7_bd_read - read from MC7 through backdoor accesses
135 * @mc7: identifies MC7 to read from
136 * @start: index of first 64-bit word to read
137 * @n: number of 64-bit words to read
138 * @buf: where to store the read result
139 *
140 * Read n 64-bit words from MC7 starting at word start, using backdoor
141 * accesses.
142 */
143int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
144 u64 *buf)
145{
146 static const int shift[] = { 0, 0, 16, 24 };
147 static const int step[] = { 0, 32, 16, 8 };
148
149 unsigned int size64 = mc7->size / 8; /* # of 64-bit words */
150 struct adapter *adap = mc7->adapter;
151
152 if (start >= size64 || start + n > size64)
153 return -EINVAL;
154
155 start *= (8 << mc7->width);
156 while (n--) {
157 int i;
158 u64 val64 = 0;
159
160 for (i = (1 << mc7->width) - 1; i >= 0; --i) {
161 int attempts = 10;
162 u32 val;
163
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
165 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
166 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
167 while ((val & F_BUSY) && attempts--)
168 val = t3_read_reg(adap,
169 mc7->offset + A_MC7_BD_OP);
170 if (val & F_BUSY)
171 return -EIO;
172
173 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
174 if (mc7->width == 0) {
175 val64 = t3_read_reg(adap,
176 mc7->offset +
177 A_MC7_BD_DATA0);
178 val64 |= (u64) val << 32;
179 } else {
180 if (mc7->width > 1)
181 val >>= shift[mc7->width];
182 val64 |= (u64) val << (step[mc7->width] * i);
183 }
184 start += 8;
185 }
186 *buf++ = val64;
187 }
188 return 0;
189}
190
191/*
192 * Initialize MI1.
193 */
194static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
195{
196 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
197 u32 val = F_PREEN | V_MDIINV(ai->mdiinv) | V_MDIEN(ai->mdien) |
198 V_CLKDIV(clkdiv);
199
200 if (!(ai->caps & SUPPORTED_10000baseT_Full))
201 val |= V_ST(1);
202 t3_write_reg(adap, A_MI1_CFG, val);
203}
204
205#define MDIO_ATTEMPTS 10
206
207/*
208 * MI1 read/write operations for direct-addressed PHYs.
209 */
210static int mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr,
211 int reg_addr, unsigned int *valp)
212{
213 int ret;
214 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
215
216 if (mmd_addr)
217 return -EINVAL;
218
219 mutex_lock(&adapter->mdio_lock);
220 t3_write_reg(adapter, A_MI1_ADDR, addr);
221 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
222 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
223 if (!ret)
224 *valp = t3_read_reg(adapter, A_MI1_DATA);
225 mutex_unlock(&adapter->mdio_lock);
226 return ret;
227}
228
229static int mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr,
230 int reg_addr, unsigned int val)
231{
232 int ret;
233 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
234
235 if (mmd_addr)
236 return -EINVAL;
237
238 mutex_lock(&adapter->mdio_lock);
239 t3_write_reg(adapter, A_MI1_ADDR, addr);
240 t3_write_reg(adapter, A_MI1_DATA, val);
241 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
242 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
243 mutex_unlock(&adapter->mdio_lock);
244 return ret;
245}
246
247static const struct mdio_ops mi1_mdio_ops = {
248 mi1_read,
249 mi1_write
250};
251
252/*
253 * MI1 read/write operations for indirect-addressed PHYs.
254 */
255static int mi1_ext_read(struct adapter *adapter, int phy_addr, int mmd_addr,
256 int reg_addr, unsigned int *valp)
257{
258 int ret;
259 u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
260
261 mutex_lock(&adapter->mdio_lock);
262 t3_write_reg(adapter, A_MI1_ADDR, addr);
263 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
264 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
265 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
266 if (!ret) {
267 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
268 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
269 MDIO_ATTEMPTS, 20);
270 if (!ret)
271 *valp = t3_read_reg(adapter, A_MI1_DATA);
272 }
273 mutex_unlock(&adapter->mdio_lock);
274 return ret;
275}
276
277static int mi1_ext_write(struct adapter *adapter, int phy_addr, int mmd_addr,
278 int reg_addr, unsigned int val)
279{
280 int ret;
281 u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
282
283 mutex_lock(&adapter->mdio_lock);
284 t3_write_reg(adapter, A_MI1_ADDR, addr);
285 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
286 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
287 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
288 if (!ret) {
289 t3_write_reg(adapter, A_MI1_DATA, val);
290 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
291 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
292 MDIO_ATTEMPTS, 20);
293 }
294 mutex_unlock(&adapter->mdio_lock);
295 return ret;
296}
297
298static const struct mdio_ops mi1_mdio_ext_ops = {
299 mi1_ext_read,
300 mi1_ext_write
301};
302
303/**
304 * t3_mdio_change_bits - modify the value of a PHY register
305 * @phy: the PHY to operate on
306 * @mmd: the device address
307 * @reg: the register address
308 * @clear: what part of the register value to mask off
309 * @set: what part of the register value to set
310 *
311 * Changes the value of a PHY register by applying a mask to its current
312 * value and ORing the result with a new value.
313 */
314int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
315 unsigned int set)
316{
317 int ret;
318 unsigned int val;
319
320 ret = mdio_read(phy, mmd, reg, &val);
321 if (!ret) {
322 val &= ~clear;
323 ret = mdio_write(phy, mmd, reg, val | set);
324 }
325 return ret;
326}
327
328/**
329 * t3_phy_reset - reset a PHY block
330 * @phy: the PHY to operate on
331 * @mmd: the device address of the PHY block to reset
332 * @wait: how long to wait for the reset to complete in 1ms increments
333 *
334 * Resets a PHY block and optionally waits for the reset to complete.
335 * @mmd should be 0 for 10/100/1000 PHYs and the device address to reset
336 * for 10G PHYs.
337 */
338int t3_phy_reset(struct cphy *phy, int mmd, int wait)
339{
340 int err;
341 unsigned int ctl;
342
343 err = t3_mdio_change_bits(phy, mmd, MII_BMCR, BMCR_PDOWN, BMCR_RESET);
344 if (err || !wait)
345 return err;
346
347 do {
348 err = mdio_read(phy, mmd, MII_BMCR, &ctl);
349 if (err)
350 return err;
351 ctl &= BMCR_RESET;
352 if (ctl)
353 msleep(1);
354 } while (ctl && --wait);
355
356 return ctl ? -1 : 0;
357}
358
359/**
360 * t3_phy_advertise - set the PHY advertisement registers for autoneg
361 * @phy: the PHY to operate on
362 * @advert: bitmap of capabilities the PHY should advertise
363 *
364 * Sets a 10/100/1000 PHY's advertisement registers to advertise the
365 * requested capabilities.
366 */
367int t3_phy_advertise(struct cphy *phy, unsigned int advert)
368{
369 int err;
370 unsigned int val = 0;
371
372 err = mdio_read(phy, 0, MII_CTRL1000, &val);
373 if (err)
374 return err;
375
376 val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
377 if (advert & ADVERTISED_1000baseT_Half)
378 val |= ADVERTISE_1000HALF;
379 if (advert & ADVERTISED_1000baseT_Full)
380 val |= ADVERTISE_1000FULL;
381
382 err = mdio_write(phy, 0, MII_CTRL1000, val);
383 if (err)
384 return err;
385
386 val = 1;
387 if (advert & ADVERTISED_10baseT_Half)
388 val |= ADVERTISE_10HALF;
389 if (advert & ADVERTISED_10baseT_Full)
390 val |= ADVERTISE_10FULL;
391 if (advert & ADVERTISED_100baseT_Half)
392 val |= ADVERTISE_100HALF;
393 if (advert & ADVERTISED_100baseT_Full)
394 val |= ADVERTISE_100FULL;
395 if (advert & ADVERTISED_Pause)
396 val |= ADVERTISE_PAUSE_CAP;
397 if (advert & ADVERTISED_Asym_Pause)
398 val |= ADVERTISE_PAUSE_ASYM;
399 return mdio_write(phy, 0, MII_ADVERTISE, val);
400}
401
402/**
403 * t3_set_phy_speed_duplex - force PHY speed and duplex
404 * @phy: the PHY to operate on
405 * @speed: requested PHY speed
406 * @duplex: requested PHY duplex
407 *
408 * Force a 10/100/1000 PHY's speed and duplex. This also disables
409 * auto-negotiation except for GigE, where auto-negotiation is mandatory.
410 */
411int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
412{
413 int err;
414 unsigned int ctl;
415
416 err = mdio_read(phy, 0, MII_BMCR, &ctl);
417 if (err)
418 return err;
419
420 if (speed >= 0) {
421 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
422 if (speed == SPEED_100)
423 ctl |= BMCR_SPEED100;
424 else if (speed == SPEED_1000)
425 ctl |= BMCR_SPEED1000;
426 }
427 if (duplex >= 0) {
428 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
429 if (duplex == DUPLEX_FULL)
430 ctl |= BMCR_FULLDPLX;
431 }
432 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
433 ctl |= BMCR_ANENABLE;
434 return mdio_write(phy, 0, MII_BMCR, ctl);
435}
436
437static const struct adapter_info t3_adap_info[] = {
438 {2, 0, 0, 0,
439 F_GPIO2_OEN | F_GPIO4_OEN |
440 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
441 SUPPORTED_OFFLOAD,
442 &mi1_mdio_ops, "Chelsio PE9000"},
443 {2, 0, 0, 0,
444 F_GPIO2_OEN | F_GPIO4_OEN |
445 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
446 SUPPORTED_OFFLOAD,
447 &mi1_mdio_ops, "Chelsio T302"},
448 {1, 0, 0, 0,
449 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
450 F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
451 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_OFFLOAD,
452 &mi1_mdio_ext_ops, "Chelsio T310"},
453 {2, 0, 0, 0,
454 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
455 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
456 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
457 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_OFFLOAD,
458 &mi1_mdio_ext_ops, "Chelsio T320"},
459};
460
461/*
462 * Return the adapter_info structure with a given index. Out-of-range indices
463 * return NULL.
464 */
465const struct adapter_info *t3_get_adapter_info(unsigned int id)
466{
467 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
468}
469
470#define CAPS_1G (SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | \
471 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII)
472#define CAPS_10G (SUPPORTED_10000baseT_Full | SUPPORTED_AUI)
473
474static const struct port_type_info port_types[] = {
475 {NULL},
476 {t3_ael1002_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
477 "10GBASE-XR"},
478 {t3_vsc8211_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
479 "10/100/1000BASE-T"},
480 {NULL, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
481 "10/100/1000BASE-T"},
482 {t3_xaui_direct_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
483 {NULL, CAPS_10G, "10GBASE-KX4"},
484 {t3_qt2045_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
485 {t3_ael1006_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
486 "10GBASE-SR"},
487 {NULL, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
488};
489
490#undef CAPS_1G
491#undef CAPS_10G
492
493#define VPD_ENTRY(name, len) \
494 u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
495
496/*
497 * Partial EEPROM Vital Product Data structure. Includes only the ID and
498 * VPD-R sections.
499 */
500struct t3_vpd {
501 u8 id_tag;
502 u8 id_len[2];
503 u8 id_data[16];
504 u8 vpdr_tag;
505 u8 vpdr_len[2];
506 VPD_ENTRY(pn, 16); /* part number */
507 VPD_ENTRY(ec, 16); /* EC level */
508 VPD_ENTRY(sn, 16); /* serial number */
509 VPD_ENTRY(na, 12); /* MAC address base */
510 VPD_ENTRY(cclk, 6); /* core clock */
511 VPD_ENTRY(mclk, 6); /* mem clock */
512 VPD_ENTRY(uclk, 6); /* uP clk */
513 VPD_ENTRY(mdc, 6); /* MDIO clk */
514 VPD_ENTRY(mt, 2); /* mem timing */
515 VPD_ENTRY(xaui0cfg, 6); /* XAUI0 config */
516 VPD_ENTRY(xaui1cfg, 6); /* XAUI1 config */
517 VPD_ENTRY(port0, 2); /* PHY0 complex */
518 VPD_ENTRY(port1, 2); /* PHY1 complex */
519 VPD_ENTRY(port2, 2); /* PHY2 complex */
520 VPD_ENTRY(port3, 2); /* PHY3 complex */
521 VPD_ENTRY(rv, 1); /* csum */
522 u32 pad; /* for multiple-of-4 sizing and alignment */
523};
524
525#define EEPROM_MAX_POLL 4
526#define EEPROM_STAT_ADDR 0x4000
527#define VPD_BASE 0xc00
528
529/**
530 * t3_seeprom_read - read a VPD EEPROM location
531 * @adapter: adapter to read
532 * @addr: EEPROM address
533 * @data: where to store the read data
534 *
535 * Read a 32-bit word from a location in VPD EEPROM using the card's PCI
536 * VPD ROM capability. A zero is written to the flag bit when the
537 * addres is written to the control register. The hardware device will
538 * set the flag to 1 when 4 bytes have been read into the data register.
539 */
540int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
541{
542 u16 val;
543 int attempts = EEPROM_MAX_POLL;
544 unsigned int base = adapter->params.pci.vpd_cap_addr;
545
546 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
547 return -EINVAL;
548
549 pci_write_config_word(adapter->pdev, base + PCI_VPD_ADDR, addr);
550 do {
551 udelay(10);
552 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
553 } while (!(val & PCI_VPD_ADDR_F) && --attempts);
554
555 if (!(val & PCI_VPD_ADDR_F)) {
556 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr);
557 return -EIO;
558 }
559 pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, data);
560 *data = le32_to_cpu(*data);
561 return 0;
562}
563
564/**
565 * t3_seeprom_write - write a VPD EEPROM location
566 * @adapter: adapter to write
567 * @addr: EEPROM address
568 * @data: value to write
569 *
570 * Write a 32-bit word to a location in VPD EEPROM using the card's PCI
571 * VPD ROM capability.
572 */
573int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
574{
575 u16 val;
576 int attempts = EEPROM_MAX_POLL;
577 unsigned int base = adapter->params.pci.vpd_cap_addr;
578
579 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
580 return -EINVAL;
581
582 pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA,
583 cpu_to_le32(data));
584 pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR,
585 addr | PCI_VPD_ADDR_F);
586 do {
587 msleep(1);
588 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
589 } while ((val & PCI_VPD_ADDR_F) && --attempts);
590
591 if (val & PCI_VPD_ADDR_F) {
592 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
593 return -EIO;
594 }
595 return 0;
596}
597
598/**
599 * t3_seeprom_wp - enable/disable EEPROM write protection
600 * @adapter: the adapter
601 * @enable: 1 to enable write protection, 0 to disable it
602 *
603 * Enables or disables write protection on the serial EEPROM.
604 */
605int t3_seeprom_wp(struct adapter *adapter, int enable)
606{
607 return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
608}
609
610/*
611 * Convert a character holding a hex digit to a number.
612 */
613static unsigned int hex2int(unsigned char c)
614{
615 return isdigit(c) ? c - '0' : toupper(c) - 'A' + 10;
616}
617
618/**
619 * get_vpd_params - read VPD parameters from VPD EEPROM
620 * @adapter: adapter to read
621 * @p: where to store the parameters
622 *
623 * Reads card parameters stored in VPD EEPROM.
624 */
625static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
626{
627 int i, addr, ret;
628 struct t3_vpd vpd;
629
630 /*
631 * Card information is normally at VPD_BASE but some early cards had
632 * it at 0.
633 */
634 ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd);
635 if (ret)
636 return ret;
637 addr = vpd.id_tag == 0x82 ? VPD_BASE : 0;
638
639 for (i = 0; i < sizeof(vpd); i += 4) {
640 ret = t3_seeprom_read(adapter, addr + i,
641 (u32 *)((u8 *)&vpd + i));
642 if (ret)
643 return ret;
644 }
645
646 p->cclk = simple_strtoul(vpd.cclk_data, NULL, 10);
647 p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10);
648 p->uclk = simple_strtoul(vpd.uclk_data, NULL, 10);
649 p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10);
650 p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10);
651
652 /* Old eeproms didn't have port information */
653 if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
654 p->port_type[0] = uses_xaui(adapter) ? 1 : 2;
655 p->port_type[1] = uses_xaui(adapter) ? 6 : 2;
656 } else {
657 p->port_type[0] = hex2int(vpd.port0_data[0]);
658 p->port_type[1] = hex2int(vpd.port1_data[0]);
659 p->xauicfg[0] = simple_strtoul(vpd.xaui0cfg_data, NULL, 16);
660 p->xauicfg[1] = simple_strtoul(vpd.xaui1cfg_data, NULL, 16);
661 }
662
663 for (i = 0; i < 6; i++)
664 p->eth_base[i] = hex2int(vpd.na_data[2 * i]) * 16 +
665 hex2int(vpd.na_data[2 * i + 1]);
666 return 0;
667}
668
669/* serial flash and firmware constants */
670enum {
671 SF_ATTEMPTS = 5, /* max retries for SF1 operations */
672 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
673 SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */
674
675 /* flash command opcodes */
676 SF_PROG_PAGE = 2, /* program page */
677 SF_WR_DISABLE = 4, /* disable writes */
678 SF_RD_STATUS = 5, /* read status register */
679 SF_WR_ENABLE = 6, /* enable writes */
680 SF_RD_DATA_FAST = 0xb, /* read flash */
681 SF_ERASE_SECTOR = 0xd8, /* erase sector */
682
683 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
2e283962
DLR		 684 FW_VERS_ADDR = 0x77ffc, /* flash address holding FW version */
685 FW_MIN_SIZE = 8 /* at least version and csum */
4d22de3e
DLR		 686};
687
688/**
689 * sf1_read - read data from the serial flash
690 * @adapter: the adapter
691 * @byte_cnt: number of bytes to read
692 * @cont: whether another operation will be chained
693 * @valp: where to store the read data
694 *
695 * Reads up to 4 bytes of data from the serial flash. The location of
696 * the read needs to be specified prior to calling this by issuing the
697 * appropriate commands to the serial flash.
698 */
699static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
700 u32 *valp)
701{
702 int ret;
703
704 if (!byte_cnt || byte_cnt > 4)
705 return -EINVAL;
706 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
707 return -EBUSY;
708 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
709 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
710 if (!ret)
711 *valp = t3_read_reg(adapter, A_SF_DATA);
712 return ret;
713}
714
715/**
716 * sf1_write - write data to the serial flash
717 * @adapter: the adapter
718 * @byte_cnt: number of bytes to write
719 * @cont: whether another operation will be chained
720 * @val: value to write
721 *
722 * Writes up to 4 bytes of data to the serial flash. The location of
723 * the write needs to be specified prior to calling this by issuing the
724 * appropriate commands to the serial flash.
725 */
726static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
727 u32 val)
728{
729 if (!byte_cnt || byte_cnt > 4)
730 return -EINVAL;
731 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
732 return -EBUSY;
733 t3_write_reg(adapter, A_SF_DATA, val);
734 t3_write_reg(adapter, A_SF_OP,
735 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
736 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
737}
738
739/**
740 * flash_wait_op - wait for a flash operation to complete
741 * @adapter: the adapter
742 * @attempts: max number of polls of the status register
743 * @delay: delay between polls in ms
744 *
745 * Wait for a flash operation to complete by polling the status register.
746 */
747static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
748{
749 int ret;
750 u32 status;
751
752 while (1) {
753 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
754 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
755 return ret;
756 if (!(status & 1))
757 return 0;
758 if (--attempts == 0)
759 return -EAGAIN;
760 if (delay)
761 msleep(delay);
762 }
763}
764
765/**
766 * t3_read_flash - read words from serial flash
767 * @adapter: the adapter
768 * @addr: the start address for the read
769 * @nwords: how many 32-bit words to read
770 * @data: where to store the read data
771 * @byte_oriented: whether to store data as bytes or as words
772 *
773 * Read the specified number of 32-bit words from the serial flash.
774 * If @byte_oriented is set the read data is stored as a byte array
775 * (i.e., big-endian), otherwise as 32-bit words in the platform's
776 * natural endianess.
777 */
778int t3_read_flash(struct adapter *adapter, unsigned int addr,
779 unsigned int nwords, u32 *data, int byte_oriented)
780{
781 int ret;
782
783 if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3))
784 return -EINVAL;
785
786 addr = swab32(addr) | SF_RD_DATA_FAST;
787
788 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 ||
789 (ret = sf1_read(adapter, 1, 1, data)) != 0)
790 return ret;
791
792 for (; nwords; nwords--, data++) {
793 ret = sf1_read(adapter, 4, nwords > 1, data);
794 if (ret)
795 return ret;
796 if (byte_oriented)
797 *data = htonl(*data);
798 }
799 return 0;
800}
801
802/**
803 * t3_write_flash - write up to a page of data to the serial flash
804 * @adapter: the adapter
805 * @addr: the start address to write
806 * @n: length of data to write
807 * @data: the data to write
808 *
809 * Writes up to a page of data (256 bytes) to the serial flash starting
810 * at the given address.
811 */
812static int t3_write_flash(struct adapter *adapter, unsigned int addr,
813 unsigned int n, const u8 *data)
814{
815 int ret;
816 u32 buf[64];
817 unsigned int i, c, left, val, offset = addr & 0xff;
818
819 if (addr + n > SF_SIZE || offset + n > 256)
820 return -EINVAL;
821
822 val = swab32(addr) | SF_PROG_PAGE;
823
824 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
825 (ret = sf1_write(adapter, 4, 1, val)) != 0)
826 return ret;
827
828 for (left = n; left; left -= c) {
829 c = min(left, 4U);
830 for (val = 0, i = 0; i < c; ++i)
831 val = (val << 8) + *data++;
832
833 ret = sf1_write(adapter, c, c != left, val);
834 if (ret)
835 return ret;
836 }
837 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
838 return ret;
839
840 /* Read the page to verify the write succeeded */
841 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
842 if (ret)
843 return ret;
844
845 if (memcmp(data - n, (u8 *) buf + offset, n))
846 return -EIO;
847 return 0;
848}
849
4aac3899
DLR		 850enum fw_version_type {
851 FW_VERSION_N3,
852 FW_VERSION_T3
853};
854
4d22de3e
DLR		 855/**
856 * t3_get_fw_version - read the firmware version
857 * @adapter: the adapter
858 * @vers: where to place the version
859 *
860 * Reads the FW version from flash.
861 */
862int t3_get_fw_version(struct adapter *adapter, u32 *vers)
863{
864 return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
865}
866
867/**
868 * t3_check_fw_version - check if the FW is compatible with this driver
869 * @adapter: the adapter
870 *
871 * Checks if an adapter's FW is compatible with the driver. Returns 0
872 * if the versions are compatible, a negative error otherwise.
873 */
874int t3_check_fw_version(struct adapter *adapter)
875{
876 int ret;
877 u32 vers;
4aac3899 878 unsigned int type, major, minor;
4d22de3e
DLR		 879
880 ret = t3_get_fw_version(adapter, &vers);
881 if (ret)
882 return ret;
883
4aac3899
DLR		 884 type = G_FW_VERSION_TYPE(vers);
885 major = G_FW_VERSION_MAJOR(vers);
886 minor = G_FW_VERSION_MINOR(vers);
4d22de3e 887
75d8626f
DLR		 888 if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR &&
889 minor == FW_VERSION_MINOR)
4d22de3e
DLR		 890 return 0;
891
4aac3899 892 CH_ERR(adapter, "found wrong FW version(%u.%u), "
75d8626f
DLR		 893 "driver needs version %u.%u\n", major, minor,
894 FW_VERSION_MAJOR, FW_VERSION_MINOR);
4d22de3e
DLR		 895 return -EINVAL;
896}
897
898/**
899 * t3_flash_erase_sectors - erase a range of flash sectors
900 * @adapter: the adapter
901 * @start: the first sector to erase
902 * @end: the last sector to erase
903 *
904 * Erases the sectors in the given range.
905 */
906static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end)
907{
908 while (start <= end) {
909 int ret;
910
911 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
912 (ret = sf1_write(adapter, 4, 0,
913 SF_ERASE_SECTOR | (start << 8))) != 0 ||
914 (ret = flash_wait_op(adapter, 5, 500)) != 0)
915 return ret;
916 start++;
917 }
918 return 0;
919}
920
921/*
922 * t3_load_fw - download firmware
923 * @adapter: the adapter
924 * @fw_data: the firrware image to write
925 * @size: image size
926 *
927 * Write the supplied firmware image to the card's serial flash.
928 * The FW image has the following sections: @size - 8 bytes of code and
929 * data, followed by 4 bytes of FW version, followed by the 32-bit
930 * 1's complement checksum of the whole image.
931 */
932int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size)
933{
934 u32 csum;
935 unsigned int i;
936 const u32 *p = (const u32 *)fw_data;
937 int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
938
2e283962 939 if ((size & 3) || size < FW_MIN_SIZE)
4d22de3e
DLR		 940 return -EINVAL;
941 if (size > FW_VERS_ADDR + 8 - FW_FLASH_BOOT_ADDR)
942 return -EFBIG;
943
944 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
945 csum += ntohl(p[i]);
946 if (csum != 0xffffffff) {
947 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
948 csum);
949 return -EINVAL;
950 }
951
952 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
953 if (ret)
954 goto out;
955
956 size -= 8; /* trim off version and checksum */
957 for (addr = FW_FLASH_BOOT_ADDR; size;) {
958 unsigned int chunk_size = min(size, 256U);
959
960 ret = t3_write_flash(adapter, addr, chunk_size, fw_data);
961 if (ret)
962 goto out;
963
964 addr += chunk_size;
965 fw_data += chunk_size;
966 size -= chunk_size;
967 }
968
969 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data);
970out:
971 if (ret)
972 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
973 return ret;
974}
975
976#define CIM_CTL_BASE 0x2000
977
978/**
979 * t3_cim_ctl_blk_read - read a block from CIM control region
980 *
981 * @adap: the adapter
982 * @addr: the start address within the CIM control region
983 * @n: number of words to read
984 * @valp: where to store the result
985 *
986 * Reads a block of 4-byte words from the CIM control region.
987 */
988int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
989 unsigned int n, unsigned int *valp)
990{
991 int ret = 0;
992
993 if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
994 return -EBUSY;
995
996 for ( ; !ret && n--; addr += 4) {
997 t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
998 ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
999 0, 5, 2);
1000 if (!ret)
1001 *valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
1002 }
1003 return ret;
1004}
1005
1006
1007/**
1008 * t3_link_changed - handle interface link changes
1009 * @adapter: the adapter
1010 * @port_id: the port index that changed link state
1011 *
1012 * Called when a port's link settings change to propagate the new values
1013 * to the associated PHY and MAC. After performing the common tasks it
1014 * invokes an OS-specific handler.
1015 */
1016void t3_link_changed(struct adapter *adapter, int port_id)
1017{
1018 int link_ok, speed, duplex, fc;
1019 struct port_info *pi = adap2pinfo(adapter, port_id);
1020 struct cphy *phy = &pi->phy;
1021 struct cmac *mac = &pi->mac;
1022 struct link_config *lc = &pi->link_config;
1023
1024 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
1025
1026 if (link_ok != lc->link_ok && adapter->params.rev > 0 &&
1027 uses_xaui(adapter)) {
1028 if (link_ok)
1029 t3b_pcs_reset(mac);
1030 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1031 link_ok ? F_TXACTENABLE | F_RXEN : 0);
1032 }
1033 lc->link_ok = link_ok;
1034 lc->speed = speed < 0 ? SPEED_INVALID : speed;
1035 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
1036 if (lc->requested_fc & PAUSE_AUTONEG)
1037 fc &= lc->requested_fc;
1038 else
1039 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1040
1041 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
1042 /* Set MAC speed, duplex, and flow control to match PHY. */
1043 t3_mac_set_speed_duplex_fc(mac, speed, duplex, fc);
1044 lc->fc = fc;
1045 }
1046
1047 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
1048}
1049
1050/**
1051 * t3_link_start - apply link configuration to MAC/PHY
1052 * @phy: the PHY to setup
1053 * @mac: the MAC to setup
1054 * @lc: the requested link configuration
1055 *
1056 * Set up a port's MAC and PHY according to a desired link configuration.
1057 * - If the PHY can auto-negotiate first decide what to advertise, then
1058 * enable/disable auto-negotiation as desired, and reset.
1059 * - If the PHY does not auto-negotiate just reset it.
1060 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1061 * otherwise do it later based on the outcome of auto-negotiation.
1062 */
1063int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
1064{
1065 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1066
1067 lc->link_ok = 0;
1068 if (lc->supported & SUPPORTED_Autoneg) {
1069 lc->advertising &= ~(ADVERTISED_Asym_Pause | ADVERTISED_Pause);
1070 if (fc) {
1071 lc->advertising |= ADVERTISED_Asym_Pause;
1072 if (fc & PAUSE_RX)
1073 lc->advertising |= ADVERTISED_Pause;
1074 }
1075 phy->ops->advertise(phy, lc->advertising);
1076
1077 if (lc->autoneg == AUTONEG_DISABLE) {
1078 lc->speed = lc->requested_speed;
1079 lc->duplex = lc->requested_duplex;
1080 lc->fc = (unsigned char)fc;
1081 t3_mac_set_speed_duplex_fc(mac, lc->speed, lc->duplex,
1082 fc);
1083 /* Also disables autoneg */
1084 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
1085 phy->ops->reset(phy, 0);
1086 } else
1087 phy->ops->autoneg_enable(phy);
1088 } else {
1089 t3_mac_set_speed_duplex_fc(mac, -1, -1, fc);
1090 lc->fc = (unsigned char)fc;
1091 phy->ops->reset(phy, 0);
1092 }
1093 return 0;
1094}
1095
1096/**
1097 * t3_set_vlan_accel - control HW VLAN extraction
1098 * @adapter: the adapter
1099 * @ports: bitmap of adapter ports to operate on
1100 * @on: enable (1) or disable (0) HW VLAN extraction
1101 *
1102 * Enables or disables HW extraction of VLAN tags for the given port.
1103 */
1104void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on)
1105{
1106 t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
1107 ports << S_VLANEXTRACTIONENABLE,
1108 on ? (ports << S_VLANEXTRACTIONENABLE) : 0);
1109}
1110
1111struct intr_info {
1112 unsigned int mask; /* bits to check in interrupt status */
1113 const char *msg; /* message to print or NULL */
1114 short stat_idx; /* stat counter to increment or -1 */
1115 unsigned short fatal:1; /* whether the condition reported is fatal */
1116};
1117
1118/**
1119 * t3_handle_intr_status - table driven interrupt handler
1120 * @adapter: the adapter that generated the interrupt
1121 * @reg: the interrupt status register to process
1122 * @mask: a mask to apply to the interrupt status
1123 * @acts: table of interrupt actions
1124 * @stats: statistics counters tracking interrupt occurences
1125 *
1126 * A table driven interrupt handler that applies a set of masks to an
1127 * interrupt status word and performs the corresponding actions if the
1128 * interrupts described by the mask have occured. The actions include
1129 * optionally printing a warning or alert message, and optionally
1130 * incrementing a stat counter. The table is terminated by an entry
1131 * specifying mask 0. Returns the number of fatal interrupt conditions.
1132 */
1133static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg,
1134 unsigned int mask,
1135 const struct intr_info *acts,
1136 unsigned long *stats)
1137{
1138 int fatal = 0;
1139 unsigned int status = t3_read_reg(adapter, reg) & mask;
1140
1141 for (; acts->mask; ++acts) {
1142 if (!(status & acts->mask))
1143 continue;
1144 if (acts->fatal) {
1145 fatal++;
1146 CH_ALERT(adapter, "%s (0x%x)\n",
1147 acts->msg, status & acts->mask);
1148 } else if (acts->msg)
1149 CH_WARN(adapter, "%s (0x%x)\n",
1150 acts->msg, status & acts->mask);
1151 if (acts->stat_idx >= 0)
1152 stats[acts->stat_idx]++;
1153 }
1154 if (status) /* clear processed interrupts */
1155 t3_write_reg(adapter, reg, status);
1156 return fatal;
1157}
1158
1159#define SGE_INTR_MASK (F_RSPQDISABLED)
1160#define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \
1161 F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \
1162 F_NFASRCHFAIL)
1163#define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE))
1164#define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1165 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \
1166 F_TXFIFO_UNDERRUN | F_RXFIFO_OVERFLOW)
1167#define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \
1168 F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \
1169 F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \
1170 F_DETCORECCERR | F_DETUNCECCERR | F_PIOPARERR | \
1171 V_WFPARERR(M_WFPARERR) | V_RFPARERR(M_RFPARERR) | \
1172 V_CFPARERR(M_CFPARERR) /* | V_MSIXPARERR(M_MSIXPARERR) */)
1173#define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\
1174 F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \
1175 /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \
1176 V_BISTERR(M_BISTERR) | F_PEXERR)
1177#define ULPRX_INTR_MASK F_PARERR
1178#define ULPTX_INTR_MASK 0
1179#define CPLSW_INTR_MASK (F_TP_FRAMING_ERROR | \
1180 F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \
1181 F_ZERO_SWITCH_ERROR)
1182#define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \
1183 F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \
1184 F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \
1185 F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT)
1186#define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \
1187 V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \
1188 V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR))
1189#define PMRX_INTR_MASK (F_ZERO_E_CMD_ERROR | IESPI_FRM_ERR | OCSPI_FRM_ERR | \
1190 V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR) | \
1191 V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR))
1192#define MPS_INTR_MASK (V_TX0TPPARERRENB(M_TX0TPPARERRENB) | \
1193 V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \
1194 V_RXTPPARERRENB(M_RXTPPARERRENB) | \
1195 V_MCAPARERRENB(M_MCAPARERRENB))
1196#define PL_INTR_MASK (F_T3DBG | F_XGMAC0_0 | F_XGMAC0_1 | F_MC5A | F_PM1_TX | \
1197 F_PM1_RX | F_ULP2_TX | F_ULP2_RX | F_TP1 | F_CIM | \
1198 F_MC7_CM | F_MC7_PMTX | F_MC7_PMRX | F_SGE3 | F_PCIM0 | \
1199 F_MPS0 | F_CPL_SWITCH)
1200
1201/*
1202 * Interrupt handler for the PCIX1 module.
1203 */
1204static void pci_intr_handler(struct adapter *adapter)
1205{
1206 static const struct intr_info pcix1_intr_info[] = {
4d22de3e
DLR		 1207 {F_MSTDETPARERR, "PCI master detected parity error", -1, 1},
1208 {F_SIGTARABT, "PCI signaled target abort", -1, 1},
1209 {F_RCVTARABT, "PCI received target abort", -1, 1},
1210 {F_RCVMSTABT, "PCI received master abort", -1, 1},
1211 {F_SIGSYSERR, "PCI signaled system error", -1, 1},
1212 {F_DETPARERR, "PCI detected parity error", -1, 1},
1213 {F_SPLCMPDIS, "PCI split completion discarded", -1, 1},
1214 {F_UNXSPLCMP, "PCI unexpected split completion error", -1, 1},
1215 {F_RCVSPLCMPERR, "PCI received split completion error", -1,
1216 1},
1217 {F_DETCORECCERR, "PCI correctable ECC error",
1218 STAT_PCI_CORR_ECC, 0},
1219 {F_DETUNCECCERR, "PCI uncorrectable ECC error", -1, 1},
1220 {F_PIOPARERR, "PCI PIO FIFO parity error", -1, 1},
1221 {V_WFPARERR(M_WFPARERR), "PCI write FIFO parity error", -1,
1222 1},
1223 {V_RFPARERR(M_RFPARERR), "PCI read FIFO parity error", -1,
1224 1},
1225 {V_CFPARERR(M_CFPARERR), "PCI command FIFO parity error", -1,
1226 1},
1227 {V_MSIXPARERR(M_MSIXPARERR), "PCI MSI-X table/PBA parity "
1228 "error", -1, 1},
1229 {0}
1230 };
1231
1232 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK,
1233 pcix1_intr_info, adapter->irq_stats))
1234 t3_fatal_err(adapter);
1235}
1236
1237/*
1238 * Interrupt handler for the PCIE module.
1239 */
1240static void pcie_intr_handler(struct adapter *adapter)
1241{
1242 static const struct intr_info pcie_intr_info[] = {
b5a44bcb 1243 {F_PEXERR, "PCI PEX error", -1, 1},
4d22de3e
DLR		 1244 {F_UNXSPLCPLERRR,
1245 "PCI unexpected split completion DMA read error", -1, 1},
1246 {F_UNXSPLCPLERRC,
1247 "PCI unexpected split completion DMA command error", -1, 1},
1248 {F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1},
1249 {F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1},
1250 {F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1},
1251 {F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1},
1252 {V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR),
1253 "PCI MSI-X table/PBA parity error", -1, 1},
1254 {V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1},
1255 {0}
1256 };
1257
1258 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK,
1259 pcie_intr_info, adapter->irq_stats))
1260 t3_fatal_err(adapter);
1261}
1262
1263/*
1264 * TP interrupt handler.
1265 */
1266static void tp_intr_handler(struct adapter *adapter)
1267{
1268 static const struct intr_info tp_intr_info[] = {
1269 {0xffffff, "TP parity error", -1, 1},
1270 {0x1000000, "TP out of Rx pages", -1, 1},
1271 {0x2000000, "TP out of Tx pages", -1, 1},
1272 {0}
1273 };
1274
1275 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
1276 tp_intr_info, NULL))
1277 t3_fatal_err(adapter);
1278}
1279
1280/*
1281 * CIM interrupt handler.
1282 */
1283static void cim_intr_handler(struct adapter *adapter)
1284{
1285 static const struct intr_info cim_intr_info[] = {
1286 {F_RSVDSPACEINT, "CIM reserved space write", -1, 1},
1287 {F_SDRAMRANGEINT, "CIM SDRAM address out of range", -1, 1},
1288 {F_FLASHRANGEINT, "CIM flash address out of range", -1, 1},
1289 {F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1},
1290 {F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1},
1291 {F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1},
1292 {F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1},
1293 {F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1},
1294 {F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1},
1295 {F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1},
1296 {F_BLKRDPLINT, "CIM block read from PL space", -1, 1},
1297 {F_BLKWRPLINT, "CIM block write to PL space", -1, 1},
1298 {0}
1299 };
1300
1301 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff,
1302 cim_intr_info, NULL))
1303 t3_fatal_err(adapter);
1304}
1305
1306/*
1307 * ULP RX interrupt handler.
1308 */
1309static void ulprx_intr_handler(struct adapter *adapter)
1310{
1311 static const struct intr_info ulprx_intr_info[] = {
1312 {F_PARERR, "ULP RX parity error", -1, 1},
1313 {0}
1314 };
1315
1316 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1317 ulprx_intr_info, NULL))
1318 t3_fatal_err(adapter);
1319}
1320
1321/*
1322 * ULP TX interrupt handler.
1323 */
1324static void ulptx_intr_handler(struct adapter *adapter)
1325{
1326 static const struct intr_info ulptx_intr_info[] = {
1327 {F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds",
1328 STAT_ULP_CH0_PBL_OOB, 0},
1329 {F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds",
1330 STAT_ULP_CH1_PBL_OOB, 0},
1331 {0}
1332 };
1333
1334 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1335 ulptx_intr_info, adapter->irq_stats))
1336 t3_fatal_err(adapter);
1337}
1338
1339#define ICSPI_FRM_ERR (F_ICSPI0_FIFO2X_RX_FRAMING_ERROR | \
1340 F_ICSPI1_FIFO2X_RX_FRAMING_ERROR | F_ICSPI0_RX_FRAMING_ERROR | \
1341 F_ICSPI1_RX_FRAMING_ERROR | F_ICSPI0_TX_FRAMING_ERROR | \
1342 F_ICSPI1_TX_FRAMING_ERROR)
1343#define OESPI_FRM_ERR (F_OESPI0_RX_FRAMING_ERROR | \
1344 F_OESPI1_RX_FRAMING_ERROR | F_OESPI0_TX_FRAMING_ERROR | \
1345 F_OESPI1_TX_FRAMING_ERROR | F_OESPI0_OFIFO2X_TX_FRAMING_ERROR | \
1346 F_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1347
1348/*
1349 * PM TX interrupt handler.
1350 */
1351static void pmtx_intr_handler(struct adapter *adapter)
1352{
1353 static const struct intr_info pmtx_intr_info[] = {
1354 {F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1},
1355 {ICSPI_FRM_ERR, "PMTX ispi framing error", -1, 1},
1356 {OESPI_FRM_ERR, "PMTX ospi framing error", -1, 1},
1357 {V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR),
1358 "PMTX ispi parity error", -1, 1},
1359 {V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR),
1360 "PMTX ospi parity error", -1, 1},
1361 {0}
1362 };
1363
1364 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff,
1365 pmtx_intr_info, NULL))
1366 t3_fatal_err(adapter);
1367}
1368
1369#define IESPI_FRM_ERR (F_IESPI0_FIFO2X_RX_FRAMING_ERROR | \
1370 F_IESPI1_FIFO2X_RX_FRAMING_ERROR | F_IESPI0_RX_FRAMING_ERROR | \
1371 F_IESPI1_RX_FRAMING_ERROR | F_IESPI0_TX_FRAMING_ERROR | \
1372 F_IESPI1_TX_FRAMING_ERROR)
1373#define OCSPI_FRM_ERR (F_OCSPI0_RX_FRAMING_ERROR | \
1374 F_OCSPI1_RX_FRAMING_ERROR | F_OCSPI0_TX_FRAMING_ERROR | \
1375 F_OCSPI1_TX_FRAMING_ERROR | F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR | \
1376 F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1377
1378/*
1379 * PM RX interrupt handler.
1380 */
1381static void pmrx_intr_handler(struct adapter *adapter)
1382{
1383 static const struct intr_info pmrx_intr_info[] = {
1384 {F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1},
1385 {IESPI_FRM_ERR, "PMRX ispi framing error", -1, 1},
1386 {OCSPI_FRM_ERR, "PMRX ospi framing error", -1, 1},
1387 {V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR),
1388 "PMRX ispi parity error", -1, 1},
1389 {V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR),
1390 "PMRX ospi parity error", -1, 1},
1391 {0}
1392 };
1393
1394 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff,
1395 pmrx_intr_info, NULL))
1396 t3_fatal_err(adapter);
1397}
1398
1399/*
1400 * CPL switch interrupt handler.
1401 */
1402static void cplsw_intr_handler(struct adapter *adapter)
1403{
1404 static const struct intr_info cplsw_intr_info[] = {
1405/* { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 }, */
1406 {F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1},
1407 {F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1},
1408 {F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1},
1409 {F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1},
1410 {0}
1411 };
1412
1413 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
1414 cplsw_intr_info, NULL))
1415 t3_fatal_err(adapter);
1416}
1417
1418/*
1419 * MPS interrupt handler.
1420 */
1421static void mps_intr_handler(struct adapter *adapter)
1422{
1423 static const struct intr_info mps_intr_info[] = {
1424 {0x1ff, "MPS parity error", -1, 1},
1425 {0}
1426 };
1427
1428 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff,
1429 mps_intr_info, NULL))
1430 t3_fatal_err(adapter);
1431}
1432
1433#define MC7_INTR_FATAL (F_UE | V_PE(M_PE) | F_AE)
1434
1435/*
1436 * MC7 interrupt handler.
1437 */
1438static void mc7_intr_handler(struct mc7 *mc7)
1439{
1440 struct adapter *adapter = mc7->adapter;
1441 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1442
1443 if (cause & F_CE) {
1444 mc7->stats.corr_err++;
1445 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, "
1446 "data 0x%x 0x%x 0x%x\n", mc7->name,
1447 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1448 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1449 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1450 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1451 }
1452
1453 if (cause & F_UE) {
1454 mc7->stats.uncorr_err++;
1455 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, "
1456 "data 0x%x 0x%x 0x%x\n", mc7->name,
1457 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1458 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1459 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1460 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1461 }
1462
1463 if (G_PE(cause)) {
1464 mc7->stats.parity_err++;
1465 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n",
1466 mc7->name, G_PE(cause));
1467 }
1468
1469 if (cause & F_AE) {
1470 u32 addr = 0;
1471
1472 if (adapter->params.rev > 0)
1473 addr = t3_read_reg(adapter,
1474 mc7->offset + A_MC7_ERR_ADDR);
1475 mc7->stats.addr_err++;
1476 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n",
1477 mc7->name, addr);
1478 }
1479
1480 if (cause & MC7_INTR_FATAL)
1481 t3_fatal_err(adapter);
1482
1483 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1484}
1485
1486#define XGM_INTR_FATAL (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1487 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR))
1488/*
1489 * XGMAC interrupt handler.
1490 */
1491static int mac_intr_handler(struct adapter *adap, unsigned int idx)
1492{
1493 struct cmac *mac = &adap2pinfo(adap, idx)->mac;
1494 u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset);
1495
1496 if (cause & V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR)) {
1497 mac->stats.tx_fifo_parity_err++;
1498 CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx);
1499 }
1500 if (cause & V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR)) {
1501 mac->stats.rx_fifo_parity_err++;
1502 CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx);
1503 }
1504 if (cause & F_TXFIFO_UNDERRUN)
1505 mac->stats.tx_fifo_urun++;
1506 if (cause & F_RXFIFO_OVERFLOW)
1507 mac->stats.rx_fifo_ovfl++;
1508 if (cause & V_SERDES_LOS(M_SERDES_LOS))
1509 mac->stats.serdes_signal_loss++;
1510 if (cause & F_XAUIPCSCTCERR)
1511 mac->stats.xaui_pcs_ctc_err++;
1512 if (cause & F_XAUIPCSALIGNCHANGE)
1513 mac->stats.xaui_pcs_align_change++;
1514
1515 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
1516 if (cause & XGM_INTR_FATAL)
1517 t3_fatal_err(adap);
1518 return cause != 0;
1519}
1520
1521/*
1522 * Interrupt handler for PHY events.
1523 */
1524int t3_phy_intr_handler(struct adapter *adapter)
1525{
1526 static const int intr_gpio_bits[] = { 8, 0x20 };
1527
1528 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1529
1530 for_each_port(adapter, i) {
1531 if (cause & intr_gpio_bits[i]) {
1532 struct cphy *phy = &adap2pinfo(adapter, i)->phy;
1533 int phy_cause = phy->ops->intr_handler(phy);
1534
1535 if (phy_cause & cphy_cause_link_change)
1536 t3_link_changed(adapter, i);
1537 if (phy_cause & cphy_cause_fifo_error)
1538 phy->fifo_errors++;
1539 }
1540 }
1541
1542 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1543 return 0;
1544}
1545
1546/*
1547 * T3 slow path (non-data) interrupt handler.
1548 */
1549int t3_slow_intr_handler(struct adapter *adapter)
1550{
1551 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1552
1553 cause &= adapter->slow_intr_mask;
1554 if (!cause)
1555 return 0;
1556 if (cause & F_PCIM0) {
1557 if (is_pcie(adapter))
1558 pcie_intr_handler(adapter);
1559 else
1560 pci_intr_handler(adapter);
1561 }
1562 if (cause & F_SGE3)
1563 t3_sge_err_intr_handler(adapter);
1564 if (cause & F_MC7_PMRX)
1565 mc7_intr_handler(&adapter->pmrx);
1566 if (cause & F_MC7_PMTX)
1567 mc7_intr_handler(&adapter->pmtx);
1568 if (cause & F_MC7_CM)
1569 mc7_intr_handler(&adapter->cm);
1570 if (cause & F_CIM)
1571 cim_intr_handler(adapter);
1572 if (cause & F_TP1)
1573 tp_intr_handler(adapter);
1574 if (cause & F_ULP2_RX)
1575 ulprx_intr_handler(adapter);
1576 if (cause & F_ULP2_TX)
1577 ulptx_intr_handler(adapter);
1578 if (cause & F_PM1_RX)
1579 pmrx_intr_handler(adapter);
1580 if (cause & F_PM1_TX)
1581 pmtx_intr_handler(adapter);
1582 if (cause & F_CPL_SWITCH)
1583 cplsw_intr_handler(adapter);
1584 if (cause & F_MPS0)
1585 mps_intr_handler(adapter);
1586 if (cause & F_MC5A)
1587 t3_mc5_intr_handler(&adapter->mc5);
1588 if (cause & F_XGMAC0_0)
1589 mac_intr_handler(adapter, 0);
1590 if (cause & F_XGMAC0_1)
1591 mac_intr_handler(adapter, 1);
1592 if (cause & F_T3DBG)
1593 t3_os_ext_intr_handler(adapter);
1594
1595 /* Clear the interrupts just processed. */
1596 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1597 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1598 return 1;
1599}
1600
1601/**
1602 * t3_intr_enable - enable interrupts
1603 * @adapter: the adapter whose interrupts should be enabled
1604 *
1605 * Enable interrupts by setting the interrupt enable registers of the
1606 * various HW modules and then enabling the top-level interrupt
1607 * concentrator.
1608 */
1609void t3_intr_enable(struct adapter *adapter)
1610{
1611 static const struct addr_val_pair intr_en_avp[] = {
1612 {A_SG_INT_ENABLE, SGE_INTR_MASK},
1613 {A_MC7_INT_ENABLE, MC7_INTR_MASK},
1614 {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
1615 MC7_INTR_MASK},
1616 {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
1617 MC7_INTR_MASK},
1618 {A_MC5_DB_INT_ENABLE, MC5_INTR_MASK},
1619 {A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK},
1620 {A_TP_INT_ENABLE, 0x3bfffff},
1621 {A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK},
1622 {A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK},
1623 {A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK},
1624 {A_MPS_INT_ENABLE, MPS_INTR_MASK},
1625 };
1626
1627 adapter->slow_intr_mask = PL_INTR_MASK;
1628
1629 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
1630
1631 if (adapter->params.rev > 0) {
1632 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1633 CPLSW_INTR_MASK | F_CIM_OVFL_ERROR);
1634 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1635 ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
1636 F_PBL_BOUND_ERR_CH1);
1637 } else {
1638 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1639 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1640 }
1641
1642 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW,
1643 adapter_info(adapter)->gpio_intr);
1644 t3_write_reg(adapter, A_T3DBG_INT_ENABLE,
1645 adapter_info(adapter)->gpio_intr);
1646 if (is_pcie(adapter))
1647 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1648 else
1649 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1650 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1651 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1652}
1653
1654/**
1655 * t3_intr_disable - disable a card's interrupts
1656 * @adapter: the adapter whose interrupts should be disabled
1657 *
1658 * Disable interrupts. We only disable the top-level interrupt
1659 * concentrator and the SGE data interrupts.
1660 */
1661void t3_intr_disable(struct adapter *adapter)
1662{
1663 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
1664 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1665 adapter->slow_intr_mask = 0;
1666}
1667
1668/**
1669 * t3_intr_clear - clear all interrupts
1670 * @adapter: the adapter whose interrupts should be cleared
1671 *
1672 * Clears all interrupts.
1673 */
1674void t3_intr_clear(struct adapter *adapter)
1675{
1676 static const unsigned int cause_reg_addr[] = {
1677 A_SG_INT_CAUSE,
1678 A_SG_RSPQ_FL_STATUS,
1679 A_PCIX_INT_CAUSE,
1680 A_MC7_INT_CAUSE,
1681 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
1682 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
1683 A_CIM_HOST_INT_CAUSE,
1684 A_TP_INT_CAUSE,
1685 A_MC5_DB_INT_CAUSE,
1686 A_ULPRX_INT_CAUSE,
1687 A_ULPTX_INT_CAUSE,
1688 A_CPL_INTR_CAUSE,
1689 A_PM1_TX_INT_CAUSE,
1690 A_PM1_RX_INT_CAUSE,
1691 A_MPS_INT_CAUSE,
1692 A_T3DBG_INT_CAUSE,
1693 };
1694 unsigned int i;
1695
1696 /* Clear PHY and MAC interrupts for each port. */
1697 for_each_port(adapter, i)
1698 t3_port_intr_clear(adapter, i);
1699
1700 for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i)
1701 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
1702
1703 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
1704 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1705}
1706
1707/**
1708 * t3_port_intr_enable - enable port-specific interrupts
1709 * @adapter: associated adapter
1710 * @idx: index of port whose interrupts should be enabled
1711 *
1712 * Enable port-specific (i.e., MAC and PHY) interrupts for the given
1713 * adapter port.
1714 */
1715void t3_port_intr_enable(struct adapter *adapter, int idx)
1716{
1717 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
1718
1719 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK);
1720 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
1721 phy->ops->intr_enable(phy);
1722}
1723
1724/**
1725 * t3_port_intr_disable - disable port-specific interrupts
1726 * @adapter: associated adapter
1727 * @idx: index of port whose interrupts should be disabled
1728 *
1729 * Disable port-specific (i.e., MAC and PHY) interrupts for the given
1730 * adapter port.
1731 */
1732void t3_port_intr_disable(struct adapter *adapter, int idx)
1733{
1734 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
1735
1736 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0);
1737 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
1738 phy->ops->intr_disable(phy);
1739}
1740
1741/**
1742 * t3_port_intr_clear - clear port-specific interrupts
1743 * @adapter: associated adapter
1744 * @idx: index of port whose interrupts to clear
1745 *
1746 * Clear port-specific (i.e., MAC and PHY) interrupts for the given
1747 * adapter port.
1748 */
1749void t3_port_intr_clear(struct adapter *adapter, int idx)
1750{
1751 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
1752
1753 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff);
1754 t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */
1755 phy->ops->intr_clear(phy);
1756}
1757
1758/**
1759 * t3_sge_write_context - write an SGE context
1760 * @adapter: the adapter
1761 * @id: the context id
1762 * @type: the context type
1763 *
1764 * Program an SGE context with the values already loaded in the
1765 * CONTEXT_DATA? registers.
1766 */
1767static int t3_sge_write_context(struct adapter *adapter, unsigned int id,
1768 unsigned int type)
1769{
1770 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
1771 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
1772 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
1773 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
1774 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
1775 V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
1776 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
1777 0, 5, 1);
1778}
1779
1780/**
1781 * t3_sge_init_ecntxt - initialize an SGE egress context
1782 * @adapter: the adapter to configure
1783 * @id: the context id
1784 * @gts_enable: whether to enable GTS for the context
1785 * @type: the egress context type
1786 * @respq: associated response queue
1787 * @base_addr: base address of queue
1788 * @size: number of queue entries
1789 * @token: uP token
1790 * @gen: initial generation value for the context
1791 * @cidx: consumer pointer
1792 *
1793 * Initialize an SGE egress context and make it ready for use. If the
1794 * platform allows concurrent context operations, the caller is
1795 * responsible for appropriate locking.
1796 */
1797int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
1798 enum sge_context_type type, int respq, u64 base_addr,
1799 unsigned int size, unsigned int token, int gen,
1800 unsigned int cidx)
1801{
1802 unsigned int credits = type == SGE_CNTXT_OFLD ? 0 : FW_WR_NUM;
1803
1804 if (base_addr & 0xfff) /* must be 4K aligned */
1805 return -EINVAL;
1806 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1807 return -EBUSY;
1808
1809 base_addr >>= 12;
1810 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
1811 V_EC_CREDITS(credits) | V_EC_GTS(gts_enable));
1812 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
1813 V_EC_BASE_LO(base_addr & 0xffff));
1814 base_addr >>= 16;
1815 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr);
1816 base_addr >>= 32;
1817 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
1818 V_EC_BASE_HI(base_addr & 0xf) | V_EC_RESPQ(respq) |
1819 V_EC_TYPE(type) | V_EC_GEN(gen) | V_EC_UP_TOKEN(token) |
1820 F_EC_VALID);
1821 return t3_sge_write_context(adapter, id, F_EGRESS);
1822}
1823
1824/**
1825 * t3_sge_init_flcntxt - initialize an SGE free-buffer list context
1826 * @adapter: the adapter to configure
1827 * @id: the context id
1828 * @gts_enable: whether to enable GTS for the context
1829 * @base_addr: base address of queue
1830 * @size: number of queue entries
1831 * @bsize: size of each buffer for this queue
1832 * @cong_thres: threshold to signal congestion to upstream producers
1833 * @gen: initial generation value for the context
1834 * @cidx: consumer pointer
1835 *
1836 * Initialize an SGE free list context and make it ready for use. The
1837 * caller is responsible for ensuring only one context operation occurs
1838 * at a time.
1839 */
1840int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
1841 int gts_enable, u64 base_addr, unsigned int size,
1842 unsigned int bsize, unsigned int cong_thres, int gen,
1843 unsigned int cidx)
1844{
1845 if (base_addr & 0xfff) /* must be 4K aligned */
1846 return -EINVAL;
1847 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1848 return -EBUSY;
1849
1850 base_addr >>= 12;
1851 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr);
1852 base_addr >>= 32;
1853 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
1854 V_FL_BASE_HI((u32) base_addr) |
1855 V_FL_INDEX_LO(cidx & M_FL_INDEX_LO));
1856 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
1857 V_FL_GEN(gen) | V_FL_INDEX_HI(cidx >> 12) |
1858 V_FL_ENTRY_SIZE_LO(bsize & M_FL_ENTRY_SIZE_LO));
1859 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
1860 V_FL_ENTRY_SIZE_HI(bsize >> (32 - S_FL_ENTRY_SIZE_LO)) |
1861 V_FL_CONG_THRES(cong_thres) | V_FL_GTS(gts_enable));
1862 return t3_sge_write_context(adapter, id, F_FREELIST);
1863}
1864
1865/**
1866 * t3_sge_init_rspcntxt - initialize an SGE response queue context
1867 * @adapter: the adapter to configure
1868 * @id: the context id
1869 * @irq_vec_idx: MSI-X interrupt vector index, 0 if no MSI-X, -1 if no IRQ
1870 * @base_addr: base address of queue
1871 * @size: number of queue entries
1872 * @fl_thres: threshold for selecting the normal or jumbo free list
1873 * @gen: initial generation value for the context
1874 * @cidx: consumer pointer
1875 *
1876 * Initialize an SGE response queue context and make it ready for use.
1877 * The caller is responsible for ensuring only one context operation
1878 * occurs at a time.
1879 */
1880int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
1881 int irq_vec_idx, u64 base_addr, unsigned int size,
1882 unsigned int fl_thres, int gen, unsigned int cidx)
1883{
1884 unsigned int intr = 0;
1885
1886 if (base_addr & 0xfff) /* must be 4K aligned */
1887 return -EINVAL;
1888 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1889 return -EBUSY;
1890
1891 base_addr >>= 12;
1892 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
1893 V_CQ_INDEX(cidx));
1894 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
1895 base_addr >>= 32;
1896 if (irq_vec_idx >= 0)
1897 intr = V_RQ_MSI_VEC(irq_vec_idx) | F_RQ_INTR_EN;
1898 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
1899 V_CQ_BASE_HI((u32) base_addr) | intr | V_RQ_GEN(gen));
1900 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
1901 return t3_sge_write_context(adapter, id, F_RESPONSEQ);
1902}
1903
1904/**
1905 * t3_sge_init_cqcntxt - initialize an SGE completion queue context
1906 * @adapter: the adapter to configure
1907 * @id: the context id
1908 * @base_addr: base address of queue
1909 * @size: number of queue entries
1910 * @rspq: response queue for async notifications
1911 * @ovfl_mode: CQ overflow mode
1912 * @credits: completion queue credits
1913 * @credit_thres: the credit threshold
1914 *
1915 * Initialize an SGE completion queue context and make it ready for use.
1916 * The caller is responsible for ensuring only one context operation
1917 * occurs at a time.
1918 */
1919int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
1920 unsigned int size, int rspq, int ovfl_mode,
1921 unsigned int credits, unsigned int credit_thres)
1922{
1923 if (base_addr & 0xfff) /* must be 4K aligned */
1924 return -EINVAL;
1925 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1926 return -EBUSY;
1927
1928 base_addr >>= 12;
1929 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
1930 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
1931 base_addr >>= 32;
1932 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
1933 V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) |
1934 V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode));
1935 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
1936 V_CQ_CREDIT_THRES(credit_thres));
1937 return t3_sge_write_context(adapter, id, F_CQ);
1938}
1939
1940/**
1941 * t3_sge_enable_ecntxt - enable/disable an SGE egress context
1942 * @adapter: the adapter
1943 * @id: the egress context id
1944 * @enable: enable (1) or disable (0) the context
1945 *
1946 * Enable or disable an SGE egress context. The caller is responsible for
1947 * ensuring only one context operation occurs at a time.
1948 */
1949int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable)
1950{
1951 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1952 return -EBUSY;
1953
1954 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
1955 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
1956 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
1957 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
1958 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
1959 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
1960 V_CONTEXT_CMD_OPCODE(1) | F_EGRESS | V_CONTEXT(id));
1961 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
1962 0, 5, 1);
1963}
1964
1965/**
1966 * t3_sge_disable_fl - disable an SGE free-buffer list
1967 * @adapter: the adapter
1968 * @id: the free list context id
1969 *
1970 * Disable an SGE free-buffer list. The caller is responsible for
1971 * ensuring only one context operation occurs at a time.
1972 */
1973int t3_sge_disable_fl(struct adapter *adapter, unsigned int id)
1974{
1975 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1976 return -EBUSY;
1977
1978 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
1979 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
1980 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
1981 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
1982 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
1983 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
1984 V_CONTEXT_CMD_OPCODE(1) | F_FREELIST | V_CONTEXT(id));
1985 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
1986 0, 5, 1);
1987}
1988
1989/**
1990 * t3_sge_disable_rspcntxt - disable an SGE response queue
1991 * @adapter: the adapter
1992 * @id: the response queue context id
1993 *
1994 * Disable an SGE response queue. The caller is responsible for
1995 * ensuring only one context operation occurs at a time.
1996 */
1997int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id)
1998{
1999 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2000 return -EBUSY;
2001
2002 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2003 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2004 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2005 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2006 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2007 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2008 V_CONTEXT_CMD_OPCODE(1) | F_RESPONSEQ | V_CONTEXT(id));
2009 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2010 0, 5, 1);
2011}
2012
2013/**
2014 * t3_sge_disable_cqcntxt - disable an SGE completion queue
2015 * @adapter: the adapter
2016 * @id: the completion queue context id
2017 *
2018 * Disable an SGE completion queue. The caller is responsible for
2019 * ensuring only one context operation occurs at a time.
2020 */
2021int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id)
2022{
2023 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2024 return -EBUSY;
2025
2026 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2027 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2028 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2029 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2030 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2031 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2032 V_CONTEXT_CMD_OPCODE(1) | F_CQ | V_CONTEXT(id));
2033 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2034 0, 5, 1);
2035}
2036
2037/**
2038 * t3_sge_cqcntxt_op - perform an operation on a completion queue context
2039 * @adapter: the adapter
2040 * @id: the context id
2041 * @op: the operation to perform
2042 *
2043 * Perform the selected operation on an SGE completion queue context.
2044 * The caller is responsible for ensuring only one context operation
2045 * occurs at a time.
2046 */
2047int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
2048 unsigned int credits)
2049{
2050 u32 val;
2051
2052 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2053 return -EBUSY;
2054
2055 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2056 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2057 V_CONTEXT(id) | F_CQ);
2058 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2059 0, 5, 1, &val))
2060 return -EIO;
2061
2062 if (op >= 2 && op < 7) {
2063 if (adapter->params.rev > 0)
2064 return G_CQ_INDEX(val);
2065
2066 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2067 V_CONTEXT_CMD_OPCODE(0) | F_CQ | V_CONTEXT(id));
2068 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD,
2069 F_CONTEXT_CMD_BUSY, 0, 5, 1))
2070 return -EIO;
2071 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2072 }
2073 return 0;
2074}
2075
2076/**
2077 * t3_sge_read_context - read an SGE context
2078 * @type: the context type
2079 * @adapter: the adapter
2080 * @id: the context id
2081 * @data: holds the retrieved context
2082 *
2083 * Read an SGE egress context. The caller is responsible for ensuring
2084 * only one context operation occurs at a time.
2085 */
2086static int t3_sge_read_context(unsigned int type, struct adapter *adapter,
2087 unsigned int id, u32 data[4])
2088{
2089 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2090 return -EBUSY;
2091
2092 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2093 V_CONTEXT_CMD_OPCODE(0) | type | V_CONTEXT(id));
2094 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0,
2095 5, 1))
2096 return -EIO;
2097 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
2098 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
2099 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2);
2100 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3);
2101 return 0;
2102}
2103
2104/**
2105 * t3_sge_read_ecntxt - read an SGE egress context
2106 * @adapter: the adapter
2107 * @id: the context id
2108 * @data: holds the retrieved context
2109 *
2110 * Read an SGE egress context. The caller is responsible for ensuring
2111 * only one context operation occurs at a time.
2112 */
2113int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4])
2114{
2115 if (id >= 65536)
2116 return -EINVAL;
2117 return t3_sge_read_context(F_EGRESS, adapter, id, data);
2118}
2119
2120/**
2121 * t3_sge_read_cq - read an SGE CQ context
2122 * @adapter: the adapter
2123 * @id: the context id
2124 * @data: holds the retrieved context
2125 *
2126 * Read an SGE CQ context. The caller is responsible for ensuring
2127 * only one context operation occurs at a time.
2128 */
2129int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4])
2130{
2131 if (id >= 65536)
2132 return -EINVAL;
2133 return t3_sge_read_context(F_CQ, adapter, id, data);
2134}
2135
2136/**
2137 * t3_sge_read_fl - read an SGE free-list context
2138 * @adapter: the adapter
2139 * @id: the context id
2140 * @data: holds the retrieved context
2141 *
2142 * Read an SGE free-list context. The caller is responsible for ensuring
2143 * only one context operation occurs at a time.
2144 */
2145int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4])
2146{
2147 if (id >= SGE_QSETS * 2)
2148 return -EINVAL;
2149 return t3_sge_read_context(F_FREELIST, adapter, id, data);
2150}
2151
2152/**
2153 * t3_sge_read_rspq - read an SGE response queue context
2154 * @adapter: the adapter
2155 * @id: the context id
2156 * @data: holds the retrieved context
2157 *
2158 * Read an SGE response queue context. The caller is responsible for
2159 * ensuring only one context operation occurs at a time.
2160 */
2161int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4])
2162{
2163 if (id >= SGE_QSETS)
2164 return -EINVAL;
2165 return t3_sge_read_context(F_RESPONSEQ, adapter, id, data);
2166}
2167
2168/**
2169 * t3_config_rss - configure Rx packet steering
2170 * @adapter: the adapter
2171 * @rss_config: RSS settings (written to TP_RSS_CONFIG)
2172 * @cpus: values for the CPU lookup table (0xff terminated)
2173 * @rspq: values for the response queue lookup table (0xffff terminated)
2174 *
2175 * Programs the receive packet steering logic. @cpus and @rspq provide
2176 * the values for the CPU and response queue lookup tables. If they
2177 * provide fewer values than the size of the tables the supplied values
2178 * are used repeatedly until the tables are fully populated.
2179 */
2180void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
2181 const u8 * cpus, const u16 *rspq)
2182{
2183 int i, j, cpu_idx = 0, q_idx = 0;
2184
2185 if (cpus)
2186 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2187 u32 val = i << 16;
2188
2189 for (j = 0; j < 2; ++j) {
2190 val |= (cpus[cpu_idx++] & 0x3f) << (8 * j);
2191 if (cpus[cpu_idx] == 0xff)
2192 cpu_idx = 0;
2193 }
2194 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2195 }
2196
2197 if (rspq)
2198 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2199 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2200 (i << 16) | rspq[q_idx++]);
2201 if (rspq[q_idx] == 0xffff)
2202 q_idx = 0;
2203 }
2204
2205 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2206}
2207
2208/**
2209 * t3_read_rss - read the contents of the RSS tables
2210 * @adapter: the adapter
2211 * @lkup: holds the contents of the RSS lookup table
2212 * @map: holds the contents of the RSS map table
2213 *
2214 * Reads the contents of the receive packet steering tables.
2215 */
2216int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map)
2217{
2218 int i;
2219 u32 val;
2220
2221 if (lkup)
2222 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2223 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE,
2224 0xffff0000 | i);
2225 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE);
2226 if (!(val & 0x80000000))
2227 return -EAGAIN;
2228 *lkup++ = val;
2229 *lkup++ = (val >> 8);
2230 }
2231
2232 if (map)
2233 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2234 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2235 0xffff0000 | i);
2236 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE);
2237 if (!(val & 0x80000000))
2238 return -EAGAIN;
2239 *map++ = val;
2240 }
2241 return 0;
2242}
2243
2244/**
2245 * t3_tp_set_offload_mode - put TP in NIC/offload mode
2246 * @adap: the adapter
2247 * @enable: 1 to select offload mode, 0 for regular NIC
2248 *
2249 * Switches TP to NIC/offload mode.
2250 */
2251void t3_tp_set_offload_mode(struct adapter *adap, int enable)
2252{
2253 if (is_offload(adap) || !enable)
2254 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2255 V_NICMODE(!enable));
2256}
2257
2258/**
2259 * pm_num_pages - calculate the number of pages of the payload memory
2260 * @mem_size: the size of the payload memory
2261 * @pg_size: the size of each payload memory page
2262 *
2263 * Calculate the number of pages, each of the given size, that fit in a
2264 * memory of the specified size, respecting the HW requirement that the
2265 * number of pages must be a multiple of 24.
2266 */
2267static inline unsigned int pm_num_pages(unsigned int mem_size,
2268 unsigned int pg_size)
2269{
2270 unsigned int n = mem_size / pg_size;
2271
2272 return n - n % 24;
2273}
2274
2275#define mem_region(adap, start, size, reg) \
2276 t3_write_reg((adap), A_ ## reg, (start)); \
2277 start += size
2278
2279/*
2280 * partition_mem - partition memory and configure TP memory settings
2281 * @adap: the adapter
2282 * @p: the TP parameters
2283 *
2284 * Partitions context and payload memory and configures TP's memory
2285 * registers.
2286 */
2287static void partition_mem(struct adapter *adap, const struct tp_params *p)
2288{
2289 unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5);
2290 unsigned int timers = 0, timers_shift = 22;
2291
2292 if (adap->params.rev > 0) {
2293 if (tids <= 16 * 1024) {
2294 timers = 1;
2295 timers_shift = 16;
2296 } else if (tids <= 64 * 1024) {
2297 timers = 2;
2298 timers_shift = 18;
2299 } else if (tids <= 256 * 1024) {
2300 timers = 3;
2301 timers_shift = 20;
2302 }
2303 }
2304
2305 t3_write_reg(adap, A_TP_PMM_SIZE,
2306 p->chan_rx_size | (p->chan_tx_size >> 16));
2307
2308 t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
2309 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
2310 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
2311 t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
2312 V_TXDATAACKIDX(fls(p->tx_pg_size) - 12));
2313
2314 t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
2315 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
2316 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
2317
2318 pstructs = p->rx_num_pgs + p->tx_num_pgs;
2319 /* Add a bit of headroom and make multiple of 24 */
2320 pstructs += 48;
2321 pstructs -= pstructs % 24;
2322 t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
2323
2324 m = tids * TCB_SIZE;
2325 mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR);
2326 mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR);
2327 t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
2328 m += ((p->ntimer_qs - 1) << timers_shift) + (1 << 22);
2329 mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE);
2330 mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE);
2331 mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE);
2332 mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE);
2333
2334 m = (m + 4095) & ~0xfff;
2335 t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
2336 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
2337
2338 tids = (p->cm_size - m - (3 << 20)) / 3072 - 32;
2339 m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
2340 adap->params.mc5.nfilters - adap->params.mc5.nroutes;
2341 if (tids < m)
2342 adap->params.mc5.nservers += m - tids;
2343}
2344
2345static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr,
2346 u32 val)
2347{
2348 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2349 t3_write_reg(adap, A_TP_PIO_DATA, val);
2350}
2351
2352static void tp_config(struct adapter *adap, const struct tp_params *p)
2353{
4d22de3e
DLR		 2354 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2355 F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD |
2356 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2357 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2358 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2359 V_TIMESTAMPSMODE(1) | V_SACKMODE(1) | V_SACKRX(1));
2360 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2361 V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
2362 V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
2363 F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
2364 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_IPV6ENABLE | F_NICMODE,
2365 F_IPV6ENABLE | F_NICMODE);
2366 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2367 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2368 t3_set_reg_field(adap, A_TP_PARA_REG6,
2369 adap->params.rev > 0 ? F_ENABLEESND : F_T3A_ENABLEESND,
2370 0);
2371
3b1d307b
DLR		 2372 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2373 F_ENABLEEPCMDAFULL | F_ENABLEOCSPIFULL,
2374 F_TXDEFERENABLE | F_HEARBEATDACK | F_TXCONGESTIONMODE |
2375 F_RXCONGESTIONMODE);
2376 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
4d22de3e
DLR		 2377
2378 if (adap->params.rev > 0) {
2379 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2380 t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,
2381 F_TXPACEAUTO);
2382 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2383 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT);
2384 } else
2385 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2386
2387 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0x12121212);
2388 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0x12121212);
2389 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0x1212);
2390}
2391
2392/* Desired TP timer resolution in usec */
2393#define TP_TMR_RES 50
2394
2395/* TCP timer values in ms */
2396#define TP_DACK_TIMER 50
2397#define TP_RTO_MIN 250
2398
2399/**
2400 * tp_set_timers - set TP timing parameters
2401 * @adap: the adapter to set
2402 * @core_clk: the core clock frequency in Hz
2403 *
2404 * Set TP's timing parameters, such as the various timer resolutions and
2405 * the TCP timer values.
2406 */
2407static void tp_set_timers(struct adapter *adap, unsigned int core_clk)
2408{
2409 unsigned int tre = fls(core_clk / (1000000 / TP_TMR_RES)) - 1;
2410 unsigned int dack_re = fls(core_clk / 5000) - 1; /* 200us */
2411 unsigned int tstamp_re = fls(core_clk / 1000); /* 1ms, at least */
2412 unsigned int tps = core_clk >> tre;
2413
2414 t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
2415 V_DELAYEDACKRESOLUTION(dack_re) |
2416 V_TIMESTAMPRESOLUTION(tstamp_re));
2417 t3_write_reg(adap, A_TP_DACK_TIMER,
2418 (core_clk >> dack_re) / (1000 / TP_DACK_TIMER));
2419 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
2420 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
2421 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
2422 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
2423 t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
2424 V_RXTSHIFTMAXR1(4) | V_RXTSHIFTMAXR2(15) |
2425 V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) |
2426 V_KEEPALIVEMAX(9));
2427
2428#define SECONDS * tps
2429
2430 t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS);
2431 t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
2432 t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
2433 t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
2434 t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
2435 t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
2436 t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
2437 t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
2438 t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
2439
2440#undef SECONDS
2441}
2442
2443/**
2444 * t3_tp_set_coalescing_size - set receive coalescing size
2445 * @adap: the adapter
2446 * @size: the receive coalescing size
2447 * @psh: whether a set PSH bit should deliver coalesced data
2448 *
2449 * Set the receive coalescing size and PSH bit handling.
2450 */
2451int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh)
2452{
2453 u32 val;
2454
2455 if (size > MAX_RX_COALESCING_LEN)
2456 return -EINVAL;
2457
2458 val = t3_read_reg(adap, A_TP_PARA_REG3);
2459 val &= ~(F_RXCOALESCEENABLE | F_RXCOALESCEPSHEN);
2460
2461 if (size) {
2462 val |= F_RXCOALESCEENABLE;
2463 if (psh)
2464 val |= F_RXCOALESCEPSHEN;
2465 t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
2466 V_MAXRXDATA(MAX_RX_COALESCING_LEN));
2467 }
2468 t3_write_reg(adap, A_TP_PARA_REG3, val);
2469 return 0;
2470}
2471
2472/**
2473 * t3_tp_set_max_rxsize - set the max receive size
2474 * @adap: the adapter
2475 * @size: the max receive size
2476 *
2477 * Set TP's max receive size. This is the limit that applies when
2478 * receive coalescing is disabled.
2479 */
2480void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size)
2481{
2482 t3_write_reg(adap, A_TP_PARA_REG7,
2483 V_PMMAXXFERLEN0(size) | V_PMMAXXFERLEN1(size));
2484}
2485
2486static void __devinit init_mtus(unsigned short mtus[])
2487{
2488 /*
2489 * See draft-mathis-plpmtud-00.txt for the values. The min is 88 so
2490 * it can accomodate max size TCP/IP headers when SACK and timestamps
2491 * are enabled and still have at least 8 bytes of payload.
2492 */
2493 mtus[0] = 88;
2494 mtus[1] = 256;
2495 mtus[2] = 512;
2496 mtus[3] = 576;
2497 mtus[4] = 808;
2498 mtus[5] = 1024;
2499 mtus[6] = 1280;
2500 mtus[7] = 1492;
2501 mtus[8] = 1500;
2502 mtus[9] = 2002;
2503 mtus[10] = 2048;
2504 mtus[11] = 4096;
2505 mtus[12] = 4352;
2506 mtus[13] = 8192;
2507 mtus[14] = 9000;
2508 mtus[15] = 9600;
2509}
2510
2511/*
2512 * Initial congestion control parameters.
2513 */
2514static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b)
2515{
2516 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2517 a[9] = 2;
2518 a[10] = 3;
2519 a[11] = 4;
2520 a[12] = 5;
2521 a[13] = 6;
2522 a[14] = 7;
2523 a[15] = 8;
2524 a[16] = 9;
2525 a[17] = 10;
2526 a[18] = 14;
2527 a[19] = 17;
2528 a[20] = 21;
2529 a[21] = 25;
2530 a[22] = 30;
2531 a[23] = 35;
2532 a[24] = 45;
2533 a[25] = 60;
2534 a[26] = 80;
2535 a[27] = 100;
2536 a[28] = 200;
2537 a[29] = 300;
2538 a[30] = 400;
2539 a[31] = 500;
2540
2541 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2542 b[9] = b[10] = 1;
2543 b[11] = b[12] = 2;
2544 b[13] = b[14] = b[15] = b[16] = 3;
2545 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2546 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2547 b[28] = b[29] = 6;
2548 b[30] = b[31] = 7;
2549}
2550
2551/* The minimum additive increment value for the congestion control table */
2552#define CC_MIN_INCR 2U
2553
2554/**
2555 * t3_load_mtus - write the MTU and congestion control HW tables
2556 * @adap: the adapter
2557 * @mtus: the unrestricted values for the MTU table
2558 * @alphs: the values for the congestion control alpha parameter
2559 * @beta: the values for the congestion control beta parameter
2560 * @mtu_cap: the maximum permitted effective MTU
2561 *
2562 * Write the MTU table with the supplied MTUs capping each at &mtu_cap.
2563 * Update the high-speed congestion control table with the supplied alpha,
2564 * beta, and MTUs.
2565 */
2566void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
2567 unsigned short alpha[NCCTRL_WIN],
2568 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap)
2569{
2570 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2571 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2572 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2573 28672, 40960, 57344, 81920, 114688, 163840, 229376
2574 };
2575
2576 unsigned int i, w;
2577
2578 for (i = 0; i < NMTUS; ++i) {
2579 unsigned int mtu = min(mtus[i], mtu_cap);
2580 unsigned int log2 = fls(mtu);
2581
2582 if (!(mtu & ((1 << log2) >> 2))) /* round */
2583 log2--;
2584 t3_write_reg(adap, A_TP_MTU_TABLE,
2585 (i << 24) | (log2 << 16) | mtu);
2586
2587 for (w = 0; w < NCCTRL_WIN; ++w) {
2588 unsigned int inc;
2589
2590 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2591 CC_MIN_INCR);
2592
2593 t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
2594 (w << 16) | (beta[w] << 13) | inc);
2595 }
2596 }
2597}
2598
2599/**
2600 * t3_read_hw_mtus - returns the values in the HW MTU table
2601 * @adap: the adapter
2602 * @mtus: where to store the HW MTU values
2603 *
2604 * Reads the HW MTU table.
2605 */
2606void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS])
2607{
2608 int i;
2609
2610 for (i = 0; i < NMTUS; ++i) {
2611 unsigned int val;
2612
2613 t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i);
2614 val = t3_read_reg(adap, A_TP_MTU_TABLE);
2615 mtus[i] = val & 0x3fff;
2616 }
2617}
2618
2619/**
2620 * t3_get_cong_cntl_tab - reads the congestion control table
2621 * @adap: the adapter
2622 * @incr: where to store the alpha values
2623 *
2624 * Reads the additive increments programmed into the HW congestion
2625 * control table.
2626 */
2627void t3_get_cong_cntl_tab(struct adapter *adap,
2628 unsigned short incr[NMTUS][NCCTRL_WIN])
2629{
2630 unsigned int mtu, w;
2631
2632 for (mtu = 0; mtu < NMTUS; ++mtu)
2633 for (w = 0; w < NCCTRL_WIN; ++w) {
2634 t3_write_reg(adap, A_TP_CCTRL_TABLE,
2635 0xffff0000 | (mtu << 5) | w);
2636 incr[mtu][w] = t3_read_reg(adap, A_TP_CCTRL_TABLE) &
2637 0x1fff;
2638 }
2639}
2640
2641/**
2642 * t3_tp_get_mib_stats - read TP's MIB counters
2643 * @adap: the adapter
2644 * @tps: holds the returned counter values
2645 *
2646 * Returns the values of TP's MIB counters.
2647 */
2648void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps)
2649{
2650 t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *) tps,
2651 sizeof(*tps) / sizeof(u32), 0);
2652}
2653
2654#define ulp_region(adap, name, start, len) \
2655 t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
2656 t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
2657 (start) + (len) - 1); \
2658 start += len
2659
2660#define ulptx_region(adap, name, start, len) \
2661 t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
2662 t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
2663 (start) + (len) - 1)
2664
2665static void ulp_config(struct adapter *adap, const struct tp_params *p)
2666{
2667 unsigned int m = p->chan_rx_size;
2668
2669 ulp_region(adap, ISCSI, m, p->chan_rx_size / 8);
2670 ulp_region(adap, TDDP, m, p->chan_rx_size / 8);
2671 ulptx_region(adap, TPT, m, p->chan_rx_size / 4);
2672 ulp_region(adap, STAG, m, p->chan_rx_size / 4);
2673 ulp_region(adap, RQ, m, p->chan_rx_size / 4);
2674 ulptx_region(adap, PBL, m, p->chan_rx_size / 4);
2675 ulp_region(adap, PBL, m, p->chan_rx_size / 4);
2676 t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
2677}
2678
2679void t3_config_trace_filter(struct adapter *adapter,
2680 const struct trace_params *tp, int filter_index,
2681 int invert, int enable)
2682{
2683 u32 addr, key[4], mask[4];
2684
2685 key[0] = tp->sport | (tp->sip << 16);
2686 key[1] = (tp->sip >> 16) | (tp->dport << 16);
2687 key[2] = tp->dip;
2688 key[3] = tp->proto | (tp->vlan << 8) | (tp->intf << 20);
2689
2690 mask[0] = tp->sport_mask | (tp->sip_mask << 16);
2691 mask[1] = (tp->sip_mask >> 16) | (tp->dport_mask << 16);
2692 mask[2] = tp->dip_mask;
2693 mask[3] = tp->proto_mask | (tp->vlan_mask << 8) | (tp->intf_mask << 20);
2694
2695 if (invert)
2696 key[3] |= (1 << 29);
2697 if (enable)
2698 key[3] |= (1 << 28);
2699
2700 addr = filter_index ? A_TP_RX_TRC_KEY0 : A_TP_TX_TRC_KEY0;
2701 tp_wr_indirect(adapter, addr++, key[0]);
2702 tp_wr_indirect(adapter, addr++, mask[0]);
2703 tp_wr_indirect(adapter, addr++, key[1]);
2704 tp_wr_indirect(adapter, addr++, mask[1]);
2705 tp_wr_indirect(adapter, addr++, key[2]);
2706 tp_wr_indirect(adapter, addr++, mask[2]);
2707 tp_wr_indirect(adapter, addr++, key[3]);
2708 tp_wr_indirect(adapter, addr, mask[3]);
2709 t3_read_reg(adapter, A_TP_PIO_DATA);
2710}
2711
2712/**
2713 * t3_config_sched - configure a HW traffic scheduler
2714 * @adap: the adapter
2715 * @kbps: target rate in Kbps
2716 * @sched: the scheduler index
2717 *
2718 * Configure a HW scheduler for the target rate
2719 */
2720int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched)
2721{
2722 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
2723 unsigned int clk = adap->params.vpd.cclk * 1000;
2724 unsigned int selected_cpt = 0, selected_bpt = 0;
2725
2726 if (kbps > 0) {
2727 kbps *= 125; /* -> bytes */
2728 for (cpt = 1; cpt <= 255; cpt++) {
2729 tps = clk / cpt;
2730 bpt = (kbps + tps / 2) / tps;
2731 if (bpt > 0 && bpt <= 255) {
2732 v = bpt * tps;
2733 delta = v >= kbps ? v - kbps : kbps - v;
2734 if (delta <= mindelta) {
2735 mindelta = delta;
2736 selected_cpt = cpt;
2737 selected_bpt = bpt;
2738 }
2739 } else if (selected_cpt)
2740 break;
2741 }
2742 if (!selected_cpt)
2743 return -EINVAL;
2744 }
2745 t3_write_reg(adap, A_TP_TM_PIO_ADDR,
2746 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
2747 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
2748 if (sched & 1)
2749 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
2750 else
2751 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
2752 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
2753 return 0;
2754}
2755
2756static int tp_init(struct adapter *adap, const struct tp_params *p)
2757{
2758 int busy = 0;
2759
2760 tp_config(adap, p);
2761 t3_set_vlan_accel(adap, 3, 0);
2762
2763 if (is_offload(adap)) {
2764 tp_set_timers(adap, adap->params.vpd.cclk * 1000);
2765 t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
2766 busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE,
2767 0, 1000, 5);
2768 if (busy)
2769 CH_ERR(adap, "TP initialization timed out\n");
2770 }
2771
2772 if (!busy)
2773 t3_write_reg(adap, A_TP_RESET, F_TPRESET);
2774 return busy;
2775}
2776
2777int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask)
2778{
2779 if (port_mask & ~((1 << adap->params.nports) - 1))
2780 return -EINVAL;
2781 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
2782 port_mask << S_PORT0ACTIVE);
2783 return 0;
2784}
2785
2786/*
2787 * Perform the bits of HW initialization that are dependent on the number
2788 * of available ports.
2789 */
2790static void init_hw_for_avail_ports(struct adapter *adap, int nports)
2791{
2792 int i;
2793
2794 if (nports == 1) {
2795 t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
2796 t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
2797 t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN |
2798 F_PORT0ACTIVE | F_ENFORCEPKT);
2799 t3_write_reg(adap, A_PM1_TX_CFG, 0xc000c000);
2800 } else {
2801 t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
2802 t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
2803 t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
2804 V_D1_WEIGHT(16) | V_D0_WEIGHT(16));
2805 t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
2806 F_TPRXPORTEN | F_PORT0ACTIVE | F_PORT1ACTIVE |
2807 F_ENFORCEPKT);
2808 t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
2809 t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
2810 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
2811 V_TX_MOD_QUEUE_REQ_MAP(0xaa));
2812 for (i = 0; i < 16; i++)
2813 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
2814 (i << 16) | 0x1010);
2815 }
2816}
2817
2818static int calibrate_xgm(struct adapter *adapter)
2819{
2820 if (uses_xaui(adapter)) {
2821 unsigned int v, i;
2822
2823 for (i = 0; i < 5; ++i) {
2824 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
2825 t3_read_reg(adapter, A_XGM_XAUI_IMP);
2826 msleep(1);
2827 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
2828 if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) {
2829 t3_write_reg(adapter, A_XGM_XAUI_IMP,
2830 V_XAUIIMP(G_CALIMP(v) >> 2));
2831 return 0;
2832 }
2833 }
2834 CH_ERR(adapter, "MAC calibration failed\n");
2835 return -1;
2836 } else {
2837 t3_write_reg(adapter, A_XGM_RGMII_IMP,
2838 V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3));
2839 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
2840 F_XGM_IMPSETUPDATE);
2841 }
2842 return 0;
2843}
2844
2845static void calibrate_xgm_t3b(struct adapter *adapter)
2846{
2847 if (!uses_xaui(adapter)) {
2848 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
2849 F_CALUPDATE | V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3));
2850 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
2851 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
2852 F_XGM_IMPSETUPDATE);
2853 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
2854 0);
2855 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
2856 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
2857 }
2858}
2859
2860struct mc7_timing_params {
2861 unsigned char ActToPreDly;
2862 unsigned char ActToRdWrDly;
2863 unsigned char PreCyc;
2864 unsigned char RefCyc[5];
2865 unsigned char BkCyc;
2866 unsigned char WrToRdDly;
2867 unsigned char RdToWrDly;
2868};
2869
2870/*
2871 * Write a value to a register and check that the write completed. These
2872 * writes normally complete in a cycle or two, so one read should suffice.
2873 * The very first read exists to flush the posted write to the device.
2874 */
2875static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val)
2876{
2877 t3_write_reg(adapter, addr, val);
2878 t3_read_reg(adapter, addr); /* flush */
2879 if (!(t3_read_reg(adapter, addr) & F_BUSY))
2880 return 0;
2881 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr);
2882 return -EIO;
2883}
2884
2885static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)
2886{
2887 static const unsigned int mc7_mode[] = {
2888 0x632, 0x642, 0x652, 0x432, 0x442
2889 };
2890 static const struct mc7_timing_params mc7_timings[] = {
2891 {12, 3, 4, {20, 28, 34, 52, 0}, 15, 6, 4},
2892 {12, 4, 5, {20, 28, 34, 52, 0}, 16, 7, 4},
2893 {12, 5, 6, {20, 28, 34, 52, 0}, 17, 8, 4},
2894 {9, 3, 4, {15, 21, 26, 39, 0}, 12, 6, 4},
2895 {9, 4, 5, {15, 21, 26, 39, 0}, 13, 7, 4}
2896 };
2897
2898 u32 val;
2899 unsigned int width, density, slow, attempts;
2900 struct adapter *adapter = mc7->adapter;
2901 const struct mc7_timing_params *p = &mc7_timings[mem_type];
2902
2903 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
2904 slow = val & F_SLOW;
2905 width = G_WIDTH(val);
2906 density = G_DEN(val);
2907
2908 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
2909 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
2910 msleep(1);
2911
2912 if (!slow) {
2913 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
2914 t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
2915 msleep(1);
2916 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
2917 (F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) {
2918 CH_ERR(adapter, "%s MC7 calibration timed out\n",
2919 mc7->name);
2920 goto out_fail;
2921 }
2922 }
2923
2924 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
2925 V_ACTTOPREDLY(p->ActToPreDly) |
2926 V_ACTTORDWRDLY(p->ActToRdWrDly) | V_PRECYC(p->PreCyc) |
2927 V_REFCYC(p->RefCyc[density]) | V_BKCYC(p->BkCyc) |
2928 V_WRTORDDLY(p->WrToRdDly) | V_RDTOWRDLY(p->RdToWrDly));
2929
2930 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
2931 val | F_CLKEN | F_TERM150);
2932 t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
2933
2934 if (!slow)
2935 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
2936 F_DLLENB);
2937 udelay(1);
2938
2939 val = slow ? 3 : 6;
2940 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
2941 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
2942 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
2943 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
2944 goto out_fail;
2945
2946 if (!slow) {
2947 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
2948 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);
2949 udelay(5);
2950 }
2951
2952 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
2953 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
2954 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
2955 wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
2956 mc7_mode[mem_type]) ||
2957 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
2958 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
2959 goto out_fail;
2960
2961 /* clock value is in KHz */
2962 mc7_clock = mc7_clock * 7812 + mc7_clock / 2; /* ns */
2963 mc7_clock /= 1000000; /* KHz->MHz, ns->us */
2964
2965 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
2966 F_PERREFEN | V_PREREFDIV(mc7_clock));
2967 t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
2968
2969 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);
2970 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
2971 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
2972 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
2973 (mc7->size << width) - 1);
2974 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
2975 t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
2976
2977 attempts = 50;
2978 do {
2979 msleep(250);
2980 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
2981 } while ((val & F_BUSY) && --attempts);
2982 if (val & F_BUSY) {
2983 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
2984 goto out_fail;
2985 }
2986
2987 /* Enable normal memory accesses. */
2988 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
2989 return 0;
2990
2991out_fail:
2992 return -1;
2993}
2994
2995static void config_pcie(struct adapter *adap)
2996{
2997 static const u16 ack_lat[4][6] = {
2998 {237, 416, 559, 1071, 2095, 4143},
2999 {128, 217, 289, 545, 1057, 2081},
3000 {73, 118, 154, 282, 538, 1050},
3001 {67, 107, 86, 150, 278, 534}
3002 };
3003 static const u16 rpl_tmr[4][6] = {
3004 {711, 1248, 1677, 3213, 6285, 12429},
3005 {384, 651, 867, 1635, 3171, 6243},
3006 {219, 354, 462, 846, 1614, 3150},
3007 {201, 321, 258, 450, 834, 1602}
3008 };
3009
3010 u16 val;
3011 unsigned int log2_width, pldsize;
3012 unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
3013
3014 pci_read_config_word(adap->pdev,
3015 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
3016 &val);
3017 pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
3018 pci_read_config_word(adap->pdev,
3019 adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
3020 &val);
3021
3022 fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
3023 fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
3024 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3025 log2_width = fls(adap->params.pci.width) - 1;
3026 acklat = ack_lat[log2_width][pldsize];
3027 if (val & 1) /* check LOsEnable */
3028 acklat += fst_trn_tx * 4;
3029 rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;
3030
3031 if (adap->params.rev == 0)
3032 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
3033 V_T3A_ACKLAT(M_T3A_ACKLAT),
3034 V_T3A_ACKLAT(acklat));
3035 else
3036 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3037 V_ACKLAT(acklat));
3038
3039 t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3040 V_REPLAYLMT(rpllmt));
3041
3042 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3043 t3_set_reg_field(adap, A_PCIE_CFG, F_PCIE_CLIDECEN, F_PCIE_CLIDECEN);
3044}
3045
3046/*
3047 * Initialize and configure T3 HW modules. This performs the
3048 * initialization steps that need to be done once after a card is reset.
3049 * MAC and PHY initialization is handled separarely whenever a port is enabled.
3050 *
3051 * fw_params are passed to FW and their value is platform dependent. Only the
3052 * top 8 bits are available for use, the rest must be 0.
3053 */
3054int t3_init_hw(struct adapter *adapter, u32 fw_params)
3055{
3056 int err = -EIO, attempts = 100;
3057 const struct vpd_params *vpd = &adapter->params.vpd;
3058
3059 if (adapter->params.rev > 0)
3060 calibrate_xgm_t3b(adapter);
3061 else if (calibrate_xgm(adapter))
3062 goto out_err;
3063
3064 if (vpd->mclk) {
3065 partition_mem(adapter, &adapter->params.tp);
3066
3067 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3068 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3069 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3070 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
3071 adapter->params.mc5.nfilters,
3072 adapter->params.mc5.nroutes))
3073 goto out_err;
3074 }
3075
3076 if (tp_init(adapter, &adapter->params.tp))
3077 goto out_err;
3078
3079 t3_tp_set_coalescing_size(adapter,
3080 min(adapter->params.sge.max_pkt_size,
3081 MAX_RX_COALESCING_LEN), 1);
3082 t3_tp_set_max_rxsize(adapter,
3083 min(adapter->params.sge.max_pkt_size, 16384U));
3084 ulp_config(adapter, &adapter->params.tp);
3085
3086 if (is_pcie(adapter))
3087 config_pcie(adapter);
3088 else
3089 t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN);
3090
3091 t3_write_reg(adapter, A_PM1_RX_CFG, 0xf000f000);
3092 init_hw_for_avail_ports(adapter, adapter->params.nports);
3093 t3_sge_init(adapter, &adapter->params.sge);
3094
3095 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3096 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3097 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3098 t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3099
3100 do { /* wait for uP to initialize */
3101 msleep(20);
3102 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3103 if (!attempts)
3104 goto out_err;
3105
3106 err = 0;
3107out_err:
3108 return err;
3109}
3110
3111/**
3112 * get_pci_mode - determine a card's PCI mode
3113 * @adapter: the adapter
3114 * @p: where to store the PCI settings
3115 *
3116 * Determines a card's PCI mode and associated parameters, such as speed
3117 * and width.
3118 */
3119static void __devinit get_pci_mode(struct adapter *adapter,
3120 struct pci_params *p)
3121{
3122 static unsigned short speed_map[] = { 33, 66, 100, 133 };
3123 u32 pci_mode, pcie_cap;
3124
3125 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
3126 if (pcie_cap) {
3127 u16 val;
3128
3129 p->variant = PCI_VARIANT_PCIE;
3130 p->pcie_cap_addr = pcie_cap;
3131 pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
3132 &val);
3133 p->width = (val >> 4) & 0x3f;
3134 return;
3135 }
3136
3137 pci_mode = t3_read_reg(adapter, A_PCIX_MODE);
3138 p->speed = speed_map[G_PCLKRANGE(pci_mode)];
3139 p->width = (pci_mode & F_64BIT) ? 64 : 32;
3140 pci_mode = G_PCIXINITPAT(pci_mode);
3141 if (pci_mode == 0)
3142 p->variant = PCI_VARIANT_PCI;
3143 else if (pci_mode < 4)
3144 p->variant = PCI_VARIANT_PCIX_MODE1_PARITY;
3145 else if (pci_mode < 8)
3146 p->variant = PCI_VARIANT_PCIX_MODE1_ECC;
3147 else
3148 p->variant = PCI_VARIANT_PCIX_266_MODE2;
3149}
3150
3151/**
3152 * init_link_config - initialize a link's SW state
3153 * @lc: structure holding the link state
3154 * @ai: information about the current card
3155 *
3156 * Initializes the SW state maintained for each link, including the link's
3157 * capabilities and default speed/duplex/flow-control/autonegotiation
3158 * settings.
3159 */
3160static void __devinit init_link_config(struct link_config *lc,
3161 unsigned int caps)
3162{
3163 lc->supported = caps;
3164 lc->requested_speed = lc->speed = SPEED_INVALID;
3165 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
3166 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3167 if (lc->supported & SUPPORTED_Autoneg) {
3168 lc->advertising = lc->supported;
3169 lc->autoneg = AUTONEG_ENABLE;
3170 lc->requested_fc |= PAUSE_AUTONEG;
3171 } else {
3172 lc->advertising = 0;
3173 lc->autoneg = AUTONEG_DISABLE;
3174 }
3175}
3176
3177/**
3178 * mc7_calc_size - calculate MC7 memory size
3179 * @cfg: the MC7 configuration
3180 *
3181 * Calculates the size of an MC7 memory in bytes from the value of its
3182 * configuration register.
3183 */
3184static unsigned int __devinit mc7_calc_size(u32 cfg)
3185{
3186 unsigned int width = G_WIDTH(cfg);
3187 unsigned int banks = !!(cfg & F_BKS) + 1;
3188 unsigned int org = !!(cfg & F_ORG) + 1;
3189 unsigned int density = G_DEN(cfg);
3190 unsigned int MBs = ((256 << density) * banks) / (org << width);
3191
3192 return MBs << 20;
3193}
3194
3195static void __devinit mc7_prep(struct adapter *adapter, struct mc7 *mc7,
3196 unsigned int base_addr, const char *name)
3197{
3198 u32 cfg;
3199
3200 mc7->adapter = adapter;
3201 mc7->name = name;
3202 mc7->offset = base_addr - MC7_PMRX_BASE_ADDR;
3203 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3204 mc7->size = mc7_calc_size(cfg);
3205 mc7->width = G_WIDTH(cfg);
3206}
3207
3208void mac_prep(struct cmac *mac, struct adapter *adapter, int index)
3209{
3210 mac->adapter = adapter;
3211 mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index;
3212 mac->nucast = 1;
3213
3214 if (adapter->params.rev == 0 && uses_xaui(adapter)) {
3215 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
3216 is_10G(adapter) ? 0x2901c04 : 0x2301c04);
3217 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
3218 F_ENRGMII, 0);
3219 }
3220}
3221
3222void early_hw_init(struct adapter *adapter, const struct adapter_info *ai)
3223{
3224 u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2);
3225
3226 mi1_init(adapter, ai);
3227 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3228 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
3229 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3230 ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
3231
3232 if (adapter->params.rev == 0 || !uses_xaui(adapter))
3233 val |= F_ENRGMII;
3234
3235 /* Enable MAC clocks so we can access the registers */
3236 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3237 t3_read_reg(adapter, A_XGM_PORT_CFG);
3238
3239 val |= F_CLKDIVRESET_;
3240 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3241 t3_read_reg(adapter, A_XGM_PORT_CFG);
3242 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
3243 t3_read_reg(adapter, A_XGM_PORT_CFG);
3244}
3245
3246/*
e4d08359
DLR		 3247 * Reset the adapter.
3248 * Older PCIe cards lose their config space during reset, PCI-X
4d22de3e
DLR		 3249 * ones don't.
3250 */
3251int t3_reset_adapter(struct adapter *adapter)
3252{
e4d08359
DLR		 3253 int i, save_and_restore_pcie =
3254 adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
4d22de3e
DLR		 3255 uint16_t devid = 0;
3256
e4d08359 3257 if (save_and_restore_pcie)
4d22de3e
DLR		 3258 pci_save_state(adapter->pdev);
3259 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3260
3261 /*
3262 * Delay. Give Some time to device to reset fully.
3263 * XXX The delay time should be modified.
3264 */
3265 for (i = 0; i < 10; i++) {
3266 msleep(50);
3267 pci_read_config_word(adapter->pdev, 0x00, &devid);
3268 if (devid == 0x1425)
3269 break;
3270 }
3271
3272 if (devid != 0x1425)
3273 return -1;
3274
e4d08359 3275 if (save_and_restore_pcie)
4d22de3e
DLR		 3276 pci_restore_state(adapter->pdev);
3277 return 0;
3278}
3279
3280/*
3281 * Initialize adapter SW state for the various HW modules, set initial values
3282 * for some adapter tunables, take PHYs out of reset, and initialize the MDIO
3283 * interface.
3284 */
3285int __devinit t3_prep_adapter(struct adapter *adapter,
3286 const struct adapter_info *ai, int reset)
3287{
3288 int ret;
3289 unsigned int i, j = 0;
3290
3291 get_pci_mode(adapter, &adapter->params.pci);
3292
3293 adapter->params.info = ai;
3294 adapter->params.nports = ai->nports;
3295 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
3296 adapter->params.linkpoll_period = 0;
3297 adapter->params.stats_update_period = is_10G(adapter) ?
3298 MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10);
3299 adapter->params.pci.vpd_cap_addr =
3300 pci_find_capability(adapter->pdev, PCI_CAP_ID_VPD);
3301 ret = get_vpd_params(adapter, &adapter->params.vpd);
3302 if (ret < 0)
3303 return ret;
3304
3305 if (reset && t3_reset_adapter(adapter))
3306 return -1;
3307
3308 t3_sge_prep(adapter, &adapter->params.sge);
3309
3310 if (adapter->params.vpd.mclk) {
3311 struct tp_params *p = &adapter->params.tp;
3312
3313 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX");
3314 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX");
3315 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM");
3316
3317 p->nchan = ai->nports;
3318 p->pmrx_size = t3_mc7_size(&adapter->pmrx);
3319 p->pmtx_size = t3_mc7_size(&adapter->pmtx);
3320 p->cm_size = t3_mc7_size(&adapter->cm);
3321 p->chan_rx_size = p->pmrx_size / 2; /* only 1 Rx channel */
3322 p->chan_tx_size = p->pmtx_size / p->nchan;
3323 p->rx_pg_size = 64 * 1024;
3324 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024;
3325 p->rx_num_pgs = pm_num_pages(p->chan_rx_size, p->rx_pg_size);
3326 p->tx_num_pgs = pm_num_pages(p->chan_tx_size, p->tx_pg_size);
3327 p->ntimer_qs = p->cm_size >= (128 << 20) ||
3328 adapter->params.rev > 0 ? 12 : 6;
3329
3330 adapter->params.mc5.nservers = DEFAULT_NSERVERS;
3331 adapter->params.mc5.nfilters = adapter->params.rev > 0 ?
3332 DEFAULT_NFILTERS : 0;
3333 adapter->params.mc5.nroutes = 0;
3334 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT);
3335
3336 init_mtus(adapter->params.mtus);
3337 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3338 }
3339
3340 early_hw_init(adapter, ai);
3341
3342 for_each_port(adapter, i) {
3343 u8 hw_addr[6];
3344 struct port_info *p = adap2pinfo(adapter, i);
3345
3346 while (!adapter->params.vpd.port_type[j])
3347 ++j;
3348
3349 p->port_type = &port_types[adapter->params.vpd.port_type[j]];
3350 p->port_type->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3351 ai->mdio_ops);
3352 mac_prep(&p->mac, adapter, j);
3353 ++j;
3354
3355 /*
3356 * The VPD EEPROM stores the base Ethernet address for the
3357 * card. A port's address is derived from the base by adding
3358 * the port's index to the base's low octet.
3359 */
3360 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
3361 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
3362
3363 memcpy(adapter->port[i]->dev_addr, hw_addr,
3364 ETH_ALEN);
3365 memcpy(adapter->port[i]->perm_addr, hw_addr,
3366 ETH_ALEN);
3367 init_link_config(&p->link_config, p->port_type->caps);
3368 p->phy.ops->power_down(&p->phy, 1);
3369 if (!(p->port_type->caps & SUPPORTED_IRQ))
3370 adapter->params.linkpoll_period = 10;
3371 }
3372
3373 return 0;
3374}
3375
3376void t3_led_ready(struct adapter *adapter)
3377{
3378 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
3379 F_GPIO0_OUT_VAL);
3380}
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